1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/compiler_globals.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "gc/shared/barrierSet.hpp"
  32 #include "gc/shared/barrierSetAssembler.hpp"
  33 #include "gc/shared/collectedHeap.inline.hpp"
  34 #include "gc/shared/tlab_globals.hpp"
  35 #include "interpreter/bytecodeHistogram.hpp"
  36 #include "interpreter/interpreter.hpp"
  37 #include "memory/resourceArea.hpp"
  38 #include "memory/universe.hpp"
  39 #include "oops/accessDecorators.hpp"
  40 #include "oops/compressedOops.inline.hpp"
  41 #include "oops/klass.inline.hpp"
  42 #include "prims/methodHandles.hpp"
  43 #include "runtime/flags/flagSetting.hpp"
  44 #include "runtime/interfaceSupport.inline.hpp"
  45 #include "runtime/jniHandles.hpp"
  46 #include "runtime/objectMonitor.hpp"
  47 #include "runtime/os.hpp"
  48 #include "runtime/safepoint.hpp"
  49 #include "runtime/safepointMechanism.hpp"
  50 #include "runtime/sharedRuntime.hpp"
  51 #include "runtime/stubRoutines.hpp"
  52 #include "runtime/thread.hpp"
  53 #include "utilities/macros.hpp"
  54 #include "crc32c.h"
  55 
  56 #ifdef PRODUCT
  57 #define BLOCK_COMMENT(str) /* nothing */
  58 #define STOP(error) stop(error)
  59 #else
  60 #define BLOCK_COMMENT(str) block_comment(str)
  61 #define STOP(error) block_comment(error); stop(error)
  62 #endif
  63 
  64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  65 
  66 #ifdef ASSERT
  67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  68 #endif
  69 
  70 static Assembler::Condition reverse[] = {
  71     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  72     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  73     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  74     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  75     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  76     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  77     Assembler::above          /* belowEqual    = 0x6 */ ,
  78     Assembler::belowEqual     /* above         = 0x7 */ ,
  79     Assembler::positive       /* negative      = 0x8 */ ,
  80     Assembler::negative       /* positive      = 0x9 */ ,
  81     Assembler::noParity       /* parity        = 0xa */ ,
  82     Assembler::parity         /* noParity      = 0xb */ ,
  83     Assembler::greaterEqual   /* less          = 0xc */ ,
  84     Assembler::less           /* greaterEqual  = 0xd */ ,
  85     Assembler::greater        /* lessEqual     = 0xe */ ,
  86     Assembler::lessEqual      /* greater       = 0xf, */
  87 
  88 };
  89 
  90 
  91 // Implementation of MacroAssembler
  92 
  93 // First all the versions that have distinct versions depending on 32/64 bit
  94 // Unless the difference is trivial (1 line or so).
  95 
  96 #ifndef _LP64
  97 
  98 // 32bit versions
  99 
 100 Address MacroAssembler::as_Address(AddressLiteral adr) {
 101   return Address(adr.target(), adr.rspec());
 102 }
 103 
 104 Address MacroAssembler::as_Address(ArrayAddress adr) {
 105   return Address::make_array(adr);
 106 }
 107 
 108 void MacroAssembler::call_VM_leaf_base(address entry_point,
 109                                        int number_of_arguments) {
 110   call(RuntimeAddress(entry_point));
 111   increment(rsp, number_of_arguments * wordSize);
 112 }
 113 
 114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 115   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 116 }
 117 
 118 
 119 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 120   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 121 }
 122 
 123 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 124   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 125 }
 126 
 127 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 128   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 129 }
 130 
 131 void MacroAssembler::extend_sign(Register hi, Register lo) {
 132   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 133   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 134     cdql();
 135   } else {
 136     movl(hi, lo);
 137     sarl(hi, 31);
 138   }
 139 }
 140 
 141 void MacroAssembler::jC2(Register tmp, Label& L) {
 142   // set parity bit if FPU flag C2 is set (via rax)
 143   save_rax(tmp);
 144   fwait(); fnstsw_ax();
 145   sahf();
 146   restore_rax(tmp);
 147   // branch
 148   jcc(Assembler::parity, L);
 149 }
 150 
 151 void MacroAssembler::jnC2(Register tmp, Label& L) {
 152   // set parity bit if FPU flag C2 is set (via rax)
 153   save_rax(tmp);
 154   fwait(); fnstsw_ax();
 155   sahf();
 156   restore_rax(tmp);
 157   // branch
 158   jcc(Assembler::noParity, L);
 159 }
 160 
 161 // 32bit can do a case table jump in one instruction but we no longer allow the base
 162 // to be installed in the Address class
 163 void MacroAssembler::jump(ArrayAddress entry) {
 164   jmp(as_Address(entry));
 165 }
 166 
 167 // Note: y_lo will be destroyed
 168 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 169   // Long compare for Java (semantics as described in JVM spec.)
 170   Label high, low, done;
 171 
 172   cmpl(x_hi, y_hi);
 173   jcc(Assembler::less, low);
 174   jcc(Assembler::greater, high);
 175   // x_hi is the return register
 176   xorl(x_hi, x_hi);
 177   cmpl(x_lo, y_lo);
 178   jcc(Assembler::below, low);
 179   jcc(Assembler::equal, done);
 180 
 181   bind(high);
 182   xorl(x_hi, x_hi);
 183   increment(x_hi);
 184   jmp(done);
 185 
 186   bind(low);
 187   xorl(x_hi, x_hi);
 188   decrementl(x_hi);
 189 
 190   bind(done);
 191 }
 192 
 193 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 194     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 195 }
 196 
 197 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 198   // leal(dst, as_Address(adr));
 199   // see note in movl as to why we must use a move
 200   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 201 }
 202 
 203 void MacroAssembler::leave() {
 204   mov(rsp, rbp);
 205   pop(rbp);
 206 }
 207 
 208 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 209   // Multiplication of two Java long values stored on the stack
 210   // as illustrated below. Result is in rdx:rax.
 211   //
 212   // rsp ---> [  ??  ] \               \
 213   //            ....    | y_rsp_offset  |
 214   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 215   //          [ y_hi ]                  | (in bytes)
 216   //            ....                    |
 217   //          [ x_lo ]                 /
 218   //          [ x_hi ]
 219   //            ....
 220   //
 221   // Basic idea: lo(result) = lo(x_lo * y_lo)
 222   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 223   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 224   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 225   Label quick;
 226   // load x_hi, y_hi and check if quick
 227   // multiplication is possible
 228   movl(rbx, x_hi);
 229   movl(rcx, y_hi);
 230   movl(rax, rbx);
 231   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 232   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 233   // do full multiplication
 234   // 1st step
 235   mull(y_lo);                                    // x_hi * y_lo
 236   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 237   // 2nd step
 238   movl(rax, x_lo);
 239   mull(rcx);                                     // x_lo * y_hi
 240   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 241   // 3rd step
 242   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 243   movl(rax, x_lo);
 244   mull(y_lo);                                    // x_lo * y_lo
 245   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 246 }
 247 
 248 void MacroAssembler::lneg(Register hi, Register lo) {
 249   negl(lo);
 250   adcl(hi, 0);
 251   negl(hi);
 252 }
 253 
 254 void MacroAssembler::lshl(Register hi, Register lo) {
 255   // Java shift left long support (semantics as described in JVM spec., p.305)
 256   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 257   // shift value is in rcx !
 258   assert(hi != rcx, "must not use rcx");
 259   assert(lo != rcx, "must not use rcx");
 260   const Register s = rcx;                        // shift count
 261   const int      n = BitsPerWord;
 262   Label L;
 263   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 264   cmpl(s, n);                                    // if (s < n)
 265   jcc(Assembler::less, L);                       // else (s >= n)
 266   movl(hi, lo);                                  // x := x << n
 267   xorl(lo, lo);
 268   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 269   bind(L);                                       // s (mod n) < n
 270   shldl(hi, lo);                                 // x := x << s
 271   shll(lo);
 272 }
 273 
 274 
 275 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 276   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 277   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 278   assert(hi != rcx, "must not use rcx");
 279   assert(lo != rcx, "must not use rcx");
 280   const Register s = rcx;                        // shift count
 281   const int      n = BitsPerWord;
 282   Label L;
 283   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 284   cmpl(s, n);                                    // if (s < n)
 285   jcc(Assembler::less, L);                       // else (s >= n)
 286   movl(lo, hi);                                  // x := x >> n
 287   if (sign_extension) sarl(hi, 31);
 288   else                xorl(hi, hi);
 289   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 290   bind(L);                                       // s (mod n) < n
 291   shrdl(lo, hi);                                 // x := x >> s
 292   if (sign_extension) sarl(hi);
 293   else                shrl(hi);
 294 }
 295 
 296 void MacroAssembler::movoop(Register dst, jobject obj) {
 297   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 298 }
 299 
 300 void MacroAssembler::movoop(Address dst, jobject obj) {
 301   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 302 }
 303 
 304 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 305   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 306 }
 307 
 308 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 309   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 310 }
 311 
 312 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 313   // scratch register is not used,
 314   // it is defined to match parameters of 64-bit version of this method.
 315   if (src.is_lval()) {
 316     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 317   } else {
 318     movl(dst, as_Address(src));
 319   }
 320 }
 321 
 322 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 323   movl(as_Address(dst), src);
 324 }
 325 
 326 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 327   movl(dst, as_Address(src));
 328 }
 329 
 330 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 331 void MacroAssembler::movptr(Address dst, intptr_t src) {
 332   movl(dst, src);
 333 }
 334 
 335 void MacroAssembler::pushoop(jobject obj) {
 336   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 337 }
 338 
 339 void MacroAssembler::pushklass(Metadata* obj) {
 340   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 341 }
 342 
 343 void MacroAssembler::pushptr(AddressLiteral src) {
 344   if (src.is_lval()) {
 345     push_literal32((int32_t)src.target(), src.rspec());
 346   } else {
 347     pushl(as_Address(src));
 348   }
 349 }
 350 
 351 static void pass_arg0(MacroAssembler* masm, Register arg) {
 352   masm->push(arg);
 353 }
 354 
 355 static void pass_arg1(MacroAssembler* masm, Register arg) {
 356   masm->push(arg);
 357 }
 358 
 359 static void pass_arg2(MacroAssembler* masm, Register arg) {
 360   masm->push(arg);
 361 }
 362 
 363 static void pass_arg3(MacroAssembler* masm, Register arg) {
 364   masm->push(arg);
 365 }
 366 
 367 #ifndef PRODUCT
 368 extern "C" void findpc(intptr_t x);
 369 #endif
 370 
 371 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 372   // In order to get locks to work, we need to fake a in_VM state
 373   JavaThread* thread = JavaThread::current();
 374   JavaThreadState saved_state = thread->thread_state();
 375   thread->set_thread_state(_thread_in_vm);
 376   if (ShowMessageBoxOnError) {
 377     JavaThread* thread = JavaThread::current();
 378     JavaThreadState saved_state = thread->thread_state();
 379     thread->set_thread_state(_thread_in_vm);
 380     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 381       ttyLocker ttyl;
 382       BytecodeCounter::print();
 383     }
 384     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 385     // This is the value of eip which points to where verify_oop will return.
 386     if (os::message_box(msg, "Execution stopped, print registers?")) {
 387       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 388       BREAKPOINT;
 389     }
 390   }
 391   fatal("DEBUG MESSAGE: %s", msg);
 392 }
 393 
 394 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 395   ttyLocker ttyl;
 396   FlagSetting fs(Debugging, true);
 397   tty->print_cr("eip = 0x%08x", eip);
 398 #ifndef PRODUCT
 399   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 400     tty->cr();
 401     findpc(eip);
 402     tty->cr();
 403   }
 404 #endif
 405 #define PRINT_REG(rax) \
 406   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 407   PRINT_REG(rax);
 408   PRINT_REG(rbx);
 409   PRINT_REG(rcx);
 410   PRINT_REG(rdx);
 411   PRINT_REG(rdi);
 412   PRINT_REG(rsi);
 413   PRINT_REG(rbp);
 414   PRINT_REG(rsp);
 415 #undef PRINT_REG
 416   // Print some words near top of staack.
 417   int* dump_sp = (int*) rsp;
 418   for (int col1 = 0; col1 < 8; col1++) {
 419     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 420     os::print_location(tty, *dump_sp++);
 421   }
 422   for (int row = 0; row < 16; row++) {
 423     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 424     for (int col = 0; col < 8; col++) {
 425       tty->print(" 0x%08x", *dump_sp++);
 426     }
 427     tty->cr();
 428   }
 429   // Print some instructions around pc:
 430   Disassembler::decode((address)eip-64, (address)eip);
 431   tty->print_cr("--------");
 432   Disassembler::decode((address)eip, (address)eip+32);
 433 }
 434 
 435 void MacroAssembler::stop(const char* msg) {
 436   ExternalAddress message((address)msg);
 437   // push address of message
 438   pushptr(message.addr());
 439   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 440   pusha();                                            // push registers
 441   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 442   hlt();
 443 }
 444 
 445 void MacroAssembler::warn(const char* msg) {
 446   push_CPU_state();
 447 
 448   ExternalAddress message((address) msg);
 449   // push address of message
 450   pushptr(message.addr());
 451 
 452   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 453   addl(rsp, wordSize);       // discard argument
 454   pop_CPU_state();
 455 }
 456 
 457 void MacroAssembler::print_state() {
 458   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 459   pusha();                                            // push registers
 460 
 461   push_CPU_state();
 462   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 463   pop_CPU_state();
 464 
 465   popa();
 466   addl(rsp, wordSize);
 467 }
 468 
 469 #else // _LP64
 470 
 471 // 64 bit versions
 472 
 473 Address MacroAssembler::as_Address(AddressLiteral adr) {
 474   // amd64 always does this as a pc-rel
 475   // we can be absolute or disp based on the instruction type
 476   // jmp/call are displacements others are absolute
 477   assert(!adr.is_lval(), "must be rval");
 478   assert(reachable(adr), "must be");
 479   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 480 
 481 }
 482 
 483 Address MacroAssembler::as_Address(ArrayAddress adr) {
 484   AddressLiteral base = adr.base();
 485   lea(rscratch1, base);
 486   Address index = adr.index();
 487   assert(index._disp == 0, "must not have disp"); // maybe it can?
 488   Address array(rscratch1, index._index, index._scale, index._disp);
 489   return array;
 490 }
 491 
 492 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 493   Label L, E;
 494 
 495 #ifdef _WIN64
 496   // Windows always allocates space for it's register args
 497   assert(num_args <= 4, "only register arguments supported");
 498   subq(rsp,  frame::arg_reg_save_area_bytes);
 499 #endif
 500 
 501   // Align stack if necessary
 502   testl(rsp, 15);
 503   jcc(Assembler::zero, L);
 504 
 505   subq(rsp, 8);
 506   {
 507     call(RuntimeAddress(entry_point));
 508   }
 509   addq(rsp, 8);
 510   jmp(E);
 511 
 512   bind(L);
 513   {
 514     call(RuntimeAddress(entry_point));
 515   }
 516 
 517   bind(E);
 518 
 519 #ifdef _WIN64
 520   // restore stack pointer
 521   addq(rsp, frame::arg_reg_save_area_bytes);
 522 #endif
 523 
 524 }
 525 
 526 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 527   assert(!src2.is_lval(), "should use cmpptr");
 528 
 529   if (reachable(src2)) {
 530     cmpq(src1, as_Address(src2));
 531   } else {
 532     lea(rscratch1, src2);
 533     Assembler::cmpq(src1, Address(rscratch1, 0));
 534   }
 535 }
 536 
 537 int MacroAssembler::corrected_idivq(Register reg) {
 538   // Full implementation of Java ldiv and lrem; checks for special
 539   // case as described in JVM spec., p.243 & p.271.  The function
 540   // returns the (pc) offset of the idivl instruction - may be needed
 541   // for implicit exceptions.
 542   //
 543   //         normal case                           special case
 544   //
 545   // input : rax: dividend                         min_long
 546   //         reg: divisor   (may not be eax/edx)   -1
 547   //
 548   // output: rax: quotient  (= rax idiv reg)       min_long
 549   //         rdx: remainder (= rax irem reg)       0
 550   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 551   static const int64_t min_long = 0x8000000000000000;
 552   Label normal_case, special_case;
 553 
 554   // check for special case
 555   cmp64(rax, ExternalAddress((address) &min_long));
 556   jcc(Assembler::notEqual, normal_case);
 557   xorl(rdx, rdx); // prepare rdx for possible special case (where
 558                   // remainder = 0)
 559   cmpq(reg, -1);
 560   jcc(Assembler::equal, special_case);
 561 
 562   // handle normal case
 563   bind(normal_case);
 564   cdqq();
 565   int idivq_offset = offset();
 566   idivq(reg);
 567 
 568   // normal and special case exit
 569   bind(special_case);
 570 
 571   return idivq_offset;
 572 }
 573 
 574 void MacroAssembler::decrementq(Register reg, int value) {
 575   if (value == min_jint) { subq(reg, value); return; }
 576   if (value <  0) { incrementq(reg, -value); return; }
 577   if (value == 0) {                        ; return; }
 578   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 579   /* else */      { subq(reg, value)       ; return; }
 580 }
 581 
 582 void MacroAssembler::decrementq(Address dst, int value) {
 583   if (value == min_jint) { subq(dst, value); return; }
 584   if (value <  0) { incrementq(dst, -value); return; }
 585   if (value == 0) {                        ; return; }
 586   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 587   /* else */      { subq(dst, value)       ; return; }
 588 }
 589 
 590 void MacroAssembler::incrementq(AddressLiteral dst) {
 591   if (reachable(dst)) {
 592     incrementq(as_Address(dst));
 593   } else {
 594     lea(rscratch1, dst);
 595     incrementq(Address(rscratch1, 0));
 596   }
 597 }
 598 
 599 void MacroAssembler::incrementq(Register reg, int value) {
 600   if (value == min_jint) { addq(reg, value); return; }
 601   if (value <  0) { decrementq(reg, -value); return; }
 602   if (value == 0) {                        ; return; }
 603   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 604   /* else */      { addq(reg, value)       ; return; }
 605 }
 606 
 607 void MacroAssembler::incrementq(Address dst, int value) {
 608   if (value == min_jint) { addq(dst, value); return; }
 609   if (value <  0) { decrementq(dst, -value); return; }
 610   if (value == 0) {                        ; return; }
 611   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 612   /* else */      { addq(dst, value)       ; return; }
 613 }
 614 
 615 // 32bit can do a case table jump in one instruction but we no longer allow the base
 616 // to be installed in the Address class
 617 void MacroAssembler::jump(ArrayAddress entry) {
 618   lea(rscratch1, entry.base());
 619   Address dispatch = entry.index();
 620   assert(dispatch._base == noreg, "must be");
 621   dispatch._base = rscratch1;
 622   jmp(dispatch);
 623 }
 624 
 625 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 626   ShouldNotReachHere(); // 64bit doesn't use two regs
 627   cmpq(x_lo, y_lo);
 628 }
 629 
 630 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 631     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 632 }
 633 
 634 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 635   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 636   movptr(dst, rscratch1);
 637 }
 638 
 639 void MacroAssembler::leave() {
 640   // %%% is this really better? Why not on 32bit too?
 641   emit_int8((unsigned char)0xC9); // LEAVE
 642 }
 643 
 644 void MacroAssembler::lneg(Register hi, Register lo) {
 645   ShouldNotReachHere(); // 64bit doesn't use two regs
 646   negq(lo);
 647 }
 648 
 649 void MacroAssembler::movoop(Register dst, jobject obj) {
 650   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 651 }
 652 
 653 void MacroAssembler::movoop(Address dst, jobject obj) {
 654   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 655   movq(dst, rscratch1);
 656 }
 657 
 658 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 659   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 660 }
 661 
 662 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 663   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 664   movq(dst, rscratch1);
 665 }
 666 
 667 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 668   if (src.is_lval()) {
 669     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 670   } else {
 671     if (reachable(src)) {
 672       movq(dst, as_Address(src));
 673     } else {
 674       lea(scratch, src);
 675       movq(dst, Address(scratch, 0));
 676     }
 677   }
 678 }
 679 
 680 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 681   movq(as_Address(dst), src);
 682 }
 683 
 684 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 685   movq(dst, as_Address(src));
 686 }
 687 
 688 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 689 void MacroAssembler::movptr(Address dst, intptr_t src) {
 690   if (is_simm32(src)) {
 691     movptr(dst, checked_cast<int32_t>(src));
 692   } else {
 693     mov64(rscratch1, src);
 694     movq(dst, rscratch1);
 695   }
 696 }
 697 
 698 // These are mostly for initializing NULL
 699 void MacroAssembler::movptr(Address dst, int32_t src) {
 700   movslq(dst, src);
 701 }
 702 
 703 void MacroAssembler::movptr(Register dst, int32_t src) {
 704   mov64(dst, (intptr_t)src);
 705 }
 706 
 707 void MacroAssembler::pushoop(jobject obj) {
 708   movoop(rscratch1, obj);
 709   push(rscratch1);
 710 }
 711 
 712 void MacroAssembler::pushklass(Metadata* obj) {
 713   mov_metadata(rscratch1, obj);
 714   push(rscratch1);
 715 }
 716 
 717 void MacroAssembler::pushptr(AddressLiteral src) {
 718   lea(rscratch1, src);
 719   if (src.is_lval()) {
 720     push(rscratch1);
 721   } else {
 722     pushq(Address(rscratch1, 0));
 723   }
 724 }
 725 
 726 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 727   reset_last_Java_frame(r15_thread, clear_fp);
 728 }
 729 
 730 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 731                                          Register last_java_fp,
 732                                          address  last_java_pc) {
 733   vzeroupper();
 734   // determine last_java_sp register
 735   if (!last_java_sp->is_valid()) {
 736     last_java_sp = rsp;
 737   }
 738 
 739   // last_java_fp is optional
 740   if (last_java_fp->is_valid()) {
 741     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 742            last_java_fp);
 743   }
 744 
 745   // last_java_pc is optional
 746   if (last_java_pc != NULL) {
 747     Address java_pc(r15_thread,
 748                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 749     lea(rscratch1, InternalAddress(last_java_pc));
 750     movptr(java_pc, rscratch1);
 751   }
 752 
 753   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 754 }
 755 
 756 static void pass_arg0(MacroAssembler* masm, Register arg) {
 757   if (c_rarg0 != arg ) {
 758     masm->mov(c_rarg0, arg);
 759   }
 760 }
 761 
 762 static void pass_arg1(MacroAssembler* masm, Register arg) {
 763   if (c_rarg1 != arg ) {
 764     masm->mov(c_rarg1, arg);
 765   }
 766 }
 767 
 768 static void pass_arg2(MacroAssembler* masm, Register arg) {
 769   if (c_rarg2 != arg ) {
 770     masm->mov(c_rarg2, arg);
 771   }
 772 }
 773 
 774 static void pass_arg3(MacroAssembler* masm, Register arg) {
 775   if (c_rarg3 != arg ) {
 776     masm->mov(c_rarg3, arg);
 777   }
 778 }
 779 
 780 void MacroAssembler::stop(const char* msg) {
 781   if (ShowMessageBoxOnError) {
 782     address rip = pc();
 783     pusha(); // get regs on stack
 784     lea(c_rarg1, InternalAddress(rip));
 785     movq(c_rarg2, rsp); // pass pointer to regs array
 786   }
 787   lea(c_rarg0, ExternalAddress((address) msg));
 788   andq(rsp, -16); // align stack as required by ABI
 789   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 790   hlt();
 791 }
 792 
 793 void MacroAssembler::warn(const char* msg) {
 794   push(rbp);
 795   movq(rbp, rsp);
 796   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 797   push_CPU_state();   // keeps alignment at 16 bytes
 798   lea(c_rarg0, ExternalAddress((address) msg));
 799   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 800   call(rax);
 801   pop_CPU_state();
 802   mov(rsp, rbp);
 803   pop(rbp);
 804 }
 805 
 806 void MacroAssembler::print_state() {
 807   address rip = pc();
 808   pusha();            // get regs on stack
 809   push(rbp);
 810   movq(rbp, rsp);
 811   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 812   push_CPU_state();   // keeps alignment at 16 bytes
 813 
 814   lea(c_rarg0, InternalAddress(rip));
 815   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 816   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 817 
 818   pop_CPU_state();
 819   mov(rsp, rbp);
 820   pop(rbp);
 821   popa();
 822 }
 823 
 824 #ifndef PRODUCT
 825 extern "C" void findpc(intptr_t x);
 826 #endif
 827 
 828 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 829   // In order to get locks to work, we need to fake a in_VM state
 830   if (ShowMessageBoxOnError) {
 831     JavaThread* thread = JavaThread::current();
 832     JavaThreadState saved_state = thread->thread_state();
 833     thread->set_thread_state(_thread_in_vm);
 834 #ifndef PRODUCT
 835     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 836       ttyLocker ttyl;
 837       BytecodeCounter::print();
 838     }
 839 #endif
 840     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 841     // XXX correct this offset for amd64
 842     // This is the value of eip which points to where verify_oop will return.
 843     if (os::message_box(msg, "Execution stopped, print registers?")) {
 844       print_state64(pc, regs);
 845       BREAKPOINT;
 846     }
 847   }
 848   fatal("DEBUG MESSAGE: %s", msg);
 849 }
 850 
 851 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 852   ttyLocker ttyl;
 853   FlagSetting fs(Debugging, true);
 854   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 855 #ifndef PRODUCT
 856   tty->cr();
 857   findpc(pc);
 858   tty->cr();
 859 #endif
 860 #define PRINT_REG(rax, value) \
 861   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 862   PRINT_REG(rax, regs[15]);
 863   PRINT_REG(rbx, regs[12]);
 864   PRINT_REG(rcx, regs[14]);
 865   PRINT_REG(rdx, regs[13]);
 866   PRINT_REG(rdi, regs[8]);
 867   PRINT_REG(rsi, regs[9]);
 868   PRINT_REG(rbp, regs[10]);
 869   // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
 870   PRINT_REG(rsp, (intptr_t)(&regs[16]));
 871   PRINT_REG(r8 , regs[7]);
 872   PRINT_REG(r9 , regs[6]);
 873   PRINT_REG(r10, regs[5]);
 874   PRINT_REG(r11, regs[4]);
 875   PRINT_REG(r12, regs[3]);
 876   PRINT_REG(r13, regs[2]);
 877   PRINT_REG(r14, regs[1]);
 878   PRINT_REG(r15, regs[0]);
 879 #undef PRINT_REG
 880   // Print some words near the top of the stack.
 881   int64_t* rsp = &regs[16];
 882   int64_t* dump_sp = rsp;
 883   for (int col1 = 0; col1 < 8; col1++) {
 884     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 885     os::print_location(tty, *dump_sp++);
 886   }
 887   for (int row = 0; row < 25; row++) {
 888     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 889     for (int col = 0; col < 4; col++) {
 890       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 891     }
 892     tty->cr();
 893   }
 894   // Print some instructions around pc:
 895   Disassembler::decode((address)pc-64, (address)pc);
 896   tty->print_cr("--------");
 897   Disassembler::decode((address)pc, (address)pc+32);
 898 }
 899 
 900 // The java_calling_convention describes stack locations as ideal slots on
 901 // a frame with no abi restrictions. Since we must observe abi restrictions
 902 // (like the placement of the register window) the slots must be biased by
 903 // the following value.
 904 static int reg2offset_in(VMReg r) {
 905   // Account for saved rbp and return address
 906   // This should really be in_preserve_stack_slots
 907   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 908 }
 909 
 910 static int reg2offset_out(VMReg r) {
 911   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 912 }
 913 
 914 // A long move
 915 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) {
 916 
 917   // The calling conventions assures us that each VMregpair is either
 918   // all really one physical register or adjacent stack slots.
 919 
 920   if (src.is_single_phys_reg() ) {
 921     if (dst.is_single_phys_reg()) {
 922       if (dst.first() != src.first()) {
 923         mov(dst.first()->as_Register(), src.first()->as_Register());
 924       }
 925     } else {
 926       assert(dst.is_single_reg(), "not a stack pair");
 927       movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
 928     }
 929   } else if (dst.is_single_phys_reg()) {
 930     assert(src.is_single_reg(),  "not a stack pair");
 931     movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
 932   } else {
 933     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 934     movq(rax, Address(rbp, reg2offset_in(src.first())));
 935     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 936   }
 937 }
 938 
 939 // A double move
 940 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) {
 941 
 942   // The calling conventions assures us that each VMregpair is either
 943   // all really one physical register or adjacent stack slots.
 944 
 945   if (src.is_single_phys_reg() ) {
 946     if (dst.is_single_phys_reg()) {
 947       // In theory these overlap but the ordering is such that this is likely a nop
 948       if ( src.first() != dst.first()) {
 949         movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
 950       }
 951     } else {
 952       assert(dst.is_single_reg(), "not a stack pair");
 953       movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
 954     }
 955   } else if (dst.is_single_phys_reg()) {
 956     assert(src.is_single_reg(),  "not a stack pair");
 957     movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
 958   } else {
 959     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 960     movq(rax, Address(rbp, reg2offset_in(src.first())));
 961     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 962   }
 963 }
 964 
 965 
 966 // A float arg may have to do float reg int reg conversion
 967 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) {
 968   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
 969 
 970   // The calling conventions assures us that each VMregpair is either
 971   // all really one physical register or adjacent stack slots.
 972 
 973   if (src.first()->is_stack()) {
 974     if (dst.first()->is_stack()) {
 975       movl(rax, Address(rbp, reg2offset_in(src.first())));
 976       movptr(Address(rsp, reg2offset_out(dst.first())), rax);
 977     } else {
 978       // stack to reg
 979       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
 980       movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
 981     }
 982   } else if (dst.first()->is_stack()) {
 983     // reg to stack
 984     assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
 985     movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
 986   } else {
 987     // reg to reg
 988     // In theory these overlap but the ordering is such that this is likely a nop
 989     if ( src.first() != dst.first()) {
 990       movdbl(dst.first()->as_XMMRegister(),  src.first()->as_XMMRegister());
 991     }
 992   }
 993 }
 994 
 995 // On 64 bit we will store integer like items to the stack as
 996 // 64 bits items (x86_32/64 abi) even though java would only store
 997 // 32bits for a parameter. On 32bit it will simply be 32 bits
 998 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
 999 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) {
1000   if (src.first()->is_stack()) {
1001     if (dst.first()->is_stack()) {
1002       // stack to stack
1003       movslq(rax, Address(rbp, reg2offset_in(src.first())));
1004       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1005     } else {
1006       // stack to reg
1007       movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1008     }
1009   } else if (dst.first()->is_stack()) {
1010     // reg to stack
1011     // Do we really have to sign extend???
1012     // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1013     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1014   } else {
1015     // Do we really have to sign extend???
1016     // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1017     if (dst.first() != src.first()) {
1018       movq(dst.first()->as_Register(), src.first()->as_Register());
1019     }
1020   }
1021 }
1022 
1023 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1024   if (src.first()->is_stack()) {
1025     if (dst.first()->is_stack()) {
1026       // stack to stack
1027       movq(rax, Address(rbp, reg2offset_in(src.first())));
1028       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1029     } else {
1030       // stack to reg
1031       movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1032     }
1033   } else if (dst.first()->is_stack()) {
1034     // reg to stack
1035     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1036   } else {
1037     if (dst.first() != src.first()) {
1038       movq(dst.first()->as_Register(), src.first()->as_Register());
1039     }
1040   }
1041 }
1042 
1043 // An oop arg. Must pass a handle not the oop itself
1044 void MacroAssembler::object_move(OopMap* map,
1045                         int oop_handle_offset,
1046                         int framesize_in_slots,
1047                         VMRegPair src,
1048                         VMRegPair dst,
1049                         bool is_receiver,
1050                         int* receiver_offset) {
1051 
1052   // must pass a handle. First figure out the location we use as a handle
1053 
1054   Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1055 
1056   // See if oop is NULL if it is we need no handle
1057 
1058   if (src.first()->is_stack()) {
1059 
1060     // Oop is already on the stack as an argument
1061     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1062     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1063     if (is_receiver) {
1064       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1065     }
1066 
1067     cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1068     lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1069     // conditionally move a NULL
1070     cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1071   } else {
1072 
1073     // Oop is in an a register we must store it to the space we reserve
1074     // on the stack for oop_handles and pass a handle if oop is non-NULL
1075 
1076     const Register rOop = src.first()->as_Register();
1077     int oop_slot;
1078     if (rOop == j_rarg0)
1079       oop_slot = 0;
1080     else if (rOop == j_rarg1)
1081       oop_slot = 1;
1082     else if (rOop == j_rarg2)
1083       oop_slot = 2;
1084     else if (rOop == j_rarg3)
1085       oop_slot = 3;
1086     else if (rOop == j_rarg4)
1087       oop_slot = 4;
1088     else {
1089       assert(rOop == j_rarg5, "wrong register");
1090       oop_slot = 5;
1091     }
1092 
1093     oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1094     int offset = oop_slot*VMRegImpl::stack_slot_size;
1095 
1096     map->set_oop(VMRegImpl::stack2reg(oop_slot));
1097     // Store oop in handle area, may be NULL
1098     movptr(Address(rsp, offset), rOop);
1099     if (is_receiver) {
1100       *receiver_offset = offset;
1101     }
1102 
1103     cmpptr(rOop, (int32_t)NULL_WORD);
1104     lea(rHandle, Address(rsp, offset));
1105     // conditionally move a NULL from the handle area where it was just stored
1106     cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1107   }
1108 
1109   // If arg is on the stack then place it otherwise it is already in correct reg.
1110   if (dst.first()->is_stack()) {
1111     movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1112   }
1113 }
1114 
1115 #endif // _LP64
1116 
1117 // Now versions that are common to 32/64 bit
1118 
1119 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1120   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1121 }
1122 
1123 void MacroAssembler::addptr(Register dst, Register src) {
1124   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1125 }
1126 
1127 void MacroAssembler::addptr(Address dst, Register src) {
1128   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1129 }
1130 
1131 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1132   if (reachable(src)) {
1133     Assembler::addsd(dst, as_Address(src));
1134   } else {
1135     lea(rscratch1, src);
1136     Assembler::addsd(dst, Address(rscratch1, 0));
1137   }
1138 }
1139 
1140 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1141   if (reachable(src)) {
1142     addss(dst, as_Address(src));
1143   } else {
1144     lea(rscratch1, src);
1145     addss(dst, Address(rscratch1, 0));
1146   }
1147 }
1148 
1149 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
1150   if (reachable(src)) {
1151     Assembler::addpd(dst, as_Address(src));
1152   } else {
1153     lea(rscratch1, src);
1154     Assembler::addpd(dst, Address(rscratch1, 0));
1155   }
1156 }
1157 
1158 // See 8273459.  Function for ensuring 64-byte alignment, intended for stubs only.
1159 // Stub code is generated once and never copied.
1160 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1161 void MacroAssembler::align64() {
1162   align(64, (unsigned long long) pc());
1163 }
1164 
1165 void MacroAssembler::align32() {
1166   align(32, (unsigned long long) pc());
1167 }
1168 
1169 void MacroAssembler::align(int modulus) {
1170   // 8273459: Ensure alignment is possible with current segment alignment
1171   assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1172   align(modulus, offset());
1173 }
1174 
1175 void MacroAssembler::align(int modulus, int target) {
1176   if (target % modulus != 0) {
1177     nop(modulus - (target % modulus));
1178   }
1179 }
1180 
1181 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1182   // Used in sign-masking with aligned address.
1183   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1184   if (reachable(src)) {
1185     Assembler::andpd(dst, as_Address(src));
1186   } else {
1187     lea(scratch_reg, src);
1188     Assembler::andpd(dst, Address(scratch_reg, 0));
1189   }
1190 }
1191 
1192 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1193   // Used in sign-masking with aligned address.
1194   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1195   if (reachable(src)) {
1196     Assembler::andps(dst, as_Address(src));
1197   } else {
1198     lea(scratch_reg, src);
1199     Assembler::andps(dst, Address(scratch_reg, 0));
1200   }
1201 }
1202 
1203 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1204   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1205 }
1206 
1207 void MacroAssembler::atomic_incl(Address counter_addr) {
1208   lock();
1209   incrementl(counter_addr);
1210 }
1211 
1212 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1213   if (reachable(counter_addr)) {
1214     atomic_incl(as_Address(counter_addr));
1215   } else {
1216     lea(scr, counter_addr);
1217     atomic_incl(Address(scr, 0));
1218   }
1219 }
1220 
1221 #ifdef _LP64
1222 void MacroAssembler::atomic_incq(Address counter_addr) {
1223   lock();
1224   incrementq(counter_addr);
1225 }
1226 
1227 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1228   if (reachable(counter_addr)) {
1229     atomic_incq(as_Address(counter_addr));
1230   } else {
1231     lea(scr, counter_addr);
1232     atomic_incq(Address(scr, 0));
1233   }
1234 }
1235 #endif
1236 
1237 // Writes to stack successive pages until offset reached to check for
1238 // stack overflow + shadow pages.  This clobbers tmp.
1239 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1240   movptr(tmp, rsp);
1241   // Bang stack for total size given plus shadow page size.
1242   // Bang one page at a time because large size can bang beyond yellow and
1243   // red zones.
1244   Label loop;
1245   bind(loop);
1246   movl(Address(tmp, (-os::vm_page_size())), size );
1247   subptr(tmp, os::vm_page_size());
1248   subl(size, os::vm_page_size());
1249   jcc(Assembler::greater, loop);
1250 
1251   // Bang down shadow pages too.
1252   // At this point, (tmp-0) is the last address touched, so don't
1253   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1254   // was post-decremented.)  Skip this address by starting at i=1, and
1255   // touch a few more pages below.  N.B.  It is important to touch all
1256   // the way down including all pages in the shadow zone.
1257   for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1258     // this could be any sized move but this is can be a debugging crumb
1259     // so the bigger the better.
1260     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1261   }
1262 }
1263 
1264 void MacroAssembler::reserved_stack_check() {
1265     // testing if reserved zone needs to be enabled
1266     Label no_reserved_zone_enabling;
1267     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1268     NOT_LP64(get_thread(rsi);)
1269 
1270     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1271     jcc(Assembler::below, no_reserved_zone_enabling);
1272 
1273     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1274     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1275     should_not_reach_here();
1276 
1277     bind(no_reserved_zone_enabling);
1278 }
1279 
1280 void MacroAssembler::c2bool(Register x) {
1281   // implements x == 0 ? 0 : 1
1282   // note: must only look at least-significant byte of x
1283   //       since C-style booleans are stored in one byte
1284   //       only! (was bug)
1285   andl(x, 0xFF);
1286   setb(Assembler::notZero, x);
1287 }
1288 
1289 // Wouldn't need if AddressLiteral version had new name
1290 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1291   Assembler::call(L, rtype);
1292 }
1293 
1294 void MacroAssembler::call(Register entry) {
1295   Assembler::call(entry);
1296 }
1297 
1298 void MacroAssembler::call(AddressLiteral entry) {
1299   if (reachable(entry)) {
1300     Assembler::call_literal(entry.target(), entry.rspec());
1301   } else {
1302     lea(rscratch1, entry);
1303     Assembler::call(rscratch1);
1304   }
1305 }
1306 
1307 void MacroAssembler::ic_call(address entry, jint method_index) {
1308   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1309   movptr(rax, (intptr_t)Universe::non_oop_word());
1310   call(AddressLiteral(entry, rh));
1311 }
1312 
1313 // Implementation of call_VM versions
1314 
1315 void MacroAssembler::call_VM(Register oop_result,
1316                              address entry_point,
1317                              bool check_exceptions) {
1318   Label C, E;
1319   call(C, relocInfo::none);
1320   jmp(E);
1321 
1322   bind(C);
1323   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1324   ret(0);
1325 
1326   bind(E);
1327 }
1328 
1329 void MacroAssembler::call_VM(Register oop_result,
1330                              address entry_point,
1331                              Register arg_1,
1332                              bool check_exceptions) {
1333   Label C, E;
1334   call(C, relocInfo::none);
1335   jmp(E);
1336 
1337   bind(C);
1338   pass_arg1(this, arg_1);
1339   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1340   ret(0);
1341 
1342   bind(E);
1343 }
1344 
1345 void MacroAssembler::call_VM(Register oop_result,
1346                              address entry_point,
1347                              Register arg_1,
1348                              Register arg_2,
1349                              bool check_exceptions) {
1350   Label C, E;
1351   call(C, relocInfo::none);
1352   jmp(E);
1353 
1354   bind(C);
1355 
1356   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1357 
1358   pass_arg2(this, arg_2);
1359   pass_arg1(this, arg_1);
1360   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1361   ret(0);
1362 
1363   bind(E);
1364 }
1365 
1366 void MacroAssembler::call_VM(Register oop_result,
1367                              address entry_point,
1368                              Register arg_1,
1369                              Register arg_2,
1370                              Register arg_3,
1371                              bool check_exceptions) {
1372   Label C, E;
1373   call(C, relocInfo::none);
1374   jmp(E);
1375 
1376   bind(C);
1377 
1378   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1379   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1380   pass_arg3(this, arg_3);
1381 
1382   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1383   pass_arg2(this, arg_2);
1384 
1385   pass_arg1(this, arg_1);
1386   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1387   ret(0);
1388 
1389   bind(E);
1390 }
1391 
1392 void MacroAssembler::call_VM(Register oop_result,
1393                              Register last_java_sp,
1394                              address entry_point,
1395                              int number_of_arguments,
1396                              bool check_exceptions) {
1397   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1398   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1399 }
1400 
1401 void MacroAssembler::call_VM(Register oop_result,
1402                              Register last_java_sp,
1403                              address entry_point,
1404                              Register arg_1,
1405                              bool check_exceptions) {
1406   pass_arg1(this, arg_1);
1407   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1408 }
1409 
1410 void MacroAssembler::call_VM(Register oop_result,
1411                              Register last_java_sp,
1412                              address entry_point,
1413                              Register arg_1,
1414                              Register arg_2,
1415                              bool check_exceptions) {
1416 
1417   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1418   pass_arg2(this, arg_2);
1419   pass_arg1(this, arg_1);
1420   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1421 }
1422 
1423 void MacroAssembler::call_VM(Register oop_result,
1424                              Register last_java_sp,
1425                              address entry_point,
1426                              Register arg_1,
1427                              Register arg_2,
1428                              Register arg_3,
1429                              bool check_exceptions) {
1430   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1431   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1432   pass_arg3(this, arg_3);
1433   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1434   pass_arg2(this, arg_2);
1435   pass_arg1(this, arg_1);
1436   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1437 }
1438 
1439 void MacroAssembler::super_call_VM(Register oop_result,
1440                                    Register last_java_sp,
1441                                    address entry_point,
1442                                    int number_of_arguments,
1443                                    bool check_exceptions) {
1444   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1445   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1446 }
1447 
1448 void MacroAssembler::super_call_VM(Register oop_result,
1449                                    Register last_java_sp,
1450                                    address entry_point,
1451                                    Register arg_1,
1452                                    bool check_exceptions) {
1453   pass_arg1(this, arg_1);
1454   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1455 }
1456 
1457 void MacroAssembler::super_call_VM(Register oop_result,
1458                                    Register last_java_sp,
1459                                    address entry_point,
1460                                    Register arg_1,
1461                                    Register arg_2,
1462                                    bool check_exceptions) {
1463 
1464   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1465   pass_arg2(this, arg_2);
1466   pass_arg1(this, arg_1);
1467   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1468 }
1469 
1470 void MacroAssembler::super_call_VM(Register oop_result,
1471                                    Register last_java_sp,
1472                                    address entry_point,
1473                                    Register arg_1,
1474                                    Register arg_2,
1475                                    Register arg_3,
1476                                    bool check_exceptions) {
1477   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1478   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1479   pass_arg3(this, arg_3);
1480   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1481   pass_arg2(this, arg_2);
1482   pass_arg1(this, arg_1);
1483   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1484 }
1485 
1486 void MacroAssembler::call_VM_base(Register oop_result,
1487                                   Register java_thread,
1488                                   Register last_java_sp,
1489                                   address  entry_point,
1490                                   int      number_of_arguments,
1491                                   bool     check_exceptions) {
1492   // determine java_thread register
1493   if (!java_thread->is_valid()) {
1494 #ifdef _LP64
1495     java_thread = r15_thread;
1496 #else
1497     java_thread = rdi;
1498     get_thread(java_thread);
1499 #endif // LP64
1500   }
1501   // determine last_java_sp register
1502   if (!last_java_sp->is_valid()) {
1503     last_java_sp = rsp;
1504   }
1505   // debugging support
1506   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
1507   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1508 #ifdef ASSERT
1509   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1510   // r12 is the heapbase.
1511   LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1512 #endif // ASSERT
1513 
1514   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
1515   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1516 
1517   // push java thread (becomes first argument of C function)
1518 
1519   NOT_LP64(push(java_thread); number_of_arguments++);
1520   LP64_ONLY(mov(c_rarg0, r15_thread));
1521 
1522   // set last Java frame before call
1523   assert(last_java_sp != rbp, "can't use ebp/rbp");
1524 
1525   // Only interpreter should have to set fp
1526   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1527 
1528   // do the call, remove parameters
1529   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1530 
1531   // restore the thread (cannot use the pushed argument since arguments
1532   // may be overwritten by C code generated by an optimizing compiler);
1533   // however can use the register value directly if it is callee saved.
1534   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1535     // rdi & rsi (also r15) are callee saved -> nothing to do
1536 #ifdef ASSERT
1537     guarantee(java_thread != rax, "change this code");
1538     push(rax);
1539     { Label L;
1540       get_thread(rax);
1541       cmpptr(java_thread, rax);
1542       jcc(Assembler::equal, L);
1543       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1544       bind(L);
1545     }
1546     pop(rax);
1547 #endif
1548   } else {
1549     get_thread(java_thread);
1550   }
1551   // reset last Java frame
1552   // Only interpreter should have to clear fp
1553   reset_last_Java_frame(java_thread, true);
1554 
1555    // C++ interp handles this in the interpreter
1556   check_and_handle_popframe(java_thread);
1557   check_and_handle_earlyret(java_thread);
1558 
1559   if (check_exceptions) {
1560     // check for pending exceptions (java_thread is set upon return)
1561     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1562 #ifndef _LP64
1563     jump_cc(Assembler::notEqual,
1564             RuntimeAddress(StubRoutines::forward_exception_entry()));
1565 #else
1566     // This used to conditionally jump to forward_exception however it is
1567     // possible if we relocate that the branch will not reach. So we must jump
1568     // around so we can always reach
1569 
1570     Label ok;
1571     jcc(Assembler::equal, ok);
1572     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1573     bind(ok);
1574 #endif // LP64
1575   }
1576 
1577   // get oop result if there is one and reset the value in the thread
1578   if (oop_result->is_valid()) {
1579     get_vm_result(oop_result, java_thread);
1580   }
1581 }
1582 
1583 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1584 
1585   // Calculate the value for last_Java_sp
1586   // somewhat subtle. call_VM does an intermediate call
1587   // which places a return address on the stack just under the
1588   // stack pointer as the user finished with it. This allows
1589   // use to retrieve last_Java_pc from last_Java_sp[-1].
1590   // On 32bit we then have to push additional args on the stack to accomplish
1591   // the actual requested call. On 64bit call_VM only can use register args
1592   // so the only extra space is the return address that call_VM created.
1593   // This hopefully explains the calculations here.
1594 
1595 #ifdef _LP64
1596   // We've pushed one address, correct last_Java_sp
1597   lea(rax, Address(rsp, wordSize));
1598 #else
1599   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1600 #endif // LP64
1601 
1602   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1603 
1604 }
1605 
1606 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1607 void MacroAssembler::call_VM_leaf0(address entry_point) {
1608   MacroAssembler::call_VM_leaf_base(entry_point, 0);
1609 }
1610 
1611 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1612   call_VM_leaf_base(entry_point, number_of_arguments);
1613 }
1614 
1615 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1616   pass_arg0(this, arg_0);
1617   call_VM_leaf(entry_point, 1);
1618 }
1619 
1620 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1621 
1622   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1623   pass_arg1(this, arg_1);
1624   pass_arg0(this, arg_0);
1625   call_VM_leaf(entry_point, 2);
1626 }
1627 
1628 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1629   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1630   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1631   pass_arg2(this, arg_2);
1632   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1633   pass_arg1(this, arg_1);
1634   pass_arg0(this, arg_0);
1635   call_VM_leaf(entry_point, 3);
1636 }
1637 
1638 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1639   pass_arg0(this, arg_0);
1640   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1641 }
1642 
1643 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1644 
1645   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1646   pass_arg1(this, arg_1);
1647   pass_arg0(this, arg_0);
1648   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1649 }
1650 
1651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1652   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1653   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1654   pass_arg2(this, arg_2);
1655   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1656   pass_arg1(this, arg_1);
1657   pass_arg0(this, arg_0);
1658   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1659 }
1660 
1661 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1662   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1663   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1664   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1665   pass_arg3(this, arg_3);
1666   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1667   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1668   pass_arg2(this, arg_2);
1669   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1670   pass_arg1(this, arg_1);
1671   pass_arg0(this, arg_0);
1672   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1673 }
1674 
1675 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1676   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1677   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1678   verify_oop_msg(oop_result, "broken oop in call_VM_base");
1679 }
1680 
1681 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1682   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1683   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1684 }
1685 
1686 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1687 }
1688 
1689 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1690 }
1691 
1692 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1693   if (reachable(src1)) {
1694     cmpl(as_Address(src1), imm);
1695   } else {
1696     lea(rscratch1, src1);
1697     cmpl(Address(rscratch1, 0), imm);
1698   }
1699 }
1700 
1701 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1702   assert(!src2.is_lval(), "use cmpptr");
1703   if (reachable(src2)) {
1704     cmpl(src1, as_Address(src2));
1705   } else {
1706     lea(rscratch1, src2);
1707     cmpl(src1, Address(rscratch1, 0));
1708   }
1709 }
1710 
1711 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1712   Assembler::cmpl(src1, imm);
1713 }
1714 
1715 void MacroAssembler::cmp32(Register src1, Address src2) {
1716   Assembler::cmpl(src1, src2);
1717 }
1718 
1719 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1720   ucomisd(opr1, opr2);
1721 
1722   Label L;
1723   if (unordered_is_less) {
1724     movl(dst, -1);
1725     jcc(Assembler::parity, L);
1726     jcc(Assembler::below , L);
1727     movl(dst, 0);
1728     jcc(Assembler::equal , L);
1729     increment(dst);
1730   } else { // unordered is greater
1731     movl(dst, 1);
1732     jcc(Assembler::parity, L);
1733     jcc(Assembler::above , L);
1734     movl(dst, 0);
1735     jcc(Assembler::equal , L);
1736     decrementl(dst);
1737   }
1738   bind(L);
1739 }
1740 
1741 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1742   ucomiss(opr1, opr2);
1743 
1744   Label L;
1745   if (unordered_is_less) {
1746     movl(dst, -1);
1747     jcc(Assembler::parity, L);
1748     jcc(Assembler::below , L);
1749     movl(dst, 0);
1750     jcc(Assembler::equal , L);
1751     increment(dst);
1752   } else { // unordered is greater
1753     movl(dst, 1);
1754     jcc(Assembler::parity, L);
1755     jcc(Assembler::above , L);
1756     movl(dst, 0);
1757     jcc(Assembler::equal , L);
1758     decrementl(dst);
1759   }
1760   bind(L);
1761 }
1762 
1763 
1764 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1765   if (reachable(src1)) {
1766     cmpb(as_Address(src1), imm);
1767   } else {
1768     lea(rscratch1, src1);
1769     cmpb(Address(rscratch1, 0), imm);
1770   }
1771 }
1772 
1773 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1774 #ifdef _LP64
1775   if (src2.is_lval()) {
1776     movptr(rscratch1, src2);
1777     Assembler::cmpq(src1, rscratch1);
1778   } else if (reachable(src2)) {
1779     cmpq(src1, as_Address(src2));
1780   } else {
1781     lea(rscratch1, src2);
1782     Assembler::cmpq(src1, Address(rscratch1, 0));
1783   }
1784 #else
1785   if (src2.is_lval()) {
1786     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1787   } else {
1788     cmpl(src1, as_Address(src2));
1789   }
1790 #endif // _LP64
1791 }
1792 
1793 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1794   assert(src2.is_lval(), "not a mem-mem compare");
1795 #ifdef _LP64
1796   // moves src2's literal address
1797   movptr(rscratch1, src2);
1798   Assembler::cmpq(src1, rscratch1);
1799 #else
1800   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1801 #endif // _LP64
1802 }
1803 
1804 void MacroAssembler::cmpoop(Register src1, Register src2) {
1805   cmpptr(src1, src2);
1806 }
1807 
1808 void MacroAssembler::cmpoop(Register src1, Address src2) {
1809   cmpptr(src1, src2);
1810 }
1811 
1812 #ifdef _LP64
1813 void MacroAssembler::cmpoop(Register src1, jobject src2) {
1814   movoop(rscratch1, src2);
1815   cmpptr(src1, rscratch1);
1816 }
1817 #endif
1818 
1819 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1820   if (reachable(adr)) {
1821     lock();
1822     cmpxchgptr(reg, as_Address(adr));
1823   } else {
1824     lea(rscratch1, adr);
1825     lock();
1826     cmpxchgptr(reg, Address(rscratch1, 0));
1827   }
1828 }
1829 
1830 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1831   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1832 }
1833 
1834 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1835   if (reachable(src)) {
1836     Assembler::comisd(dst, as_Address(src));
1837   } else {
1838     lea(rscratch1, src);
1839     Assembler::comisd(dst, Address(rscratch1, 0));
1840   }
1841 }
1842 
1843 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1844   if (reachable(src)) {
1845     Assembler::comiss(dst, as_Address(src));
1846   } else {
1847     lea(rscratch1, src);
1848     Assembler::comiss(dst, Address(rscratch1, 0));
1849   }
1850 }
1851 
1852 
1853 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1854   Condition negated_cond = negate_condition(cond);
1855   Label L;
1856   jcc(negated_cond, L);
1857   pushf(); // Preserve flags
1858   atomic_incl(counter_addr);
1859   popf();
1860   bind(L);
1861 }
1862 
1863 int MacroAssembler::corrected_idivl(Register reg) {
1864   // Full implementation of Java idiv and irem; checks for
1865   // special case as described in JVM spec., p.243 & p.271.
1866   // The function returns the (pc) offset of the idivl
1867   // instruction - may be needed for implicit exceptions.
1868   //
1869   //         normal case                           special case
1870   //
1871   // input : rax,: dividend                         min_int
1872   //         reg: divisor   (may not be rax,/rdx)   -1
1873   //
1874   // output: rax,: quotient  (= rax, idiv reg)       min_int
1875   //         rdx: remainder (= rax, irem reg)       0
1876   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1877   const int min_int = 0x80000000;
1878   Label normal_case, special_case;
1879 
1880   // check for special case
1881   cmpl(rax, min_int);
1882   jcc(Assembler::notEqual, normal_case);
1883   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1884   cmpl(reg, -1);
1885   jcc(Assembler::equal, special_case);
1886 
1887   // handle normal case
1888   bind(normal_case);
1889   cdql();
1890   int idivl_offset = offset();
1891   idivl(reg);
1892 
1893   // normal and special case exit
1894   bind(special_case);
1895 
1896   return idivl_offset;
1897 }
1898 
1899 
1900 
1901 void MacroAssembler::decrementl(Register reg, int value) {
1902   if (value == min_jint) {subl(reg, value) ; return; }
1903   if (value <  0) { incrementl(reg, -value); return; }
1904   if (value == 0) {                        ; return; }
1905   if (value == 1 && UseIncDec) { decl(reg) ; return; }
1906   /* else */      { subl(reg, value)       ; return; }
1907 }
1908 
1909 void MacroAssembler::decrementl(Address dst, int value) {
1910   if (value == min_jint) {subl(dst, value) ; return; }
1911   if (value <  0) { incrementl(dst, -value); return; }
1912   if (value == 0) {                        ; return; }
1913   if (value == 1 && UseIncDec) { decl(dst) ; return; }
1914   /* else */      { subl(dst, value)       ; return; }
1915 }
1916 
1917 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1918   assert (shift_value > 0, "illegal shift value");
1919   Label _is_positive;
1920   testl (reg, reg);
1921   jcc (Assembler::positive, _is_positive);
1922   int offset = (1 << shift_value) - 1 ;
1923 
1924   if (offset == 1) {
1925     incrementl(reg);
1926   } else {
1927     addl(reg, offset);
1928   }
1929 
1930   bind (_is_positive);
1931   sarl(reg, shift_value);
1932 }
1933 
1934 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
1935   if (reachable(src)) {
1936     Assembler::divsd(dst, as_Address(src));
1937   } else {
1938     lea(rscratch1, src);
1939     Assembler::divsd(dst, Address(rscratch1, 0));
1940   }
1941 }
1942 
1943 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
1944   if (reachable(src)) {
1945     Assembler::divss(dst, as_Address(src));
1946   } else {
1947     lea(rscratch1, src);
1948     Assembler::divss(dst, Address(rscratch1, 0));
1949   }
1950 }
1951 
1952 void MacroAssembler::enter() {
1953   push(rbp);
1954   mov(rbp, rsp);
1955 }
1956 
1957 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1958 void MacroAssembler::fat_nop() {
1959   if (UseAddressNop) {
1960     addr_nop_5();
1961   } else {
1962     emit_int8(0x26); // es:
1963     emit_int8(0x2e); // cs:
1964     emit_int8(0x64); // fs:
1965     emit_int8(0x65); // gs:
1966     emit_int8((unsigned char)0x90);
1967   }
1968 }
1969 
1970 #ifndef _LP64
1971 void MacroAssembler::fcmp(Register tmp) {
1972   fcmp(tmp, 1, true, true);
1973 }
1974 
1975 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
1976   assert(!pop_right || pop_left, "usage error");
1977   if (VM_Version::supports_cmov()) {
1978     assert(tmp == noreg, "unneeded temp");
1979     if (pop_left) {
1980       fucomip(index);
1981     } else {
1982       fucomi(index);
1983     }
1984     if (pop_right) {
1985       fpop();
1986     }
1987   } else {
1988     assert(tmp != noreg, "need temp");
1989     if (pop_left) {
1990       if (pop_right) {
1991         fcompp();
1992       } else {
1993         fcomp(index);
1994       }
1995     } else {
1996       fcom(index);
1997     }
1998     // convert FPU condition into eflags condition via rax,
1999     save_rax(tmp);
2000     fwait(); fnstsw_ax();
2001     sahf();
2002     restore_rax(tmp);
2003   }
2004   // condition codes set as follows:
2005   //
2006   // CF (corresponds to C0) if x < y
2007   // PF (corresponds to C2) if unordered
2008   // ZF (corresponds to C3) if x = y
2009 }
2010 
2011 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2012   fcmp2int(dst, unordered_is_less, 1, true, true);
2013 }
2014 
2015 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2016   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2017   Label L;
2018   if (unordered_is_less) {
2019     movl(dst, -1);
2020     jcc(Assembler::parity, L);
2021     jcc(Assembler::below , L);
2022     movl(dst, 0);
2023     jcc(Assembler::equal , L);
2024     increment(dst);
2025   } else { // unordered is greater
2026     movl(dst, 1);
2027     jcc(Assembler::parity, L);
2028     jcc(Assembler::above , L);
2029     movl(dst, 0);
2030     jcc(Assembler::equal , L);
2031     decrementl(dst);
2032   }
2033   bind(L);
2034 }
2035 
2036 void MacroAssembler::fld_d(AddressLiteral src) {
2037   fld_d(as_Address(src));
2038 }
2039 
2040 void MacroAssembler::fld_s(AddressLiteral src) {
2041   fld_s(as_Address(src));
2042 }
2043 
2044 void MacroAssembler::fldcw(AddressLiteral src) {
2045   Assembler::fldcw(as_Address(src));
2046 }
2047 
2048 void MacroAssembler::fpop() {
2049   ffree();
2050   fincstp();
2051 }
2052 
2053 void MacroAssembler::fremr(Register tmp) {
2054   save_rax(tmp);
2055   { Label L;
2056     bind(L);
2057     fprem();
2058     fwait(); fnstsw_ax();
2059     sahf();
2060     jcc(Assembler::parity, L);
2061   }
2062   restore_rax(tmp);
2063   // Result is in ST0.
2064   // Note: fxch & fpop to get rid of ST1
2065   // (otherwise FPU stack could overflow eventually)
2066   fxch(1);
2067   fpop();
2068 }
2069 
2070 void MacroAssembler::empty_FPU_stack() {
2071   if (VM_Version::supports_mmx()) {
2072     emms();
2073   } else {
2074     for (int i = 8; i-- > 0; ) ffree(i);
2075   }
2076 }
2077 #endif // !LP64
2078 
2079 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2080   if (reachable(src)) {
2081     Assembler::mulpd(dst, as_Address(src));
2082   } else {
2083     lea(rscratch1, src);
2084     Assembler::mulpd(dst, Address(rscratch1, 0));
2085   }
2086 }
2087 
2088 void MacroAssembler::load_float(Address src) {
2089 #ifdef _LP64
2090   movflt(xmm0, src);
2091 #else
2092   if (UseSSE >= 1) {
2093     movflt(xmm0, src);
2094   } else {
2095     fld_s(src);
2096   }
2097 #endif // LP64
2098 }
2099 
2100 void MacroAssembler::store_float(Address dst) {
2101 #ifdef _LP64
2102   movflt(dst, xmm0);
2103 #else
2104   if (UseSSE >= 1) {
2105     movflt(dst, xmm0);
2106   } else {
2107     fstp_s(dst);
2108   }
2109 #endif // LP64
2110 }
2111 
2112 void MacroAssembler::load_double(Address src) {
2113 #ifdef _LP64
2114   movdbl(xmm0, src);
2115 #else
2116   if (UseSSE >= 2) {
2117     movdbl(xmm0, src);
2118   } else {
2119     fld_d(src);
2120   }
2121 #endif // LP64
2122 }
2123 
2124 void MacroAssembler::store_double(Address dst) {
2125 #ifdef _LP64
2126   movdbl(dst, xmm0);
2127 #else
2128   if (UseSSE >= 2) {
2129     movdbl(dst, xmm0);
2130   } else {
2131     fstp_d(dst);
2132   }
2133 #endif // LP64
2134 }
2135 
2136 // dst = c = a * b + c
2137 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2138   Assembler::vfmadd231sd(c, a, b);
2139   if (dst != c) {
2140     movdbl(dst, c);
2141   }
2142 }
2143 
2144 // dst = c = a * b + c
2145 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2146   Assembler::vfmadd231ss(c, a, b);
2147   if (dst != c) {
2148     movflt(dst, c);
2149   }
2150 }
2151 
2152 // dst = c = a * b + c
2153 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2154   Assembler::vfmadd231pd(c, a, b, vector_len);
2155   if (dst != c) {
2156     vmovdqu(dst, c);
2157   }
2158 }
2159 
2160 // dst = c = a * b + c
2161 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2162   Assembler::vfmadd231ps(c, a, b, vector_len);
2163   if (dst != c) {
2164     vmovdqu(dst, c);
2165   }
2166 }
2167 
2168 // dst = c = a * b + c
2169 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2170   Assembler::vfmadd231pd(c, a, b, vector_len);
2171   if (dst != c) {
2172     vmovdqu(dst, c);
2173   }
2174 }
2175 
2176 // dst = c = a * b + c
2177 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2178   Assembler::vfmadd231ps(c, a, b, vector_len);
2179   if (dst != c) {
2180     vmovdqu(dst, c);
2181   }
2182 }
2183 
2184 void MacroAssembler::incrementl(AddressLiteral dst) {
2185   if (reachable(dst)) {
2186     incrementl(as_Address(dst));
2187   } else {
2188     lea(rscratch1, dst);
2189     incrementl(Address(rscratch1, 0));
2190   }
2191 }
2192 
2193 void MacroAssembler::incrementl(ArrayAddress dst) {
2194   incrementl(as_Address(dst));
2195 }
2196 
2197 void MacroAssembler::incrementl(Register reg, int value) {
2198   if (value == min_jint) {addl(reg, value) ; return; }
2199   if (value <  0) { decrementl(reg, -value); return; }
2200   if (value == 0) {                        ; return; }
2201   if (value == 1 && UseIncDec) { incl(reg) ; return; }
2202   /* else */      { addl(reg, value)       ; return; }
2203 }
2204 
2205 void MacroAssembler::incrementl(Address dst, int value) {
2206   if (value == min_jint) {addl(dst, value) ; return; }
2207   if (value <  0) { decrementl(dst, -value); return; }
2208   if (value == 0) {                        ; return; }
2209   if (value == 1 && UseIncDec) { incl(dst) ; return; }
2210   /* else */      { addl(dst, value)       ; return; }
2211 }
2212 
2213 void MacroAssembler::jump(AddressLiteral dst) {
2214   if (reachable(dst)) {
2215     jmp_literal(dst.target(), dst.rspec());
2216   } else {
2217     lea(rscratch1, dst);
2218     jmp(rscratch1);
2219   }
2220 }
2221 
2222 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2223   if (reachable(dst)) {
2224     InstructionMark im(this);
2225     relocate(dst.reloc());
2226     const int short_size = 2;
2227     const int long_size = 6;
2228     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2229     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2230       // 0111 tttn #8-bit disp
2231       emit_int8(0x70 | cc);
2232       emit_int8((offs - short_size) & 0xFF);
2233     } else {
2234       // 0000 1111 1000 tttn #32-bit disp
2235       emit_int8(0x0F);
2236       emit_int8((unsigned char)(0x80 | cc));
2237       emit_int32(offs - long_size);
2238     }
2239   } else {
2240 #ifdef ASSERT
2241     warning("reversing conditional branch");
2242 #endif /* ASSERT */
2243     Label skip;
2244     jccb(reverse[cc], skip);
2245     lea(rscratch1, dst);
2246     Assembler::jmp(rscratch1);
2247     bind(skip);
2248   }
2249 }
2250 
2251 void MacroAssembler::fld_x(AddressLiteral src) {
2252   Assembler::fld_x(as_Address(src));
2253 }
2254 
2255 void MacroAssembler::ldmxcsr(AddressLiteral src, Register scratchReg) {
2256   if (reachable(src)) {
2257     Assembler::ldmxcsr(as_Address(src));
2258   } else {
2259     lea(scratchReg, src);
2260     Assembler::ldmxcsr(Address(scratchReg, 0));
2261   }
2262 }
2263 
2264 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2265   int off;
2266   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2267     off = offset();
2268     movsbl(dst, src); // movsxb
2269   } else {
2270     off = load_unsigned_byte(dst, src);
2271     shll(dst, 24);
2272     sarl(dst, 24);
2273   }
2274   return off;
2275 }
2276 
2277 // Note: load_signed_short used to be called load_signed_word.
2278 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2279 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2280 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2281 int MacroAssembler::load_signed_short(Register dst, Address src) {
2282   int off;
2283   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2284     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2285     // version but this is what 64bit has always done. This seems to imply
2286     // that users are only using 32bits worth.
2287     off = offset();
2288     movswl(dst, src); // movsxw
2289   } else {
2290     off = load_unsigned_short(dst, src);
2291     shll(dst, 16);
2292     sarl(dst, 16);
2293   }
2294   return off;
2295 }
2296 
2297 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2298   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2299   // and "3.9 Partial Register Penalties", p. 22).
2300   int off;
2301   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2302     off = offset();
2303     movzbl(dst, src); // movzxb
2304   } else {
2305     xorl(dst, dst);
2306     off = offset();
2307     movb(dst, src);
2308   }
2309   return off;
2310 }
2311 
2312 // Note: load_unsigned_short used to be called load_unsigned_word.
2313 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2314   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2315   // and "3.9 Partial Register Penalties", p. 22).
2316   int off;
2317   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2318     off = offset();
2319     movzwl(dst, src); // movzxw
2320   } else {
2321     xorl(dst, dst);
2322     off = offset();
2323     movw(dst, src);
2324   }
2325   return off;
2326 }
2327 
2328 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2329   switch (size_in_bytes) {
2330 #ifndef _LP64
2331   case  8:
2332     assert(dst2 != noreg, "second dest register required");
2333     movl(dst,  src);
2334     movl(dst2, src.plus_disp(BytesPerInt));
2335     break;
2336 #else
2337   case  8:  movq(dst, src); break;
2338 #endif
2339   case  4:  movl(dst, src); break;
2340   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2341   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2342   default:  ShouldNotReachHere();
2343   }
2344 }
2345 
2346 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2347   switch (size_in_bytes) {
2348 #ifndef _LP64
2349   case  8:
2350     assert(src2 != noreg, "second source register required");
2351     movl(dst,                        src);
2352     movl(dst.plus_disp(BytesPerInt), src2);
2353     break;
2354 #else
2355   case  8:  movq(dst, src); break;
2356 #endif
2357   case  4:  movl(dst, src); break;
2358   case  2:  movw(dst, src); break;
2359   case  1:  movb(dst, src); break;
2360   default:  ShouldNotReachHere();
2361   }
2362 }
2363 
2364 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2365   if (reachable(dst)) {
2366     movl(as_Address(dst), src);
2367   } else {
2368     lea(rscratch1, dst);
2369     movl(Address(rscratch1, 0), src);
2370   }
2371 }
2372 
2373 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2374   if (reachable(src)) {
2375     movl(dst, as_Address(src));
2376   } else {
2377     lea(rscratch1, src);
2378     movl(dst, Address(rscratch1, 0));
2379   }
2380 }
2381 
2382 // C++ bool manipulation
2383 
2384 void MacroAssembler::movbool(Register dst, Address src) {
2385   if(sizeof(bool) == 1)
2386     movb(dst, src);
2387   else if(sizeof(bool) == 2)
2388     movw(dst, src);
2389   else if(sizeof(bool) == 4)
2390     movl(dst, src);
2391   else
2392     // unsupported
2393     ShouldNotReachHere();
2394 }
2395 
2396 void MacroAssembler::movbool(Address dst, bool boolconst) {
2397   if(sizeof(bool) == 1)
2398     movb(dst, (int) boolconst);
2399   else if(sizeof(bool) == 2)
2400     movw(dst, (int) boolconst);
2401   else if(sizeof(bool) == 4)
2402     movl(dst, (int) boolconst);
2403   else
2404     // unsupported
2405     ShouldNotReachHere();
2406 }
2407 
2408 void MacroAssembler::movbool(Address dst, Register src) {
2409   if(sizeof(bool) == 1)
2410     movb(dst, src);
2411   else if(sizeof(bool) == 2)
2412     movw(dst, src);
2413   else if(sizeof(bool) == 4)
2414     movl(dst, src);
2415   else
2416     // unsupported
2417     ShouldNotReachHere();
2418 }
2419 
2420 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2421   movb(as_Address(dst), src);
2422 }
2423 
2424 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2425   if (reachable(src)) {
2426     movdl(dst, as_Address(src));
2427   } else {
2428     lea(rscratch1, src);
2429     movdl(dst, Address(rscratch1, 0));
2430   }
2431 }
2432 
2433 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2434   if (reachable(src)) {
2435     movq(dst, as_Address(src));
2436   } else {
2437     lea(rscratch1, src);
2438     movq(dst, Address(rscratch1, 0));
2439   }
2440 }
2441 
2442 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2443   if (reachable(src)) {
2444     if (UseXmmLoadAndClearUpper) {
2445       movsd (dst, as_Address(src));
2446     } else {
2447       movlpd(dst, as_Address(src));
2448     }
2449   } else {
2450     lea(rscratch1, src);
2451     if (UseXmmLoadAndClearUpper) {
2452       movsd (dst, Address(rscratch1, 0));
2453     } else {
2454       movlpd(dst, Address(rscratch1, 0));
2455     }
2456   }
2457 }
2458 
2459 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2460   if (reachable(src)) {
2461     movss(dst, as_Address(src));
2462   } else {
2463     lea(rscratch1, src);
2464     movss(dst, Address(rscratch1, 0));
2465   }
2466 }
2467 
2468 void MacroAssembler::movptr(Register dst, Register src) {
2469   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2470 }
2471 
2472 void MacroAssembler::movptr(Register dst, Address src) {
2473   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2474 }
2475 
2476 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2477 void MacroAssembler::movptr(Register dst, intptr_t src) {
2478   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2479 }
2480 
2481 void MacroAssembler::movptr(Address dst, Register src) {
2482   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2483 }
2484 
2485 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2486     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2487     Assembler::movdqu(dst, src);
2488 }
2489 
2490 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2491     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2492     Assembler::movdqu(dst, src);
2493 }
2494 
2495 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2496     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2497     Assembler::movdqu(dst, src);
2498 }
2499 
2500 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
2501   if (reachable(src)) {
2502     movdqu(dst, as_Address(src));
2503   } else {
2504     lea(scratchReg, src);
2505     movdqu(dst, Address(scratchReg, 0));
2506   }
2507 }
2508 
2509 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2510     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2511     Assembler::vmovdqu(dst, src);
2512 }
2513 
2514 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2515     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2516     Assembler::vmovdqu(dst, src);
2517 }
2518 
2519 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2520     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2521     Assembler::vmovdqu(dst, src);
2522 }
2523 
2524 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
2525   if (reachable(src)) {
2526     vmovdqu(dst, as_Address(src));
2527   }
2528   else {
2529     lea(scratch_reg, src);
2530     vmovdqu(dst, Address(scratch_reg, 0));
2531   }
2532 }
2533 
2534 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg, int vector_len) {
2535   assert(vector_len <= AVX_512bit, "unexpected vector length");
2536   if (vector_len == AVX_512bit) {
2537     evmovdquq(dst, src, AVX_512bit, scratch_reg);
2538   } else if (vector_len == AVX_256bit) {
2539     vmovdqu(dst, src, scratch_reg);
2540   } else {
2541     movdqu(dst, src, scratch_reg);
2542   }
2543 }
2544 
2545 void MacroAssembler::kmov(KRegister dst, Address src) {
2546   if (VM_Version::supports_avx512bw()) {
2547     kmovql(dst, src);
2548   } else {
2549     assert(VM_Version::supports_evex(), "");
2550     kmovwl(dst, src);
2551   }
2552 }
2553 
2554 void MacroAssembler::kmov(Address dst, KRegister src) {
2555   if (VM_Version::supports_avx512bw()) {
2556     kmovql(dst, src);
2557   } else {
2558     assert(VM_Version::supports_evex(), "");
2559     kmovwl(dst, src);
2560   }
2561 }
2562 
2563 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2564   if (VM_Version::supports_avx512bw()) {
2565     kmovql(dst, src);
2566   } else {
2567     assert(VM_Version::supports_evex(), "");
2568     kmovwl(dst, src);
2569   }
2570 }
2571 
2572 void MacroAssembler::kmov(Register dst, KRegister src) {
2573   if (VM_Version::supports_avx512bw()) {
2574     kmovql(dst, src);
2575   } else {
2576     assert(VM_Version::supports_evex(), "");
2577     kmovwl(dst, src);
2578   }
2579 }
2580 
2581 void MacroAssembler::kmov(KRegister dst, Register src) {
2582   if (VM_Version::supports_avx512bw()) {
2583     kmovql(dst, src);
2584   } else {
2585     assert(VM_Version::supports_evex(), "");
2586     kmovwl(dst, src);
2587   }
2588 }
2589 
2590 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) {
2591   if (reachable(src)) {
2592     kmovql(dst, as_Address(src));
2593   } else {
2594     lea(scratch_reg, src);
2595     kmovql(dst, Address(scratch_reg, 0));
2596   }
2597 }
2598 
2599 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) {
2600   if (reachable(src)) {
2601     kmovwl(dst, as_Address(src));
2602   } else {
2603     lea(scratch_reg, src);
2604     kmovwl(dst, Address(scratch_reg, 0));
2605   }
2606 }
2607 
2608 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2609                                int vector_len, Register scratch_reg) {
2610   if (reachable(src)) {
2611     if (mask == k0) {
2612       Assembler::evmovdqub(dst, as_Address(src), merge, vector_len);
2613     } else {
2614       Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2615     }
2616   } else {
2617     lea(scratch_reg, src);
2618     if (mask == k0) {
2619       Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len);
2620     } else {
2621       Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2622     }
2623   }
2624 }
2625 
2626 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2627                                int vector_len, Register scratch_reg) {
2628   if (reachable(src)) {
2629     Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2630   } else {
2631     lea(scratch_reg, src);
2632     Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2633   }
2634 }
2635 
2636 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2637                                int vector_len, Register scratch_reg) {
2638   if (reachable(src)) {
2639     Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2640   } else {
2641     lea(scratch_reg, src);
2642     Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2643   }
2644 }
2645 
2646 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2647                                int vector_len, Register scratch_reg) {
2648   if (reachable(src)) {
2649     Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2650   } else {
2651     lea(scratch_reg, src);
2652     Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2653   }
2654 }
2655 
2656 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2657   if (reachable(src)) {
2658     Assembler::evmovdquq(dst, as_Address(src), vector_len);
2659   } else {
2660     lea(rscratch, src);
2661     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2662   }
2663 }
2664 
2665 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2666   if (reachable(src)) {
2667     Assembler::movdqa(dst, as_Address(src));
2668   } else {
2669     lea(rscratch1, src);
2670     Assembler::movdqa(dst, Address(rscratch1, 0));
2671   }
2672 }
2673 
2674 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2675   if (reachable(src)) {
2676     Assembler::movsd(dst, as_Address(src));
2677   } else {
2678     lea(rscratch1, src);
2679     Assembler::movsd(dst, Address(rscratch1, 0));
2680   }
2681 }
2682 
2683 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2684   if (reachable(src)) {
2685     Assembler::movss(dst, as_Address(src));
2686   } else {
2687     lea(rscratch1, src);
2688     Assembler::movss(dst, Address(rscratch1, 0));
2689   }
2690 }
2691 
2692 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2693   if (reachable(src)) {
2694     Assembler::vmovddup(dst, as_Address(src), vector_len);
2695   } else {
2696     lea(rscratch, src);
2697     Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2698   }
2699 }
2700 
2701 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2702   if (reachable(src)) {
2703     Assembler::mulsd(dst, as_Address(src));
2704   } else {
2705     lea(rscratch1, src);
2706     Assembler::mulsd(dst, Address(rscratch1, 0));
2707   }
2708 }
2709 
2710 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2711   if (reachable(src)) {
2712     Assembler::mulss(dst, as_Address(src));
2713   } else {
2714     lea(rscratch1, src);
2715     Assembler::mulss(dst, Address(rscratch1, 0));
2716   }
2717 }
2718 
2719 void MacroAssembler::null_check(Register reg, int offset) {
2720   if (needs_explicit_null_check(offset)) {
2721     // provoke OS NULL exception if reg = NULL by
2722     // accessing M[reg] w/o changing any (non-CC) registers
2723     // NOTE: cmpl is plenty here to provoke a segv
2724     cmpptr(rax, Address(reg, 0));
2725     // Note: should probably use testl(rax, Address(reg, 0));
2726     //       may be shorter code (however, this version of
2727     //       testl needs to be implemented first)
2728   } else {
2729     // nothing to do, (later) access of M[reg + offset]
2730     // will provoke OS NULL exception if reg = NULL
2731   }
2732 }
2733 
2734 void MacroAssembler::os_breakpoint() {
2735   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2736   // (e.g., MSVC can't call ps() otherwise)
2737   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2738 }
2739 
2740 void MacroAssembler::unimplemented(const char* what) {
2741   const char* buf = NULL;
2742   {
2743     ResourceMark rm;
2744     stringStream ss;
2745     ss.print("unimplemented: %s", what);
2746     buf = code_string(ss.as_string());
2747   }
2748   stop(buf);
2749 }
2750 
2751 #ifdef _LP64
2752 #define XSTATE_BV 0x200
2753 #endif
2754 
2755 void MacroAssembler::pop_CPU_state() {
2756   pop_FPU_state();
2757   pop_IU_state();
2758 }
2759 
2760 void MacroAssembler::pop_FPU_state() {
2761 #ifndef _LP64
2762   frstor(Address(rsp, 0));
2763 #else
2764   fxrstor(Address(rsp, 0));
2765 #endif
2766   addptr(rsp, FPUStateSizeInWords * wordSize);
2767 }
2768 
2769 void MacroAssembler::pop_IU_state() {
2770   popa();
2771   LP64_ONLY(addq(rsp, 8));
2772   popf();
2773 }
2774 
2775 // Save Integer and Float state
2776 // Warning: Stack must be 16 byte aligned (64bit)
2777 void MacroAssembler::push_CPU_state() {
2778   push_IU_state();
2779   push_FPU_state();
2780 }
2781 
2782 void MacroAssembler::push_FPU_state() {
2783   subptr(rsp, FPUStateSizeInWords * wordSize);
2784 #ifndef _LP64
2785   fnsave(Address(rsp, 0));
2786   fwait();
2787 #else
2788   fxsave(Address(rsp, 0));
2789 #endif // LP64
2790 }
2791 
2792 void MacroAssembler::push_IU_state() {
2793   // Push flags first because pusha kills them
2794   pushf();
2795   // Make sure rsp stays 16-byte aligned
2796   LP64_ONLY(subq(rsp, 8));
2797   pusha();
2798 }
2799 
2800 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
2801   if (!java_thread->is_valid()) {
2802     java_thread = rdi;
2803     get_thread(java_thread);
2804   }
2805   // we must set sp to zero to clear frame
2806   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2807   // must clear fp, so that compiled frames are not confused; it is
2808   // possible that we need it only for debugging
2809   if (clear_fp) {
2810     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2811   }
2812   // Always clear the pc because it could have been set by make_walkable()
2813   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2814   vzeroupper();
2815 }
2816 
2817 void MacroAssembler::restore_rax(Register tmp) {
2818   if (tmp == noreg) pop(rax);
2819   else if (tmp != rax) mov(rax, tmp);
2820 }
2821 
2822 void MacroAssembler::round_to(Register reg, int modulus) {
2823   addptr(reg, modulus - 1);
2824   andptr(reg, -modulus);
2825 }
2826 
2827 void MacroAssembler::save_rax(Register tmp) {
2828   if (tmp == noreg) push(rax);
2829   else if (tmp != rax) mov(tmp, rax);
2830 }
2831 
2832 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
2833   if (at_return) {
2834     // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2835     // we may safely use rsp instead to perform the stack watermark check.
2836     cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
2837     jcc(Assembler::above, slow_path);
2838     return;
2839   }
2840   testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2841   jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2842 }
2843 
2844 // Calls to C land
2845 //
2846 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2847 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2848 // has to be reset to 0. This is required to allow proper stack traversal.
2849 void MacroAssembler::set_last_Java_frame(Register java_thread,
2850                                          Register last_java_sp,
2851                                          Register last_java_fp,
2852                                          address  last_java_pc) {
2853   vzeroupper();
2854   // determine java_thread register
2855   if (!java_thread->is_valid()) {
2856     java_thread = rdi;
2857     get_thread(java_thread);
2858   }
2859   // determine last_java_sp register
2860   if (!last_java_sp->is_valid()) {
2861     last_java_sp = rsp;
2862   }
2863 
2864   // last_java_fp is optional
2865 
2866   if (last_java_fp->is_valid()) {
2867     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2868   }
2869 
2870   // last_java_pc is optional
2871 
2872   if (last_java_pc != NULL) {
2873     lea(Address(java_thread,
2874                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
2875         InternalAddress(last_java_pc));
2876 
2877   }
2878   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2879 }
2880 
2881 void MacroAssembler::shlptr(Register dst, int imm8) {
2882   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
2883 }
2884 
2885 void MacroAssembler::shrptr(Register dst, int imm8) {
2886   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
2887 }
2888 
2889 void MacroAssembler::sign_extend_byte(Register reg) {
2890   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
2891     movsbl(reg, reg); // movsxb
2892   } else {
2893     shll(reg, 24);
2894     sarl(reg, 24);
2895   }
2896 }
2897 
2898 void MacroAssembler::sign_extend_short(Register reg) {
2899   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2900     movswl(reg, reg); // movsxw
2901   } else {
2902     shll(reg, 16);
2903     sarl(reg, 16);
2904   }
2905 }
2906 
2907 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2908   assert(reachable(src), "Address should be reachable");
2909   testl(dst, as_Address(src));
2910 }
2911 
2912 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2913   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2914   Assembler::pcmpeqb(dst, src);
2915 }
2916 
2917 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2918   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2919   Assembler::pcmpeqw(dst, src);
2920 }
2921 
2922 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2923   assert((dst->encoding() < 16),"XMM register should be 0-15");
2924   Assembler::pcmpestri(dst, src, imm8);
2925 }
2926 
2927 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2928   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2929   Assembler::pcmpestri(dst, src, imm8);
2930 }
2931 
2932 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2933   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2934   Assembler::pmovzxbw(dst, src);
2935 }
2936 
2937 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2938   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2939   Assembler::pmovzxbw(dst, src);
2940 }
2941 
2942 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2943   assert((src->encoding() < 16),"XMM register should be 0-15");
2944   Assembler::pmovmskb(dst, src);
2945 }
2946 
2947 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2948   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2949   Assembler::ptest(dst, src);
2950 }
2951 
2952 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
2953   if (reachable(src)) {
2954     Assembler::sqrtsd(dst, as_Address(src));
2955   } else {
2956     lea(rscratch1, src);
2957     Assembler::sqrtsd(dst, Address(rscratch1, 0));
2958   }
2959 }
2960 
2961 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
2962   if (reachable(src)) {
2963     Assembler::sqrtss(dst, as_Address(src));
2964   } else {
2965     lea(rscratch1, src);
2966     Assembler::sqrtss(dst, Address(rscratch1, 0));
2967   }
2968 }
2969 
2970 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
2971   if (reachable(src)) {
2972     Assembler::subsd(dst, as_Address(src));
2973   } else {
2974     lea(rscratch1, src);
2975     Assembler::subsd(dst, Address(rscratch1, 0));
2976   }
2977 }
2978 
2979 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
2980   if (reachable(src)) {
2981     Assembler::roundsd(dst, as_Address(src), rmode);
2982   } else {
2983     lea(scratch_reg, src);
2984     Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
2985   }
2986 }
2987 
2988 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
2989   if (reachable(src)) {
2990     Assembler::subss(dst, as_Address(src));
2991   } else {
2992     lea(rscratch1, src);
2993     Assembler::subss(dst, Address(rscratch1, 0));
2994   }
2995 }
2996 
2997 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
2998   if (reachable(src)) {
2999     Assembler::ucomisd(dst, as_Address(src));
3000   } else {
3001     lea(rscratch1, src);
3002     Assembler::ucomisd(dst, Address(rscratch1, 0));
3003   }
3004 }
3005 
3006 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3007   if (reachable(src)) {
3008     Assembler::ucomiss(dst, as_Address(src));
3009   } else {
3010     lea(rscratch1, src);
3011     Assembler::ucomiss(dst, Address(rscratch1, 0));
3012   }
3013 }
3014 
3015 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3016   // Used in sign-bit flipping with aligned address.
3017   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3018   if (reachable(src)) {
3019     Assembler::xorpd(dst, as_Address(src));
3020   } else {
3021     lea(scratch_reg, src);
3022     Assembler::xorpd(dst, Address(scratch_reg, 0));
3023   }
3024 }
3025 
3026 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3027   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3028     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3029   }
3030   else {
3031     Assembler::xorpd(dst, src);
3032   }
3033 }
3034 
3035 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3036   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3037     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3038   } else {
3039     Assembler::xorps(dst, src);
3040   }
3041 }
3042 
3043 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3044   // Used in sign-bit flipping with aligned address.
3045   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3046   if (reachable(src)) {
3047     Assembler::xorps(dst, as_Address(src));
3048   } else {
3049     lea(scratch_reg, src);
3050     Assembler::xorps(dst, Address(scratch_reg, 0));
3051   }
3052 }
3053 
3054 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3055   // Used in sign-bit flipping with aligned address.
3056   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3057   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3058   if (reachable(src)) {
3059     Assembler::pshufb(dst, as_Address(src));
3060   } else {
3061     lea(rscratch1, src);
3062     Assembler::pshufb(dst, Address(rscratch1, 0));
3063   }
3064 }
3065 
3066 // AVX 3-operands instructions
3067 
3068 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3069   if (reachable(src)) {
3070     vaddsd(dst, nds, as_Address(src));
3071   } else {
3072     lea(rscratch1, src);
3073     vaddsd(dst, nds, Address(rscratch1, 0));
3074   }
3075 }
3076 
3077 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3078   if (reachable(src)) {
3079     vaddss(dst, nds, as_Address(src));
3080   } else {
3081     lea(rscratch1, src);
3082     vaddss(dst, nds, Address(rscratch1, 0));
3083   }
3084 }
3085 
3086 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3087   assert(UseAVX > 0, "requires some form of AVX");
3088   if (reachable(src)) {
3089     Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3090   } else {
3091     lea(rscratch, src);
3092     Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3093   }
3094 }
3095 
3096 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3097   assert(UseAVX > 0, "requires some form of AVX");
3098   if (reachable(src)) {
3099     Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3100   } else {
3101     lea(rscratch, src);
3102     Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3103   }
3104 }
3105 
3106 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3107   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3108   vandps(dst, nds, negate_field, vector_len);
3109 }
3110 
3111 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3112   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3113   vandpd(dst, nds, negate_field, vector_len);
3114 }
3115 
3116 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3117   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3118   Assembler::vpaddb(dst, nds, src, vector_len);
3119 }
3120 
3121 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3122   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3123   Assembler::vpaddb(dst, nds, src, vector_len);
3124 }
3125 
3126 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3127   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3128   Assembler::vpaddw(dst, nds, src, vector_len);
3129 }
3130 
3131 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3132   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3133   Assembler::vpaddw(dst, nds, src, vector_len);
3134 }
3135 
3136 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3137   if (reachable(src)) {
3138     Assembler::vpand(dst, nds, as_Address(src), vector_len);
3139   } else {
3140     lea(scratch_reg, src);
3141     Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3142   }
3143 }
3144 
3145 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3146   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3147   Assembler::vpbroadcastw(dst, src, vector_len);
3148 }
3149 
3150 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3151   if (reachable(src)) {
3152     Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3153   } else {
3154     lea(rscratch, src);
3155     Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3156   }
3157 }
3158 
3159 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3160   if (reachable(src)) {
3161     Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3162   } else {
3163     lea(rscratch, src);
3164     Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3165   }
3166 }
3167 
3168 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3169   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3170   Assembler::vpcmpeqb(dst, nds, src, vector_len);
3171 }
3172 
3173 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3174   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3175   Assembler::vpcmpeqw(dst, nds, src, vector_len);
3176 }
3177 
3178 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds,
3179                                AddressLiteral src, int vector_len, Register scratch_reg) {
3180   if (reachable(src)) {
3181     Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3182   } else {
3183     lea(scratch_reg, src);
3184     Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len);
3185   }
3186 }
3187 
3188 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3189                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3190   if (reachable(src)) {
3191     Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3192   } else {
3193     lea(scratch_reg, src);
3194     Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3195   }
3196 }
3197 
3198 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3199                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3200   if (reachable(src)) {
3201     Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3202   } else {
3203     lea(scratch_reg, src);
3204     Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3205   }
3206 }
3207 
3208 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3209                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3210   if (reachable(src)) {
3211     Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3212   } else {
3213     lea(scratch_reg, src);
3214     Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3215   }
3216 }
3217 
3218 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3219                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3220   if (reachable(src)) {
3221     Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3222   } else {
3223     lea(scratch_reg, src);
3224     Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3225   }
3226 }
3227 
3228 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3229   if (width == Assembler::Q) {
3230     Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3231   } else {
3232     Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3233   }
3234 }
3235 
3236 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3237   int eq_cond_enc = 0x29;
3238   int gt_cond_enc = 0x37;
3239   if (width != Assembler::Q) {
3240     eq_cond_enc = 0x74 + width;
3241     gt_cond_enc = 0x64 + width;
3242   }
3243   switch (cond) {
3244   case eq:
3245     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3246     break;
3247   case neq:
3248     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3249     vallones(xtmp, vector_len);
3250     vpxor(dst, xtmp, dst, vector_len);
3251     break;
3252   case le:
3253     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3254     vallones(xtmp, vector_len);
3255     vpxor(dst, xtmp, dst, vector_len);
3256     break;
3257   case nlt:
3258     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3259     vallones(xtmp, vector_len);
3260     vpxor(dst, xtmp, dst, vector_len);
3261     break;
3262   case lt:
3263     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3264     break;
3265   case nle:
3266     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3267     break;
3268   default:
3269     assert(false, "Should not reach here");
3270   }
3271 }
3272 
3273 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3274   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3275   Assembler::vpmovzxbw(dst, src, vector_len);
3276 }
3277 
3278 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3279   assert((src->encoding() < 16),"XMM register should be 0-15");
3280   Assembler::vpmovmskb(dst, src, vector_len);
3281 }
3282 
3283 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3284   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3285   Assembler::vpmullw(dst, nds, src, vector_len);
3286 }
3287 
3288 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3289   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3290   Assembler::vpmullw(dst, nds, src, vector_len);
3291 }
3292 
3293 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3294   assert((UseAVX > 0), "AVX support is needed");
3295   if (reachable(src)) {
3296     Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3297   } else {
3298     lea(scratch_reg, src);
3299     Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
3300   }
3301 }
3302 
3303 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3304   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3305   Assembler::vpsubb(dst, nds, src, vector_len);
3306 }
3307 
3308 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3309   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3310   Assembler::vpsubb(dst, nds, src, vector_len);
3311 }
3312 
3313 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3314   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3315   Assembler::vpsubw(dst, nds, src, vector_len);
3316 }
3317 
3318 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3319   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3320   Assembler::vpsubw(dst, nds, src, vector_len);
3321 }
3322 
3323 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3324   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3325   Assembler::vpsraw(dst, nds, shift, vector_len);
3326 }
3327 
3328 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3329   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3330   Assembler::vpsraw(dst, nds, shift, vector_len);
3331 }
3332 
3333 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3334   assert(UseAVX > 2,"");
3335   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3336      vector_len = 2;
3337   }
3338   Assembler::evpsraq(dst, nds, shift, vector_len);
3339 }
3340 
3341 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3342   assert(UseAVX > 2,"");
3343   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3344      vector_len = 2;
3345   }
3346   Assembler::evpsraq(dst, nds, shift, vector_len);
3347 }
3348 
3349 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3350   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3351   Assembler::vpsrlw(dst, nds, shift, vector_len);
3352 }
3353 
3354 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3355   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3356   Assembler::vpsrlw(dst, nds, shift, vector_len);
3357 }
3358 
3359 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3360   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3361   Assembler::vpsllw(dst, nds, shift, vector_len);
3362 }
3363 
3364 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3365   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3366   Assembler::vpsllw(dst, nds, shift, vector_len);
3367 }
3368 
3369 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3370   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3371   Assembler::vptest(dst, src);
3372 }
3373 
3374 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3375   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3376   Assembler::punpcklbw(dst, src);
3377 }
3378 
3379 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3380   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3381   Assembler::pshufd(dst, src, mode);
3382 }
3383 
3384 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3385   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3386   Assembler::pshuflw(dst, src, mode);
3387 }
3388 
3389 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3390   if (reachable(src)) {
3391     vandpd(dst, nds, as_Address(src), vector_len);
3392   } else {
3393     lea(scratch_reg, src);
3394     vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3395   }
3396 }
3397 
3398 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3399   if (reachable(src)) {
3400     vandps(dst, nds, as_Address(src), vector_len);
3401   } else {
3402     lea(scratch_reg, src);
3403     vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3404   }
3405 }
3406 
3407 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3408                             bool merge, int vector_len, Register scratch_reg) {
3409   if (reachable(src)) {
3410     Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3411   } else {
3412     lea(scratch_reg, src);
3413     Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len);
3414   }
3415 }
3416 
3417 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3418   if (reachable(src)) {
3419     vdivsd(dst, nds, as_Address(src));
3420   } else {
3421     lea(rscratch1, src);
3422     vdivsd(dst, nds, Address(rscratch1, 0));
3423   }
3424 }
3425 
3426 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3427   if (reachable(src)) {
3428     vdivss(dst, nds, as_Address(src));
3429   } else {
3430     lea(rscratch1, src);
3431     vdivss(dst, nds, Address(rscratch1, 0));
3432   }
3433 }
3434 
3435 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3436   if (reachable(src)) {
3437     vmulsd(dst, nds, as_Address(src));
3438   } else {
3439     lea(rscratch1, src);
3440     vmulsd(dst, nds, Address(rscratch1, 0));
3441   }
3442 }
3443 
3444 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3445   if (reachable(src)) {
3446     vmulss(dst, nds, as_Address(src));
3447   } else {
3448     lea(rscratch1, src);
3449     vmulss(dst, nds, Address(rscratch1, 0));
3450   }
3451 }
3452 
3453 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3454   if (reachable(src)) {
3455     vsubsd(dst, nds, as_Address(src));
3456   } else {
3457     lea(rscratch1, src);
3458     vsubsd(dst, nds, Address(rscratch1, 0));
3459   }
3460 }
3461 
3462 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3463   if (reachable(src)) {
3464     vsubss(dst, nds, as_Address(src));
3465   } else {
3466     lea(rscratch1, src);
3467     vsubss(dst, nds, Address(rscratch1, 0));
3468   }
3469 }
3470 
3471 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3472   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3473   vxorps(dst, nds, src, Assembler::AVX_128bit);
3474 }
3475 
3476 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3477   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3478   vxorpd(dst, nds, src, Assembler::AVX_128bit);
3479 }
3480 
3481 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3482   if (reachable(src)) {
3483     vxorpd(dst, nds, as_Address(src), vector_len);
3484   } else {
3485     lea(scratch_reg, src);
3486     vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
3487   }
3488 }
3489 
3490 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3491   if (reachable(src)) {
3492     vxorps(dst, nds, as_Address(src), vector_len);
3493   } else {
3494     lea(scratch_reg, src);
3495     vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
3496   }
3497 }
3498 
3499 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3500   if (UseAVX > 1 || (vector_len < 1)) {
3501     if (reachable(src)) {
3502       Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3503     } else {
3504       lea(scratch_reg, src);
3505       Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
3506     }
3507   }
3508   else {
3509     MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
3510   }
3511 }
3512 
3513 void MacroAssembler::vpermd(XMMRegister dst,  XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3514   if (reachable(src)) {
3515     Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3516   } else {
3517     lea(scratch_reg, src);
3518     Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len);
3519   }
3520 }
3521 
3522 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
3523   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
3524   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
3525   // The inverted mask is sign-extended
3526   andptr(possibly_jweak, inverted_jweak_mask);
3527 }
3528 
3529 void MacroAssembler::resolve_jobject(Register value,
3530                                      Register thread,
3531                                      Register tmp) {
3532   assert_different_registers(value, thread, tmp);
3533   Label done, not_weak;
3534   testptr(value, value);
3535   jcc(Assembler::zero, done);                // Use NULL as-is.
3536   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
3537   jcc(Assembler::zero, not_weak);
3538   // Resolve jweak.
3539   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3540                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
3541   verify_oop(value);
3542   jmp(done);
3543   bind(not_weak);
3544   // Resolve (untagged) jobject.
3545   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
3546   verify_oop(value);
3547   bind(done);
3548 }
3549 
3550 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3551   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3552 }
3553 
3554 // Force generation of a 4 byte immediate value even if it fits into 8bit
3555 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3556   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3557 }
3558 
3559 void MacroAssembler::subptr(Register dst, Register src) {
3560   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3561 }
3562 
3563 // C++ bool manipulation
3564 void MacroAssembler::testbool(Register dst) {
3565   if(sizeof(bool) == 1)
3566     testb(dst, 0xff);
3567   else if(sizeof(bool) == 2) {
3568     // testw implementation needed for two byte bools
3569     ShouldNotReachHere();
3570   } else if(sizeof(bool) == 4)
3571     testl(dst, dst);
3572   else
3573     // unsupported
3574     ShouldNotReachHere();
3575 }
3576 
3577 void MacroAssembler::testptr(Register dst, Register src) {
3578   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3579 }
3580 
3581 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3582 void MacroAssembler::tlab_allocate(Register thread, Register obj,
3583                                    Register var_size_in_bytes,
3584                                    int con_size_in_bytes,
3585                                    Register t1,
3586                                    Register t2,
3587                                    Label& slow_case) {
3588   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3589   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3590 }
3591 
3592 RegSet MacroAssembler::call_clobbered_gp_registers() {
3593   RegSet regs;
3594 #ifdef _LP64
3595   regs += RegSet::of(rax, rcx, rdx);
3596 #ifndef WINDOWS
3597   regs += RegSet::of(rsi, rdi);
3598 #endif
3599   regs += RegSet::range(r8, r11);
3600 #else
3601   regs += RegSet::of(rax, rcx, rdx);
3602 #endif
3603   return regs;
3604 }
3605 
3606 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3607   int num_xmm_registers = XMMRegisterImpl::available_xmm_registers();
3608 #if defined(WINDOWS) && defined(_LP64)
3609   XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3610   if (num_xmm_registers > 16) {
3611      result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3612   }
3613   return result;
3614 #else
3615   return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3616 #endif
3617 }
3618 
3619 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
3620 
3621 #ifndef _LP64
3622 static bool use_x87_registers() { return UseSSE < 2; }
3623 #endif
3624 static bool use_xmm_registers() { return UseSSE >= 1; }
3625 
3626 // C1 only ever uses the first double/float of the XMM register.
3627 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
3628 
3629 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3630   if (UseSSE == 1) {
3631     masm->movflt(Address(rsp, offset), reg);
3632   } else {
3633     masm->movdbl(Address(rsp, offset), reg);
3634   }
3635 }
3636 
3637 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3638   if (UseSSE == 1) {
3639     masm->movflt(reg, Address(rsp, offset));
3640   } else {
3641     masm->movdbl(reg, Address(rsp, offset));
3642   }
3643 }
3644 
3645 int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers, bool save_fpu,
3646                            int& gp_area_size, int& fp_area_size, int& xmm_area_size) {
3647 
3648   gp_area_size = align_up(gp_registers.size() * RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size,
3649                          StackAlignmentInBytes);
3650 #ifdef _LP64
3651   fp_area_size = 0;
3652 #else
3653   fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
3654 #endif
3655   xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
3656 
3657   return gp_area_size + fp_area_size + xmm_area_size;
3658 }
3659 
3660 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3661   block_comment("push_call_clobbered_registers start");
3662   // Regular registers
3663   RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3664 
3665   int gp_area_size;
3666   int fp_area_size;
3667   int xmm_area_size;
3668   int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3669                                                gp_area_size, fp_area_size, xmm_area_size);
3670   subptr(rsp, total_save_size);
3671 
3672   push_set(gp_registers_to_push, 0);
3673 
3674 #ifndef _LP64
3675   if (save_fpu && use_x87_registers()) {
3676     fnsave(Address(rsp, gp_area_size));
3677     fwait();
3678   }
3679 #endif
3680   if (save_fpu && use_xmm_registers()) {
3681     push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
3682   }
3683 
3684   block_comment("push_call_clobbered_registers end");
3685 }
3686 
3687 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3688   block_comment("pop_call_clobbered_registers start");
3689 
3690   RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3691 
3692   int gp_area_size;
3693   int fp_area_size;
3694   int xmm_area_size;
3695   int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3696                                                gp_area_size, fp_area_size, xmm_area_size);
3697 
3698   if (restore_fpu && use_xmm_registers()) {
3699     pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
3700   }
3701 #ifndef _LP64
3702   if (restore_fpu && use_x87_registers()) {
3703     frstor(Address(rsp, gp_area_size));
3704   }
3705 #endif
3706 
3707   pop_set(gp_registers_to_pop, 0);
3708 
3709   addptr(rsp, total_save_size);
3710 
3711   vzeroupper();
3712 
3713   block_comment("pop_call_clobbered_registers end");
3714 }
3715 
3716 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3717   assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3718   int spill_offset = offset;
3719 
3720   for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3721     save_xmm_register(this, spill_offset, *it);
3722     spill_offset += xmm_save_size();
3723   }
3724 }
3725 
3726 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3727   int restore_size = set.size() * xmm_save_size();
3728   assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3729 
3730   int restore_offset = offset + restore_size - xmm_save_size();
3731 
3732   for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3733     restore_xmm_register(this, restore_offset, *it);
3734     restore_offset -= xmm_save_size();
3735   }
3736 }
3737 
3738 void MacroAssembler::push_set(RegSet set, int offset) {
3739   int spill_offset;
3740   if (offset == -1) {
3741     int register_push_size = set.size() * RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size;
3742     int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3743     subptr(rsp, aligned_size);
3744     spill_offset = 0;
3745   } else {
3746     spill_offset = offset;
3747   }
3748 
3749   for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3750     movptr(Address(rsp, spill_offset), *it);
3751     spill_offset += RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size;
3752   }
3753 }
3754 
3755 void MacroAssembler::pop_set(RegSet set, int offset) {
3756 
3757   int gp_reg_size = RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size;
3758   int restore_size = set.size() * gp_reg_size;
3759   int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3760 
3761   int restore_offset;
3762   if (offset == -1) {
3763     restore_offset = restore_size - gp_reg_size;
3764   } else {
3765     restore_offset = offset + restore_size - gp_reg_size;
3766   }
3767   for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3768     movptr(*it, Address(rsp, restore_offset));
3769     restore_offset -= gp_reg_size;
3770   }
3771 
3772   if (offset == -1) {
3773     addptr(rsp, aligned_size);
3774   }
3775 }
3776 
3777 // Defines obj, preserves var_size_in_bytes
3778 void MacroAssembler::eden_allocate(Register thread, Register obj,
3779                                    Register var_size_in_bytes,
3780                                    int con_size_in_bytes,
3781                                    Register t1,
3782                                    Label& slow_case) {
3783   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3784   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
3785 }
3786 
3787 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3788 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3789   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3790   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3791   Label done;
3792 
3793   testptr(length_in_bytes, length_in_bytes);
3794   jcc(Assembler::zero, done);
3795 
3796   // initialize topmost word, divide index by 2, check if odd and test if zero
3797   // note: for the remaining code to work, index must be a multiple of BytesPerWord
3798 #ifdef ASSERT
3799   {
3800     Label L;
3801     testptr(length_in_bytes, BytesPerWord - 1);
3802     jcc(Assembler::zero, L);
3803     stop("length must be a multiple of BytesPerWord");
3804     bind(L);
3805   }
3806 #endif
3807   Register index = length_in_bytes;
3808   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
3809   if (UseIncDec) {
3810     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
3811   } else {
3812     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
3813     shrptr(index, 1);
3814   }
3815 #ifndef _LP64
3816   // index could have not been a multiple of 8 (i.e., bit 2 was set)
3817   {
3818     Label even;
3819     // note: if index was a multiple of 8, then it cannot
3820     //       be 0 now otherwise it must have been 0 before
3821     //       => if it is even, we don't need to check for 0 again
3822     jcc(Assembler::carryClear, even);
3823     // clear topmost word (no jump would be needed if conditional assignment worked here)
3824     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
3825     // index could be 0 now, must check again
3826     jcc(Assembler::zero, done);
3827     bind(even);
3828   }
3829 #endif // !_LP64
3830   // initialize remaining object fields: index is a multiple of 2 now
3831   {
3832     Label loop;
3833     bind(loop);
3834     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3835     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
3836     decrement(index);
3837     jcc(Assembler::notZero, loop);
3838   }
3839 
3840   bind(done);
3841 }
3842 
3843 // Look up the method for a megamorphic invokeinterface call.
3844 // The target method is determined by <intf_klass, itable_index>.
3845 // The receiver klass is in recv_klass.
3846 // On success, the result will be in method_result, and execution falls through.
3847 // On failure, execution transfers to the given label.
3848 void MacroAssembler::lookup_interface_method(Register recv_klass,
3849                                              Register intf_klass,
3850                                              RegisterOrConstant itable_index,
3851                                              Register method_result,
3852                                              Register scan_temp,
3853                                              Label& L_no_such_interface,
3854                                              bool return_method) {
3855   assert_different_registers(recv_klass, intf_klass, scan_temp);
3856   assert_different_registers(method_result, intf_klass, scan_temp);
3857   assert(recv_klass != method_result || !return_method,
3858          "recv_klass can be destroyed when method isn't needed");
3859 
3860   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3861          "caller must use same register for non-constant itable index as for method");
3862 
3863   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3864   int vtable_base = in_bytes(Klass::vtable_start_offset());
3865   int itentry_off = itableMethodEntry::method_offset_in_bytes();
3866   int scan_step   = itableOffsetEntry::size() * wordSize;
3867   int vte_size    = vtableEntry::size_in_bytes();
3868   Address::ScaleFactor times_vte_scale = Address::times_ptr;
3869   assert(vte_size == wordSize, "else adjust times_vte_scale");
3870 
3871   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3872 
3873   // %%% Could store the aligned, prescaled offset in the klassoop.
3874   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3875 
3876   if (return_method) {
3877     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3878     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3879     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3880   }
3881 
3882   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3883   //   if (scan->interface() == intf) {
3884   //     result = (klass + scan->offset() + itable_index);
3885   //   }
3886   // }
3887   Label search, found_method;
3888 
3889   for (int peel = 1; peel >= 0; peel--) {
3890     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
3891     cmpptr(intf_klass, method_result);
3892 
3893     if (peel) {
3894       jccb(Assembler::equal, found_method);
3895     } else {
3896       jccb(Assembler::notEqual, search);
3897       // (invert the test to fall through to found_method...)
3898     }
3899 
3900     if (!peel)  break;
3901 
3902     bind(search);
3903 
3904     // Check that the previous entry is non-null.  A null entry means that
3905     // the receiver class doesn't implement the interface, and wasn't the
3906     // same as when the caller was compiled.
3907     testptr(method_result, method_result);
3908     jcc(Assembler::zero, L_no_such_interface);
3909     addptr(scan_temp, scan_step);
3910   }
3911 
3912   bind(found_method);
3913 
3914   if (return_method) {
3915     // Got a hit.
3916     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
3917     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3918   }
3919 }
3920 
3921 
3922 // virtual method calling
3923 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3924                                            RegisterOrConstant vtable_index,
3925                                            Register method_result) {
3926   const int base = in_bytes(Klass::vtable_start_offset());
3927   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3928   Address vtable_entry_addr(recv_klass,
3929                             vtable_index, Address::times_ptr,
3930                             base + vtableEntry::method_offset_in_bytes());
3931   movptr(method_result, vtable_entry_addr);
3932 }
3933 
3934 
3935 void MacroAssembler::check_klass_subtype(Register sub_klass,
3936                            Register super_klass,
3937                            Register temp_reg,
3938                            Label& L_success) {
3939   Label L_failure;
3940   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
3941   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3942   bind(L_failure);
3943 }
3944 
3945 
3946 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3947                                                    Register super_klass,
3948                                                    Register temp_reg,
3949                                                    Label* L_success,
3950                                                    Label* L_failure,
3951                                                    Label* L_slow_path,
3952                                         RegisterOrConstant super_check_offset) {
3953   assert_different_registers(sub_klass, super_klass, temp_reg);
3954   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3955   if (super_check_offset.is_register()) {
3956     assert_different_registers(sub_klass, super_klass,
3957                                super_check_offset.as_register());
3958   } else if (must_load_sco) {
3959     assert(temp_reg != noreg, "supply either a temp or a register offset");
3960   }
3961 
3962   Label L_fallthrough;
3963   int label_nulls = 0;
3964   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3965   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3966   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3967   assert(label_nulls <= 1, "at most one NULL in the batch");
3968 
3969   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3970   int sco_offset = in_bytes(Klass::super_check_offset_offset());
3971   Address super_check_offset_addr(super_klass, sco_offset);
3972 
3973   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3974   // range of a jccb.  If this routine grows larger, reconsider at
3975   // least some of these.
3976 #define local_jcc(assembler_cond, label)                                \
3977   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
3978   else                             jcc( assembler_cond, label) /*omit semi*/
3979 
3980   // Hacked jmp, which may only be used just before L_fallthrough.
3981 #define final_jmp(label)                                                \
3982   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
3983   else                            jmp(label)                /*omit semi*/
3984 
3985   // If the pointers are equal, we are done (e.g., String[] elements).
3986   // This self-check enables sharing of secondary supertype arrays among
3987   // non-primary types such as array-of-interface.  Otherwise, each such
3988   // type would need its own customized SSA.
3989   // We move this check to the front of the fast path because many
3990   // type checks are in fact trivially successful in this manner,
3991   // so we get a nicely predicted branch right at the start of the check.
3992   cmpptr(sub_klass, super_klass);
3993   local_jcc(Assembler::equal, *L_success);
3994 
3995   // Check the supertype display:
3996   if (must_load_sco) {
3997     // Positive movl does right thing on LP64.
3998     movl(temp_reg, super_check_offset_addr);
3999     super_check_offset = RegisterOrConstant(temp_reg);
4000   }
4001   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4002   cmpptr(super_klass, super_check_addr); // load displayed supertype
4003 
4004   // This check has worked decisively for primary supers.
4005   // Secondary supers are sought in the super_cache ('super_cache_addr').
4006   // (Secondary supers are interfaces and very deeply nested subtypes.)
4007   // This works in the same check above because of a tricky aliasing
4008   // between the super_cache and the primary super display elements.
4009   // (The 'super_check_addr' can address either, as the case requires.)
4010   // Note that the cache is updated below if it does not help us find
4011   // what we need immediately.
4012   // So if it was a primary super, we can just fail immediately.
4013   // Otherwise, it's the slow path for us (no success at this point).
4014 
4015   if (super_check_offset.is_register()) {
4016     local_jcc(Assembler::equal, *L_success);
4017     cmpl(super_check_offset.as_register(), sc_offset);
4018     if (L_failure == &L_fallthrough) {
4019       local_jcc(Assembler::equal, *L_slow_path);
4020     } else {
4021       local_jcc(Assembler::notEqual, *L_failure);
4022       final_jmp(*L_slow_path);
4023     }
4024   } else if (super_check_offset.as_constant() == sc_offset) {
4025     // Need a slow path; fast failure is impossible.
4026     if (L_slow_path == &L_fallthrough) {
4027       local_jcc(Assembler::equal, *L_success);
4028     } else {
4029       local_jcc(Assembler::notEqual, *L_slow_path);
4030       final_jmp(*L_success);
4031     }
4032   } else {
4033     // No slow path; it's a fast decision.
4034     if (L_failure == &L_fallthrough) {
4035       local_jcc(Assembler::equal, *L_success);
4036     } else {
4037       local_jcc(Assembler::notEqual, *L_failure);
4038       final_jmp(*L_success);
4039     }
4040   }
4041 
4042   bind(L_fallthrough);
4043 
4044 #undef local_jcc
4045 #undef final_jmp
4046 }
4047 
4048 
4049 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4050                                                    Register super_klass,
4051                                                    Register temp_reg,
4052                                                    Register temp2_reg,
4053                                                    Label* L_success,
4054                                                    Label* L_failure,
4055                                                    bool set_cond_codes) {
4056   assert_different_registers(sub_klass, super_klass, temp_reg);
4057   if (temp2_reg != noreg)
4058     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4059 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4060 
4061   Label L_fallthrough;
4062   int label_nulls = 0;
4063   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4064   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4065   assert(label_nulls <= 1, "at most one NULL in the batch");
4066 
4067   // a couple of useful fields in sub_klass:
4068   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4069   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4070   Address secondary_supers_addr(sub_klass, ss_offset);
4071   Address super_cache_addr(     sub_klass, sc_offset);
4072 
4073   // Do a linear scan of the secondary super-klass chain.
4074   // This code is rarely used, so simplicity is a virtue here.
4075   // The repne_scan instruction uses fixed registers, which we must spill.
4076   // Don't worry too much about pre-existing connections with the input regs.
4077 
4078   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4079   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4080 
4081   // Get super_klass value into rax (even if it was in rdi or rcx).
4082   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4083   if (super_klass != rax || UseCompressedOops) {
4084     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4085     mov(rax, super_klass);
4086   }
4087   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4088   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4089 
4090 #ifndef PRODUCT
4091   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4092   ExternalAddress pst_counter_addr((address) pst_counter);
4093   NOT_LP64(  incrementl(pst_counter_addr) );
4094   LP64_ONLY( lea(rcx, pst_counter_addr) );
4095   LP64_ONLY( incrementl(Address(rcx, 0)) );
4096 #endif //PRODUCT
4097 
4098   // We will consult the secondary-super array.
4099   movptr(rdi, secondary_supers_addr);
4100   // Load the array length.  (Positive movl does right thing on LP64.)
4101   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4102   // Skip to start of data.
4103   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4104 
4105   // Scan RCX words at [RDI] for an occurrence of RAX.
4106   // Set NZ/Z based on last compare.
4107   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4108   // not change flags (only scas instruction which is repeated sets flags).
4109   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4110 
4111     testptr(rax,rax); // Set Z = 0
4112     repne_scan();
4113 
4114   // Unspill the temp. registers:
4115   if (pushed_rdi)  pop(rdi);
4116   if (pushed_rcx)  pop(rcx);
4117   if (pushed_rax)  pop(rax);
4118 
4119   if (set_cond_codes) {
4120     // Special hack for the AD files:  rdi is guaranteed non-zero.
4121     assert(!pushed_rdi, "rdi must be left non-NULL");
4122     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4123   }
4124 
4125   if (L_failure == &L_fallthrough)
4126         jccb(Assembler::notEqual, *L_failure);
4127   else  jcc(Assembler::notEqual, *L_failure);
4128 
4129   // Success.  Cache the super we found and proceed in triumph.
4130   movptr(super_cache_addr, super_klass);
4131 
4132   if (L_success != &L_fallthrough) {
4133     jmp(*L_success);
4134   }
4135 
4136 #undef IS_A_TEMP
4137 
4138   bind(L_fallthrough);
4139 }
4140 
4141 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4142   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4143 
4144   Label L_fallthrough;
4145   if (L_fast_path == NULL) {
4146     L_fast_path = &L_fallthrough;
4147   } else if (L_slow_path == NULL) {
4148     L_slow_path = &L_fallthrough;
4149   }
4150 
4151   // Fast path check: class is fully initialized
4152   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4153   jcc(Assembler::equal, *L_fast_path);
4154 
4155   // Fast path check: current thread is initializer thread
4156   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4157   if (L_slow_path == &L_fallthrough) {
4158     jcc(Assembler::equal, *L_fast_path);
4159     bind(*L_slow_path);
4160   } else if (L_fast_path == &L_fallthrough) {
4161     jcc(Assembler::notEqual, *L_slow_path);
4162     bind(*L_fast_path);
4163   } else {
4164     Unimplemented();
4165   }
4166 }
4167 
4168 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4169   if (VM_Version::supports_cmov()) {
4170     cmovl(cc, dst, src);
4171   } else {
4172     Label L;
4173     jccb(negate_condition(cc), L);
4174     movl(dst, src);
4175     bind(L);
4176   }
4177 }
4178 
4179 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4180   if (VM_Version::supports_cmov()) {
4181     cmovl(cc, dst, src);
4182   } else {
4183     Label L;
4184     jccb(negate_condition(cc), L);
4185     movl(dst, src);
4186     bind(L);
4187   }
4188 }
4189 
4190 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4191   if (!VerifyOops) return;
4192 
4193   // Pass register number to verify_oop_subroutine
4194   const char* b = NULL;
4195   {
4196     ResourceMark rm;
4197     stringStream ss;
4198     ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4199     b = code_string(ss.as_string());
4200   }
4201   BLOCK_COMMENT("verify_oop {");
4202 #ifdef _LP64
4203   push(rscratch1);                    // save r10, trashed by movptr()
4204 #endif
4205   push(rax);                          // save rax,
4206   push(reg);                          // pass register argument
4207   ExternalAddress buffer((address) b);
4208   // avoid using pushptr, as it modifies scratch registers
4209   // and our contract is not to modify anything
4210   movptr(rax, buffer.addr());
4211   push(rax);
4212   // call indirectly to solve generation ordering problem
4213   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4214   call(rax);
4215   // Caller pops the arguments (oop, message) and restores rax, r10
4216   BLOCK_COMMENT("} verify_oop");
4217 }
4218 
4219 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4220   if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4221     vpternlogd(dst, 0xFF, dst, dst, vector_len);
4222   } else {
4223     assert(UseAVX > 0, "");
4224     vpcmpeqb(dst, dst, dst, vector_len);
4225   }
4226 }
4227 
4228 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4229                                          int extra_slot_offset) {
4230   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4231   int stackElementSize = Interpreter::stackElementSize;
4232   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4233 #ifdef ASSERT
4234   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4235   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4236 #endif
4237   Register             scale_reg    = noreg;
4238   Address::ScaleFactor scale_factor = Address::no_scale;
4239   if (arg_slot.is_constant()) {
4240     offset += arg_slot.as_constant() * stackElementSize;
4241   } else {
4242     scale_reg    = arg_slot.as_register();
4243     scale_factor = Address::times(stackElementSize);
4244   }
4245   offset += wordSize;           // return PC is on stack
4246   return Address(rsp, scale_reg, scale_factor, offset);
4247 }
4248 
4249 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4250   if (!VerifyOops) return;
4251 
4252   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4253   // Pass register number to verify_oop_subroutine
4254   const char* b = NULL;
4255   {
4256     ResourceMark rm;
4257     stringStream ss;
4258     ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4259     b = code_string(ss.as_string());
4260   }
4261 #ifdef _LP64
4262   push(rscratch1);                    // save r10, trashed by movptr()
4263 #endif
4264   push(rax);                          // save rax,
4265   // addr may contain rsp so we will have to adjust it based on the push
4266   // we just did (and on 64 bit we do two pushes)
4267   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4268   // stores rax into addr which is backwards of what was intended.
4269   if (addr.uses(rsp)) {
4270     lea(rax, addr);
4271     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4272   } else {
4273     pushptr(addr);
4274   }
4275 
4276   ExternalAddress buffer((address) b);
4277   // pass msg argument
4278   // avoid using pushptr, as it modifies scratch registers
4279   // and our contract is not to modify anything
4280   movptr(rax, buffer.addr());
4281   push(rax);
4282 
4283   // call indirectly to solve generation ordering problem
4284   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4285   call(rax);
4286   // Caller pops the arguments (addr, message) and restores rax, r10.
4287 }
4288 
4289 void MacroAssembler::verify_tlab() {
4290 #ifdef ASSERT
4291   if (UseTLAB && VerifyOops) {
4292     Label next, ok;
4293     Register t1 = rsi;
4294     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4295 
4296     push(t1);
4297     NOT_LP64(push(thread_reg));
4298     NOT_LP64(get_thread(thread_reg));
4299 
4300     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4301     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4302     jcc(Assembler::aboveEqual, next);
4303     STOP("assert(top >= start)");
4304     should_not_reach_here();
4305 
4306     bind(next);
4307     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4308     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4309     jcc(Assembler::aboveEqual, ok);
4310     STOP("assert(top <= end)");
4311     should_not_reach_here();
4312 
4313     bind(ok);
4314     NOT_LP64(pop(thread_reg));
4315     pop(t1);
4316   }
4317 #endif
4318 }
4319 
4320 class ControlWord {
4321  public:
4322   int32_t _value;
4323 
4324   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4325   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4326   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4327   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4328   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4329   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4330   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4331   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4332 
4333   void print() const {
4334     // rounding control
4335     const char* rc;
4336     switch (rounding_control()) {
4337       case 0: rc = "round near"; break;
4338       case 1: rc = "round down"; break;
4339       case 2: rc = "round up  "; break;
4340       case 3: rc = "chop      "; break;
4341       default:
4342         rc = NULL; // silence compiler warnings
4343         fatal("Unknown rounding control: %d", rounding_control());
4344     };
4345     // precision control
4346     const char* pc;
4347     switch (precision_control()) {
4348       case 0: pc = "24 bits "; break;
4349       case 1: pc = "reserved"; break;
4350       case 2: pc = "53 bits "; break;
4351       case 3: pc = "64 bits "; break;
4352       default:
4353         pc = NULL; // silence compiler warnings
4354         fatal("Unknown precision control: %d", precision_control());
4355     };
4356     // flags
4357     char f[9];
4358     f[0] = ' ';
4359     f[1] = ' ';
4360     f[2] = (precision   ()) ? 'P' : 'p';
4361     f[3] = (underflow   ()) ? 'U' : 'u';
4362     f[4] = (overflow    ()) ? 'O' : 'o';
4363     f[5] = (zero_divide ()) ? 'Z' : 'z';
4364     f[6] = (denormalized()) ? 'D' : 'd';
4365     f[7] = (invalid     ()) ? 'I' : 'i';
4366     f[8] = '\x0';
4367     // output
4368     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4369   }
4370 
4371 };
4372 
4373 class StatusWord {
4374  public:
4375   int32_t _value;
4376 
4377   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4378   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4379   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4380   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4381   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4382   int  top() const                     { return  (_value >> 11) & 7      ; }
4383   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4384   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4385   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4386   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4387   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4388   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4389   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4390   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4391 
4392   void print() const {
4393     // condition codes
4394     char c[5];
4395     c[0] = (C3()) ? '3' : '-';
4396     c[1] = (C2()) ? '2' : '-';
4397     c[2] = (C1()) ? '1' : '-';
4398     c[3] = (C0()) ? '0' : '-';
4399     c[4] = '\x0';
4400     // flags
4401     char f[9];
4402     f[0] = (error_status()) ? 'E' : '-';
4403     f[1] = (stack_fault ()) ? 'S' : '-';
4404     f[2] = (precision   ()) ? 'P' : '-';
4405     f[3] = (underflow   ()) ? 'U' : '-';
4406     f[4] = (overflow    ()) ? 'O' : '-';
4407     f[5] = (zero_divide ()) ? 'Z' : '-';
4408     f[6] = (denormalized()) ? 'D' : '-';
4409     f[7] = (invalid     ()) ? 'I' : '-';
4410     f[8] = '\x0';
4411     // output
4412     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4413   }
4414 
4415 };
4416 
4417 class TagWord {
4418  public:
4419   int32_t _value;
4420 
4421   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4422 
4423   void print() const {
4424     printf("%04x", _value & 0xFFFF);
4425   }
4426 
4427 };
4428 
4429 class FPU_Register {
4430  public:
4431   int32_t _m0;
4432   int32_t _m1;
4433   int16_t _ex;
4434 
4435   bool is_indefinite() const           {
4436     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4437   }
4438 
4439   void print() const {
4440     char  sign = (_ex < 0) ? '-' : '+';
4441     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4442     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4443   };
4444 
4445 };
4446 
4447 class FPU_State {
4448  public:
4449   enum {
4450     register_size       = 10,
4451     number_of_registers =  8,
4452     register_mask       =  7
4453   };
4454 
4455   ControlWord  _control_word;
4456   StatusWord   _status_word;
4457   TagWord      _tag_word;
4458   int32_t      _error_offset;
4459   int32_t      _error_selector;
4460   int32_t      _data_offset;
4461   int32_t      _data_selector;
4462   int8_t       _register[register_size * number_of_registers];
4463 
4464   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4465   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4466 
4467   const char* tag_as_string(int tag) const {
4468     switch (tag) {
4469       case 0: return "valid";
4470       case 1: return "zero";
4471       case 2: return "special";
4472       case 3: return "empty";
4473     }
4474     ShouldNotReachHere();
4475     return NULL;
4476   }
4477 
4478   void print() const {
4479     // print computation registers
4480     { int t = _status_word.top();
4481       for (int i = 0; i < number_of_registers; i++) {
4482         int j = (i - t) & register_mask;
4483         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4484         st(j)->print();
4485         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4486       }
4487     }
4488     printf("\n");
4489     // print control registers
4490     printf("ctrl = "); _control_word.print(); printf("\n");
4491     printf("stat = "); _status_word .print(); printf("\n");
4492     printf("tags = "); _tag_word    .print(); printf("\n");
4493   }
4494 
4495 };
4496 
4497 class Flag_Register {
4498  public:
4499   int32_t _value;
4500 
4501   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4502   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4503   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4504   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4505   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4506   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4507   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4508 
4509   void print() const {
4510     // flags
4511     char f[8];
4512     f[0] = (overflow       ()) ? 'O' : '-';
4513     f[1] = (direction      ()) ? 'D' : '-';
4514     f[2] = (sign           ()) ? 'S' : '-';
4515     f[3] = (zero           ()) ? 'Z' : '-';
4516     f[4] = (auxiliary_carry()) ? 'A' : '-';
4517     f[5] = (parity         ()) ? 'P' : '-';
4518     f[6] = (carry          ()) ? 'C' : '-';
4519     f[7] = '\x0';
4520     // output
4521     printf("%08x  flags = %s", _value, f);
4522   }
4523 
4524 };
4525 
4526 class IU_Register {
4527  public:
4528   int32_t _value;
4529 
4530   void print() const {
4531     printf("%08x  %11d", _value, _value);
4532   }
4533 
4534 };
4535 
4536 class IU_State {
4537  public:
4538   Flag_Register _eflags;
4539   IU_Register   _rdi;
4540   IU_Register   _rsi;
4541   IU_Register   _rbp;
4542   IU_Register   _rsp;
4543   IU_Register   _rbx;
4544   IU_Register   _rdx;
4545   IU_Register   _rcx;
4546   IU_Register   _rax;
4547 
4548   void print() const {
4549     // computation registers
4550     printf("rax,  = "); _rax.print(); printf("\n");
4551     printf("rbx,  = "); _rbx.print(); printf("\n");
4552     printf("rcx  = "); _rcx.print(); printf("\n");
4553     printf("rdx  = "); _rdx.print(); printf("\n");
4554     printf("rdi  = "); _rdi.print(); printf("\n");
4555     printf("rsi  = "); _rsi.print(); printf("\n");
4556     printf("rbp,  = "); _rbp.print(); printf("\n");
4557     printf("rsp  = "); _rsp.print(); printf("\n");
4558     printf("\n");
4559     // control registers
4560     printf("flgs = "); _eflags.print(); printf("\n");
4561   }
4562 };
4563 
4564 
4565 class CPU_State {
4566  public:
4567   FPU_State _fpu_state;
4568   IU_State  _iu_state;
4569 
4570   void print() const {
4571     printf("--------------------------------------------------\n");
4572     _iu_state .print();
4573     printf("\n");
4574     _fpu_state.print();
4575     printf("--------------------------------------------------\n");
4576   }
4577 
4578 };
4579 
4580 
4581 static void _print_CPU_state(CPU_State* state) {
4582   state->print();
4583 };
4584 
4585 
4586 void MacroAssembler::print_CPU_state() {
4587   push_CPU_state();
4588   push(rsp);                // pass CPU state
4589   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4590   addptr(rsp, wordSize);       // discard argument
4591   pop_CPU_state();
4592 }
4593 
4594 
4595 #ifndef _LP64
4596 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4597   static int counter = 0;
4598   FPU_State* fs = &state->_fpu_state;
4599   counter++;
4600   // For leaf calls, only verify that the top few elements remain empty.
4601   // We only need 1 empty at the top for C2 code.
4602   if( stack_depth < 0 ) {
4603     if( fs->tag_for_st(7) != 3 ) {
4604       printf("FPR7 not empty\n");
4605       state->print();
4606       assert(false, "error");
4607       return false;
4608     }
4609     return true;                // All other stack states do not matter
4610   }
4611 
4612   assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
4613          "bad FPU control word");
4614 
4615   // compute stack depth
4616   int i = 0;
4617   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4618   int d = i;
4619   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4620   // verify findings
4621   if (i != FPU_State::number_of_registers) {
4622     // stack not contiguous
4623     printf("%s: stack not contiguous at ST%d\n", s, i);
4624     state->print();
4625     assert(false, "error");
4626     return false;
4627   }
4628   // check if computed stack depth corresponds to expected stack depth
4629   if (stack_depth < 0) {
4630     // expected stack depth is -stack_depth or less
4631     if (d > -stack_depth) {
4632       // too many elements on the stack
4633       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4634       state->print();
4635       assert(false, "error");
4636       return false;
4637     }
4638   } else {
4639     // expected stack depth is stack_depth
4640     if (d != stack_depth) {
4641       // wrong stack depth
4642       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4643       state->print();
4644       assert(false, "error");
4645       return false;
4646     }
4647   }
4648   // everything is cool
4649   return true;
4650 }
4651 
4652 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4653   if (!VerifyFPU) return;
4654   push_CPU_state();
4655   push(rsp);                // pass CPU state
4656   ExternalAddress msg((address) s);
4657   // pass message string s
4658   pushptr(msg.addr());
4659   push(stack_depth);        // pass stack depth
4660   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4661   addptr(rsp, 3 * wordSize);   // discard arguments
4662   // check for error
4663   { Label L;
4664     testl(rax, rax);
4665     jcc(Assembler::notZero, L);
4666     int3();                  // break if error condition
4667     bind(L);
4668   }
4669   pop_CPU_state();
4670 }
4671 #endif // _LP64
4672 
4673 void MacroAssembler::restore_cpu_control_state_after_jni() {
4674   // Either restore the MXCSR register after returning from the JNI Call
4675   // or verify that it wasn't changed (with -Xcheck:jni flag).
4676   if (VM_Version::supports_sse()) {
4677     if (RestoreMXCSROnJNICalls) {
4678       ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()));
4679     } else if (CheckJNICalls) {
4680       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4681     }
4682   }
4683   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4684   vzeroupper();
4685 
4686 #ifndef _LP64
4687   // Either restore the x87 floating pointer control word after returning
4688   // from the JNI call or verify that it wasn't changed.
4689   if (CheckJNICalls) {
4690     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4691   }
4692 #endif // _LP64
4693 }
4694 
4695 // ((OopHandle)result).resolve();
4696 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
4697   assert_different_registers(result, tmp);
4698 
4699   // Only 64 bit platforms support GCs that require a tmp register
4700   // Only IN_HEAP loads require a thread_tmp register
4701   // OopHandle::resolve is an indirection like jobject.
4702   access_load_at(T_OBJECT, IN_NATIVE,
4703                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
4704 }
4705 
4706 // ((WeakHandle)result).resolve();
4707 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
4708   assert_different_registers(rresult, rtmp);
4709   Label resolved;
4710 
4711   // A null weak handle resolves to null.
4712   cmpptr(rresult, 0);
4713   jcc(Assembler::equal, resolved);
4714 
4715   // Only 64 bit platforms support GCs that require a tmp register
4716   // Only IN_HEAP loads require a thread_tmp register
4717   // WeakHandle::resolve is an indirection like jweak.
4718   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4719                  rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
4720   bind(resolved);
4721 }
4722 
4723 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
4724   // get mirror
4725   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4726   load_method_holder(mirror, method);
4727   movptr(mirror, Address(mirror, mirror_offset));
4728   resolve_oop_handle(mirror, tmp);
4729 }
4730 
4731 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4732   load_method_holder(rresult, rmethod);
4733   movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4734 }
4735 
4736 void MacroAssembler::load_method_holder(Register holder, Register method) {
4737   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
4738   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
4739   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4740 }
4741 
4742 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
4743   assert_different_registers(src, tmp);
4744   assert_different_registers(dst, tmp);
4745 #ifdef _LP64
4746   if (UseCompressedClassPointers) {
4747     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4748     decode_klass_not_null(dst, tmp);
4749   } else
4750 #endif
4751     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4752 }
4753 
4754 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
4755   assert_different_registers(src, tmp);
4756   assert_different_registers(dst, tmp);
4757 #ifdef _LP64
4758   if (UseCompressedClassPointers) {
4759     encode_klass_not_null(src, tmp);
4760     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4761   } else
4762 #endif
4763     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4764 }
4765 
4766 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
4767                                     Register tmp1, Register thread_tmp) {
4768   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4769   decorators = AccessInternal::decorator_fixup(decorators);
4770   bool as_raw = (decorators & AS_RAW) != 0;
4771   if (as_raw) {
4772     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4773   } else {
4774     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4775   }
4776 }
4777 
4778 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
4779                                      Register tmp1, Register tmp2, Register tmp3) {
4780   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4781   decorators = AccessInternal::decorator_fixup(decorators);
4782   bool as_raw = (decorators & AS_RAW) != 0;
4783   if (as_raw) {
4784     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
4785   } else {
4786     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
4787   }
4788 }
4789 
4790 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4791                                    Register thread_tmp, DecoratorSet decorators) {
4792   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4793 }
4794 
4795 // Doesn't do verification, generates fixed size code
4796 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4797                                             Register thread_tmp, DecoratorSet decorators) {
4798   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4799 }
4800 
4801 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4802                                     Register tmp2, Register tmp3, DecoratorSet decorators) {
4803   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2, tmp3);
4804 }
4805 
4806 // Used for storing NULLs.
4807 void MacroAssembler::store_heap_oop_null(Address dst) {
4808   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4809 }
4810 
4811 #ifdef _LP64
4812 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4813   if (UseCompressedClassPointers) {
4814     // Store to klass gap in destination
4815     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4816   }
4817 }
4818 
4819 #ifdef ASSERT
4820 void MacroAssembler::verify_heapbase(const char* msg) {
4821   assert (UseCompressedOops, "should be compressed");
4822   assert (Universe::heap() != NULL, "java heap should be initialized");
4823   if (CheckCompressedOops) {
4824     Label ok;
4825     const auto src2 = ExternalAddress((address)CompressedOops::ptrs_base_addr());
4826     assert(!src2.is_lval(), "should not be lval");
4827     const bool is_src2_reachable = reachable(src2);
4828     if (!is_src2_reachable) {
4829       push(rscratch1);  // cmpptr trashes rscratch1
4830     }
4831     cmpptr(r12_heapbase, src2);
4832     jcc(Assembler::equal, ok);
4833     STOP(msg);
4834     bind(ok);
4835     if (!is_src2_reachable) {
4836       pop(rscratch1);
4837     }
4838   }
4839 }
4840 #endif
4841 
4842 // Algorithm must match oop.inline.hpp encode_heap_oop.
4843 void MacroAssembler::encode_heap_oop(Register r) {
4844 #ifdef ASSERT
4845   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4846 #endif
4847   verify_oop_msg(r, "broken oop in encode_heap_oop");
4848   if (CompressedOops::base() == NULL) {
4849     if (CompressedOops::shift() != 0) {
4850       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4851       shrq(r, LogMinObjAlignmentInBytes);
4852     }
4853     return;
4854   }
4855   testq(r, r);
4856   cmovq(Assembler::equal, r, r12_heapbase);
4857   subq(r, r12_heapbase);
4858   shrq(r, LogMinObjAlignmentInBytes);
4859 }
4860 
4861 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4862 #ifdef ASSERT
4863   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4864   if (CheckCompressedOops) {
4865     Label ok;
4866     testq(r, r);
4867     jcc(Assembler::notEqual, ok);
4868     STOP("null oop passed to encode_heap_oop_not_null");
4869     bind(ok);
4870   }
4871 #endif
4872   verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4873   if (CompressedOops::base() != NULL) {
4874     subq(r, r12_heapbase);
4875   }
4876   if (CompressedOops::shift() != 0) {
4877     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4878     shrq(r, LogMinObjAlignmentInBytes);
4879   }
4880 }
4881 
4882 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4883 #ifdef ASSERT
4884   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4885   if (CheckCompressedOops) {
4886     Label ok;
4887     testq(src, src);
4888     jcc(Assembler::notEqual, ok);
4889     STOP("null oop passed to encode_heap_oop_not_null2");
4890     bind(ok);
4891   }
4892 #endif
4893   verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4894   if (dst != src) {
4895     movq(dst, src);
4896   }
4897   if (CompressedOops::base() != NULL) {
4898     subq(dst, r12_heapbase);
4899   }
4900   if (CompressedOops::shift() != 0) {
4901     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4902     shrq(dst, LogMinObjAlignmentInBytes);
4903   }
4904 }
4905 
4906 void  MacroAssembler::decode_heap_oop(Register r) {
4907 #ifdef ASSERT
4908   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4909 #endif
4910   if (CompressedOops::base() == NULL) {
4911     if (CompressedOops::shift() != 0) {
4912       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4913       shlq(r, LogMinObjAlignmentInBytes);
4914     }
4915   } else {
4916     Label done;
4917     shlq(r, LogMinObjAlignmentInBytes);
4918     jccb(Assembler::equal, done);
4919     addq(r, r12_heapbase);
4920     bind(done);
4921   }
4922   verify_oop_msg(r, "broken oop in decode_heap_oop");
4923 }
4924 
4925 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
4926   // Note: it will change flags
4927   assert (UseCompressedOops, "should only be used for compressed headers");
4928   assert (Universe::heap() != NULL, "java heap should be initialized");
4929   // Cannot assert, unverified entry point counts instructions (see .ad file)
4930   // vtableStubs also counts instructions in pd_code_size_limit.
4931   // Also do not verify_oop as this is called by verify_oop.
4932   if (CompressedOops::shift() != 0) {
4933     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4934     shlq(r, LogMinObjAlignmentInBytes);
4935     if (CompressedOops::base() != NULL) {
4936       addq(r, r12_heapbase);
4937     }
4938   } else {
4939     assert (CompressedOops::base() == NULL, "sanity");
4940   }
4941 }
4942 
4943 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
4944   // Note: it will change flags
4945   assert (UseCompressedOops, "should only be used for compressed headers");
4946   assert (Universe::heap() != NULL, "java heap should be initialized");
4947   // Cannot assert, unverified entry point counts instructions (see .ad file)
4948   // vtableStubs also counts instructions in pd_code_size_limit.
4949   // Also do not verify_oop as this is called by verify_oop.
4950   if (CompressedOops::shift() != 0) {
4951     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4952     if (LogMinObjAlignmentInBytes == Address::times_8) {
4953       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
4954     } else {
4955       if (dst != src) {
4956         movq(dst, src);
4957       }
4958       shlq(dst, LogMinObjAlignmentInBytes);
4959       if (CompressedOops::base() != NULL) {
4960         addq(dst, r12_heapbase);
4961       }
4962     }
4963   } else {
4964     assert (CompressedOops::base() == NULL, "sanity");
4965     if (dst != src) {
4966       movq(dst, src);
4967     }
4968   }
4969 }
4970 
4971 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
4972   assert_different_registers(r, tmp);
4973   if (CompressedKlassPointers::base() != NULL) {
4974     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4975     subq(r, tmp);
4976   }
4977   if (CompressedKlassPointers::shift() != 0) {
4978     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4979     shrq(r, LogKlassAlignmentInBytes);
4980   }
4981 }
4982 
4983 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
4984   assert_different_registers(src, dst);
4985   if (CompressedKlassPointers::base() != NULL) {
4986     mov64(dst, -(int64_t)CompressedKlassPointers::base());
4987     addq(dst, src);
4988   } else {
4989     movptr(dst, src);
4990   }
4991   if (CompressedKlassPointers::shift() != 0) {
4992     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4993     shrq(dst, LogKlassAlignmentInBytes);
4994   }
4995 }
4996 
4997 void  MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
4998   assert_different_registers(r, tmp);
4999   // Note: it will change flags
5000   assert(UseCompressedClassPointers, "should only be used for compressed headers");
5001   // Cannot assert, unverified entry point counts instructions (see .ad file)
5002   // vtableStubs also counts instructions in pd_code_size_limit.
5003   // Also do not verify_oop as this is called by verify_oop.
5004   if (CompressedKlassPointers::shift() != 0) {
5005     assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5006     shlq(r, LogKlassAlignmentInBytes);
5007   }
5008   if (CompressedKlassPointers::base() != NULL) {
5009     mov64(tmp, (int64_t)CompressedKlassPointers::base());
5010     addq(r, tmp);
5011   }
5012 }
5013 
5014 void  MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5015   assert_different_registers(src, dst);
5016   // Note: it will change flags
5017   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5018   // Cannot assert, unverified entry point counts instructions (see .ad file)
5019   // vtableStubs also counts instructions in pd_code_size_limit.
5020   // Also do not verify_oop as this is called by verify_oop.
5021 
5022   if (CompressedKlassPointers::base() == NULL &&
5023       CompressedKlassPointers::shift() == 0) {
5024     // The best case scenario is that there is no base or shift. Then it is already
5025     // a pointer that needs nothing but a register rename.
5026     movl(dst, src);
5027   } else {
5028     if (CompressedKlassPointers::base() != NULL) {
5029       mov64(dst, (int64_t)CompressedKlassPointers::base());
5030     } else {
5031       xorq(dst, dst);
5032     }
5033     if (CompressedKlassPointers::shift() != 0) {
5034       assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5035       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5036       leaq(dst, Address(dst, src, Address::times_8, 0));
5037     } else {
5038       addq(dst, src);
5039     }
5040   }
5041 }
5042 
5043 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5044   assert (UseCompressedOops, "should only be used for compressed headers");
5045   assert (Universe::heap() != NULL, "java heap should be initialized");
5046   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5047   int oop_index = oop_recorder()->find_index(obj);
5048   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5049   mov_narrow_oop(dst, oop_index, rspec);
5050 }
5051 
5052 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5053   assert (UseCompressedOops, "should only be used for compressed headers");
5054   assert (Universe::heap() != NULL, "java heap should be initialized");
5055   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5056   int oop_index = oop_recorder()->find_index(obj);
5057   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5058   mov_narrow_oop(dst, oop_index, rspec);
5059 }
5060 
5061 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5062   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5063   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5064   int klass_index = oop_recorder()->find_index(k);
5065   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5066   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5067 }
5068 
5069 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5070   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5071   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5072   int klass_index = oop_recorder()->find_index(k);
5073   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5074   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5075 }
5076 
5077 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5078   assert (UseCompressedOops, "should only be used for compressed headers");
5079   assert (Universe::heap() != NULL, "java heap should be initialized");
5080   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5081   int oop_index = oop_recorder()->find_index(obj);
5082   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5083   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5084 }
5085 
5086 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5087   assert (UseCompressedOops, "should only be used for compressed headers");
5088   assert (Universe::heap() != NULL, "java heap should be initialized");
5089   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5090   int oop_index = oop_recorder()->find_index(obj);
5091   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5092   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5093 }
5094 
5095 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5096   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5097   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5098   int klass_index = oop_recorder()->find_index(k);
5099   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5100   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5101 }
5102 
5103 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5104   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5105   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5106   int klass_index = oop_recorder()->find_index(k);
5107   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5108   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5109 }
5110 
5111 void MacroAssembler::reinit_heapbase() {
5112   if (UseCompressedOops) {
5113     if (Universe::heap() != NULL) {
5114       if (CompressedOops::base() == NULL) {
5115         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5116       } else {
5117         mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5118       }
5119     } else {
5120       movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5121     }
5122   }
5123 }
5124 
5125 #endif // _LP64
5126 
5127 // C2 compiled method's prolog code.
5128 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5129 
5130   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5131   // NativeJump::patch_verified_entry will be able to patch out the entry
5132   // code safely. The push to verify stack depth is ok at 5 bytes,
5133   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5134   // stack bang then we must use the 6 byte frame allocation even if
5135   // we have no frame. :-(
5136   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5137 
5138   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5139   // Remove word for return addr
5140   framesize -= wordSize;
5141   stack_bang_size -= wordSize;
5142 
5143   // Calls to C2R adapters often do not accept exceptional returns.
5144   // We require that their callers must bang for them.  But be careful, because
5145   // some VM calls (such as call site linkage) can use several kilobytes of
5146   // stack.  But the stack safety zone should account for that.
5147   // See bugs 4446381, 4468289, 4497237.
5148   if (stack_bang_size > 0) {
5149     generate_stack_overflow_check(stack_bang_size);
5150 
5151     // We always push rbp, so that on return to interpreter rbp, will be
5152     // restored correctly and we can correct the stack.
5153     push(rbp);
5154     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5155     if (PreserveFramePointer) {
5156       mov(rbp, rsp);
5157     }
5158     // Remove word for ebp
5159     framesize -= wordSize;
5160 
5161     // Create frame
5162     if (framesize) {
5163       subptr(rsp, framesize);
5164     }
5165   } else {
5166     // Create frame (force generation of a 4 byte immediate value)
5167     subptr_imm32(rsp, framesize);
5168 
5169     // Save RBP register now.
5170     framesize -= wordSize;
5171     movptr(Address(rsp, framesize), rbp);
5172     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5173     if (PreserveFramePointer) {
5174       movptr(rbp, rsp);
5175       if (framesize > 0) {
5176         addptr(rbp, framesize);
5177       }
5178     }
5179   }
5180 
5181   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5182     framesize -= wordSize;
5183     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5184   }
5185 
5186 #ifndef _LP64
5187   // If method sets FPU control word do it now
5188   if (fp_mode_24b) {
5189     fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
5190   }
5191   if (UseSSE >= 2 && VerifyFPU) {
5192     verify_FPU(0, "FPU stack must be clean on entry");
5193   }
5194 #endif
5195 
5196 #ifdef ASSERT
5197   if (VerifyStackAtCalls) {
5198     Label L;
5199     push(rax);
5200     mov(rax, rsp);
5201     andptr(rax, StackAlignmentInBytes-1);
5202     cmpptr(rax, StackAlignmentInBytes-wordSize);
5203     pop(rax);
5204     jcc(Assembler::equal, L);
5205     STOP("Stack is not properly aligned!");
5206     bind(L);
5207   }
5208 #endif
5209 
5210   if (!is_stub) {
5211     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5212     bs->nmethod_entry_barrier(this);
5213   }
5214 }
5215 
5216 #if COMPILER2_OR_JVMCI
5217 
5218 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5219 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5220   // cnt - number of qwords (8-byte words).
5221   // base - start address, qword aligned.
5222   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5223   bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
5224   if (use64byteVector) {
5225     vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5226   } else if (MaxVectorSize >= 32) {
5227     vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5228   } else {
5229     pxor(xtmp, xtmp);
5230   }
5231   jmp(L_zero_64_bytes);
5232 
5233   BIND(L_loop);
5234   if (MaxVectorSize >= 32) {
5235     fill64(base, 0, xtmp, use64byteVector);
5236   } else {
5237     movdqu(Address(base,  0), xtmp);
5238     movdqu(Address(base, 16), xtmp);
5239     movdqu(Address(base, 32), xtmp);
5240     movdqu(Address(base, 48), xtmp);
5241   }
5242   addptr(base, 64);
5243 
5244   BIND(L_zero_64_bytes);
5245   subptr(cnt, 8);
5246   jccb(Assembler::greaterEqual, L_loop);
5247 
5248   // Copy trailing 64 bytes
5249   if (use64byteVector) {
5250     addptr(cnt, 8);
5251     jccb(Assembler::equal, L_end);
5252     fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5253     jmp(L_end);
5254   } else {
5255     addptr(cnt, 4);
5256     jccb(Assembler::less, L_tail);
5257     if (MaxVectorSize >= 32) {
5258       vmovdqu(Address(base, 0), xtmp);
5259     } else {
5260       movdqu(Address(base,  0), xtmp);
5261       movdqu(Address(base, 16), xtmp);
5262     }
5263   }
5264   addptr(base, 32);
5265   subptr(cnt, 4);
5266 
5267   BIND(L_tail);
5268   addptr(cnt, 4);
5269   jccb(Assembler::lessEqual, L_end);
5270   if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5271     fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5272   } else {
5273     decrement(cnt);
5274 
5275     BIND(L_sloop);
5276     movq(Address(base, 0), xtmp);
5277     addptr(base, 8);
5278     decrement(cnt);
5279     jccb(Assembler::greaterEqual, L_sloop);
5280   }
5281   BIND(L_end);
5282 }
5283 
5284 // Clearing constant sized memory using YMM/ZMM registers.
5285 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5286   assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
5287   bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
5288 
5289   int vector64_count = (cnt & (~0x7)) >> 3;
5290   cnt = cnt & 0x7;
5291 
5292   // 64 byte initialization loop.
5293   vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5294   for (int i = 0; i < vector64_count; i++) {
5295     fill64(base, i * 64, xtmp, use64byteVector);
5296   }
5297 
5298   // Clear remaining 64 byte tail.
5299   int disp = vector64_count * 64;
5300   if (cnt) {
5301     switch (cnt) {
5302       case 1:
5303         movq(Address(base, disp), xtmp);
5304         break;
5305       case 2:
5306         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit);
5307         break;
5308       case 3:
5309         movl(rtmp, 0x7);
5310         kmovwl(mask, rtmp);
5311         evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit);
5312         break;
5313       case 4:
5314         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5315         break;
5316       case 5:
5317         if (use64byteVector) {
5318           movl(rtmp, 0x1F);
5319           kmovwl(mask, rtmp);
5320           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5321         } else {
5322           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5323           movq(Address(base, disp + 32), xtmp);
5324         }
5325         break;
5326       case 6:
5327         if (use64byteVector) {
5328           movl(rtmp, 0x3F);
5329           kmovwl(mask, rtmp);
5330           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5331         } else {
5332           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5333           evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit);
5334         }
5335         break;
5336       case 7:
5337         if (use64byteVector) {
5338           movl(rtmp, 0x7F);
5339           kmovwl(mask, rtmp);
5340           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5341         } else {
5342           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5343           movl(rtmp, 0x7);
5344           kmovwl(mask, rtmp);
5345           evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit);
5346         }
5347         break;
5348       default:
5349         fatal("Unexpected length : %d\n",cnt);
5350         break;
5351     }
5352   }
5353 }
5354 
5355 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5356                                bool is_large, KRegister mask) {
5357   // cnt      - number of qwords (8-byte words).
5358   // base     - start address, qword aligned.
5359   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5360   assert(base==rdi, "base register must be edi for rep stos");
5361   assert(tmp==rax,   "tmp register must be eax for rep stos");
5362   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5363   assert(InitArrayShortSize % BytesPerLong == 0,
5364     "InitArrayShortSize should be the multiple of BytesPerLong");
5365 
5366   Label DONE;
5367   if (!is_large || !UseXMMForObjInit) {
5368     xorptr(tmp, tmp);
5369   }
5370 
5371   if (!is_large) {
5372     Label LOOP, LONG;
5373     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5374     jccb(Assembler::greater, LONG);
5375 
5376     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5377 
5378     decrement(cnt);
5379     jccb(Assembler::negative, DONE); // Zero length
5380 
5381     // Use individual pointer-sized stores for small counts:
5382     BIND(LOOP);
5383     movptr(Address(base, cnt, Address::times_ptr), tmp);
5384     decrement(cnt);
5385     jccb(Assembler::greaterEqual, LOOP);
5386     jmpb(DONE);
5387 
5388     BIND(LONG);
5389   }
5390 
5391   // Use longer rep-prefixed ops for non-small counts:
5392   if (UseFastStosb) {
5393     shlptr(cnt, 3); // convert to number of bytes
5394     rep_stosb();
5395   } else if (UseXMMForObjInit) {
5396     xmm_clear_mem(base, cnt, tmp, xtmp, mask);
5397   } else {
5398     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5399     rep_stos();
5400   }
5401 
5402   BIND(DONE);
5403 }
5404 
5405 #endif //COMPILER2_OR_JVMCI
5406 
5407 
5408 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5409                                    Register to, Register value, Register count,
5410                                    Register rtmp, XMMRegister xtmp) {
5411   ShortBranchVerifier sbv(this);
5412   assert_different_registers(to, value, count, rtmp);
5413   Label L_exit;
5414   Label L_fill_2_bytes, L_fill_4_bytes;
5415 
5416 #if defined(COMPILER2) && defined(_LP64)
5417   if(MaxVectorSize >=32 &&
5418      VM_Version::supports_avx512vlbw() &&
5419      VM_Version::supports_bmi2()) {
5420     generate_fill_avx3(t, to, value, count, rtmp, xtmp);
5421     return;
5422   }
5423 #endif
5424 
5425   int shift = -1;
5426   switch (t) {
5427     case T_BYTE:
5428       shift = 2;
5429       break;
5430     case T_SHORT:
5431       shift = 1;
5432       break;
5433     case T_INT:
5434       shift = 0;
5435       break;
5436     default: ShouldNotReachHere();
5437   }
5438 
5439   if (t == T_BYTE) {
5440     andl(value, 0xff);
5441     movl(rtmp, value);
5442     shll(rtmp, 8);
5443     orl(value, rtmp);
5444   }
5445   if (t == T_SHORT) {
5446     andl(value, 0xffff);
5447   }
5448   if (t == T_BYTE || t == T_SHORT) {
5449     movl(rtmp, value);
5450     shll(rtmp, 16);
5451     orl(value, rtmp);
5452   }
5453 
5454   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
5455   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
5456   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
5457     Label L_skip_align2;
5458     // align source address at 4 bytes address boundary
5459     if (t == T_BYTE) {
5460       Label L_skip_align1;
5461       // One byte misalignment happens only for byte arrays
5462       testptr(to, 1);
5463       jccb(Assembler::zero, L_skip_align1);
5464       movb(Address(to, 0), value);
5465       increment(to);
5466       decrement(count);
5467       BIND(L_skip_align1);
5468     }
5469     // Two bytes misalignment happens only for byte and short (char) arrays
5470     testptr(to, 2);
5471     jccb(Assembler::zero, L_skip_align2);
5472     movw(Address(to, 0), value);
5473     addptr(to, 2);
5474     subl(count, 1<<(shift-1));
5475     BIND(L_skip_align2);
5476   }
5477   if (UseSSE < 2) {
5478     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5479     // Fill 32-byte chunks
5480     subl(count, 8 << shift);
5481     jcc(Assembler::less, L_check_fill_8_bytes);
5482     align(16);
5483 
5484     BIND(L_fill_32_bytes_loop);
5485 
5486     for (int i = 0; i < 32; i += 4) {
5487       movl(Address(to, i), value);
5488     }
5489 
5490     addptr(to, 32);
5491     subl(count, 8 << shift);
5492     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5493     BIND(L_check_fill_8_bytes);
5494     addl(count, 8 << shift);
5495     jccb(Assembler::zero, L_exit);
5496     jmpb(L_fill_8_bytes);
5497 
5498     //
5499     // length is too short, just fill qwords
5500     //
5501     BIND(L_fill_8_bytes_loop);
5502     movl(Address(to, 0), value);
5503     movl(Address(to, 4), value);
5504     addptr(to, 8);
5505     BIND(L_fill_8_bytes);
5506     subl(count, 1 << (shift + 1));
5507     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5508     // fall through to fill 4 bytes
5509   } else {
5510     Label L_fill_32_bytes;
5511     if (!UseUnalignedLoadStores) {
5512       // align to 8 bytes, we know we are 4 byte aligned to start
5513       testptr(to, 4);
5514       jccb(Assembler::zero, L_fill_32_bytes);
5515       movl(Address(to, 0), value);
5516       addptr(to, 4);
5517       subl(count, 1<<shift);
5518     }
5519     BIND(L_fill_32_bytes);
5520     {
5521       assert( UseSSE >= 2, "supported cpu only" );
5522       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5523       movdl(xtmp, value);
5524       if (UseAVX >= 2 && UseUnalignedLoadStores) {
5525         Label L_check_fill_32_bytes;
5526         if (UseAVX > 2) {
5527           // Fill 64-byte chunks
5528           Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
5529 
5530           // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
5531           cmpl(count, VM_Version::avx3_threshold());
5532           jccb(Assembler::below, L_check_fill_64_bytes_avx2);
5533 
5534           vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
5535 
5536           subl(count, 16 << shift);
5537           jccb(Assembler::less, L_check_fill_32_bytes);
5538           align(16);
5539 
5540           BIND(L_fill_64_bytes_loop_avx3);
5541           evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
5542           addptr(to, 64);
5543           subl(count, 16 << shift);
5544           jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
5545           jmpb(L_check_fill_32_bytes);
5546 
5547           BIND(L_check_fill_64_bytes_avx2);
5548         }
5549         // Fill 64-byte chunks
5550         Label L_fill_64_bytes_loop;
5551         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
5552 
5553         subl(count, 16 << shift);
5554         jcc(Assembler::less, L_check_fill_32_bytes);
5555         align(16);
5556 
5557         BIND(L_fill_64_bytes_loop);
5558         vmovdqu(Address(to, 0), xtmp);
5559         vmovdqu(Address(to, 32), xtmp);
5560         addptr(to, 64);
5561         subl(count, 16 << shift);
5562         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
5563 
5564         BIND(L_check_fill_32_bytes);
5565         addl(count, 8 << shift);
5566         jccb(Assembler::less, L_check_fill_8_bytes);
5567         vmovdqu(Address(to, 0), xtmp);
5568         addptr(to, 32);
5569         subl(count, 8 << shift);
5570 
5571         BIND(L_check_fill_8_bytes);
5572         // clean upper bits of YMM registers
5573         movdl(xtmp, value);
5574         pshufd(xtmp, xtmp, 0);
5575       } else {
5576         // Fill 32-byte chunks
5577         pshufd(xtmp, xtmp, 0);
5578 
5579         subl(count, 8 << shift);
5580         jcc(Assembler::less, L_check_fill_8_bytes);
5581         align(16);
5582 
5583         BIND(L_fill_32_bytes_loop);
5584 
5585         if (UseUnalignedLoadStores) {
5586           movdqu(Address(to, 0), xtmp);
5587           movdqu(Address(to, 16), xtmp);
5588         } else {
5589           movq(Address(to, 0), xtmp);
5590           movq(Address(to, 8), xtmp);
5591           movq(Address(to, 16), xtmp);
5592           movq(Address(to, 24), xtmp);
5593         }
5594 
5595         addptr(to, 32);
5596         subl(count, 8 << shift);
5597         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5598 
5599         BIND(L_check_fill_8_bytes);
5600       }
5601       addl(count, 8 << shift);
5602       jccb(Assembler::zero, L_exit);
5603       jmpb(L_fill_8_bytes);
5604 
5605       //
5606       // length is too short, just fill qwords
5607       //
5608       BIND(L_fill_8_bytes_loop);
5609       movq(Address(to, 0), xtmp);
5610       addptr(to, 8);
5611       BIND(L_fill_8_bytes);
5612       subl(count, 1 << (shift + 1));
5613       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5614     }
5615   }
5616   // fill trailing 4 bytes
5617   BIND(L_fill_4_bytes);
5618   testl(count, 1<<shift);
5619   jccb(Assembler::zero, L_fill_2_bytes);
5620   movl(Address(to, 0), value);
5621   if (t == T_BYTE || t == T_SHORT) {
5622     Label L_fill_byte;
5623     addptr(to, 4);
5624     BIND(L_fill_2_bytes);
5625     // fill trailing 2 bytes
5626     testl(count, 1<<(shift-1));
5627     jccb(Assembler::zero, L_fill_byte);
5628     movw(Address(to, 0), value);
5629     if (t == T_BYTE) {
5630       addptr(to, 2);
5631       BIND(L_fill_byte);
5632       // fill trailing byte
5633       testl(count, 1);
5634       jccb(Assembler::zero, L_exit);
5635       movb(Address(to, 0), value);
5636     } else {
5637       BIND(L_fill_byte);
5638     }
5639   } else {
5640     BIND(L_fill_2_bytes);
5641   }
5642   BIND(L_exit);
5643 }
5644 
5645 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
5646   switch(type) {
5647     case T_BYTE:
5648     case T_BOOLEAN:
5649       evpbroadcastb(dst, src, vector_len);
5650       break;
5651     case T_SHORT:
5652     case T_CHAR:
5653       evpbroadcastw(dst, src, vector_len);
5654       break;
5655     case T_INT:
5656     case T_FLOAT:
5657       evpbroadcastd(dst, src, vector_len);
5658       break;
5659     case T_LONG:
5660     case T_DOUBLE:
5661       evpbroadcastq(dst, src, vector_len);
5662       break;
5663     default:
5664       fatal("Unhandled type : %s", type2name(type));
5665       break;
5666   }
5667 }
5668 
5669 // encode char[] to byte[] in ISO_8859_1 or ASCII
5670    //@IntrinsicCandidate
5671    //private static int implEncodeISOArray(byte[] sa, int sp,
5672    //byte[] da, int dp, int len) {
5673    //  int i = 0;
5674    //  for (; i < len; i++) {
5675    //    char c = StringUTF16.getChar(sa, sp++);
5676    //    if (c > '\u00FF')
5677    //      break;
5678    //    da[dp++] = (byte)c;
5679    //  }
5680    //  return i;
5681    //}
5682    //
5683    //@IntrinsicCandidate
5684    //private static int implEncodeAsciiArray(char[] sa, int sp,
5685    //    byte[] da, int dp, int len) {
5686    //  int i = 0;
5687    //  for (; i < len; i++) {
5688    //    char c = sa[sp++];
5689    //    if (c >= '\u0080')
5690    //      break;
5691    //    da[dp++] = (byte)c;
5692    //  }
5693    //  return i;
5694    //}
5695 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
5696   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
5697   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
5698   Register tmp5, Register result, bool ascii) {
5699 
5700   // rsi: src
5701   // rdi: dst
5702   // rdx: len
5703   // rcx: tmp5
5704   // rax: result
5705   ShortBranchVerifier sbv(this);
5706   assert_different_registers(src, dst, len, tmp5, result);
5707   Label L_done, L_copy_1_char, L_copy_1_char_exit;
5708 
5709   int mask = ascii ? 0xff80ff80 : 0xff00ff00;
5710   int short_mask = ascii ? 0xff80 : 0xff00;
5711 
5712   // set result
5713   xorl(result, result);
5714   // check for zero length
5715   testl(len, len);
5716   jcc(Assembler::zero, L_done);
5717 
5718   movl(result, len);
5719 
5720   // Setup pointers
5721   lea(src, Address(src, len, Address::times_2)); // char[]
5722   lea(dst, Address(dst, len, Address::times_1)); // byte[]
5723   negptr(len);
5724 
5725   if (UseSSE42Intrinsics || UseAVX >= 2) {
5726     Label L_copy_8_chars, L_copy_8_chars_exit;
5727     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
5728 
5729     if (UseAVX >= 2) {
5730       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
5731       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5732       movdl(tmp1Reg, tmp5);
5733       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
5734       jmp(L_chars_32_check);
5735 
5736       bind(L_copy_32_chars);
5737       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
5738       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
5739       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5740       vptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5741       jccb(Assembler::notZero, L_copy_32_chars_exit);
5742       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5743       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
5744       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
5745 
5746       bind(L_chars_32_check);
5747       addptr(len, 32);
5748       jcc(Assembler::lessEqual, L_copy_32_chars);
5749 
5750       bind(L_copy_32_chars_exit);
5751       subptr(len, 16);
5752       jccb(Assembler::greater, L_copy_16_chars_exit);
5753 
5754     } else if (UseSSE42Intrinsics) {
5755       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5756       movdl(tmp1Reg, tmp5);
5757       pshufd(tmp1Reg, tmp1Reg, 0);
5758       jmpb(L_chars_16_check);
5759     }
5760 
5761     bind(L_copy_16_chars);
5762     if (UseAVX >= 2) {
5763       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
5764       vptest(tmp2Reg, tmp1Reg);
5765       jcc(Assembler::notZero, L_copy_16_chars_exit);
5766       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
5767       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
5768     } else {
5769       if (UseAVX > 0) {
5770         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5771         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5772         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
5773       } else {
5774         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5775         por(tmp2Reg, tmp3Reg);
5776         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5777         por(tmp2Reg, tmp4Reg);
5778       }
5779       ptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5780       jccb(Assembler::notZero, L_copy_16_chars_exit);
5781       packuswb(tmp3Reg, tmp4Reg);
5782     }
5783     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
5784 
5785     bind(L_chars_16_check);
5786     addptr(len, 16);
5787     jcc(Assembler::lessEqual, L_copy_16_chars);
5788 
5789     bind(L_copy_16_chars_exit);
5790     if (UseAVX >= 2) {
5791       // clean upper bits of YMM registers
5792       vpxor(tmp2Reg, tmp2Reg);
5793       vpxor(tmp3Reg, tmp3Reg);
5794       vpxor(tmp4Reg, tmp4Reg);
5795       movdl(tmp1Reg, tmp5);
5796       pshufd(tmp1Reg, tmp1Reg, 0);
5797     }
5798     subptr(len, 8);
5799     jccb(Assembler::greater, L_copy_8_chars_exit);
5800 
5801     bind(L_copy_8_chars);
5802     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
5803     ptest(tmp3Reg, tmp1Reg);
5804     jccb(Assembler::notZero, L_copy_8_chars_exit);
5805     packuswb(tmp3Reg, tmp1Reg);
5806     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
5807     addptr(len, 8);
5808     jccb(Assembler::lessEqual, L_copy_8_chars);
5809 
5810     bind(L_copy_8_chars_exit);
5811     subptr(len, 8);
5812     jccb(Assembler::zero, L_done);
5813   }
5814 
5815   bind(L_copy_1_char);
5816   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
5817   testl(tmp5, short_mask);      // check if Unicode or non-ASCII char
5818   jccb(Assembler::notZero, L_copy_1_char_exit);
5819   movb(Address(dst, len, Address::times_1, 0), tmp5);
5820   addptr(len, 1);
5821   jccb(Assembler::less, L_copy_1_char);
5822 
5823   bind(L_copy_1_char_exit);
5824   addptr(result, len); // len is negative count of not processed elements
5825 
5826   bind(L_done);
5827 }
5828 
5829 #ifdef _LP64
5830 /**
5831  * Helper for multiply_to_len().
5832  */
5833 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
5834   addq(dest_lo, src1);
5835   adcq(dest_hi, 0);
5836   addq(dest_lo, src2);
5837   adcq(dest_hi, 0);
5838 }
5839 
5840 /**
5841  * Multiply 64 bit by 64 bit first loop.
5842  */
5843 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
5844                                            Register y, Register y_idx, Register z,
5845                                            Register carry, Register product,
5846                                            Register idx, Register kdx) {
5847   //
5848   //  jlong carry, x[], y[], z[];
5849   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5850   //    huge_128 product = y[idx] * x[xstart] + carry;
5851   //    z[kdx] = (jlong)product;
5852   //    carry  = (jlong)(product >>> 64);
5853   //  }
5854   //  z[xstart] = carry;
5855   //
5856 
5857   Label L_first_loop, L_first_loop_exit;
5858   Label L_one_x, L_one_y, L_multiply;
5859 
5860   decrementl(xstart);
5861   jcc(Assembler::negative, L_one_x);
5862 
5863   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
5864   rorq(x_xstart, 32); // convert big-endian to little-endian
5865 
5866   bind(L_first_loop);
5867   decrementl(idx);
5868   jcc(Assembler::negative, L_first_loop_exit);
5869   decrementl(idx);
5870   jcc(Assembler::negative, L_one_y);
5871   movq(y_idx, Address(y, idx, Address::times_4,  0));
5872   rorq(y_idx, 32); // convert big-endian to little-endian
5873   bind(L_multiply);
5874   movq(product, x_xstart);
5875   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
5876   addq(product, carry);
5877   adcq(rdx, 0);
5878   subl(kdx, 2);
5879   movl(Address(z, kdx, Address::times_4,  4), product);
5880   shrq(product, 32);
5881   movl(Address(z, kdx, Address::times_4,  0), product);
5882   movq(carry, rdx);
5883   jmp(L_first_loop);
5884 
5885   bind(L_one_y);
5886   movl(y_idx, Address(y,  0));
5887   jmp(L_multiply);
5888 
5889   bind(L_one_x);
5890   movl(x_xstart, Address(x,  0));
5891   jmp(L_first_loop);
5892 
5893   bind(L_first_loop_exit);
5894 }
5895 
5896 /**
5897  * Multiply 64 bit by 64 bit and add 128 bit.
5898  */
5899 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
5900                                             Register yz_idx, Register idx,
5901                                             Register carry, Register product, int offset) {
5902   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
5903   //     z[kdx] = (jlong)product;
5904 
5905   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
5906   rorq(yz_idx, 32); // convert big-endian to little-endian
5907   movq(product, x_xstart);
5908   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
5909   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
5910   rorq(yz_idx, 32); // convert big-endian to little-endian
5911 
5912   add2_with_carry(rdx, product, carry, yz_idx);
5913 
5914   movl(Address(z, idx, Address::times_4,  offset+4), product);
5915   shrq(product, 32);
5916   movl(Address(z, idx, Address::times_4,  offset), product);
5917 
5918 }
5919 
5920 /**
5921  * Multiply 128 bit by 128 bit. Unrolled inner loop.
5922  */
5923 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
5924                                              Register yz_idx, Register idx, Register jdx,
5925                                              Register carry, Register product,
5926                                              Register carry2) {
5927   //   jlong carry, x[], y[], z[];
5928   //   int kdx = ystart+1;
5929   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5930   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
5931   //     z[kdx+idx+1] = (jlong)product;
5932   //     jlong carry2  = (jlong)(product >>> 64);
5933   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
5934   //     z[kdx+idx] = (jlong)product;
5935   //     carry  = (jlong)(product >>> 64);
5936   //   }
5937   //   idx += 2;
5938   //   if (idx > 0) {
5939   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
5940   //     z[kdx+idx] = (jlong)product;
5941   //     carry  = (jlong)(product >>> 64);
5942   //   }
5943   //
5944 
5945   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5946 
5947   movl(jdx, idx);
5948   andl(jdx, 0xFFFFFFFC);
5949   shrl(jdx, 2);
5950 
5951   bind(L_third_loop);
5952   subl(jdx, 1);
5953   jcc(Assembler::negative, L_third_loop_exit);
5954   subl(idx, 4);
5955 
5956   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
5957   movq(carry2, rdx);
5958 
5959   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
5960   movq(carry, rdx);
5961   jmp(L_third_loop);
5962 
5963   bind (L_third_loop_exit);
5964 
5965   andl (idx, 0x3);
5966   jcc(Assembler::zero, L_post_third_loop_done);
5967 
5968   Label L_check_1;
5969   subl(idx, 2);
5970   jcc(Assembler::negative, L_check_1);
5971 
5972   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
5973   movq(carry, rdx);
5974 
5975   bind (L_check_1);
5976   addl (idx, 0x2);
5977   andl (idx, 0x1);
5978   subl(idx, 1);
5979   jcc(Assembler::negative, L_post_third_loop_done);
5980 
5981   movl(yz_idx, Address(y, idx, Address::times_4,  0));
5982   movq(product, x_xstart);
5983   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
5984   movl(yz_idx, Address(z, idx, Address::times_4,  0));
5985 
5986   add2_with_carry(rdx, product, yz_idx, carry);
5987 
5988   movl(Address(z, idx, Address::times_4,  0), product);
5989   shrq(product, 32);
5990 
5991   shlq(rdx, 32);
5992   orq(product, rdx);
5993   movq(carry, product);
5994 
5995   bind(L_post_third_loop_done);
5996 }
5997 
5998 /**
5999  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6000  *
6001  */
6002 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6003                                                   Register carry, Register carry2,
6004                                                   Register idx, Register jdx,
6005                                                   Register yz_idx1, Register yz_idx2,
6006                                                   Register tmp, Register tmp3, Register tmp4) {
6007   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6008 
6009   //   jlong carry, x[], y[], z[];
6010   //   int kdx = ystart+1;
6011   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6012   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6013   //     jlong carry2  = (jlong)(tmp3 >>> 64);
6014   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
6015   //     carry  = (jlong)(tmp4 >>> 64);
6016   //     z[kdx+idx+1] = (jlong)tmp3;
6017   //     z[kdx+idx] = (jlong)tmp4;
6018   //   }
6019   //   idx += 2;
6020   //   if (idx > 0) {
6021   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6022   //     z[kdx+idx] = (jlong)yz_idx1;
6023   //     carry  = (jlong)(yz_idx1 >>> 64);
6024   //   }
6025   //
6026 
6027   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6028 
6029   movl(jdx, idx);
6030   andl(jdx, 0xFFFFFFFC);
6031   shrl(jdx, 2);
6032 
6033   bind(L_third_loop);
6034   subl(jdx, 1);
6035   jcc(Assembler::negative, L_third_loop_exit);
6036   subl(idx, 4);
6037 
6038   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
6039   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6040   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
6041   rorxq(yz_idx2, yz_idx2, 32);
6042 
6043   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
6044   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
6045 
6046   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
6047   rorxq(yz_idx1, yz_idx1, 32);
6048   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6049   rorxq(yz_idx2, yz_idx2, 32);
6050 
6051   if (VM_Version::supports_adx()) {
6052     adcxq(tmp3, carry);
6053     adoxq(tmp3, yz_idx1);
6054 
6055     adcxq(tmp4, tmp);
6056     adoxq(tmp4, yz_idx2);
6057 
6058     movl(carry, 0); // does not affect flags
6059     adcxq(carry2, carry);
6060     adoxq(carry2, carry);
6061   } else {
6062     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6063     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6064   }
6065   movq(carry, carry2);
6066 
6067   movl(Address(z, idx, Address::times_4, 12), tmp3);
6068   shrq(tmp3, 32);
6069   movl(Address(z, idx, Address::times_4,  8), tmp3);
6070 
6071   movl(Address(z, idx, Address::times_4,  4), tmp4);
6072   shrq(tmp4, 32);
6073   movl(Address(z, idx, Address::times_4,  0), tmp4);
6074 
6075   jmp(L_third_loop);
6076 
6077   bind (L_third_loop_exit);
6078 
6079   andl (idx, 0x3);
6080   jcc(Assembler::zero, L_post_third_loop_done);
6081 
6082   Label L_check_1;
6083   subl(idx, 2);
6084   jcc(Assembler::negative, L_check_1);
6085 
6086   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
6087   rorxq(yz_idx1, yz_idx1, 32);
6088   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
6089   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6090   rorxq(yz_idx2, yz_idx2, 32);
6091 
6092   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6093 
6094   movl(Address(z, idx, Address::times_4,  4), tmp3);
6095   shrq(tmp3, 32);
6096   movl(Address(z, idx, Address::times_4,  0), tmp3);
6097   movq(carry, tmp4);
6098 
6099   bind (L_check_1);
6100   addl (idx, 0x2);
6101   andl (idx, 0x1);
6102   subl(idx, 1);
6103   jcc(Assembler::negative, L_post_third_loop_done);
6104   movl(tmp4, Address(y, idx, Address::times_4,  0));
6105   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
6106   movl(tmp4, Address(z, idx, Address::times_4,  0));
6107 
6108   add2_with_carry(carry2, tmp3, tmp4, carry);
6109 
6110   movl(Address(z, idx, Address::times_4,  0), tmp3);
6111   shrq(tmp3, 32);
6112 
6113   shlq(carry2, 32);
6114   orq(tmp3, carry2);
6115   movq(carry, tmp3);
6116 
6117   bind(L_post_third_loop_done);
6118 }
6119 
6120 /**
6121  * Code for BigInteger::multiplyToLen() intrinsic.
6122  *
6123  * rdi: x
6124  * rax: xlen
6125  * rsi: y
6126  * rcx: ylen
6127  * r8:  z
6128  * r11: zlen
6129  * r12: tmp1
6130  * r13: tmp2
6131  * r14: tmp3
6132  * r15: tmp4
6133  * rbx: tmp5
6134  *
6135  */
6136 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
6137                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6138   ShortBranchVerifier sbv(this);
6139   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6140 
6141   push(tmp1);
6142   push(tmp2);
6143   push(tmp3);
6144   push(tmp4);
6145   push(tmp5);
6146 
6147   push(xlen);
6148   push(zlen);
6149 
6150   const Register idx = tmp1;
6151   const Register kdx = tmp2;
6152   const Register xstart = tmp3;
6153 
6154   const Register y_idx = tmp4;
6155   const Register carry = tmp5;
6156   const Register product  = xlen;
6157   const Register x_xstart = zlen;  // reuse register
6158 
6159   // First Loop.
6160   //
6161   //  final static long LONG_MASK = 0xffffffffL;
6162   //  int xstart = xlen - 1;
6163   //  int ystart = ylen - 1;
6164   //  long carry = 0;
6165   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6166   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6167   //    z[kdx] = (int)product;
6168   //    carry = product >>> 32;
6169   //  }
6170   //  z[xstart] = (int)carry;
6171   //
6172 
6173   movl(idx, ylen);      // idx = ylen;
6174   movl(kdx, zlen);      // kdx = xlen+ylen;
6175   xorq(carry, carry);   // carry = 0;
6176 
6177   Label L_done;
6178 
6179   movl(xstart, xlen);
6180   decrementl(xstart);
6181   jcc(Assembler::negative, L_done);
6182 
6183   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6184 
6185   Label L_second_loop;
6186   testl(kdx, kdx);
6187   jcc(Assembler::zero, L_second_loop);
6188 
6189   Label L_carry;
6190   subl(kdx, 1);
6191   jcc(Assembler::zero, L_carry);
6192 
6193   movl(Address(z, kdx, Address::times_4,  0), carry);
6194   shrq(carry, 32);
6195   subl(kdx, 1);
6196 
6197   bind(L_carry);
6198   movl(Address(z, kdx, Address::times_4,  0), carry);
6199 
6200   // Second and third (nested) loops.
6201   //
6202   // for (int i = xstart-1; i >= 0; i--) { // Second loop
6203   //   carry = 0;
6204   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6205   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6206   //                    (z[k] & LONG_MASK) + carry;
6207   //     z[k] = (int)product;
6208   //     carry = product >>> 32;
6209   //   }
6210   //   z[i] = (int)carry;
6211   // }
6212   //
6213   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6214 
6215   const Register jdx = tmp1;
6216 
6217   bind(L_second_loop);
6218   xorl(carry, carry);    // carry = 0;
6219   movl(jdx, ylen);       // j = ystart+1
6220 
6221   subl(xstart, 1);       // i = xstart-1;
6222   jcc(Assembler::negative, L_done);
6223 
6224   push (z);
6225 
6226   Label L_last_x;
6227   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6228   subl(xstart, 1);       // i = xstart-1;
6229   jcc(Assembler::negative, L_last_x);
6230 
6231   if (UseBMI2Instructions) {
6232     movq(rdx,  Address(x, xstart, Address::times_4,  0));
6233     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6234   } else {
6235     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
6236     rorq(x_xstart, 32);  // convert big-endian to little-endian
6237   }
6238 
6239   Label L_third_loop_prologue;
6240   bind(L_third_loop_prologue);
6241 
6242   push (x);
6243   push (xstart);
6244   push (ylen);
6245 
6246 
6247   if (UseBMI2Instructions) {
6248     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6249   } else { // !UseBMI2Instructions
6250     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6251   }
6252 
6253   pop(ylen);
6254   pop(xlen);
6255   pop(x);
6256   pop(z);
6257 
6258   movl(tmp3, xlen);
6259   addl(tmp3, 1);
6260   movl(Address(z, tmp3, Address::times_4,  0), carry);
6261   subl(tmp3, 1);
6262   jccb(Assembler::negative, L_done);
6263 
6264   shrq(carry, 32);
6265   movl(Address(z, tmp3, Address::times_4,  0), carry);
6266   jmp(L_second_loop);
6267 
6268   // Next infrequent code is moved outside loops.
6269   bind(L_last_x);
6270   if (UseBMI2Instructions) {
6271     movl(rdx, Address(x,  0));
6272   } else {
6273     movl(x_xstart, Address(x,  0));
6274   }
6275   jmp(L_third_loop_prologue);
6276 
6277   bind(L_done);
6278 
6279   pop(zlen);
6280   pop(xlen);
6281 
6282   pop(tmp5);
6283   pop(tmp4);
6284   pop(tmp3);
6285   pop(tmp2);
6286   pop(tmp1);
6287 }
6288 
6289 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6290   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6291   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6292   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6293   Label VECTOR8_TAIL, VECTOR4_TAIL;
6294   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6295   Label SAME_TILL_END, DONE;
6296   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6297 
6298   //scale is in rcx in both Win64 and Unix
6299   ShortBranchVerifier sbv(this);
6300 
6301   shlq(length);
6302   xorq(result, result);
6303 
6304   if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6305       VM_Version::supports_avx512vlbw()) {
6306     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6307 
6308     cmpq(length, 64);
6309     jcc(Assembler::less, VECTOR32_TAIL);
6310 
6311     movq(tmp1, length);
6312     andq(tmp1, 0x3F);      // tail count
6313     andq(length, ~(0x3F)); //vector count
6314 
6315     bind(VECTOR64_LOOP);
6316     // AVX512 code to compare 64 byte vectors.
6317     evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit);
6318     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6319     kortestql(k7, k7);
6320     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
6321     addq(result, 64);
6322     subq(length, 64);
6323     jccb(Assembler::notZero, VECTOR64_LOOP);
6324 
6325     //bind(VECTOR64_TAIL);
6326     testq(tmp1, tmp1);
6327     jcc(Assembler::zero, SAME_TILL_END);
6328 
6329     //bind(VECTOR64_TAIL);
6330     // AVX512 code to compare up to 63 byte vectors.
6331     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6332     shlxq(tmp2, tmp2, tmp1);
6333     notq(tmp2);
6334     kmovql(k3, tmp2);
6335 
6336     evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6337     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6338 
6339     ktestql(k7, k3);
6340     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
6341 
6342     bind(VECTOR64_NOT_EQUAL);
6343     kmovql(tmp1, k7);
6344     notq(tmp1);
6345     tzcntq(tmp1, tmp1);
6346     addq(result, tmp1);
6347     shrq(result);
6348     jmp(DONE);
6349     bind(VECTOR32_TAIL);
6350   }
6351 
6352   cmpq(length, 8);
6353   jcc(Assembler::equal, VECTOR8_LOOP);
6354   jcc(Assembler::less, VECTOR4_TAIL);
6355 
6356   if (UseAVX >= 2) {
6357     Label VECTOR16_TAIL, VECTOR32_LOOP;
6358 
6359     cmpq(length, 16);
6360     jcc(Assembler::equal, VECTOR16_LOOP);
6361     jcc(Assembler::less, VECTOR8_LOOP);
6362 
6363     cmpq(length, 32);
6364     jccb(Assembler::less, VECTOR16_TAIL);
6365 
6366     subq(length, 32);
6367     bind(VECTOR32_LOOP);
6368     vmovdqu(rymm0, Address(obja, result));
6369     vmovdqu(rymm1, Address(objb, result));
6370     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6371     vptest(rymm2, rymm2);
6372     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6373     addq(result, 32);
6374     subq(length, 32);
6375     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6376     addq(length, 32);
6377     jcc(Assembler::equal, SAME_TILL_END);
6378     //falling through if less than 32 bytes left //close the branch here.
6379 
6380     bind(VECTOR16_TAIL);
6381     cmpq(length, 16);
6382     jccb(Assembler::less, VECTOR8_TAIL);
6383     bind(VECTOR16_LOOP);
6384     movdqu(rymm0, Address(obja, result));
6385     movdqu(rymm1, Address(objb, result));
6386     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6387     ptest(rymm2, rymm2);
6388     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6389     addq(result, 16);
6390     subq(length, 16);
6391     jcc(Assembler::equal, SAME_TILL_END);
6392     //falling through if less than 16 bytes left
6393   } else {//regular intrinsics
6394 
6395     cmpq(length, 16);
6396     jccb(Assembler::less, VECTOR8_TAIL);
6397 
6398     subq(length, 16);
6399     bind(VECTOR16_LOOP);
6400     movdqu(rymm0, Address(obja, result));
6401     movdqu(rymm1, Address(objb, result));
6402     pxor(rymm0, rymm1);
6403     ptest(rymm0, rymm0);
6404     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6405     addq(result, 16);
6406     subq(length, 16);
6407     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6408     addq(length, 16);
6409     jcc(Assembler::equal, SAME_TILL_END);
6410     //falling through if less than 16 bytes left
6411   }
6412 
6413   bind(VECTOR8_TAIL);
6414   cmpq(length, 8);
6415   jccb(Assembler::less, VECTOR4_TAIL);
6416   bind(VECTOR8_LOOP);
6417   movq(tmp1, Address(obja, result));
6418   movq(tmp2, Address(objb, result));
6419   xorq(tmp1, tmp2);
6420   testq(tmp1, tmp1);
6421   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
6422   addq(result, 8);
6423   subq(length, 8);
6424   jcc(Assembler::equal, SAME_TILL_END);
6425   //falling through if less than 8 bytes left
6426 
6427   bind(VECTOR4_TAIL);
6428   cmpq(length, 4);
6429   jccb(Assembler::less, BYTES_TAIL);
6430   bind(VECTOR4_LOOP);
6431   movl(tmp1, Address(obja, result));
6432   xorl(tmp1, Address(objb, result));
6433   testl(tmp1, tmp1);
6434   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
6435   addq(result, 4);
6436   subq(length, 4);
6437   jcc(Assembler::equal, SAME_TILL_END);
6438   //falling through if less than 4 bytes left
6439 
6440   bind(BYTES_TAIL);
6441   bind(BYTES_LOOP);
6442   load_unsigned_byte(tmp1, Address(obja, result));
6443   load_unsigned_byte(tmp2, Address(objb, result));
6444   xorl(tmp1, tmp2);
6445   testl(tmp1, tmp1);
6446   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6447   decq(length);
6448   jcc(Assembler::zero, SAME_TILL_END);
6449   incq(result);
6450   load_unsigned_byte(tmp1, Address(obja, result));
6451   load_unsigned_byte(tmp2, Address(objb, result));
6452   xorl(tmp1, tmp2);
6453   testl(tmp1, tmp1);
6454   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6455   decq(length);
6456   jcc(Assembler::zero, SAME_TILL_END);
6457   incq(result);
6458   load_unsigned_byte(tmp1, Address(obja, result));
6459   load_unsigned_byte(tmp2, Address(objb, result));
6460   xorl(tmp1, tmp2);
6461   testl(tmp1, tmp1);
6462   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6463   jmp(SAME_TILL_END);
6464 
6465   if (UseAVX >= 2) {
6466     bind(VECTOR32_NOT_EQUAL);
6467     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
6468     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
6469     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
6470     vpmovmskb(tmp1, rymm0);
6471     bsfq(tmp1, tmp1);
6472     addq(result, tmp1);
6473     shrq(result);
6474     jmp(DONE);
6475   }
6476 
6477   bind(VECTOR16_NOT_EQUAL);
6478   if (UseAVX >= 2) {
6479     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
6480     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
6481     pxor(rymm0, rymm2);
6482   } else {
6483     pcmpeqb(rymm2, rymm2);
6484     pxor(rymm0, rymm1);
6485     pcmpeqb(rymm0, rymm1);
6486     pxor(rymm0, rymm2);
6487   }
6488   pmovmskb(tmp1, rymm0);
6489   bsfq(tmp1, tmp1);
6490   addq(result, tmp1);
6491   shrq(result);
6492   jmpb(DONE);
6493 
6494   bind(VECTOR8_NOT_EQUAL);
6495   bind(VECTOR4_NOT_EQUAL);
6496   bsfq(tmp1, tmp1);
6497   shrq(tmp1, 3);
6498   addq(result, tmp1);
6499   bind(BYTES_NOT_EQUAL);
6500   shrq(result);
6501   jmpb(DONE);
6502 
6503   bind(SAME_TILL_END);
6504   mov64(result, -1);
6505 
6506   bind(DONE);
6507 }
6508 
6509 //Helper functions for square_to_len()
6510 
6511 /**
6512  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
6513  * Preserves x and z and modifies rest of the registers.
6514  */
6515 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6516   // Perform square and right shift by 1
6517   // Handle odd xlen case first, then for even xlen do the following
6518   // jlong carry = 0;
6519   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
6520   //     huge_128 product = x[j:j+1] * x[j:j+1];
6521   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
6522   //     z[i+2:i+3] = (jlong)(product >>> 1);
6523   //     carry = (jlong)product;
6524   // }
6525 
6526   xorq(tmp5, tmp5);     // carry
6527   xorq(rdxReg, rdxReg);
6528   xorl(tmp1, tmp1);     // index for x
6529   xorl(tmp4, tmp4);     // index for z
6530 
6531   Label L_first_loop, L_first_loop_exit;
6532 
6533   testl(xlen, 1);
6534   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
6535 
6536   // Square and right shift by 1 the odd element using 32 bit multiply
6537   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
6538   imulq(raxReg, raxReg);
6539   shrq(raxReg, 1);
6540   adcq(tmp5, 0);
6541   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
6542   incrementl(tmp1);
6543   addl(tmp4, 2);
6544 
6545   // Square and  right shift by 1 the rest using 64 bit multiply
6546   bind(L_first_loop);
6547   cmpptr(tmp1, xlen);
6548   jccb(Assembler::equal, L_first_loop_exit);
6549 
6550   // Square
6551   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
6552   rorq(raxReg, 32);    // convert big-endian to little-endian
6553   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
6554 
6555   // Right shift by 1 and save carry
6556   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
6557   rcrq(rdxReg, 1);
6558   rcrq(raxReg, 1);
6559   adcq(tmp5, 0);
6560 
6561   // Store result in z
6562   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
6563   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
6564 
6565   // Update indices for x and z
6566   addl(tmp1, 2);
6567   addl(tmp4, 4);
6568   jmp(L_first_loop);
6569 
6570   bind(L_first_loop_exit);
6571 }
6572 
6573 
6574 /**
6575  * Perform the following multiply add operation using BMI2 instructions
6576  * carry:sum = sum + op1*op2 + carry
6577  * op2 should be in rdx
6578  * op2 is preserved, all other registers are modified
6579  */
6580 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
6581   // assert op2 is rdx
6582   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
6583   addq(sum, carry);
6584   adcq(tmp2, 0);
6585   addq(sum, op1);
6586   adcq(tmp2, 0);
6587   movq(carry, tmp2);
6588 }
6589 
6590 /**
6591  * Perform the following multiply add operation:
6592  * carry:sum = sum + op1*op2 + carry
6593  * Preserves op1, op2 and modifies rest of registers
6594  */
6595 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
6596   // rdx:rax = op1 * op2
6597   movq(raxReg, op2);
6598   mulq(op1);
6599 
6600   //  rdx:rax = sum + carry + rdx:rax
6601   addq(sum, carry);
6602   adcq(rdxReg, 0);
6603   addq(sum, raxReg);
6604   adcq(rdxReg, 0);
6605 
6606   // carry:sum = rdx:sum
6607   movq(carry, rdxReg);
6608 }
6609 
6610 /**
6611  * Add 64 bit long carry into z[] with carry propagation.
6612  * Preserves z and carry register values and modifies rest of registers.
6613  *
6614  */
6615 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
6616   Label L_fourth_loop, L_fourth_loop_exit;
6617 
6618   movl(tmp1, 1);
6619   subl(zlen, 2);
6620   addq(Address(z, zlen, Address::times_4, 0), carry);
6621 
6622   bind(L_fourth_loop);
6623   jccb(Assembler::carryClear, L_fourth_loop_exit);
6624   subl(zlen, 2);
6625   jccb(Assembler::negative, L_fourth_loop_exit);
6626   addq(Address(z, zlen, Address::times_4, 0), tmp1);
6627   jmp(L_fourth_loop);
6628   bind(L_fourth_loop_exit);
6629 }
6630 
6631 /**
6632  * Shift z[] left by 1 bit.
6633  * Preserves x, len, z and zlen registers and modifies rest of the registers.
6634  *
6635  */
6636 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
6637 
6638   Label L_fifth_loop, L_fifth_loop_exit;
6639 
6640   // Fifth loop
6641   // Perform primitiveLeftShift(z, zlen, 1)
6642 
6643   const Register prev_carry = tmp1;
6644   const Register new_carry = tmp4;
6645   const Register value = tmp2;
6646   const Register zidx = tmp3;
6647 
6648   // int zidx, carry;
6649   // long value;
6650   // carry = 0;
6651   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
6652   //    (carry:value)  = (z[i] << 1) | carry ;
6653   //    z[i] = value;
6654   // }
6655 
6656   movl(zidx, zlen);
6657   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
6658 
6659   bind(L_fifth_loop);
6660   decl(zidx);  // Use decl to preserve carry flag
6661   decl(zidx);
6662   jccb(Assembler::negative, L_fifth_loop_exit);
6663 
6664   if (UseBMI2Instructions) {
6665      movq(value, Address(z, zidx, Address::times_4, 0));
6666      rclq(value, 1);
6667      rorxq(value, value, 32);
6668      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6669   }
6670   else {
6671     // clear new_carry
6672     xorl(new_carry, new_carry);
6673 
6674     // Shift z[i] by 1, or in previous carry and save new carry
6675     movq(value, Address(z, zidx, Address::times_4, 0));
6676     shlq(value, 1);
6677     adcl(new_carry, 0);
6678 
6679     orq(value, prev_carry);
6680     rorq(value, 0x20);
6681     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6682 
6683     // Set previous carry = new carry
6684     movl(prev_carry, new_carry);
6685   }
6686   jmp(L_fifth_loop);
6687 
6688   bind(L_fifth_loop_exit);
6689 }
6690 
6691 
6692 /**
6693  * Code for BigInteger::squareToLen() intrinsic
6694  *
6695  * rdi: x
6696  * rsi: len
6697  * r8:  z
6698  * rcx: zlen
6699  * r12: tmp1
6700  * r13: tmp2
6701  * r14: tmp3
6702  * r15: tmp4
6703  * rbx: tmp5
6704  *
6705  */
6706 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6707 
6708   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
6709   push(tmp1);
6710   push(tmp2);
6711   push(tmp3);
6712   push(tmp4);
6713   push(tmp5);
6714 
6715   // First loop
6716   // Store the squares, right shifted one bit (i.e., divided by 2).
6717   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
6718 
6719   // Add in off-diagonal sums.
6720   //
6721   // Second, third (nested) and fourth loops.
6722   // zlen +=2;
6723   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
6724   //    carry = 0;
6725   //    long op2 = x[xidx:xidx+1];
6726   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
6727   //       k -= 2;
6728   //       long op1 = x[j:j+1];
6729   //       long sum = z[k:k+1];
6730   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
6731   //       z[k:k+1] = sum;
6732   //    }
6733   //    add_one_64(z, k, carry, tmp_regs);
6734   // }
6735 
6736   const Register carry = tmp5;
6737   const Register sum = tmp3;
6738   const Register op1 = tmp4;
6739   Register op2 = tmp2;
6740 
6741   push(zlen);
6742   push(len);
6743   addl(zlen,2);
6744   bind(L_second_loop);
6745   xorq(carry, carry);
6746   subl(zlen, 4);
6747   subl(len, 2);
6748   push(zlen);
6749   push(len);
6750   cmpl(len, 0);
6751   jccb(Assembler::lessEqual, L_second_loop_exit);
6752 
6753   // Multiply an array by one 64 bit long.
6754   if (UseBMI2Instructions) {
6755     op2 = rdxReg;
6756     movq(op2, Address(x, len, Address::times_4,  0));
6757     rorxq(op2, op2, 32);
6758   }
6759   else {
6760     movq(op2, Address(x, len, Address::times_4,  0));
6761     rorq(op2, 32);
6762   }
6763 
6764   bind(L_third_loop);
6765   decrementl(len);
6766   jccb(Assembler::negative, L_third_loop_exit);
6767   decrementl(len);
6768   jccb(Assembler::negative, L_last_x);
6769 
6770   movq(op1, Address(x, len, Address::times_4,  0));
6771   rorq(op1, 32);
6772 
6773   bind(L_multiply);
6774   subl(zlen, 2);
6775   movq(sum, Address(z, zlen, Address::times_4,  0));
6776 
6777   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
6778   if (UseBMI2Instructions) {
6779     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
6780   }
6781   else {
6782     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6783   }
6784 
6785   movq(Address(z, zlen, Address::times_4, 0), sum);
6786 
6787   jmp(L_third_loop);
6788   bind(L_third_loop_exit);
6789 
6790   // Fourth loop
6791   // Add 64 bit long carry into z with carry propagation.
6792   // Uses offsetted zlen.
6793   add_one_64(z, zlen, carry, tmp1);
6794 
6795   pop(len);
6796   pop(zlen);
6797   jmp(L_second_loop);
6798 
6799   // Next infrequent code is moved outside loops.
6800   bind(L_last_x);
6801   movl(op1, Address(x, 0));
6802   jmp(L_multiply);
6803 
6804   bind(L_second_loop_exit);
6805   pop(len);
6806   pop(zlen);
6807   pop(len);
6808   pop(zlen);
6809 
6810   // Fifth loop
6811   // Shift z left 1 bit.
6812   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
6813 
6814   // z[zlen-1] |= x[len-1] & 1;
6815   movl(tmp3, Address(x, len, Address::times_4, -4));
6816   andl(tmp3, 1);
6817   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
6818 
6819   pop(tmp5);
6820   pop(tmp4);
6821   pop(tmp3);
6822   pop(tmp2);
6823   pop(tmp1);
6824 }
6825 
6826 /**
6827  * Helper function for mul_add()
6828  * Multiply the in[] by int k and add to out[] starting at offset offs using
6829  * 128 bit by 32 bit multiply and return the carry in tmp5.
6830  * Only quad int aligned length of in[] is operated on in this function.
6831  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
6832  * This function preserves out, in and k registers.
6833  * len and offset point to the appropriate index in "in" & "out" correspondingly
6834  * tmp5 has the carry.
6835  * other registers are temporary and are modified.
6836  *
6837  */
6838 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
6839   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
6840   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6841 
6842   Label L_first_loop, L_first_loop_exit;
6843 
6844   movl(tmp1, len);
6845   shrl(tmp1, 2);
6846 
6847   bind(L_first_loop);
6848   subl(tmp1, 1);
6849   jccb(Assembler::negative, L_first_loop_exit);
6850 
6851   subl(len, 4);
6852   subl(offset, 4);
6853 
6854   Register op2 = tmp2;
6855   const Register sum = tmp3;
6856   const Register op1 = tmp4;
6857   const Register carry = tmp5;
6858 
6859   if (UseBMI2Instructions) {
6860     op2 = rdxReg;
6861   }
6862 
6863   movq(op1, Address(in, len, Address::times_4,  8));
6864   rorq(op1, 32);
6865   movq(sum, Address(out, offset, Address::times_4,  8));
6866   rorq(sum, 32);
6867   if (UseBMI2Instructions) {
6868     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6869   }
6870   else {
6871     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6872   }
6873   // Store back in big endian from little endian
6874   rorq(sum, 0x20);
6875   movq(Address(out, offset, Address::times_4,  8), sum);
6876 
6877   movq(op1, Address(in, len, Address::times_4,  0));
6878   rorq(op1, 32);
6879   movq(sum, Address(out, offset, Address::times_4,  0));
6880   rorq(sum, 32);
6881   if (UseBMI2Instructions) {
6882     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6883   }
6884   else {
6885     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6886   }
6887   // Store back in big endian from little endian
6888   rorq(sum, 0x20);
6889   movq(Address(out, offset, Address::times_4,  0), sum);
6890 
6891   jmp(L_first_loop);
6892   bind(L_first_loop_exit);
6893 }
6894 
6895 /**
6896  * Code for BigInteger::mulAdd() intrinsic
6897  *
6898  * rdi: out
6899  * rsi: in
6900  * r11: offs (out.length - offset)
6901  * rcx: len
6902  * r8:  k
6903  * r12: tmp1
6904  * r13: tmp2
6905  * r14: tmp3
6906  * r15: tmp4
6907  * rbx: tmp5
6908  * Multiply the in[] by word k and add to out[], return the carry in rax
6909  */
6910 void MacroAssembler::mul_add(Register out, Register in, Register offs,
6911    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
6912    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6913 
6914   Label L_carry, L_last_in, L_done;
6915 
6916 // carry = 0;
6917 // for (int j=len-1; j >= 0; j--) {
6918 //    long product = (in[j] & LONG_MASK) * kLong +
6919 //                   (out[offs] & LONG_MASK) + carry;
6920 //    out[offs--] = (int)product;
6921 //    carry = product >>> 32;
6922 // }
6923 //
6924   push(tmp1);
6925   push(tmp2);
6926   push(tmp3);
6927   push(tmp4);
6928   push(tmp5);
6929 
6930   Register op2 = tmp2;
6931   const Register sum = tmp3;
6932   const Register op1 = tmp4;
6933   const Register carry =  tmp5;
6934 
6935   if (UseBMI2Instructions) {
6936     op2 = rdxReg;
6937     movl(op2, k);
6938   }
6939   else {
6940     movl(op2, k);
6941   }
6942 
6943   xorq(carry, carry);
6944 
6945   //First loop
6946 
6947   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
6948   //The carry is in tmp5
6949   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
6950 
6951   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
6952   decrementl(len);
6953   jccb(Assembler::negative, L_carry);
6954   decrementl(len);
6955   jccb(Assembler::negative, L_last_in);
6956 
6957   movq(op1, Address(in, len, Address::times_4,  0));
6958   rorq(op1, 32);
6959 
6960   subl(offs, 2);
6961   movq(sum, Address(out, offs, Address::times_4,  0));
6962   rorq(sum, 32);
6963 
6964   if (UseBMI2Instructions) {
6965     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6966   }
6967   else {
6968     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6969   }
6970 
6971   // Store back in big endian from little endian
6972   rorq(sum, 0x20);
6973   movq(Address(out, offs, Address::times_4,  0), sum);
6974 
6975   testl(len, len);
6976   jccb(Assembler::zero, L_carry);
6977 
6978   //Multiply the last in[] entry, if any
6979   bind(L_last_in);
6980   movl(op1, Address(in, 0));
6981   movl(sum, Address(out, offs, Address::times_4,  -4));
6982 
6983   movl(raxReg, k);
6984   mull(op1); //tmp4 * eax -> edx:eax
6985   addl(sum, carry);
6986   adcl(rdxReg, 0);
6987   addl(sum, raxReg);
6988   adcl(rdxReg, 0);
6989   movl(carry, rdxReg);
6990 
6991   movl(Address(out, offs, Address::times_4,  -4), sum);
6992 
6993   bind(L_carry);
6994   //return tmp5/carry as carry in rax
6995   movl(rax, carry);
6996 
6997   bind(L_done);
6998   pop(tmp5);
6999   pop(tmp4);
7000   pop(tmp3);
7001   pop(tmp2);
7002   pop(tmp1);
7003 }
7004 #endif
7005 
7006 /**
7007  * Emits code to update CRC-32 with a byte value according to constants in table
7008  *
7009  * @param [in,out]crc   Register containing the crc.
7010  * @param [in]val       Register containing the byte to fold into the CRC.
7011  * @param [in]table     Register containing the table of crc constants.
7012  *
7013  * uint32_t crc;
7014  * val = crc_table[(val ^ crc) & 0xFF];
7015  * crc = val ^ (crc >> 8);
7016  *
7017  */
7018 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7019   xorl(val, crc);
7020   andl(val, 0xFF);
7021   shrl(crc, 8); // unsigned shift
7022   xorl(crc, Address(table, val, Address::times_4, 0));
7023 }
7024 
7025 /**
7026  * Fold 128-bit data chunk
7027  */
7028 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7029   if (UseAVX > 0) {
7030     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7031     vpclmulldq(xcrc, xK, xcrc); // [63:0]
7032     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7033     pxor(xcrc, xtmp);
7034   } else {
7035     movdqa(xtmp, xcrc);
7036     pclmulhdq(xtmp, xK);   // [123:64]
7037     pclmulldq(xcrc, xK);   // [63:0]
7038     pxor(xcrc, xtmp);
7039     movdqu(xtmp, Address(buf, offset));
7040     pxor(xcrc, xtmp);
7041   }
7042 }
7043 
7044 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7045   if (UseAVX > 0) {
7046     vpclmulhdq(xtmp, xK, xcrc);
7047     vpclmulldq(xcrc, xK, xcrc);
7048     pxor(xcrc, xbuf);
7049     pxor(xcrc, xtmp);
7050   } else {
7051     movdqa(xtmp, xcrc);
7052     pclmulhdq(xtmp, xK);
7053     pclmulldq(xcrc, xK);
7054     pxor(xcrc, xbuf);
7055     pxor(xcrc, xtmp);
7056   }
7057 }
7058 
7059 /**
7060  * 8-bit folds to compute 32-bit CRC
7061  *
7062  * uint64_t xcrc;
7063  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7064  */
7065 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7066   movdl(tmp, xcrc);
7067   andl(tmp, 0xFF);
7068   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7069   psrldq(xcrc, 1); // unsigned shift one byte
7070   pxor(xcrc, xtmp);
7071 }
7072 
7073 /**
7074  * uint32_t crc;
7075  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7076  */
7077 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7078   movl(tmp, crc);
7079   andl(tmp, 0xFF);
7080   shrl(crc, 8);
7081   xorl(crc, Address(table, tmp, Address::times_4, 0));
7082 }
7083 
7084 /**
7085  * @param crc   register containing existing CRC (32-bit)
7086  * @param buf   register pointing to input byte buffer (byte*)
7087  * @param len   register containing number of bytes
7088  * @param table register that will contain address of CRC table
7089  * @param tmp   scratch register
7090  */
7091 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7092   assert_different_registers(crc, buf, len, table, tmp, rax);
7093 
7094   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7095   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7096 
7097   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7098   // context for the registers used, where all instructions below are using 128-bit mode
7099   // On EVEX without VL and BW, these instructions will all be AVX.
7100   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7101   notl(crc); // ~crc
7102   cmpl(len, 16);
7103   jcc(Assembler::less, L_tail);
7104 
7105   // Align buffer to 16 bytes
7106   movl(tmp, buf);
7107   andl(tmp, 0xF);
7108   jccb(Assembler::zero, L_aligned);
7109   subl(tmp,  16);
7110   addl(len, tmp);
7111 
7112   align(4);
7113   BIND(L_align_loop);
7114   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7115   update_byte_crc32(crc, rax, table);
7116   increment(buf);
7117   incrementl(tmp);
7118   jccb(Assembler::less, L_align_loop);
7119 
7120   BIND(L_aligned);
7121   movl(tmp, len); // save
7122   shrl(len, 4);
7123   jcc(Assembler::zero, L_tail_restore);
7124 
7125   // Fold crc into first bytes of vector
7126   movdqa(xmm1, Address(buf, 0));
7127   movdl(rax, xmm1);
7128   xorl(crc, rax);
7129   if (VM_Version::supports_sse4_1()) {
7130     pinsrd(xmm1, crc, 0);
7131   } else {
7132     pinsrw(xmm1, crc, 0);
7133     shrl(crc, 16);
7134     pinsrw(xmm1, crc, 1);
7135   }
7136   addptr(buf, 16);
7137   subl(len, 4); // len > 0
7138   jcc(Assembler::less, L_fold_tail);
7139 
7140   movdqa(xmm2, Address(buf,  0));
7141   movdqa(xmm3, Address(buf, 16));
7142   movdqa(xmm4, Address(buf, 32));
7143   addptr(buf, 48);
7144   subl(len, 3);
7145   jcc(Assembler::lessEqual, L_fold_512b);
7146 
7147   // Fold total 512 bits of polynomial on each iteration,
7148   // 128 bits per each of 4 parallel streams.
7149   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7150 
7151   align32();
7152   BIND(L_fold_512b_loop);
7153   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7154   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7155   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7156   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7157   addptr(buf, 64);
7158   subl(len, 4);
7159   jcc(Assembler::greater, L_fold_512b_loop);
7160 
7161   // Fold 512 bits to 128 bits.
7162   BIND(L_fold_512b);
7163   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7164   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7165   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7166   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7167 
7168   // Fold the rest of 128 bits data chunks
7169   BIND(L_fold_tail);
7170   addl(len, 3);
7171   jccb(Assembler::lessEqual, L_fold_128b);
7172   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7173 
7174   BIND(L_fold_tail_loop);
7175   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7176   addptr(buf, 16);
7177   decrementl(len);
7178   jccb(Assembler::greater, L_fold_tail_loop);
7179 
7180   // Fold 128 bits in xmm1 down into 32 bits in crc register.
7181   BIND(L_fold_128b);
7182   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7183   if (UseAVX > 0) {
7184     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7185     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7186     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7187   } else {
7188     movdqa(xmm2, xmm0);
7189     pclmulqdq(xmm2, xmm1, 0x1);
7190     movdqa(xmm3, xmm0);
7191     pand(xmm3, xmm2);
7192     pclmulqdq(xmm0, xmm3, 0x1);
7193   }
7194   psrldq(xmm1, 8);
7195   psrldq(xmm2, 4);
7196   pxor(xmm0, xmm1);
7197   pxor(xmm0, xmm2);
7198 
7199   // 8 8-bit folds to compute 32-bit CRC.
7200   for (int j = 0; j < 4; j++) {
7201     fold_8bit_crc32(xmm0, table, xmm1, rax);
7202   }
7203   movdl(crc, xmm0); // mov 32 bits to general register
7204   for (int j = 0; j < 4; j++) {
7205     fold_8bit_crc32(crc, table, rax);
7206   }
7207 
7208   BIND(L_tail_restore);
7209   movl(len, tmp); // restore
7210   BIND(L_tail);
7211   andl(len, 0xf);
7212   jccb(Assembler::zero, L_exit);
7213 
7214   // Fold the rest of bytes
7215   align(4);
7216   BIND(L_tail_loop);
7217   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7218   update_byte_crc32(crc, rax, table);
7219   increment(buf);
7220   decrementl(len);
7221   jccb(Assembler::greater, L_tail_loop);
7222 
7223   BIND(L_exit);
7224   notl(crc); // ~c
7225 }
7226 
7227 #ifdef _LP64
7228 // Helper function for AVX 512 CRC32
7229 // Fold 512-bit data chunks
7230 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7231                                              Register pos, int offset) {
7232   evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7233   evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7234   evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7235   evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7236   evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7237 }
7238 
7239 // Helper function for AVX 512 CRC32
7240 // Compute CRC32 for < 256B buffers
7241 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
7242                                               Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7243                                               Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7244 
7245   Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7246   Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7247   Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7248 
7249   // check if there is enough buffer to be able to fold 16B at a time
7250   cmpl(len, 32);
7251   jcc(Assembler::less, L_less_than_32);
7252 
7253   // if there is, load the constants
7254   movdqu(xmm10, Address(table, 1 * 16));    //rk1 and rk2 in xmm10
7255   movdl(xmm0, crc);                        // get the initial crc value
7256   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7257   pxor(xmm7, xmm0);
7258 
7259   // update the buffer pointer
7260   addl(pos, 16);
7261   //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7262   subl(len, 32);
7263   jmp(L_16B_reduction_loop);
7264 
7265   bind(L_less_than_32);
7266   //mov initial crc to the return value. this is necessary for zero - length buffers.
7267   movl(rax, crc);
7268   testl(len, len);
7269   jcc(Assembler::equal, L_cleanup);
7270 
7271   movdl(xmm0, crc);                        //get the initial crc value
7272 
7273   cmpl(len, 16);
7274   jcc(Assembler::equal, L_exact_16_left);
7275   jcc(Assembler::less, L_less_than_16_left);
7276 
7277   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7278   pxor(xmm7, xmm0);                       //xor the initial crc value
7279   addl(pos, 16);
7280   subl(len, 16);
7281   movdqu(xmm10, Address(table, 1 * 16));    // rk1 and rk2 in xmm10
7282   jmp(L_get_last_two_xmms);
7283 
7284   bind(L_less_than_16_left);
7285   //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7286   pxor(xmm1, xmm1);
7287   movptr(tmp1, rsp);
7288   movdqu(Address(tmp1, 0 * 16), xmm1);
7289 
7290   cmpl(len, 4);
7291   jcc(Assembler::less, L_only_less_than_4);
7292 
7293   //backup the counter value
7294   movl(tmp2, len);
7295   cmpl(len, 8);
7296   jcc(Assembler::less, L_less_than_8_left);
7297 
7298   //load 8 Bytes
7299   movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7300   movq(Address(tmp1, 0 * 16), rax);
7301   addptr(tmp1, 8);
7302   subl(len, 8);
7303   addl(pos, 8);
7304 
7305   bind(L_less_than_8_left);
7306   cmpl(len, 4);
7307   jcc(Assembler::less, L_less_than_4_left);
7308 
7309   //load 4 Bytes
7310   movl(rax, Address(buf, pos, Address::times_1, 0));
7311   movl(Address(tmp1, 0 * 16), rax);
7312   addptr(tmp1, 4);
7313   subl(len, 4);
7314   addl(pos, 4);
7315 
7316   bind(L_less_than_4_left);
7317   cmpl(len, 2);
7318   jcc(Assembler::less, L_less_than_2_left);
7319 
7320   // load 2 Bytes
7321   movw(rax, Address(buf, pos, Address::times_1, 0));
7322   movl(Address(tmp1, 0 * 16), rax);
7323   addptr(tmp1, 2);
7324   subl(len, 2);
7325   addl(pos, 2);
7326 
7327   bind(L_less_than_2_left);
7328   cmpl(len, 1);
7329   jcc(Assembler::less, L_zero_left);
7330 
7331   // load 1 Byte
7332   movb(rax, Address(buf, pos, Address::times_1, 0));
7333   movb(Address(tmp1, 0 * 16), rax);
7334 
7335   bind(L_zero_left);
7336   movdqu(xmm7, Address(rsp, 0));
7337   pxor(xmm7, xmm0);                       //xor the initial crc value
7338 
7339   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7340   movdqu(xmm0, Address(rax, tmp2));
7341   pshufb(xmm7, xmm0);
7342   jmp(L_128_done);
7343 
7344   bind(L_exact_16_left);
7345   movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7346   pxor(xmm7, xmm0);                       //xor the initial crc value
7347   jmp(L_128_done);
7348 
7349   bind(L_only_less_than_4);
7350   cmpl(len, 3);
7351   jcc(Assembler::less, L_only_less_than_3);
7352 
7353   // load 3 Bytes
7354   movb(rax, Address(buf, pos, Address::times_1, 0));
7355   movb(Address(tmp1, 0), rax);
7356 
7357   movb(rax, Address(buf, pos, Address::times_1, 1));
7358   movb(Address(tmp1, 1), rax);
7359 
7360   movb(rax, Address(buf, pos, Address::times_1, 2));
7361   movb(Address(tmp1, 2), rax);
7362 
7363   movdqu(xmm7, Address(rsp, 0));
7364   pxor(xmm7, xmm0);                     //xor the initial crc value
7365 
7366   pslldq(xmm7, 0x5);
7367   jmp(L_barrett);
7368   bind(L_only_less_than_3);
7369   cmpl(len, 2);
7370   jcc(Assembler::less, L_only_less_than_2);
7371 
7372   // load 2 Bytes
7373   movb(rax, Address(buf, pos, Address::times_1, 0));
7374   movb(Address(tmp1, 0), rax);
7375 
7376   movb(rax, Address(buf, pos, Address::times_1, 1));
7377   movb(Address(tmp1, 1), rax);
7378 
7379   movdqu(xmm7, Address(rsp, 0));
7380   pxor(xmm7, xmm0);                     //xor the initial crc value
7381 
7382   pslldq(xmm7, 0x6);
7383   jmp(L_barrett);
7384 
7385   bind(L_only_less_than_2);
7386   //load 1 Byte
7387   movb(rax, Address(buf, pos, Address::times_1, 0));
7388   movb(Address(tmp1, 0), rax);
7389 
7390   movdqu(xmm7, Address(rsp, 0));
7391   pxor(xmm7, xmm0);                     //xor the initial crc value
7392 
7393   pslldq(xmm7, 0x7);
7394 }
7395 
7396 /**
7397 * Compute CRC32 using AVX512 instructions
7398 * param crc   register containing existing CRC (32-bit)
7399 * param buf   register pointing to input byte buffer (byte*)
7400 * param len   register containing number of bytes
7401 * param table address of crc or crc32c table
7402 * param tmp1  scratch register
7403 * param tmp2  scratch register
7404 * return rax  result register
7405 *
7406 * This routine is identical for crc32c with the exception of the precomputed constant
7407 * table which will be passed as the table argument.  The calculation steps are
7408 * the same for both variants.
7409 */
7410 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
7411   assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
7412 
7413   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7414   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7415   Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7416   Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7417   Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
7418 
7419   const Register pos = r12;
7420   push(r12);
7421   subptr(rsp, 16 * 2 + 8);
7422 
7423   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7424   // context for the registers used, where all instructions below are using 128-bit mode
7425   // On EVEX without VL and BW, these instructions will all be AVX.
7426   movl(pos, 0);
7427 
7428   // check if smaller than 256B
7429   cmpl(len, 256);
7430   jcc(Assembler::less, L_less_than_256);
7431 
7432   // load the initial crc value
7433   movdl(xmm10, crc);
7434 
7435   // receive the initial 64B data, xor the initial crc value
7436   evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
7437   evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
7438   evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
7439   evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
7440 
7441   subl(len, 256);
7442   cmpl(len, 256);
7443   jcc(Assembler::less, L_fold_128_B_loop);
7444 
7445   evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
7446   evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
7447   evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
7448   subl(len, 256);
7449 
7450   bind(L_fold_256_B_loop);
7451   addl(pos, 256);
7452   fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
7453   fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
7454   fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
7455   fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
7456 
7457   subl(len, 256);
7458   jcc(Assembler::greaterEqual, L_fold_256_B_loop);
7459 
7460   // Fold 256 into 128
7461   addl(pos, 256);
7462   evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
7463   evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
7464   vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
7465 
7466   evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
7467   evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
7468   vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
7469 
7470   evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
7471   evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
7472 
7473   addl(len, 128);
7474   jmp(L_fold_128_B_register);
7475 
7476   // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
7477   // loop will fold 128B at a time until we have 128 + y Bytes of buffer
7478 
7479   // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
7480   bind(L_fold_128_B_loop);
7481   addl(pos, 128);
7482   fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
7483   fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
7484 
7485   subl(len, 128);
7486   jcc(Assembler::greaterEqual, L_fold_128_B_loop);
7487 
7488   addl(pos, 128);
7489 
7490   // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
7491   // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
7492   bind(L_fold_128_B_register);
7493   evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
7494   evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
7495   evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
7496   evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
7497   // save last that has no multiplicand
7498   vextracti64x2(xmm7, xmm4, 3);
7499 
7500   evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
7501   evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
7502   // Needed later in reduction loop
7503   movdqu(xmm10, Address(table, 1 * 16));
7504   vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
7505   vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
7506 
7507   // Swap 1,0,3,2 - 01 00 11 10
7508   evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
7509   evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
7510   vextracti128(xmm5, xmm8, 1);
7511   evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
7512 
7513   // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
7514   // instead of a cmp instruction, we use the negative flag with the jl instruction
7515   addl(len, 128 - 16);
7516   jcc(Assembler::less, L_final_reduction_for_128);
7517 
7518   bind(L_16B_reduction_loop);
7519   vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
7520   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7521   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7522   movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
7523   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7524   addl(pos, 16);
7525   subl(len, 16);
7526   jcc(Assembler::greaterEqual, L_16B_reduction_loop);
7527 
7528   bind(L_final_reduction_for_128);
7529   addl(len, 16);
7530   jcc(Assembler::equal, L_128_done);
7531 
7532   bind(L_get_last_two_xmms);
7533   movdqu(xmm2, xmm7);
7534   addl(pos, len);
7535   movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
7536   subl(pos, len);
7537 
7538   // get rid of the extra data that was loaded before
7539   // load the shift constant
7540   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7541   movdqu(xmm0, Address(rax, len));
7542   addl(rax, len);
7543 
7544   vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7545   //Change mask to 512
7546   vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
7547   vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
7548 
7549   blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
7550   vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
7551   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7552   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7553   vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
7554 
7555   bind(L_128_done);
7556   // compute crc of a 128-bit value
7557   movdqu(xmm10, Address(table, 3 * 16));
7558   movdqu(xmm0, xmm7);
7559 
7560   // 64b fold
7561   vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
7562   vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
7563   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7564 
7565   // 32b fold
7566   movdqu(xmm0, xmm7);
7567   vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
7568   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7569   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7570   jmp(L_barrett);
7571 
7572   bind(L_less_than_256);
7573   kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
7574 
7575   //barrett reduction
7576   bind(L_barrett);
7577   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
7578   movdqu(xmm1, xmm7);
7579   movdqu(xmm2, xmm7);
7580   movdqu(xmm10, Address(table, 4 * 16));
7581 
7582   pclmulqdq(xmm7, xmm10, 0x0);
7583   pxor(xmm7, xmm2);
7584   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
7585   movdqu(xmm2, xmm7);
7586   pclmulqdq(xmm7, xmm10, 0x10);
7587   pxor(xmm7, xmm2);
7588   pxor(xmm7, xmm1);
7589   pextrd(crc, xmm7, 2);
7590 
7591   bind(L_cleanup);
7592   addptr(rsp, 16 * 2 + 8);
7593   pop(r12);
7594 }
7595 
7596 // S. Gueron / Information Processing Letters 112 (2012) 184
7597 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
7598 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
7599 // Output: the 64-bit carry-less product of B * CONST
7600 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
7601                                      Register tmp1, Register tmp2, Register tmp3) {
7602   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7603   if (n > 0) {
7604     addq(tmp3, n * 256 * 8);
7605   }
7606   //    Q1 = TABLEExt[n][B & 0xFF];
7607   movl(tmp1, in);
7608   andl(tmp1, 0x000000FF);
7609   shll(tmp1, 3);
7610   addq(tmp1, tmp3);
7611   movq(tmp1, Address(tmp1, 0));
7612 
7613   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7614   movl(tmp2, in);
7615   shrl(tmp2, 8);
7616   andl(tmp2, 0x000000FF);
7617   shll(tmp2, 3);
7618   addq(tmp2, tmp3);
7619   movq(tmp2, Address(tmp2, 0));
7620 
7621   shlq(tmp2, 8);
7622   xorq(tmp1, tmp2);
7623 
7624   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7625   movl(tmp2, in);
7626   shrl(tmp2, 16);
7627   andl(tmp2, 0x000000FF);
7628   shll(tmp2, 3);
7629   addq(tmp2, tmp3);
7630   movq(tmp2, Address(tmp2, 0));
7631 
7632   shlq(tmp2, 16);
7633   xorq(tmp1, tmp2);
7634 
7635   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7636   shrl(in, 24);
7637   andl(in, 0x000000FF);
7638   shll(in, 3);
7639   addq(in, tmp3);
7640   movq(in, Address(in, 0));
7641 
7642   shlq(in, 24);
7643   xorq(in, tmp1);
7644   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7645 }
7646 
7647 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7648                                       Register in_out,
7649                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7650                                       XMMRegister w_xtmp2,
7651                                       Register tmp1,
7652                                       Register n_tmp2, Register n_tmp3) {
7653   if (is_pclmulqdq_supported) {
7654     movdl(w_xtmp1, in_out); // modified blindly
7655 
7656     movl(tmp1, const_or_pre_comp_const_index);
7657     movdl(w_xtmp2, tmp1);
7658     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7659 
7660     movdq(in_out, w_xtmp1);
7661   } else {
7662     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
7663   }
7664 }
7665 
7666 // Recombination Alternative 2: No bit-reflections
7667 // T1 = (CRC_A * U1) << 1
7668 // T2 = (CRC_B * U2) << 1
7669 // C1 = T1 >> 32
7670 // C2 = T2 >> 32
7671 // T1 = T1 & 0xFFFFFFFF
7672 // T2 = T2 & 0xFFFFFFFF
7673 // T1 = CRC32(0, T1)
7674 // T2 = CRC32(0, T2)
7675 // C1 = C1 ^ T1
7676 // C2 = C2 ^ T2
7677 // CRC = C1 ^ C2 ^ CRC_C
7678 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7679                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7680                                      Register tmp1, Register tmp2,
7681                                      Register n_tmp3) {
7682   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7683   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7684   shlq(in_out, 1);
7685   movl(tmp1, in_out);
7686   shrq(in_out, 32);
7687   xorl(tmp2, tmp2);
7688   crc32(tmp2, tmp1, 4);
7689   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
7690   shlq(in1, 1);
7691   movl(tmp1, in1);
7692   shrq(in1, 32);
7693   xorl(tmp2, tmp2);
7694   crc32(tmp2, tmp1, 4);
7695   xorl(in1, tmp2);
7696   xorl(in_out, in1);
7697   xorl(in_out, in2);
7698 }
7699 
7700 // Set N to predefined value
7701 // Subtract from a length of a buffer
7702 // execute in a loop:
7703 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
7704 // for i = 1 to N do
7705 //  CRC_A = CRC32(CRC_A, A[i])
7706 //  CRC_B = CRC32(CRC_B, B[i])
7707 //  CRC_C = CRC32(CRC_C, C[i])
7708 // end for
7709 // Recombine
7710 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7711                                        Register in_out1, Register in_out2, Register in_out3,
7712                                        Register tmp1, Register tmp2, Register tmp3,
7713                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7714                                        Register tmp4, Register tmp5,
7715                                        Register n_tmp6) {
7716   Label L_processPartitions;
7717   Label L_processPartition;
7718   Label L_exit;
7719 
7720   bind(L_processPartitions);
7721   cmpl(in_out1, 3 * size);
7722   jcc(Assembler::less, L_exit);
7723     xorl(tmp1, tmp1);
7724     xorl(tmp2, tmp2);
7725     movq(tmp3, in_out2);
7726     addq(tmp3, size);
7727 
7728     bind(L_processPartition);
7729       crc32(in_out3, Address(in_out2, 0), 8);
7730       crc32(tmp1, Address(in_out2, size), 8);
7731       crc32(tmp2, Address(in_out2, size * 2), 8);
7732       addq(in_out2, 8);
7733       cmpq(in_out2, tmp3);
7734       jcc(Assembler::less, L_processPartition);
7735     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7736             w_xtmp1, w_xtmp2, w_xtmp3,
7737             tmp4, tmp5,
7738             n_tmp6);
7739     addq(in_out2, 2 * size);
7740     subl(in_out1, 3 * size);
7741     jmp(L_processPartitions);
7742 
7743   bind(L_exit);
7744 }
7745 #else
7746 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
7747                                      Register tmp1, Register tmp2, Register tmp3,
7748                                      XMMRegister xtmp1, XMMRegister xtmp2) {
7749   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7750   if (n > 0) {
7751     addl(tmp3, n * 256 * 8);
7752   }
7753   //    Q1 = TABLEExt[n][B & 0xFF];
7754   movl(tmp1, in_out);
7755   andl(tmp1, 0x000000FF);
7756   shll(tmp1, 3);
7757   addl(tmp1, tmp3);
7758   movq(xtmp1, Address(tmp1, 0));
7759 
7760   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7761   movl(tmp2, in_out);
7762   shrl(tmp2, 8);
7763   andl(tmp2, 0x000000FF);
7764   shll(tmp2, 3);
7765   addl(tmp2, tmp3);
7766   movq(xtmp2, Address(tmp2, 0));
7767 
7768   psllq(xtmp2, 8);
7769   pxor(xtmp1, xtmp2);
7770 
7771   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7772   movl(tmp2, in_out);
7773   shrl(tmp2, 16);
7774   andl(tmp2, 0x000000FF);
7775   shll(tmp2, 3);
7776   addl(tmp2, tmp3);
7777   movq(xtmp2, Address(tmp2, 0));
7778 
7779   psllq(xtmp2, 16);
7780   pxor(xtmp1, xtmp2);
7781 
7782   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7783   shrl(in_out, 24);
7784   andl(in_out, 0x000000FF);
7785   shll(in_out, 3);
7786   addl(in_out, tmp3);
7787   movq(xtmp2, Address(in_out, 0));
7788 
7789   psllq(xtmp2, 24);
7790   pxor(xtmp1, xtmp2); // Result in CXMM
7791   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7792 }
7793 
7794 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7795                                       Register in_out,
7796                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7797                                       XMMRegister w_xtmp2,
7798                                       Register tmp1,
7799                                       Register n_tmp2, Register n_tmp3) {
7800   if (is_pclmulqdq_supported) {
7801     movdl(w_xtmp1, in_out);
7802 
7803     movl(tmp1, const_or_pre_comp_const_index);
7804     movdl(w_xtmp2, tmp1);
7805     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7806     // Keep result in XMM since GPR is 32 bit in length
7807   } else {
7808     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
7809   }
7810 }
7811 
7812 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7813                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7814                                      Register tmp1, Register tmp2,
7815                                      Register n_tmp3) {
7816   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7817   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7818 
7819   psllq(w_xtmp1, 1);
7820   movdl(tmp1, w_xtmp1);
7821   psrlq(w_xtmp1, 32);
7822   movdl(in_out, w_xtmp1);
7823 
7824   xorl(tmp2, tmp2);
7825   crc32(tmp2, tmp1, 4);
7826   xorl(in_out, tmp2);
7827 
7828   psllq(w_xtmp2, 1);
7829   movdl(tmp1, w_xtmp2);
7830   psrlq(w_xtmp2, 32);
7831   movdl(in1, w_xtmp2);
7832 
7833   xorl(tmp2, tmp2);
7834   crc32(tmp2, tmp1, 4);
7835   xorl(in1, tmp2);
7836   xorl(in_out, in1);
7837   xorl(in_out, in2);
7838 }
7839 
7840 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7841                                        Register in_out1, Register in_out2, Register in_out3,
7842                                        Register tmp1, Register tmp2, Register tmp3,
7843                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7844                                        Register tmp4, Register tmp5,
7845                                        Register n_tmp6) {
7846   Label L_processPartitions;
7847   Label L_processPartition;
7848   Label L_exit;
7849 
7850   bind(L_processPartitions);
7851   cmpl(in_out1, 3 * size);
7852   jcc(Assembler::less, L_exit);
7853     xorl(tmp1, tmp1);
7854     xorl(tmp2, tmp2);
7855     movl(tmp3, in_out2);
7856     addl(tmp3, size);
7857 
7858     bind(L_processPartition);
7859       crc32(in_out3, Address(in_out2, 0), 4);
7860       crc32(tmp1, Address(in_out2, size), 4);
7861       crc32(tmp2, Address(in_out2, size*2), 4);
7862       crc32(in_out3, Address(in_out2, 0+4), 4);
7863       crc32(tmp1, Address(in_out2, size+4), 4);
7864       crc32(tmp2, Address(in_out2, size*2+4), 4);
7865       addl(in_out2, 8);
7866       cmpl(in_out2, tmp3);
7867       jcc(Assembler::less, L_processPartition);
7868 
7869         push(tmp3);
7870         push(in_out1);
7871         push(in_out2);
7872         tmp4 = tmp3;
7873         tmp5 = in_out1;
7874         n_tmp6 = in_out2;
7875 
7876       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7877             w_xtmp1, w_xtmp2, w_xtmp3,
7878             tmp4, tmp5,
7879             n_tmp6);
7880 
7881         pop(in_out2);
7882         pop(in_out1);
7883         pop(tmp3);
7884 
7885     addl(in_out2, 2 * size);
7886     subl(in_out1, 3 * size);
7887     jmp(L_processPartitions);
7888 
7889   bind(L_exit);
7890 }
7891 #endif //LP64
7892 
7893 #ifdef _LP64
7894 // Algorithm 2: Pipelined usage of the CRC32 instruction.
7895 // Input: A buffer I of L bytes.
7896 // Output: the CRC32C value of the buffer.
7897 // Notations:
7898 // Write L = 24N + r, with N = floor (L/24).
7899 // r = L mod 24 (0 <= r < 24).
7900 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
7901 // N quadwords, and R consists of r bytes.
7902 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
7903 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
7904 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
7905 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
7906 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7907                                           Register tmp1, Register tmp2, Register tmp3,
7908                                           Register tmp4, Register tmp5, Register tmp6,
7909                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7910                                           bool is_pclmulqdq_supported) {
7911   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7912   Label L_wordByWord;
7913   Label L_byteByByteProlog;
7914   Label L_byteByByte;
7915   Label L_exit;
7916 
7917   if (is_pclmulqdq_supported ) {
7918     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7919     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
7920 
7921     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7922     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7923 
7924     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7925     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7926     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
7927   } else {
7928     const_or_pre_comp_const_index[0] = 1;
7929     const_or_pre_comp_const_index[1] = 0;
7930 
7931     const_or_pre_comp_const_index[2] = 3;
7932     const_or_pre_comp_const_index[3] = 2;
7933 
7934     const_or_pre_comp_const_index[4] = 5;
7935     const_or_pre_comp_const_index[5] = 4;
7936    }
7937   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7938                     in2, in1, in_out,
7939                     tmp1, tmp2, tmp3,
7940                     w_xtmp1, w_xtmp2, w_xtmp3,
7941                     tmp4, tmp5,
7942                     tmp6);
7943   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7944                     in2, in1, in_out,
7945                     tmp1, tmp2, tmp3,
7946                     w_xtmp1, w_xtmp2, w_xtmp3,
7947                     tmp4, tmp5,
7948                     tmp6);
7949   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7950                     in2, in1, in_out,
7951                     tmp1, tmp2, tmp3,
7952                     w_xtmp1, w_xtmp2, w_xtmp3,
7953                     tmp4, tmp5,
7954                     tmp6);
7955   movl(tmp1, in2);
7956   andl(tmp1, 0x00000007);
7957   negl(tmp1);
7958   addl(tmp1, in2);
7959   addq(tmp1, in1);
7960 
7961   BIND(L_wordByWord);
7962   cmpq(in1, tmp1);
7963   jcc(Assembler::greaterEqual, L_byteByByteProlog);
7964     crc32(in_out, Address(in1, 0), 4);
7965     addq(in1, 4);
7966     jmp(L_wordByWord);
7967 
7968   BIND(L_byteByByteProlog);
7969   andl(in2, 0x00000007);
7970   movl(tmp2, 1);
7971 
7972   BIND(L_byteByByte);
7973   cmpl(tmp2, in2);
7974   jccb(Assembler::greater, L_exit);
7975     crc32(in_out, Address(in1, 0), 1);
7976     incq(in1);
7977     incl(tmp2);
7978     jmp(L_byteByByte);
7979 
7980   BIND(L_exit);
7981 }
7982 #else
7983 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7984                                           Register tmp1, Register  tmp2, Register tmp3,
7985                                           Register tmp4, Register  tmp5, Register tmp6,
7986                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7987                                           bool is_pclmulqdq_supported) {
7988   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7989   Label L_wordByWord;
7990   Label L_byteByByteProlog;
7991   Label L_byteByByte;
7992   Label L_exit;
7993 
7994   if (is_pclmulqdq_supported) {
7995     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7996     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
7997 
7998     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7999     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8000 
8001     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8002     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8003   } else {
8004     const_or_pre_comp_const_index[0] = 1;
8005     const_or_pre_comp_const_index[1] = 0;
8006 
8007     const_or_pre_comp_const_index[2] = 3;
8008     const_or_pre_comp_const_index[3] = 2;
8009 
8010     const_or_pre_comp_const_index[4] = 5;
8011     const_or_pre_comp_const_index[5] = 4;
8012   }
8013   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8014                     in2, in1, in_out,
8015                     tmp1, tmp2, tmp3,
8016                     w_xtmp1, w_xtmp2, w_xtmp3,
8017                     tmp4, tmp5,
8018                     tmp6);
8019   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8020                     in2, in1, in_out,
8021                     tmp1, tmp2, tmp3,
8022                     w_xtmp1, w_xtmp2, w_xtmp3,
8023                     tmp4, tmp5,
8024                     tmp6);
8025   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8026                     in2, in1, in_out,
8027                     tmp1, tmp2, tmp3,
8028                     w_xtmp1, w_xtmp2, w_xtmp3,
8029                     tmp4, tmp5,
8030                     tmp6);
8031   movl(tmp1, in2);
8032   andl(tmp1, 0x00000007);
8033   negl(tmp1);
8034   addl(tmp1, in2);
8035   addl(tmp1, in1);
8036 
8037   BIND(L_wordByWord);
8038   cmpl(in1, tmp1);
8039   jcc(Assembler::greaterEqual, L_byteByByteProlog);
8040     crc32(in_out, Address(in1,0), 4);
8041     addl(in1, 4);
8042     jmp(L_wordByWord);
8043 
8044   BIND(L_byteByByteProlog);
8045   andl(in2, 0x00000007);
8046   movl(tmp2, 1);
8047 
8048   BIND(L_byteByByte);
8049   cmpl(tmp2, in2);
8050   jccb(Assembler::greater, L_exit);
8051     movb(tmp1, Address(in1, 0));
8052     crc32(in_out, tmp1, 1);
8053     incl(in1);
8054     incl(tmp2);
8055     jmp(L_byteByByte);
8056 
8057   BIND(L_exit);
8058 }
8059 #endif // LP64
8060 #undef BIND
8061 #undef BLOCK_COMMENT
8062 
8063 // Compress char[] array to byte[].
8064 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
8065 //   @IntrinsicCandidate
8066 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8067 //     for (int i = 0; i < len; i++) {
8068 //       int c = src[srcOff++];
8069 //       if (c >>> 8 != 0) {
8070 //         return 0;
8071 //       }
8072 //       dst[dstOff++] = (byte)c;
8073 //     }
8074 //     return len;
8075 //   }
8076 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8077   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8078   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8079   Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8080   Label copy_chars_loop, return_length, return_zero, done;
8081 
8082   // rsi: src
8083   // rdi: dst
8084   // rdx: len
8085   // rcx: tmp5
8086   // rax: result
8087 
8088   // rsi holds start addr of source char[] to be compressed
8089   // rdi holds start addr of destination byte[]
8090   // rdx holds length
8091 
8092   assert(len != result, "");
8093 
8094   // save length for return
8095   push(len);
8096 
8097   if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8098     VM_Version::supports_avx512vlbw() &&
8099     VM_Version::supports_bmi2()) {
8100 
8101     Label copy_32_loop, copy_loop_tail, below_threshold;
8102 
8103     // alignment
8104     Label post_alignment;
8105 
8106     // if length of the string is less than 16, handle it in an old fashioned way
8107     testl(len, -32);
8108     jcc(Assembler::zero, below_threshold);
8109 
8110     // First check whether a character is compressible ( <= 0xFF).
8111     // Create mask to test for Unicode chars inside zmm vector
8112     movl(result, 0x00FF);
8113     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
8114 
8115     testl(len, -64);
8116     jcc(Assembler::zero, post_alignment);
8117 
8118     movl(tmp5, dst);
8119     andl(tmp5, (32 - 1));
8120     negl(tmp5);
8121     andl(tmp5, (32 - 1));
8122 
8123     // bail out when there is nothing to be done
8124     testl(tmp5, 0xFFFFFFFF);
8125     jcc(Assembler::zero, post_alignment);
8126 
8127     // ~(~0 << len), where len is the # of remaining elements to process
8128     movl(result, 0xFFFFFFFF);
8129     shlxl(result, result, tmp5);
8130     notl(result);
8131     kmovdl(mask2, result);
8132 
8133     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8134     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8135     ktestd(mask1, mask2);
8136     jcc(Assembler::carryClear, return_zero);
8137 
8138     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8139 
8140     addptr(src, tmp5);
8141     addptr(src, tmp5);
8142     addptr(dst, tmp5);
8143     subl(len, tmp5);
8144 
8145     bind(post_alignment);
8146     // end of alignment
8147 
8148     movl(tmp5, len);
8149     andl(tmp5, (32 - 1));    // tail count (in chars)
8150     andl(len, ~(32 - 1));    // vector count (in chars)
8151     jcc(Assembler::zero, copy_loop_tail);
8152 
8153     lea(src, Address(src, len, Address::times_2));
8154     lea(dst, Address(dst, len, Address::times_1));
8155     negptr(len);
8156 
8157     bind(copy_32_loop);
8158     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit);
8159     evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8160     kortestdl(mask1, mask1);
8161     jcc(Assembler::carryClear, return_zero);
8162 
8163     // All elements in current processed chunk are valid candidates for
8164     // compression. Write a truncated byte elements to the memory.
8165     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8166     addptr(len, 32);
8167     jcc(Assembler::notZero, copy_32_loop);
8168 
8169     bind(copy_loop_tail);
8170     // bail out when there is nothing to be done
8171     testl(tmp5, 0xFFFFFFFF);
8172     jcc(Assembler::zero, return_length);
8173 
8174     movl(len, tmp5);
8175 
8176     // ~(~0 << len), where len is the # of remaining elements to process
8177     movl(result, 0xFFFFFFFF);
8178     shlxl(result, result, len);
8179     notl(result);
8180 
8181     kmovdl(mask2, result);
8182 
8183     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8184     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8185     ktestd(mask1, mask2);
8186     jcc(Assembler::carryClear, return_zero);
8187 
8188     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8189     jmp(return_length);
8190 
8191     bind(below_threshold);
8192   }
8193 
8194   if (UseSSE42Intrinsics) {
8195     Label copy_32_loop, copy_16, copy_tail;
8196 
8197     movl(result, len);
8198 
8199     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
8200 
8201     // vectored compression
8202     andl(len, 0xfffffff0);    // vector count (in chars)
8203     andl(result, 0x0000000f);    // tail count (in chars)
8204     testl(len, len);
8205     jcc(Assembler::zero, copy_16);
8206 
8207     // compress 16 chars per iter
8208     movdl(tmp1Reg, tmp5);
8209     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8210     pxor(tmp4Reg, tmp4Reg);
8211 
8212     lea(src, Address(src, len, Address::times_2));
8213     lea(dst, Address(dst, len, Address::times_1));
8214     negptr(len);
8215 
8216     bind(copy_32_loop);
8217     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
8218     por(tmp4Reg, tmp2Reg);
8219     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8220     por(tmp4Reg, tmp3Reg);
8221     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
8222     jcc(Assembler::notZero, return_zero);
8223     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
8224     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8225     addptr(len, 16);
8226     jcc(Assembler::notZero, copy_32_loop);
8227 
8228     // compress next vector of 8 chars (if any)
8229     bind(copy_16);
8230     movl(len, result);
8231     andl(len, 0xfffffff8);    // vector count (in chars)
8232     andl(result, 0x00000007);    // tail count (in chars)
8233     testl(len, len);
8234     jccb(Assembler::zero, copy_tail);
8235 
8236     movdl(tmp1Reg, tmp5);
8237     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8238     pxor(tmp3Reg, tmp3Reg);
8239 
8240     movdqu(tmp2Reg, Address(src, 0));
8241     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
8242     jccb(Assembler::notZero, return_zero);
8243     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
8244     movq(Address(dst, 0), tmp2Reg);
8245     addptr(src, 16);
8246     addptr(dst, 8);
8247 
8248     bind(copy_tail);
8249     movl(len, result);
8250   }
8251   // compress 1 char per iter
8252   testl(len, len);
8253   jccb(Assembler::zero, return_length);
8254   lea(src, Address(src, len, Address::times_2));
8255   lea(dst, Address(dst, len, Address::times_1));
8256   negptr(len);
8257 
8258   bind(copy_chars_loop);
8259   load_unsigned_short(result, Address(src, len, Address::times_2));
8260   testl(result, 0xff00);      // check if Unicode char
8261   jccb(Assembler::notZero, return_zero);
8262   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
8263   increment(len);
8264   jcc(Assembler::notZero, copy_chars_loop);
8265 
8266   // if compression succeeded, return length
8267   bind(return_length);
8268   pop(result);
8269   jmpb(done);
8270 
8271   // if compression failed, return 0
8272   bind(return_zero);
8273   xorl(result, result);
8274   addptr(rsp, wordSize);
8275 
8276   bind(done);
8277 }
8278 
8279 // Inflate byte[] array to char[].
8280 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8281 //   @IntrinsicCandidate
8282 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8283 //     for (int i = 0; i < len; i++) {
8284 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8285 //     }
8286 //   }
8287 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8288   XMMRegister tmp1, Register tmp2, KRegister mask) {
8289   Label copy_chars_loop, done, below_threshold, avx3_threshold;
8290   // rsi: src
8291   // rdi: dst
8292   // rdx: len
8293   // rcx: tmp2
8294 
8295   // rsi holds start addr of source byte[] to be inflated
8296   // rdi holds start addr of destination char[]
8297   // rdx holds length
8298   assert_different_registers(src, dst, len, tmp2);
8299   movl(tmp2, len);
8300   if ((UseAVX > 2) && // AVX512
8301     VM_Version::supports_avx512vlbw() &&
8302     VM_Version::supports_bmi2()) {
8303 
8304     Label copy_32_loop, copy_tail;
8305     Register tmp3_aliased = len;
8306 
8307     // if length of the string is less than 16, handle it in an old fashioned way
8308     testl(len, -16);
8309     jcc(Assembler::zero, below_threshold);
8310 
8311     testl(len, -1 * AVX3Threshold);
8312     jcc(Assembler::zero, avx3_threshold);
8313 
8314     // In order to use only one arithmetic operation for the main loop we use
8315     // this pre-calculation
8316     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8317     andl(len, -32);     // vector count
8318     jccb(Assembler::zero, copy_tail);
8319 
8320     lea(src, Address(src, len, Address::times_1));
8321     lea(dst, Address(dst, len, Address::times_2));
8322     negptr(len);
8323 
8324 
8325     // inflate 32 chars per iter
8326     bind(copy_32_loop);
8327     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8328     evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit);
8329     addptr(len, 32);
8330     jcc(Assembler::notZero, copy_32_loop);
8331 
8332     bind(copy_tail);
8333     // bail out when there is nothing to be done
8334     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8335     jcc(Assembler::zero, done);
8336 
8337     // ~(~0 << length), where length is the # of remaining elements to process
8338     movl(tmp3_aliased, -1);
8339     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8340     notl(tmp3_aliased);
8341     kmovdl(mask, tmp3_aliased);
8342     evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8343     evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8344 
8345     jmp(done);
8346     bind(avx3_threshold);
8347   }
8348   if (UseSSE42Intrinsics) {
8349     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8350 
8351     if (UseAVX > 1) {
8352       andl(tmp2, (16 - 1));
8353       andl(len, -16);
8354       jccb(Assembler::zero, copy_new_tail);
8355     } else {
8356       andl(tmp2, 0x00000007);   // tail count (in chars)
8357       andl(len, 0xfffffff8);    // vector count (in chars)
8358       jccb(Assembler::zero, copy_tail);
8359     }
8360 
8361     // vectored inflation
8362     lea(src, Address(src, len, Address::times_1));
8363     lea(dst, Address(dst, len, Address::times_2));
8364     negptr(len);
8365 
8366     if (UseAVX > 1) {
8367       bind(copy_16_loop);
8368       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8369       vmovdqu(Address(dst, len, Address::times_2), tmp1);
8370       addptr(len, 16);
8371       jcc(Assembler::notZero, copy_16_loop);
8372 
8373       bind(below_threshold);
8374       bind(copy_new_tail);
8375       movl(len, tmp2);
8376       andl(tmp2, 0x00000007);
8377       andl(len, 0xFFFFFFF8);
8378       jccb(Assembler::zero, copy_tail);
8379 
8380       pmovzxbw(tmp1, Address(src, 0));
8381       movdqu(Address(dst, 0), tmp1);
8382       addptr(src, 8);
8383       addptr(dst, 2 * 8);
8384 
8385       jmp(copy_tail, true);
8386     }
8387 
8388     // inflate 8 chars per iter
8389     bind(copy_8_loop);
8390     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
8391     movdqu(Address(dst, len, Address::times_2), tmp1);
8392     addptr(len, 8);
8393     jcc(Assembler::notZero, copy_8_loop);
8394 
8395     bind(copy_tail);
8396     movl(len, tmp2);
8397 
8398     cmpl(len, 4);
8399     jccb(Assembler::less, copy_bytes);
8400 
8401     movdl(tmp1, Address(src, 0));  // load 4 byte chars
8402     pmovzxbw(tmp1, tmp1);
8403     movq(Address(dst, 0), tmp1);
8404     subptr(len, 4);
8405     addptr(src, 4);
8406     addptr(dst, 8);
8407 
8408     bind(copy_bytes);
8409   } else {
8410     bind(below_threshold);
8411   }
8412 
8413   testl(len, len);
8414   jccb(Assembler::zero, done);
8415   lea(src, Address(src, len, Address::times_1));
8416   lea(dst, Address(dst, len, Address::times_2));
8417   negptr(len);
8418 
8419   // inflate 1 char per iter
8420   bind(copy_chars_loop);
8421   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
8422   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
8423   increment(len);
8424   jcc(Assembler::notZero, copy_chars_loop);
8425 
8426   bind(done);
8427 }
8428 
8429 
8430 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) {
8431   switch(type) {
8432     case T_BYTE:
8433     case T_BOOLEAN:
8434       evmovdqub(dst, kmask, src, false, vector_len);
8435       break;
8436     case T_CHAR:
8437     case T_SHORT:
8438       evmovdquw(dst, kmask, src, false, vector_len);
8439       break;
8440     case T_INT:
8441     case T_FLOAT:
8442       evmovdqul(dst, kmask, src, false, vector_len);
8443       break;
8444     case T_LONG:
8445     case T_DOUBLE:
8446       evmovdquq(dst, kmask, src, false, vector_len);
8447       break;
8448     default:
8449       fatal("Unexpected type argument %s", type2name(type));
8450       break;
8451   }
8452 }
8453 
8454 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) {
8455   switch(type) {
8456     case T_BYTE:
8457     case T_BOOLEAN:
8458       evmovdqub(dst, kmask, src, true, vector_len);
8459       break;
8460     case T_CHAR:
8461     case T_SHORT:
8462       evmovdquw(dst, kmask, src, true, vector_len);
8463       break;
8464     case T_INT:
8465     case T_FLOAT:
8466       evmovdqul(dst, kmask, src, true, vector_len);
8467       break;
8468     case T_LONG:
8469     case T_DOUBLE:
8470       evmovdquq(dst, kmask, src, true, vector_len);
8471       break;
8472     default:
8473       fatal("Unexpected type argument %s", type2name(type));
8474       break;
8475   }
8476 }
8477 
8478 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8479   switch(masklen) {
8480     case 2:
8481        knotbl(dst, src);
8482        movl(rtmp, 3);
8483        kmovbl(ktmp, rtmp);
8484        kandbl(dst, ktmp, dst);
8485        break;
8486     case 4:
8487        knotbl(dst, src);
8488        movl(rtmp, 15);
8489        kmovbl(ktmp, rtmp);
8490        kandbl(dst, ktmp, dst);
8491        break;
8492     case 8:
8493        knotbl(dst, src);
8494        break;
8495     case 16:
8496        knotwl(dst, src);
8497        break;
8498     case 32:
8499        knotdl(dst, src);
8500        break;
8501     case 64:
8502        knotql(dst, src);
8503        break;
8504     default:
8505       fatal("Unexpected vector length %d", masklen);
8506       break;
8507   }
8508 }
8509 
8510 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8511   switch(type) {
8512     case T_BOOLEAN:
8513     case T_BYTE:
8514        kandbl(dst, src1, src2);
8515        break;
8516     case T_CHAR:
8517     case T_SHORT:
8518        kandwl(dst, src1, src2);
8519        break;
8520     case T_INT:
8521     case T_FLOAT:
8522        kanddl(dst, src1, src2);
8523        break;
8524     case T_LONG:
8525     case T_DOUBLE:
8526        kandql(dst, src1, src2);
8527        break;
8528     default:
8529       fatal("Unexpected type argument %s", type2name(type));
8530       break;
8531   }
8532 }
8533 
8534 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8535   switch(type) {
8536     case T_BOOLEAN:
8537     case T_BYTE:
8538        korbl(dst, src1, src2);
8539        break;
8540     case T_CHAR:
8541     case T_SHORT:
8542        korwl(dst, src1, src2);
8543        break;
8544     case T_INT:
8545     case T_FLOAT:
8546        kordl(dst, src1, src2);
8547        break;
8548     case T_LONG:
8549     case T_DOUBLE:
8550        korql(dst, src1, src2);
8551        break;
8552     default:
8553       fatal("Unexpected type argument %s", type2name(type));
8554       break;
8555   }
8556 }
8557 
8558 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8559   switch(type) {
8560     case T_BOOLEAN:
8561     case T_BYTE:
8562        kxorbl(dst, src1, src2);
8563        break;
8564     case T_CHAR:
8565     case T_SHORT:
8566        kxorwl(dst, src1, src2);
8567        break;
8568     case T_INT:
8569     case T_FLOAT:
8570        kxordl(dst, src1, src2);
8571        break;
8572     case T_LONG:
8573     case T_DOUBLE:
8574        kxorql(dst, src1, src2);
8575        break;
8576     default:
8577       fatal("Unexpected type argument %s", type2name(type));
8578       break;
8579   }
8580 }
8581 
8582 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8583   switch(type) {
8584     case T_BOOLEAN:
8585     case T_BYTE:
8586       evpermb(dst, mask, nds, src, merge, vector_len); break;
8587     case T_CHAR:
8588     case T_SHORT:
8589       evpermw(dst, mask, nds, src, merge, vector_len); break;
8590     case T_INT:
8591     case T_FLOAT:
8592       evpermd(dst, mask, nds, src, merge, vector_len); break;
8593     case T_LONG:
8594     case T_DOUBLE:
8595       evpermq(dst, mask, nds, src, merge, vector_len); break;
8596     default:
8597       fatal("Unexpected type argument %s", type2name(type)); break;
8598   }
8599 }
8600 
8601 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8602   switch(type) {
8603     case T_BOOLEAN:
8604     case T_BYTE:
8605       evpermb(dst, mask, nds, src, merge, vector_len); break;
8606     case T_CHAR:
8607     case T_SHORT:
8608       evpermw(dst, mask, nds, src, merge, vector_len); break;
8609     case T_INT:
8610     case T_FLOAT:
8611       evpermd(dst, mask, nds, src, merge, vector_len); break;
8612     case T_LONG:
8613     case T_DOUBLE:
8614       evpermq(dst, mask, nds, src, merge, vector_len); break;
8615     default:
8616       fatal("Unexpected type argument %s", type2name(type)); break;
8617   }
8618 }
8619 
8620 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8621   switch(type) {
8622     case T_BYTE:
8623       evpminsb(dst, mask, nds, src, merge, vector_len); break;
8624     case T_SHORT:
8625       evpminsw(dst, mask, nds, src, merge, vector_len); break;
8626     case T_INT:
8627       evpminsd(dst, mask, nds, src, merge, vector_len); break;
8628     case T_LONG:
8629       evpminsq(dst, mask, nds, src, merge, vector_len); break;
8630     default:
8631       fatal("Unexpected type argument %s", type2name(type)); break;
8632   }
8633 }
8634 
8635 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8636   switch(type) {
8637     case T_BYTE:
8638       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8639     case T_SHORT:
8640       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8641     case T_INT:
8642       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8643     case T_LONG:
8644       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8645     default:
8646       fatal("Unexpected type argument %s", type2name(type)); break;
8647   }
8648 }
8649 
8650 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8651   switch(type) {
8652     case T_BYTE:
8653       evpminsb(dst, mask, nds, src, merge, vector_len); break;
8654     case T_SHORT:
8655       evpminsw(dst, mask, nds, src, merge, vector_len); break;
8656     case T_INT:
8657       evpminsd(dst, mask, nds, src, merge, vector_len); break;
8658     case T_LONG:
8659       evpminsq(dst, mask, nds, src, merge, vector_len); break;
8660     default:
8661       fatal("Unexpected type argument %s", type2name(type)); break;
8662   }
8663 }
8664 
8665 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8666   switch(type) {
8667     case T_BYTE:
8668       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8669     case T_SHORT:
8670       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8671     case T_INT:
8672       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8673     case T_LONG:
8674       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8675     default:
8676       fatal("Unexpected type argument %s", type2name(type)); break;
8677   }
8678 }
8679 
8680 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8681   switch(type) {
8682     case T_INT:
8683       evpxord(dst, mask, nds, src, merge, vector_len); break;
8684     case T_LONG:
8685       evpxorq(dst, mask, nds, src, merge, vector_len); break;
8686     default:
8687       fatal("Unexpected type argument %s", type2name(type)); break;
8688   }
8689 }
8690 
8691 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8692   switch(type) {
8693     case T_INT:
8694       evpxord(dst, mask, nds, src, merge, vector_len); break;
8695     case T_LONG:
8696       evpxorq(dst, mask, nds, src, merge, vector_len); break;
8697     default:
8698       fatal("Unexpected type argument %s", type2name(type)); break;
8699   }
8700 }
8701 
8702 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8703   switch(type) {
8704     case T_INT:
8705       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8706     case T_LONG:
8707       evporq(dst, mask, nds, src, merge, vector_len); break;
8708     default:
8709       fatal("Unexpected type argument %s", type2name(type)); break;
8710   }
8711 }
8712 
8713 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8714   switch(type) {
8715     case T_INT:
8716       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8717     case T_LONG:
8718       evporq(dst, mask, nds, src, merge, vector_len); break;
8719     default:
8720       fatal("Unexpected type argument %s", type2name(type)); break;
8721   }
8722 }
8723 
8724 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8725   switch(type) {
8726     case T_INT:
8727       evpandd(dst, mask, nds, src, merge, vector_len); break;
8728     case T_LONG:
8729       evpandq(dst, mask, nds, src, merge, vector_len); break;
8730     default:
8731       fatal("Unexpected type argument %s", type2name(type)); break;
8732   }
8733 }
8734 
8735 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8736   switch(type) {
8737     case T_INT:
8738       evpandd(dst, mask, nds, src, merge, vector_len); break;
8739     case T_LONG:
8740       evpandq(dst, mask, nds, src, merge, vector_len); break;
8741     default:
8742       fatal("Unexpected type argument %s", type2name(type)); break;
8743   }
8744 }
8745 
8746 void MacroAssembler::anytrue(Register dst, uint masklen, KRegister src1, KRegister src2) {
8747    masklen = masklen < 8 ? 8 : masklen;
8748    ktest(masklen, src1, src2);
8749    setb(Assembler::notZero, dst);
8750    movzbl(dst, dst);
8751 }
8752 
8753 void MacroAssembler::alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch) {
8754   if (masklen < 8) {
8755     knotbl(kscratch, src2);
8756     kortestbl(src1, kscratch);
8757     setb(Assembler::carrySet, dst);
8758     movzbl(dst, dst);
8759   } else {
8760     ktest(masklen, src1, src2);
8761     setb(Assembler::carrySet, dst);
8762     movzbl(dst, dst);
8763   }
8764 }
8765 
8766 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
8767   switch(masklen) {
8768     case 8:
8769        kortestbl(src1, src2);
8770        break;
8771     case 16:
8772        kortestwl(src1, src2);
8773        break;
8774     case 32:
8775        kortestdl(src1, src2);
8776        break;
8777     case 64:
8778        kortestql(src1, src2);
8779        break;
8780     default:
8781       fatal("Unexpected mask length %d", masklen);
8782       break;
8783   }
8784 }
8785 
8786 
8787 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
8788   switch(masklen)  {
8789     case 8:
8790        ktestbl(src1, src2);
8791        break;
8792     case 16:
8793        ktestwl(src1, src2);
8794        break;
8795     case 32:
8796        ktestdl(src1, src2);
8797        break;
8798     case 64:
8799        ktestql(src1, src2);
8800        break;
8801     default:
8802       fatal("Unexpected mask length %d", masklen);
8803       break;
8804   }
8805 }
8806 
8807 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8808   switch(type) {
8809     case T_INT:
8810       evprold(dst, mask, src, shift, merge, vlen_enc); break;
8811     case T_LONG:
8812       evprolq(dst, mask, src, shift, merge, vlen_enc); break;
8813     default:
8814       fatal("Unexpected type argument %s", type2name(type)); break;
8815       break;
8816   }
8817 }
8818 
8819 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8820   switch(type) {
8821     case T_INT:
8822       evprord(dst, mask, src, shift, merge, vlen_enc); break;
8823     case T_LONG:
8824       evprorq(dst, mask, src, shift, merge, vlen_enc); break;
8825     default:
8826       fatal("Unexpected type argument %s", type2name(type)); break;
8827   }
8828 }
8829 
8830 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8831   switch(type) {
8832     case T_INT:
8833       evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
8834     case T_LONG:
8835       evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
8836     default:
8837       fatal("Unexpected type argument %s", type2name(type)); break;
8838   }
8839 }
8840 
8841 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8842   switch(type) {
8843     case T_INT:
8844       evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
8845     case T_LONG:
8846       evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
8847     default:
8848       fatal("Unexpected type argument %s", type2name(type)); break;
8849   }
8850 }
8851 #if COMPILER2_OR_JVMCI
8852 
8853 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
8854                                  Register length, Register temp, int vec_enc) {
8855   // Computing mask for predicated vector store.
8856   movptr(temp, -1);
8857   bzhiq(temp, temp, length);
8858   kmov(mask, temp);
8859   evmovdqu(bt, mask, dst, xmm, vec_enc);
8860 }
8861 
8862 // Set memory operation for length "less than" 64 bytes.
8863 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
8864                                        XMMRegister xmm, KRegister mask, Register length,
8865                                        Register temp, bool use64byteVector) {
8866   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8867   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8868   if (!use64byteVector) {
8869     fill32(dst, disp, xmm);
8870     subptr(length, 32 >> shift);
8871     fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
8872   } else {
8873     assert(MaxVectorSize == 64, "vector length != 64");
8874     fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
8875   }
8876 }
8877 
8878 
8879 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
8880                                        XMMRegister xmm, KRegister mask, Register length,
8881                                        Register temp) {
8882   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8883   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8884   fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
8885 }
8886 
8887 
8888 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
8889   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8890   vmovdqu(Address(dst, disp), xmm);
8891 }
8892 
8893 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
8894   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8895   BasicType type[] = {T_BYTE,  T_SHORT,  T_INT,   T_LONG};
8896   if (!use64byteVector) {
8897     fill32(dst, disp, xmm);
8898     fill32(dst, disp + 32, xmm);
8899   } else {
8900     evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit);
8901   }
8902 }
8903 
8904 #ifdef _LP64
8905 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
8906                                         Register count, Register rtmp, XMMRegister xtmp) {
8907   Label L_exit;
8908   Label L_fill_start;
8909   Label L_fill_64_bytes;
8910   Label L_fill_96_bytes;
8911   Label L_fill_128_bytes;
8912   Label L_fill_128_bytes_loop;
8913   Label L_fill_128_loop_header;
8914   Label L_fill_128_bytes_loop_header;
8915   Label L_fill_128_bytes_loop_pre_header;
8916   Label L_fill_zmm_sequence;
8917 
8918   int shift = -1;
8919   int avx3threshold = VM_Version::avx3_threshold();
8920   switch(type) {
8921     case T_BYTE:  shift = 0;
8922       break;
8923     case T_SHORT: shift = 1;
8924       break;
8925     case T_INT:   shift = 2;
8926       break;
8927     /* Uncomment when LONG fill stubs are supported.
8928     case T_LONG:  shift = 3;
8929       break;
8930     */
8931     default:
8932       fatal("Unhandled type: %s\n", type2name(type));
8933   }
8934 
8935   if ((avx3threshold != 0)  || (MaxVectorSize == 32)) {
8936 
8937     if (MaxVectorSize == 64) {
8938       cmpq(count, avx3threshold >> shift);
8939       jcc(Assembler::greater, L_fill_zmm_sequence);
8940     }
8941 
8942     evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
8943 
8944     bind(L_fill_start);
8945 
8946     cmpq(count, 32 >> shift);
8947     jccb(Assembler::greater, L_fill_64_bytes);
8948     fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
8949     jmp(L_exit);
8950 
8951     bind(L_fill_64_bytes);
8952     cmpq(count, 64 >> shift);
8953     jccb(Assembler::greater, L_fill_96_bytes);
8954     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
8955     jmp(L_exit);
8956 
8957     bind(L_fill_96_bytes);
8958     cmpq(count, 96 >> shift);
8959     jccb(Assembler::greater, L_fill_128_bytes);
8960     fill64(to, 0, xtmp);
8961     subq(count, 64 >> shift);
8962     fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
8963     jmp(L_exit);
8964 
8965     bind(L_fill_128_bytes);
8966     cmpq(count, 128 >> shift);
8967     jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
8968     fill64(to, 0, xtmp);
8969     fill32(to, 64, xtmp);
8970     subq(count, 96 >> shift);
8971     fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
8972     jmp(L_exit);
8973 
8974     bind(L_fill_128_bytes_loop_pre_header);
8975     {
8976       mov(rtmp, to);
8977       andq(rtmp, 31);
8978       jccb(Assembler::zero, L_fill_128_bytes_loop_header);
8979       negq(rtmp);
8980       addq(rtmp, 32);
8981       mov64(r8, -1L);
8982       bzhiq(r8, r8, rtmp);
8983       kmovql(k2, r8);
8984       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_256bit);
8985       addq(to, rtmp);
8986       shrq(rtmp, shift);
8987       subq(count, rtmp);
8988     }
8989 
8990     cmpq(count, 128 >> shift);
8991     jcc(Assembler::less, L_fill_start);
8992 
8993     bind(L_fill_128_bytes_loop_header);
8994     subq(count, 128 >> shift);
8995 
8996     align32();
8997     bind(L_fill_128_bytes_loop);
8998       fill64(to, 0, xtmp);
8999       fill64(to, 64, xtmp);
9000       addq(to, 128);
9001       subq(count, 128 >> shift);
9002       jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9003 
9004     addq(count, 128 >> shift);
9005     jcc(Assembler::zero, L_exit);
9006     jmp(L_fill_start);
9007   }
9008 
9009   if (MaxVectorSize == 64) {
9010     // Sequence using 64 byte ZMM register.
9011     Label L_fill_128_bytes_zmm;
9012     Label L_fill_192_bytes_zmm;
9013     Label L_fill_192_bytes_loop_zmm;
9014     Label L_fill_192_bytes_loop_header_zmm;
9015     Label L_fill_192_bytes_loop_pre_header_zmm;
9016     Label L_fill_start_zmm_sequence;
9017 
9018     bind(L_fill_zmm_sequence);
9019     evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9020 
9021     bind(L_fill_start_zmm_sequence);
9022     cmpq(count, 64 >> shift);
9023     jccb(Assembler::greater, L_fill_128_bytes_zmm);
9024     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9025     jmp(L_exit);
9026 
9027     bind(L_fill_128_bytes_zmm);
9028     cmpq(count, 128 >> shift);
9029     jccb(Assembler::greater, L_fill_192_bytes_zmm);
9030     fill64(to, 0, xtmp, true);
9031     subq(count, 64 >> shift);
9032     fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9033     jmp(L_exit);
9034 
9035     bind(L_fill_192_bytes_zmm);
9036     cmpq(count, 192 >> shift);
9037     jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9038     fill64(to, 0, xtmp, true);
9039     fill64(to, 64, xtmp, true);
9040     subq(count, 128 >> shift);
9041     fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9042     jmp(L_exit);
9043 
9044     bind(L_fill_192_bytes_loop_pre_header_zmm);
9045     {
9046       movq(rtmp, to);
9047       andq(rtmp, 63);
9048       jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9049       negq(rtmp);
9050       addq(rtmp, 64);
9051       mov64(r8, -1L);
9052       bzhiq(r8, r8, rtmp);
9053       kmovql(k2, r8);
9054       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_512bit);
9055       addq(to, rtmp);
9056       shrq(rtmp, shift);
9057       subq(count, rtmp);
9058     }
9059 
9060     cmpq(count, 192 >> shift);
9061     jcc(Assembler::less, L_fill_start_zmm_sequence);
9062 
9063     bind(L_fill_192_bytes_loop_header_zmm);
9064     subq(count, 192 >> shift);
9065 
9066     align32();
9067     bind(L_fill_192_bytes_loop_zmm);
9068       fill64(to, 0, xtmp, true);
9069       fill64(to, 64, xtmp, true);
9070       fill64(to, 128, xtmp, true);
9071       addq(to, 192);
9072       subq(count, 192 >> shift);
9073       jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
9074 
9075     addq(count, 192 >> shift);
9076     jcc(Assembler::zero, L_exit);
9077     jmp(L_fill_start_zmm_sequence);
9078   }
9079   bind(L_exit);
9080 }
9081 #endif
9082 #endif //COMPILER2_OR_JVMCI
9083 
9084 
9085 #ifdef _LP64
9086 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9087   Label done;
9088   cvttss2sil(dst, src);
9089   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9090   cmpl(dst, 0x80000000); // float_sign_flip
9091   jccb(Assembler::notEqual, done);
9092   subptr(rsp, 8);
9093   movflt(Address(rsp, 0), src);
9094   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9095   pop(dst);
9096   bind(done);
9097 }
9098 
9099 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9100   Label done;
9101   cvttsd2sil(dst, src);
9102   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9103   cmpl(dst, 0x80000000); // float_sign_flip
9104   jccb(Assembler::notEqual, done);
9105   subptr(rsp, 8);
9106   movdbl(Address(rsp, 0), src);
9107   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9108   pop(dst);
9109   bind(done);
9110 }
9111 
9112 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9113   Label done;
9114   cvttss2siq(dst, src);
9115   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9116   jccb(Assembler::notEqual, done);
9117   subptr(rsp, 8);
9118   movflt(Address(rsp, 0), src);
9119   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9120   pop(dst);
9121   bind(done);
9122 }
9123 
9124 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9125   // Following code is line by line assembly translation rounding algorithm.
9126   // Please refer to java.lang.Math.round(float) algorithm for details.
9127   const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
9128   const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
9129   const int32_t FloatConsts_EXP_BIAS = 127;
9130   const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
9131   const int32_t MINUS_32 = 0xFFFFFFE0;
9132   Label L_special_case, L_block1, L_exit;
9133   movl(rtmp, FloatConsts_EXP_BIT_MASK);
9134   movdl(dst, src);
9135   andl(dst, rtmp);
9136   sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
9137   movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
9138   subl(rtmp, dst);
9139   movl(rcx, rtmp);
9140   movl(dst, MINUS_32);
9141   testl(rtmp, dst);
9142   jccb(Assembler::notEqual, L_special_case);
9143   movdl(dst, src);
9144   andl(dst, FloatConsts_SIGNIF_BIT_MASK);
9145   orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
9146   movdl(rtmp, src);
9147   testl(rtmp, rtmp);
9148   jccb(Assembler::greaterEqual, L_block1);
9149   negl(dst);
9150   bind(L_block1);
9151   sarl(dst);
9152   addl(dst, 0x1);
9153   sarl(dst, 0x1);
9154   jmp(L_exit);
9155   bind(L_special_case);
9156   convert_f2i(dst, src);
9157   bind(L_exit);
9158 }
9159 
9160 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9161   // Following code is line by line assembly translation rounding algorithm.
9162   // Please refer to java.lang.Math.round(double) algorithm for details.
9163   const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
9164   const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
9165   const int64_t DoubleConsts_EXP_BIAS = 1023;
9166   const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
9167   const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
9168   Label L_special_case, L_block1, L_exit;
9169   mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
9170   movq(dst, src);
9171   andq(dst, rtmp);
9172   sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
9173   mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
9174   subq(rtmp, dst);
9175   movq(rcx, rtmp);
9176   mov64(dst, MINUS_64);
9177   testq(rtmp, dst);
9178   jccb(Assembler::notEqual, L_special_case);
9179   movq(dst, src);
9180   mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
9181   andq(dst, rtmp);
9182   mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
9183   orq(dst, rtmp);
9184   movq(rtmp, src);
9185   testq(rtmp, rtmp);
9186   jccb(Assembler::greaterEqual, L_block1);
9187   negq(dst);
9188   bind(L_block1);
9189   sarq(dst);
9190   addq(dst, 0x1);
9191   sarq(dst, 0x1);
9192   jmp(L_exit);
9193   bind(L_special_case);
9194   convert_d2l(dst, src);
9195   bind(L_exit);
9196 }
9197 
9198 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9199   Label done;
9200   cvttsd2siq(dst, src);
9201   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9202   jccb(Assembler::notEqual, done);
9203   subptr(rsp, 8);
9204   movdbl(Address(rsp, 0), src);
9205   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9206   pop(dst);
9207   bind(done);
9208 }
9209 
9210 void MacroAssembler::cache_wb(Address line)
9211 {
9212   // 64 bit cpus always support clflush
9213   assert(VM_Version::supports_clflush(), "clflush should be available");
9214   bool optimized = VM_Version::supports_clflushopt();
9215   bool no_evict = VM_Version::supports_clwb();
9216 
9217   // prefer clwb (writeback without evict) otherwise
9218   // prefer clflushopt (potentially parallel writeback with evict)
9219   // otherwise fallback on clflush (serial writeback with evict)
9220 
9221   if (optimized) {
9222     if (no_evict) {
9223       clwb(line);
9224     } else {
9225       clflushopt(line);
9226     }
9227   } else {
9228     // no need for fence when using CLFLUSH
9229     clflush(line);
9230   }
9231 }
9232 
9233 void MacroAssembler::cache_wbsync(bool is_pre)
9234 {
9235   assert(VM_Version::supports_clflush(), "clflush should be available");
9236   bool optimized = VM_Version::supports_clflushopt();
9237   bool no_evict = VM_Version::supports_clwb();
9238 
9239   // pick the correct implementation
9240 
9241   if (!is_pre && (optimized || no_evict)) {
9242     // need an sfence for post flush when using clflushopt or clwb
9243     // otherwise no no need for any synchroniaztion
9244 
9245     sfence();
9246   }
9247 }
9248 
9249 #endif // _LP64
9250 
9251 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9252   switch (cond) {
9253     // Note some conditions are synonyms for others
9254     case Assembler::zero:         return Assembler::notZero;
9255     case Assembler::notZero:      return Assembler::zero;
9256     case Assembler::less:         return Assembler::greaterEqual;
9257     case Assembler::lessEqual:    return Assembler::greater;
9258     case Assembler::greater:      return Assembler::lessEqual;
9259     case Assembler::greaterEqual: return Assembler::less;
9260     case Assembler::below:        return Assembler::aboveEqual;
9261     case Assembler::belowEqual:   return Assembler::above;
9262     case Assembler::above:        return Assembler::belowEqual;
9263     case Assembler::aboveEqual:   return Assembler::below;
9264     case Assembler::overflow:     return Assembler::noOverflow;
9265     case Assembler::noOverflow:   return Assembler::overflow;
9266     case Assembler::negative:     return Assembler::positive;
9267     case Assembler::positive:     return Assembler::negative;
9268     case Assembler::parity:       return Assembler::noParity;
9269     case Assembler::noParity:     return Assembler::parity;
9270   }
9271   ShouldNotReachHere(); return Assembler::overflow;
9272 }
9273 
9274 SkipIfEqual::SkipIfEqual(
9275     MacroAssembler* masm, const bool* flag_addr, bool value) {
9276   _masm = masm;
9277   _masm->cmp8(ExternalAddress((address)flag_addr), value);
9278   _masm->jcc(Assembler::equal, _label);
9279 }
9280 
9281 SkipIfEqual::~SkipIfEqual() {
9282   _masm->bind(_label);
9283 }
9284 
9285 // 32-bit Windows has its own fast-path implementation
9286 // of get_thread
9287 #if !defined(WIN32) || defined(_LP64)
9288 
9289 // This is simply a call to Thread::current()
9290 void MacroAssembler::get_thread(Register thread) {
9291   if (thread != rax) {
9292     push(rax);
9293   }
9294   LP64_ONLY(push(rdi);)
9295   LP64_ONLY(push(rsi);)
9296   push(rdx);
9297   push(rcx);
9298 #ifdef _LP64
9299   push(r8);
9300   push(r9);
9301   push(r10);
9302   push(r11);
9303 #endif
9304 
9305   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9306 
9307 #ifdef _LP64
9308   pop(r11);
9309   pop(r10);
9310   pop(r9);
9311   pop(r8);
9312 #endif
9313   pop(rcx);
9314   pop(rdx);
9315   LP64_ONLY(pop(rsi);)
9316   LP64_ONLY(pop(rdi);)
9317   if (thread != rax) {
9318     mov(thread, rax);
9319     pop(rax);
9320   }
9321 }
9322 
9323 
9324 #endif // !WIN32 || _LP64