1 /*
2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "code/vmreg.inline.hpp"
30 #include "compiler/oopMap.hpp"
31 #include "utilities/macros.hpp"
32 #include "runtime/rtmLocking.hpp"
33 #include "runtime/vm_version.hpp"
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42 friend class Runtime1; // as_Address()
43
44 public:
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments // the number of arguments to pop after the call
54 );
55
56 protected:
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 Address as_Address(AddressLiteral adr);
91 Address as_Address(ArrayAddress adr);
92
93 // Support for NULL-checks
94 //
95 // Generates code that causes a NULL OS exception if the content of reg is NULL.
96 // If the accessed location is M[reg + offset] and the offset is known, provide the
97 // offset. No explicit code generation is needed if the offset is within a certain
98 // range (0 <= offset <= page_size).
99
100 void null_check(Register reg, int offset = -1);
101 static bool needs_explicit_null_check(intptr_t offset);
102 static bool uses_implicit_null_check(void* address);
103
104 // Required platform-specific helpers for Label::patch_instructions.
105 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
106 void pd_patch_instruction(address branch, address target, const char* file, int line) {
107 unsigned char op = branch[0];
108 assert(op == 0xE8 /* call */ ||
109 op == 0xE9 /* jmp */ ||
110 op == 0xEB /* short jmp */ ||
111 (op & 0xF0) == 0x70 /* short jcc */ ||
112 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
113 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
114 "Invalid opcode at patch point");
115
116 if (op == 0xEB || (op & 0xF0) == 0x70) {
117 // short offset operators (jmp and jcc)
118 char* disp = (char*) &branch[1];
119 int imm8 = target - (address) &disp[1];
120 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
121 file == NULL ? "<NULL>" : file, line);
122 *disp = imm8;
123 } else {
124 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
125 int imm32 = target - (address) &disp[1];
126 *disp = imm32;
127 }
128 }
129
130 // The following 4 methods return the offset of the appropriate move instruction
131
132 // Support for fast byte/short loading with zero extension (depending on particular CPU)
133 int load_unsigned_byte(Register dst, Address src);
134 int load_unsigned_short(Register dst, Address src);
135
136 // Support for fast byte/short loading with sign extension (depending on particular CPU)
137 int load_signed_byte(Register dst, Address src);
138 int load_signed_short(Register dst, Address src);
139
140 // Support for sign-extension (hi:lo = extend_sign(lo))
141 void extend_sign(Register hi, Register lo);
142
143 // Load and store values by size and signed-ness
144 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
145 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
146
147 // Support for inc/dec with optimal instruction selection depending on value
148
149 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
150 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
151
152 void decrementl(Address dst, int value = 1);
153 void decrementl(Register reg, int value = 1);
154
155 void decrementq(Register reg, int value = 1);
156 void decrementq(Address dst, int value = 1);
157
158 void incrementl(Address dst, int value = 1);
159 void incrementl(Register reg, int value = 1);
160
161 void incrementq(Register reg, int value = 1);
162 void incrementq(Address dst, int value = 1);
163
164 // Support optimal SSE move instructions.
165 void movflt(XMMRegister dst, XMMRegister src) {
166 if (dst-> encoding() == src->encoding()) return;
167 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
168 else { movss (dst, src); return; }
169 }
170 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
171 void movflt(XMMRegister dst, AddressLiteral src);
172 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
173
174 // Move with zero extension
175 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
176
177 void movdbl(XMMRegister dst, XMMRegister src) {
178 if (dst-> encoding() == src->encoding()) return;
179 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
180 else { movsd (dst, src); return; }
181 }
182
183 void movdbl(XMMRegister dst, AddressLiteral src);
184
185 void movdbl(XMMRegister dst, Address src) {
186 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
187 else { movlpd(dst, src); return; }
188 }
189 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
190
191 void incrementl(AddressLiteral dst);
192 void incrementl(ArrayAddress dst);
193
194 void incrementq(AddressLiteral dst);
195
196 // Alignment
197 void align64();
198 void align(int modulus);
199 void align(int modulus, int target);
200
201 // A 5 byte nop that is safe for patching (see patch_verified_entry)
202 void fat_nop();
203
204 // Stack frame creation/removal
205 void enter();
206 void leave();
207
208 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
209 // The pointer will be loaded into the thread register.
210 void get_thread(Register thread);
211
212 #ifdef _LP64
213 // Support for argument shuffling
214
215 void move32_64(VMRegPair src, VMRegPair dst);
216 void long_move(VMRegPair src, VMRegPair dst);
217 void float_move(VMRegPair src, VMRegPair dst);
218 void double_move(VMRegPair src, VMRegPair dst);
219 void move_ptr(VMRegPair src, VMRegPair dst);
220 void object_move(OopMap* map,
221 int oop_handle_offset,
222 int framesize_in_slots,
223 VMRegPair src,
224 VMRegPair dst,
225 bool is_receiver,
226 int* receiver_offset);
227 #endif // _LP64
228
229 // Support for VM calls
230 //
231 // It is imperative that all calls into the VM are handled via the call_VM macros.
232 // They make sure that the stack linkage is setup correctly. call_VM's correspond
233 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
234
235
236 void call_VM(Register oop_result,
237 address entry_point,
238 bool check_exceptions = true);
239 void call_VM(Register oop_result,
240 address entry_point,
241 Register arg_1,
242 bool check_exceptions = true);
243 void call_VM(Register oop_result,
244 address entry_point,
245 Register arg_1, Register arg_2,
246 bool check_exceptions = true);
247 void call_VM(Register oop_result,
248 address entry_point,
249 Register arg_1, Register arg_2, Register arg_3,
250 bool check_exceptions = true);
251
252 // Overloadings with last_Java_sp
253 void call_VM(Register oop_result,
254 Register last_java_sp,
255 address entry_point,
256 int number_of_arguments = 0,
257 bool check_exceptions = true);
258 void call_VM(Register oop_result,
259 Register last_java_sp,
260 address entry_point,
261 Register arg_1, bool
262 check_exceptions = true);
263 void call_VM(Register oop_result,
264 Register last_java_sp,
265 address entry_point,
266 Register arg_1, Register arg_2,
267 bool check_exceptions = true);
268 void call_VM(Register oop_result,
269 Register last_java_sp,
270 address entry_point,
271 Register arg_1, Register arg_2, Register arg_3,
272 bool check_exceptions = true);
273
274 void get_vm_result (Register oop_result, Register thread);
275 void get_vm_result_2(Register metadata_result, Register thread);
276
277 // These always tightly bind to MacroAssembler::call_VM_base
278 // bypassing the virtual implementation
279 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
280 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
281 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
282 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
283 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
284
285 void call_VM_leaf0(address entry_point);
286 void call_VM_leaf(address entry_point,
287 int number_of_arguments = 0);
288 void call_VM_leaf(address entry_point,
289 Register arg_1);
290 void call_VM_leaf(address entry_point,
291 Register arg_1, Register arg_2);
292 void call_VM_leaf(address entry_point,
293 Register arg_1, Register arg_2, Register arg_3);
294
295 // These always tightly bind to MacroAssembler::call_VM_leaf_base
296 // bypassing the virtual implementation
297 void super_call_VM_leaf(address entry_point);
298 void super_call_VM_leaf(address entry_point, Register arg_1);
299 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
300 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
301 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
302
303 // last Java Frame (fills frame anchor)
304 void set_last_Java_frame(Register thread,
305 Register last_java_sp,
306 Register last_java_fp,
307 address last_java_pc);
308
309 // thread in the default location (r15_thread on 64bit)
310 void set_last_Java_frame(Register last_java_sp,
311 Register last_java_fp,
312 address last_java_pc);
313
314 void reset_last_Java_frame(Register thread, bool clear_fp);
315
316 // thread in the default location (r15_thread on 64bit)
317 void reset_last_Java_frame(bool clear_fp);
318
319 // jobjects
320 void clear_jweak_tag(Register possibly_jweak);
321 void resolve_jobject(Register value, Register thread, Register tmp);
322
323 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
324 void c2bool(Register x);
325
326 // C++ bool manipulation
327
328 void movbool(Register dst, Address src);
329 void movbool(Address dst, bool boolconst);
330 void movbool(Address dst, Register src);
331 void testbool(Register dst);
332
333 void resolve_oop_handle(Register result, Register tmp = rscratch2);
334 void resolve_weak_handle(Register result, Register tmp);
335 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
336 void load_method_holder_cld(Register rresult, Register rmethod);
337
338 void load_method_holder(Register holder, Register method);
339
340 // oop manipulations
341 void load_klass(Register dst, Register src, Register tmp);
342 void store_klass(Register dst, Register src, Register tmp);
343
344 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
345 Register tmp1, Register thread_tmp);
346 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
347 Register tmp1, Register tmp2);
348
349 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
350 Register thread_tmp = noreg, DecoratorSet decorators = 0);
351 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
352 Register thread_tmp = noreg, DecoratorSet decorators = 0);
353 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
354 Register tmp2 = noreg, DecoratorSet decorators = 0);
355
356 // Used for storing NULL. All other oop constants should be
357 // stored using routines that take a jobject.
358 void store_heap_oop_null(Address dst);
359
360 #ifdef _LP64
361 void store_klass_gap(Register dst, Register src);
362
363 // This dummy is to prevent a call to store_heap_oop from
364 // converting a zero (like NULL) into a Register by giving
365 // the compiler two choices it can't resolve
366
367 void store_heap_oop(Address dst, void* dummy);
368
369 void encode_heap_oop(Register r);
370 void decode_heap_oop(Register r);
371 void encode_heap_oop_not_null(Register r);
372 void decode_heap_oop_not_null(Register r);
373 void encode_heap_oop_not_null(Register dst, Register src);
374 void decode_heap_oop_not_null(Register dst, Register src);
375
376 void set_narrow_oop(Register dst, jobject obj);
377 void set_narrow_oop(Address dst, jobject obj);
378 void cmp_narrow_oop(Register dst, jobject obj);
379 void cmp_narrow_oop(Address dst, jobject obj);
380
381 void encode_klass_not_null(Register r, Register tmp);
382 void decode_klass_not_null(Register r, Register tmp);
383 void encode_and_move_klass_not_null(Register dst, Register src);
384 void decode_and_move_klass_not_null(Register dst, Register src);
385 void set_narrow_klass(Register dst, Klass* k);
386 void set_narrow_klass(Address dst, Klass* k);
387 void cmp_narrow_klass(Register dst, Klass* k);
388 void cmp_narrow_klass(Address dst, Klass* k);
389
390 // if heap base register is used - reinit it with the correct value
391 void reinit_heapbase();
392
393 DEBUG_ONLY(void verify_heapbase(const char* msg);)
394
395 #endif // _LP64
396
397 // Int division/remainder for Java
398 // (as idivl, but checks for special case as described in JVM spec.)
399 // returns idivl instruction offset for implicit exception handling
400 int corrected_idivl(Register reg);
401
402 // Long division/remainder for Java
403 // (as idivq, but checks for special case as described in JVM spec.)
404 // returns idivq instruction offset for implicit exception handling
405 int corrected_idivq(Register reg);
406
407 void int3();
408
409 // Long operation macros for a 32bit cpu
410 // Long negation for Java
411 void lneg(Register hi, Register lo);
412
413 // Long multiplication for Java
414 // (destroys contents of eax, ebx, ecx and edx)
415 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
416
417 // Long shifts for Java
418 // (semantics as described in JVM spec.)
419 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
420 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
421
422 // Long compare for Java
423 // (semantics as described in JVM spec.)
424 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
425
426
427 // misc
428
429 // Sign extension
430 void sign_extend_short(Register reg);
431 void sign_extend_byte(Register reg);
432
433 // Division by power of 2, rounding towards 0
434 void division_with_shift(Register reg, int shift_value);
435
436 #ifndef _LP64
437 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
438 //
439 // CF (corresponds to C0) if x < y
440 // PF (corresponds to C2) if unordered
441 // ZF (corresponds to C3) if x = y
442 //
443 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
444 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
445 void fcmp(Register tmp);
446 // Variant of the above which allows y to be further down the stack
447 // and which only pops x and y if specified. If pop_right is
448 // specified then pop_left must also be specified.
449 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
450
451 // Floating-point comparison for Java
452 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
453 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
454 // (semantics as described in JVM spec.)
455 void fcmp2int(Register dst, bool unordered_is_less);
456 // Variant of the above which allows y to be further down the stack
457 // and which only pops x and y if specified. If pop_right is
458 // specified then pop_left must also be specified.
459 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
460
461 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
462 // tmp is a temporary register, if none is available use noreg
463 void fremr(Register tmp);
464
465 // only if +VerifyFPU
466 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
467 #endif // !LP64
468
469 // dst = c = a * b + c
470 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
471 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
472
473 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
474 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
475 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
476 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
477
478
479 // same as fcmp2int, but using SSE2
480 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
481 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
482
483 // branch to L if FPU flag C2 is set/not set
484 // tmp is a temporary register, if none is available use noreg
485 void jC2 (Register tmp, Label& L);
486 void jnC2(Register tmp, Label& L);
487
488 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
489 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
490 void load_float(Address src);
491
492 // Store float value to 'address'. If UseSSE >= 1, the value is stored
493 // from register xmm0. Otherwise, the value is stored from the FPU stack.
494 void store_float(Address dst);
495
496 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
497 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
498 void load_double(Address src);
499
500 // Store double value to 'address'. If UseSSE >= 2, the value is stored
501 // from register xmm0. Otherwise, the value is stored from the FPU stack.
502 void store_double(Address dst);
503
504 #ifndef _LP64
505 // Pop ST (ffree & fincstp combined)
506 void fpop();
507
508 void empty_FPU_stack();
509 #endif // !_LP64
510
511 void push_IU_state();
512 void pop_IU_state();
513
514 void push_FPU_state();
515 void pop_FPU_state();
516
517 void push_CPU_state();
518 void pop_CPU_state();
519
520 // Round up to a power of two
521 void round_to(Register reg, int modulus);
522
523 // Callee saved registers handling
524 void push_callee_saved_registers();
525 void pop_callee_saved_registers();
526
527 // allocation
528 void eden_allocate(
529 Register thread, // Current thread
530 Register obj, // result: pointer to object after successful allocation
531 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
532 int con_size_in_bytes, // object size in bytes if known at compile time
533 Register t1, // temp register
534 Label& slow_case // continuation point if fast allocation fails
535 );
536 void tlab_allocate(
537 Register thread, // Current thread
538 Register obj, // result: pointer to object after successful allocation
539 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
540 int con_size_in_bytes, // object size in bytes if known at compile time
541 Register t1, // temp register
542 Register t2, // temp register
543 Label& slow_case // continuation point if fast allocation fails
544 );
545 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
546
547 // interface method calling
548 void lookup_interface_method(Register recv_klass,
549 Register intf_klass,
550 RegisterOrConstant itable_index,
551 Register method_result,
552 Register scan_temp,
553 Label& no_such_interface,
554 bool return_method = true);
555
556 // virtual method calling
557 void lookup_virtual_method(Register recv_klass,
558 RegisterOrConstant vtable_index,
559 Register method_result);
560
561 // Test sub_klass against super_klass, with fast and slow paths.
562
563 // The fast path produces a tri-state answer: yes / no / maybe-slow.
564 // One of the three labels can be NULL, meaning take the fall-through.
565 // If super_check_offset is -1, the value is loaded up from super_klass.
566 // No registers are killed, except temp_reg.
567 void check_klass_subtype_fast_path(Register sub_klass,
568 Register super_klass,
569 Register temp_reg,
570 Label* L_success,
571 Label* L_failure,
572 Label* L_slow_path,
573 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
574
575 // The rest of the type check; must be wired to a corresponding fast path.
576 // It does not repeat the fast path logic, so don't use it standalone.
577 // The temp_reg and temp2_reg can be noreg, if no temps are available.
578 // Updates the sub's secondary super cache as necessary.
579 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
580 void check_klass_subtype_slow_path(Register sub_klass,
581 Register super_klass,
582 Register temp_reg,
583 Register temp2_reg,
584 Label* L_success,
585 Label* L_failure,
586 bool set_cond_codes = false);
587
588 // Simplified, combined version, good for typical uses.
589 // Falls through on failure.
590 void check_klass_subtype(Register sub_klass,
591 Register super_klass,
592 Register temp_reg,
593 Label& L_success);
594
595 void clinit_barrier(Register klass,
596 Register thread,
597 Label* L_fast_path = NULL,
598 Label* L_slow_path = NULL);
599
600 // method handles (JSR 292)
601 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
602
603 // Debugging
604
605 // only if +VerifyOops
606 void _verify_oop(Register reg, const char* s, const char* file, int line);
607 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
608
609 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
610 if (VerifyOops) {
611 _verify_oop(reg, s, file, line);
612 }
613 }
614 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
615 if (VerifyOops) {
616 _verify_oop_addr(reg, s, file, line);
617 }
618 }
619
620 // TODO: verify method and klass metadata (compare against vptr?)
621 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
622 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
623
624 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
625 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
626 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
627 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
628 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
629
630 // Verify or restore cpu control state after JNI call
631 void restore_cpu_control_state_after_jni();
632
633 // prints msg, dumps registers and stops execution
634 void stop(const char* msg);
635
636 // prints msg and continues
637 void warn(const char* msg);
638
639 // dumps registers and other state
640 void print_state();
641
642 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
643 static void debug64(char* msg, int64_t pc, int64_t regs[]);
644 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
645 static void print_state64(int64_t pc, int64_t regs[]);
646
647 void os_breakpoint();
648
649 void untested() { stop("untested"); }
650
651 void unimplemented(const char* what = "");
652
653 void should_not_reach_here() { stop("should not reach here"); }
654
655 void print_CPU_state();
656
657 // Stack overflow checking
658 void bang_stack_with_offset(int offset) {
659 // stack grows down, caller passes positive offset
660 assert(offset > 0, "must bang with negative offset");
661 movl(Address(rsp, (-offset)), rax);
662 }
663
664 // Writes to stack successive pages until offset reached to check for
665 // stack overflow + shadow pages. Also, clobbers tmp
666 void bang_stack_size(Register size, Register tmp);
667
668 // Check for reserved stack access in method being exited (for JIT)
669 void reserved_stack_check();
670
671 void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
672
673 void verify_tlab();
674
675 Condition negate_condition(Condition cond);
676
677 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
678 // operands. In general the names are modified to avoid hiding the instruction in Assembler
679 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
680 // here in MacroAssembler. The major exception to this rule is call
681
682 // Arithmetics
683
684
685 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
686 void addptr(Address dst, Register src);
687
688 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
689 void addptr(Register dst, int32_t src);
690 void addptr(Register dst, Register src);
691 void addptr(Register dst, RegisterOrConstant src) {
692 if (src.is_constant()) addptr(dst, (int) src.as_constant());
693 else addptr(dst, src.as_register());
694 }
695
696 void andptr(Register dst, int32_t src);
697 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
698
699 void cmp8(AddressLiteral src1, int imm);
700
701 // renamed to drag out the casting of address to int32_t/intptr_t
702 void cmp32(Register src1, int32_t imm);
703
704 void cmp32(AddressLiteral src1, int32_t imm);
705 // compare reg - mem, or reg - &mem
706 void cmp32(Register src1, AddressLiteral src2);
707
708 void cmp32(Register src1, Address src2);
709
710 #ifndef _LP64
711 void cmpklass(Address dst, Metadata* obj);
712 void cmpklass(Register dst, Metadata* obj);
713 void cmpoop(Address dst, jobject obj);
714 #endif // _LP64
715
716 void cmpoop(Register src1, Register src2);
717 void cmpoop(Register src1, Address src2);
718 void cmpoop(Register dst, jobject obj);
719
720 // NOTE src2 must be the lval. This is NOT an mem-mem compare
721 void cmpptr(Address src1, AddressLiteral src2);
722
723 void cmpptr(Register src1, AddressLiteral src2);
724
725 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
726 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
727 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
728
729 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
730 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
731
732 // cmp64 to avoild hiding cmpq
733 void cmp64(Register src1, AddressLiteral src);
734
735 void cmpxchgptr(Register reg, Address adr);
736
737 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
738
739
740 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
741 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
742
743
744 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
745
746 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
747
748 void shlptr(Register dst, int32_t shift);
749 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
750
751 void shrptr(Register dst, int32_t shift);
752 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
753
754 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
755 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
756
757 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
758
759 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
760 void subptr(Register dst, int32_t src);
761 // Force generation of a 4 byte immediate value even if it fits into 8bit
762 void subptr_imm32(Register dst, int32_t src);
763 void subptr(Register dst, Register src);
764 void subptr(Register dst, RegisterOrConstant src) {
765 if (src.is_constant()) subptr(dst, (int) src.as_constant());
766 else subptr(dst, src.as_register());
767 }
768
769 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
770 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
771
772 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
773 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
774
775 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
776
777
778
779 // Helper functions for statistics gathering.
780 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
781 void cond_inc32(Condition cond, AddressLiteral counter_addr);
782 // Unconditional atomic increment.
783 void atomic_incl(Address counter_addr);
784 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
785 #ifdef _LP64
786 void atomic_incq(Address counter_addr);
787 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
788 #endif
789 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
790 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
791
792 void lea(Register dst, AddressLiteral adr);
793 void lea(Address dst, AddressLiteral adr);
794 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
795
796 void leal32(Register dst, Address src) { leal(dst, src); }
797
798 // Import other testl() methods from the parent class or else
799 // they will be hidden by the following overriding declaration.
800 using Assembler::testl;
801 void testl(Register dst, AddressLiteral src);
802
803 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
804 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
805 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
806 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
807
808 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
809 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
810 void testptr(Register src1, Register src2);
811
812 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
813 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
814
815 // Calls
816
817 void call(Label& L, relocInfo::relocType rtype);
818 void call(Register entry);
819 void call(Address addr) { Assembler::call(addr); }
820
821 // NOTE: this call transfers to the effective address of entry NOT
822 // the address contained by entry. This is because this is more natural
823 // for jumps/calls.
824 void call(AddressLiteral entry);
825
826 // Emit the CompiledIC call idiom
827 void ic_call(address entry, jint method_index = 0);
828
829 // Jumps
830
831 // NOTE: these jumps tranfer to the effective address of dst NOT
832 // the address contained by dst. This is because this is more natural
833 // for jumps/calls.
834 void jump(AddressLiteral dst);
835 void jump_cc(Condition cc, AddressLiteral dst);
836
837 // 32bit can do a case table jump in one instruction but we no longer allow the base
838 // to be installed in the Address class. This jump will tranfers to the address
839 // contained in the location described by entry (not the address of entry)
840 void jump(ArrayAddress entry);
841
842 // Floating
843
844 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
845 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
846 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
847
848 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
849 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
850 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
851
852 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
853 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
854 void comiss(XMMRegister dst, AddressLiteral src);
855
856 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
857 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
858 void comisd(XMMRegister dst, AddressLiteral src);
859
860 #ifndef _LP64
861 void fadd_s(Address src) { Assembler::fadd_s(src); }
862 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
863
864 void fldcw(Address src) { Assembler::fldcw(src); }
865 void fldcw(AddressLiteral src);
866
867 void fld_s(int index) { Assembler::fld_s(index); }
868 void fld_s(Address src) { Assembler::fld_s(src); }
869 void fld_s(AddressLiteral src);
870
871 void fld_d(Address src) { Assembler::fld_d(src); }
872 void fld_d(AddressLiteral src);
873
874 void fmul_s(Address src) { Assembler::fmul_s(src); }
875 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
876 #endif // _LP64
877
878 void fld_x(Address src) { Assembler::fld_x(src); }
879 void fld_x(AddressLiteral src);
880
881 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
882 void ldmxcsr(AddressLiteral src);
883
884 #ifdef _LP64
885 private:
886 void sha256_AVX2_one_round_compute(
887 Register reg_old_h,
888 Register reg_a,
889 Register reg_b,
890 Register reg_c,
891 Register reg_d,
892 Register reg_e,
893 Register reg_f,
894 Register reg_g,
895 Register reg_h,
896 int iter);
897 void sha256_AVX2_four_rounds_compute_first(int start);
898 void sha256_AVX2_four_rounds_compute_last(int start);
899 void sha256_AVX2_one_round_and_sched(
900 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
901 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
902 XMMRegister xmm_2, /* ymm6 */
903 XMMRegister xmm_3, /* ymm7 */
904 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
905 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
906 Register reg_c, /* edi */
907 Register reg_d, /* esi */
908 Register reg_e, /* r8d */
909 Register reg_f, /* r9d */
910 Register reg_g, /* r10d */
911 Register reg_h, /* r11d */
912 int iter);
913
914 void addm(int disp, Register r1, Register r2);
915 void gfmul(XMMRegister tmp0, XMMRegister t);
916 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
917 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
918 void generateHtbl_one_block(Register htbl);
919 void generateHtbl_eight_blocks(Register htbl);
920 public:
921 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
922 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
923 Register buf, Register state, Register ofs, Register limit, Register rsp,
924 bool multi_block, XMMRegister shuf_mask);
925 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
926 #endif
927
928 #ifdef _LP64
929 private:
930 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
931 Register e, Register f, Register g, Register h, int iteration);
932
933 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
934 Register a, Register b, Register c, Register d, Register e, Register f,
935 Register g, Register h, int iteration);
936
937 void addmq(int disp, Register r1, Register r2);
938 public:
939 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
940 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
941 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
942 XMMRegister shuf_mask);
943 private:
944 void roundEnc(XMMRegister key, int rnum);
945 void lastroundEnc(XMMRegister key, int rnum);
946 void roundDec(XMMRegister key, int rnum);
947 void lastroundDec(XMMRegister key, int rnum);
948 void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask);
949 void gfmul_avx512(XMMRegister ghash, XMMRegister hkey);
950 void generateHtbl_48_block_zmm(Register htbl, Register avx512_subkeyHtbl);
951 void ghash16_encrypt16_parallel(Register key, Register subkeyHtbl, XMMRegister ctr_blockx,
952 XMMRegister aad_hashx, Register in, Register out, Register data, Register pos, bool reduction,
953 XMMRegister addmask, bool no_ghash_input, Register rounds, Register ghash_pos,
954 bool final_reduction, int index, XMMRegister counter_inc_mask);
955 public:
956 void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len);
957 void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len);
958 void aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter,
959 Register len_reg, Register used, Register used_addr, Register saved_encCounter_start);
960 void aesgcm_encrypt(Register in, Register len, Register ct, Register out, Register key,
961 Register state, Register subkeyHtbl, Register avx512_subkeyHtbl, Register counter);
962
963 #endif
964
965 void fast_md5(Register buf, Address state, Address ofs, Address limit,
966 bool multi_block);
967
968 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
969 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
970 Register buf, Register state, Register ofs, Register limit, Register rsp,
971 bool multi_block);
972
973 #ifdef _LP64
974 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
975 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
976 Register buf, Register state, Register ofs, Register limit, Register rsp,
977 bool multi_block, XMMRegister shuf_mask);
978 #else
979 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
980 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
981 Register buf, Register state, Register ofs, Register limit, Register rsp,
982 bool multi_block);
983 #endif
984
985 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
986 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
987 Register rax, Register rcx, Register rdx, Register tmp);
988
989 #ifdef _LP64
990 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
991 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
992 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
993
994 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
995 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
996 Register rax, Register rcx, Register rdx, Register r11);
997
998 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
999 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1000 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1001
1002 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1003 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1004 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1005 Register tmp3, Register tmp4);
1006
1007 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1008 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1009 Register rax, Register rcx, Register rdx, Register tmp1,
1010 Register tmp2, Register tmp3, Register tmp4);
1011 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1012 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1013 Register rax, Register rcx, Register rdx, Register tmp1,
1014 Register tmp2, Register tmp3, Register tmp4);
1015 #else
1016 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1017 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1018 Register rax, Register rcx, Register rdx, Register tmp1);
1019
1020 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1021 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1022 Register rax, Register rcx, Register rdx, Register tmp);
1023
1024 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1025 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1026 Register rdx, Register tmp);
1027
1028 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1029 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1030 Register rax, Register rbx, Register rdx);
1031
1032 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1033 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1034 Register rax, Register rcx, Register rdx, Register tmp);
1035
1036 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1037 Register edx, Register ebx, Register esi, Register edi,
1038 Register ebp, Register esp);
1039
1040 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1041 Register esi, Register edi, Register ebp, Register esp);
1042
1043 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1044 Register edx, Register ebx, Register esi, Register edi,
1045 Register ebp, Register esp);
1046
1047 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1048 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1049 Register rax, Register rcx, Register rdx, Register tmp);
1050 #endif
1051
1052 private:
1053
1054 // these are private because users should be doing movflt/movdbl
1055
1056 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1057 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1058 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1059 void movss(XMMRegister dst, AddressLiteral src);
1060
1061 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1062 void movlpd(XMMRegister dst, AddressLiteral src);
1063
1064 public:
1065
1066 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1067 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1068 void addsd(XMMRegister dst, AddressLiteral src);
1069
1070 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1071 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1072 void addss(XMMRegister dst, AddressLiteral src);
1073
1074 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1075 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1076 void addpd(XMMRegister dst, AddressLiteral src);
1077
1078 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1079 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1080 void divsd(XMMRegister dst, AddressLiteral src);
1081
1082 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1083 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1084 void divss(XMMRegister dst, AddressLiteral src);
1085
1086 // Move Unaligned Double Quadword
1087 void movdqu(Address dst, XMMRegister src);
1088 void movdqu(XMMRegister dst, Address src);
1089 void movdqu(XMMRegister dst, XMMRegister src);
1090 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1091
1092 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1093 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1094 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1095 void kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1096 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1097 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1098
1099 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1100 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1101 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1102 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1103 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1104 void kmovql(KRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1105
1106 // Safe move operation, lowers down to 16bit moves for targets supporting
1107 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1108 void kmov(Address dst, KRegister src);
1109 void kmov(KRegister dst, Address src);
1110 void kmov(KRegister dst, KRegister src);
1111 void kmov(Register dst, KRegister src);
1112 void kmov(KRegister dst, Register src);
1113
1114 // AVX Unaligned forms
1115 void vmovdqu(Address dst, XMMRegister src);
1116 void vmovdqu(XMMRegister dst, Address src);
1117 void vmovdqu(XMMRegister dst, XMMRegister src);
1118 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1119
1120 // AVX512 Unaligned
1121 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len);
1122 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len);
1123
1124 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1125 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1126 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1127 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1128 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1129 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1130
1131 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1132 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1133 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1134 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1135 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1136
1137 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1138 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1139 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1140 if (dst->encoding() == src->encoding()) return;
1141 Assembler::evmovdqul(dst, src, vector_len);
1142 }
1143 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1144 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1145 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1146 if (dst->encoding() == src->encoding() && mask == k0) return;
1147 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1148 }
1149 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1150
1151 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1152 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1153 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1154 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1155 if (dst->encoding() == src->encoding()) return;
1156 Assembler::evmovdquq(dst, src, vector_len);
1157 }
1158 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1159 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1160 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1161 if (dst->encoding() == src->encoding() && mask == k0) return;
1162 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1163 }
1164 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1165
1166 // Move Aligned Double Quadword
1167 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1168 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1169 void movdqa(XMMRegister dst, AddressLiteral src);
1170
1171 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1172 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1173 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1174 void movsd(XMMRegister dst, AddressLiteral src);
1175
1176 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1177 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1178 void mulpd(XMMRegister dst, AddressLiteral src);
1179
1180 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1181 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1182 void mulsd(XMMRegister dst, AddressLiteral src);
1183
1184 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1185 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1186 void mulss(XMMRegister dst, AddressLiteral src);
1187
1188 // Carry-Less Multiplication Quadword
1189 void pclmulldq(XMMRegister dst, XMMRegister src) {
1190 // 0x00 - multiply lower 64 bits [0:63]
1191 Assembler::pclmulqdq(dst, src, 0x00);
1192 }
1193 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1194 // 0x11 - multiply upper 64 bits [64:127]
1195 Assembler::pclmulqdq(dst, src, 0x11);
1196 }
1197
1198 void pcmpeqb(XMMRegister dst, XMMRegister src);
1199 void pcmpeqw(XMMRegister dst, XMMRegister src);
1200
1201 void pcmpestri(XMMRegister dst, Address src, int imm8);
1202 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1203
1204 void pmovzxbw(XMMRegister dst, XMMRegister src);
1205 void pmovzxbw(XMMRegister dst, Address src);
1206
1207 void pmovmskb(Register dst, XMMRegister src);
1208
1209 void ptest(XMMRegister dst, XMMRegister src);
1210
1211 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1212 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1213 void sqrtsd(XMMRegister dst, AddressLiteral src);
1214
1215 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1216 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1217 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
1218
1219 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1220 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1221 void sqrtss(XMMRegister dst, AddressLiteral src);
1222
1223 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1224 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1225 void subsd(XMMRegister dst, AddressLiteral src);
1226
1227 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1228 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1229 void subss(XMMRegister dst, AddressLiteral src);
1230
1231 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1232 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1233 void ucomiss(XMMRegister dst, AddressLiteral src);
1234
1235 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1236 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1237 void ucomisd(XMMRegister dst, AddressLiteral src);
1238
1239 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1240 void xorpd(XMMRegister dst, XMMRegister src);
1241 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1242 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1243
1244 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1245 void xorps(XMMRegister dst, XMMRegister src);
1246 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1247 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1248
1249 // Shuffle Bytes
1250 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1251 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1252 void pshufb(XMMRegister dst, AddressLiteral src);
1253 // AVX 3-operands instructions
1254
1255 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1256 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1257 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1258
1259 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1260 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1261 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1262
1263 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1264 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1265
1266 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1267 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1268 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1269
1270 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1271 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1272
1273 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1274 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1275 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1276
1277 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1278 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1279 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1280
1281 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1282 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1283
1284 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1285
1286 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1287 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1288
1289 // Vector compares
1290 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1291 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1292 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1293 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1294 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1295 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1296 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1297 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1298 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1299 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1300 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1301 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1302 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1303 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1304 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1305 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1306
1307
1308 // Emit comparison instruction for the specified comparison predicate.
1309 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg);
1310 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1311
1312 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1313 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1314
1315 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1316
1317 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1318 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1319 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1320 Assembler::vpmulld(dst, nds, src, vector_len);
1321 };
1322 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1323 Assembler::vpmulld(dst, nds, src, vector_len);
1324 }
1325 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1326
1327 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1328 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1329
1330 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1331 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1332
1333 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1334 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1335
1336 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1337 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1338
1339 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1340 if (!is_varshift) {
1341 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1342 } else {
1343 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1344 }
1345 }
1346 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1347 if (!is_varshift) {
1348 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1349 } else {
1350 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1351 }
1352 }
1353 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1354 if (!is_varshift) {
1355 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1356 } else {
1357 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1358 }
1359 }
1360 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1361 if (!is_varshift) {
1362 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1363 } else {
1364 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1365 }
1366 }
1367 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1368 if (!is_varshift) {
1369 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1370 } else {
1371 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1372 }
1373 }
1374 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1375 if (!is_varshift) {
1376 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1377 } else {
1378 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1379 }
1380 }
1381 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1382 if (!is_varshift) {
1383 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1384 } else {
1385 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1386 }
1387 }
1388 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1389 if (!is_varshift) {
1390 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1391 } else {
1392 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1393 }
1394 }
1395 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1396 if (!is_varshift) {
1397 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1398 } else {
1399 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1400 }
1401 }
1402
1403 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1404 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1405 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1406 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1407
1408 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1409 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1410
1411 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1412 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1413
1414 void vptest(XMMRegister dst, XMMRegister src);
1415 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1416
1417 void punpcklbw(XMMRegister dst, XMMRegister src);
1418 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1419
1420 void pshufd(XMMRegister dst, Address src, int mode);
1421 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1422
1423 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1424 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1425
1426 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1427 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1428 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1429
1430 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1431 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1432 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1433
1434 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1435
1436 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1437 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1438 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1439
1440 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1441 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1442 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1443
1444 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1445 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1446 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1447
1448 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1449 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1450 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1451
1452 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1453 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1454 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1455
1456 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1457 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1458 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1459
1460 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1461 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1462
1463 // AVX Vector instructions
1464
1465 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1466 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1467 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1468
1469 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1470 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1471 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1472
1473 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1474 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1475 Assembler::vpxor(dst, nds, src, vector_len);
1476 else
1477 Assembler::vxorpd(dst, nds, src, vector_len);
1478 }
1479 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1480 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1481 Assembler::vpxor(dst, nds, src, vector_len);
1482 else
1483 Assembler::vxorpd(dst, nds, src, vector_len);
1484 }
1485 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1486
1487 // Simple version for AVX2 256bit vectors
1488 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1489 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1490
1491 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1492 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1493
1494 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1495 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1496 Assembler::vinserti32x4(dst, nds, src, imm8);
1497 } else if (UseAVX > 1) {
1498 // vinserti128 is available only in AVX2
1499 Assembler::vinserti128(dst, nds, src, imm8);
1500 } else {
1501 Assembler::vinsertf128(dst, nds, src, imm8);
1502 }
1503 }
1504
1505 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1506 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1507 Assembler::vinserti32x4(dst, nds, src, imm8);
1508 } else if (UseAVX > 1) {
1509 // vinserti128 is available only in AVX2
1510 Assembler::vinserti128(dst, nds, src, imm8);
1511 } else {
1512 Assembler::vinsertf128(dst, nds, src, imm8);
1513 }
1514 }
1515
1516 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1517 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1518 Assembler::vextracti32x4(dst, src, imm8);
1519 } else if (UseAVX > 1) {
1520 // vextracti128 is available only in AVX2
1521 Assembler::vextracti128(dst, src, imm8);
1522 } else {
1523 Assembler::vextractf128(dst, src, imm8);
1524 }
1525 }
1526
1527 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1528 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1529 Assembler::vextracti32x4(dst, src, imm8);
1530 } else if (UseAVX > 1) {
1531 // vextracti128 is available only in AVX2
1532 Assembler::vextracti128(dst, src, imm8);
1533 } else {
1534 Assembler::vextractf128(dst, src, imm8);
1535 }
1536 }
1537
1538 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1539 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1540 vinserti128(dst, dst, src, 1);
1541 }
1542 void vinserti128_high(XMMRegister dst, Address src) {
1543 vinserti128(dst, dst, src, 1);
1544 }
1545 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1546 vextracti128(dst, src, 1);
1547 }
1548 void vextracti128_high(Address dst, XMMRegister src) {
1549 vextracti128(dst, src, 1);
1550 }
1551
1552 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1553 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1554 Assembler::vinsertf32x4(dst, dst, src, 1);
1555 } else {
1556 Assembler::vinsertf128(dst, dst, src, 1);
1557 }
1558 }
1559
1560 void vinsertf128_high(XMMRegister dst, Address src) {
1561 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1562 Assembler::vinsertf32x4(dst, dst, src, 1);
1563 } else {
1564 Assembler::vinsertf128(dst, dst, src, 1);
1565 }
1566 }
1567
1568 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1569 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1570 Assembler::vextractf32x4(dst, src, 1);
1571 } else {
1572 Assembler::vextractf128(dst, src, 1);
1573 }
1574 }
1575
1576 void vextractf128_high(Address dst, XMMRegister src) {
1577 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1578 Assembler::vextractf32x4(dst, src, 1);
1579 } else {
1580 Assembler::vextractf128(dst, src, 1);
1581 }
1582 }
1583
1584 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1585 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1586 Assembler::vinserti64x4(dst, dst, src, 1);
1587 }
1588 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1589 Assembler::vinsertf64x4(dst, dst, src, 1);
1590 }
1591 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1592 Assembler::vextracti64x4(dst, src, 1);
1593 }
1594 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1595 Assembler::vextractf64x4(dst, src, 1);
1596 }
1597 void vextractf64x4_high(Address dst, XMMRegister src) {
1598 Assembler::vextractf64x4(dst, src, 1);
1599 }
1600 void vinsertf64x4_high(XMMRegister dst, Address src) {
1601 Assembler::vinsertf64x4(dst, dst, src, 1);
1602 }
1603
1604 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1605 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1606 vinserti128(dst, dst, src, 0);
1607 }
1608 void vinserti128_low(XMMRegister dst, Address src) {
1609 vinserti128(dst, dst, src, 0);
1610 }
1611 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1612 vextracti128(dst, src, 0);
1613 }
1614 void vextracti128_low(Address dst, XMMRegister src) {
1615 vextracti128(dst, src, 0);
1616 }
1617
1618 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1619 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1620 Assembler::vinsertf32x4(dst, dst, src, 0);
1621 } else {
1622 Assembler::vinsertf128(dst, dst, src, 0);
1623 }
1624 }
1625
1626 void vinsertf128_low(XMMRegister dst, Address src) {
1627 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1628 Assembler::vinsertf32x4(dst, dst, src, 0);
1629 } else {
1630 Assembler::vinsertf128(dst, dst, src, 0);
1631 }
1632 }
1633
1634 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1635 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1636 Assembler::vextractf32x4(dst, src, 0);
1637 } else {
1638 Assembler::vextractf128(dst, src, 0);
1639 }
1640 }
1641
1642 void vextractf128_low(Address dst, XMMRegister src) {
1643 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1644 Assembler::vextractf32x4(dst, src, 0);
1645 } else {
1646 Assembler::vextractf128(dst, src, 0);
1647 }
1648 }
1649
1650 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1651 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1652 Assembler::vinserti64x4(dst, dst, src, 0);
1653 }
1654 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1655 Assembler::vinsertf64x4(dst, dst, src, 0);
1656 }
1657 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1658 Assembler::vextracti64x4(dst, src, 0);
1659 }
1660 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1661 Assembler::vextractf64x4(dst, src, 0);
1662 }
1663 void vextractf64x4_low(Address dst, XMMRegister src) {
1664 Assembler::vextractf64x4(dst, src, 0);
1665 }
1666 void vinsertf64x4_low(XMMRegister dst, Address src) {
1667 Assembler::vinsertf64x4(dst, dst, src, 0);
1668 }
1669
1670 // Carry-Less Multiplication Quadword
1671 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1672 // 0x00 - multiply lower 64 bits [0:63]
1673 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1674 }
1675 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1676 // 0x11 - multiply upper 64 bits [64:127]
1677 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1678 }
1679 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1680 // 0x10 - multiply nds[0:63] and src[64:127]
1681 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1682 }
1683 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1684 //0x01 - multiply nds[64:127] and src[0:63]
1685 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1686 }
1687
1688 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1689 // 0x00 - multiply lower 64 bits [0:63]
1690 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1691 }
1692 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1693 // 0x11 - multiply upper 64 bits [64:127]
1694 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1695 }
1696
1697 // AVX-512 mask operations.
1698 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1699 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1700 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1701 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1702 void kortest(uint masklen, KRegister src1, KRegister src2);
1703 void ktest(uint masklen, KRegister src1, KRegister src2);
1704
1705 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1706 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1707
1708 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1709 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1710
1711 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1712 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1713
1714 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1715 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1716
1717 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1718 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1719 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1720 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1721
1722 void alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch);
1723 void anytrue(Register dst, uint masklen, KRegister src, KRegister kscratch);
1724
1725 void cmov32( Condition cc, Register dst, Address src);
1726 void cmov32( Condition cc, Register dst, Register src);
1727
1728 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1729
1730 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1731 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1732
1733 void movoop(Register dst, jobject obj);
1734 void movoop(Address dst, jobject obj);
1735
1736 void mov_metadata(Register dst, Metadata* obj);
1737 void mov_metadata(Address dst, Metadata* obj);
1738
1739 void movptr(ArrayAddress dst, Register src);
1740 // can this do an lea?
1741 void movptr(Register dst, ArrayAddress src);
1742
1743 void movptr(Register dst, Address src);
1744
1745 #ifdef _LP64
1746 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1747 #else
1748 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1749 #endif
1750
1751 void movptr(Register dst, intptr_t src);
1752 void movptr(Register dst, Register src);
1753 void movptr(Address dst, intptr_t src);
1754
1755 void movptr(Address dst, Register src);
1756
1757 void movptr(Register dst, RegisterOrConstant src) {
1758 if (src.is_constant()) movptr(dst, src.as_constant());
1759 else movptr(dst, src.as_register());
1760 }
1761
1762 #ifdef _LP64
1763 // Generally the next two are only used for moving NULL
1764 // Although there are situations in initializing the mark word where
1765 // they could be used. They are dangerous.
1766
1767 // They only exist on LP64 so that int32_t and intptr_t are not the same
1768 // and we have ambiguous declarations.
1769
1770 void movptr(Address dst, int32_t imm32);
1771 void movptr(Register dst, int32_t imm32);
1772 #endif // _LP64
1773
1774 // to avoid hiding movl
1775 void mov32(AddressLiteral dst, Register src);
1776 void mov32(Register dst, AddressLiteral src);
1777
1778 // to avoid hiding movb
1779 void movbyte(ArrayAddress dst, int src);
1780
1781 // Import other mov() methods from the parent class or else
1782 // they will be hidden by the following overriding declaration.
1783 using Assembler::movdl;
1784 using Assembler::movq;
1785 void movdl(XMMRegister dst, AddressLiteral src);
1786 void movq(XMMRegister dst, AddressLiteral src);
1787
1788 // Can push value or effective address
1789 void pushptr(AddressLiteral src);
1790
1791 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1792 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1793
1794 void pushoop(jobject obj);
1795 void pushklass(Metadata* obj);
1796
1797 // sign extend as need a l to ptr sized element
1798 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1799 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1800
1801
1802 public:
1803 // C2 compiled method's prolog code.
1804 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub);
1805
1806 // clear memory of size 'cnt' qwords, starting at 'base';
1807 // if 'is_large' is set, do not try to produce short loop
1808 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
1809
1810 // clear memory initialization sequence for constant size;
1811 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1812
1813 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1814 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1815
1816 // Fill primitive arrays
1817 void generate_fill(BasicType t, bool aligned,
1818 Register to, Register value, Register count,
1819 Register rtmp, XMMRegister xtmp);
1820
1821 void encode_iso_array(Register src, Register dst, Register len,
1822 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1823 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1824
1825 #ifdef _LP64
1826 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1827 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1828 Register y, Register y_idx, Register z,
1829 Register carry, Register product,
1830 Register idx, Register kdx);
1831 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1832 Register yz_idx, Register idx,
1833 Register carry, Register product, int offset);
1834 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1835 Register carry, Register carry2,
1836 Register idx, Register jdx,
1837 Register yz_idx1, Register yz_idx2,
1838 Register tmp, Register tmp3, Register tmp4);
1839 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1840 Register yz_idx, Register idx, Register jdx,
1841 Register carry, Register product,
1842 Register carry2);
1843 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1844 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1845 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1846 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1847 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1848 Register tmp2);
1849 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1850 Register rdxReg, Register raxReg);
1851 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1852 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1853 Register tmp3, Register tmp4);
1854 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1855 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1856
1857 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1858 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1859 Register raxReg);
1860 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1861 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1862 Register raxReg);
1863 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1864 Register result, Register tmp1, Register tmp2,
1865 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1866 #endif
1867
1868 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1869 void update_byte_crc32(Register crc, Register val, Register table);
1870 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1871
1872
1873 #ifdef _LP64
1874 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1875 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1876 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
1877 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
1878 void updateBytesAdler32(Register adler32, Register buf, Register length, XMMRegister shuf0, XMMRegister shuf1, ExternalAddress scale);
1879 #endif // _LP64
1880
1881 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1882 // Note on a naming convention:
1883 // Prefix w = register only used on a Westmere+ architecture
1884 // Prefix n = register only used on a Nehalem architecture
1885 #ifdef _LP64
1886 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1887 Register tmp1, Register tmp2, Register tmp3);
1888 #else
1889 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1890 Register tmp1, Register tmp2, Register tmp3,
1891 XMMRegister xtmp1, XMMRegister xtmp2);
1892 #endif
1893 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1894 Register in_out,
1895 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1896 XMMRegister w_xtmp2,
1897 Register tmp1,
1898 Register n_tmp2, Register n_tmp3);
1899 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1900 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1901 Register tmp1, Register tmp2,
1902 Register n_tmp3);
1903 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1904 Register in_out1, Register in_out2, Register in_out3,
1905 Register tmp1, Register tmp2, Register tmp3,
1906 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1907 Register tmp4, Register tmp5,
1908 Register n_tmp6);
1909 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1910 Register tmp1, Register tmp2, Register tmp3,
1911 Register tmp4, Register tmp5, Register tmp6,
1912 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1913 bool is_pclmulqdq_supported);
1914 // Fold 128-bit data chunk
1915 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1916 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1917 #ifdef _LP64
1918 // Fold 512-bit data chunk
1919 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
1920 #endif // _LP64
1921 // Fold 8-bit data
1922 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1923 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1924
1925 // Compress char[] array to byte[].
1926 void char_array_compress(Register src, Register dst, Register len,
1927 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1928 XMMRegister tmp4, Register tmp5, Register result,
1929 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
1930
1931 // Inflate byte[] array to char[].
1932 void byte_array_inflate(Register src, Register dst, Register len,
1933 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
1934
1935 void fill64_masked_avx(uint shift, Register dst, int disp,
1936 XMMRegister xmm, KRegister mask, Register length,
1937 Register temp, bool use64byteVector = false);
1938
1939 void fill32_masked_avx(uint shift, Register dst, int disp,
1940 XMMRegister xmm, KRegister mask, Register length,
1941 Register temp);
1942
1943 void fill32_avx(Register dst, int disp, XMMRegister xmm);
1944
1945 void fill64_avx(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
1946
1947 #ifdef _LP64
1948 void convert_f2i(Register dst, XMMRegister src);
1949 void convert_d2i(Register dst, XMMRegister src);
1950 void convert_f2l(Register dst, XMMRegister src);
1951 void convert_d2l(Register dst, XMMRegister src);
1952
1953 void cache_wb(Address line);
1954 void cache_wbsync(bool is_pre);
1955
1956 #if COMPILER2_OR_JVMCI
1957 void arraycopy_avx3_special_cases(XMMRegister xmm, KRegister mask, Register from,
1958 Register to, Register count, int shift,
1959 Register index, Register temp,
1960 bool use64byteVector, Label& L_entry, Label& L_exit);
1961
1962 void arraycopy_avx3_special_cases_conjoint(XMMRegister xmm, KRegister mask, Register from,
1963 Register to, Register start_index, Register end_index,
1964 Register count, int shift, Register temp,
1965 bool use64byteVector, Label& L_entry, Label& L_exit);
1966
1967 void copy64_masked_avx(Register dst, Register src, XMMRegister xmm,
1968 KRegister mask, Register length, Register index,
1969 Register temp, int shift = Address::times_1, int offset = 0,
1970 bool use64byteVector = false);
1971
1972 void copy32_masked_avx(Register dst, Register src, XMMRegister xmm,
1973 KRegister mask, Register length, Register index,
1974 Register temp, int shift = Address::times_1, int offset = 0);
1975
1976 void copy32_avx(Register dst, Register src, Register index, XMMRegister xmm,
1977 int shift = Address::times_1, int offset = 0);
1978
1979 void copy64_avx(Register dst, Register src, Register index, XMMRegister xmm,
1980 bool conjoint, int shift = Address::times_1, int offset = 0,
1981 bool use64byteVector = false);
1982 #endif // COMPILER2_OR_JVMCI
1983
1984 #endif // _LP64
1985
1986 void vallones(XMMRegister dst, int vector_len);
1987 };
1988
1989 /**
1990 * class SkipIfEqual:
1991 *
1992 * Instantiating this class will result in assembly code being output that will
1993 * jump around any code emitted between the creation of the instance and it's
1994 * automatic destruction at the end of a scope block, depending on the value of
1995 * the flag passed to the constructor, which will be checked at run-time.
1996 */
1997 class SkipIfEqual {
1998 private:
1999 MacroAssembler* _masm;
2000 Label _label;
2001
2002 public:
2003 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2004 ~SkipIfEqual();
2005 };
2006
2007 #endif // CPU_X86_MACROASSEMBLER_X86_HPP