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src/hotspot/share/opto/chaitin.cpp

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  60   else tty->print("? ");
  61 
  62   if( is_multidef() ) {
  63     tty->print("MultiDef ");
  64     if (_defs != NULL) {
  65       tty->print("(");
  66       for (int i = 0; i < _defs->length(); i++) {
  67         tty->print("N%d ", _defs->at(i)->_idx);
  68       }
  69       tty->print(") ");
  70     }
  71   }
  72   else if( _def == 0 ) tty->print("Dead ");
  73   else tty->print("Def: N%d ",_def->_idx);
  74 
  75   tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
  76   // Flags
  77   if( _is_oop ) tty->print("Oop ");
  78   if( _is_float ) tty->print("Float ");
  79   if( _is_vector ) tty->print("Vector ");

  80   if( _is_scalable ) tty->print("Scalable ");
  81   if( _was_spilled1 ) tty->print("Spilled ");
  82   if( _was_spilled2 ) tty->print("Spilled2 ");
  83   if( _direct_conflict ) tty->print("Direct_conflict ");
  84   if( _fat_proj ) tty->print("Fat ");
  85   if( _was_lo ) tty->print("Lo ");
  86   if( _has_copy ) tty->print("Copy ");
  87   if( _at_risk ) tty->print("Risk ");
  88 
  89   if( _must_spill ) tty->print("Must_spill ");
  90   if( _is_bound ) tty->print("Bound ");
  91   if( _msize_valid ) {
  92     if( _degree_valid && lo_degree() ) tty->print("Trivial ");
  93   }
  94 
  95   tty->cr();
  96 }
  97 #endif
  98 
  99 // Compute score from cost and area.  Low score is best to spill.

 621 
 622   // Log regalloc results
 623   CompileLog* log = Compile::current()->log();
 624   if (log != NULL) {
 625     log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
 626   }
 627 
 628   if (C->failing()) {
 629     return;
 630   }
 631 
 632   NOT_PRODUCT(C->verify_graph_edges();)
 633 
 634   // Move important info out of the live_arena to longer lasting storage.
 635   alloc_node_regs(_lrg_map.size());
 636   for (uint i=0; i < _lrg_map.size(); i++) {
 637     if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
 638       LRG &lrg = lrgs(_lrg_map.live_range_id(i));
 639       if (!lrg.alive()) {
 640         set_bad(i);
 641       } else if (lrg.num_regs() == 1) {

 642         set1(i, lrg.reg());
 643       } else {                  // Must be a register-set
 644         if (!lrg._fat_proj) {   // Must be aligned adjacent register set
 645           // Live ranges record the highest register in their mask.
 646           // We want the low register for the AD file writer's convenience.
 647           OptoReg::Name hi = lrg.reg(); // Get hi register
 648           int num_regs = lrg.num_regs();
 649           if (lrg.is_scalable() && OptoReg::is_stack(hi)) {
 650             // For scalable vector registers, when they are allocated in physical
 651             // registers, num_regs is RegMask::SlotsPerVecA for reg mask of scalable
 652             // vector. If they are allocated on stack, we need to get the actual
 653             // num_regs, which reflects the physical length of scalable registers.
 654             num_regs = lrg.scalable_reg_slots();
 655           }
 656           OptoReg::Name lo = OptoReg::add(hi, (1-num_regs)); // Find lo
 657           // We have to use pair [lo,lo+1] even for wide vectors because
 658           // the rest of code generation works only with pairs. It is safe
 659           // since for registers encoding only 'lo' is used.
 660           // Second reg from pair is used in ScheduleAndBundle on SPARC where
 661           // vector max size is 8 which corresponds to registers pair.
 662           // It is also used in BuildOopMaps but oop operations are not
 663           // vectorized.
 664           set2(i, lo);




 665         } else {                // Misaligned; extract 2 bits
 666           OptoReg::Name hi = lrg.reg(); // Get hi register
 667           lrg.Remove(hi);       // Yank from mask
 668           int lo = lrg.mask().find_first_elem(); // Find lo
 669           set_pair(i, hi, lo);
 670         }
 671       }
 672       if( lrg._is_oop ) _node_oops.set(i);
 673     } else {
 674       set_bad(i);
 675     }
 676   }
 677 
 678   // Done!
 679   _live = NULL;
 680   _ifg = NULL;
 681   C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
 682 }
 683 
 684 void PhaseChaitin::de_ssa() {

 807         uint ireg = n->ideal_reg();
 808         assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
 809                 "oops must be in Op_RegP's" );
 810 
 811         // Check for vector live range (only if vector register is used).
 812         // On SPARC vector uses RegD which could be misaligned so it is not
 813         // processes as vector in RA.
 814         if (RegMask::is_vector(ireg)) {
 815           lrg._is_vector = 1;
 816           if (Matcher::implements_scalable_vector && ireg == Op_VecA) {
 817             assert(Matcher::supports_scalable_vector(), "scalable vector should be supported");
 818             lrg._is_scalable = 1;
 819             // For scalable vector, when it is allocated in physical register,
 820             // num_regs is RegMask::SlotsPerVecA for reg mask,
 821             // which may not be the actual physical register size.
 822             // If it is allocated in stack, we need to get the actual
 823             // physical length of scalable vector register.
 824             lrg.set_scalable_reg_slots(Matcher::scalable_vector_reg_size(T_FLOAT));
 825           }
 826         }














 827         assert(n_type->isa_vect() == NULL || lrg._is_vector ||
 828                ireg == Op_RegD || ireg == Op_RegL  || ireg == Op_RegVectMask,
 829                "vector must be in vector registers");
 830 
 831         // Check for bound register masks
 832         const RegMask &lrgmask = lrg.mask();
 833         if (lrgmask.is_bound(ireg)) {
 834           lrg._is_bound = 1;
 835         }
 836 
 837         // Check for maximum frequency value
 838         if (lrg._maxfreq < block->_freq) {
 839           lrg._maxfreq = block->_freq;
 840         }
 841 
 842         // Check for oop-iness, or long/double
 843         // Check for multi-kill projection
 844         switch (ireg) {
 845         case MachProjNode::fat_proj:
 846           // Fat projections have size equal to number of registers killed
 847           lrg.set_num_regs(rm.Size());
 848           lrg.set_reg_pressure(lrg.num_regs());

 902 #elif defined(IA32)
 903           if( ireg == Op_RegL ) {
 904             lrg.set_reg_pressure(2);
 905           } else {
 906             lrg.set_reg_pressure(1);
 907           }
 908 #else
 909           lrg.set_reg_pressure(1);  // normally one value per register
 910 #endif
 911           // If this def of a double forces a mis-aligned double,
 912           // flag as '_fat_proj' - really flag as allowing misalignment
 913           // AND changes how we count interferences.  A mis-aligned
 914           // double can interfere with TWO aligned pairs, or effectively
 915           // FOUR registers!
 916           if (rm.is_misaligned_pair()) {
 917             lrg._fat_proj = 1;
 918             lrg._is_bound = 1;
 919           }
 920           break;
 921         case Op_RegVectMask:


 922           lrg.set_num_regs(RegMask::SlotsPerRegVectMask);
 923           lrg.set_reg_pressure(1);
 924           break;
 925         case Op_RegF:
 926         case Op_RegI:
 927         case Op_RegN:
 928         case Op_RegFlags:
 929         case 0:                 // not an ideal register
 930           lrg.set_num_regs(1);
 931           lrg.set_reg_pressure(1);
 932           break;
 933         case Op_VecA:
 934           assert(Matcher::supports_scalable_vector(), "does not support scalable vector");
 935           assert(RegMask::num_registers(Op_VecA) == RegMask::SlotsPerVecA, "sanity");
 936           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecA), "vector should be aligned");
 937           lrg.set_num_regs(RegMask::SlotsPerVecA);
 938           lrg.set_reg_pressure(1);
 939           break;
 940         case Op_VecS:
 941           assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");

1354       if (num_regs == RegMask::SlotsPerVecA) {
1355         return assigned;
1356       }
1357 
1358       // mask has been cleared out by clear_to_sets(SlotsPerVecA) before choose_color, but it
1359       // does not work for scalable size. We have to find adjacent scalable_reg_slots() bits
1360       // instead of SlotsPerVecA bits.
1361       assigned = mask.find_first_set(lrg, num_regs); // find highest valid reg
1362       while (OptoReg::is_valid(assigned) && RegMask::can_represent(assigned)) {
1363         // Verify the found reg has scalable_reg_slots() bits set.
1364         if (mask.is_valid_reg(assigned, num_regs)) {
1365           return assigned;
1366         } else {
1367           // Remove more for each iteration
1368           mask.Remove(assigned - num_regs + 1); // Unmask the lowest reg
1369           mask.clear_to_sets(RegMask::SlotsPerVecA); // Align by SlotsPerVecA bits
1370           assigned = mask.find_first_set(lrg, num_regs);
1371         }
1372       }
1373       return OptoReg::Bad; // will cause chunk change, and retry next chunk





1374     }
1375   }
1376 
1377   return assigned;
1378 }
1379 
1380 // Choose a color using the biasing heuristic
1381 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1382 
1383   // Check for "at_risk" LRG's
1384   uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1385   if (risk_lrg != 0 && !_ifg->neighbors(risk_lrg)->is_empty()) {
1386     // Walk the colored neighbors of the "at_risk" candidate
1387     // Choose a color which is both legal and already taken by a neighbor
1388     // of the "at_risk" candidate in order to improve the chances of the
1389     // "at_risk" candidate of coloring
1390     IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1391     uint datum;
1392     while ((datum = elements.next()) != 0) {
1393       OptoReg::Name reg = lrgs(datum).reg();

1400   uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1401   if (copy_lrg != 0) {
1402     // If he has a color,
1403     if(!_ifg->_yanked->test(copy_lrg)) {
1404       OptoReg::Name reg = lrgs(copy_lrg).reg();
1405       //  And it is legal for you,
1406       if (is_legal_reg(lrg, reg, chunk))
1407         return reg;
1408     } else if( chunk == 0 ) {
1409       // Choose a color which is legal for him
1410       RegMask tempmask = lrg.mask();
1411       tempmask.AND(lrgs(copy_lrg).mask());
1412       tempmask.clear_to_sets(lrg.num_regs());
1413       OptoReg::Name reg = find_first_set(lrg, tempmask, chunk);
1414       if (OptoReg::is_valid(reg))
1415         return reg;
1416     }
1417   }
1418 
1419   // If no bias info exists, just go with the register selection ordering
1420   if (lrg._is_vector || lrg.num_regs() == 2) {
1421     // Find an aligned set
1422     return OptoReg::add(find_first_set(lrg, lrg.mask(), chunk), chunk);
1423   }
1424 
1425   // CNC - Fun hack.  Alternate 1st and 2nd selection.  Enables post-allocate
1426   // copy removal to remove many more copies, by preventing a just-assigned
1427   // register from being repeatedly assigned.
1428   OptoReg::Name reg = lrg.mask().find_first_elem();
1429   if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1430     // This 'Remove; find; Insert' idiom is an expensive way to find the
1431     // SECOND element in the mask.
1432     lrg.Remove(reg);
1433     OptoReg::Name reg2 = lrg.mask().find_first_elem();
1434     lrg.Insert(reg);
1435     if( OptoReg::is_reg(reg2))
1436       reg = reg2;
1437   }
1438   return OptoReg::add( reg, chunk );
1439 }
1440 

  60   else tty->print("? ");
  61 
  62   if( is_multidef() ) {
  63     tty->print("MultiDef ");
  64     if (_defs != NULL) {
  65       tty->print("(");
  66       for (int i = 0; i < _defs->length(); i++) {
  67         tty->print("N%d ", _defs->at(i)->_idx);
  68       }
  69       tty->print(") ");
  70     }
  71   }
  72   else if( _def == 0 ) tty->print("Dead ");
  73   else tty->print("Def: N%d ",_def->_idx);
  74 
  75   tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
  76   // Flags
  77   if( _is_oop ) tty->print("Oop ");
  78   if( _is_float ) tty->print("Float ");
  79   if( _is_vector ) tty->print("Vector ");
  80   if( _is_predicate ) tty->print("Predicate ");
  81   if( _is_scalable ) tty->print("Scalable ");
  82   if( _was_spilled1 ) tty->print("Spilled ");
  83   if( _was_spilled2 ) tty->print("Spilled2 ");
  84   if( _direct_conflict ) tty->print("Direct_conflict ");
  85   if( _fat_proj ) tty->print("Fat ");
  86   if( _was_lo ) tty->print("Lo ");
  87   if( _has_copy ) tty->print("Copy ");
  88   if( _at_risk ) tty->print("Risk ");
  89 
  90   if( _must_spill ) tty->print("Must_spill ");
  91   if( _is_bound ) tty->print("Bound ");
  92   if( _msize_valid ) {
  93     if( _degree_valid && lo_degree() ) tty->print("Trivial ");
  94   }
  95 
  96   tty->cr();
  97 }
  98 #endif
  99 
 100 // Compute score from cost and area.  Low score is best to spill.

 622 
 623   // Log regalloc results
 624   CompileLog* log = Compile::current()->log();
 625   if (log != NULL) {
 626     log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
 627   }
 628 
 629   if (C->failing()) {
 630     return;
 631   }
 632 
 633   NOT_PRODUCT(C->verify_graph_edges();)
 634 
 635   // Move important info out of the live_arena to longer lasting storage.
 636   alloc_node_regs(_lrg_map.size());
 637   for (uint i=0; i < _lrg_map.size(); i++) {
 638     if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
 639       LRG &lrg = lrgs(_lrg_map.live_range_id(i));
 640       if (!lrg.alive()) {
 641         set_bad(i);
 642       } else if ((lrg.num_regs() == 1 && !lrg.is_scalable()) ||
 643                  (lrg.is_scalable() && lrg.scalable_reg_slots() == 1)) {
 644         set1(i, lrg.reg());
 645       } else {                  // Must be a register-set
 646         if (!lrg._fat_proj) {   // Must be aligned adjacent register set
 647           // Live ranges record the highest register in their mask.
 648           // We want the low register for the AD file writer's convenience.
 649           OptoReg::Name hi = lrg.reg(); // Get hi register
 650           int num_regs = lrg.num_regs();
 651           if (lrg.is_scalable() && OptoReg::is_stack(hi)) {
 652             // For scalable vector registers, when they are allocated in physical
 653             // registers, num_regs is RegMask::SlotsPerVecA for reg mask of scalable
 654             // vector. If they are allocated on stack, we need to get the actual
 655             // num_regs, which reflects the physical length of scalable registers.
 656             num_regs = lrg.scalable_reg_slots();
 657           }
 658           if (num_regs == 1) {
 659             set1(i, hi);
 660           } else {
 661             OptoReg::Name lo = OptoReg::add(hi, (1 - num_regs)); // Find lo
 662             // We have to use pair [lo,lo+1] even for wide vectors/vmasks because
 663             // the rest of code generation works only with pairs. It is safe
 664             // since for registers encoding only 'lo' is used.
 665             // Second reg from pair is used in ScheduleAndBundle with vector max
 666             // size 8 which corresponds to registers pair.
 667             // It is also used in BuildOopMaps but oop operations are not
 668             // vectorized.
 669             set2(i, lo);
 670           }
 671         } else {                // Misaligned; extract 2 bits
 672           OptoReg::Name hi = lrg.reg(); // Get hi register
 673           lrg.Remove(hi);       // Yank from mask
 674           int lo = lrg.mask().find_first_elem(); // Find lo
 675           set_pair(i, hi, lo);
 676         }
 677       }
 678       if( lrg._is_oop ) _node_oops.set(i);
 679     } else {
 680       set_bad(i);
 681     }
 682   }
 683 
 684   // Done!
 685   _live = NULL;
 686   _ifg = NULL;
 687   C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
 688 }
 689 
 690 void PhaseChaitin::de_ssa() {

 813         uint ireg = n->ideal_reg();
 814         assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
 815                 "oops must be in Op_RegP's" );
 816 
 817         // Check for vector live range (only if vector register is used).
 818         // On SPARC vector uses RegD which could be misaligned so it is not
 819         // processes as vector in RA.
 820         if (RegMask::is_vector(ireg)) {
 821           lrg._is_vector = 1;
 822           if (Matcher::implements_scalable_vector && ireg == Op_VecA) {
 823             assert(Matcher::supports_scalable_vector(), "scalable vector should be supported");
 824             lrg._is_scalable = 1;
 825             // For scalable vector, when it is allocated in physical register,
 826             // num_regs is RegMask::SlotsPerVecA for reg mask,
 827             // which may not be the actual physical register size.
 828             // If it is allocated in stack, we need to get the actual
 829             // physical length of scalable vector register.
 830             lrg.set_scalable_reg_slots(Matcher::scalable_vector_reg_size(T_FLOAT));
 831           }
 832         }
 833 
 834         if (ireg == Op_RegVectMask) {
 835           assert(Matcher::has_predicated_vectors(), "predicated vector should be supported");
 836           lrg._is_predicate = 1;
 837           if (Matcher::supports_scalable_vector()) {
 838             lrg._is_scalable = 1;
 839             // For scalable predicate, when it is allocated in physical register,
 840             // num_regs is RegMask::SlotsPerRegVectMask for reg mask,
 841             // which may not be the actual physical register size.
 842             // If it is allocated in stack, we need to get the actual
 843             // physical length of scalable predicate register.
 844             lrg.set_scalable_reg_slots(Matcher::scalable_predicate_reg_slots());
 845           }
 846         }
 847         assert(n_type->isa_vect() == NULL || lrg._is_vector ||
 848                ireg == Op_RegD || ireg == Op_RegL || ireg == Op_RegVectMask,
 849                "vector must be in vector registers");
 850 
 851         // Check for bound register masks
 852         const RegMask &lrgmask = lrg.mask();
 853         if (lrgmask.is_bound(ireg)) {
 854           lrg._is_bound = 1;
 855         }
 856 
 857         // Check for maximum frequency value
 858         if (lrg._maxfreq < block->_freq) {
 859           lrg._maxfreq = block->_freq;
 860         }
 861 
 862         // Check for oop-iness, or long/double
 863         // Check for multi-kill projection
 864         switch (ireg) {
 865         case MachProjNode::fat_proj:
 866           // Fat projections have size equal to number of registers killed
 867           lrg.set_num_regs(rm.Size());
 868           lrg.set_reg_pressure(lrg.num_regs());

 922 #elif defined(IA32)
 923           if( ireg == Op_RegL ) {
 924             lrg.set_reg_pressure(2);
 925           } else {
 926             lrg.set_reg_pressure(1);
 927           }
 928 #else
 929           lrg.set_reg_pressure(1);  // normally one value per register
 930 #endif
 931           // If this def of a double forces a mis-aligned double,
 932           // flag as '_fat_proj' - really flag as allowing misalignment
 933           // AND changes how we count interferences.  A mis-aligned
 934           // double can interfere with TWO aligned pairs, or effectively
 935           // FOUR registers!
 936           if (rm.is_misaligned_pair()) {
 937             lrg._fat_proj = 1;
 938             lrg._is_bound = 1;
 939           }
 940           break;
 941         case Op_RegVectMask:
 942           assert(Matcher::has_predicated_vectors(), "sanity");
 943           assert(RegMask::num_registers(Op_RegVectMask) == RegMask::SlotsPerRegVectMask, "sanity");
 944           lrg.set_num_regs(RegMask::SlotsPerRegVectMask);
 945           lrg.set_reg_pressure(1);
 946           break;
 947         case Op_RegF:
 948         case Op_RegI:
 949         case Op_RegN:
 950         case Op_RegFlags:
 951         case 0:                 // not an ideal register
 952           lrg.set_num_regs(1);
 953           lrg.set_reg_pressure(1);
 954           break;
 955         case Op_VecA:
 956           assert(Matcher::supports_scalable_vector(), "does not support scalable vector");
 957           assert(RegMask::num_registers(Op_VecA) == RegMask::SlotsPerVecA, "sanity");
 958           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecA), "vector should be aligned");
 959           lrg.set_num_regs(RegMask::SlotsPerVecA);
 960           lrg.set_reg_pressure(1);
 961           break;
 962         case Op_VecS:
 963           assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");

1376       if (num_regs == RegMask::SlotsPerVecA) {
1377         return assigned;
1378       }
1379 
1380       // mask has been cleared out by clear_to_sets(SlotsPerVecA) before choose_color, but it
1381       // does not work for scalable size. We have to find adjacent scalable_reg_slots() bits
1382       // instead of SlotsPerVecA bits.
1383       assigned = mask.find_first_set(lrg, num_regs); // find highest valid reg
1384       while (OptoReg::is_valid(assigned) && RegMask::can_represent(assigned)) {
1385         // Verify the found reg has scalable_reg_slots() bits set.
1386         if (mask.is_valid_reg(assigned, num_regs)) {
1387           return assigned;
1388         } else {
1389           // Remove more for each iteration
1390           mask.Remove(assigned - num_regs + 1); // Unmask the lowest reg
1391           mask.clear_to_sets(RegMask::SlotsPerVecA); // Align by SlotsPerVecA bits
1392           assigned = mask.find_first_set(lrg, num_regs);
1393         }
1394       }
1395       return OptoReg::Bad; // will cause chunk change, and retry next chunk
1396     } else if (lrg._is_predicate) {
1397       assert(num_regs == RegMask::SlotsPerRegVectMask, "scalable predicate register");
1398       num_regs = lrg.scalable_reg_slots();
1399       mask.clear_to_sets(num_regs);
1400       return mask.find_first_set(lrg, num_regs);
1401     }
1402   }
1403 
1404   return assigned;
1405 }
1406 
1407 // Choose a color using the biasing heuristic
1408 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1409 
1410   // Check for "at_risk" LRG's
1411   uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1412   if (risk_lrg != 0 && !_ifg->neighbors(risk_lrg)->is_empty()) {
1413     // Walk the colored neighbors of the "at_risk" candidate
1414     // Choose a color which is both legal and already taken by a neighbor
1415     // of the "at_risk" candidate in order to improve the chances of the
1416     // "at_risk" candidate of coloring
1417     IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1418     uint datum;
1419     while ((datum = elements.next()) != 0) {
1420       OptoReg::Name reg = lrgs(datum).reg();

1427   uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1428   if (copy_lrg != 0) {
1429     // If he has a color,
1430     if(!_ifg->_yanked->test(copy_lrg)) {
1431       OptoReg::Name reg = lrgs(copy_lrg).reg();
1432       //  And it is legal for you,
1433       if (is_legal_reg(lrg, reg, chunk))
1434         return reg;
1435     } else if( chunk == 0 ) {
1436       // Choose a color which is legal for him
1437       RegMask tempmask = lrg.mask();
1438       tempmask.AND(lrgs(copy_lrg).mask());
1439       tempmask.clear_to_sets(lrg.num_regs());
1440       OptoReg::Name reg = find_first_set(lrg, tempmask, chunk);
1441       if (OptoReg::is_valid(reg))
1442         return reg;
1443     }
1444   }
1445 
1446   // If no bias info exists, just go with the register selection ordering
1447   if (lrg._is_vector || lrg.num_regs() == 2 || lrg.is_scalable()) {
1448     // Find an aligned set
1449     return OptoReg::add(find_first_set(lrg, lrg.mask(), chunk), chunk);
1450   }
1451 
1452   // CNC - Fun hack.  Alternate 1st and 2nd selection.  Enables post-allocate
1453   // copy removal to remove many more copies, by preventing a just-assigned
1454   // register from being repeatedly assigned.
1455   OptoReg::Name reg = lrg.mask().find_first_elem();
1456   if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1457     // This 'Remove; find; Insert' idiom is an expensive way to find the
1458     // SECOND element in the mask.
1459     lrg.Remove(reg);
1460     OptoReg::Name reg2 = lrg.mask().find_first_elem();
1461     lrg.Insert(reg);
1462     if( OptoReg::is_reg(reg2))
1463       reg = reg2;
1464   }
1465   return OptoReg::add( reg, chunk );
1466 }
1467 
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