1 /*
  2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
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 24 
 25 #ifndef SHARE_OPTO_CHAITIN_HPP
 26 #define SHARE_OPTO_CHAITIN_HPP
 27 
 28 #include "code/vmreg.hpp"
 29 #include "memory/resourceArea.hpp"
 30 #include "opto/connode.hpp"
 31 #include "opto/live.hpp"
 32 #include "opto/machnode.hpp"
 33 #include "opto/matcher.hpp"
 34 #include "opto/phase.hpp"
 35 #include "opto/regalloc.hpp"
 36 #include "opto/regmask.hpp"
 37 
 38 class Matcher;
 39 class PhaseCFG;
 40 class PhaseLive;
 41 class PhaseRegAlloc;
 42 class PhaseChaitin;
 43 
 44 #define OPTO_DEBUG_SPLIT_FREQ  BLOCK_FREQUENCY(0.001)
 45 #define OPTO_LRG_HIGH_FREQ     BLOCK_FREQUENCY(0.25)
 46 
 47 //------------------------------LRG--------------------------------------------
 48 // Live-RanGe structure.
 49 class LRG : public ResourceObj {
 50   friend class VMStructs;
 51 public:
 52   static const uint AllStack_size = 0xFFFFF; // This mask size is used to tell that the mask of this LRG supports stack positions
 53   enum { SPILL_REG=29999 };     // Register number of a spilled LRG
 54 
 55   double _cost;                 // 2 for loads/1 for stores times block freq
 56   double _area;                 // Sum of all simultaneously live values
 57   double score() const;         // Compute score from cost and area
 58   double _maxfreq;              // Maximum frequency of any def or use
 59 
 60   Node *_def;                   // Check for multi-def live ranges
 61 #ifndef PRODUCT
 62   GrowableArray<Node*>* _defs;
 63 #endif
 64 
 65   uint _risk_bias;              // Index of LRG which we want to avoid color
 66   uint _copy_bias;              // Index of LRG which we want to share color
 67 
 68   uint _next;                   // Index of next LRG in linked list
 69   uint _prev;                   // Index of prev LRG in linked list
 70 private:
 71   uint _reg;                    // Chosen register; undefined if mask is plural
 72 public:
 73   // Return chosen register for this LRG.  Error if the LRG is not bound to
 74   // a single register.
 75   OptoReg::Name reg() const { return OptoReg::Name(_reg); }
 76   void set_reg( OptoReg::Name r ) { _reg = r; }
 77 
 78 private:
 79   uint _eff_degree;             // Effective degree: Sum of neighbors _num_regs
 80 public:
 81   int degree() const { assert( _degree_valid , "" ); return _eff_degree; }
 82   // Degree starts not valid and any change to the IFG neighbor
 83   // set makes it not valid.
 84   void set_degree( uint degree ) {
 85     _eff_degree = degree;
 86     debug_only(_degree_valid = 1;)
 87     assert(!_mask.is_AllStack() || (_mask.is_AllStack() && lo_degree()), "_eff_degree can't be bigger than AllStack_size - _num_regs if the mask supports stack registers");
 88   }
 89   // Made a change that hammered degree
 90   void invalid_degree() { debug_only(_degree_valid=0;) }
 91   // Incrementally modify degree.  If it was correct, it should remain correct
 92   void inc_degree( uint mod ) {
 93     _eff_degree += mod;
 94     assert(!_mask.is_AllStack() || (_mask.is_AllStack() && lo_degree()), "_eff_degree can't be bigger than AllStack_size - _num_regs if the mask supports stack registers");
 95   }
 96   // Compute the degree between 2 live ranges
 97   int compute_degree( LRG &l ) const;
 98   bool mask_is_nonempty_and_up() const {
 99     return mask().is_UP() && mask_size();
100   }
101   bool is_float_or_vector() const {
102     return _is_float || _is_vector;
103   }
104 
105 private:
106   RegMask _mask;                // Allowed registers for this LRG
107   uint _mask_size;              // cache of _mask.Size();
108 public:
109   int compute_mask_size() const { return _mask.is_AllStack() ? AllStack_size : _mask.Size(); }
110   void set_mask_size( int size ) {
111     assert((size == (int)AllStack_size) || (size == (int)_mask.Size()), "");
112     _mask_size = size;
113 #ifdef ASSERT
114     _msize_valid=1;
115     if (_is_vector) {
116       assert(!_fat_proj, "sanity");
117       if (!(_is_scalable && OptoReg::is_stack(_reg))) {
118         assert(_mask.is_aligned_sets(_num_regs), "mask is not aligned, adjacent sets");
119       }
120     } else if (_num_regs == 2 && !_fat_proj) {
121       assert(_mask.is_aligned_pairs(), "mask is not aligned, adjacent pairs");
122     }
123 #endif
124   }
125   void compute_set_mask_size() { set_mask_size(compute_mask_size()); }
126   int mask_size() const { assert( _msize_valid, "mask size not valid" );
127                           return _mask_size; }
128   // Get the last mask size computed, even if it does not match the
129   // count of bits in the current mask.
130   int get_invalid_mask_size() const { return _mask_size; }
131   const RegMask &mask() const { return _mask; }
132   void set_mask( const RegMask &rm ) { _mask = rm; debug_only(_msize_valid=0;)}
133   void AND( const RegMask &rm ) { _mask.AND(rm); debug_only(_msize_valid=0;)}
134   void SUBTRACT( const RegMask &rm ) { _mask.SUBTRACT(rm); debug_only(_msize_valid=0;)}
135   void Clear()   { _mask.Clear()  ; debug_only(_msize_valid=1); _mask_size = 0; }
136   void Set_All() { _mask.Set_All(); debug_only(_msize_valid=1); _mask_size = RegMask::CHUNK_SIZE; }
137 
138   void Insert( OptoReg::Name reg ) { _mask.Insert(reg);  debug_only(_msize_valid=0;) }
139   void Remove( OptoReg::Name reg ) { _mask.Remove(reg);  debug_only(_msize_valid=0;) }
140   void clear_to_sets()  { _mask.clear_to_sets(_num_regs); debug_only(_msize_valid=0;) }
141 
142 private:
143   // Number of registers this live range uses when it colors
144   uint16_t _num_regs;           // 2 for Longs and Doubles, 1 for all else
145                                 // except _num_regs is kill count for fat_proj
146 
147   // For scalable register, num_regs may not be the actual physical register size.
148   // We need to get the actual physical length of scalable register when scalable
149   // register is spilled. The size of one slot is 32-bit.
150   uint _scalable_reg_slots;     // Actual scalable register length of slots.
151                                 // Meaningful only when _is_scalable is true.
152 public:
153   int num_regs() const { return _num_regs; }
154   void set_num_regs( int reg ) { assert( _num_regs == reg || !_num_regs, "" ); _num_regs = reg; }
155 
156   uint scalable_reg_slots() { return _scalable_reg_slots; }
157   void set_scalable_reg_slots(uint slots) {
158     assert(_is_scalable, "scalable register");
159     assert(slots > 0, "slots of scalable register is not valid");
160     _scalable_reg_slots = slots;
161   }
162 
163   bool is_scalable() {
164 #ifdef ASSERT
165     if (_is_scalable) {
166       assert(_is_vector && (_num_regs == RegMask::SlotsPerVecA) ||
167              _is_predicate && (_num_regs == RegMask::SlotsPerRegVectMask), "unexpected scalable reg");
168     }
169 #endif
170     return Matcher::implements_scalable_vector && _is_scalable;
171   }
172 
173 private:
174   // Number of physical registers this live range uses when it colors
175   // Architecture and register-set dependent
176   uint16_t _reg_pressure;
177 public:
178   void set_reg_pressure(int i)  { _reg_pressure = i; }
179   int      reg_pressure() const { return _reg_pressure; }
180 
181   // How much 'wiggle room' does this live range have?
182   // How many color choices can it make (scaled by _num_regs)?
183   int degrees_of_freedom() const { return mask_size() - _num_regs; }
184   // Bound LRGs have ZERO degrees of freedom.  We also count
185   // must_spill as bound.
186   bool is_bound  () const { return _is_bound; }
187   // Negative degrees-of-freedom; even with no neighbors this
188   // live range must spill.
189   bool not_free() const { return degrees_of_freedom() <  0; }
190   // Is this live range of "low-degree"?  Trivially colorable?
191   bool lo_degree () const { return degree() <= degrees_of_freedom(); }
192   // Is this live range just barely "low-degree"?  Trivially colorable?
193   bool just_lo_degree () const { return degree() == degrees_of_freedom(); }
194 
195   uint   _is_oop:1,             // Live-range holds an oop
196          _is_float:1,           // True if in float registers
197          _is_vector:1,          // True if in vector registers
198          _is_predicate:1,       // True if in mask/predicate registers
199          _is_scalable:1,        // True if register size is scalable
200                                 //      e.g. Arm SVE vector/predicate registers.
201          _was_spilled1:1,       // True if prior spilling on def
202          _was_spilled2:1,       // True if twice prior spilling on def
203          _is_bound:1,           // live range starts life with no
204                                 // degrees of freedom.
205          _direct_conflict:1,    // True if def and use registers in conflict
206          _must_spill:1,         // live range has lost all degrees of freedom
207     // If _fat_proj is set, live range does NOT require aligned, adjacent
208     // registers and has NO interferences.
209     // If _fat_proj is clear, live range requires num_regs() to be a power of
210     // 2, and it requires registers to form an aligned, adjacent set.
211          _fat_proj:1,           //
212          _was_lo:1,             // Was lo-degree prior to coalesce
213          _msize_valid:1,        // _mask_size cache valid
214          _degree_valid:1,       // _degree cache valid
215          _has_copy:1,           // Adjacent to some copy instruction
216          _at_risk:1;            // Simplify says this guy is at risk to spill
217 
218 
219   // Alive if non-zero, dead if zero
220   bool alive() const { return _def != NULL; }
221   bool is_multidef() const { return _def == NodeSentinel; }
222   bool is_singledef() const { return _def != NodeSentinel; }
223 
224 #ifndef PRODUCT
225   void dump( ) const;
226 #endif
227 };
228 
229 //------------------------------IFG--------------------------------------------
230 //                         InterFerence Graph
231 // An undirected graph implementation.  Created with a fixed number of
232 // vertices.  Edges can be added & tested.  Vertices can be removed, then
233 // added back later with all edges intact.  Can add edges between one vertex
234 // and a list of other vertices.  Can union vertices (and their edges)
235 // together.  The IFG needs to be really really fast, and also fairly
236 // abstract!  It needs abstraction so I can fiddle with the implementation to
237 // get even more speed.
238 class PhaseIFG : public Phase {
239   friend class VMStructs;
240   // Current implementation: a triangular adjacency list.
241 
242   // Array of adjacency-lists, indexed by live-range number
243   IndexSet *_adjs;
244 
245   // Assertion bit for proper use of Squaring
246   bool _is_square;
247 
248   // Live range structure goes here
249   LRG *_lrgs;                   // Array of LRG structures
250 
251 public:
252   // Largest live-range number
253   uint _maxlrg;
254 
255   Arena *_arena;
256 
257   // Keep track of inserted and deleted Nodes
258   VectorSet *_yanked;
259 
260   PhaseIFG( Arena *arena );
261   void init( uint maxlrg );
262 
263   // Add edge between a and b.  Returns true if actually addded.
264   int add_edge( uint a, uint b );
265 
266   // Test for edge existance
267   int test_edge( uint a, uint b ) const;
268 
269   // Square-up matrix for faster Union
270   void SquareUp();
271 
272   // Return number of LRG neighbors
273   uint neighbor_cnt( uint a ) const { return _adjs[a].count(); }
274   // Union edges of b into a on Squared-up matrix
275   void Union( uint a, uint b );
276   // Test for edge in Squared-up matrix
277   int test_edge_sq( uint a, uint b ) const;
278   // Yank a Node and all connected edges from the IFG.  Be prepared to
279   // re-insert the yanked Node in reverse order of yanking.  Return a
280   // list of neighbors (edges) yanked.
281   IndexSet *remove_node( uint a );
282   // Reinsert a yanked Node
283   void re_insert( uint a );
284   // Return set of neighbors
285   IndexSet *neighbors( uint a ) const { return &_adjs[a]; }
286 
287 #ifndef PRODUCT
288   // Dump the IFG
289   void dump() const;
290   void stats() const;
291   void verify( const PhaseChaitin * ) const;
292 #endif
293 
294   //--------------- Live Range Accessors
295   LRG &lrgs(uint idx) const { assert(idx < _maxlrg, "oob"); return _lrgs[idx]; }
296 
297   // Compute and set effective degree.  Might be folded into SquareUp().
298   void Compute_Effective_Degree();
299 
300   // Compute effective degree as the sum of neighbors' _sizes.
301   int effective_degree( uint lidx ) const;
302 };
303 
304 // The LiveRangeMap class is responsible for storing node to live range id mapping.
305 // Each node is mapped to a live range id (a virtual register). Nodes that are
306 // not considered for register allocation are given live range id 0.
307 class LiveRangeMap {
308 
309 private:
310 
311   uint _max_lrg_id;
312 
313   // Union-find map.  Declared as a short for speed.
314   // Indexed by live-range number, it returns the compacted live-range number
315   LRG_List _uf_map;
316 
317   // Map from Nodes to live ranges
318   LRG_List _names;
319 
320   // Straight out of Tarjan's union-find algorithm
321   uint find_compress(const Node *node) {
322     uint lrg_id = find_compress(_names.at(node->_idx));
323     _names.at_put(node->_idx, lrg_id);
324     return lrg_id;
325   }
326 
327   uint find_compress(uint lrg);
328 
329 public:
330 
331   const LRG_List& names() {
332     return _names;
333   }
334 
335   uint max_lrg_id() const {
336     return _max_lrg_id;
337   }
338 
339   void set_max_lrg_id(uint max_lrg_id) {
340     _max_lrg_id = max_lrg_id;
341   }
342 
343   uint size() const {
344     return _names.length();
345   }
346 
347   uint live_range_id(uint idx) const {
348     return _names.at(idx);
349   }
350 
351   uint live_range_id(const Node *node) const {
352     return _names.at(node->_idx);
353   }
354 
355   uint uf_live_range_id(uint lrg_id) const {
356     return _uf_map.at(lrg_id);
357   }
358 
359   void map(uint idx, uint lrg_id) {
360     _names.at_put(idx, lrg_id);
361   }
362 
363   void uf_map(uint dst_lrg_id, uint src_lrg_id) {
364     _uf_map.at_put(dst_lrg_id, src_lrg_id);
365   }
366 
367   void extend(uint idx, uint lrg_id) {
368     _names.at_put_grow(idx, lrg_id);
369   }
370 
371   void uf_extend(uint dst_lrg_id, uint src_lrg_id) {
372     _uf_map.at_put_grow(dst_lrg_id, src_lrg_id);
373   }
374 
375   LiveRangeMap(Arena* arena, uint unique)
376   :  _max_lrg_id(0)
377   , _uf_map(arena, unique, unique, 0)
378   , _names(arena, unique, unique, 0) {}
379 
380   uint find_id( const Node *n ) {
381     uint retval = live_range_id(n);
382     assert(retval == find(n),"Invalid node to lidx mapping");
383     return retval;
384   }
385 
386   // Reset the Union-Find map to identity
387   void reset_uf_map(uint max_lrg_id);
388 
389   // Make all Nodes map directly to their final live range; no need for
390   // the Union-Find mapping after this call.
391   void compress_uf_map_for_nodes();
392 
393   uint find(uint lidx) {
394     uint uf_lidx = _uf_map.at(lidx);
395     return (uf_lidx == lidx) ? uf_lidx : find_compress(lidx);
396   }
397 
398   // Convert a Node into a Live Range Index - a lidx
399   uint find(const Node *node) {
400     uint lidx = live_range_id(node);
401     uint uf_lidx = _uf_map.at(lidx);
402     return (uf_lidx == lidx) ? uf_lidx : find_compress(node);
403   }
404 
405   // Like Find above, but no path compress, so bad asymptotic behavior
406   uint find_const(uint lrg) const;
407 
408   // Like Find above, but no path compress, so bad asymptotic behavior
409   uint find_const(const Node *node) const {
410     if(node->_idx >= (uint)_names.length()) {
411       return 0; // not mapped, usual for debug dump
412     }
413     return find_const(_names.at(node->_idx));
414   }
415 };
416 
417 //------------------------------Chaitin----------------------------------------
418 // Briggs-Chaitin style allocation, mostly.
419 class PhaseChaitin : public PhaseRegAlloc {
420   friend class VMStructs;
421 
422   int _trip_cnt;
423   int _alternate;
424 
425   PhaseLive *_live;             // Liveness, used in the interference graph
426   PhaseIFG *_ifg;               // Interference graph (for original chunk)
427   VectorSet _spilled_once;      // Nodes that have been spilled
428   VectorSet _spilled_twice;     // Nodes that have been spilled twice
429 
430   // Combine the Live Range Indices for these 2 Nodes into a single live
431   // range.  Future requests for any Node in either live range will
432   // return the live range index for the combined live range.
433   void Union( const Node *src, const Node *dst );
434 
435   void new_lrg( const Node *x, uint lrg );
436 
437   // Compact live ranges, removing unused ones.  Return new maxlrg.
438   void compact();
439 
440   uint _lo_degree;              // Head of lo-degree LRGs list
441   uint _lo_stk_degree;          // Head of lo-stk-degree LRGs list
442   uint _hi_degree;              // Head of hi-degree LRGs list
443   uint _simplified;             // Linked list head of simplified LRGs
444 
445   // Helper functions for Split()
446   uint split_DEF(Node *def, Block *b, int loc, uint max, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx );
447   int split_USE(MachSpillCopyNode::SpillType spill_type, Node *def, Block *b, Node *use, uint useidx, uint max, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx );
448 
449   //------------------------------clone_projs------------------------------------
450   // After cloning some rematerialized instruction, clone any MachProj's that
451   // follow it.  Example: Intel zero is XOR, kills flags.  Sparc FP constants
452   // use G3 as an address temp.
453   int clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id);
454 
455   int clone_projs(Block* b, uint idx, Node* orig, Node* copy, LiveRangeMap& lrg_map) {
456     uint max_lrg_id = lrg_map.max_lrg_id();
457     int found_projs = clone_projs(b, idx, orig, copy, max_lrg_id);
458     if (found_projs > 0) {
459       // max_lrg_id is updated during call above
460       lrg_map.set_max_lrg_id(max_lrg_id);
461     }
462     return found_projs;
463   }
464 
465   Node *split_Rematerialize(Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits,
466                             int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru);
467   // True if lidx is used before any real register is def'd in the block
468   bool prompt_use( Block *b, uint lidx );
469   Node *get_spillcopy_wide(MachSpillCopyNode::SpillType spill_type, Node *def, Node *use, uint uidx );
470   // Insert the spill at chosen location.  Skip over any intervening Proj's or
471   // Phis.  Skip over a CatchNode and projs, inserting in the fall-through block
472   // instead.  Update high-pressure indices.  Create a new live range.
473   void insert_proj( Block *b, uint i, Node *spill, uint maxlrg );
474 
475   bool is_high_pressure( Block *b, LRG *lrg, uint insidx );
476 
477   uint _oldphi;                 // Node index which separates pre-allocation nodes
478 
479   Block **_blks;                // Array of blocks sorted by frequency for coalescing
480 
481   float _high_frequency_lrg;    // Frequency at which LRG will be spilled for debug info
482 
483 #ifndef PRODUCT
484   bool _trace_spilling;
485 #endif
486 
487 public:
488   PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher, bool track_liveout_pressure);
489   ~PhaseChaitin() {}
490 
491   LiveRangeMap _lrg_map;
492 
493   LRG &lrgs(uint idx) const { return _ifg->lrgs(idx); }
494 
495   // Do all the real work of allocate
496   void Register_Allocate();
497 
498   float high_frequency_lrg() const { return _high_frequency_lrg; }
499 
500   // Used when scheduling info generated, not in general register allocation
501   bool _scheduling_info_generated;
502 
503   void set_ifg(PhaseIFG &ifg) { _ifg = &ifg;  }
504   void set_live(PhaseLive &live) { _live = &live; }
505   PhaseLive* get_live() { return _live; }
506 
507   // Populate the live range maps with ssa info for scheduling
508   void mark_ssa();
509 
510 #ifndef PRODUCT
511   bool trace_spilling() const { return _trace_spilling; }
512 #endif
513 
514 private:
515   // De-SSA the world.  Assign registers to Nodes.  Use the same register for
516   // all inputs to a PhiNode, effectively coalescing live ranges.  Insert
517   // copies as needed.
518   void de_ssa();
519 
520   // Add edge between reg and everything in the vector.
521   // Use the RegMask information to trim the set of interferences.  Return the
522   // count of edges added.
523   void interfere_with_live(uint lid, IndexSet* liveout);
524 #ifdef ASSERT
525   // Count register pressure for asserts
526   uint count_int_pressure(IndexSet* liveout);
527   uint count_float_pressure(IndexSet* liveout);
528 #endif
529 
530   // Build the interference graph using virtual registers only.
531   // Used for aggressive coalescing.
532   void build_ifg_virtual( );
533 
534   // used when computing the register pressure for each block in the CFG. This
535   // is done during IFG creation.
536   class Pressure {
537       // keeps track of the register pressure at the current
538       // instruction (used when stepping backwards in the block)
539       uint _current_pressure;
540 
541       // keeps track of the instruction index of the first low to high register pressure
542       // transition (starting from the top) in the block
543       // if high_pressure_index == 0 then the whole block is high pressure
544       // if high_pressure_index = b.end_idx() + 1 then the whole block is low pressure
545       uint _high_pressure_index;
546 
547       // stores the highest pressure we find
548       uint _final_pressure;
549 
550       // number of live ranges that constitute high register pressure
551       uint _high_pressure_limit;
552 
553       // initial pressure observed
554       uint _start_pressure;
555 
556     public:
557 
558       // lower the register pressure and look for a low to high pressure
559       // transition
560       void lower(LRG& lrg, uint& location) {
561         _current_pressure -= lrg.reg_pressure();
562         if (_current_pressure == _high_pressure_limit) {
563           _high_pressure_index = location;
564         }
565       }
566 
567       // raise the pressure and store the pressure if it's the biggest
568       // pressure so far
569       void raise(LRG &lrg) {
570         _current_pressure += lrg.reg_pressure();
571         if (_current_pressure > _final_pressure) {
572           _final_pressure = _current_pressure;
573         }
574       }
575 
576       void init(int limit) {
577         _current_pressure = 0;
578         _high_pressure_index = 0;
579         _final_pressure = 0;
580         _high_pressure_limit = limit;
581         _start_pressure = 0;
582       }
583 
584       uint high_pressure_index() const {
585         return _high_pressure_index;
586       }
587 
588       uint final_pressure() const {
589         return _final_pressure;
590       }
591 
592       uint start_pressure() const {
593         return _start_pressure;
594       }
595 
596       uint current_pressure() const {
597         return _current_pressure;
598       }
599 
600       uint high_pressure_limit() const {
601         return _high_pressure_limit;
602       }
603 
604       void lower_high_pressure_index() {
605         _high_pressure_index--;
606       }
607 
608       void set_high_pressure_index_to_block_start() {
609         _high_pressure_index = 0;
610       }
611 
612       void set_start_pressure(int value) {
613         _start_pressure = value;
614         _final_pressure = value;
615       }
616 
617       void set_current_pressure(int value) {
618         _current_pressure = value;
619       }
620 
621       void check_pressure_at_fatproj(uint fatproj_location, RegMask& fatproj_mask) {
622         // this pressure is only valid at this instruction, i.e. we don't need to lower
623         // the register pressure since the fat proj was never live before (going backwards)
624         uint new_pressure = current_pressure() + fatproj_mask.Size();
625         if (new_pressure > final_pressure()) {
626           _final_pressure = new_pressure;
627         }
628 
629         // if we were at a low pressure and now and the fat proj is at high pressure, record the fat proj location
630         // as coming from a low to high (to low again)
631         if (current_pressure() <= high_pressure_limit() && new_pressure > high_pressure_limit()) {
632           _high_pressure_index = fatproj_location;
633         }
634       }
635 
636       Pressure(uint high_pressure_index, uint high_pressure_limit)
637         : _current_pressure(0)
638         , _high_pressure_index(high_pressure_index)
639         , _final_pressure(0)
640         , _high_pressure_limit(high_pressure_limit)
641         , _start_pressure(0) {}
642   };
643 
644   void check_for_high_pressure_transition_at_fatproj(uint& block_reg_pressure, uint location, LRG& lrg, Pressure& pressure, const int op_regtype);
645   void add_input_to_liveout(Block* b, Node* n, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure);
646   void compute_initial_block_pressure(Block* b, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure, double cost);
647   bool remove_node_if_not_used(Block* b, uint location, Node* n, uint lid, IndexSet* liveout);
648   void assign_high_score_to_immediate_copies(Block* b, Node* n, LRG& lrg, uint next_inst, uint last_inst);
649   void remove_interference_from_copy(Block* b, uint location, uint lid_copy, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure);
650   void remove_bound_register_from_interfering_live_ranges(LRG& lrg, IndexSet* liveout, uint& must_spill);
651   void check_for_high_pressure_block(Pressure& pressure);
652   void adjust_high_pressure_index(Block* b, uint& hrp_index, Pressure& pressure);
653 
654   // Build the interference graph using physical registers when available.
655   // That is, if 2 live ranges are simultaneously alive but in their
656   // acceptable register sets do not overlap, then they do not interfere.
657   uint build_ifg_physical( ResourceArea *a );
658 
659 public:
660   // Gather LiveRanGe information, including register masks and base pointer/
661   // derived pointer relationships.
662   void gather_lrg_masks( bool mod_cisc_masks );
663 
664   // user visible pressure variables for scheduling
665   Pressure _sched_int_pressure;
666   Pressure _sched_float_pressure;
667   Pressure _scratch_int_pressure;
668   Pressure _scratch_float_pressure;
669 
670   // Pressure functions for user context
671   void lower_pressure(Block* b, uint location, LRG& lrg, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure);
672   void raise_pressure(Block* b, LRG& lrg, Pressure& int_pressure, Pressure& float_pressure);
673   void compute_entry_block_pressure(Block* b);
674   void compute_exit_block_pressure(Block* b);
675   void print_pressure_info(Pressure& pressure, const char *str);
676 
677 private:
678   // Force the bases of derived pointers to be alive at GC points.
679   bool stretch_base_pointer_live_ranges( ResourceArea *a );
680   // Helper to stretch above; recursively discover the base Node for
681   // a given derived Node.  Easy for AddP-related machine nodes, but
682   // needs to be recursive for derived Phis.
683   Node *find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg );
684 
685   // Set the was-lo-degree bit.  Conservative coalescing should not change the
686   // colorability of the graph.  If any live range was of low-degree before
687   // coalescing, it should Simplify.  This call sets the was-lo-degree bit.
688   void set_was_low();
689 
690   // Init LRG caching of degree, numregs.  Init lo_degree list.
691   void cache_lrg_info( );
692 
693   // Simplify the IFG by removing LRGs of low degree
694   void Simplify();
695 
696   // Select colors by re-inserting edges into the IFG.
697   // Return TRUE if any spills occurred.
698   uint Select( );
699   // Helper function for select which allows biased coloring
700   OptoReg::Name choose_color( LRG &lrg, int chunk );
701   // Helper function which implements biasing heuristic
702   OptoReg::Name bias_color( LRG &lrg, int chunk );
703 
704   // Split uncolorable live ranges
705   // Return new number of live ranges
706   uint Split(uint maxlrg, ResourceArea* split_arena);
707 
708   // Set the 'spilled_once' or 'spilled_twice' flag on a node.
709   void set_was_spilled( Node *n );
710 
711   // Convert ideal spill-nodes into machine loads & stores
712   // Set C->failing when fixup spills could not complete, node limit exceeded.
713   void fixup_spills();
714 
715   // Post-Allocation peephole copy removal
716   void post_allocate_copy_removal();
717   Node *skip_copies( Node *c );
718   // Replace the old node with the current live version of that value
719   // and yank the old value if it's dead.
720   int replace_and_yank_if_dead( Node *old, OptoReg::Name nreg,
721       Block *current_block, Node_List& value, Node_List& regnd ) {
722     Node* v = regnd[nreg];
723     assert(v->outcnt() != 0, "no dead values");
724     old->replace_by(v);
725     return yank_if_dead(old, current_block, &value, &regnd);
726   }
727 
728   int yank_if_dead( Node *old, Block *current_block, Node_List *value, Node_List *regnd ) {
729     return yank_if_dead_recurse(old, old, current_block, value, regnd);
730   }
731   int yank_if_dead_recurse(Node *old, Node *orig_old, Block *current_block,
732       Node_List *value, Node_List *regnd);
733   int yank( Node *old, Block *current_block, Node_List *value, Node_List *regnd );
734   int elide_copy( Node *n, int k, Block *current_block, Node_List &value, Node_List &regnd, bool can_change_regs );
735   int use_prior_register( Node *copy, uint idx, Node *def, Block *current_block, Node_List &value, Node_List &regnd );
736   bool may_be_copy_of_callee( Node *def ) const;
737 
738   // If nreg already contains the same constant as val then eliminate it
739   bool eliminate_copy_of_constant(Node* val, Node* n,
740       Block *current_block, Node_List& value, Node_List &regnd,
741       OptoReg::Name nreg, OptoReg::Name nreg2);
742   // Extend the node to LRG mapping
743   void add_reference( const Node *node, const Node *old_node);
744 
745   // Record the first use of a def in the block for a register.
746   class RegDefUse {
747     Node* _def;
748     Node* _first_use;
749   public:
750     RegDefUse() : _def(NULL), _first_use(NULL) { }
751     Node* def() const       { return _def;       }
752     Node* first_use() const { return _first_use; }
753 
754     void update(Node* def, Node* use) {
755       if (_def != def) {
756         _def = def;
757         _first_use = use;
758       }
759     }
760     void clear() {
761       _def = NULL;
762       _first_use = NULL;
763     }
764   };
765   typedef GrowableArray<RegDefUse> RegToDefUseMap;
766   int possibly_merge_multidef(Node *n, uint k, Block *block, RegToDefUseMap& reg2defuse);
767 
768   // Merge nodes that are a part of a multidef lrg and produce the same value within a block.
769   void merge_multidefs();
770 
771 private:
772 
773   static int _final_loads, _final_stores, _final_copies, _final_memoves;
774   static double _final_load_cost, _final_store_cost, _final_copy_cost, _final_memove_cost;
775   static int _conserv_coalesce, _conserv_coalesce_pair;
776   static int _conserv_coalesce_trie, _conserv_coalesce_quad;
777   static int _post_alloc;
778   static int _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce;
779   static int _used_cisc_instructions, _unused_cisc_instructions;
780   static int _allocator_attempts, _allocator_successes;
781 
782 #ifdef ASSERT
783   // Verify that base pointers and derived pointers are still sane
784   void verify_base_ptrs(ResourceArea* a) const;
785   void verify(ResourceArea* a, bool verify_ifg = false) const;
786 #endif // ASSERT
787 
788 #ifndef PRODUCT
789   static uint _high_pressure, _low_pressure;
790 
791   void dump() const;
792   void dump(const Node* n) const;
793   void dump(const Block* b) const;
794   void dump_degree_lists() const;
795   void dump_simplified() const;
796   void dump_lrg(uint lidx, bool defs_only) const;
797   void dump_lrg(uint lidx) const {
798     // dump defs and uses by default
799     dump_lrg(lidx, false);
800   }
801   void dump_bb(uint pre_order) const;
802   void dump_for_spill_split_recycle() const;
803 
804 public:
805   void dump_frame() const;
806   char *dump_register(const Node* n, char* buf) const;
807 private:
808   static void print_chaitin_statistics();
809 #endif // not PRODUCT
810   friend class PhaseCoalesce;
811   friend class PhaseAggressiveCoalesce;
812   friend class PhaseConservativeCoalesce;
813 };
814 
815 #endif // SHARE_OPTO_CHAITIN_HPP