2124 // CastPP nodes.
2125 remove_speculative_types(igvn);
2126
2127 // No more new expensive nodes will be added to the list from here
2128 // so keep only the actual candidates for optimizations.
2129 cleanup_expensive_nodes(igvn);
2130
2131 assert(EnableVectorSupport || !has_vbox_nodes(), "sanity");
2132 if (EnableVectorSupport && has_vbox_nodes()) {
2133 TracePhase tp("", &timers[_t_vector]);
2134 PhaseVector pv(igvn);
2135 pv.optimize_vector_boxes();
2136
2137 print_method(PHASE_ITER_GVN_AFTER_VECTOR, 2);
2138 }
2139 assert(!has_vbox_nodes(), "sanity");
2140
2141 if (!failing() && RenumberLiveNodes && live_nodes() + NodeLimitFudgeFactor < unique()) {
2142 Compile::TracePhase tp("", &timers[_t_renumberLive]);
2143 initial_gvn()->replace_with(&igvn);
2144 for_igvn()->clear();
2145 Unique_Node_List new_worklist(C->comp_arena());
2146 {
2147 ResourceMark rm;
2148 PhaseRenumberLive prl = PhaseRenumberLive(initial_gvn(), for_igvn(), &new_worklist);
2149 }
2150 Unique_Node_List* save_for_igvn = for_igvn();
2151 set_for_igvn(&new_worklist);
2152 igvn = PhaseIterGVN(initial_gvn());
2153 igvn.optimize();
2154 set_for_igvn(save_for_igvn);
2155 }
2156
2157 // Now that all inlining is over and no PhaseRemoveUseless will run, cut edge from root to loop
2158 // safepoints
2159 remove_root_to_sfpts_edges(igvn);
2160
2161 // Perform escape analysis
2162 if (_do_escape_analysis && ConnectionGraph::has_candidates(this)) {
2163 if (has_loops()) {
2164 // Cleanup graph (remove dead nodes).
2165 TracePhase tp("idealLoop", &timers[_t_idealLoop]);
2166 PhaseIdealLoop::optimize(igvn, LoopOptsMaxUnroll);
2167 if (major_progress()) print_method(PHASE_PHASEIDEAL_BEFORE_EA, 2);
2168 if (failing()) return;
2169 }
2170 ConnectionGraph::do_analysis(this, &igvn);
2171
2172 if (failing()) return;
2173
2174 // Optimize out fields loads from scalar replaceable allocations.
2348 }
2349
2350 bool Compile::has_vbox_nodes() {
2351 if (C->_vector_reboxing_late_inlines.length() > 0) {
2352 return true;
2353 }
2354 for (int macro_idx = C->macro_count() - 1; macro_idx >= 0; macro_idx--) {
2355 Node * n = C->macro_node(macro_idx);
2356 assert(n->is_macro(), "only macro nodes expected here");
2357 if (n->Opcode() == Op_VectorUnbox || n->Opcode() == Op_VectorBox || n->Opcode() == Op_VectorBoxAllocate) {
2358 return true;
2359 }
2360 }
2361 return false;
2362 }
2363
2364 //---------------------------- Bitwise operation packing optimization ---------------------------
2365
2366 static bool is_vector_unary_bitwise_op(Node* n) {
2367 return n->Opcode() == Op_XorV &&
2368 VectorNode::is_vector_bitwise_not_pattern(n);
2369 }
2370
2371 static bool is_vector_binary_bitwise_op(Node* n) {
2372 switch (n->Opcode()) {
2373 case Op_AndV:
2374 case Op_OrV:
2375 return true;
2376
2377 case Op_XorV:
2378 return !is_vector_unary_bitwise_op(n);
2379
2380 default:
2381 return false;
2382 }
2383 }
2384
2385 static bool is_vector_ternary_bitwise_op(Node* n) {
2386 return n->Opcode() == Op_MacroLogicV;
2387 }
2388
2389 static bool is_vector_bitwise_op(Node* n) {
2390 return is_vector_unary_bitwise_op(n) ||
2391 is_vector_binary_bitwise_op(n) ||
2392 is_vector_ternary_bitwise_op(n);
2393 }
2394
2395 static bool is_vector_bitwise_cone_root(Node* n) {
3414 if (d) {
3415 // Replace them with a fused divmod if supported
3416 if (Matcher::has_match_rule(Op_DivModL)) {
3417 DivModLNode* divmod = DivModLNode::make(n);
3418 d->subsume_by(divmod->div_proj(), this);
3419 n->subsume_by(divmod->mod_proj(), this);
3420 } else {
3421 // replace a%b with a-((a/b)*b)
3422 Node* mult = new MulLNode(d, d->in(2));
3423 Node* sub = new SubLNode(d->in(1), mult);
3424 n->subsume_by(sub, this);
3425 }
3426 }
3427 }
3428 break;
3429
3430 case Op_LoadVector:
3431 case Op_StoreVector:
3432 case Op_LoadVectorGather:
3433 case Op_StoreVectorScatter:
3434 case Op_VectorCmpMasked:
3435 case Op_VectorMaskGen:
3436 case Op_LoadVectorMasked:
3437 case Op_StoreVectorMasked:
3438 break;
3439
3440 case Op_AddReductionVI:
3441 case Op_AddReductionVL:
3442 case Op_AddReductionVF:
3443 case Op_AddReductionVD:
3444 case Op_MulReductionVI:
3445 case Op_MulReductionVL:
3446 case Op_MulReductionVF:
3447 case Op_MulReductionVD:
3448 case Op_MinReductionV:
3449 case Op_MaxReductionV:
3450 case Op_AndReductionV:
3451 case Op_OrReductionV:
3452 case Op_XorReductionV:
3453 break;
|
2124 // CastPP nodes.
2125 remove_speculative_types(igvn);
2126
2127 // No more new expensive nodes will be added to the list from here
2128 // so keep only the actual candidates for optimizations.
2129 cleanup_expensive_nodes(igvn);
2130
2131 assert(EnableVectorSupport || !has_vbox_nodes(), "sanity");
2132 if (EnableVectorSupport && has_vbox_nodes()) {
2133 TracePhase tp("", &timers[_t_vector]);
2134 PhaseVector pv(igvn);
2135 pv.optimize_vector_boxes();
2136
2137 print_method(PHASE_ITER_GVN_AFTER_VECTOR, 2);
2138 }
2139 assert(!has_vbox_nodes(), "sanity");
2140
2141 if (!failing() && RenumberLiveNodes && live_nodes() + NodeLimitFudgeFactor < unique()) {
2142 Compile::TracePhase tp("", &timers[_t_renumberLive]);
2143 initial_gvn()->replace_with(&igvn);
2144 Unique_Node_List* old_worklist = for_igvn();
2145 old_worklist->clear();
2146 Unique_Node_List new_worklist(C->comp_arena());
2147 {
2148 ResourceMark rm;
2149 PhaseRenumberLive prl = PhaseRenumberLive(initial_gvn(), for_igvn(), &new_worklist);
2150 }
2151 Unique_Node_List* save_for_igvn = for_igvn();
2152 set_for_igvn(&new_worklist);
2153 igvn = PhaseIterGVN(initial_gvn());
2154 igvn.optimize();
2155 set_for_igvn(old_worklist); // new_worklist is dead beyond this point
2156 }
2157
2158 // Now that all inlining is over and no PhaseRemoveUseless will run, cut edge from root to loop
2159 // safepoints
2160 remove_root_to_sfpts_edges(igvn);
2161
2162 // Perform escape analysis
2163 if (_do_escape_analysis && ConnectionGraph::has_candidates(this)) {
2164 if (has_loops()) {
2165 // Cleanup graph (remove dead nodes).
2166 TracePhase tp("idealLoop", &timers[_t_idealLoop]);
2167 PhaseIdealLoop::optimize(igvn, LoopOptsMaxUnroll);
2168 if (major_progress()) print_method(PHASE_PHASEIDEAL_BEFORE_EA, 2);
2169 if (failing()) return;
2170 }
2171 ConnectionGraph::do_analysis(this, &igvn);
2172
2173 if (failing()) return;
2174
2175 // Optimize out fields loads from scalar replaceable allocations.
2349 }
2350
2351 bool Compile::has_vbox_nodes() {
2352 if (C->_vector_reboxing_late_inlines.length() > 0) {
2353 return true;
2354 }
2355 for (int macro_idx = C->macro_count() - 1; macro_idx >= 0; macro_idx--) {
2356 Node * n = C->macro_node(macro_idx);
2357 assert(n->is_macro(), "only macro nodes expected here");
2358 if (n->Opcode() == Op_VectorUnbox || n->Opcode() == Op_VectorBox || n->Opcode() == Op_VectorBoxAllocate) {
2359 return true;
2360 }
2361 }
2362 return false;
2363 }
2364
2365 //---------------------------- Bitwise operation packing optimization ---------------------------
2366
2367 static bool is_vector_unary_bitwise_op(Node* n) {
2368 return n->Opcode() == Op_XorV &&
2369 n->req() == 2 &&
2370 VectorNode::is_vector_bitwise_not_pattern(n);
2371 }
2372
2373 static bool is_vector_binary_bitwise_op(Node* n) {
2374 switch (n->Opcode()) {
2375 case Op_AndV:
2376 case Op_OrV:
2377 return n->req() == 2;
2378
2379 case Op_XorV:
2380 return !is_vector_unary_bitwise_op(n);
2381
2382 default:
2383 return false;
2384 }
2385 }
2386
2387 static bool is_vector_ternary_bitwise_op(Node* n) {
2388 return n->Opcode() == Op_MacroLogicV;
2389 }
2390
2391 static bool is_vector_bitwise_op(Node* n) {
2392 return is_vector_unary_bitwise_op(n) ||
2393 is_vector_binary_bitwise_op(n) ||
2394 is_vector_ternary_bitwise_op(n);
2395 }
2396
2397 static bool is_vector_bitwise_cone_root(Node* n) {
3416 if (d) {
3417 // Replace them with a fused divmod if supported
3418 if (Matcher::has_match_rule(Op_DivModL)) {
3419 DivModLNode* divmod = DivModLNode::make(n);
3420 d->subsume_by(divmod->div_proj(), this);
3421 n->subsume_by(divmod->mod_proj(), this);
3422 } else {
3423 // replace a%b with a-((a/b)*b)
3424 Node* mult = new MulLNode(d, d->in(2));
3425 Node* sub = new SubLNode(d->in(1), mult);
3426 n->subsume_by(sub, this);
3427 }
3428 }
3429 }
3430 break;
3431
3432 case Op_LoadVector:
3433 case Op_StoreVector:
3434 case Op_LoadVectorGather:
3435 case Op_StoreVectorScatter:
3436 case Op_LoadVectorGatherMasked:
3437 case Op_StoreVectorScatterMasked:
3438 case Op_VectorCmpMasked:
3439 case Op_VectorMaskGen:
3440 case Op_LoadVectorMasked:
3441 case Op_StoreVectorMasked:
3442 break;
3443
3444 case Op_AddReductionVI:
3445 case Op_AddReductionVL:
3446 case Op_AddReductionVF:
3447 case Op_AddReductionVD:
3448 case Op_MulReductionVI:
3449 case Op_MulReductionVL:
3450 case Op_MulReductionVF:
3451 case Op_MulReductionVD:
3452 case Op_MinReductionV:
3453 case Op_MaxReductionV:
3454 case Op_AndReductionV:
3455 case Op_OrReductionV:
3456 case Op_XorReductionV:
3457 break;
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