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src/hotspot/share/opto/postaloc.cpp

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*** 1,7 ***
  /*
!  * Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ---
  /*
!  * Copyright (c) 1998, 2021, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.

*** 307,21 ***
      Node *vv = value[reg];
      // For scalable register, number of registers may be inconsistent between
      // "val_reg" and "reg". For example, when "val" resides in register
      // but "reg" is located in stack.
      if (lrgs(val_idx).is_scalable()) {
!       assert(val->ideal_reg() == Op_VecA, "scalable vector register");
        if (OptoReg::is_stack(reg)) {
          n_regs = lrgs(val_idx).scalable_reg_slots();
        } else {
!         n_regs = RegMask::SlotsPerVecA;
        }
      }
      if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set
        uint last;
!       if (lrgs(val_idx).is_scalable()) {
-         assert(val->ideal_reg() == Op_VecA, "scalable vector register");
          // For scalable vector register, regmask is always SlotsPerVecA bits aligned
          last = RegMask::SlotsPerVecA - 1;
        } else {
          last = (n_regs-1); // Looking for the last part of a set
        }
--- 307,20 ---
      Node *vv = value[reg];
      // For scalable register, number of registers may be inconsistent between
      // "val_reg" and "reg". For example, when "val" resides in register
      // but "reg" is located in stack.
      if (lrgs(val_idx).is_scalable()) {
!       assert(val->ideal_reg() == Op_VecA || val->ideal_reg() == Op_RegVectMask, "scalable register");
        if (OptoReg::is_stack(reg)) {
          n_regs = lrgs(val_idx).scalable_reg_slots();
        } else {
!         n_regs = lrgs(val_idx)._is_predicate ? RegMask::SlotsPerRegVectMask : RegMask::SlotsPerVecA;
        }
      }
      if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set
        uint last;
!       if (lrgs(val_idx).is_scalable() && val->ideal_reg() == Op_VecA) {
          // For scalable vector register, regmask is always SlotsPerVecA bits aligned
          last = RegMask::SlotsPerVecA - 1;
        } else {
          last = (n_regs-1); // Looking for the last part of a set
        }
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