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src/hotspot/share/opto/postaloc.cpp

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  1 /*
  2  * Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *

292   for( uint reg = 0; reg < (uint)_max_reg; reg++ ) {
293     if (reg == (uint)nk_reg) {
294       // Found ourselves so check if there is only one user of this
295       // copy and keep on searching for a better copy if so.
296       bool ignore_self = true;
297       x = n->in(k);
298       DUIterator_Fast imax, i = x->fast_outs(imax);
299       Node* first = x->fast_out(i); i++;
300       while (i < imax && ignore_self) {
301         Node* use = x->fast_out(i); i++;
302         if (use != first) ignore_self = false;
303       }
304       if (ignore_self) continue;
305     }
306 
307     Node *vv = value[reg];
308     // For scalable register, number of registers may be inconsistent between
309     // "val_reg" and "reg". For example, when "val" resides in register
310     // but "reg" is located in stack.
311     if (lrgs(val_idx).is_scalable()) {
312       assert(val->ideal_reg() == Op_VecA, "scalable vector register");
313       if (OptoReg::is_stack(reg)) {
314         n_regs = lrgs(val_idx).scalable_reg_slots();
315       } else {
316         n_regs = RegMask::SlotsPerVecA;
317       }
318     }
319     if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set
320       uint last;
321       if (lrgs(val_idx).is_scalable()) {
322         assert(val->ideal_reg() == Op_VecA, "scalable vector register");
323         // For scalable vector register, regmask is always SlotsPerVecA bits aligned
324         last = RegMask::SlotsPerVecA - 1;
325       } else {
326         last = (n_regs-1); // Looking for the last part of a set
327       }
328       if ((reg&last) != last) continue; // Wrong part of a set
329       if (!register_contains_value(vv, reg, n_regs, value)) continue; // Different value
330     }
331     if( vv == val ||            // Got a direct hit?
332         (t && vv && vv->bottom_type() == t && vv->is_Mach() &&
333          vv->as_Mach()->rule() == val->as_Mach()->rule()) ) { // Or same constant?
334       assert( !n->is_Phi(), "cannot change registers at a Phi so easily" );
335       if( OptoReg::is_stack(nk_reg) || // CISC-loading from stack OR
336           OptoReg::is_reg(reg) || // turning into a register use OR
337           regnd[reg]->outcnt()==1 ) { // last use of a spill-load turns into a CISC use
338         blk_adjust += use_prior_register(n,k,regnd[reg],current_block,value,regnd);
339         if( n->in(k) == regnd[reg] ) // Success!  Quit trying
340           return blk_adjust;
341       } // End of if not degrading to a stack
342     } // End of if found value in another register

  1 /*
  2  * Copyright (c) 1998, 2021, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *

292   for( uint reg = 0; reg < (uint)_max_reg; reg++ ) {
293     if (reg == (uint)nk_reg) {
294       // Found ourselves so check if there is only one user of this
295       // copy and keep on searching for a better copy if so.
296       bool ignore_self = true;
297       x = n->in(k);
298       DUIterator_Fast imax, i = x->fast_outs(imax);
299       Node* first = x->fast_out(i); i++;
300       while (i < imax && ignore_self) {
301         Node* use = x->fast_out(i); i++;
302         if (use != first) ignore_self = false;
303       }
304       if (ignore_self) continue;
305     }
306 
307     Node *vv = value[reg];
308     // For scalable register, number of registers may be inconsistent between
309     // "val_reg" and "reg". For example, when "val" resides in register
310     // but "reg" is located in stack.
311     if (lrgs(val_idx).is_scalable()) {
312       assert(val->ideal_reg() == Op_VecA || val->ideal_reg() == Op_RegVectMask, "scalable register");
313       if (OptoReg::is_stack(reg)) {
314         n_regs = lrgs(val_idx).scalable_reg_slots();
315       } else {
316         n_regs = lrgs(val_idx)._is_predicate ? RegMask::SlotsPerRegVectMask : RegMask::SlotsPerVecA;
317       }
318     }
319     if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set
320       uint last;
321       if (lrgs(val_idx).is_scalable() && val->ideal_reg() == Op_VecA) {

322         // For scalable vector register, regmask is always SlotsPerVecA bits aligned
323         last = RegMask::SlotsPerVecA - 1;
324       } else {
325         last = (n_regs-1); // Looking for the last part of a set
326       }
327       if ((reg&last) != last) continue; // Wrong part of a set
328       if (!register_contains_value(vv, reg, n_regs, value)) continue; // Different value
329     }
330     if( vv == val ||            // Got a direct hit?
331         (t && vv && vv->bottom_type() == t && vv->is_Mach() &&
332          vv->as_Mach()->rule() == val->as_Mach()->rule()) ) { // Or same constant?
333       assert( !n->is_Phi(), "cannot change registers at a Phi so easily" );
334       if( OptoReg::is_stack(nk_reg) || // CISC-loading from stack OR
335           OptoReg::is_reg(reg) || // turning into a register use OR
336           regnd[reg]->outcnt()==1 ) { // last use of a spill-load turns into a CISC use
337         blk_adjust += use_prior_register(n,k,regnd[reg],current_block,value,regnd);
338         if( n->in(k) == regnd[reg] ) // Success!  Quit trying
339           return blk_adjust;
340       } // End of if not degrading to a stack
341     } // End of if found value in another register
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