1 import os
   2 import random
   3 import subprocess
   4 import sys
   5 
   6 AARCH64_AS = "as"
   7 AARCH64_OBJDUMP = "objdump"
   8 AARCH64_OBJCOPY = "objcopy"
   9 
  10 # These tables are legal immediate logical operands
  11 immediates8 \
  12      = [0x1, 0x0c, 0x3e, 0x60, 0x7c, 0x80, 0x83,
  13         0xe1, 0xbf, 0xef, 0xf3, 0xfe]
  14 
  15 immediates16 \
  16      = [0x1, 0x38, 0x7e, 0xff, 0x1fc, 0x1ff, 0x3f0,
  17         0x7e0, 0xfc0, 0x1f80, 0x3ff0, 0x7e00, 0x7e00,
  18         0x8000, 0x81ff, 0xc1ff, 0xc003, 0xc7ff, 0xdfff,
  19         0xe03f, 0xe10f, 0xe1ff, 0xf801, 0xfc00, 0xfc07,
  20         0xff03, 0xfffe]
  21 
  22 immediates32 \
  23      = [0x1, 0x3f, 0x1f0, 0x7e0,
  24         0x1c00, 0x3ff0, 0x8000, 0x1e000,
  25         0x3e000, 0x78000, 0xe0000, 0x100000,
  26         0x1fffe0, 0x3fe000, 0x780000, 0x7ffff8,
  27         0xff8000, 0x1800180, 0x1fffc00, 0x3c003c0,
  28         0x3ffff00, 0x7c00000, 0x7fffe00, 0xf000f00,
  29         0xfffe000, 0x18181818, 0x1ffc0000, 0x1ffffffe,
  30         0x3f003f00, 0x3fffe000, 0x60006000, 0x7f807f80,
  31         0x7ffffc00, 0x800001ff, 0x803fffff, 0x9f9f9f9f,
  32         0xc0000fff, 0xc0c0c0c0, 0xe0000000, 0xe003e003,
  33         0xe3ffffff, 0xf0000fff, 0xf0f0f0f0, 0xf80000ff,
  34         0xf83ff83f, 0xfc00007f, 0xfc1fffff, 0xfe0001ff,
  35         0xfe3fffff, 0xff003fff, 0xff800003, 0xff87ff87,
  36         0xffc00fff, 0xffe0000f, 0xffefffef, 0xfff1fff1,
  37         0xfff83fff, 0xfffc0fff, 0xfffe0fff, 0xffff3fff,
  38         0xffffc007, 0xffffe1ff, 0xfffff80f, 0xfffffe07,
  39         0xffffffbf, 0xfffffffd]
  40 
  41 immediates64 \
  42      = [0x1, 0x1f80, 0x3fff0, 0x3ffffc,
  43         0x3fe0000, 0x1ffc0000, 0xf8000000, 0x3ffffc000,
  44         0xffffffe00, 0x3ffffff800, 0xffffc00000, 0x3f000000000,
  45         0x7fffffff800, 0x1fe000001fe0, 0x3ffffff80000, 0xc00000000000,
  46         0x1ffc000000000, 0x3ffff0003ffff, 0x7ffffffe00000, 0xfffffffffc000,
  47         0x1ffffffffffc00, 0x3fffffffffff00, 0x7ffffffffffc00, 0xffffffffff8000,
  48         0x1ffffffff800000, 0x3fffffc03fffffc, 0x7fffc0000000000, 0xff80ff80ff80ff8,
  49         0x1c00000000000000, 0x1fffffffffff0000, 0x3fffff803fffff80, 0x7fc000007fc00000,
  50         0x8000000000000000, 0x803fffff803fffff, 0xc000007fc000007f, 0xe00000000000ffff,
  51         0xe3ffffffffffffff, 0xf007f007f007f007, 0xf80003ffffffffff, 0xfc000003fc000003,
  52         0xfe000000007fffff, 0xff00000000007fff, 0xff800000000003ff, 0xffc00000000000ff,
  53         0xffe00000000003ff, 0xfff0000000003fff, 0xfff80000001fffff, 0xfffc0000fffc0000,
  54         0xfffe003fffffffff, 0xffff3fffffffffff, 0xffffc0000007ffff, 0xffffe01fffffe01f,
  55         0xfffff800000007ff, 0xfffffc0fffffffff, 0xffffff00003fffff, 0xffffffc0000007ff,
  56         0xfffffff0000001ff, 0xfffffffc00003fff, 0xffffffff07ffffff, 0xffffffffe003ffff,
  57         0xfffffffffc01ffff, 0xffffffffffc00003, 0xfffffffffffc000f, 0xffffffffffffe07f]
  58 
  59 class Operand(object):
  60 
  61      def generate(self):
  62         return self
  63 
  64 class Register(Operand):
  65 
  66     def generate(self):
  67         self.number = random.randint(0, 30)
  68         if self.number == 18:
  69             self.number = 17
  70         return self
  71 
  72     def astr(self, prefix):
  73         return prefix + str(self.number)
  74 
  75 class FloatRegister(Register):
  76 
  77     def __str__(self):
  78         return self.astr("v")
  79 
  80     def nextReg(self):
  81         next = FloatRegister()
  82         next.number = (self.number + 1) % 32
  83         return next
  84 
  85 class GeneralRegister(Register):
  86 
  87     def __str__(self):
  88         return self.astr("r")
  89 
  90 class GeneralRegisterOrZr(Register):
  91 
  92     def generate(self):
  93         self.number = random.randint(0, 31)
  94         if self.number == 18:
  95             self.number = 16
  96         return self
  97 
  98     def astr(self, prefix = ""):
  99         if (self.number == 31):
 100             return prefix + "zr"
 101         else:
 102             return prefix + str(self.number)
 103 
 104     def __str__(self):
 105         if (self.number == 31):
 106             return self.astr()
 107         else:
 108             return self.astr("r")
 109 
 110 class GeneralRegisterOrSp(Register):
 111     def generate(self):
 112         self.number = random.randint(0, 31)
 113         if self.number == 18:
 114             self.number = 15
 115         return self
 116 
 117     def astr(self, prefix = ""):
 118         if (self.number == 31):
 119             return "sp"
 120         else:
 121             return prefix + str(self.number)
 122 
 123     def __str__(self):
 124         if (self.number == 31):
 125             return self.astr()
 126         else:
 127             return self.astr("r")
 128 
 129 class SVEVectorRegister(FloatRegister):
 130     def __str__(self):
 131         return self.astr("z")
 132 
 133 class SVEPRegister(Register):
 134     def __str__(self):
 135         return self.astr("p")
 136 
 137     def generate(self):
 138         self.number = random.randint(0, 15)
 139         return self
 140 
 141 class SVEGoverningPRegister(Register):
 142     def __str__(self):
 143         return self.astr("p")
 144     def generate(self):
 145         self.number = random.randint(0, 7)
 146         return self
 147 
 148 class RegVariant(object):
 149     def __init__(self, low, high):
 150         self.number = random.randint(low, high)
 151 
 152     def astr(self):
 153         nameMap = {
 154              0: ".b",
 155              1: ".h",
 156              2: ".s",
 157              3: ".d",
 158              4: ".q"
 159         }
 160         return nameMap.get(self.number)
 161 
 162     def cstr(self):
 163         nameMap = {
 164              0: "__ B",
 165              1: "__ H",
 166              2: "__ S",
 167              3: "__ D",
 168              4: "__ Q"
 169         }
 170         return nameMap.get(self.number)
 171 
 172 class FloatZero(Operand):
 173 
 174     def __str__(self):
 175         return "0.0"
 176 
 177     def astr(self, ignored):
 178         return "#0.0"
 179 
 180 class OperandFactory:
 181 
 182     _modes = {'x' : GeneralRegister,
 183               'w' : GeneralRegister,
 184               'b' : FloatRegister,
 185               'h' : FloatRegister,
 186               's' : FloatRegister,
 187               'd' : FloatRegister,
 188               'z' : FloatZero,
 189               'p' : SVEPRegister,
 190               'P' : SVEGoverningPRegister,
 191               'Z' : SVEVectorRegister}
 192 
 193     @classmethod
 194     def create(cls, mode):
 195         return OperandFactory._modes[mode]()
 196 
 197 class ShiftKind:
 198 
 199     def generate(self):
 200         self.kind = ["LSL", "LSR", "ASR"][random.randint(0,2)]
 201         return self
 202 
 203     def cstr(self):
 204         return self.kind
 205 
 206 class Instruction(object):
 207 
 208     def __init__(self, name):
 209         self._name = name
 210         self.isWord = name.endswith("w") | name.endswith("wi")
 211         self.asmRegPrefix = ["x", "w"][self.isWord]
 212 
 213     def aname(self):
 214         if (self._name.endswith("wi")):
 215             return self._name[:len(self._name)-2]
 216         else:
 217             if (self._name.endswith("i") | self._name.endswith("w")):
 218                 return self._name[:len(self._name)-1]
 219             else:
 220                 return self._name
 221 
 222     def emit(self) :
 223         pass
 224 
 225     def compare(self) :
 226         pass
 227 
 228     def generate(self) :
 229         return self
 230 
 231     def cstr(self):
 232         return '__ %s(' % self.name()
 233 
 234     def astr(self):
 235         return '%s\t' % self.aname()
 236 
 237     def name(self):
 238         name = self._name
 239         if name == "and":
 240             name = "andr" # Special case: the name "and" can't be used
 241                           # in HotSpot, even for a member.
 242         return name
 243 
 244     def multipleForms(self):
 245          return 0
 246 
 247 class InstructionWithModes(Instruction):
 248 
 249     def __init__(self, name, mode):
 250         Instruction.__init__(self, name)
 251         self.mode = mode
 252         self.isFloat = (mode == 'd') | (mode == 's')
 253         if self.isFloat:
 254             self.isWord = mode != 'd'
 255             self.asmRegPrefix = ["d", "s"][self.isWord]
 256         else:
 257             self.isWord = mode != 'x'
 258             self.asmRegPrefix = ["x", "w"][self.isWord]
 259 
 260     def name(self):
 261         return self._name + (self.mode if self.mode != 'x' else '')
 262 
 263     def aname(self):
 264         return (self._name+mode if (mode == 'b' or mode == 'h')
 265             else self._name)
 266 
 267 class ThreeRegInstruction(Instruction):
 268 
 269     def generate(self):
 270         self.reg = [GeneralRegister().generate(), GeneralRegister().generate(),
 271                     GeneralRegister().generate()]
 272         return self
 273 
 274 
 275     def cstr(self):
 276         return (super(ThreeRegInstruction, self).cstr()
 277                 + ('%s, %s, %s'
 278                    % (self.reg[0],
 279                       self.reg[1], self.reg[2])))
 280 
 281     def astr(self):
 282         prefix = self.asmRegPrefix
 283         return (super(ThreeRegInstruction, self).astr()
 284                 + ('%s, %s, %s'
 285                    % (self.reg[0].astr(prefix),
 286                       self.reg[1].astr(prefix), self.reg[2].astr(prefix))))
 287 
 288 class FourRegInstruction(ThreeRegInstruction):
 289 
 290     def generate(self):
 291         self.reg = ThreeRegInstruction.generate(self).reg + [GeneralRegister().generate()]
 292         return self
 293 
 294 
 295     def cstr(self):
 296         return (super(FourRegInstruction, self).cstr()
 297                 + (', %s' % self.reg[3]))
 298 
 299     def astr(self):
 300         prefix = self.asmRegPrefix
 301         return (super(FourRegInstruction, self).astr()
 302                 + (', %s' % self.reg[3].astr(prefix)))
 303 
 304 class TwoRegInstruction(Instruction):
 305 
 306     def generate(self):
 307         self.reg = [GeneralRegister().generate(), GeneralRegister().generate()]
 308         return self
 309 
 310     def cstr(self):
 311         return (super(TwoRegInstruction, self).cstr()
 312                 + '%s, %s' % (self.reg[0],
 313                               self.reg[1]))
 314 
 315     def astr(self):
 316         prefix = self.asmRegPrefix
 317         return (super(TwoRegInstruction, self).astr()
 318                 + ('%s, %s'
 319                    % (self.reg[0].astr(prefix),
 320                       self.reg[1].astr(prefix))))
 321 
 322 class TwoRegImmedInstruction(TwoRegInstruction):
 323 
 324     def generate(self):
 325         super(TwoRegImmedInstruction, self).generate()
 326         self.immed = random.randint(0, 1<<11 -1)
 327         return self
 328 
 329     def cstr(self):
 330         return (super(TwoRegImmedInstruction, self).cstr()
 331                 + ', %su' % self.immed)
 332 
 333     def astr(self):
 334         return (super(TwoRegImmedInstruction, self).astr()
 335                 + ', #%s' % self.immed)
 336 
 337 class OneRegOp(Instruction):
 338 
 339     def generate(self):
 340         self.reg = GeneralRegister().generate()
 341         return self
 342 
 343     def cstr(self):
 344         return (super(OneRegOp, self).cstr()
 345                 + '%s);' % self.reg)
 346 
 347     def astr(self):
 348         return (super(OneRegOp, self).astr()
 349                 + '%s' % self.reg.astr(self.asmRegPrefix))
 350 
 351 class ArithOp(ThreeRegInstruction):
 352 
 353     def generate(self):
 354         super(ArithOp, self).generate()
 355         self.kind = ShiftKind().generate()
 356         self.distance = random.randint(0, (1<<5)-1 if self.isWord else (1<<6)-1)
 357         return self
 358 
 359     def cstr(self):
 360         return ('%s, Assembler::%s, %s);'
 361                 % (ThreeRegInstruction.cstr(self),
 362                    self.kind.cstr(), self.distance))
 363 
 364     def astr(self):
 365         return ('%s, %s #%s'
 366                 % (ThreeRegInstruction.astr(self),
 367                    self.kind.cstr(),
 368                    self.distance))
 369 
 370 class AddSubCarryOp(ThreeRegInstruction):
 371 
 372     def cstr(self):
 373         return ('%s);'
 374                 % (ThreeRegInstruction.cstr(self)))
 375 
 376 class AddSubExtendedOp(ThreeRegInstruction):
 377 
 378     uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx = range(8)
 379     optNames = ["uxtb", "uxth", "uxtw", "uxtx", "sxtb", "sxth", "sxtw", "sxtx"]
 380 
 381     def generate(self):
 382         super(AddSubExtendedOp, self).generate()
 383         self.amount = random.randint(1, 4)
 384         self.option = random.randint(0, 7)
 385         return self
 386 
 387     def cstr(self):
 388         return (super(AddSubExtendedOp, self).cstr()
 389                 + (", ext::" + AddSubExtendedOp.optNames[self.option]
 390                    + ", " + str(self.amount) + ");"))
 391 
 392     def astr(self):
 393         return (super(AddSubExtendedOp, self).astr()
 394                 + (", " + AddSubExtendedOp.optNames[self.option]
 395                    + " #" + str(self.amount)))
 396 
 397 class AddSubImmOp(TwoRegImmedInstruction):
 398 
 399     def cstr(self):
 400          return super(AddSubImmOp, self).cstr() + ");"
 401 
 402 class LogicalImmOp(AddSubImmOp):
 403      def generate(self):
 404           AddSubImmOp.generate(self)
 405           self.immed = \
 406               immediates32[random.randint(0, len(immediates32)-1)] \
 407               if self.isWord else \
 408               immediates64[random.randint(0, len(immediates64)-1)]
 409 
 410           return self
 411 
 412      def astr(self):
 413           return (super(TwoRegImmedInstruction, self).astr()
 414                   + ', #0x%x' % self.immed)
 415 
 416      def cstr(self):
 417           return super(AddSubImmOp, self).cstr() + "ll);"
 418 
 419 class SVEBinaryImmOp(Instruction):
 420     def __init__(self, name):
 421         reg = SVEVectorRegister().generate()
 422         self.reg = [reg, reg]
 423         self.numRegs = len(self.reg)
 424         self._width = RegVariant(0, 3)
 425         self._isLogical = False
 426         if name in ["and", "eor", "orr"]:
 427             self._isLogical = True
 428         Instruction.__init__(self, name)
 429 
 430     def generate(self):
 431         Instruction.generate(self)
 432         self.immed = random.randint(0, (1<<8)-1)
 433         if self._isLogical:
 434             vectype = self._width.cstr()
 435             if vectype == "__ B":
 436                 self.immed = immediates8[random.randint(0, len(immediates8)-1)]
 437             elif vectype == "__ H":
 438                 self.immed = immediates16[random.randint(0, len(immediates16)-1)]
 439             elif vectype == "__ S":
 440                 self.immed = immediates32[random.randint(0, len(immediates32)-1)]
 441             elif vectype == "__ D":
 442                 self.immed = immediates64[random.randint(0, len(immediates64)-1)]
 443         return self
 444 
 445     def cstr(self):
 446         formatStr = "%s%s, %s, %su);"
 447         return (formatStr
 448                 % tuple(["__ sve_" + self._name + "("] +
 449                         [str(self.reg[0]), self._width.cstr(), self.immed]))
 450 
 451     def astr(self):
 452         formatStr = "%s%s, %s, #0x%x"
 453         Regs = [str(self.reg[i]) + self._width.astr() for i in range(0, self.numRegs)]
 454         return (formatStr
 455                 % tuple([Instruction.astr(self)] + Regs + [self.immed]))
 456 
 457 class MultiOp():
 458 
 459     def multipleForms(self):
 460          return 3
 461 
 462     def forms(self):
 463          return ["__ pc()", "back", "forth"]
 464 
 465     def aforms(self):
 466          return [".", "back", "forth"]
 467 
 468 class AbsOp(MultiOp, Instruction):
 469 
 470     def cstr(self):
 471         return super(AbsOp, self).cstr() + "%s);"
 472 
 473     def astr(self):
 474         return Instruction.astr(self) + "%s"
 475 
 476 class RegAndAbsOp(MultiOp, Instruction):
 477 
 478     def multipleForms(self):
 479         if self.name() == "adrp":
 480             # We can only test one form of adrp because anything other
 481             # than "adrp ." requires relocs in the assembler output
 482             return 1
 483         return 3
 484 
 485     def generate(self):
 486         Instruction.generate(self)
 487         self.reg = GeneralRegister().generate()
 488         return self
 489 
 490     def cstr(self):
 491         if self.name() == "adrp":
 492             return "__ _adrp(" + "%s, %s);" % (self.reg, "%s")
 493         return (super(RegAndAbsOp, self).cstr()
 494                 + "%s, %s);" % (self.reg, "%s"))
 495 
 496     def astr(self):
 497         return (super(RegAndAbsOp, self).astr()
 498                 + self.reg.astr(self.asmRegPrefix) + ", %s")
 499 
 500 class RegImmAbsOp(RegAndAbsOp):
 501 
 502     def cstr(self):
 503         return (Instruction.cstr(self)
 504                 + "%s, %s, %s);" % (self.reg, self.immed, "%s"))
 505 
 506     def astr(self):
 507         return (Instruction.astr(self)
 508                 + ("%s, #%s, %s"
 509                    % (self.reg.astr(self.asmRegPrefix), self.immed, "%s")))
 510 
 511     def generate(self):
 512         super(RegImmAbsOp, self).generate()
 513         self.immed = random.randint(0, 1<<5 -1)
 514         return self
 515 
 516 class MoveWideImmOp(RegImmAbsOp):
 517 
 518     def multipleForms(self):
 519          return 0
 520 
 521     def cstr(self):
 522         return (Instruction.cstr(self)
 523                 + "%s, %s, %s);" % (self.reg, self.immed, self.shift))
 524 
 525     def astr(self):
 526         return (Instruction.astr(self)
 527                 + ("%s, #%s, lsl %s"
 528                    % (self.reg.astr(self.asmRegPrefix),
 529                       self.immed, self.shift)))
 530 
 531     def generate(self):
 532         super(RegImmAbsOp, self).generate()
 533         self.immed = random.randint(0, 1<<16 -1)
 534         if self.isWord:
 535             self.shift = random.randint(0, 1) * 16
 536         else:
 537             self.shift = random.randint(0, 3) * 16
 538         return self
 539 
 540 class BitfieldOp(TwoRegInstruction):
 541 
 542     def cstr(self):
 543         return (Instruction.cstr(self)
 544                 + ("%s, %s, %s, %s);"
 545                    % (self.reg[0], self.reg[1], self.immr, self.imms)))
 546 
 547     def astr(self):
 548         return (TwoRegInstruction.astr(self)
 549                 + (", #%s, #%s"
 550                    % (self.immr, self.imms)))
 551 
 552     def generate(self):
 553         TwoRegInstruction.generate(self)
 554         self.immr = random.randint(0, 31)
 555         self.imms = random.randint(0, 31)
 556         return self
 557 
 558 class ExtractOp(ThreeRegInstruction):
 559 
 560     def generate(self):
 561         super(ExtractOp, self).generate()
 562         self.lsb = random.randint(0, (1<<5)-1 if self.isWord else (1<<6)-1)
 563         return self
 564 
 565     def cstr(self):
 566         return (ThreeRegInstruction.cstr(self)
 567                 + (", %s);" % self.lsb))
 568 
 569     def astr(self):
 570         return (ThreeRegInstruction.astr(self)
 571                 + (", #%s" % self.lsb))
 572 
 573 class CondBranchOp(MultiOp, Instruction):
 574 
 575     def cstr(self):
 576         return "__ br(Assembler::" + self.name() + ", %s);"
 577 
 578     def astr(self):
 579         return "b." + self.name() + "\t%s"
 580 
 581 class ImmOp(Instruction):
 582 
 583     def cstr(self):
 584         return "%s%s);" % (Instruction.cstr(self), self.immed)
 585 
 586     def astr(self):
 587         return Instruction.astr(self) + "#" + str(self.immed)
 588 
 589     def generate(self):
 590         self.immed = random.randint(0, 1<<16 -1)
 591         return self
 592 
 593 class Op(Instruction):
 594 
 595     def cstr(self):
 596         return Instruction.cstr(self) + ");"
 597     def astr(self):
 598         return self.aname();
 599 
 600 class SystemOp(Instruction):
 601 
 602      def __init__(self, op):
 603           Instruction.__init__(self, op[0])
 604           self.barriers = op[1]
 605 
 606      def generate(self):
 607           Instruction.generate(self)
 608           self.barrier \
 609               = self.barriers[random.randint(0, len(self.barriers)-1)]
 610           return self
 611 
 612      def cstr(self):
 613           return Instruction.cstr(self) + "Assembler::" + self.barrier + ");"
 614 
 615      def astr(self):
 616           return Instruction.astr(self) + self.barrier
 617 
 618 conditionCodes = ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", \
 619                        "VC", "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV"]
 620 
 621 class ConditionalCompareOp(TwoRegImmedInstruction):
 622 
 623     def generate(self):
 624         TwoRegImmedInstruction.generate(self)
 625         self.cond = random.randint(0, 15)
 626         self.immed = random.randint(0, 15)
 627         return self
 628 
 629     def cstr(self):
 630         return (super(ConditionalCompareOp, self).cstr() + ", "
 631                 + "Assembler::" + conditionCodes[self.cond] + ");")
 632 
 633     def astr(self):
 634         return (super(ConditionalCompareOp, self).astr() +
 635                  ", " + conditionCodes[self.cond])
 636 
 637 class ConditionalCompareImmedOp(Instruction):
 638 
 639     def generate(self):
 640         self.reg = GeneralRegister().generate()
 641         self.cond = random.randint(0, 15)
 642         self.immed2 = random.randint(0, 15)
 643         self.immed = random.randint(0, 31)
 644         return self
 645 
 646     def cstr(self):
 647         return (Instruction.cstr(self) + str(self.reg) + ", "
 648                 + str(self.immed) + ", "
 649                 + str(self.immed2) + ", "
 650                 + "Assembler::" + conditionCodes[self.cond] + ");")
 651 
 652     def astr(self):
 653         return (Instruction.astr(self)
 654                 + self.reg.astr(self.asmRegPrefix)
 655                 + ", #" + str(self.immed)
 656                 + ", #" + str(self.immed2)
 657                 + ", " + conditionCodes[self.cond])
 658 
 659 class TwoRegOp(TwoRegInstruction):
 660 
 661     def cstr(self):
 662         return TwoRegInstruction.cstr(self) + ");"
 663 
 664 class ThreeRegOp(ThreeRegInstruction):
 665 
 666     def cstr(self):
 667         return ThreeRegInstruction.cstr(self) + ");"
 668 
 669 class FourRegMulOp(FourRegInstruction):
 670 
 671     def cstr(self):
 672         return FourRegInstruction.cstr(self) + ");"
 673 
 674     def astr(self):
 675         isMaddsub = self.name().startswith("madd") | self.name().startswith("msub")
 676         midPrefix = self.asmRegPrefix if isMaddsub else "w"
 677         return (Instruction.astr(self)
 678                 + self.reg[0].astr(self.asmRegPrefix)
 679                 + ", " + self.reg[1].astr(midPrefix)
 680                 + ", " + self.reg[2].astr(midPrefix)
 681                 + ", " + self.reg[3].astr(self.asmRegPrefix))
 682 
 683 class ConditionalSelectOp(ThreeRegInstruction):
 684 
 685     def generate(self):
 686         ThreeRegInstruction.generate(self)
 687         self.cond = random.randint(0, 15)
 688         return self
 689 
 690     def cstr(self):
 691         return (ThreeRegInstruction.cstr(self) + ", "
 692                 + "Assembler::" + conditionCodes[self.cond] + ");")
 693 
 694     def astr(self):
 695         return (ThreeRegInstruction.astr(self)
 696                 + ", " + conditionCodes[self.cond])
 697 
 698 class LoadStoreExclusiveOp(InstructionWithModes):
 699 
 700     def __init__(self, op): # op is a tuple of ["name", "mode", registers]
 701         InstructionWithModes.__init__(self, op[0], op[1])
 702         self.num_registers = op[2]
 703 
 704     def astr(self):
 705         result = self.aname() + '\t'
 706         regs = list(self.regs)
 707         index = regs.pop() # The last reg is the index register
 708         prefix = ('x' if (self.mode == 'x')
 709                   & ((self.name().startswith("ld"))
 710                      | (self.name().startswith("stlr"))) # Ewww :-(
 711                   else 'w')
 712         result = result + regs.pop(0).astr(prefix) + ", "
 713         for s in regs:
 714             result = result + s.astr(self.asmRegPrefix) + ", "
 715         result = result + "[" + index.astr("x") + "]"
 716         return result
 717 
 718     def cstr(self):
 719         result = InstructionWithModes.cstr(self)
 720         regs = list(self.regs)
 721         index = regs.pop() # The last reg is the index register
 722         for s in regs:
 723             result = result + str(s) + ", "
 724         result = result + str(index) + ");"
 725         return result
 726 
 727     def appendUniqueReg(self):
 728         result = 0
 729         while result == 0:
 730             newReg = GeneralRegister().generate()
 731             result = 1
 732             for i in self.regs:
 733                 result = result and (i.number != newReg.number)
 734         self.regs.append(newReg)
 735 
 736     def generate(self):
 737         self.regs = []
 738         for i in range(self.num_registers):
 739             self.appendUniqueReg()
 740         return self
 741 
 742     def name(self):
 743         if self.mode == 'x':
 744             return self._name
 745         else:
 746             return self._name + self.mode
 747 
 748     def aname(self):
 749         if (self.mode == 'b') | (self.mode == 'h'):
 750             return self._name + self.mode
 751         else:
 752             return self._name
 753 
 754 class Address(object):
 755 
 756     base_plus_unscaled_offset, pre, post, base_plus_reg, \
 757         base_plus_scaled_offset, pcrel, post_reg, base_only = range(8)
 758     kinds = ["base_plus_unscaled_offset", "pre", "post", "base_plus_reg",
 759              "base_plus_scaled_offset", "pcrel", "post_reg", "base_only"]
 760     extend_kinds = ["uxtw", "lsl", "sxtw", "sxtx"]
 761 
 762     @classmethod
 763     def kindToStr(cls, i):
 764          return cls.kinds[i]
 765 
 766     def generate(self, kind, shift_distance):
 767         self.kind = kind
 768         self.base = GeneralRegister().generate()
 769         self.index = GeneralRegister().generate()
 770         self.offset = {
 771             Address.base_plus_unscaled_offset: random.randint(-1<<8, 1<<8-1) | 1,
 772             Address.pre: random.randint(-1<<8, 1<<8-1),
 773             Address.post: random.randint(-1<<8, 1<<8-1),
 774             Address.pcrel: random.randint(0, 2),
 775             Address.base_plus_reg: 0,
 776             Address.base_plus_scaled_offset: (random.randint(0, 1<<11-1) | (3 << 9))*8,
 777             Address.post_reg: 0,
 778             Address.base_only: 0} [kind]
 779         self.offset >>= (3 - shift_distance)
 780         self.extend_kind = Address.extend_kinds[random.randint(0, 3)]
 781         self.shift_distance = random.randint(0, 1) * shift_distance
 782         return self
 783 
 784     def __str__(self):
 785         result = {
 786             Address.base_plus_unscaled_offset: "Address(%s, %s)" \
 787                 % (str(self.base), self.offset),
 788             Address.pre: "Address(__ pre(%s, %s))" % (str(self.base), self.offset),
 789             Address.post: "Address(__ post(%s, %s))" % (str(self.base), self.offset),
 790             Address.post_reg: "Address(__ post(%s, %s))" % (str(self.base), self.index),
 791             Address.base_only: "Address(%s)" % (str(self.base)),
 792             Address.pcrel: "",
 793             Address.base_plus_reg: "Address(%s, %s, Address::%s(%s))" \
 794                 % (self.base, self.index, self.extend_kind, self.shift_distance),
 795             Address.base_plus_scaled_offset:
 796             "Address(%s, %s)" % (self.base, self.offset) } [self.kind]
 797         if (self.kind == Address.pcrel):
 798             result = ["__ pc()", "back", "forth"][self.offset]
 799         return result
 800 
 801     def astr(self, prefix):
 802         extend_prefix = prefix
 803         if self.kind == Address.base_plus_reg:
 804             if self.extend_kind.endswith("w"):
 805                 extend_prefix = "w"
 806         result = {
 807             Address.base_plus_unscaled_offset: "[%s, %s]" \
 808                  % (self.base.astr(prefix), self.offset),
 809             Address.pre: "[%s, %s]!" % (self.base.astr(prefix), self.offset),
 810             Address.post: "[%s], %s" % (self.base.astr(prefix), self.offset),
 811             Address.post_reg: "[%s], %s" % (self.base.astr(prefix), self.index.astr(prefix)),
 812             Address.base_only: "[%s]" %  (self.base.astr(prefix)),
 813             Address.pcrel: "",
 814             Address.base_plus_reg: "[%s, %s, %s #%s]" \
 815                 % (self.base.astr(prefix), self.index.astr(extend_prefix),
 816                    self.extend_kind, self.shift_distance),
 817             Address.base_plus_scaled_offset: \
 818                 "[%s, %s]" \
 819                 % (self.base.astr(prefix), self.offset)
 820             } [self.kind]
 821         if (self.kind == Address.pcrel):
 822             result = [".", "back", "forth"][self.offset]
 823         return result
 824 
 825 class LoadStoreOp(InstructionWithModes):
 826 
 827     def __init__(self, args):
 828         name, self.asmname, self.kind, mode = args
 829         InstructionWithModes.__init__(self, name, mode)
 830 
 831     def generate(self):
 832 
 833         # This is something of a kludge, but the offset needs to be
 834         # scaled by the memory datamode somehow.
 835         shift = 3
 836         if (self.mode == 'b') | (self.asmname.endswith("b")):
 837             shift = 0
 838         elif (self.mode == 'h') | (self.asmname.endswith("h")):
 839             shift = 1
 840         elif (self.mode == 'w') | (self.asmname.endswith("w")) \
 841                 | (self.mode == 's') :
 842             shift = 2
 843 
 844         self.adr = Address().generate(self.kind, shift)
 845 
 846         isFloat = (self.mode == 'd') | (self.mode == 's')
 847 
 848         regMode = FloatRegister if isFloat else GeneralRegister
 849         self.reg = regMode().generate()
 850         kindStr = Address.kindToStr(self.kind);
 851         if (not isFloat) and (kindStr is "pre" or kindStr is "post"):
 852             (self.reg.number, self.adr.base.number) = random.sample(list(set(range(31)) - set([18])), 2)
 853         return self
 854 
 855     def cstr(self):
 856         if not(self._name.startswith("prfm")):
 857             return "%s%s, %s);" % (Instruction.cstr(self), str(self.reg), str(self.adr))
 858         else: # No target register for a prefetch
 859             return "%s%s);" % (Instruction.cstr(self), str(self.adr))
 860 
 861     def astr(self):
 862         if not(self._name.startswith("prfm")):
 863             return "%s\t%s, %s" % (self.aname(), self.reg.astr(self.asmRegPrefix),
 864                                      self.adr.astr("x"))
 865         else: # No target register for a prefetch
 866             return "%s %s" % (self.aname(),
 867                                      self.adr.astr("x"))
 868 
 869     def aname(self):
 870          result = self.asmname
 871          # if self.kind == Address.base_plus_unscaled_offset:
 872          #      result = result.replace("ld", "ldu", 1)
 873          #      result = result.replace("st", "stu", 1)
 874          return result
 875 
 876 class LoadStorePairOp(InstructionWithModes):
 877 
 878      numRegs = 2
 879 
 880      def __init__(self, args):
 881           name, self.asmname, self.kind, mode = args
 882           InstructionWithModes.__init__(self, name, mode)
 883           self.offset = random.randint(-1<<4, 1<<4-1) << 4
 884 
 885      def generate(self):
 886           self.reg = [OperandFactory.create(self.mode).generate()
 887                       for i in range(self.numRegs)]
 888           self.base = OperandFactory.create('x').generate()
 889           kindStr = Address.kindToStr(self.kind);
 890           if kindStr is "pre" or kindStr is "post":
 891               if self._name.startswith("ld"):
 892                   (self.reg[0].number, self.reg[1].number, self.base.number) = random.sample(list(set(range(31)) - set([18])), 3)
 893               if self._name.startswith("st"):
 894                   self.base.number = random.choice(list(set(range(31)) - set([self.reg[0].number, self.reg[1].number, 18])))
 895           elif self._name.startswith("ld"):
 896               (self.reg[0].number, self.reg[1].number) = random.sample(list(set(range(31)) - set([18])), 2)
 897           return self
 898 
 899      def astr(self):
 900           address = ["[%s, #%s]", "[%s, #%s]!", "[%s], #%s"][self.kind]
 901           address = address % (self.base.astr('x'), self.offset)
 902           result = "%s\t%s, %s, %s" \
 903               % (self.asmname,
 904                  self.reg[0].astr(self.asmRegPrefix),
 905                  self.reg[1].astr(self.asmRegPrefix), address)
 906           return result
 907 
 908      def cstr(self):
 909           address = {
 910                Address.base_plus_unscaled_offset: "Address(%s, %s)" \
 911                     % (str(self.base), self.offset),
 912                Address.pre: "Address(__ pre(%s, %s))" % (str(self.base), self.offset),
 913                Address.post: "Address(__ post(%s, %s))" % (str(self.base), self.offset),
 914                } [self.kind]
 915           result = "__ %s(%s, %s, %s);" \
 916               % (self.name(), self.reg[0], self.reg[1], address)
 917           return result
 918 
 919 class FloatInstruction(Instruction):
 920 
 921     def aname(self):
 922         if (self._name.endswith("s") | self._name.endswith("d")):
 923             return self._name[:len(self._name)-1]
 924         else:
 925             return self._name
 926 
 927     def __init__(self, args):
 928         name, self.modes = args
 929         Instruction.__init__(self, name)
 930 
 931     def generate(self):
 932         self.reg = [OperandFactory.create(self.modes[i]).generate()
 933                     for i in range(self.numRegs)]
 934         return self
 935 
 936     def cstr(self):
 937         formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"])
 938         return (formatStr
 939                 % tuple([Instruction.cstr(self)] +
 940                         [str(self.reg[i]) for i in range(self.numRegs)])) # Yowza
 941 
 942     def astr(self):
 943         formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)])
 944         return (formatStr
 945                 % tuple([Instruction.astr(self)] +
 946                         [(self.reg[i].astr(self.modes[i])) for i in range(self.numRegs)]))
 947 
 948 class SVEVectorOp(Instruction):
 949     def __init__(self, args):
 950         name = args[0]
 951         regTypes = args[1]
 952         regs = []
 953         for c in regTypes:
 954             regs.append(OperandFactory.create(c).generate())
 955         self.reg = regs
 956         self.numRegs = len(regs)
 957         if regTypes[0] != "p" and regTypes[1] == 'P':
 958            self._isPredicated = True
 959            assert len(args) > 2, "Must specify predicate type"
 960            for arg in args[2:]:
 961               if arg == 'm':
 962                  self._merge = "/m"
 963               elif arg == 'z':
 964                  self._merge = "/z"
 965               else:
 966                  assert arg == "dn", "Unknown predicate type"
 967         else:
 968            self._isPredicated = False
 969            self._merge = ""
 970 
 971         self._bitwiseop = False
 972         if name[0] == 'f':
 973             self._width = RegVariant(2, 3)
 974         elif not self._isPredicated and (name in ["and", "eor", "orr", "bic"]):
 975             self._width = RegVariant(3, 3)
 976             self._bitwiseop = True
 977         else:
 978             self._width = RegVariant(0, 3)
 979 
 980         self._dnm = None
 981         if len(args) > 2:
 982            for arg in args[2:]:
 983              if arg == "dn":
 984                self._dnm = arg
 985 
 986         Instruction.__init__(self, name)
 987 
 988     def cstr(self):
 989         formatStr = "%s%s" + ''.join([", %s" for i in range(0, self.numRegs)] + [");"])
 990         if self._bitwiseop:
 991             width = []
 992             formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)] + [");"])
 993         else:
 994             width = [self._width.cstr()]
 995         return (formatStr
 996                 % tuple(["__ sve_" + self._name + "("] +
 997                         [str(self.reg[0])] +
 998                         width +
 999                         [str(self.reg[i]) for i in range(1, self.numRegs)]))
1000     def astr(self):
1001         formatStr = "%s%s" + ''.join([", %s" for i in range(1, self.numRegs)])
1002         if self._dnm == 'dn':
1003             formatStr += ", %s"
1004             dnReg = [str(self.reg[0]) + self._width.astr()]
1005         else:
1006             dnReg = []
1007 
1008         if self._isPredicated:
1009             restRegs = [str(self.reg[1]) + self._merge] + dnReg + [str(self.reg[i]) + self._width.astr() for i in range(2, self.numRegs)]
1010         else:
1011             restRegs = dnReg + [str(self.reg[i]) + self._width.astr() for i in range(1, self.numRegs)]
1012         return (formatStr
1013                 % tuple([Instruction.astr(self)] +
1014                         [str(self.reg[0]) + self._width.astr()] +
1015                         restRegs))
1016     def generate(self):
1017         return self
1018 
1019 class SVEReductionOp(Instruction):
1020     def __init__(self, args):
1021         name = args[0]
1022         lowRegType = args[1]
1023         self.reg = []
1024         Instruction.__init__(self, name)
1025         self.reg.append(OperandFactory.create('s').generate())
1026         self.reg.append(OperandFactory.create('P').generate())
1027         self.reg.append(OperandFactory.create('Z').generate())
1028         self._width = RegVariant(lowRegType, 3)
1029     def cstr(self):
1030         return "__ sve_%s(%s, %s, %s, %s);" % (self.name(),
1031                                               str(self.reg[0]),
1032                                               self._width.cstr(),
1033                                               str(self.reg[1]),
1034                                               str(self.reg[2]))
1035     def astr(self):
1036         if self.name() == "uaddv":
1037             dstRegName = "d" + str(self.reg[0].number)
1038         else:
1039             dstRegName = self._width.astr()[1] + str(self.reg[0].number)
1040         formatStr = "%s %s, %s, %s"
1041         if self.name() == "fadda":
1042             formatStr += ", %s"
1043             moreReg = [dstRegName]
1044         else:
1045             moreReg = []
1046         return formatStr % tuple([self.name()] +
1047                                  [dstRegName] +
1048                                  [str(self.reg[1])] +
1049                                  moreReg +
1050                                  [str(self.reg[2]) + self._width.astr()])
1051 
1052 class LdStNEONOp(Instruction):
1053     def __init__(self, args):
1054         self._name, self.regnum, self.arrangement, self.addresskind = args
1055 
1056     def generate(self):
1057         self.address = Address().generate(self.addresskind, 0)
1058         self._firstSIMDreg = FloatRegister().generate()
1059         if (self.addresskind  == Address.post):
1060             if (self._name in ["ld1r", "ld2r", "ld3r", "ld4r"]):
1061                 elem_size = {"8B" : 1, "16B" : 1, "4H" : 2, "8H" : 2, "2S" : 4, "4S" : 4, "1D" : 8, "2D" : 8} [self.arrangement]
1062                 self.address.offset = self.regnum * elem_size
1063             else:
1064                 if (self.arrangement in ["8B", "4H", "2S", "1D"]):
1065                     self.address.offset = self.regnum * 8
1066                 else:
1067                     self.address.offset = self.regnum * 16
1068         return self
1069 
1070     def cstr(self):
1071         buf = super(LdStNEONOp, self).cstr() + str(self._firstSIMDreg)
1072         current = self._firstSIMDreg
1073         for cnt in range(1, self.regnum):
1074             buf = '%s, %s' % (buf, current.nextReg())
1075             current = current.nextReg()
1076         return '%s, __ T%s, %s);' % (buf, self.arrangement, str(self.address))
1077 
1078     def astr(self):
1079         buf = '%s\t{%s.%s' % (self._name, self._firstSIMDreg, self.arrangement)
1080         current = self._firstSIMDreg
1081         for cnt in range(1, self.regnum):
1082             buf = '%s, %s.%s' % (buf, current.nextReg(), self.arrangement)
1083             current = current.nextReg()
1084         return  '%s}, %s' % (buf, self.address.astr("x"))
1085 
1086     def aname(self):
1087          return self._name
1088 
1089 class NEONReduceInstruction(Instruction):
1090     def __init__(self, args):
1091         self._name, self.insname, self.arrangement = args
1092 
1093     def generate(self):
1094         current = FloatRegister().generate()
1095         self.dstSIMDreg = current
1096         self.srcSIMDreg = current.nextReg()
1097         return self
1098 
1099     def cstr(self):
1100         buf = Instruction.cstr(self) + str(self.dstSIMDreg)
1101         if self._name == "fmaxp" or self._name == "fminp":
1102             buf = '%s, %s, __ %s);' % (buf, self.srcSIMDreg, self.arrangement[1:])
1103         else:
1104             buf = '%s, __ T%s, %s);' % (buf, self.arrangement, self.srcSIMDreg)
1105         return buf
1106 
1107     def astr(self):
1108         buf = '%s\t%s' % (self.insname, self.dstSIMDreg.astr(self.arrangement[-1].lower()))
1109         buf = '%s, %s.%s' % (buf, self.srcSIMDreg, self.arrangement)
1110         return buf
1111 
1112     def aname(self):
1113         return self._name
1114 
1115 class CommonNEONInstruction(Instruction):
1116     def __init__(self, args):
1117         self._name, self.insname, self.arrangement = args
1118 
1119     def generate(self):
1120         self._firstSIMDreg = FloatRegister().generate()
1121         return self
1122 
1123     def cstr(self):
1124         buf = Instruction.cstr(self) + str(self._firstSIMDreg)
1125         buf = '%s, __ T%s' % (buf, self.arrangement)
1126         current = self._firstSIMDreg
1127         for cnt in range(1, self.numRegs):
1128             buf = '%s, %s' % (buf, current.nextReg())
1129             current = current.nextReg()
1130         return '%s);' % (buf)
1131 
1132     def astr(self):
1133         buf = '%s\t%s.%s' % (self.insname, self._firstSIMDreg, self.arrangement)
1134         current = self._firstSIMDreg
1135         for cnt in range(1, self.numRegs):
1136             buf = '%s, %s.%s' % (buf, current.nextReg(), self.arrangement)
1137             current = current.nextReg()
1138         return buf
1139 
1140     def aname(self):
1141         return self._name
1142 
1143 class SHA512SIMDOp(Instruction):
1144 
1145     def generate(self):
1146         if (self._name == 'sha512su0'):
1147             self.reg = [FloatRegister().generate(), FloatRegister().generate()]
1148         else:
1149             self.reg = [FloatRegister().generate(), FloatRegister().generate(),
1150                         FloatRegister().generate()]
1151         return self
1152 
1153     def cstr(self):
1154         if (self._name == 'sha512su0'):
1155             return (super(SHA512SIMDOp, self).cstr()
1156                     + ('%s, __ T2D, %s);' % (self.reg[0], self.reg[1])))
1157         else:
1158             return (super(SHA512SIMDOp, self).cstr()
1159                     + ('%s, __ T2D, %s, %s);' % (self.reg[0], self.reg[1], self.reg[2])))
1160 
1161     def astr(self):
1162         if (self._name == 'sha512su0'):
1163             return (super(SHA512SIMDOp, self).astr()
1164                     + ('\t%s.2D, %s.2D' % (self.reg[0].astr("v"), self.reg[1].astr("v"))))
1165         elif (self._name == 'sha512su1'):
1166             return (super(SHA512SIMDOp, self).astr()
1167                     + ('\t%s.2D, %s.2D, %s.2D' % (self.reg[0].astr("v"),
1168                        self.reg[1].astr("v"), self.reg[2].astr("v"))))
1169         else:
1170             return (super(SHA512SIMDOp, self).astr()
1171                     + ('\t%s, %s, %s.2D' % (self.reg[0].astr("q"),
1172                        self.reg[1].astr("q"), self.reg[2].astr("v"))))
1173 
1174 class SHA3SIMDOp(Instruction):
1175 
1176     def generate(self):
1177         if ((self._name == 'eor3') or (self._name == 'bcax')):
1178             self.reg = [FloatRegister().generate(), FloatRegister().generate(),
1179                         FloatRegister().generate(), FloatRegister().generate()]
1180         else:
1181             self.reg = [FloatRegister().generate(), FloatRegister().generate(),
1182                         FloatRegister().generate()]
1183             if (self._name == 'xar'):
1184                 self.imm6 = random.randint(0, 63)
1185         return self
1186 
1187     def cstr(self):
1188         if ((self._name == 'eor3') or (self._name == 'bcax')):
1189             return (super(SHA3SIMDOp, self).cstr()
1190                     + ('%s, __ T16B, %s, %s, %s);' % (self.reg[0], self.reg[1], self.reg[2], self.reg[3])))
1191         elif (self._name == 'rax1'):
1192             return (super(SHA3SIMDOp, self).cstr()
1193                     + ('%s, __ T2D, %s, %s);' % (self.reg[0], self.reg[1], self.reg[2])))
1194         else:
1195             return (super(SHA3SIMDOp, self).cstr()
1196                     + ('%s, __ T2D, %s, %s, %s);' % (self.reg[0], self.reg[1], self.reg[2], self.imm6)))
1197 
1198     def astr(self):
1199         if ((self._name == 'eor3') or (self._name == 'bcax')):
1200             return (super(SHA3SIMDOp, self).astr()
1201                     + ('\t%s.16B, %s.16B, %s.16B, %s.16B' % (self.reg[0].astr("v"), self.reg[1].astr("v"),
1202                         self.reg[2].astr("v"), self.reg[3].astr("v"))))
1203         elif (self._name == 'rax1'):
1204             return (super(SHA3SIMDOp, self).astr()
1205                     + ('\t%s.2D, %s.2D, %s.2D') % (self.reg[0].astr("v"), self.reg[1].astr("v"),
1206                         self.reg[2].astr("v")))
1207         else:
1208             return (super(SHA3SIMDOp, self).astr()
1209                     + ('\t%s.2D, %s.2D, %s.2D, #%s') % (self.reg[0].astr("v"), self.reg[1].astr("v"),
1210                         self.reg[2].astr("v"), self.imm6))
1211 
1212 class LSEOp(Instruction):
1213     def __init__(self, args):
1214         self._name, self.asmname, self.size, self.suffix = args
1215 
1216     def generate(self):
1217         self._name = "%s%s" % (self._name, self.suffix)
1218         self.asmname = "%s%s" % (self.asmname, self.suffix)
1219         self.srcReg = GeneralRegisterOrZr().generate()
1220         self.tgtReg = GeneralRegisterOrZr().generate()
1221         self.adrReg = GeneralRegisterOrSp().generate()
1222 
1223         return self
1224 
1225     def cstr(self):
1226         sizeSpec = {"x" : "Assembler::xword", "w" : "Assembler::word"} [self.size]
1227         return super(LSEOp, self).cstr() + "%s, %s, %s, %s);" % (sizeSpec, self.srcReg, self.tgtReg, self.adrReg)
1228 
1229     def astr(self):
1230         return "%s\t%s, %s, [%s]" % (self.asmname, self.srcReg.astr(self.size), self.tgtReg.astr(self.size), self.adrReg.astr("x"))
1231 
1232     def aname(self):
1233          return self.asmname
1234 
1235 class TwoRegFloatOp(FloatInstruction):
1236     numRegs = 2
1237 
1238 class ThreeRegFloatOp(TwoRegFloatOp):
1239     numRegs = 3
1240 
1241 class FourRegFloatOp(TwoRegFloatOp):
1242     numRegs = 4
1243 
1244 class FloatConvertOp(TwoRegFloatOp):
1245 
1246     def __init__(self, args):
1247         self._cname, self._aname, modes = args
1248         TwoRegFloatOp.__init__(self, [self._cname, modes])
1249 
1250     def aname(self):
1251         return self._aname
1252 
1253     def cname(self):
1254         return self._cname
1255 
1256 class TwoRegNEONOp(CommonNEONInstruction):
1257     numRegs = 2
1258 
1259 class ThreeRegNEONOp(TwoRegNEONOp):
1260     numRegs = 3
1261 
1262 class SpecialCases(Instruction):
1263     def __init__(self, data):
1264         self._name = data[0]
1265         self._cstr = data[1]
1266         self._astr = data[2]
1267 
1268     def cstr(self):
1269         return self._cstr
1270 
1271     def astr(self):
1272         return self._astr
1273 
1274 def generate(kind, names):
1275     outfile.write("# " + kind.__name__ + "\n");
1276     print "\n// " + kind.__name__
1277     for name in names:
1278         for i in range(1):
1279              op = kind(name).generate()
1280              if op.multipleForms():
1281                   forms = op.forms()
1282                   aforms = op.aforms()
1283                   for i in range(op.multipleForms()):
1284                        cstr = op.cstr() % forms[i]
1285                        astr = op.astr() % aforms[i]
1286                        print "    %-50s //\t%s" % (cstr, astr)
1287                        outfile.write("\t" + astr + "\n")
1288              else:
1289                   print "    %-50s //\t%s" % (op.cstr(), op.astr())
1290                   outfile.write("\t" + op.astr() + "\n")
1291 
1292 outfile = open("aarch64ops.s", "w")
1293 
1294 # To minimize the changes of assembler test code
1295 random.seed(0)
1296 
1297 print "// BEGIN  Generated code -- do not edit"
1298 print "// Generated by aarch64-asmtest.py"
1299 
1300 print "    Label back, forth;"
1301 print "    __ bind(back);"
1302 
1303 outfile.write("back:\n")
1304 
1305 generate (ArithOp,
1306           [ "add", "sub", "adds", "subs",
1307             "addw", "subw", "addsw", "subsw",
1308             "and", "orr", "eor", "ands",
1309             "andw", "orrw", "eorw", "andsw",
1310             "bic", "orn", "eon", "bics",
1311             "bicw", "ornw", "eonw", "bicsw" ])
1312 
1313 generate (AddSubImmOp,
1314           [ "addw", "addsw", "subw", "subsw",
1315             "add", "adds", "sub", "subs"])
1316 generate (LogicalImmOp,
1317           [ "andw", "orrw", "eorw", "andsw",
1318             "and", "orr", "eor", "ands"])
1319 
1320 generate (AbsOp, [ "b", "bl" ])
1321 
1322 generate (RegAndAbsOp, ["cbzw", "cbnzw", "cbz", "cbnz", "adr", "adrp"])
1323 
1324 generate (RegImmAbsOp, ["tbz", "tbnz"])
1325 
1326 generate (MoveWideImmOp, ["movnw", "movzw", "movkw", "movn", "movz", "movk"])
1327 
1328 generate (BitfieldOp, ["sbfm", "bfmw", "ubfmw", "sbfm", "bfm", "ubfm"])
1329 
1330 generate (ExtractOp, ["extrw", "extr"])
1331 
1332 generate (CondBranchOp, ["EQ", "NE", "HS", "CS", "LO", "CC", "MI", "PL", "VS", "VC",
1333                         "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" ])
1334 
1335 generate (ImmOp, ["svc", "hvc", "smc", "brk", "hlt", # "dcps1",  "dcps2",  "dcps3"
1336                ])
1337 
1338 generate (Op, ["nop", "eret", "drps", "isb"])
1339 
1340 barriers = ["OSHLD", "OSHST", "OSH", "NSHLD", "NSHST", "NSH",
1341             "ISHLD", "ISHST", "ISH", "LD", "ST", "SY"]
1342 
1343 generate (SystemOp, [["dsb", barriers], ["dmb", barriers]])
1344 
1345 generate (OneRegOp, ["br", "blr"])
1346 
1347 for mode in 'xwhb':
1348     generate (LoadStoreExclusiveOp, [["stxr", mode, 3], ["stlxr", mode, 3],
1349                                      ["ldxr", mode, 2], ["ldaxr", mode, 2],
1350                                      ["stlr", mode, 2], ["ldar", mode, 2]])
1351 
1352 for mode in 'xw':
1353     generate (LoadStoreExclusiveOp, [["ldxp", mode, 3], ["ldaxp", mode, 3],
1354                                      ["stxp", mode, 4], ["stlxp", mode, 4]])
1355 
1356 for kind in range(6):
1357     sys.stdout.write("\n// " + Address.kindToStr(kind))
1358     if kind != Address.pcrel:
1359         generate (LoadStoreOp,
1360                   [["str", "str", kind, "x"], ["str", "str", kind, "w"],
1361                    ["str", "strb", kind, "b"], ["str", "strh", kind, "h"],
1362                    ["ldr", "ldr", kind, "x"], ["ldr", "ldr", kind, "w"],
1363                    ["ldr", "ldrb", kind, "b"], ["ldr", "ldrh", kind, "h"],
1364                    ["ldrsb", "ldrsb", kind, "x"], ["ldrsh", "ldrsh", kind, "x"],
1365                    ["ldrsh", "ldrsh", kind, "w"], ["ldrsw", "ldrsw", kind, "x"],
1366                    ["ldr", "ldr", kind, "d"], ["ldr", "ldr", kind, "s"],
1367                    ["str", "str", kind, "d"], ["str", "str", kind, "s"],
1368                    ])
1369     else:
1370         generate (LoadStoreOp,
1371                   [["ldr", "ldr", kind, "x"], ["ldr", "ldr", kind, "w"]])
1372 
1373 
1374 for kind in (Address.base_plus_unscaled_offset, Address.pcrel, Address.base_plus_reg, \
1375                  Address.base_plus_scaled_offset):
1376     generate (LoadStoreOp,
1377               [["prfm", "prfm\tPLDL1KEEP,", kind, "x"]])
1378 
1379 generate(AddSubCarryOp, ["adcw", "adcsw", "sbcw", "sbcsw", "adc", "adcs", "sbc", "sbcs"])
1380 
1381 generate(AddSubExtendedOp, ["addw", "addsw", "sub", "subsw", "add", "adds", "sub", "subs"])
1382 
1383 generate(ConditionalCompareOp, ["ccmnw", "ccmpw", "ccmn", "ccmp"])
1384 generate(ConditionalCompareImmedOp, ["ccmnw", "ccmpw", "ccmn", "ccmp"])
1385 generate(ConditionalSelectOp,
1386          ["cselw", "csincw", "csinvw", "csnegw", "csel", "csinc", "csinv", "csneg"])
1387 
1388 generate(TwoRegOp,
1389          ["rbitw", "rev16w", "revw", "clzw", "clsw", "rbit",
1390           "rev16", "rev32", "rev", "clz", "cls"])
1391 generate(ThreeRegOp,
1392          ["udivw", "sdivw", "lslvw", "lsrvw", "asrvw", "rorvw", "udiv", "sdiv",
1393           "lslv", "lsrv", "asrv", "rorv", "umulh", "smulh"])
1394 generate(FourRegMulOp,
1395          ["maddw", "msubw", "madd", "msub", "smaddl", "smsubl", "umaddl", "umsubl"])
1396 
1397 generate(ThreeRegFloatOp,
1398          [["fabds", "sss"], ["fmuls", "sss"], ["fdivs", "sss"], ["fadds", "sss"], ["fsubs", "sss"],
1399           ["fabdd", "ddd"], ["fmuld", "ddd"], ["fdivd", "ddd"], ["faddd", "ddd"], ["fsubd", "ddd"],
1400           ])
1401 
1402 generate(FourRegFloatOp,
1403          [["fmadds", "ssss"], ["fmsubs", "ssss"], ["fnmadds", "ssss"], ["fnmadds", "ssss"],
1404           ["fmaddd", "dddd"], ["fmsubd", "dddd"], ["fnmaddd", "dddd"], ["fnmaddd", "dddd"],])
1405 
1406 generate(TwoRegFloatOp,
1407          [["fmovs", "ss"], ["fabss", "ss"], ["fnegs", "ss"], ["fsqrts", "ss"],
1408           ["fcvts", "ds"],
1409           ["fmovd", "dd"], ["fabsd", "dd"], ["fnegd", "dd"], ["fsqrtd", "dd"],
1410           ["fcvtd", "sd"],
1411           ])
1412 
1413 generate(FloatConvertOp, [["fcvtzsw", "fcvtzs", "ws"], ["fcvtzs", "fcvtzs", "xs"],
1414                           ["fcvtzdw", "fcvtzs", "wd"], ["fcvtzd", "fcvtzs", "xd"],
1415                           ["scvtfws", "scvtf", "sw"], ["scvtfs", "scvtf", "sx"],
1416                           ["scvtfwd", "scvtf", "dw"], ["scvtfd", "scvtf", "dx"],
1417                           ["fmovs", "fmov", "ws"], ["fmovd", "fmov", "xd"],
1418                           ["fmovs", "fmov", "sw"], ["fmovd", "fmov", "dx"]])
1419 
1420 generate(TwoRegFloatOp, [["fcmps", "ss"], ["fcmpd", "dd"],
1421                          ["fcmps", "sz"], ["fcmpd", "dz"]])
1422 
1423 for kind in range(3):
1424      generate(LoadStorePairOp, [["stp", "stp", kind, "w"], ["ldp", "ldp", kind, "w"],
1425                                 ["ldpsw", "ldpsw", kind, "x"],
1426                                 ["stp", "stp", kind, "x"], ["ldp", "ldp", kind, "x"]
1427                                 ])
1428 generate(LoadStorePairOp, [["stnp", "stnp", 0, "w"], ["ldnp", "ldnp", 0, "w"],
1429                            ["stnp", "stnp", 0, "x"], ["ldnp", "ldnp", 0, "x"]])
1430 
1431 generate(LdStNEONOp, [["ld1",  1, "8B",  Address.base_only],
1432                       ["ld1",  2, "16B", Address.post],
1433                       ["ld1",  3, "1D",  Address.post_reg],
1434                       ["ld1",  4, "8H",  Address.post],
1435                       ["ld1r", 1, "8B",  Address.base_only],
1436                       ["ld1r", 1, "4S",  Address.post],
1437                       ["ld1r", 1, "1D",  Address.post_reg],
1438                       ["ld2",  2, "2D",  Address.base_only],
1439                       ["ld2",  2, "4H",  Address.post],
1440                       ["ld2r", 2, "16B", Address.base_only],
1441                       ["ld2r", 2, "2S",  Address.post],
1442                       ["ld2r", 2, "2D",  Address.post_reg],
1443                       ["ld3",  3, "4S",  Address.post_reg],
1444                       ["ld3",  3, "2S",  Address.base_only],
1445                       ["ld3r", 3, "8H",  Address.base_only],
1446                       ["ld3r", 3, "4S",  Address.post],
1447                       ["ld3r", 3, "1D",  Address.post_reg],
1448                       ["ld4",  4, "8H",  Address.post],
1449                       ["ld4",  4, "8B",  Address.post_reg],
1450                       ["ld4r", 4, "8B",  Address.base_only],
1451                       ["ld4r", 4, "4H",  Address.post],
1452                       ["ld4r", 4, "2S",  Address.post_reg],
1453 ])
1454 
1455 generate(NEONReduceInstruction,
1456          [["addv", "addv", "8B"], ["addv", "addv", "16B"],
1457           ["addv", "addv", "4H"], ["addv", "addv", "8H"],
1458           ["addv", "addv", "4S"],
1459           ["smaxv", "smaxv", "8B"], ["smaxv", "smaxv", "16B"],
1460           ["smaxv", "smaxv", "4H"], ["smaxv", "smaxv", "8H"],
1461           ["smaxv", "smaxv", "4S"], ["fmaxv", "fmaxv", "4S"],
1462           ["sminv", "sminv", "8B"], ["uminv", "uminv", "8B"],
1463           ["sminv", "sminv", "16B"],["uminv", "uminv", "16B"],
1464           ["sminv", "sminv", "4H"], ["uminv", "uminv", "4H"],
1465           ["sminv", "sminv", "8H"], ["uminv", "uminv", "8H"],
1466           ["sminv", "sminv", "4S"], ["uminv", "uminv", "4S"],
1467           ["fminv", "fminv", "4S"],
1468           ["fmaxp", "fmaxp", "2S"], ["fmaxp", "fmaxp", "2D"],
1469           ["fminp", "fminp", "2S"], ["fminp", "fminp", "2D"],
1470           ])
1471 
1472 generate(TwoRegNEONOp,
1473          [["absr", "abs", "8B"], ["absr", "abs", "16B"],
1474           ["absr", "abs", "4H"], ["absr", "abs", "8H"],
1475           ["absr", "abs", "2S"], ["absr", "abs", "4S"],
1476           ["absr", "abs", "2D"],
1477           ["fabs", "fabs", "2S"], ["fabs", "fabs", "4S"],
1478           ["fabs", "fabs", "2D"],
1479           ["fneg", "fneg", "2S"], ["fneg", "fneg", "4S"],
1480           ["fneg", "fneg", "2D"],
1481           ["fsqrt", "fsqrt", "2S"], ["fsqrt", "fsqrt", "4S"],
1482           ["fsqrt", "fsqrt", "2D"],
1483           ["notr", "not", "8B"], ["notr", "not", "16B"],
1484           ])
1485 
1486 generate(ThreeRegNEONOp,
1487          [["andr", "and", "8B"], ["andr", "and", "16B"],
1488           ["orr", "orr", "8B"], ["orr", "orr", "16B"],
1489           ["eor", "eor", "8B"], ["eor", "eor", "16B"],
1490           ["addv", "add", "8B"], ["addv", "add", "16B"],
1491           ["addv", "add", "4H"], ["addv", "add", "8H"],
1492           ["addv", "add", "2S"], ["addv", "add", "4S"],
1493           ["addv", "add", "2D"],
1494           ["fadd", "fadd", "2S"], ["fadd", "fadd", "4S"],
1495           ["fadd", "fadd", "2D"],
1496           ["subv", "sub", "8B"], ["subv", "sub", "16B"],
1497           ["subv", "sub", "4H"], ["subv", "sub", "8H"],
1498           ["subv", "sub", "2S"], ["subv", "sub", "4S"],
1499           ["subv", "sub", "2D"],
1500           ["fsub", "fsub", "2S"], ["fsub", "fsub", "4S"],
1501           ["fsub", "fsub", "2D"],
1502           ["mulv", "mul", "8B"], ["mulv", "mul", "16B"],
1503           ["mulv", "mul", "4H"], ["mulv", "mul", "8H"],
1504           ["mulv", "mul", "2S"], ["mulv", "mul", "4S"],
1505           ["fabd", "fabd", "2S"], ["fabd", "fabd", "4S"],
1506           ["fabd", "fabd", "2D"],
1507           ["fmul", "fmul", "2S"], ["fmul", "fmul", "4S"],
1508           ["fmul", "fmul", "2D"],
1509           ["mlav", "mla", "4H"], ["mlav", "mla", "8H"],
1510           ["mlav", "mla", "2S"], ["mlav", "mla", "4S"],
1511           ["fmla", "fmla", "2S"], ["fmla", "fmla", "4S"],
1512           ["fmla", "fmla", "2D"],
1513           ["mlsv", "mls", "4H"], ["mlsv", "mls", "8H"],
1514           ["mlsv", "mls", "2S"], ["mlsv", "mls", "4S"],
1515           ["fmls", "fmls", "2S"], ["fmls", "fmls", "4S"],
1516           ["fmls", "fmls", "2D"],
1517           ["fdiv", "fdiv", "2S"], ["fdiv", "fdiv", "4S"],
1518           ["fdiv", "fdiv", "2D"],
1519           ["maxv", "smax", "8B"], ["maxv", "smax", "16B"],
1520           ["maxv", "smax", "4H"], ["maxv", "smax", "8H"],
1521           ["maxv", "smax", "2S"], ["maxv", "smax", "4S"],
1522           ["smaxp", "smaxp", "8B"], ["smaxp", "smaxp", "16B"],
1523           ["smaxp", "smaxp", "4H"], ["smaxp", "smaxp", "8H"],
1524           ["smaxp", "smaxp", "2S"], ["smaxp", "smaxp", "4S"],
1525           ["fmax", "fmax", "2S"], ["fmax", "fmax", "4S"],
1526           ["fmax", "fmax", "2D"],
1527           ["minv", "smin", "8B"], ["minv", "smin", "16B"],
1528           ["minv", "smin", "4H"], ["minv", "smin", "8H"],
1529           ["minv", "smin", "2S"], ["minv", "smin", "4S"],
1530           ["sminp", "sminp", "8B"], ["sminp", "sminp", "16B"],
1531           ["sminp", "sminp", "4H"], ["sminp", "sminp", "8H"],
1532           ["sminp", "sminp", "2S"], ["sminp", "sminp", "4S"],
1533           ["fmin", "fmin", "2S"], ["fmin", "fmin", "4S"],
1534           ["fmin", "fmin", "2D"],
1535           ["cmeq", "cmeq", "8B"], ["cmeq", "cmeq", "16B"],
1536           ["cmeq", "cmeq", "4H"], ["cmeq", "cmeq", "8H"],
1537           ["cmeq", "cmeq", "2S"], ["cmeq", "cmeq", "4S"],
1538           ["cmeq", "cmeq", "2D"],
1539           ["fcmeq", "fcmeq", "2S"], ["fcmeq", "fcmeq", "4S"],
1540           ["fcmeq", "fcmeq", "2D"],
1541           ["cmgt", "cmgt", "8B"], ["cmgt", "cmgt", "16B"],
1542           ["cmgt", "cmgt", "4H"], ["cmgt", "cmgt", "8H"],
1543           ["cmgt", "cmgt", "2S"], ["cmgt", "cmgt", "4S"],
1544           ["cmgt", "cmgt", "2D"],
1545           ["cmhi", "cmhi", "8B"], ["cmhi", "cmhi", "16B"],
1546           ["cmhi", "cmhi", "4H"], ["cmhi", "cmhi", "8H"],
1547           ["cmhi", "cmhi", "2S"], ["cmhi", "cmhi", "4S"],
1548           ["cmhi", "cmhi", "2D"],
1549           ["cmhs", "cmhs", "8B"], ["cmhs", "cmhs", "16B"],
1550           ["cmhs", "cmhs", "4H"], ["cmhs", "cmhs", "8H"],
1551           ["cmhs", "cmhs", "2S"], ["cmhs", "cmhs", "4S"],
1552           ["cmhs", "cmhs", "2D"],
1553           ["fcmgt", "fcmgt", "2S"], ["fcmgt", "fcmgt", "4S"],
1554           ["fcmgt", "fcmgt", "2D"],
1555           ["cmge", "cmge", "8B"], ["cmge", "cmge", "16B"],
1556           ["cmge", "cmge", "4H"], ["cmge", "cmge", "8H"],
1557           ["cmge", "cmge", "2S"], ["cmge", "cmge", "4S"],
1558           ["cmge", "cmge", "2D"],
1559           ["fcmge", "fcmge", "2S"], ["fcmge", "fcmge", "4S"],
1560           ["fcmge", "fcmge", "2D"],
1561           ])
1562 
1563 generate(SpecialCases, [["ccmn",   "__ ccmn(zr, zr, 3u, Assembler::LE);",                "ccmn\txzr, xzr, #3, LE"],
1564                         ["ccmnw",  "__ ccmnw(zr, zr, 5u, Assembler::EQ);",               "ccmn\twzr, wzr, #5, EQ"],
1565                         ["ccmp",   "__ ccmp(zr, 1, 4u, Assembler::NE);",                 "ccmp\txzr, 1, #4, NE"],
1566                         ["ccmpw",  "__ ccmpw(zr, 2, 2, Assembler::GT);",                 "ccmp\twzr, 2, #2, GT"],
1567                         ["extr",   "__ extr(zr, zr, zr, 0);",                            "extr\txzr, xzr, xzr, 0"],
1568                         ["stlxp",  "__ stlxp(r0, zr, zr, sp);",                          "stlxp\tw0, xzr, xzr, [sp]"],
1569                         ["stlxpw", "__ stlxpw(r2, zr, zr, r3);",                         "stlxp\tw2, wzr, wzr, [x3]"],
1570                         ["stxp",   "__ stxp(r4, zr, zr, r5);",                           "stxp\tw4, xzr, xzr, [x5]"],
1571                         ["stxpw",  "__ stxpw(r6, zr, zr, sp);",                          "stxp\tw6, wzr, wzr, [sp]"],
1572                         ["dup",    "__ dup(v0, __ T16B, zr);",                           "dup\tv0.16b, wzr"],
1573                         ["dup",    "__ dup(v0, __ S, v1);",                              "dup\ts0, v1.s[0]"],
1574                         ["mov",    "__ mov(v1, __ D, 0, zr);",                           "mov\tv1.d[0], xzr"],
1575                         ["mov",    "__ mov(v1, __ S, 1, zr);",                           "mov\tv1.s[1], wzr"],
1576                         ["mov",    "__ mov(v1, __ H, 2, zr);",                           "mov\tv1.h[2], wzr"],
1577                         ["mov",    "__ mov(v1, __ B, 3, zr);",                           "mov\tv1.b[3], wzr"],
1578                         ["smov",   "__ smov(r0, v1, __ S, 0);",                          "smov\tx0, v1.s[0]"],
1579                         ["smov",   "__ smov(r0, v1, __ H, 1);",                          "smov\tx0, v1.h[1]"],
1580                         ["smov",   "__ smov(r0, v1, __ B, 2);",                          "smov\tx0, v1.b[2]"],
1581                         ["umov",   "__ umov(r0, v1, __ D, 0);",                          "umov\tx0, v1.d[0]"],
1582                         ["umov",   "__ umov(r0, v1, __ S, 1);",                          "umov\tw0, v1.s[1]"],
1583                         ["umov",   "__ umov(r0, v1, __ H, 2);",                          "umov\tw0, v1.h[2]"],
1584                         ["umov",   "__ umov(r0, v1, __ B, 3);",                          "umov\tw0, v1.b[3]"],
1585                         ["fmov",   "__ fmovhid(r0, v1);",                                "fmov\tx0, v1.d[1]"],
1586                         ["ld1",    "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"],
1587                         ["fcvtzs", "__ fcvtzs(v0, __ T4S, v1);",                         "fcvtzs\tv0.4s, v1.4s"],
1588                         # SVE instructions
1589                         ["cpy",     "__ sve_cpy(z0, __ S, p0, v1);",                      "mov\tz0.s, p0/m, s1"],
1590                         ["cpy",     "__ sve_cpy(z0, __ B, p0, 127, true);",               "mov\tz0.b, p0/m, 127"],
1591                         ["cpy",     "__ sve_cpy(z1, __ H, p0, -128, true);",              "mov\tz1.h, p0/m, -128"],
1592                         ["cpy",     "__ sve_cpy(z2, __ S, p0, 32512, true);",             "mov\tz2.s, p0/m, 32512"],
1593                         ["cpy",     "__ sve_cpy(z5, __ D, p0, -32768, false);",           "mov\tz5.d, p0/z, -32768"],
1594                         ["cpy",     "__ sve_cpy(z10, __ B, p0, -1, false);",              "mov\tz10.b, p0/z, -1"],
1595                         ["cpy",     "__ sve_cpy(z11, __ S, p0, -1, false);",              "mov\tz11.s, p0/z, -1"],
1596                         ["inc",     "__ sve_inc(r0, __ S);",                              "incw\tx0"],
1597                         ["dec",     "__ sve_dec(r1, __ H);",                              "dech\tx1"],
1598                         ["lsl",     "__ sve_lsl(z0, __ B, z1, 7);",                       "lsl\tz0.b, z1.b, #7"],
1599                         ["lsl",     "__ sve_lsl(z21, __ H, z1, 15);",                     "lsl\tz21.h, z1.h, #15"],
1600                         ["lsl",     "__ sve_lsl(z0, __ S, z1, 31);",                      "lsl\tz0.s, z1.s, #31"],
1601                         ["lsl",     "__ sve_lsl(z0, __ D, z1, 63);",                      "lsl\tz0.d, z1.d, #63"],
1602                         ["lsr",     "__ sve_lsr(z0, __ B, z1, 7);",                       "lsr\tz0.b, z1.b, #7"],
1603                         ["asr",     "__ sve_asr(z0, __ H, z11, 15);",                     "asr\tz0.h, z11.h, #15"],
1604                         ["lsr",     "__ sve_lsr(z30, __ S, z1, 31);",                     "lsr\tz30.s, z1.s, #31"],
1605                         ["asr",     "__ sve_asr(z0, __ D, z1, 63);",                      "asr\tz0.d, z1.d, #63"],
1606                         ["lsl",     "__ sve_lsl(z0, __ B, p0, 0);",                       "lsl\tz0.b, p0/m, z0.b, #0"],
1607                         ["lsl",     "__ sve_lsl(z0, __ B, p0, 5);",                       "lsl\tz0.b, p0/m, z0.b, #5"],
1608                         ["lsl",     "__ sve_lsl(z1, __ H, p1, 15);",                      "lsl\tz1.h, p1/m, z1.h, #15"],
1609                         ["lsl",     "__ sve_lsl(z2, __ S, p2, 31);",                      "lsl\tz2.s, p2/m, z2.s, #31"],
1610                         ["lsl",     "__ sve_lsl(z3, __ D, p3, 63);",                      "lsl\tz3.d, p3/m, z3.d, #63"],
1611                         ["lsr",     "__ sve_lsr(z0, __ B, p0, 1);",                       "lsr\tz0.b, p0/m, z0.b, #1"],
1612                         ["lsr",     "__ sve_lsr(z0, __ B, p0, 8);",                       "lsr\tz0.b, p0/m, z0.b, #8"],
1613                         ["lsr",     "__ sve_lsr(z1, __ H, p1, 15);",                      "lsr\tz1.h, p1/m, z1.h, #15"],
1614                         ["lsr",     "__ sve_lsr(z2, __ S, p2, 7);",                       "lsr\tz2.s, p2/m, z2.s, #7"],
1615                         ["lsr",     "__ sve_lsr(z2, __ S, p2, 31);",                      "lsr\tz2.s, p2/m, z2.s, #31"],
1616                         ["lsr",     "__ sve_lsr(z3, __ D, p3, 63);",                      "lsr\tz3.d, p3/m, z3.d, #63"],
1617                         ["asr",     "__ sve_asr(z0, __ B, p0, 1);",                       "asr\tz0.b, p0/m, z0.b, #1"],
1618                         ["asr",     "__ sve_asr(z0, __ B, p0, 7);",                       "asr\tz0.b, p0/m, z0.b, #7"],
1619                         ["asr",     "__ sve_asr(z1, __ H, p1, 5);",                       "asr\tz1.h, p1/m, z1.h, #5"],
1620                         ["asr",     "__ sve_asr(z1, __ H, p1, 15);",                      "asr\tz1.h, p1/m, z1.h, #15"],
1621                         ["asr",     "__ sve_asr(z2, __ S, p2, 31);",                      "asr\tz2.s, p2/m, z2.s, #31"],
1622                         ["asr",     "__ sve_asr(z3, __ D, p3, 63);",                      "asr\tz3.d, p3/m, z3.d, #63"],
1623                         ["addvl",   "__ sve_addvl(sp, r0, 31);",                          "addvl\tsp, x0, #31"],
1624                         ["addpl",   "__ sve_addpl(r1, sp, -32);",                         "addpl\tx1, sp, -32"],
1625                         ["cntp",    "__ sve_cntp(r8, __ B, p0, p1);",                     "cntp\tx8, p0, p1.b"],
1626                         ["dup",     "__ sve_dup(z0, __ B, 127);",                         "dup\tz0.b, 127"],
1627                         ["dup",     "__ sve_dup(z1, __ H, -128);",                        "dup\tz1.h, -128"],
1628                         ["dup",     "__ sve_dup(z2, __ S, 32512);",                       "dup\tz2.s, 32512"],
1629                         ["dup",     "__ sve_dup(z7, __ D, -32768);",                      "dup\tz7.d, -32768"],
1630                         ["dup",     "__ sve_dup(z10, __ B, -1);",                         "dup\tz10.b, -1"],
1631                         ["dup",     "__ sve_dup(z11, __ S, -1);",                         "dup\tz11.s, -1"],
1632                         ["ld1b",    "__ sve_ld1b(z0, __ B, p0, Address(sp));",            "ld1b\t{z0.b}, p0/z, [sp]"],
1633                         ["ld1b",    "__ sve_ld1b(z0, __ H, p1, Address(sp));",            "ld1b\t{z0.h}, p1/z, [sp]"],
1634                         ["ld1b",    "__ sve_ld1b(z0, __ S, p2, Address(sp, r8));",        "ld1b\t{z0.s}, p2/z, [sp, x8]"],
1635                         ["ld1b",    "__ sve_ld1b(z0, __ D, p3, Address(sp, 7));",         "ld1b\t{z0.d}, p3/z, [sp, #7, MUL VL]"],
1636                         ["ld1h",    "__ sve_ld1h(z10, __ H, p1, Address(sp, -8));",       "ld1h\t{z10.h}, p1/z, [sp, #-8, MUL VL]"],
1637                         ["ld1w",    "__ sve_ld1w(z20, __ S, p2, Address(r0, 7));",        "ld1w\t{z20.s}, p2/z, [x0, #7, MUL VL]"],
1638                         ["ld1b",    "__ sve_ld1b(z30, __ B, p3, Address(sp, r8));",       "ld1b\t{z30.b}, p3/z, [sp, x8]"],
1639                         ["ld1w",    "__ sve_ld1w(z0, __ S, p4, Address(sp, r28));",       "ld1w\t{z0.s}, p4/z, [sp, x28, LSL #2]"],
1640                         ["ld1d",    "__ sve_ld1d(z11, __ D, p5, Address(r0, r1));",       "ld1d\t{z11.d}, p5/z, [x0, x1, LSL #3]"],
1641                         ["st1b",    "__ sve_st1b(z22, __ B, p6, Address(sp));",           "st1b\t{z22.b}, p6, [sp]"],
1642                         ["st1b",    "__ sve_st1b(z31, __ B, p7, Address(sp, -8));",       "st1b\t{z31.b}, p7, [sp, #-8, MUL VL]"],
1643                         ["st1b",    "__ sve_st1b(z0, __ H, p1, Address(sp));",            "st1b\t{z0.h}, p1, [sp]"],
1644                         ["st1b",    "__ sve_st1b(z0, __ S, p2, Address(sp, r8));",        "st1b\t{z0.s}, p2, [sp, x8]"],
1645                         ["st1b",    "__ sve_st1b(z0, __ D, p3, Address(sp));",            "st1b\t{z0.d}, p3, [sp]"],
1646                         ["st1w",    "__ sve_st1w(z0, __ S, p1, Address(r0, 7));",         "st1w\t{z0.s}, p1, [x0, #7, MUL VL]"],
1647                         ["st1b",    "__ sve_st1b(z0, __ B, p2, Address(sp, r1));",        "st1b\t{z0.b}, p2, [sp, x1]"],
1648                         ["st1h",    "__ sve_st1h(z0, __ H, p3, Address(sp, r8));",        "st1h\t{z0.h}, p3, [sp, x8, LSL #1]"],
1649                         ["st1d",    "__ sve_st1d(z0, __ D, p4, Address(r0, r17));",       "st1d\t{z0.d}, p4, [x0, x17, LSL #3]"],
1650                         ["ldr",     "__ sve_ldr(z0, Address(sp));",                       "ldr\tz0, [sp]"],
1651                         ["ldr",     "__ sve_ldr(z31, Address(sp, -256));",                "ldr\tz31, [sp, #-256, MUL VL]"],
1652                         ["str",     "__ sve_str(z8, Address(r8, 255));",                  "str\tz8, [x8, #255, MUL VL]"],
1653                         ["cntb",    "__ sve_cntb(r9);",                                   "cntb\tx9"],
1654                         ["cnth",    "__ sve_cnth(r10);",                                  "cnth\tx10"],
1655                         ["cntw",    "__ sve_cntw(r11);",                                  "cntw\tx11"],
1656                         ["cntd",    "__ sve_cntd(r12);",                                  "cntd\tx12"],
1657                         ["brka",    "__ sve_brka(p2, p0, p2, false);",                    "brka\tp2.b, p0/z, p2.b"],
1658                         ["brka",    "__ sve_brka(p1, p2, p3, true);",                     "brka\tp1.b, p2/m, p3.b"],
1659                         ["brkb",    "__ sve_brkb(p1, p2, p3, false);",                    "brkb\tp1.b, p2/z, p3.b"],
1660                         ["brkb",    "__ sve_brkb(p2, p3, p4, true);",                     "brkb\tp2.b, p3/m, p4.b"],
1661                         ["rev",     "__ sve_rev(p0, __ B, p1);",                          "rev\tp0.b, p1.b"],
1662                         ["rev",     "__ sve_rev(p1, __ H, p2);",                          "rev\tp1.h, p2.h"],
1663                         ["rev",     "__ sve_rev(p2, __ S, p3);",                          "rev\tp2.s, p3.s"],
1664                         ["rev",     "__ sve_rev(p3, __ D, p4);",                          "rev\tp3.d, p4.d"],
1665                         ["incp",    "__ sve_incp(r0, __ B, p2);",                         "incp\tx0, p2.b"],
1666                         ["whilelt", "__ sve_whilelt(p0, __ B, r1, r28);",                 "whilelt\tp0.b, x1, x28"],
1667                         ["whilele", "__ sve_whilele(p2, __ H, r11, r8);",                 "whilele\tp2.h, x11, x8"],
1668                         ["whilelo", "__ sve_whilelo(p3, __ S, r7, r2);",                  "whilelo\tp3.s, x7, x2"],
1669                         ["whilels", "__ sve_whilels(p4, __ D, r17, r10);",                "whilels\tp4.d, x17, x10"],
1670                         ["sel",     "__ sve_sel(z0, __ B, p0, z1, z2);",                  "sel\tz0.b, p0, z1.b, z2.b"],
1671                         ["sel",     "__ sve_sel(z4, __ D, p0, z5, z6);",                  "sel\tz4.d, p0, z5.d, z6.d"],
1672                         ["cmpeq",   "__ sve_cmp(Assembler::EQ, p1, __ B, p0, z0, z1);",   "cmpeq\tp1.b, p0/z, z0.b, z1.b"],
1673                         ["cmpne",   "__ sve_cmp(Assembler::NE, p1, __ H, p0, z2, z3);",   "cmpne\tp1.h, p0/z, z2.h, z3.h"],
1674                         ["cmpge",   "__ sve_cmp(Assembler::GE, p1, __ S, p2, z4, z5);",   "cmpge\tp1.s, p2/z, z4.s, z5.s"],
1675                         ["cmpgt",   "__ sve_cmp(Assembler::GT, p1, __ D, p3, z6, z7);",   "cmpgt\tp1.d, p3/z, z6.d, z7.d"],
1676                         ["cmphi",   "__ sve_cmp(Assembler::HI, p1, __ S, p2, z4, z5);",   "cmphi\tp1.s, p2/z, z4.s, z5.s"],
1677                         ["cmphs",   "__ sve_cmp(Assembler::HS, p1, __ D, p3, z6, z7);",   "cmphs\tp1.d, p3/z, z6.d, z7.d"],
1678                         ["cmpeq",   "__ sve_cmp(Assembler::EQ, p1, __ B, p4, z0, 15);",   "cmpeq\tp1.b, p4/z, z0.b, #15"],
1679                         ["cmpne",   "__ sve_cmp(Assembler::NE, p1, __ H, p0, z2, -16);",  "cmpne\tp1.h, p0/z, z2.h, #-16"],
1680                         ["cmple",   "__ sve_cmp(Assembler::LE, p1, __ S, p1, z4, 0);",    "cmple\tp1.s, p1/z, z4.s, #0"],
1681                         ["cmplt",   "__ sve_cmp(Assembler::LT, p1, __ D, p2, z6, -1);",   "cmplt\tp1.d, p2/z, z6.d, #-1"],
1682                         ["cmpge",   "__ sve_cmp(Assembler::GE, p1, __ S, p3, z4, 5);",    "cmpge\tp1.s, p3/z, z4.s, #5"],
1683                         ["cmpgt",   "__ sve_cmp(Assembler::GT, p1, __ B, p4, z6, -2);",   "cmpgt\tp1.b, p4/z, z6.b, #-2"],
1684                         ["fcmeq",   "__ sve_fcm(Assembler::EQ, p1, __ S, p0, z0, z1);",   "fcmeq\tp1.s, p0/z, z0.s, z1.s"],
1685                         ["fcmne",   "__ sve_fcm(Assembler::NE, p1, __ D, p0, z2, z3);",   "fcmne\tp1.d, p0/z, z2.d, z3.d"],
1686                         ["fcmgt",   "__ sve_fcm(Assembler::GT, p1, __ S, p2, z4, z5);",   "fcmgt\tp1.s, p2/z, z4.s, z5.s"],
1687                         ["fcmge",   "__ sve_fcm(Assembler::GE, p1, __ D, p3, z6, z7);",   "fcmge\tp1.d, p3/z, z6.d, z7.d"],
1688                         ["uunpkhi", "__ sve_uunpkhi(z0, __ H, z1);",                      "uunpkhi\tz0.h, z1.b"],
1689                         ["uunpklo", "__ sve_uunpklo(z4, __ S, z5);",                      "uunpklo\tz4.s, z5.h"],
1690                         ["sunpkhi", "__ sve_sunpkhi(z6, __ D, z7);",                      "sunpkhi\tz6.d, z7.s"],
1691                         ["sunpklo", "__ sve_sunpklo(z10, __ H, z11);",                    "sunpklo\tz10.h, z11.b"],
1692                         ["scvtf",   "__ sve_scvtf(z1, __ D, p0, z0, __ S);",              "scvtf\tz1.d, p0/m, z0.s"],
1693                         ["scvtf",   "__ sve_scvtf(z3, __ D, p1, z2, __ D);",              "scvtf\tz3.d, p1/m, z2.d"],
1694                         ["scvtf",   "__ sve_scvtf(z6, __ S, p2, z1, __ D);",              "scvtf\tz6.s, p2/m, z1.d"],
1695                         ["scvtf",   "__ sve_scvtf(z6, __ S, p3, z1, __ S);",              "scvtf\tz6.s, p3/m, z1.s"],
1696                         ["scvtf",   "__ sve_scvtf(z6, __ H, p3, z1, __ S);",              "scvtf\tz6.h, p3/m, z1.s"],
1697                         ["scvtf",   "__ sve_scvtf(z6, __ H, p3, z1, __ D);",              "scvtf\tz6.h, p3/m, z1.d"],
1698                         ["scvtf",   "__ sve_scvtf(z6, __ H, p3, z1, __ H);",              "scvtf\tz6.h, p3/m, z1.h"],
1699                         ["fcvt",    "__ sve_fcvt(z5, __ D, p3, z4, __ S);",               "fcvt\tz5.d, p3/m, z4.s"],
1700                         ["fcvt",    "__ sve_fcvt(z1, __ S, p3, z0, __ D);",               "fcvt\tz1.s, p3/m, z0.d"],
1701                         ["fcvtzs",  "__ sve_fcvtzs(z19, __ D, p2, z1, __ D);",            "fcvtzs\tz19.d, p2/m, z1.d"],
1702                         ["fcvtzs",  "__ sve_fcvtzs(z9, __ S, p1, z8, __ S);",             "fcvtzs\tz9.s, p1/m, z8.s"],
1703                         ["fcvtzs",  "__ sve_fcvtzs(z1, __ S, p2, z0, __ D);",             "fcvtzs\tz1.s, p2/m, z0.d"],
1704                         ["fcvtzs",  "__ sve_fcvtzs(z1, __ D, p3, z0, __ S);",             "fcvtzs\tz1.d, p3/m, z0.s"],
1705                         ["fcvtzs",  "__ sve_fcvtzs(z1, __ S, p4, z18, __ H);",            "fcvtzs\tz1.s, p4/m, z18.h"],
1706                         ["lasta",   "__ sve_lasta(r0, __ B, p0, z15);",                   "lasta\tw0, p0, z15.b"],
1707                         ["lastb",   "__ sve_lastb(r1, __ B, p1, z16);",                   "lastb\tw1, p1, z16.b"],
1708                         ["lasta",   "__ sve_lasta(v0, __ B, p0, z15);",                   "lasta\tb0, p0, z15.b"],
1709                         ["lastb",   "__ sve_lastb(v1, __ B, p1, z16);",                   "lastb\tb1, p1, z16.b"],
1710                         ["index",   "__ sve_index(z6, __ S, 1, 1);",                      "index\tz6.s, #1, #1"],
1711                         ["index",   "__ sve_index(z6, __ B, r5, 2);",                     "index\tz6.b, w5, #2"],
1712                         ["index",   "__ sve_index(z6, __ H, r5, 3);",                     "index\tz6.h, w5, #3"],
1713                         ["index",   "__ sve_index(z6, __ S, r5, 4);",                     "index\tz6.s, w5, #4"],
1714                         ["index",   "__ sve_index(z7, __ D, r5, 5);",                     "index\tz7.d, x5, #5"],
1715                         ["cpy",     "__ sve_cpy(z7, __ H, p3, r5);",                      "cpy\tz7.h, p3/m, w5"],
1716                         ["tbl",     "__ sve_tbl(z16, __ S, z17, z18);",                   "tbl\tz16.s, {z17.s}, z18.s"],
1717                         ["ld1w",    "__ sve_ld1w_gather(z15, p0, r5, z16);",              "ld1w\t{z15.s}, p0/z, [x5, z16.s, uxtw #2]"],
1718                         ["ld1d",    "__ sve_ld1d_gather(z15, p0, r5, z16);",              "ld1d\t{z15.d}, p0/z, [x5, z16.d, uxtw #3]"],
1719                         ["st1w",    "__ sve_st1w_scatter(z15, p0, r5, z16);",             "st1w\t{z15.s}, p0, [x5, z16.s, uxtw #2]"],
1720                         ["st1d",    "__ sve_st1d_scatter(z15, p0, r5, z16);",             "st1d\t{z15.d}, p0, [x5, z16.d, uxtw #3]"],
1721                         ["and",     "__ sve_and(p0, p1, p2, p3);",                        "and\tp0.b, p1/z, p2.b, p3.b"],
1722                         ["ands",    "__ sve_ands(p4, p5, p6, p0);",                       "ands\tp4.b, p5/z, p6.b, p0.b"],
1723                         ["eor",     "__ sve_eor(p0, p1, p2, p3);",                        "eor\tp0.b, p1/z, p2.b, p3.b"],
1724                         ["eors",    "__ sve_eors(p5, p6, p0, p1);",                       "eors\tp5.b, p6/z, p0.b, p1.b"],
1725                         ["orr",     "__ sve_orr(p0, p1, p2, p3);",                        "orr\tp0.b, p1/z, p2.b, p3.b"],
1726                         ["orrs",    "__ sve_orrs(p9, p1, p4, p5);",                       "orrs\tp9.b, p1/z, p4.b, p5.b"],
1727                         ["bic",     "__ sve_bic(p10, p7, p9, p11);",                      "bic\tp10.b, p7/z, p9.b, p11.b"],
1728                         ["ptest",   "__ sve_ptest(p7, p1);",                              "ptest\tp7, p1.b"],
1729                         ["ptrue",   "__ sve_ptrue(p1, __ B);",                            "ptrue\tp1.b"],
1730                         ["ptrue",   "__ sve_ptrue(p1, __ B, 0b00001);",                   "ptrue\tp1.b, vl1"],
1731                         ["ptrue",   "__ sve_ptrue(p1, __ B, 0b00101);",                   "ptrue\tp1.b, vl5"],
1732                         ["ptrue",   "__ sve_ptrue(p1, __ B, 0b01001);",                   "ptrue\tp1.b, vl16"],
1733                         ["ptrue",   "__ sve_ptrue(p1, __ B, 0b01101);",                   "ptrue\tp1.b, vl256"],
1734                         ["ptrue",   "__ sve_ptrue(p2, __ H);",                            "ptrue\tp2.h"],
1735                         ["ptrue",   "__ sve_ptrue(p2, __ H, 0b00010);",                   "ptrue\tp2.h, vl2"],
1736                         ["ptrue",   "__ sve_ptrue(p2, __ H, 0b00110);",                   "ptrue\tp2.h, vl6"],
1737                         ["ptrue",   "__ sve_ptrue(p2, __ H, 0b01010);",                   "ptrue\tp2.h, vl32"],
1738                         ["ptrue",   "__ sve_ptrue(p3, __ S);",                            "ptrue\tp3.s"],
1739                         ["ptrue",   "__ sve_ptrue(p3, __ S, 0b00011);",                   "ptrue\tp3.s, vl3"],
1740                         ["ptrue",   "__ sve_ptrue(p3, __ S, 0b00111);",                   "ptrue\tp3.s, vl7"],
1741                         ["ptrue",   "__ sve_ptrue(p3, __ S, 0b01011);",                   "ptrue\tp3.s, vl64"],
1742                         ["ptrue",   "__ sve_ptrue(p4, __ D);",                            "ptrue\tp4.d"],
1743                         ["ptrue",   "__ sve_ptrue(p4, __ D, 0b00100);",                   "ptrue\tp4.d, vl4"],
1744                         ["ptrue",   "__ sve_ptrue(p4, __ D, 0b01000);",                   "ptrue\tp4.d, vl8"],
1745                         ["ptrue",   "__ sve_ptrue(p4, __ D, 0b01100);",                   "ptrue\tp4.d, vl128"],
1746                         ["pfalse",  "__ sve_pfalse(p7);",                                 "pfalse\tp7.b"],
1747                         ["uzp1",    "__ sve_uzp1(p0, __ B, p0, p1);",                     "uzp1\tp0.b, p0.b, p1.b"],
1748                         ["uzp1",    "__ sve_uzp1(p0, __ H, p0, p1);",                     "uzp1\tp0.h, p0.h, p1.h"],
1749                         ["uzp1",    "__ sve_uzp1(p0, __ S, p0, p1);",                     "uzp1\tp0.s, p0.s, p1.s"],
1750                         ["uzp1",    "__ sve_uzp1(p0, __ D, p0, p1);",                     "uzp1\tp0.d, p0.d, p1.d"],
1751                         ["uzp2",    "__ sve_uzp2(p0, __ B, p0, p1);",                     "uzp2\tp0.b, p0.b, p1.b"],
1752                         ["uzp2",    "__ sve_uzp2(p0, __ H, p0, p1);",                     "uzp2\tp0.h, p0.h, p1.h"],
1753                         ["uzp2",    "__ sve_uzp2(p0, __ S, p0, p1);",                     "uzp2\tp0.s, p0.s, p1.s"],
1754                         ["uzp2",    "__ sve_uzp2(p0, __ D, p0, p1);",                     "uzp2\tp0.d, p0.d, p1.d"],
1755                         ["punpklo", "__ sve_punpklo(p1, p0);",                            "punpklo\tp1.h, p0.b"],
1756                         ["punpkhi", "__ sve_punpkhi(p1, p0);",                            "punpkhi\tp1.h, p0.b"],
1757                         ["compact", "__ sve_compact(z16, __ S, z16, p1);",                "compact\tz16.s, p1, z16.s"],
1758                         ["compact", "__ sve_compact(z16, __ D, z16, p1);",                "compact\tz16.d, p1, z16.d"],
1759 ])
1760 
1761 print "\n// FloatImmediateOp"
1762 for float in ("2.0", "2.125", "4.0", "4.25", "8.0", "8.5", "16.0", "17.0", "0.125",
1763               "0.1328125", "0.25", "0.265625", "0.5", "0.53125", "1.0", "1.0625",
1764               "-2.0", "-2.125", "-4.0", "-4.25", "-8.0", "-8.5", "-16.0", "-17.0",
1765               "-0.125", "-0.1328125", "-0.25", "-0.265625", "-0.5", "-0.53125", "-1.0", "-1.0625"):
1766     astr = "fmov d0, #" + float
1767     cstr = "__ fmovd(v0, " + float + ");"
1768     print "    %-50s //\t%s" % (cstr, astr)
1769     outfile.write("\t" + astr + "\n")
1770 
1771 # ARMv8.1A
1772 for size in ("x", "w"):
1773     for suffix in ("", "a", "al", "l"):
1774         generate(LSEOp, [["swp", "swp", size, suffix],
1775                          ["ldadd", "ldadd", size, suffix],
1776                          ["ldbic", "ldclr", size, suffix],
1777                          ["ldeor", "ldeor", size, suffix],
1778                          ["ldorr", "ldset", size, suffix],
1779                          ["ldsmin", "ldsmin", size, suffix],
1780                          ["ldsmax", "ldsmax", size, suffix],
1781                          ["ldumin", "ldumin", size, suffix],
1782                          ["ldumax", "ldumax", size, suffix]]);
1783 
1784 # ARMv8.2A
1785 generate(SHA3SIMDOp, ["bcax", "eor3", "rax1", "xar"])
1786 
1787 generate(SHA512SIMDOp, ["sha512h", "sha512h2", "sha512su0", "sha512su1"])
1788 
1789 for i in range(6):
1790     generate(SVEBinaryImmOp, ["add", "sub", "and", "eor", "orr"])
1791 
1792 generate(SVEVectorOp, [["add", "ZZZ"],
1793                        ["sub", "ZZZ"],
1794                        ["fadd", "ZZZ"],
1795                        ["fmul", "ZZZ"],
1796                        ["fsub", "ZZZ"],
1797                        ["abs", "ZPZ", "m"],
1798                        ["add", "ZPZ", "m", "dn"],
1799                        ["and", "ZPZ", "m", "dn"],
1800                        ["asr", "ZPZ", "m", "dn"],
1801                        ["cnt", "ZPZ", "m"],
1802                        ["eor", "ZPZ", "m", "dn"],
1803                        ["lsl", "ZPZ", "m", "dn"],
1804                        ["lsr", "ZPZ", "m", "dn"],
1805                        ["mul", "ZPZ", "m", "dn"],
1806                        ["neg", "ZPZ", "m"],
1807                        ["not", "ZPZ", "m"],
1808                        ["orr", "ZPZ", "m", "dn"],
1809                        ["smax", "ZPZ", "m", "dn"],
1810                        ["smin", "ZPZ", "m", "dn"],
1811                        ["sub", "ZPZ", "m", "dn"],
1812                        ["fabs", "ZPZ", "m"],
1813                        ["fadd", "ZPZ", "m", "dn"],
1814                        ["fdiv", "ZPZ", "m", "dn"],
1815                        ["fmax", "ZPZ", "m", "dn"],
1816                        ["fmin", "ZPZ", "m", "dn"],
1817                        ["fmul", "ZPZ", "m", "dn"],
1818                        ["fneg", "ZPZ", "m"],
1819                        ["frintm", "ZPZ", "m"],
1820                        ["frintn", "ZPZ", "m"],
1821                        ["frintp", "ZPZ", "m"],
1822                        ["fsqrt", "ZPZ", "m"],
1823                        ["fsub", "ZPZ", "m", "dn"],
1824                        ["fmad", "ZPZZ", "m"],
1825                        ["fmla", "ZPZZ", "m"],
1826                        ["fmls", "ZPZZ", "m"],
1827                        ["fnmla", "ZPZZ", "m"],
1828                        ["fnmls", "ZPZZ", "m"],
1829                        ["mla", "ZPZZ", "m"],
1830                        ["mls", "ZPZZ", "m"],
1831                        ["and", "ZZZ"],
1832                        ["eor", "ZZZ"],
1833                        ["orr", "ZZZ"],
1834                        ["bic", "ZZZ"],
1835                        ["uzp1", "ZZZ"],
1836                        ["uzp2", "ZZZ"],
1837                       ])
1838 
1839 generate(SVEReductionOp, [["andv", 0], ["orv", 0], ["eorv", 0], ["smaxv", 0], ["sminv", 0],
1840                           ["fminv", 2], ["fmaxv", 2], ["fadda", 2], ["uaddv", 0]])
1841 
1842 print "\n    __ bind(forth);"
1843 outfile.write("forth:\n")
1844 
1845 outfile.close()
1846 
1847 # compile for sve with 8.2 and sha3 because of SHA3 crypto extension.
1848 subprocess.check_call([AARCH64_AS, "-march=armv8.2-a+sha3+sve", "aarch64ops.s", "-o", "aarch64ops.o"])
1849 
1850 print
1851 print "/*"
1852 print "*/"
1853 
1854 subprocess.check_call([AARCH64_OBJCOPY, "-O", "binary", "-j", ".text", "aarch64ops.o", "aarch64ops.bin"])
1855 
1856 infile = open("aarch64ops.bin", "r")
1857 bytes = bytearray(infile.read())
1858 
1859 print
1860 print "  static const unsigned int insns[] ="
1861 print "  {"
1862 
1863 i = 0
1864 while i < len(bytes):
1865      print "    0x%02x%02x%02x%02x," % (bytes[i+3], bytes[i+2], bytes[i+1], bytes[i]),
1866      i += 4
1867      if i%16 == 0:
1868           print
1869 print
1870 print "  };"
1871 print "// END  Generated code -- do not edit"
1872 
1873 infile.close()
1874 
1875 for f in ["aarch64ops.s", "aarch64ops.o", "aarch64ops.bin"]:
1876     os.remove(f)