1 // BEGIN  Generated code -- do not edit
   2 // Generated by aarch64-asmtest.py
   3     Label back, forth;
   4     __ bind(back);
   5 
   6 // ArithOp
   7     __ add(r26, r23, r13, Assembler::LSL, 32);         //       add     x26, x23, x13, LSL #32
   8     __ sub(r12, r24, r9, Assembler::LSR, 37);          //       sub     x12, x24, x9, LSR #37
   9     __ adds(r28, r15, r8, Assembler::ASR, 39);         //       adds    x28, x15, x8, ASR #39
  10     __ subs(r7, r28, r30, Assembler::ASR, 57);         //       subs    x7, x28, x30, ASR #57
  11     __ addw(r9, r22, r27, Assembler::ASR, 15);         //       add     w9, w22, w27, ASR #15
  12     __ subw(r3, r13, r17, Assembler::ASR, 30);         //       sub     w3, w13, w17, ASR #30
  13     __ addsw(r14, r26, r8, Assembler::ASR, 17);        //       adds    w14, w26, w8, ASR #17
  14     __ subsw(r0, r22, r12, Assembler::ASR, 21);        //       subs    w0, w22, w12, ASR #21
  15     __ andr(r0, r15, r26, Assembler::LSL, 20);         //       and     x0, x15, x26, LSL #20
  16     __ orr(r26, r5, r17, Assembler::LSL, 61);          //       orr     x26, x5, x17, LSL #61
  17     __ eor(r24, r13, r2, Assembler::LSL, 32);          //       eor     x24, x13, x2, LSL #32
  18     __ ands(r28, r3, r17, Assembler::ASR, 35);         //       ands    x28, x3, x17, ASR #35
  19     __ andw(r25, r16, r29, Assembler::LSR, 18);        //       and     w25, w16, w29, LSR #18
  20     __ orrw(r13, r17, r11, Assembler::LSR, 9);         //       orr     w13, w17, w11, LSR #9
  21     __ eorw(r5, r5, r17, Assembler::LSR, 15);          //       eor     w5, w5, w17, LSR #15
  22     __ andsw(r2, r23, r27, Assembler::ASR, 26);        //       ands    w2, w23, w27, ASR #26
  23     __ bic(r27, r28, r16, Assembler::LSR, 45);         //       bic     x27, x28, x16, LSR #45
  24     __ orn(r8, r25, r26, Assembler::ASR, 37);          //       orn     x8, x25, x26, ASR #37
  25     __ eon(r29, r17, r13, Assembler::LSR, 63);         //       eon     x29, x17, x13, LSR #63
  26     __ bics(r28, r24, r2, Assembler::LSR, 31);         //       bics    x28, x24, x2, LSR #31
  27     __ bicw(r19, r26, r7, Assembler::ASR, 3);          //       bic     w19, w26, w7, ASR #3
  28     __ ornw(r6, r24, r10, Assembler::ASR, 3);          //       orn     w6, w24, w10, ASR #3
  29     __ eonw(r4, r21, r1, Assembler::LSR, 29);          //       eon     w4, w21, w1, LSR #29
  30     __ bicsw(r16, r21, r0, Assembler::LSR, 19);        //       bics    w16, w21, w0, LSR #19
  31 
  32 // AddSubImmOp
  33     __ addw(r17, r12, 379u);                           //       add     w17, w12, #379
  34     __ addsw(r30, r1, 22u);                            //       adds    w30, w1, #22
  35     __ subw(r29, r5, 126u);                            //       sub     w29, w5, #126
  36     __ subsw(r6, r24, 960u);                           //       subs    w6, w24, #960
  37     __ add(r0, r13, 104u);                             //       add     x0, x13, #104
  38     __ adds(r8, r6, 663u);                             //       adds    x8, x6, #663
  39     __ sub(r10, r5, 516u);                             //       sub     x10, x5, #516
  40     __ subs(r1, r3, 1012u);                            //       subs    x1, x3, #1012
  41 
  42 // LogicalImmOp
  43     __ andw(r6, r11, 4294049777ull);                   //       and     w6, w11, #0xfff1fff1
  44     __ orrw(r28, r5, 4294966791ull);                   //       orr     w28, w5, #0xfffffe07
  45     __ eorw(r1, r20, 134217216ull);                    //       eor     w1, w20, #0x7fffe00
  46     __ andsw(r7, r17, 1048576ull);                     //       ands    w7, w17, #0x100000
  47     __ andr(r14, r12, 9223372036854775808ull);         //       and     x14, x12, #0x8000000000000000
  48     __ orr(r9, r11, 562675075514368ull);               //       orr     x9, x11, #0x1ffc000000000
  49     __ eor(r17, r0, 18014398509481728ull);             //       eor     x17, x0, #0x3fffffffffff00
  50     __ ands(r1, r8, 18446744073705357315ull);          //       ands    x1, x8, #0xffffffffffc00003
  51 
  52 // AbsOp
  53     __ b(__ pc());                                     //       b       .
  54     __ b(back);                                        //       b       back
  55     __ b(forth);                                       //       b       forth
  56     __ bl(__ pc());                                    //       bl      .
  57     __ bl(back);                                       //       bl      back
  58     __ bl(forth);                                      //       bl      forth
  59 
  60 // RegAndAbsOp
  61     __ cbzw(r10, __ pc());                             //       cbz     w10, .
  62     __ cbzw(r10, back);                                //       cbz     w10, back
  63     __ cbzw(r10, forth);                               //       cbz     w10, forth
  64     __ cbnzw(r8, __ pc());                             //       cbnz    w8, .
  65     __ cbnzw(r8, back);                                //       cbnz    w8, back
  66     __ cbnzw(r8, forth);                               //       cbnz    w8, forth
  67     __ cbz(r11, __ pc());                              //       cbz     x11, .
  68     __ cbz(r11, back);                                 //       cbz     x11, back
  69     __ cbz(r11, forth);                                //       cbz     x11, forth
  70     __ cbnz(r29, __ pc());                             //       cbnz    x29, .
  71     __ cbnz(r29, back);                                //       cbnz    x29, back
  72     __ cbnz(r29, forth);                               //       cbnz    x29, forth
  73     __ adr(r19, __ pc());                              //       adr     x19, .
  74     __ adr(r19, back);                                 //       adr     x19, back
  75     __ adr(r19, forth);                                //       adr     x19, forth
  76     __ _adrp(r19, __ pc());                            //       adrp    x19, .
  77 
  78 // RegImmAbsOp
  79     __ tbz(r22, 6, __ pc());                           //       tbz     x22, #6, .
  80     __ tbz(r22, 6, back);                              //       tbz     x22, #6, back
  81     __ tbz(r22, 6, forth);                             //       tbz     x22, #6, forth
  82     __ tbnz(r12, 11, __ pc());                         //       tbnz    x12, #11, .
  83     __ tbnz(r12, 11, back);                            //       tbnz    x12, #11, back
  84     __ tbnz(r12, 11, forth);                           //       tbnz    x12, #11, forth
  85 
  86 // MoveWideImmOp
  87     __ movnw(r0, 6301, 0);                             //       movn    w0, #6301, lsl 0
  88     __ movzw(r7, 20886, 0);                            //       movz    w7, #20886, lsl 0
  89     __ movkw(r27, 18617, 0);                           //       movk    w27, #18617, lsl 0
  90     __ movn(r12, 22998, 16);                           //       movn    x12, #22998, lsl 16
  91     __ movz(r20, 1532, 16);                            //       movz    x20, #1532, lsl 16
  92     __ movk(r8, 5167, 32);                             //       movk    x8, #5167, lsl 32
  93 
  94 // BitfieldOp
  95     __ sbfm(r15, r17, 24, 28);                         //       sbfm    x15, x17, #24, #28
  96     __ bfmw(r15, r9, 14, 25);                          //       bfm     w15, w9, #14, #25
  97     __ ubfmw(r27, r25, 6, 31);                         //       ubfm    w27, w25, #6, #31
  98     __ sbfm(r19, r2, 23, 31);                          //       sbfm    x19, x2, #23, #31
  99     __ bfm(r12, r21, 10, 6);                           //       bfm     x12, x21, #10, #6
 100     __ ubfm(r22, r0, 26, 16);                          //       ubfm    x22, x0, #26, #16
 101 
 102 // ExtractOp
 103     __ extrw(r3, r3, r20, 27);                         //       extr    w3, w3, w20, #27
 104     __ extr(r8, r30, r3, 54);                          //       extr    x8, x30, x3, #54
 105 
 106 // CondBranchOp
 107     __ br(Assembler::EQ, __ pc());                     //       b.EQ    .
 108     __ br(Assembler::EQ, back);                        //       b.EQ    back
 109     __ br(Assembler::EQ, forth);                       //       b.EQ    forth
 110     __ br(Assembler::NE, __ pc());                     //       b.NE    .
 111     __ br(Assembler::NE, back);                        //       b.NE    back
 112     __ br(Assembler::NE, forth);                       //       b.NE    forth
 113     __ br(Assembler::HS, __ pc());                     //       b.HS    .
 114     __ br(Assembler::HS, back);                        //       b.HS    back
 115     __ br(Assembler::HS, forth);                       //       b.HS    forth
 116     __ br(Assembler::CS, __ pc());                     //       b.CS    .
 117     __ br(Assembler::CS, back);                        //       b.CS    back
 118     __ br(Assembler::CS, forth);                       //       b.CS    forth
 119     __ br(Assembler::LO, __ pc());                     //       b.LO    .
 120     __ br(Assembler::LO, back);                        //       b.LO    back
 121     __ br(Assembler::LO, forth);                       //       b.LO    forth
 122     __ br(Assembler::CC, __ pc());                     //       b.CC    .
 123     __ br(Assembler::CC, back);                        //       b.CC    back
 124     __ br(Assembler::CC, forth);                       //       b.CC    forth
 125     __ br(Assembler::MI, __ pc());                     //       b.MI    .
 126     __ br(Assembler::MI, back);                        //       b.MI    back
 127     __ br(Assembler::MI, forth);                       //       b.MI    forth
 128     __ br(Assembler::PL, __ pc());                     //       b.PL    .
 129     __ br(Assembler::PL, back);                        //       b.PL    back
 130     __ br(Assembler::PL, forth);                       //       b.PL    forth
 131     __ br(Assembler::VS, __ pc());                     //       b.VS    .
 132     __ br(Assembler::VS, back);                        //       b.VS    back
 133     __ br(Assembler::VS, forth);                       //       b.VS    forth
 134     __ br(Assembler::VC, __ pc());                     //       b.VC    .
 135     __ br(Assembler::VC, back);                        //       b.VC    back
 136     __ br(Assembler::VC, forth);                       //       b.VC    forth
 137     __ br(Assembler::HI, __ pc());                     //       b.HI    .
 138     __ br(Assembler::HI, back);                        //       b.HI    back
 139     __ br(Assembler::HI, forth);                       //       b.HI    forth
 140     __ br(Assembler::LS, __ pc());                     //       b.LS    .
 141     __ br(Assembler::LS, back);                        //       b.LS    back
 142     __ br(Assembler::LS, forth);                       //       b.LS    forth
 143     __ br(Assembler::GE, __ pc());                     //       b.GE    .
 144     __ br(Assembler::GE, back);                        //       b.GE    back
 145     __ br(Assembler::GE, forth);                       //       b.GE    forth
 146     __ br(Assembler::LT, __ pc());                     //       b.LT    .
 147     __ br(Assembler::LT, back);                        //       b.LT    back
 148     __ br(Assembler::LT, forth);                       //       b.LT    forth
 149     __ br(Assembler::GT, __ pc());                     //       b.GT    .
 150     __ br(Assembler::GT, back);                        //       b.GT    back
 151     __ br(Assembler::GT, forth);                       //       b.GT    forth
 152     __ br(Assembler::LE, __ pc());                     //       b.LE    .
 153     __ br(Assembler::LE, back);                        //       b.LE    back
 154     __ br(Assembler::LE, forth);                       //       b.LE    forth
 155     __ br(Assembler::AL, __ pc());                     //       b.AL    .
 156     __ br(Assembler::AL, back);                        //       b.AL    back
 157     __ br(Assembler::AL, forth);                       //       b.AL    forth
 158     __ br(Assembler::NV, __ pc());                     //       b.NV    .
 159     __ br(Assembler::NV, back);                        //       b.NV    back
 160     __ br(Assembler::NV, forth);                       //       b.NV    forth
 161 
 162 // ImmOp
 163     __ svc(12999);                                     //       svc     #12999
 164     __ hvc(2665);                                      //       hvc     #2665
 165     __ smc(9002);                                      //       smc     #9002
 166     __ brk(14843);                                     //       brk     #14843
 167     __ hlt(25964);                                     //       hlt     #25964
 168 
 169 // Op
 170     __ nop();                                          //       nop
 171     __ eret();                                         //       eret
 172     __ drps();                                         //       drps
 173     __ isb();                                          //       isb
 174 
 175 // SystemOp
 176     __ dsb(Assembler::ST);                             //       dsb     ST
 177     __ dmb(Assembler::OSHST);                          //       dmb     OSHST
 178 
 179 // OneRegOp
 180     __ br(r16);                                        //       br      x16
 181     __ blr(r20);                                       //       blr     x20
 182 
 183 // LoadStoreExclusiveOp
 184     __ stxr(r10, r27, r8);                             //       stxr    w10, x27, [x8]
 185     __ stlxr(r0, r1, r21);                             //       stlxr   w0, x1, [x21]
 186     __ ldxr(r17, r29);                                 //       ldxr    x17, [x29]
 187     __ ldaxr(r29, r28);                                //       ldaxr   x29, [x28]
 188     __ stlr(r1, r23);                                  //       stlr    x1, [x23]
 189     __ ldar(r21, r20);                                 //       ldar    x21, [x20]
 190 
 191 // LoadStoreExclusiveOp
 192     __ stxrw(r22, r27, r19);                           //       stxr    w22, w27, [x19]
 193     __ stlxrw(r11, r16, r6);                           //       stlxr   w11, w16, [x6]
 194     __ ldxrw(r17, r0);                                 //       ldxr    w17, [x0]
 195     __ ldaxrw(r4, r10);                                //       ldaxr   w4, [x10]
 196     __ stlrw(r24, r22);                                //       stlr    w24, [x22]
 197     __ ldarw(r10, r19);                                //       ldar    w10, [x19]
 198 
 199 // LoadStoreExclusiveOp
 200     __ stxrh(r1, r5, r30);                             //       stxrh   w1, w5, [x30]
 201     __ stlxrh(r8, r12, r17);                           //       stlxrh  w8, w12, [x17]
 202     __ ldxrh(r9, r14);                                 //       ldxrh   w9, [x14]
 203     __ ldaxrh(r7, r1);                                 //       ldaxrh  w7, [x1]
 204     __ stlrh(r5, r16);                                 //       stlrh   w5, [x16]
 205     __ ldarh(r2, r12);                                 //       ldarh   w2, [x12]
 206 
 207 // LoadStoreExclusiveOp
 208     __ stxrb(r10, r12, r3);                            //       stxrb   w10, w12, [x3]
 209     __ stlxrb(r28, r14, r26);                          //       stlxrb  w28, w14, [x26]
 210     __ ldxrb(r30, r10);                                //       ldxrb   w30, [x10]
 211     __ ldaxrb(r14, r21);                               //       ldaxrb  w14, [x21]
 212     __ stlrb(r13, r9);                                 //       stlrb   w13, [x9]
 213     __ ldarb(r22, r27);                                //       ldarb   w22, [x27]
 214 
 215 // LoadStoreExclusiveOp
 216     __ ldxp(r28, r19, r11);                            //       ldxp    x28, x19, [x11]
 217     __ ldaxp(r30, r19, r2);                            //       ldaxp   x30, x19, [x2]
 218     __ stxp(r2, r23, r1, r0);                          //       stxp    w2, x23, x1, [x0]
 219     __ stlxp(r12, r16, r13, r15);                      //       stlxp   w12, x16, x13, [x15]
 220 
 221 // LoadStoreExclusiveOp
 222     __ ldxpw(r17, r21, r13);                           //       ldxp    w17, w21, [x13]
 223     __ ldaxpw(r11, r30, r8);                           //       ldaxp   w11, w30, [x8]
 224     __ stxpw(r24, r13, r11, r1);                       //       stxp    w24, w13, w11, [x1]
 225     __ stlxpw(r26, r21, r27, r13);                     //       stlxp   w26, w21, w27, [x13]
 226 
 227 // base_plus_unscaled_offset
 228 // LoadStoreOp
 229     __ str(r11, Address(r20, -103));                   //       str     x11, [x20, -103]
 230     __ strw(r28, Address(r16, 62));                    //       str     w28, [x16, 62]
 231     __ strb(r27, Address(r9, -9));                     //       strb    w27, [x9, -9]
 232     __ strh(r2, Address(r25, -50));                    //       strh    w2, [x25, -50]
 233     __ ldr(r4, Address(r2, -241));                     //       ldr     x4, [x2, -241]
 234     __ ldrw(r30, Address(r20, -31));                   //       ldr     w30, [x20, -31]
 235     __ ldrb(r17, Address(r23, -23));                   //       ldrb    w17, [x23, -23]
 236     __ ldrh(r29, Address(r26, -1));                    //       ldrh    w29, [x26, -1]
 237     __ ldrsb(r1, Address(r9, 6));                      //       ldrsb   x1, [x9, 6]
 238     __ ldrsh(r11, Address(r12, 19));                   //       ldrsh   x11, [x12, 19]
 239     __ ldrshw(r11, Address(r1, -50));                  //       ldrsh   w11, [x1, -50]
 240     __ ldrsw(r19, Address(r24, 41));                   //       ldrsw   x19, [x24, 41]
 241     __ ldrd(v24, Address(r24, 95));                    //       ldr     d24, [x24, 95]
 242     __ ldrs(v15, Address(r5, -43));                    //       ldr     s15, [x5, -43]
 243     __ strd(v21, Address(r27, 1));                     //       str     d21, [x27, 1]
 244     __ strs(v23, Address(r13, -107));                  //       str     s23, [x13, -107]
 245 
 246 // pre
 247 // LoadStoreOp
 248     __ str(r10, Address(__ pre(r0, 8)));               //       str     x10, [x0, 8]!
 249     __ strw(r3, Address(__ pre(r0, 29)));              //       str     w3, [x0, 29]!
 250     __ strb(r10, Address(__ pre(r14, 9)));             //       strb    w10, [x14, 9]!
 251     __ strh(r29, Address(__ pre(r25, -3)));            //       strh    w29, [x25, -3]!
 252     __ ldr(r12, Address(__ pre(r16, -144)));           //       ldr     x12, [x16, -144]!
 253     __ ldrw(r12, Address(__ pre(r22, -6)));            //       ldr     w12, [x22, -6]!
 254     __ ldrb(r13, Address(__ pre(r11, -10)));           //       ldrb    w13, [x11, -10]!
 255     __ ldrh(r0, Address(__ pre(r21, -21)));            //       ldrh    w0, [x21, -21]!
 256     __ ldrsb(r23, Address(__ pre(r6, 4)));             //       ldrsb   x23, [x6, 4]!
 257     __ ldrsh(r3, Address(__ pre(r7, -53)));            //       ldrsh   x3, [x7, -53]!
 258     __ ldrshw(r28, Address(__ pre(r4, -7)));           //       ldrsh   w28, [x4, -7]!
 259     __ ldrsw(r24, Address(__ pre(r8, -18)));           //       ldrsw   x24, [x8, -18]!
 260     __ ldrd(v14, Address(__ pre(r11, 12)));            //       ldr     d14, [x11, 12]!
 261     __ ldrs(v19, Address(__ pre(r12, -67)));           //       ldr     s19, [x12, -67]!
 262     __ strd(v20, Address(__ pre(r0, -253)));           //       str     d20, [x0, -253]!
 263     __ strs(v8, Address(__ pre(r0, 64)));              //       str     s8, [x0, 64]!
 264 
 265 // post
 266 // LoadStoreOp
 267     __ str(r3, Address(__ post(r28, -94)));            //       str     x3, [x28], -94
 268     __ strw(r11, Address(__ post(r7, -54)));           //       str     w11, [x7], -54
 269     __ strb(r27, Address(__ post(r10, -24)));          //       strb    w27, [x10], -24
 270     __ strh(r6, Address(__ post(r7, 27)));             //       strh    w6, [x7], 27
 271     __ ldr(r13, Address(__ post(r10, -202)));          //       ldr     x13, [x10], -202
 272     __ ldrw(r15, Address(__ post(r5, -41)));           //       ldr     w15, [x5], -41
 273     __ ldrb(r2, Address(__ post(r13, 9)));             //       ldrb    w2, [x13], 9
 274     __ ldrh(r28, Address(__ post(r13, -20)));          //       ldrh    w28, [x13], -20
 275     __ ldrsb(r9, Address(__ post(r13, -31)));          //       ldrsb   x9, [x13], -31
 276     __ ldrsh(r3, Address(__ post(r24, -36)));          //       ldrsh   x3, [x24], -36
 277     __ ldrshw(r20, Address(__ post(r3, 6)));           //       ldrsh   w20, [x3], 6
 278     __ ldrsw(r7, Address(__ post(r19, -1)));           //       ldrsw   x7, [x19], -1
 279     __ ldrd(v30, Address(__ post(r8, -130)));          //       ldr     d30, [x8], -130
 280     __ ldrs(v25, Address(__ post(r15, 21)));           //       ldr     s25, [x15], 21
 281     __ strd(v14, Address(__ post(r23, 90)));           //       str     d14, [x23], 90
 282     __ strs(v8, Address(__ post(r0, -33)));            //       str     s8, [x0], -33
 283 
 284 // base_plus_reg
 285 // LoadStoreOp
 286     __ str(r10, Address(r17, r21, Address::sxtw(3)));  //       str     x10, [x17, w21, sxtw #3]
 287     __ strw(r4, Address(r13, r22, Address::sxtw(2)));  //       str     w4, [x13, w22, sxtw #2]
 288     __ strb(r13, Address(r0, r19, Address::uxtw(0)));  //       strb    w13, [x0, w19, uxtw #0]
 289     __ strh(r12, Address(r27, r6, Address::sxtw(0)));  //       strh    w12, [x27, w6, sxtw #0]
 290     __ ldr(r0, Address(r8, r16, Address::lsl(0)));     //       ldr     x0, [x8, x16, lsl #0]
 291     __ ldrw(r0, Address(r4, r26, Address::sxtx(0)));   //       ldr     w0, [x4, x26, sxtx #0]
 292     __ ldrb(r14, Address(r25, r5, Address::sxtw(0)));  //       ldrb    w14, [x25, w5, sxtw #0]
 293     __ ldrh(r9, Address(r4, r17, Address::uxtw(0)));   //       ldrh    w9, [x4, w17, uxtw #0]
 294     __ ldrsb(r27, Address(r4, r7, Address::lsl(0)));   //       ldrsb   x27, [x4, x7, lsl #0]
 295     __ ldrsh(r15, Address(r17, r30, Address::sxtw(0))); //      ldrsh   x15, [x17, w30, sxtw #0]
 296     __ ldrshw(r16, Address(r0, r22, Address::sxtw(0))); //      ldrsh   w16, [x0, w22, sxtw #0]
 297     __ ldrsw(r22, Address(r10, r30, Address::sxtx(2))); //      ldrsw   x22, [x10, x30, sxtx #2]
 298     __ ldrd(v29, Address(r21, r10, Address::sxtx(3))); //       ldr     d29, [x21, x10, sxtx #3]
 299     __ ldrs(v3, Address(r11, r19, Address::uxtw(0)));  //       ldr     s3, [x11, w19, uxtw #0]
 300     __ strd(v13, Address(r28, r29, Address::uxtw(3))); //       str     d13, [x28, w29, uxtw #3]
 301     __ strs(v23, Address(r29, r5, Address::sxtx(2)));  //       str     s23, [x29, x5, sxtx #2]
 302 
 303 // base_plus_scaled_offset
 304 // LoadStoreOp
 305     __ str(r5, Address(r8, 12600));                    //       str     x5, [x8, 12600]
 306     __ strw(r29, Address(r24, 7880));                  //       str     w29, [x24, 7880]
 307     __ strb(r19, Address(r17, 1566));                  //       strb    w19, [x17, 1566]
 308     __ strh(r13, Address(r19, 3984));                  //       strh    w13, [x19, 3984]
 309     __ ldr(r19, Address(r23, 13632));                  //       ldr     x19, [x23, 13632]
 310     __ ldrw(r23, Address(r29, 6264));                  //       ldr     w23, [x29, 6264]
 311     __ ldrb(r22, Address(r11, 2012));                  //       ldrb    w22, [x11, 2012]
 312     __ ldrh(r3, Address(r10, 3784));                   //       ldrh    w3, [x10, 3784]
 313     __ ldrsb(r8, Address(r16, 1951));                  //       ldrsb   x8, [x16, 1951]
 314     __ ldrsh(r23, Address(r20, 3346));                 //       ldrsh   x23, [x20, 3346]
 315     __ ldrshw(r2, Address(r1, 3994));                  //       ldrsh   w2, [x1, 3994]
 316     __ ldrsw(r4, Address(r17, 7204));                  //       ldrsw   x4, [x17, 7204]
 317     __ ldrd(v20, Address(r27, 14400));                 //       ldr     d20, [x27, 14400]
 318     __ ldrs(v25, Address(r14, 8096));                  //       ldr     s25, [x14, 8096]
 319     __ strd(v26, Address(r10, 15024));                 //       str     d26, [x10, 15024]
 320     __ strs(v9, Address(r3, 6936));                    //       str     s9, [x3, 6936]
 321 
 322 // pcrel
 323 // LoadStoreOp
 324     __ ldr(r27, forth);                                //       ldr     x27, forth
 325     __ ldrw(r11, __ pc());                             //       ldr     w11, .
 326 
 327 // LoadStoreOp
 328     __ prfm(Address(r3, -187));                        //       prfm    PLDL1KEEP, [x3, -187]
 329 
 330 // LoadStoreOp
 331     __ prfm(__ pc());                                  //       prfm    PLDL1KEEP, .
 332 
 333 // LoadStoreOp
 334     __ prfm(Address(r29, r14, Address::lsl(0)));       //       prfm    PLDL1KEEP, [x29, x14, lsl #0]
 335 
 336 // LoadStoreOp
 337     __ prfm(Address(r4, 13312));                       //       prfm    PLDL1KEEP, [x4, 13312]
 338 
 339 // AddSubCarryOp
 340     __ adcw(r21, r1, r7);                              //       adc     w21, w1, w7
 341     __ adcsw(r8, r5, r7);                              //       adcs    w8, w5, w7
 342     __ sbcw(r7, r27, r14);                             //       sbc     w7, w27, w14
 343     __ sbcsw(r27, r4, r17);                            //       sbcs    w27, w4, w17
 344     __ adc(r0, r28, r0);                               //       adc     x0, x28, x0
 345     __ adcs(r12, r24, r30);                            //       adcs    x12, x24, x30
 346     __ sbc(r0, r25, r15);                              //       sbc     x0, x25, x15
 347     __ sbcs(r1, r24, r3);                              //       sbcs    x1, x24, x3
 348 
 349 // AddSubExtendedOp
 350     __ addw(r17, r24, r20, ext::uxtb, 2);              //       add     w17, w24, w20, uxtb #2
 351     __ addsw(r13, r28, r10, ext::uxth, 1);             //       adds    w13, w28, w10, uxth #1
 352     __ sub(r15, r16, r2, ext::sxth, 2);                //       sub     x15, x16, x2, sxth #2
 353     __ subsw(r29, r13, r13, ext::uxth, 2);             //       subs    w29, w13, w13, uxth #2
 354     __ add(r12, r20, r12, ext::sxtw, 3);               //       add     x12, x20, x12, sxtw #3
 355     __ adds(r30, r27, r11, ext::sxtb, 1);              //       adds    x30, x27, x11, sxtb #1
 356     __ sub(r14, r7, r1, ext::sxtw, 2);                 //       sub     x14, x7, x1, sxtw #2
 357     __ subs(r29, r3, r27, ext::sxth, 1);               //       subs    x29, x3, x27, sxth #1
 358 
 359 // ConditionalCompareOp
 360     __ ccmnw(r0, r13, 14u, Assembler::MI);             //       ccmn    w0, w13, #14, MI
 361     __ ccmpw(r22, r17, 6u, Assembler::CC);             //       ccmp    w22, w17, #6, CC
 362     __ ccmn(r17, r30, 14u, Assembler::VS);             //       ccmn    x17, x30, #14, VS
 363     __ ccmp(r10, r19, 12u, Assembler::HI);             //       ccmp    x10, x19, #12, HI
 364 
 365 // ConditionalCompareImmedOp
 366     __ ccmnw(r6, 18, 2, Assembler::LE);                //       ccmn    w6, #18, #2, LE
 367     __ ccmpw(r9, 13, 4, Assembler::HI);                //       ccmp    w9, #13, #4, HI
 368     __ ccmn(r21, 11, 11, Assembler::LO);               //       ccmn    x21, #11, #11, LO
 369     __ ccmp(r4, 13, 2, Assembler::VC);                 //       ccmp    x4, #13, #2, VC
 370 
 371 // ConditionalSelectOp
 372     __ cselw(r12, r2, r22, Assembler::HI);             //       csel    w12, w2, w22, HI
 373     __ csincw(r24, r16, r17, Assembler::HS);           //       csinc   w24, w16, w17, HS
 374     __ csinvw(r6, r7, r16, Assembler::LT);             //       csinv   w6, w7, w16, LT
 375     __ csnegw(r11, r27, r22, Assembler::LS);           //       csneg   w11, w27, w22, LS
 376     __ csel(r10, r3, r29, Assembler::LT);              //       csel    x10, x3, x29, LT
 377     __ csinc(r12, r26, r27, Assembler::CC);            //       csinc   x12, x26, x27, CC
 378     __ csinv(r15, r10, r21, Assembler::GT);            //       csinv   x15, x10, x21, GT
 379     __ csneg(r30, r23, r9, Assembler::GT);             //       csneg   x30, x23, x9, GT
 380 
 381 // TwoRegOp
 382     __ rbitw(r30, r10);                                //       rbit    w30, w10
 383     __ rev16w(r29, r15);                               //       rev16   w29, w15
 384     __ revw(r29, r30);                                 //       rev     w29, w30
 385     __ clzw(r25, r21);                                 //       clz     w25, w21
 386     __ clsw(r4, r0);                                   //       cls     w4, w0
 387     __ rbit(r17, r21);                                 //       rbit    x17, x21
 388     __ rev16(r29, r16);                                //       rev16   x29, x16
 389     __ rev32(r21, r20);                                //       rev32   x21, x20
 390     __ rev(r6, r19);                                   //       rev     x6, x19
 391     __ clz(r30, r3);                                   //       clz     x30, x3
 392     __ cls(r21, r19);                                  //       cls     x21, x19
 393 
 394 // ThreeRegOp
 395     __ udivw(r11, r24, r0);                            //       udiv    w11, w24, w0
 396     __ sdivw(r27, r25, r14);                           //       sdiv    w27, w25, w14
 397     __ lslvw(r3, r14, r17);                            //       lslv    w3, w14, w17
 398     __ lsrvw(r7, r15, r24);                            //       lsrv    w7, w15, w24
 399     __ asrvw(r28, r17, r25);                           //       asrv    w28, w17, w25
 400     __ rorvw(r2, r26, r28);                            //       rorv    w2, w26, w28
 401     __ udiv(r5, r25, r26);                             //       udiv    x5, x25, x26
 402     __ sdiv(r27, r16, r17);                            //       sdiv    x27, x16, x17
 403     __ lslv(r6, r21, r12);                             //       lslv    x6, x21, x12
 404     __ lsrv(r0, r4, r12);                              //       lsrv    x0, x4, x12
 405     __ asrv(r27, r17, r28);                            //       asrv    x27, x17, x28
 406     __ rorv(r28, r2, r17);                             //       rorv    x28, x2, x17
 407     __ umulh(r10, r15, r14);                           //       umulh   x10, x15, x14
 408     __ smulh(r14, r3, r25);                            //       smulh   x14, x3, x25
 409 
 410 // FourRegMulOp
 411     __ maddw(r15, r19, r14, r5);                       //       madd    w15, w19, w14, w5
 412     __ msubw(r16, r4, r26, r25);                       //       msub    w16, w4, w26, w25
 413     __ madd(r4, r2, r2, r12);                          //       madd    x4, x2, x2, x12
 414     __ msub(r29, r17, r8, r7);                         //       msub    x29, x17, x8, x7
 415     __ smaddl(r3, r4, r25, r4);                        //       smaddl  x3, w4, w25, x4
 416     __ smsubl(r26, r25, r4, r17);                      //       smsubl  x26, w25, w4, x17
 417     __ umaddl(r0, r26, r17, r23);                      //       umaddl  x0, w26, w17, x23
 418     __ umsubl(r15, r21, r28, r17);                     //       umsubl  x15, w21, w28, x17
 419 
 420 // ThreeRegFloatOp
 421     __ fabds(v27, v10, v3);                            //       fabd    s27, s10, s3
 422     __ fmuls(v0, v7, v25);                             //       fmul    s0, s7, s25
 423     __ fdivs(v9, v6, v15);                             //       fdiv    s9, s6, s15
 424     __ fadds(v29, v15, v10);                           //       fadd    s29, s15, s10
 425     __ fsubs(v2, v17, v7);                             //       fsub    s2, s17, s7
 426     __ fabdd(v11, v11, v23);                           //       fabd    d11, d11, d23
 427     __ fmuld(v7, v29, v23);                            //       fmul    d7, d29, d23
 428     __ fdivd(v14, v27, v11);                           //       fdiv    d14, d27, d11
 429     __ faddd(v11, v4, v24);                            //       fadd    d11, d4, d24
 430     __ fsubd(v12, v15, v14);                           //       fsub    d12, d15, d14
 431 
 432 // FourRegFloatOp
 433     __ fmadds(v20, v11, v28, v13);                     //       fmadd   s20, s11, s28, s13
 434     __ fmsubs(v11, v12, v23, v30);                     //       fmsub   s11, s12, s23, s30
 435     __ fnmadds(v26, v14, v9, v13);                     //       fnmadd  s26, s14, s9, s13
 436     __ fnmadds(v10, v7, v5, v29);                      //       fnmadd  s10, s7, s5, s29
 437     __ fmaddd(v15, v3, v11, v12);                      //       fmadd   d15, d3, d11, d12
 438     __ fmsubd(v15, v30, v30, v17);                     //       fmsub   d15, d30, d30, d17
 439     __ fnmaddd(v19, v20, v15, v15);                    //       fnmadd  d19, d20, d15, d15
 440     __ fnmaddd(v9, v21, v2, v9);                       //       fnmadd  d9, d21, d2, d9
 441 
 442 // TwoRegFloatOp
 443     __ fmovs(v27, v7);                                 //       fmov    s27, s7
 444     __ fabss(v29, v30);                                //       fabs    s29, s30
 445     __ fnegs(v17, v1);                                 //       fneg    s17, s1
 446     __ fsqrts(v2, v6);                                 //       fsqrt   s2, s6
 447     __ fcvts(v10, v3);                                 //       fcvt    d10, s3
 448     __ fmovd(v24, v11);                                //       fmov    d24, d11
 449     __ fabsd(v7, v1);                                  //       fabs    d7, d1
 450     __ fnegd(v11, v0);                                 //       fneg    d11, d0
 451     __ fsqrtd(v3, v17);                                //       fsqrt   d3, d17
 452     __ fcvtd(v28, v6);                                 //       fcvt    s28, d6
 453 
 454 // FloatConvertOp
 455     __ fcvtzsw(r22, v6);                               //       fcvtzs  w22, s6
 456     __ fcvtzs(r0, v27);                                //       fcvtzs  x0, s27
 457     __ fcvtzdw(r26, v2);                               //       fcvtzs  w26, d2
 458     __ fcvtzd(r5, v7);                                 //       fcvtzs  x5, d7
 459     __ scvtfws(v28, r11);                              //       scvtf   s28, w11
 460     __ scvtfs(v25, r13);                               //       scvtf   s25, x13
 461     __ scvtfwd(v11, r23);                              //       scvtf   d11, w23
 462     __ scvtfd(v19, r8);                                //       scvtf   d19, x8
 463     __ fmovs(r17, v21);                                //       fmov    w17, s21
 464     __ fmovd(r25, v20);                                //       fmov    x25, d20
 465     __ fmovs(v19, r17);                                //       fmov    s19, w17
 466     __ fmovd(v2, r29);                                 //       fmov    d2, x29
 467 
 468 // TwoRegFloatOp
 469     __ fcmps(v22, v8);                                 //       fcmp    s22, s8
 470     __ fcmpd(v21, v19);                                //       fcmp    d21, d19
 471     __ fcmps(v20, 0.0);                                //       fcmp    s20, #0.0
 472     __ fcmpd(v11, 0.0);                                //       fcmp    d11, #0.0
 473 
 474 // LoadStorePairOp
 475     __ stpw(r20, r6, Address(r15, -32));               //       stp     w20, w6, [x15, #-32]
 476     __ ldpw(r27, r14, Address(r3, -208));              //       ldp     w27, w14, [x3, #-208]
 477     __ ldpsw(r16, r10, Address(r11, -80));             //       ldpsw   x16, x10, [x11, #-80]
 478     __ stp(r7, r7, Address(r14, 64));                  //       stp     x7, x7, [x14, #64]
 479     __ ldp(r12, r23, Address(r0, 112));                //       ldp     x12, x23, [x0, #112]
 480 
 481 // LoadStorePairOp
 482     __ stpw(r13, r7, Address(__ pre(r6, -80)));        //       stp     w13, w7, [x6, #-80]!
 483     __ ldpw(r30, r15, Address(__ pre(r2, -144)));      //       ldp     w30, w15, [x2, #-144]!
 484     __ ldpsw(r4, r1, Address(__ pre(r27, -144)));      //       ldpsw   x4, x1, [x27, #-144]!
 485     __ stp(r23, r14, Address(__ pre(r11, 64)));        //       stp     x23, x14, [x11, #64]!
 486     __ ldp(r29, r27, Address(__ pre(r21, -192)));      //       ldp     x29, x27, [x21, #-192]!
 487 
 488 // LoadStorePairOp
 489     __ stpw(r22, r5, Address(__ post(r21, -48)));      //       stp     w22, w5, [x21], #-48
 490     __ ldpw(r27, r17, Address(__ post(r6, -32)));      //       ldp     w27, w17, [x6], #-32
 491     __ ldpsw(r16, r5, Address(__ post(r1, -80)));      //       ldpsw   x16, x5, [x1], #-80
 492     __ stp(r13, r20, Address(__ post(r22, -208)));     //       stp     x13, x20, [x22], #-208
 493     __ ldp(r30, r27, Address(__ post(r10, 80)));       //       ldp     x30, x27, [x10], #80
 494 
 495 // LoadStorePairOp
 496     __ stnpw(r5, r17, Address(r11, 16));               //       stnp    w5, w17, [x11, #16]
 497     __ ldnpw(r14, r4, Address(r26, -96));              //       ldnp    w14, w4, [x26, #-96]
 498     __ stnp(r23, r29, Address(r12, 32));               //       stnp    x23, x29, [x12, #32]
 499     __ ldnp(r0, r6, Address(r21, -80));                //       ldnp    x0, x6, [x21, #-80]
 500 
 501 // LdStNEONOp
 502     __ ld1(v15, __ T8B, Address(r26));                 //       ld1     {v15.8B}, [x26]
 503     __ ld1(v23, v24, __ T16B, Address(__ post(r11, 32))); //    ld1     {v23.16B, v24.16B}, [x11], 32
 504     __ ld1(v8, v9, v10, __ T1D, Address(__ post(r23, r7))); //  ld1     {v8.1D, v9.1D, v10.1D}, [x23], x7
 505     __ ld1(v19, v20, v21, v22, __ T8H, Address(__ post(r25, 64))); //   ld1     {v19.8H, v20.8H, v21.8H, v22.8H}, [x25], 64
 506     __ ld1r(v29, __ T8B, Address(r17));                //       ld1r    {v29.8B}, [x17]
 507     __ ld1r(v24, __ T4S, Address(__ post(r23, 4)));    //       ld1r    {v24.4S}, [x23], 4
 508     __ ld1r(v10, __ T1D, Address(__ post(r5, r25)));   //       ld1r    {v10.1D}, [x5], x25
 509     __ ld2(v17, v18, __ T2D, Address(r10));            //       ld2     {v17.2D, v18.2D}, [x10]
 510     __ ld2(v12, v13, __ T4H, Address(__ post(r15, 16))); //     ld2     {v12.4H, v13.4H}, [x15], 16
 511     __ ld2r(v25, v26, __ T16B, Address(r17));          //       ld2r    {v25.16B, v26.16B}, [x17]
 512     __ ld2r(v1, v2, __ T2S, Address(__ post(r30, 8))); //       ld2r    {v1.2S, v2.2S}, [x30], 8
 513     __ ld2r(v16, v17, __ T2D, Address(__ post(r17, r9))); //    ld2r    {v16.2D, v17.2D}, [x17], x9
 514     __ ld3(v25, v26, v27, __ T4S, Address(__ post(r12, r2))); //        ld3     {v25.4S, v26.4S, v27.4S}, [x12], x2
 515     __ ld3(v26, v27, v28, __ T2S, Address(r19));       //       ld3     {v26.2S, v27.2S, v28.2S}, [x19]
 516     __ ld3r(v15, v16, v17, __ T8H, Address(r21));      //       ld3r    {v15.8H, v16.8H, v17.8H}, [x21]
 517     __ ld3r(v25, v26, v27, __ T4S, Address(__ post(r13, 12))); //       ld3r    {v25.4S, v26.4S, v27.4S}, [x13], 12
 518     __ ld3r(v14, v15, v16, __ T1D, Address(__ post(r28, r29))); //      ld3r    {v14.1D, v15.1D, v16.1D}, [x28], x29
 519     __ ld4(v17, v18, v19, v20, __ T8H, Address(__ post(r29, 64))); //   ld4     {v17.8H, v18.8H, v19.8H, v20.8H}, [x29], 64
 520     __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r7, r0))); //    ld4     {v27.8B, v28.8B, v29.8B, v30.8B}, [x7], x0
 521     __ ld4r(v24, v25, v26, v27, __ T8B, Address(r17)); //       ld4r    {v24.8B, v25.8B, v26.8B, v27.8B}, [x17]
 522     __ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r26, 8))); //       ld4r    {v0.4H, v1.4H, v2.4H, v3.4H}, [x26], 8
 523     __ ld4r(v12, v13, v14, v15, __ T2S, Address(__ post(r25, r2))); //  ld4r    {v12.2S, v13.2S, v14.2S, v15.2S}, [x25], x2
 524 
 525 // NEONReduceInstruction
 526     __ addv(v22, __ T8B, v23);                         //       addv    b22, v23.8B
 527     __ addv(v27, __ T16B, v28);                        //       addv    b27, v28.16B
 528     __ addv(v4, __ T4H, v5);                           //       addv    h4, v5.4H
 529     __ addv(v7, __ T8H, v8);                           //       addv    h7, v8.8H
 530     __ addv(v6, __ T4S, v7);                           //       addv    s6, v7.4S
 531     __ smaxv(v1, __ T8B, v2);                          //       smaxv   b1, v2.8B
 532     __ smaxv(v26, __ T16B, v27);                       //       smaxv   b26, v27.16B
 533     __ smaxv(v15, __ T4H, v16);                        //       smaxv   h15, v16.4H
 534     __ smaxv(v2, __ T8H, v3);                          //       smaxv   h2, v3.8H
 535     __ smaxv(v13, __ T4S, v14);                        //       smaxv   s13, v14.4S
 536     __ fmaxv(v13, __ T4S, v14);                        //       fmaxv   s13, v14.4S
 537     __ sminv(v24, __ T8B, v25);                        //       sminv   b24, v25.8B
 538     __ uminv(v23, __ T8B, v24);                        //       uminv   b23, v24.8B
 539     __ sminv(v4, __ T16B, v5);                         //       sminv   b4, v5.16B
 540     __ uminv(v19, __ T16B, v20);                       //       uminv   b19, v20.16B
 541     __ sminv(v15, __ T4H, v16);                        //       sminv   h15, v16.4H
 542     __ uminv(v0, __ T4H, v1);                          //       uminv   h0, v1.4H
 543     __ sminv(v4, __ T8H, v5);                          //       sminv   h4, v5.8H
 544     __ uminv(v20, __ T8H, v21);                        //       uminv   h20, v21.8H
 545     __ sminv(v11, __ T4S, v12);                        //       sminv   s11, v12.4S
 546     __ uminv(v29, __ T4S, v30);                        //       uminv   s29, v30.4S
 547     __ fminv(v15, __ T4S, v16);                        //       fminv   s15, v16.4S
 548     __ fmaxp(v21, v22, __ S);                          //       fmaxp   s21, v22.2S
 549     __ fmaxp(v4, v5, __ D);                            //       fmaxp   d4, v5.2D
 550     __ fminp(v14, v15, __ S);                          //       fminp   s14, v15.2S
 551     __ fminp(v22, v23, __ D);                          //       fminp   d22, v23.2D
 552 
 553 // TwoRegNEONOp
 554     __ absr(v25, __ T8B, v26);                         //       abs     v25.8B, v26.8B
 555     __ absr(v6, __ T16B, v7);                          //       abs     v6.16B, v7.16B
 556     __ absr(v12, __ T4H, v13);                         //       abs     v12.4H, v13.4H
 557     __ absr(v14, __ T8H, v15);                         //       abs     v14.8H, v15.8H
 558     __ absr(v13, __ T2S, v14);                         //       abs     v13.2S, v14.2S
 559     __ absr(v14, __ T4S, v15);                         //       abs     v14.4S, v15.4S
 560     __ absr(v9, __ T2D, v10);                          //       abs     v9.2D, v10.2D
 561     __ fabs(v25, __ T2S, v26);                         //       fabs    v25.2S, v26.2S
 562     __ fabs(v28, __ T4S, v29);                         //       fabs    v28.4S, v29.4S
 563     __ fabs(v10, __ T2D, v11);                         //       fabs    v10.2D, v11.2D
 564     __ fneg(v19, __ T2S, v20);                         //       fneg    v19.2S, v20.2S
 565     __ fneg(v11, __ T4S, v12);                         //       fneg    v11.4S, v12.4S
 566     __ fneg(v17, __ T2D, v18);                         //       fneg    v17.2D, v18.2D
 567     __ fsqrt(v21, __ T2S, v22);                        //       fsqrt   v21.2S, v22.2S
 568     __ fsqrt(v15, __ T4S, v16);                        //       fsqrt   v15.4S, v16.4S
 569     __ fsqrt(v20, __ T2D, v21);                        //       fsqrt   v20.2D, v21.2D
 570     __ notr(v23, __ T8B, v24);                         //       not     v23.8B, v24.8B
 571     __ notr(v26, __ T16B, v27);                        //       not     v26.16B, v27.16B
 572 
 573 // ThreeRegNEONOp
 574     __ andr(v5, __ T8B, v6, v7);                       //       and     v5.8B, v6.8B, v7.8B
 575     __ andr(v6, __ T16B, v7, v8);                      //       and     v6.16B, v7.16B, v8.16B
 576     __ orr(v15, __ T8B, v16, v17);                     //       orr     v15.8B, v16.8B, v17.8B
 577     __ orr(v15, __ T16B, v16, v17);                    //       orr     v15.16B, v16.16B, v17.16B
 578     __ eor(v25, __ T8B, v26, v27);                     //       eor     v25.8B, v26.8B, v27.8B
 579     __ eor(v16, __ T16B, v17, v18);                    //       eor     v16.16B, v17.16B, v18.16B
 580     __ addv(v27, __ T8B, v28, v29);                    //       add     v27.8B, v28.8B, v29.8B
 581     __ addv(v24, __ T16B, v25, v26);                   //       add     v24.16B, v25.16B, v26.16B
 582     __ addv(v15, __ T4H, v16, v17);                    //       add     v15.4H, v16.4H, v17.4H
 583     __ addv(v25, __ T8H, v26, v27);                    //       add     v25.8H, v26.8H, v27.8H
 584     __ addv(v14, __ T2S, v15, v16);                    //       add     v14.2S, v15.2S, v16.2S
 585     __ addv(v10, __ T4S, v11, v12);                    //       add     v10.4S, v11.4S, v12.4S
 586     __ addv(v13, __ T2D, v14, v15);                    //       add     v13.2D, v14.2D, v15.2D
 587     __ fadd(v14, __ T2S, v15, v16);                    //       fadd    v14.2S, v15.2S, v16.2S
 588     __ fadd(v20, __ T4S, v21, v22);                    //       fadd    v20.4S, v21.4S, v22.4S
 589     __ fadd(v1, __ T2D, v2, v3);                       //       fadd    v1.2D, v2.2D, v3.2D
 590     __ subv(v22, __ T8B, v23, v24);                    //       sub     v22.8B, v23.8B, v24.8B
 591     __ subv(v30, __ T16B, v31, v0);                    //       sub     v30.16B, v31.16B, v0.16B
 592     __ subv(v14, __ T4H, v15, v16);                    //       sub     v14.4H, v15.4H, v16.4H
 593     __ subv(v2, __ T8H, v3, v4);                       //       sub     v2.8H, v3.8H, v4.8H
 594     __ subv(v6, __ T2S, v7, v8);                       //       sub     v6.2S, v7.2S, v8.2S
 595     __ subv(v3, __ T4S, v4, v5);                       //       sub     v3.4S, v4.4S, v5.4S
 596     __ subv(v7, __ T2D, v8, v9);                       //       sub     v7.2D, v8.2D, v9.2D
 597     __ fsub(v24, __ T2S, v25, v26);                    //       fsub    v24.2S, v25.2S, v26.2S
 598     __ fsub(v0, __ T4S, v1, v2);                       //       fsub    v0.4S, v1.4S, v2.4S
 599     __ fsub(v27, __ T2D, v28, v29);                    //       fsub    v27.2D, v28.2D, v29.2D
 600     __ mulv(v29, __ T8B, v30, v31);                    //       mul     v29.8B, v30.8B, v31.8B
 601     __ mulv(v5, __ T16B, v6, v7);                      //       mul     v5.16B, v6.16B, v7.16B
 602     __ mulv(v5, __ T4H, v6, v7);                       //       mul     v5.4H, v6.4H, v7.4H
 603     __ mulv(v29, __ T8H, v30, v31);                    //       mul     v29.8H, v30.8H, v31.8H
 604     __ mulv(v11, __ T2S, v12, v13);                    //       mul     v11.2S, v12.2S, v13.2S
 605     __ mulv(v25, __ T4S, v26, v27);                    //       mul     v25.4S, v26.4S, v27.4S
 606     __ fabd(v0, __ T2S, v1, v2);                       //       fabd    v0.2S, v1.2S, v2.2S
 607     __ fabd(v30, __ T4S, v31, v0);                     //       fabd    v30.4S, v31.4S, v0.4S
 608     __ fabd(v0, __ T2D, v1, v2);                       //       fabd    v0.2D, v1.2D, v2.2D
 609     __ fmul(v17, __ T2S, v18, v19);                    //       fmul    v17.2S, v18.2S, v19.2S
 610     __ fmul(v28, __ T4S, v29, v30);                    //       fmul    v28.4S, v29.4S, v30.4S
 611     __ fmul(v25, __ T2D, v26, v27);                    //       fmul    v25.2D, v26.2D, v27.2D
 612     __ mlav(v9, __ T4H, v10, v11);                     //       mla     v9.4H, v10.4H, v11.4H
 613     __ mlav(v25, __ T8H, v26, v27);                    //       mla     v25.8H, v26.8H, v27.8H
 614     __ mlav(v12, __ T2S, v13, v14);                    //       mla     v12.2S, v13.2S, v14.2S
 615     __ mlav(v15, __ T4S, v16, v17);                    //       mla     v15.4S, v16.4S, v17.4S
 616     __ fmla(v11, __ T2S, v12, v13);                    //       fmla    v11.2S, v12.2S, v13.2S
 617     __ fmla(v10, __ T4S, v11, v12);                    //       fmla    v10.4S, v11.4S, v12.4S
 618     __ fmla(v17, __ T2D, v18, v19);                    //       fmla    v17.2D, v18.2D, v19.2D
 619     __ mlsv(v24, __ T4H, v25, v26);                    //       mls     v24.4H, v25.4H, v26.4H
 620     __ mlsv(v21, __ T8H, v22, v23);                    //       mls     v21.8H, v22.8H, v23.8H
 621     __ mlsv(v23, __ T2S, v24, v25);                    //       mls     v23.2S, v24.2S, v25.2S
 622     __ mlsv(v0, __ T4S, v1, v2);                       //       mls     v0.4S, v1.4S, v2.4S
 623     __ fmls(v16, __ T2S, v17, v18);                    //       fmls    v16.2S, v17.2S, v18.2S
 624     __ fmls(v10, __ T4S, v11, v12);                    //       fmls    v10.4S, v11.4S, v12.4S
 625     __ fmls(v6, __ T2D, v7, v8);                       //       fmls    v6.2D, v7.2D, v8.2D
 626     __ fdiv(v28, __ T2S, v29, v30);                    //       fdiv    v28.2S, v29.2S, v30.2S
 627     __ fdiv(v6, __ T4S, v7, v8);                       //       fdiv    v6.4S, v7.4S, v8.4S
 628     __ fdiv(v5, __ T2D, v6, v7);                       //       fdiv    v5.2D, v6.2D, v7.2D
 629     __ maxv(v5, __ T8B, v6, v7);                       //       smax    v5.8B, v6.8B, v7.8B
 630     __ maxv(v20, __ T16B, v21, v22);                   //       smax    v20.16B, v21.16B, v22.16B
 631     __ maxv(v17, __ T4H, v18, v19);                    //       smax    v17.4H, v18.4H, v19.4H
 632     __ maxv(v15, __ T8H, v16, v17);                    //       smax    v15.8H, v16.8H, v17.8H
 633     __ maxv(v17, __ T2S, v18, v19);                    //       smax    v17.2S, v18.2S, v19.2S
 634     __ maxv(v29, __ T4S, v30, v31);                    //       smax    v29.4S, v30.4S, v31.4S
 635     __ smaxp(v26, __ T8B, v27, v28);                   //       smaxp   v26.8B, v27.8B, v28.8B
 636     __ smaxp(v28, __ T16B, v29, v30);                  //       smaxp   v28.16B, v29.16B, v30.16B
 637     __ smaxp(v1, __ T4H, v2, v3);                      //       smaxp   v1.4H, v2.4H, v3.4H
 638     __ smaxp(v27, __ T8H, v28, v29);                   //       smaxp   v27.8H, v28.8H, v29.8H
 639     __ smaxp(v0, __ T2S, v1, v2);                      //       smaxp   v0.2S, v1.2S, v2.2S
 640     __ smaxp(v20, __ T4S, v21, v22);                   //       smaxp   v20.4S, v21.4S, v22.4S
 641     __ fmax(v28, __ T2S, v29, v30);                    //       fmax    v28.2S, v29.2S, v30.2S
 642     __ fmax(v15, __ T4S, v16, v17);                    //       fmax    v15.4S, v16.4S, v17.4S
 643     __ fmax(v12, __ T2D, v13, v14);                    //       fmax    v12.2D, v13.2D, v14.2D
 644     __ minv(v10, __ T8B, v11, v12);                    //       smin    v10.8B, v11.8B, v12.8B
 645     __ minv(v28, __ T16B, v29, v30);                   //       smin    v28.16B, v29.16B, v30.16B
 646     __ minv(v28, __ T4H, v29, v30);                    //       smin    v28.4H, v29.4H, v30.4H
 647     __ minv(v19, __ T8H, v20, v21);                    //       smin    v19.8H, v20.8H, v21.8H
 648     __ minv(v22, __ T2S, v23, v24);                    //       smin    v22.2S, v23.2S, v24.2S
 649     __ minv(v10, __ T4S, v11, v12);                    //       smin    v10.4S, v11.4S, v12.4S
 650     __ sminp(v4, __ T8B, v5, v6);                      //       sminp   v4.8B, v5.8B, v6.8B
 651     __ sminp(v30, __ T16B, v31, v0);                   //       sminp   v30.16B, v31.16B, v0.16B
 652     __ sminp(v20, __ T4H, v21, v22);                   //       sminp   v20.4H, v21.4H, v22.4H
 653     __ sminp(v8, __ T8H, v9, v10);                     //       sminp   v8.8H, v9.8H, v10.8H
 654     __ sminp(v30, __ T2S, v31, v0);                    //       sminp   v30.2S, v31.2S, v0.2S
 655     __ sminp(v17, __ T4S, v18, v19);                   //       sminp   v17.4S, v18.4S, v19.4S
 656     __ fmin(v10, __ T2S, v11, v12);                    //       fmin    v10.2S, v11.2S, v12.2S
 657     __ fmin(v27, __ T4S, v28, v29);                    //       fmin    v27.4S, v28.4S, v29.4S
 658     __ fmin(v2, __ T2D, v3, v4);                       //       fmin    v2.2D, v3.2D, v4.2D
 659     __ cmeq(v24, __ T8B, v25, v26);                    //       cmeq    v24.8B, v25.8B, v26.8B
 660     __ cmeq(v4, __ T16B, v5, v6);                      //       cmeq    v4.16B, v5.16B, v6.16B
 661     __ cmeq(v3, __ T4H, v4, v5);                       //       cmeq    v3.4H, v4.4H, v5.4H
 662     __ cmeq(v8, __ T8H, v9, v10);                      //       cmeq    v8.8H, v9.8H, v10.8H
 663     __ cmeq(v22, __ T2S, v23, v24);                    //       cmeq    v22.2S, v23.2S, v24.2S
 664     __ cmeq(v17, __ T4S, v18, v19);                    //       cmeq    v17.4S, v18.4S, v19.4S
 665     __ cmeq(v13, __ T2D, v14, v15);                    //       cmeq    v13.2D, v14.2D, v15.2D
 666     __ fcmeq(v4, __ T2S, v5, v6);                      //       fcmeq   v4.2S, v5.2S, v6.2S
 667     __ fcmeq(v28, __ T4S, v29, v30);                   //       fcmeq   v28.4S, v29.4S, v30.4S
 668     __ fcmeq(v23, __ T2D, v24, v25);                   //       fcmeq   v23.2D, v24.2D, v25.2D
 669     __ cmgt(v21, __ T8B, v22, v23);                    //       cmgt    v21.8B, v22.8B, v23.8B
 670     __ cmgt(v25, __ T16B, v26, v27);                   //       cmgt    v25.16B, v26.16B, v27.16B
 671     __ cmgt(v24, __ T4H, v25, v26);                    //       cmgt    v24.4H, v25.4H, v26.4H
 672     __ cmgt(v3, __ T8H, v4, v5);                       //       cmgt    v3.8H, v4.8H, v5.8H
 673     __ cmgt(v23, __ T2S, v24, v25);                    //       cmgt    v23.2S, v24.2S, v25.2S
 674     __ cmgt(v26, __ T4S, v27, v28);                    //       cmgt    v26.4S, v27.4S, v28.4S
 675     __ cmgt(v23, __ T2D, v24, v25);                    //       cmgt    v23.2D, v24.2D, v25.2D
 676     __ cmhi(v14, __ T8B, v15, v16);                    //       cmhi    v14.8B, v15.8B, v16.8B
 677     __ cmhi(v21, __ T16B, v22, v23);                   //       cmhi    v21.16B, v22.16B, v23.16B
 678     __ cmhi(v3, __ T4H, v4, v5);                       //       cmhi    v3.4H, v4.4H, v5.4H
 679     __ cmhi(v23, __ T8H, v24, v25);                    //       cmhi    v23.8H, v24.8H, v25.8H
 680     __ cmhi(v8, __ T2S, v9, v10);                      //       cmhi    v8.2S, v9.2S, v10.2S
 681     __ cmhi(v24, __ T4S, v25, v26);                    //       cmhi    v24.4S, v25.4S, v26.4S
 682     __ cmhi(v19, __ T2D, v20, v21);                    //       cmhi    v19.2D, v20.2D, v21.2D
 683     __ cmhs(v15, __ T8B, v16, v17);                    //       cmhs    v15.8B, v16.8B, v17.8B
 684     __ cmhs(v16, __ T16B, v17, v18);                   //       cmhs    v16.16B, v17.16B, v18.16B
 685     __ cmhs(v2, __ T4H, v3, v4);                       //       cmhs    v2.4H, v3.4H, v4.4H
 686     __ cmhs(v1, __ T8H, v2, v3);                       //       cmhs    v1.8H, v2.8H, v3.8H
 687     __ cmhs(v0, __ T2S, v1, v2);                       //       cmhs    v0.2S, v1.2S, v2.2S
 688     __ cmhs(v24, __ T4S, v25, v26);                    //       cmhs    v24.4S, v25.4S, v26.4S
 689     __ cmhs(v4, __ T2D, v5, v6);                       //       cmhs    v4.2D, v5.2D, v6.2D
 690     __ fcmgt(v3, __ T2S, v4, v5);                      //       fcmgt   v3.2S, v4.2S, v5.2S
 691     __ fcmgt(v11, __ T4S, v12, v13);                   //       fcmgt   v11.4S, v12.4S, v13.4S
 692     __ fcmgt(v30, __ T2D, v31, v0);                    //       fcmgt   v30.2D, v31.2D, v0.2D
 693     __ cmge(v27, __ T8B, v28, v29);                    //       cmge    v27.8B, v28.8B, v29.8B
 694     __ cmge(v9, __ T16B, v10, v11);                    //       cmge    v9.16B, v10.16B, v11.16B
 695     __ cmge(v25, __ T4H, v26, v27);                    //       cmge    v25.4H, v26.4H, v27.4H
 696     __ cmge(v2, __ T8H, v3, v4);                       //       cmge    v2.8H, v3.8H, v4.8H
 697     __ cmge(v12, __ T2S, v13, v14);                    //       cmge    v12.2S, v13.2S, v14.2S
 698     __ cmge(v17, __ T4S, v18, v19);                    //       cmge    v17.4S, v18.4S, v19.4S
 699     __ cmge(v30, __ T2D, v31, v0);                     //       cmge    v30.2D, v31.2D, v0.2D
 700     __ fcmge(v1, __ T2S, v2, v3);                      //       fcmge   v1.2S, v2.2S, v3.2S
 701     __ fcmge(v12, __ T4S, v13, v14);                   //       fcmge   v12.4S, v13.4S, v14.4S
 702     __ fcmge(v28, __ T2D, v29, v30);                   //       fcmge   v28.2D, v29.2D, v30.2D
 703 
 704 // SpecialCases
 705     __ ccmn(zr, zr, 3u, Assembler::LE);                //       ccmn    xzr, xzr, #3, LE
 706     __ ccmnw(zr, zr, 5u, Assembler::EQ);               //       ccmn    wzr, wzr, #5, EQ
 707     __ ccmp(zr, 1, 4u, Assembler::NE);                 //       ccmp    xzr, 1, #4, NE
 708     __ ccmpw(zr, 2, 2, Assembler::GT);                 //       ccmp    wzr, 2, #2, GT
 709     __ extr(zr, zr, zr, 0);                            //       extr    xzr, xzr, xzr, 0
 710     __ stlxp(r0, zr, zr, sp);                          //       stlxp   w0, xzr, xzr, [sp]
 711     __ stlxpw(r2, zr, zr, r3);                         //       stlxp   w2, wzr, wzr, [x3]
 712     __ stxp(r4, zr, zr, r5);                           //       stxp    w4, xzr, xzr, [x5]
 713     __ stxpw(r6, zr, zr, sp);                          //       stxp    w6, wzr, wzr, [sp]
 714     __ dup(v0, __ T16B, zr);                           //       dup     v0.16b, wzr
 715     __ mov(v1, __ T1D, 0, zr);                         //       mov     v1.d[0], xzr
 716     __ mov(v1, __ T2S, 1, zr);                         //       mov     v1.s[1], wzr
 717     __ mov(v1, __ T4H, 2, zr);                         //       mov     v1.h[2], wzr
 718     __ mov(v1, __ T8B, 3, zr);                         //       mov     v1.b[3], wzr
 719     __ smov(r0, v1, __ S, 0);                          //       smov    x0, v1.s[0]
 720     __ smov(r0, v1, __ H, 1);                          //       smov    x0, v1.h[1]
 721     __ smov(r0, v1, __ B, 2);                          //       smov    x0, v1.b[2]
 722     __ umov(r0, v1, __ D, 0);                          //       umov    x0, v1.d[0]
 723     __ umov(r0, v1, __ S, 1);                          //       umov    w0, v1.s[1]
 724     __ umov(r0, v1, __ H, 2);                          //       umov    w0, v1.h[2]
 725     __ umov(r0, v1, __ B, 3);                          //       umov    w0, v1.b[3]
 726     __ fmovhid(r0, v1);                                //       fmov    x0, v1.d[1]
 727     __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); //       ld1     {v31.2d, v0.2d}, [x1], x0
 728     __ sve_cpy(z0, __ S, p0, v1);                      //       mov     z0.s, p0/m, s1
 729     __ sve_cpy(z0, __ B, p0, 127, true);               //       mov     z0.b, p0/m, 127
 730     __ sve_cpy(z1, __ H, p0, -128, true);              //       mov     z1.h, p0/m, -128
 731     __ sve_cpy(z2, __ S, p0, 32512, true);             //       mov     z2.s, p0/m, 32512
 732     __ sve_cpy(z5, __ D, p0, -32768, false);           //       mov     z5.d, p0/z, -32768
 733     __ sve_cpy(z10, __ B, p0, -1, false);              //       mov     z10.b, p0/z, -1
 734     __ sve_cpy(z11, __ S, p0, -1, false);              //       mov     z11.s, p0/z, -1
 735     __ sve_inc(r0, __ S);                              //       incw    x0
 736     __ sve_dec(r1, __ H);                              //       dech    x1
 737     __ sve_lsl(z0, __ B, z1, 7);                       //       lsl     z0.b, z1.b, #7
 738     __ sve_lsl(z21, __ H, z1, 15);                     //       lsl     z21.h, z1.h, #15
 739     __ sve_lsl(z0, __ S, z1, 31);                      //       lsl     z0.s, z1.s, #31
 740     __ sve_lsl(z0, __ D, z1, 63);                      //       lsl     z0.d, z1.d, #63
 741     __ sve_lsr(z0, __ B, z1, 7);                       //       lsr     z0.b, z1.b, #7
 742     __ sve_asr(z0, __ H, z11, 15);                     //       asr     z0.h, z11.h, #15
 743     __ sve_lsr(z30, __ S, z1, 31);                     //       lsr     z30.s, z1.s, #31
 744     __ sve_asr(z0, __ D, z1, 63);                      //       asr     z0.d, z1.d, #63
 745     __ sve_addvl(sp, r0, 31);                          //       addvl   sp, x0, #31
 746     __ sve_addpl(r1, sp, -32);                         //       addpl   x1, sp, -32
 747     __ sve_cntp(r8, __ B, p0, p1);                     //       cntp    x8, p0, p1.b
 748     __ sve_dup(z0, __ B, 127);                         //       dup     z0.b, 127
 749     __ sve_dup(z1, __ H, -128);                        //       dup     z1.h, -128
 750     __ sve_dup(z2, __ S, 32512);                       //       dup     z2.s, 32512
 751     __ sve_dup(z7, __ D, -32768);                      //       dup     z7.d, -32768
 752     __ sve_dup(z10, __ B, -1);                         //       dup     z10.b, -1
 753     __ sve_dup(z11, __ S, -1);                         //       dup     z11.s, -1
 754     __ sve_ld1b(z0, __ B, p0, Address(sp));            //       ld1b    {z0.b}, p0/z, [sp]
 755     __ sve_ld1b(z0, __ H, p1, Address(sp));            //       ld1b    {z0.h}, p1/z, [sp]
 756     __ sve_ld1b(z0, __ S, p2, Address(sp, r8));        //       ld1b    {z0.s}, p2/z, [sp, x8]
 757     __ sve_ld1b(z0, __ D, p3, Address(sp, 7));         //       ld1b    {z0.d}, p3/z, [sp, #7, MUL VL]
 758     __ sve_ld1h(z10, __ H, p1, Address(sp, -8));       //       ld1h    {z10.h}, p1/z, [sp, #-8, MUL VL]
 759     __ sve_ld1w(z20, __ S, p2, Address(r0, 7));        //       ld1w    {z20.s}, p2/z, [x0, #7, MUL VL]
 760     __ sve_ld1b(z30, __ B, p3, Address(sp, r8));       //       ld1b    {z30.b}, p3/z, [sp, x8]
 761     __ sve_ld1w(z0, __ S, p4, Address(sp, r28));       //       ld1w    {z0.s}, p4/z, [sp, x28, LSL #2]
 762     __ sve_ld1d(z11, __ D, p5, Address(r0, r1));       //       ld1d    {z11.d}, p5/z, [x0, x1, LSL #3]
 763     __ sve_st1b(z22, __ B, p6, Address(sp));           //       st1b    {z22.b}, p6, [sp]
 764     __ sve_st1b(z31, __ B, p7, Address(sp, -8));       //       st1b    {z31.b}, p7, [sp, #-8, MUL VL]
 765     __ sve_st1b(z0, __ H, p1, Address(sp));            //       st1b    {z0.h}, p1, [sp]
 766     __ sve_st1b(z0, __ S, p2, Address(sp, r8));        //       st1b    {z0.s}, p2, [sp, x8]
 767     __ sve_st1b(z0, __ D, p3, Address(sp));            //       st1b    {z0.d}, p3, [sp]
 768     __ sve_st1w(z0, __ S, p1, Address(r0, 7));         //       st1w    {z0.s}, p1, [x0, #7, MUL VL]
 769     __ sve_st1b(z0, __ B, p2, Address(sp, r1));        //       st1b    {z0.b}, p2, [sp, x1]
 770     __ sve_st1h(z0, __ H, p3, Address(sp, r8));        //       st1h    {z0.h}, p3, [sp, x8, LSL #1]
 771     __ sve_st1d(z0, __ D, p4, Address(r0, r17));       //       st1d    {z0.d}, p4, [x0, x17, LSL #3]
 772     __ sve_ldr(z0, Address(sp));                       //       ldr     z0, [sp]
 773     __ sve_ldr(z31, Address(sp, -256));                //       ldr     z31, [sp, #-256, MUL VL]
 774     __ sve_str(z8, Address(r8, 255));                  //       str     z8, [x8, #255, MUL VL]
 775     __ sve_cntb(r9);                                   //       cntb    x9
 776     __ sve_cnth(r10);                                  //       cnth    x10
 777     __ sve_cntw(r11);                                  //       cntw    x11
 778     __ sve_cntd(r12);                                  //       cntd    x12
 779     __ sve_brka(p2, p0, p2, false);                    //       brka    p2.b, p0/z, p2.b
 780     __ sve_brka(p1, p2, p3, true);                     //       brka    p1.b, p2/m, p3.b
 781     __ sve_brkb(p1, p2, p3, false);                    //       brkb    p1.b, p2/z, p3.b
 782     __ sve_brkb(p2, p3, p4, true);                     //       brkb    p2.b, p3/m, p4.b
 783     __ sve_rev(p0, __ B, p1);                          //       rev     p0.b, p1.b
 784     __ sve_rev(p1, __ H, p2);                          //       rev     p1.h, p2.h
 785     __ sve_rev(p2, __ S, p3);                          //       rev     p2.s, p3.s
 786     __ sve_rev(p3, __ D, p4);                          //       rev     p3.d, p4.d
 787     __ sve_incp(r0, __ B, p2);                         //       incp    x0, p2.b
 788     __ sve_whilelt(p0, __ B, r1, r28);                 //       whilelt p0.b, x1, x28
 789     __ sve_whilele(p2, __ H, r11, r8);                 //       whilele p2.h, x11, x8
 790     __ sve_whilelo(p3, __ S, r7, r2);                  //       whilelo p3.s, x7, x2
 791     __ sve_whilels(p4, __ D, r17, r10);                //       whilels p4.d, x17, x10
 792     __ sve_sel(z0, __ B, p0, z1, z2);                  //       sel     z0.b, p0, z1.b, z2.b
 793     __ sve_sel(z4, __ D, p0, z5, z6);                  //       sel     z4.d, p0, z5.d, z6.d
 794     __ sve_cmp(Assembler::EQ, p1, __ B, p0, z0, z1);   //       cmpeq   p1.b, p0/z, z0.b, z1.b
 795     __ sve_cmp(Assembler::NE, p1, __ H, p0, z2, z3);   //       cmpne   p1.h, p0/z, z2.h, z3.h
 796     __ sve_cmp(Assembler::GE, p1, __ S, p2, z4, z5);   //       cmpge   p1.s, p2/z, z4.s, z5.s
 797     __ sve_cmp(Assembler::GT, p1, __ D, p3, z6, z7);   //       cmpgt   p1.d, p3/z, z6.d, z7.d
 798     __ sve_cmp(Assembler::HI, p1, __ S, p2, z4, z5);   //       cmphi   p1.s, p2/z, z4.s, z5.s
 799     __ sve_cmp(Assembler::HS, p1, __ D, p3, z6, z7);   //       cmphs   p1.d, p3/z, z6.d, z7.d
 800     __ sve_cmp(Assembler::EQ, p1, __ B, p4, z0, 15);   //       cmpeq   p1.b, p4/z, z0.b, #15
 801     __ sve_cmp(Assembler::NE, p1, __ H, p0, z2, -16);  //       cmpne   p1.h, p0/z, z2.h, #-16
 802     __ sve_cmp(Assembler::LE, p1, __ S, p1, z4, 0);    //       cmple   p1.s, p1/z, z4.s, #0
 803     __ sve_cmp(Assembler::LT, p1, __ D, p2, z6, -1);   //       cmplt   p1.d, p2/z, z6.d, #-1
 804     __ sve_cmp(Assembler::GE, p1, __ S, p3, z4, 5);    //       cmpge   p1.s, p3/z, z4.s, #5
 805     __ sve_cmp(Assembler::GT, p1, __ B, p4, z6, -2);   //       cmpgt   p1.b, p4/z, z6.b, #-2
 806     __ sve_fcm(Assembler::EQ, p1, __ S, p0, z0, z1);   //       fcmeq   p1.s, p0/z, z0.s, z1.s
 807     __ sve_fcm(Assembler::NE, p1, __ D, p0, z2, z3);   //       fcmne   p1.d, p0/z, z2.d, z3.d
 808     __ sve_fcm(Assembler::GT, p1, __ S, p2, z4, z5);   //       fcmgt   p1.s, p2/z, z4.s, z5.s
 809     __ sve_fcm(Assembler::GE, p1, __ D, p3, z6, z7);   //       fcmge   p1.d, p3/z, z6.d, z7.d
 810     __ sve_uunpkhi(z0, __ H, z1);                      //       uunpkhi z0.h, z1.b
 811     __ sve_uunpklo(z4, __ S, z5);                      //       uunpklo z4.s, z5.h
 812     __ sve_sunpkhi(z6, __ D, z7);                      //       sunpkhi z6.d, z7.s
 813     __ sve_sunpklo(z10, __ H, z11);                    //       sunpklo z10.h, z11.b
 814     __ sve_scvtf(z1, __ D, p0, z0, __ S);              //       scvtf   z1.d, p0/m, z0.s
 815     __ sve_scvtf(z3, __ D, p1, z2, __ D);              //       scvtf   z3.d, p1/m, z2.d
 816     __ sve_scvtf(z6, __ S, p2, z1, __ D);              //       scvtf   z6.s, p2/m, z1.d
 817     __ sve_scvtf(z6, __ S, p3, z1, __ S);              //       scvtf   z6.s, p3/m, z1.s
 818     __ sve_scvtf(z6, __ H, p3, z1, __ S);              //       scvtf   z6.h, p3/m, z1.s
 819     __ sve_scvtf(z6, __ H, p3, z1, __ D);              //       scvtf   z6.h, p3/m, z1.d
 820     __ sve_scvtf(z6, __ H, p3, z1, __ H);              //       scvtf   z6.h, p3/m, z1.h
 821     __ sve_fcvt(z5, __ D, p3, z4, __ S);               //       fcvt    z5.d, p3/m, z4.s
 822     __ sve_fcvt(z1, __ S, p3, z0, __ D);               //       fcvt    z1.s, p3/m, z0.d
 823     __ sve_fcvtzs(z19, __ D, p2, z1, __ D);            //       fcvtzs  z19.d, p2/m, z1.d
 824     __ sve_fcvtzs(z9, __ S, p1, z8, __ S);             //       fcvtzs  z9.s, p1/m, z8.s
 825     __ sve_fcvtzs(z1, __ S, p2, z0, __ D);             //       fcvtzs  z1.s, p2/m, z0.d
 826     __ sve_fcvtzs(z1, __ D, p3, z0, __ S);             //       fcvtzs  z1.d, p3/m, z0.s
 827     __ sve_fcvtzs(z1, __ S, p4, z18, __ H);            //       fcvtzs  z1.s, p4/m, z18.h
 828     __ sve_lasta(r0, __ B, p0, z15);                   //       lasta   w0, p0, z15.b
 829     __ sve_lastb(r1, __ B, p1, z16);                   //       lastb   w1, p1, z16.b
 830     __ sve_lasta(v0, __ B, p0, z15);                   //       lasta   b0, p0, z15.b
 831     __ sve_lastb(v1, __ B, p1, z16);                   //       lastb   b1, p1, z16.b
 832     __ sve_index(z6, __ S, 1, 1);                      //       index   z6.s, #1, #1
 833     __ sve_cpy(z7, __ H, p3, r5);                      //       cpy     z7.h, p3/m, w5
 834     __ sve_tbl(z16, __ S, z17, z18);                   //       tbl     z16.s, {z17.s}, z18.s
 835     __ sve_ld1w_gather(z15, p0, r5, z16);              //       ld1w    {z15.s}, p0/z, [x5, z16.s, uxtw #2]
 836     __ sve_ld1d_gather(z15, p0, r5, z16);              //       ld1d    {z15.d}, p0/z, [x5, z16.d, uxtw #3]
 837     __ sve_st1w_scatter(z15, p0, r5, z16);             //       st1w    {z15.s}, p0, [x5, z16.s, uxtw #2]
 838     __ sve_st1d_scatter(z15, p0, r5, z16);             //       st1d    {z15.d}, p0, [x5, z16.d, uxtw #3]
 839 
 840 // FloatImmediateOp
 841     __ fmovd(v0, 2.0);                                 //       fmov d0, #2.0
 842     __ fmovd(v0, 2.125);                               //       fmov d0, #2.125
 843     __ fmovd(v0, 4.0);                                 //       fmov d0, #4.0
 844     __ fmovd(v0, 4.25);                                //       fmov d0, #4.25
 845     __ fmovd(v0, 8.0);                                 //       fmov d0, #8.0
 846     __ fmovd(v0, 8.5);                                 //       fmov d0, #8.5
 847     __ fmovd(v0, 16.0);                                //       fmov d0, #16.0
 848     __ fmovd(v0, 17.0);                                //       fmov d0, #17.0
 849     __ fmovd(v0, 0.125);                               //       fmov d0, #0.125
 850     __ fmovd(v0, 0.1328125);                           //       fmov d0, #0.1328125
 851     __ fmovd(v0, 0.25);                                //       fmov d0, #0.25
 852     __ fmovd(v0, 0.265625);                            //       fmov d0, #0.265625
 853     __ fmovd(v0, 0.5);                                 //       fmov d0, #0.5
 854     __ fmovd(v0, 0.53125);                             //       fmov d0, #0.53125
 855     __ fmovd(v0, 1.0);                                 //       fmov d0, #1.0
 856     __ fmovd(v0, 1.0625);                              //       fmov d0, #1.0625
 857     __ fmovd(v0, -2.0);                                //       fmov d0, #-2.0
 858     __ fmovd(v0, -2.125);                              //       fmov d0, #-2.125
 859     __ fmovd(v0, -4.0);                                //       fmov d0, #-4.0
 860     __ fmovd(v0, -4.25);                               //       fmov d0, #-4.25
 861     __ fmovd(v0, -8.0);                                //       fmov d0, #-8.0
 862     __ fmovd(v0, -8.5);                                //       fmov d0, #-8.5
 863     __ fmovd(v0, -16.0);                               //       fmov d0, #-16.0
 864     __ fmovd(v0, -17.0);                               //       fmov d0, #-17.0
 865     __ fmovd(v0, -0.125);                              //       fmov d0, #-0.125
 866     __ fmovd(v0, -0.1328125);                          //       fmov d0, #-0.1328125
 867     __ fmovd(v0, -0.25);                               //       fmov d0, #-0.25
 868     __ fmovd(v0, -0.265625);                           //       fmov d0, #-0.265625
 869     __ fmovd(v0, -0.5);                                //       fmov d0, #-0.5
 870     __ fmovd(v0, -0.53125);                            //       fmov d0, #-0.53125
 871     __ fmovd(v0, -1.0);                                //       fmov d0, #-1.0
 872     __ fmovd(v0, -1.0625);                             //       fmov d0, #-1.0625
 873 
 874 // LSEOp
 875     __ swp(Assembler::xword, r0, r19, r12);            //       swp     x0, x19, [x12]
 876     __ ldadd(Assembler::xword, r17, r22, r13);         //       ldadd   x17, x22, [x13]
 877     __ ldbic(Assembler::xword, r28, r30, sp);          //       ldclr   x28, x30, [sp]
 878     __ ldeor(Assembler::xword, r1, r26, r28);          //       ldeor   x1, x26, [x28]
 879     __ ldorr(Assembler::xword, r4, r30, r4);           //       ldset   x4, x30, [x4]
 880     __ ldsmin(Assembler::xword, r6, r30, r26);         //       ldsmin  x6, x30, [x26]
 881     __ ldsmax(Assembler::xword, r16, r9, r8);          //       ldsmax  x16, x9, [x8]
 882     __ ldumin(Assembler::xword, r12, r0, r20);         //       ldumin  x12, x0, [x20]
 883     __ ldumax(Assembler::xword, r1, r24, r2);          //       ldumax  x1, x24, [x2]
 884 
 885 // LSEOp
 886     __ swpa(Assembler::xword, r0, r9, r24);            //       swpa    x0, x9, [x24]
 887     __ ldadda(Assembler::xword, r26, r16, r30);        //       ldadda  x26, x16, [x30]
 888     __ ldbica(Assembler::xword, r3, r10, r23);         //       ldclra  x3, x10, [x23]
 889     __ ldeora(Assembler::xword, r10, r4, r15);         //       ldeora  x10, x4, [x15]
 890     __ ldorra(Assembler::xword, r2, r11, r8);          //       ldseta  x2, x11, [x8]
 891     __ ldsmina(Assembler::xword, r10, r15, r17);       //       ldsmina x10, x15, [x17]
 892     __ ldsmaxa(Assembler::xword, r2, r10, r12);        //       ldsmaxa x2, x10, [x12]
 893     __ ldumina(Assembler::xword, r12, r15, r13);       //       ldumina x12, x15, [x13]
 894     __ ldumaxa(Assembler::xword, r2, r7, r20);         //       ldumaxa x2, x7, [x20]
 895 
 896 // LSEOp
 897     __ swpal(Assembler::xword, r26, r16, r4);          //       swpal   x26, x16, [x4]
 898     __ ldaddal(Assembler::xword, r2, r4, r12);         //       ldaddal x2, x4, [x12]
 899     __ ldbical(Assembler::xword, r16, r21, r16);       //       ldclral x16, x21, [x16]
 900     __ ldeoral(Assembler::xword, r16, r11, r21);       //       ldeoral x16, x11, [x21]
 901     __ ldorral(Assembler::xword, r23, r12, r26);       //       ldsetal x23, x12, [x26]
 902     __ ldsminal(Assembler::xword, r23, r28, r14);      //       ldsminal        x23, x28, [x14]
 903     __ ldsmaxal(Assembler::xword, r11, r24, r1);       //       ldsmaxal        x11, x24, [x1]
 904     __ lduminal(Assembler::xword, r12, zr, r10);       //       lduminal        x12, xzr, [x10]
 905     __ ldumaxal(Assembler::xword, r16, r7, r2);        //       ldumaxal        x16, x7, [x2]
 906 
 907 // LSEOp
 908     __ swpl(Assembler::xword, r3, r13, r19);           //       swpl    x3, x13, [x19]
 909     __ ldaddl(Assembler::xword, r17, r16, r3);         //       ldaddl  x17, x16, [x3]
 910     __ ldbicl(Assembler::xword, r1, r11, r30);         //       ldclrl  x1, x11, [x30]
 911     __ ldeorl(Assembler::xword, r5, r8, r15);          //       ldeorl  x5, x8, [x15]
 912     __ ldorrl(Assembler::xword, r29, r30, r0);         //       ldsetl  x29, x30, [x0]
 913     __ ldsminl(Assembler::xword, r20, r7, r20);        //       ldsminl x20, x7, [x20]
 914     __ ldsmaxl(Assembler::xword, r23, r28, r21);       //       ldsmaxl x23, x28, [x21]
 915     __ lduminl(Assembler::xword, r27, r25, r5);        //       lduminl x27, x25, [x5]
 916     __ ldumaxl(Assembler::xword, r1, r23, r16);        //       ldumaxl x1, x23, [x16]
 917 
 918 // LSEOp
 919     __ swp(Assembler::word, zr, r5, r12);              //       swp     wzr, w5, [x12]
 920     __ ldadd(Assembler::word, r9, r28, r15);           //       ldadd   w9, w28, [x15]
 921     __ ldbic(Assembler::word, r29, r22, sp);           //       ldclr   w29, w22, [sp]
 922     __ ldeor(Assembler::word, r19, zr, r5);            //       ldeor   w19, wzr, [x5]
 923     __ ldorr(Assembler::word, r14, r16, sp);           //       ldset   w14, w16, [sp]
 924     __ ldsmin(Assembler::word, r16, r27, r20);         //       ldsmin  w16, w27, [x20]
 925     __ ldsmax(Assembler::word, r16, r12, r11);         //       ldsmax  w16, w12, [x11]
 926     __ ldumin(Assembler::word, r9, r6, r30);           //       ldumin  w9, w6, [x30]
 927     __ ldumax(Assembler::word, r17, r27, r28);         //       ldumax  w17, w27, [x28]
 928 
 929 // LSEOp
 930     __ swpa(Assembler::word, r30, r7, r10);            //       swpa    w30, w7, [x10]
 931     __ ldadda(Assembler::word, r20, r10, r4);          //       ldadda  w20, w10, [x4]
 932     __ ldbica(Assembler::word, r24, r17, r17);         //       ldclra  w24, w17, [x17]
 933     __ ldeora(Assembler::word, r22, r3, r29);          //       ldeora  w22, w3, [x29]
 934     __ ldorra(Assembler::word, r15, r22, r19);         //       ldseta  w15, w22, [x19]
 935     __ ldsmina(Assembler::word, r19, r22, r2);         //       ldsmina w19, w22, [x2]
 936     __ ldsmaxa(Assembler::word, r15, r6, r12);         //       ldsmaxa w15, w6, [x12]
 937     __ ldumina(Assembler::word, r16, r11, r13);        //       ldumina w16, w11, [x13]
 938     __ ldumaxa(Assembler::word, r23, r1, r30);         //       ldumaxa w23, w1, [x30]
 939 
 940 // LSEOp
 941     __ swpal(Assembler::word, r19, r5, r17);           //       swpal   w19, w5, [x17]
 942     __ ldaddal(Assembler::word, r2, r16, r22);         //       ldaddal w2, w16, [x22]
 943     __ ldbical(Assembler::word, r13, r10, r21);        //       ldclral w13, w10, [x21]
 944     __ ldeoral(Assembler::word, r29, r27, r12);        //       ldeoral w29, w27, [x12]
 945     __ ldorral(Assembler::word, r27, r3, r1);          //       ldsetal w27, w3, [x1]
 946     __ ldsminal(Assembler::word, zr, r24, r19);        //       ldsminal        wzr, w24, [x19]
 947     __ ldsmaxal(Assembler::word, r17, r9, r28);        //       ldsmaxal        w17, w9, [x28]
 948     __ lduminal(Assembler::word, r27, r15, r7);        //       lduminal        w27, w15, [x7]
 949     __ ldumaxal(Assembler::word, r21, r23, sp);        //       ldumaxal        w21, w23, [sp]
 950 
 951 // LSEOp
 952     __ swpl(Assembler::word, r25, r2, sp);             //       swpl    w25, w2, [sp]
 953     __ ldaddl(Assembler::word, r27, r16, r10);         //       ldaddl  w27, w16, [x10]
 954     __ ldbicl(Assembler::word, r23, r19, r3);          //       ldclrl  w23, w19, [x3]
 955     __ ldeorl(Assembler::word, r16, r0, r25);          //       ldeorl  w16, w0, [x25]
 956     __ ldorrl(Assembler::word, r26, r23, r2);          //       ldsetl  w26, w23, [x2]
 957     __ ldsminl(Assembler::word, r16, r12, r4);         //       ldsminl w16, w12, [x4]
 958     __ ldsmaxl(Assembler::word, r28, r30, r29);        //       ldsmaxl w28, w30, [x29]
 959     __ lduminl(Assembler::word, r16, r27, r6);         //       lduminl w16, w27, [x6]
 960     __ ldumaxl(Assembler::word, r9, r29, r15);         //       ldumaxl w9, w29, [x15]
 961 
 962 // SHA3SIMDOp
 963     __ bcax(v7, __ T16B, v4, v7, v15);                 //       bcax            v7.16B, v4.16B, v7.16B, v15.16B
 964     __ eor3(v9, __ T16B, v22, v8, v2);                 //       eor3            v9.16B, v22.16B, v8.16B, v2.16B
 965     __ rax1(v27, __ T2D, v20, v30);                    //       rax1            v27.2D, v20.2D, v30.2D
 966     __ xar(v5, __ T2D, v26, v0, 34);                   //       xar             v5.2D, v26.2D, v0.2D, #34
 967 
 968 // SHA512SIMDOp
 969     __ sha512h(v14, __ T2D, v3, v25);                  //       sha512h         q14, q3, v25.2D
 970     __ sha512h2(v8, __ T2D, v27, v21);                 //       sha512h2                q8, q27, v21.2D
 971     __ sha512su0(v26, __ T2D, v26);                    //       sha512su0               v26.2D, v26.2D
 972     __ sha512su1(v24, __ T2D, v22, v0);                //       sha512su1               v24.2D, v22.2D, v0.2D
 973 
 974 // SVEVectorOp
 975     __ sve_add(z4, __ B, z6, z17);                     //       add     z4.b, z6.b, z17.b
 976     __ sve_sub(z3, __ H, z15, z1);                     //       sub     z3.h, z15.h, z1.h
 977     __ sve_fadd(z6, __ D, z5, z9);                     //       fadd    z6.d, z5.d, z9.d
 978     __ sve_fmul(z7, __ D, z20, z22);                   //       fmul    z7.d, z20.d, z22.d
 979     __ sve_fsub(z5, __ D, z10, z8);                    //       fsub    z5.d, z10.d, z8.d
 980     __ sve_abs(z30, __ B, p1, z17);                    //       abs     z30.b, p1/m, z17.b
 981     __ sve_add(z11, __ B, p7, z28);                    //       add     z11.b, p7/m, z11.b, z28.b
 982     __ sve_asr(z26, __ H, p5, z28);                    //       asr     z26.h, p5/m, z26.h, z28.h
 983     __ sve_cnt(z13, __ D, p7, z16);                    //       cnt     z13.d, p7/m, z16.d
 984     __ sve_lsl(z5, __ H, p0, z13);                     //       lsl     z5.h, p0/m, z5.h, z13.h
 985     __ sve_lsr(z15, __ S, p2, z26);                    //       lsr     z15.s, p2/m, z15.s, z26.s
 986     __ sve_mul(z11, __ S, p1, z22);                    //       mul     z11.s, p1/m, z11.s, z22.s
 987     __ sve_neg(z4, __ S, p0, z19);                     //       neg     z4.s, p0/m, z19.s
 988     __ sve_not(z17, __ H, p3, z14);                    //       not     z17.h, p3/m, z14.h
 989     __ sve_smax(z2, __ S, p4, z3);                     //       smax    z2.s, p4/m, z2.s, z3.s
 990     __ sve_smin(z23, __ B, p1, z6);                    //       smin    z23.b, p1/m, z23.b, z6.b
 991     __ sve_sub(z17, __ S, p3, z27);                    //       sub     z17.s, p3/m, z17.s, z27.s
 992     __ sve_fabs(z16, __ D, p1, z2);                    //       fabs    z16.d, p1/m, z2.d
 993     __ sve_fadd(z3, __ D, p1, z6);                     //       fadd    z3.d, p1/m, z3.d, z6.d
 994     __ sve_fdiv(z19, __ D, p3, z12);                   //       fdiv    z19.d, p3/m, z19.d, z12.d
 995     __ sve_fmax(z8, __ D, p6, z19);                    //       fmax    z8.d, p6/m, z8.d, z19.d
 996     __ sve_fmin(z0, __ S, p2, z23);                    //       fmin    z0.s, p2/m, z0.s, z23.s
 997     __ sve_fmul(z19, __ D, p7, z13);                   //       fmul    z19.d, p7/m, z19.d, z13.d
 998     __ sve_fneg(z6, __ S, p0, z7);                     //       fneg    z6.s, p0/m, z7.s
 999     __ sve_frintm(z17, __ S, p6, z8);                  //       frintm  z17.s, p6/m, z8.s
1000     __ sve_frintn(z22, __ D, p5, z22);                 //       frintn  z22.d, p5/m, z22.d
1001     __ sve_frintp(z2, __ D, p0, z15);                  //       frintp  z2.d, p0/m, z15.d
1002     __ sve_fsqrt(z20, __ D, p1, z4);                   //       fsqrt   z20.d, p1/m, z4.d
1003     __ sve_fsub(z7, __ D, p0, z8);                     //       fsub    z7.d, p0/m, z7.d, z8.d
1004     __ sve_fmla(z19, __ S, p5, z4, z15);               //       fmla    z19.s, p5/m, z4.s, z15.s
1005     __ sve_fmls(z22, __ D, p2, z25, z5);               //       fmls    z22.d, p2/m, z25.d, z5.d
1006     __ sve_fnmla(z16, __ S, p3, z22, z11);             //       fnmla   z16.s, p3/m, z22.s, z11.s
1007     __ sve_fnmls(z13, __ D, p2, z20, z16);             //       fnmls   z13.d, p2/m, z20.d, z16.d
1008     __ sve_mla(z15, __ H, p1, z4, z17);                //       mla     z15.h, p1/m, z4.h, z17.h
1009     __ sve_mls(z6, __ S, p7, z4, z28);                 //       mls     z6.s, p7/m, z4.s, z28.s
1010     __ sve_and(z29, z26, z9);                          //       and     z29.d, z26.d, z9.d
1011     __ sve_eor(z2, z11, z28);                          //       eor     z2.d, z11.d, z28.d
1012     __ sve_orr(z7, z1, z26);                           //       orr     z7.d, z1.d, z26.d
1013     __ sve_bic(z17, z14, z8);                          //       bic     z17.d, z14.d, z8.d
1014     __ sve_uzp1(z21, __ S, z24, z5);                   //       uzp1    z21.s, z24.s, z5.s
1015     __ sve_uzp2(z21, __ S, z17, z22);                  //       uzp2    z21.s, z17.s, z22.s
1016 
1017 // SVEReductionOp
1018     __ sve_andv(v29, __ B, p5, z19);                   //       andv b29, p5, z19.b
1019     __ sve_orv(v4, __ B, p4, z23);                     //       orv b4, p4, z23.b
1020     __ sve_eorv(v19, __ D, p1, z23);                   //       eorv d19, p1, z23.d
1021     __ sve_smaxv(v19, __ H, p0, z8);                   //       smaxv h19, p0, z8.h
1022     __ sve_sminv(v14, __ D, p6, z17);                  //       sminv d14, p6, z17.d
1023     __ sve_fminv(v21, __ S, p1, z30);                  //       fminv s21, p1, z30.s
1024     __ sve_fmaxv(v10, __ S, p5, z12);                  //       fmaxv s10, p5, z12.s
1025     __ sve_fadda(v9, __ D, p1, z24);                   //       fadda d9, p1, d9, z24.d
1026     __ sve_uaddv(v4, __ H, p6, z6);                    //       uaddv d4, p6, z6.h
1027 
1028     __ bind(forth);
1029 
1030 /*
1031 */
1032 
1033   static const unsigned int insns[] =
1034   {
1035     0x8b0d82fa,     0xcb49970c,     0xab889dfc,     0xeb9ee787,
1036     0x0b9b3ec9,     0x4b9179a3,     0x2b88474e,     0x6b8c56c0,
1037     0x8a1a51e0,     0xaa11f4ba,     0xca0281b8,     0xea918c7c,
1038     0x0a5d4a19,     0x2a4b262d,     0x4a513ca5,     0x6a9b6ae2,
1039     0x8a70b79b,     0xaaba9728,     0xca6dfe3d,     0xea627f1c,
1040     0x0aa70f53,     0x2aaa0f06,     0x4a6176a4,     0x6a604eb0,
1041     0x1105ed91,     0x3100583e,     0x5101f8bd,     0x710f0306,
1042     0x9101a1a0,     0xb10a5cc8,     0xd10810aa,     0xf10fd061,
1043     0x120cb166,     0x321764bc,     0x52174681,     0x720c0227,
1044     0x9241018e,     0xb25a2969,     0xd278b411,     0xf26aad01,
1045     0x14000000,     0x17ffffd7,     0x1400034c,     0x94000000,
1046     0x97ffffd4,     0x94000349,     0x3400000a,     0x34fffa2a,
1047     0x340068ca,     0x35000008,     0x35fff9c8,     0x35006868,
1048     0xb400000b,     0xb4fff96b,     0xb400680b,     0xb500001d,
1049     0xb5fff91d,     0xb50067bd,     0x10000013,     0x10fff8b3,
1050     0x10006753,     0x90000013,     0x36300016,     0x3637f836,
1051     0x363066d6,     0x3758000c,     0x375ff7cc,     0x3758666c,
1052     0x128313a0,     0x528a32c7,     0x7289173b,     0x92ab3acc,
1053     0xd2a0bf94,     0xf2c285e8,     0x9358722f,     0x330e652f,
1054     0x53067f3b,     0x93577c53,     0xb34a1aac,     0xd35a4016,
1055     0x13946c63,     0x93c3dbc8,     0x54000000,     0x54fff5a0,
1056     0x54006440,     0x54000001,     0x54fff541,     0x540063e1,
1057     0x54000002,     0x54fff4e2,     0x54006382,     0x54000002,
1058     0x54fff482,     0x54006322,     0x54000003,     0x54fff423,
1059     0x540062c3,     0x54000003,     0x54fff3c3,     0x54006263,
1060     0x54000004,     0x54fff364,     0x54006204,     0x54000005,
1061     0x54fff305,     0x540061a5,     0x54000006,     0x54fff2a6,
1062     0x54006146,     0x54000007,     0x54fff247,     0x540060e7,
1063     0x54000008,     0x54fff1e8,     0x54006088,     0x54000009,
1064     0x54fff189,     0x54006029,     0x5400000a,     0x54fff12a,
1065     0x54005fca,     0x5400000b,     0x54fff0cb,     0x54005f6b,
1066     0x5400000c,     0x54fff06c,     0x54005f0c,     0x5400000d,
1067     0x54fff00d,     0x54005ead,     0x5400000e,     0x54ffefae,
1068     0x54005e4e,     0x5400000f,     0x54ffef4f,     0x54005def,
1069     0xd40658e1,     0xd4014d22,     0xd4046543,     0xd4273f60,
1070     0xd44cad80,     0xd503201f,     0xd69f03e0,     0xd6bf03e0,
1071     0xd5033fdf,     0xd5033e9f,     0xd50332bf,     0xd61f0200,
1072     0xd63f0280,     0xc80a7d1b,     0xc800fea1,     0xc85f7fb1,
1073     0xc85fff9d,     0xc89ffee1,     0xc8dffe95,     0x88167e7b,
1074     0x880bfcd0,     0x885f7c11,     0x885ffd44,     0x889ffed8,
1075     0x88dffe6a,     0x48017fc5,     0x4808fe2c,     0x485f7dc9,
1076     0x485ffc27,     0x489ffe05,     0x48dffd82,     0x080a7c6c,
1077     0x081cff4e,     0x085f7d5e,     0x085ffeae,     0x089ffd2d,
1078     0x08dfff76,     0xc87f4d7c,     0xc87fcc5e,     0xc8220417,
1079     0xc82cb5f0,     0x887f55b1,     0x887ff90b,     0x88382c2d,
1080     0x883aedb5,     0xf819928b,     0xb803e21c,     0x381f713b,
1081     0x781ce322,     0xf850f044,     0xb85e129e,     0x385e92f1,
1082     0x785ff35d,     0x39801921,     0x7881318b,     0x78dce02b,
1083     0xb8829313,     0xfc45f318,     0xbc5d50af,     0xfc001375,
1084     0xbc1951b7,     0xf8008c0a,     0xb801dc03,     0x38009dca,
1085     0x781fdf3d,     0xf8570e0c,     0xb85faecc,     0x385f6d6d,
1086     0x785ebea0,     0x38804cd7,     0x789cbce3,     0x78df9c9c,
1087     0xb89eed18,     0xfc40cd6e,     0xbc5bdd93,     0xfc103c14,
1088     0xbc040c08,     0xf81a2783,     0xb81ca4eb,     0x381e855b,
1089     0x7801b4e6,     0xf853654d,     0xb85d74af,     0x384095a2,
1090     0x785ec5bc,     0x389e15a9,     0x789dc703,     0x78c06474,
1091     0xb89ff667,     0xfc57e51e,     0xbc4155f9,     0xfc05a6ee,
1092     0xbc1df408,     0xf835da2a,     0xb836d9a4,     0x3833580d,
1093     0x7826cb6c,     0xf8706900,     0xb87ae880,     0x3865db2e,
1094     0x78714889,     0x38a7789b,     0x78beca2f,     0x78f6c810,
1095     0xb8bef956,     0xfc6afabd,     0xbc734963,     0xfc3d5b8d,
1096     0xbc25fbb7,     0xf9189d05,     0xb91ecb1d,     0x39187a33,
1097     0x791f226d,     0xf95aa2f3,     0xb9587bb7,     0x395f7176,
1098     0x795d9143,     0x399e7e08,     0x799a2697,     0x79df3422,
1099     0xb99c2624,     0xfd5c2374,     0xbd5fa1d9,     0xfd1d595a,
1100     0xbd1b1869,     0x58004e3b,     0x1800000b,     0xf8945060,
1101     0xd8000000,     0xf8ae6ba0,     0xf99a0080,     0x1a070035,
1102     0x3a0700a8,     0x5a0e0367,     0x7a11009b,     0x9a000380,
1103     0xba1e030c,     0xda0f0320,     0xfa030301,     0x0b340b11,
1104     0x2b2a278d,     0xcb22aa0f,     0x6b2d29bd,     0x8b2cce8c,
1105     0xab2b877e,     0xcb21c8ee,     0xeb3ba47d,     0x3a4d400e,
1106     0x7a5132c6,     0xba5e622e,     0xfa53814c,     0x3a52d8c2,
1107     0x7a4d8924,     0xba4b3aab,     0xfa4d7882,     0x1a96804c,
1108     0x1a912618,     0x5a90b0e6,     0x5a96976b,     0x9a9db06a,
1109     0x9a9b374c,     0xda95c14f,     0xda89c6fe,     0x5ac0015e,
1110     0x5ac005fd,     0x5ac00bdd,     0x5ac012b9,     0x5ac01404,
1111     0xdac002b1,     0xdac0061d,     0xdac00a95,     0xdac00e66,
1112     0xdac0107e,     0xdac01675,     0x1ac00b0b,     0x1ace0f3b,
1113     0x1ad121c3,     0x1ad825e7,     0x1ad92a3c,     0x1adc2f42,
1114     0x9ada0b25,     0x9ad10e1b,     0x9acc22a6,     0x9acc2480,
1115     0x9adc2a3b,     0x9ad12c5c,     0x9bce7dea,     0x9b597c6e,
1116     0x1b0e166f,     0x1b1ae490,     0x9b023044,     0x9b089e3d,
1117     0x9b391083,     0x9b24c73a,     0x9bb15f40,     0x9bbcc6af,
1118     0x7ea3d55b,     0x1e3908e0,     0x1e2f18c9,     0x1e2a29fd,
1119     0x1e273a22,     0x7ef7d56b,     0x1e770ba7,     0x1e6b1b6e,
1120     0x1e78288b,     0x1e6e39ec,     0x1f1c3574,     0x1f17f98b,
1121     0x1f2935da,     0x1f2574ea,     0x1f4b306f,     0x1f5ec7cf,
1122     0x1f6f3e93,     0x1f6226a9,     0x1e2040fb,     0x1e20c3dd,
1123     0x1e214031,     0x1e21c0c2,     0x1e22c06a,     0x1e604178,
1124     0x1e60c027,     0x1e61400b,     0x1e61c223,     0x1e6240dc,
1125     0x1e3800d6,     0x9e380360,     0x1e78005a,     0x9e7800e5,
1126     0x1e22017c,     0x9e2201b9,     0x1e6202eb,     0x9e620113,
1127     0x1e2602b1,     0x9e660299,     0x1e270233,     0x9e6703a2,
1128     0x1e2822c0,     0x1e7322a0,     0x1e202288,     0x1e602168,
1129     0x293c19f4,     0x2966387b,     0x69762970,     0xa9041dc7,
1130     0xa9475c0c,     0x29b61ccd,     0x29ee3c5e,     0x69ee0764,
1131     0xa9843977,     0xa9f46ebd,     0x28ba16b6,     0x28fc44db,
1132     0x68f61430,     0xa8b352cd,     0xa8c56d5e,     0x28024565,
1133     0x2874134e,     0xa8027597,     0xa87b1aa0,     0x0c40734f,
1134     0x4cdfa177,     0x0cc76ee8,     0x4cdf2733,     0x0d40c23d,
1135     0x4ddfcaf8,     0x0dd9ccaa,     0x4c408d51,     0x0cdf85ec,
1136     0x4d60c239,     0x0dffcbc1,     0x4de9ce30,     0x4cc24999,
1137     0x0c404a7a,     0x4d40e6af,     0x4ddfe9b9,     0x0dddef8e,
1138     0x4cdf07b1,     0x0cc000fb,     0x0d60e238,     0x0dffe740,
1139     0x0de2eb2c,     0x0e31baf6,     0x4e31bb9b,     0x0e71b8a4,
1140     0x4e71b907,     0x4eb1b8e6,     0x0e30a841,     0x4e30ab7a,
1141     0x0e70aa0f,     0x4e70a862,     0x4eb0a9cd,     0x6e30f9cd,
1142     0x0e31ab38,     0x2e31ab17,     0x4e31a8a4,     0x6e31aa93,
1143     0x0e71aa0f,     0x2e71a820,     0x4e71a8a4,     0x6e71aab4,
1144     0x4eb1a98b,     0x6eb1abdd,     0x6eb0fa0f,     0x7e30fad5,
1145     0x7e70f8a4,     0x7eb0f9ee,     0x7ef0faf6,     0x0e20bb59,
1146     0x4e20b8e6,     0x0e60b9ac,     0x4e60b9ee,     0x0ea0b9cd,
1147     0x4ea0b9ee,     0x4ee0b949,     0x0ea0fb59,     0x4ea0fbbc,
1148     0x4ee0f96a,     0x2ea0fa93,     0x6ea0f98b,     0x6ee0fa51,
1149     0x2ea1fad5,     0x6ea1fa0f,     0x6ee1fab4,     0x2e205b17,
1150     0x6e205b7a,     0x0e271cc5,     0x4e281ce6,     0x0eb11e0f,
1151     0x4eb11e0f,     0x2e3b1f59,     0x6e321e30,     0x0e3d879b,
1152     0x4e3a8738,     0x0e71860f,     0x4e7b8759,     0x0eb085ee,
1153     0x4eac856a,     0x4eef85cd,     0x0e30d5ee,     0x4e36d6b4,
1154     0x4e63d441,     0x2e3886f6,     0x6e2087fe,     0x2e7085ee,
1155     0x6e648462,     0x2ea884e6,     0x6ea58483,     0x6ee98507,
1156     0x0ebad738,     0x4ea2d420,     0x4efdd79b,     0x0e3f9fdd,
1157     0x4e279cc5,     0x0e679cc5,     0x4e7f9fdd,     0x0ead9d8b,
1158     0x4ebb9f59,     0x2ea2d420,     0x6ea0d7fe,     0x6ee2d420,
1159     0x2e33de51,     0x6e3edfbc,     0x6e7bdf59,     0x0e6b9549,
1160     0x4e7b9759,     0x0eae95ac,     0x4eb1960f,     0x0e2dcd8b,
1161     0x4e2ccd6a,     0x4e73ce51,     0x2e7a9738,     0x6e7796d5,
1162     0x2eb99717,     0x6ea29420,     0x0eb2ce30,     0x4eaccd6a,
1163     0x4ee8cce6,     0x2e3effbc,     0x6e28fce6,     0x6e67fcc5,
1164     0x0e2764c5,     0x4e3666b4,     0x0e736651,     0x4e71660f,
1165     0x0eb36651,     0x4ebf67dd,     0x0e3ca77a,     0x4e3ea7bc,
1166     0x0e63a441,     0x4e7da79b,     0x0ea2a420,     0x4eb6a6b4,
1167     0x0e3ef7bc,     0x4e31f60f,     0x4e6ef5ac,     0x0e2c6d6a,
1168     0x4e3e6fbc,     0x0e7e6fbc,     0x4e756e93,     0x0eb86ef6,
1169     0x4eac6d6a,     0x0e26aca4,     0x4e20affe,     0x0e76aeb4,
1170     0x4e6aad28,     0x0ea0affe,     0x4eb3ae51,     0x0eacf56a,
1171     0x4ebdf79b,     0x4ee4f462,     0x2e3a8f38,     0x6e268ca4,
1172     0x2e658c83,     0x6e6a8d28,     0x2eb88ef6,     0x6eb38e51,
1173     0x6eef8dcd,     0x0e26e4a4,     0x4e3ee7bc,     0x4e79e717,
1174     0x0e3736d5,     0x4e3b3759,     0x0e7a3738,     0x4e653483,
1175     0x0eb93717,     0x4ebc377a,     0x4ef93717,     0x2e3035ee,
1176     0x6e3736d5,     0x2e653483,     0x6e793717,     0x2eaa3528,
1177     0x6eba3738,     0x6ef53693,     0x2e313e0f,     0x6e323e30,
1178     0x2e643c62,     0x6e633c41,     0x2ea23c20,     0x6eba3f38,
1179     0x6ee63ca4,     0x2ea5e483,     0x6eade58b,     0x6ee0e7fe,
1180     0x0e3d3f9b,     0x4e2b3d49,     0x0e7b3f59,     0x4e643c62,
1181     0x0eae3dac,     0x4eb33e51,     0x4ee03ffe,     0x2e23e441,
1182     0x6e2ee5ac,     0x6e7ee7bc,     0xba5fd3e3,     0x3a5f03e5,
1183     0xfa411be4,     0x7a42cbe2,     0x93df03ff,     0xc820ffff,
1184     0x8822fc7f,     0xc8247cbf,     0x88267fff,     0x4e010fe0,
1185     0x4e081fe1,     0x4e0c1fe1,     0x4e0a1fe1,     0x4e071fe1,
1186     0x4e042c20,     0x4e062c20,     0x4e052c20,     0x4e083c20,
1187     0x0e0c3c20,     0x0e0a3c20,     0x0e073c20,     0x9eae0020,
1188     0x4cc0ac3f,     0x05a08020,     0x05104fe0,     0x05505001,
1189     0x05906fe2,     0x05d03005,     0x05101fea,     0x05901feb,
1190     0x04b0e3e0,     0x0470e7e1,     0x042f9c20,     0x043f9c35,
1191     0x047f9c20,     0x04ff9c20,     0x04299420,     0x04319160,
1192     0x0461943e,     0x04a19020,     0x042053ff,     0x047f5401,
1193     0x25208028,     0x2538cfe0,     0x2578d001,     0x25b8efe2,
1194     0x25f8f007,     0x2538dfea,     0x25b8dfeb,     0xa400a3e0,
1195     0xa420a7e0,     0xa4484be0,     0xa467afe0,     0xa4a8a7ea,
1196     0xa547a814,     0xa4084ffe,     0xa55c53e0,     0xa5e1540b,
1197     0xe400fbf6,     0xe408ffff,     0xe420e7e0,     0xe4484be0,
1198     0xe460efe0,     0xe547e400,     0xe4014be0,     0xe4a84fe0,
1199     0xe5f15000,     0x858043e0,     0x85a043ff,     0xe59f5d08,
1200     0x0420e3e9,     0x0460e3ea,     0x04a0e3eb,     0x04e0e3ec,
1201     0x25104042,     0x25104871,     0x25904861,     0x25904c92,
1202     0x05344020,     0x05744041,     0x05b44062,     0x05f44083,
1203     0x252c8840,     0x253c1420,     0x25681572,     0x25a21ce3,
1204     0x25ea1e34,     0x0522c020,     0x05e6c0a4,     0x2401a001,
1205     0x2443a051,     0x24858881,     0x24c78cd1,     0x24850891,
1206     0x24c70cc1,     0x250f9001,     0x25508051,     0x25802491,
1207     0x25df28c1,     0x25850c81,     0x251e10d1,     0x65816001,
1208     0x65c36051,     0x65854891,     0x65c74cc1,     0x05733820,
1209     0x05b238a4,     0x05f138e6,     0x0570396a,     0x65d0a001,
1210     0x65d6a443,     0x65d4a826,     0x6594ac26,     0x6554ac26,
1211     0x6556ac26,     0x6552ac26,     0x65cbac85,     0x65caac01,
1212     0x65dea833,     0x659ca509,     0x65d8a801,     0x65dcac01,
1213     0x655cb241,     0x0520a1e0,     0x0521a601,     0x052281e0,
1214     0x05238601,     0x04a14026,     0x0568aca7,     0x05b23230,
1215     0x853040af,     0xc5b040af,     0xe57080af,     0xe5b080af,
1216     0x1e601000,     0x1e603000,     0x1e621000,     0x1e623000,
1217     0x1e641000,     0x1e643000,     0x1e661000,     0x1e663000,
1218     0x1e681000,     0x1e683000,     0x1e6a1000,     0x1e6a3000,
1219     0x1e6c1000,     0x1e6c3000,     0x1e6e1000,     0x1e6e3000,
1220     0x1e701000,     0x1e703000,     0x1e721000,     0x1e723000,
1221     0x1e741000,     0x1e743000,     0x1e761000,     0x1e763000,
1222     0x1e781000,     0x1e783000,     0x1e7a1000,     0x1e7a3000,
1223     0x1e7c1000,     0x1e7c3000,     0x1e7e1000,     0x1e7e3000,
1224     0xf8208193,     0xf83101b6,     0xf83c13fe,     0xf821239a,
1225     0xf824309e,     0xf826535e,     0xf8304109,     0xf82c7280,
1226     0xf8216058,     0xf8a08309,     0xf8ba03d0,     0xf8a312ea,
1227     0xf8aa21e4,     0xf8a2310b,     0xf8aa522f,     0xf8a2418a,
1228     0xf8ac71af,     0xf8a26287,     0xf8fa8090,     0xf8e20184,
1229     0xf8f01215,     0xf8f022ab,     0xf8f7334c,     0xf8f751dc,
1230     0xf8eb4038,     0xf8ec715f,     0xf8f06047,     0xf863826d,
1231     0xf8710070,     0xf86113cb,     0xf86521e8,     0xf87d301e,
1232     0xf8745287,     0xf87742bc,     0xf87b70b9,     0xf8616217,
1233     0xb83f8185,     0xb82901fc,     0xb83d13f6,     0xb83320bf,
1234     0xb82e33f0,     0xb830529b,     0xb830416c,     0xb82973c6,
1235     0xb831639b,     0xb8be8147,     0xb8b4008a,     0xb8b81231,
1236     0xb8b623a3,     0xb8af3276,     0xb8b35056,     0xb8af4186,
1237     0xb8b071ab,     0xb8b763c1,     0xb8f38225,     0xb8e202d0,
1238     0xb8ed12aa,     0xb8fd219b,     0xb8fb3023,     0xb8ff5278,
1239     0xb8f14389,     0xb8fb70ef,     0xb8f563f7,     0xb87983e2,
1240     0xb87b0150,     0xb8771073,     0xb8702320,     0xb87a3057,
1241     0xb870508c,     0xb87c43be,     0xb87070db,     0xb86961fd,
1242     0xce273c87,     0xce080ac9,     0xce7e8e9b,     0xce808b45,
1243     0xce79806e,     0xce758768,     0xcec0835a,     0xce608ad8,
1244     0x043100c4,     0x046105e3,     0x65c900a6,     0x65d60a87,
1245     0x65c80545,     0x0416a63e,     0x04001f8b,     0x0450979a,
1246     0x04dabe0d,     0x045381a5,     0x04918b4f,     0x049006cb,
1247     0x0497a264,     0x045eadd1,     0x04881062,     0x040a04d7,
1248     0x04810f71,     0x04dca450,     0x65c084c3,     0x65cd8d93,
1249     0x65c69a68,     0x65878ae0,     0x65c29db3,     0x049da0e6,
1250     0x6582b911,     0x65c0b6d6,     0x65c1a1e2,     0x65cda494,
1251     0x65c18107,     0x65af1493,     0x65e52b36,     0x65ab4ed0,
1252     0x65f06a8d,     0x0451448f,     0x049c7c86,     0x0429335d,
1253     0x04bc3162,     0x047a3027,     0x04e831d1,     0x05a56b15,
1254     0x05b66e35,     0x041a367d,     0x041832e4,     0x04d926f3,
1255     0x04482113,     0x04ca3a2e,     0x658727d5,     0x6586358a,
1256     0x65d82709,     0x044138c4,
1257   };
1258 // END  Generated code -- do not edit
1259