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25 
26 #ifndef CPU_RISCV_C1_DEFS_RISCV_HPP
27 #define CPU_RISCV_C1_DEFS_RISCV_HPP
28 
29 // native word offsets from memory address (little endian)
30 enum {
31   pd_lo_word_offset_in_bytes = 0,
32   pd_hi_word_offset_in_bytes = BytesPerWord
33 };
34 
35 // explicit rounding operations are required to implement the strictFP mode
36 enum {
37   pd_strict_fp_requires_explicit_rounding = false
38 };
39 
40 // registers
41 enum {
42   pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
43   pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of float registers used during code emission
44 
45   // caller saved
46   pd_nof_caller_save_cpu_regs_frame_map = 13, // number of registers killed by calls
47   pd_nof_caller_save_fpu_regs_frame_map = 32, // number of float registers killed by calls
48 
49   pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
50   pd_last_callee_saved_reg = 21,
51 
52   pd_last_allocatable_cpu_reg = pd_nof_caller_save_cpu_regs_frame_map - 1,
53 
54   pd_nof_cpu_regs_reg_alloc
55     = pd_nof_caller_save_cpu_regs_frame_map,  // number of registers that are visible to register allocator
56   pd_nof_fpu_regs_reg_alloc = 32,  // number of float registers that are visible to register allocator
57 
58   pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan
59   pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of float registers visible to linear scan
60   pd_nof_xmm_regs_linearscan = 0, // don't have vector registers
61 
62   pd_first_cpu_reg  = 0,
63   pd_last_cpu_reg   = pd_nof_cpu_regs_reg_alloc - 1,
64   pd_first_byte_reg = 0,
65   pd_last_byte_reg  = pd_nof_cpu_regs_reg_alloc - 1,
66 
67   pd_first_fpu_reg  = pd_nof_cpu_regs_frame_map,
68   pd_last_fpu_reg   = pd_first_fpu_reg + 31,
69 
70   pd_first_callee_saved_fpu_reg_1 = 8 + pd_first_fpu_reg,
71   pd_last_callee_saved_fpu_reg_1  = 9 + pd_first_fpu_reg,
72   pd_first_callee_saved_fpu_reg_2 = 18 + pd_first_fpu_reg,
73   pd_last_callee_saved_fpu_reg_2  = 27 + pd_first_fpu_reg
74 };
75 
76 
77 // Encoding of float value in debug info.  This is true on x86 where
78 // floats are extended to doubles when stored in the stack, false for
79 // RISCV where floats and doubles are stored in their native form.
80 enum {
81   pd_float_saved_as_double = false
82 };
83 
84 #endif // CPU_RISCV_C1_DEFS_RISCV_HPP