1 /*
 2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
 4  * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
 5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 6  *
 7  * This code is free software; you can redistribute it and/or modify it
 8  * under the terms of the GNU General Public License version 2 only, as
 9  * published by the Free Software Foundation.
10  *
11  * This code is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14  * version 2 for more details (a copy is included in the LICENSE file that
15  * accompanied this code).
16  *
17  * You should have received a copy of the GNU General Public License version
18  * 2 along with this work; if not, write to the Free Software Foundation,
19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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26 
27 #ifndef CPU_RISCV_DISASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_DISASSEMBLER_RISCV_HPP
29 
30 static int pd_instruction_alignment() {
31   return 1;
32 }
33 
34 static const char* pd_cpu_opts() {
35   return "";
36 }
37 
38 // special-case instruction decoding.
39 // There may be cases where the binutils disassembler doesn't do
40 // the perfect job. In those cases, decode_instruction0 may kick in
41 // and do it right.
42 // If nothing had to be done, just return "here", otherwise return "here + instr_len(here)"
43 static address decode_instruction0(address here, outputStream* st, address virtual_begin = NULL) {
44   return here;
45 }
46 
47 // platform-specific instruction annotations (like value of loaded constants)
48 static void annotate(address pc, outputStream* st) {}
49 
50 #endif // CPU_RISCV_DISASSEMBLER_RISCV_HPP