1 //
2 // Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // archtecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, SOE, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, SOE, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 reg_class no_special_reg32 %{
653 return _NO_SPECIAL_REG32_mask;
654 %}
655
656 reg_class no_special_reg %{
657 return _NO_SPECIAL_REG_mask;
658 %}
659
660 reg_class ptr_reg %{
661 return _PTR_REG_mask;
662 %}
663
664 reg_class no_special_ptr_reg %{
665 return _NO_SPECIAL_PTR_REG_mask;
666 %}
667
668 // Class for 64 bit register r10
669 reg_class r10_reg(
670 R10, R10_H
671 );
672
673 // Class for 64 bit register r11
674 reg_class r11_reg(
675 R11, R11_H
676 );
677
678 // Class for 64 bit register r12
679 reg_class r12_reg(
680 R12, R12_H
681 );
682
683 // Class for 64 bit register r13
684 reg_class r13_reg(
685 R13, R13_H
686 );
687
688 // Class for 64 bit register r14
689 reg_class r14_reg(
690 R14, R14_H
691 );
692
693 // Class for 64 bit register r15
694 reg_class r15_reg(
695 R15, R15_H
696 );
697
698 // Class for 64 bit register r16
699 reg_class r16_reg(
700 R16, R16_H
701 );
702
703 // Class for method register
704 reg_class method_reg(
705 R31, R31_H
706 );
707
708 // Class for heapbase register
709 reg_class heapbase_reg(
710 R27, R27_H
711 );
712
713 // Class for java thread register
714 reg_class java_thread_reg(
715 R23, R23_H
716 );
717
718 reg_class r28_reg(
719 R28, R28_H
720 );
721
722 reg_class r29_reg(
723 R29, R29_H
724 );
725
726 reg_class r30_reg(
727 R30, R30_H
728 );
729
730 // Class for zero registesr
731 reg_class zr_reg(
732 R0, R0_H
733 );
734
735 // Class for thread register
736 reg_class thread_reg(
737 R4, R4_H
738 );
739
740 // Class for frame pointer register
741 reg_class fp_reg(
742 R8, R8_H
743 );
744
745 // Class for link register
746 reg_class ra_reg(
747 R1, R1_H
748 );
749
750 // Class for long sp register
751 reg_class sp_reg(
752 R2, R2_H
753 );
754
755 // Class for all float registers
756 reg_class float_reg(
757 F0,
758 F1,
759 F2,
760 F3,
761 F4,
762 F5,
763 F6,
764 F7,
765 F8,
766 F9,
767 F10,
768 F11,
769 F12,
770 F13,
771 F14,
772 F15,
773 F16,
774 F17,
775 F18,
776 F19,
777 F20,
778 F21,
779 F22,
780 F23,
781 F24,
782 F25,
783 F26,
784 F27,
785 F28,
786 F29,
787 F30,
788 F31
789 );
790
791 // Double precision float registers have virtual `high halves' that
792 // are needed by the allocator.
793 // Class for all double registers
794 reg_class double_reg(
795 F0, F0_H,
796 F1, F1_H,
797 F2, F2_H,
798 F3, F3_H,
799 F4, F4_H,
800 F5, F5_H,
801 F6, F6_H,
802 F7, F7_H,
803 F8, F8_H,
804 F9, F9_H,
805 F10, F10_H,
806 F11, F11_H,
807 F12, F12_H,
808 F13, F13_H,
809 F14, F14_H,
810 F15, F15_H,
811 F16, F16_H,
812 F17, F17_H,
813 F18, F18_H,
814 F19, F19_H,
815 F20, F20_H,
816 F21, F21_H,
817 F22, F22_H,
818 F23, F23_H,
819 F24, F24_H,
820 F25, F25_H,
821 F26, F26_H,
822 F27, F27_H,
823 F28, F28_H,
824 F29, F29_H,
825 F30, F30_H,
826 F31, F31_H
827 );
828
829 // Class for all RVV vector registers
830 reg_class vectora_reg(
831 V1, V1_H, V1_J, V1_K,
832 V2, V2_H, V2_J, V2_K,
833 V3, V3_H, V3_J, V3_K,
834 V4, V4_H, V4_J, V4_K,
835 V5, V5_H, V5_J, V5_K,
836 V6, V6_H, V6_J, V6_K,
837 V7, V7_H, V7_J, V7_K,
838 V8, V8_H, V8_J, V8_K,
839 V9, V9_H, V9_J, V9_K,
840 V10, V10_H, V10_J, V10_K,
841 V11, V11_H, V11_J, V11_K,
842 V12, V12_H, V12_J, V12_K,
843 V13, V13_H, V13_J, V13_K,
844 V14, V14_H, V14_J, V14_K,
845 V15, V15_H, V15_J, V15_K,
846 V16, V16_H, V16_J, V16_K,
847 V17, V17_H, V17_J, V17_K,
848 V18, V18_H, V18_J, V18_K,
849 V19, V19_H, V19_J, V19_K,
850 V20, V20_H, V20_J, V20_K,
851 V21, V21_H, V21_J, V21_K,
852 V22, V22_H, V22_J, V22_K,
853 V23, V23_H, V23_J, V23_K,
854 V24, V24_H, V24_J, V24_K,
855 V25, V25_H, V25_J, V25_K,
856 V26, V26_H, V26_J, V26_K,
857 V27, V27_H, V27_J, V27_K,
858 V28, V28_H, V28_J, V28_K,
859 V29, V29_H, V29_J, V29_K,
860 V30, V30_H, V30_J, V30_K,
861 V31, V31_H, V31_J, V31_K
862 );
863
864 // Class for 64 bit register f0
865 reg_class f0_reg(
866 F0, F0_H
867 );
868
869 // Class for 64 bit register f1
870 reg_class f1_reg(
871 F1, F1_H
872 );
873
874 // Class for 64 bit register f2
875 reg_class f2_reg(
876 F2, F2_H
877 );
878
879 // Class for 64 bit register f3
880 reg_class f3_reg(
881 F3, F3_H
882 );
883
884 // class for vector register v1
885 reg_class v1_reg(
886 V1, V1_H, V1_J, V1_K
887 );
888
889 // class for vector register v2
890 reg_class v2_reg(
891 V2, V2_H, V2_J, V2_K
892 );
893
894 // class for vector register v3
895 reg_class v3_reg(
896 V3, V3_H, V3_J, V3_K
897 );
898
899 // class for vector register v4
900 reg_class v4_reg(
901 V4, V4_H, V4_J, V4_K
902 );
903
904 // class for vector register v5
905 reg_class v5_reg(
906 V5, V5_H, V5_J, V5_K
907 );
908
909 // class for condition codes
910 reg_class reg_flags(RFLAGS);
911 %}
912
913 //----------DEFINITION BLOCK---------------------------------------------------
914 // Define name --> value mappings to inform the ADLC of an integer valued name
915 // Current support includes integer values in the range [0, 0x7FFFFFFF]
916 // Format:
917 // int_def <name> ( <int_value>, <expression>);
918 // Generated Code in ad_<arch>.hpp
919 // #define <name> (<expression>)
920 // // value == <int_value>
921 // Generated code in ad_<arch>.cpp adlc_verification()
922 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
923 //
924
925 // we follow the ppc-aix port in using a simple cost model which ranks
926 // register operations as cheap, memory ops as more expensive and
927 // branches as most expensive. the first two have a low as well as a
928 // normal cost. huge cost appears to be a way of saying don't do
929 // something
930
931 definitions %{
932 // The default cost (of a register move instruction).
933 int_def DEFAULT_COST ( 100, 100);
934 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
935 // multi, auipc, nop, logical, move
936 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
937 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
938 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
939 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
940 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
941 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivdi
942 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivsi
943 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fadd, fmul, fmadd
944 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fadd, fmul, fmadd
945 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
946 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
947 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
948 %}
949
950
951
952 //----------SOURCE BLOCK-------------------------------------------------------
953 // This is a block of C++ code which provides values, functions, and
954 // definitions necessary in the rest of the architecture description
955
956 source_hpp %{
957
958 #include "asm/macroAssembler.hpp"
959 #include "gc/shared/barrierSetAssembler.hpp"
960 #include "gc/shared/cardTable.hpp"
961 #include "gc/shared/cardTableBarrierSet.hpp"
962 #include "gc/shared/collectedHeap.hpp"
963 #include "opto/addnode.hpp"
964 #include "opto/convertnode.hpp"
965 #include "runtime/objectMonitor.hpp"
966
967 extern RegMask _ANY_REG32_mask;
968 extern RegMask _ANY_REG_mask;
969 extern RegMask _PTR_REG_mask;
970 extern RegMask _NO_SPECIAL_REG32_mask;
971 extern RegMask _NO_SPECIAL_REG_mask;
972 extern RegMask _NO_SPECIAL_PTR_REG_mask;
973
974 class CallStubImpl {
975
976 //--------------------------------------------------------------
977 //---< Used for optimization in Compile::shorten_branches >---
978 //--------------------------------------------------------------
979
980 public:
981 // Size of call trampoline stub.
982 static uint size_call_trampoline() {
983 return 0; // no call trampolines on this platform
984 }
985
986 // number of relocations needed by a call trampoline stub
987 static uint reloc_call_trampoline() {
988 return 0; // no call trampolines on this platform
989 }
990 };
991
992 class HandlerImpl {
993
994 public:
995
996 static int emit_exception_handler(CodeBuffer &cbuf);
997 static int emit_deopt_handler(CodeBuffer& cbuf);
998
999 static uint size_exception_handler() {
1000 return MacroAssembler::far_branch_size();
1001 }
1002
1003 static uint size_deopt_handler() {
1004 // count auipc + far branch
1005 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1006 }
1007 };
1008
1009 class Node::PD {
1010 public:
1011 enum NodeFlags {
1012 _last_flag = Node::_last_flag
1013 };
1014 };
1015
1016 bool is_CAS(int opcode, bool maybe_volatile);
1017
1018 // predicate controlling translation of CompareAndSwapX
1019 bool needs_acquiring_load_reserved(const Node *load);
1020
1021 // predicate controlling addressing modes
1022 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1023 %}
1024
1025 source %{
1026
1027 // Derived RegMask with conditionally allocatable registers
1028
1029 RegMask _ANY_REG32_mask;
1030 RegMask _ANY_REG_mask;
1031 RegMask _PTR_REG_mask;
1032 RegMask _NO_SPECIAL_REG32_mask;
1033 RegMask _NO_SPECIAL_REG_mask;
1034 RegMask _NO_SPECIAL_PTR_REG_mask;
1035
1036 void reg_mask_init() {
1037
1038 _ANY_REG32_mask = _ALL_REG32_mask;
1039 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1040
1041 _ANY_REG_mask = _ALL_REG_mask;
1042 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1043
1044 _PTR_REG_mask = _ALL_REG_mask;
1045 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1046
1047 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1048 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1049
1050 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1051 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1052
1053 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1054 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1055
1056 // x27 is not allocatable when compressed oops is on
1057 if (UseCompressedOops) {
1058 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1059 _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
1060 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
1061 }
1062
1063 // x8 is not allocatable when PreserveFramePointer is on
1064 if (PreserveFramePointer) {
1065 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1066 _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
1067 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
1068 }
1069 }
1070
1071 void PhaseOutput::pd_perform_mach_node_analysis() {
1072 }
1073
1074 int MachNode::pd_alignment_required() const {
1075 return 1;
1076 }
1077
1078 int MachNode::compute_padding(int current_offset) const {
1079 return 0;
1080 }
1081
1082 // is_CAS(int opcode, bool maybe_volatile)
1083 //
1084 // return true if opcode is one of the possible CompareAndSwapX
1085 // values otherwise false.
1086 bool is_CAS(int opcode, bool maybe_volatile)
1087 {
1088 switch (opcode) {
1089 // We handle these
1090 case Op_CompareAndSwapI:
1091 case Op_CompareAndSwapL:
1092 case Op_CompareAndSwapP:
1093 case Op_CompareAndSwapN:
1094 case Op_ShenandoahCompareAndSwapP:
1095 case Op_ShenandoahCompareAndSwapN:
1096 case Op_CompareAndSwapB:
1097 case Op_CompareAndSwapS:
1098 case Op_GetAndSetI:
1099 case Op_GetAndSetL:
1100 case Op_GetAndSetP:
1101 case Op_GetAndSetN:
1102 case Op_GetAndAddI:
1103 case Op_GetAndAddL:
1104 return true;
1105 case Op_CompareAndExchangeI:
1106 case Op_CompareAndExchangeN:
1107 case Op_CompareAndExchangeB:
1108 case Op_CompareAndExchangeS:
1109 case Op_CompareAndExchangeL:
1110 case Op_CompareAndExchangeP:
1111 case Op_WeakCompareAndSwapB:
1112 case Op_WeakCompareAndSwapS:
1113 case Op_WeakCompareAndSwapI:
1114 case Op_WeakCompareAndSwapL:
1115 case Op_WeakCompareAndSwapP:
1116 case Op_WeakCompareAndSwapN:
1117 case Op_ShenandoahWeakCompareAndSwapP:
1118 case Op_ShenandoahWeakCompareAndSwapN:
1119 case Op_ShenandoahCompareAndExchangeP:
1120 case Op_ShenandoahCompareAndExchangeN:
1121 return maybe_volatile;
1122 default:
1123 return false;
1124 }
1125 }
1126
1127 // predicate controlling translation of CAS
1128 //
1129 // returns true if CAS needs to use an acquiring load otherwise false
1130 bool needs_acquiring_load_reserved(const Node *n)
1131 {
1132 assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1133
1134 LoadStoreNode* ldst = n->as_LoadStore();
1135 if (n != NULL && is_CAS(n->Opcode(), false)) {
1136 assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
1137 } else {
1138 return ldst != NULL && ldst->trailing_membar() != NULL;
1139 }
1140 // so we can just return true here
1141 return true;
1142 }
1143 #define __ _masm.
1144
1145 // advance declarations for helper functions to convert register
1146 // indices to register objects
1147
1148 // the ad file has to provide implementations of certain methods
1149 // expected by the generic code
1150 //
1151 // REQUIRED FUNCTIONALITY
1152
1153 //=============================================================================
1154
1155 // !!!!! Special hack to get all types of calls to specify the byte offset
1156 // from the start of the call to the point where the return address
1157 // will point.
1158
1159 int MachCallStaticJavaNode::ret_addr_offset()
1160 {
1161 // jal
1162 return 1 * NativeInstruction::instruction_size;
1163 }
1164
1165 int MachCallDynamicJavaNode::ret_addr_offset()
1166 {
1167 return 7 * NativeInstruction::instruction_size; // movptr, jal
1168 }
1169
1170 int MachCallRuntimeNode::ret_addr_offset() {
1171 // for generated stubs the call will be
1172 // jal(addr)
1173 // or with far branches
1174 // jal(trampoline_stub)
1175 // for real runtime callouts it will be 11 instructions
1176 // see riscv_enc_java_to_runtime
1177 // la(t1, retaddr) -> auipc + addi
1178 // la(t0, RuntimeAddress(addr)) -> lui + addi + slli + addi + slli + addi
1179 // addi(sp, sp, -2 * wordSize) -> addi
1180 // sd(t1, Address(sp, wordSize)) -> sd
1181 // jalr(t0) -> jalr
1182 CodeBlob *cb = CodeCache::find_blob(_entry_point);
1183 if (cb != NULL) {
1184 return 1 * NativeInstruction::instruction_size;
1185 } else {
1186 return 11 * NativeInstruction::instruction_size;
1187 }
1188 }
1189
1190 int MachCallNativeNode::ret_addr_offset() {
1191 Unimplemented();
1192 return -1;
1193 }
1194
1195 //
1196 // Compute padding required for nodes which need alignment
1197 //
1198
1199 // With RVC a call instruction may get 2-byte aligned.
1200 // The address of the call instruction needs to be 4-byte aligned to
1201 // ensure that it does not span a cache line so that it can be patched.
1202 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1203 {
1204 // to make sure the address of jal 4-byte aligned.
1205 return align_up(current_offset, alignment_required()) - current_offset;
1206 }
1207
1208 // With RVC a call instruction may get 2-byte aligned.
1209 // The address of the call instruction needs to be 4-byte aligned to
1210 // ensure that it does not span a cache line so that it can be patched.
1211 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1212 {
1213 // skip the movptr in MacroAssembler::ic_call():
1214 // lui + addi + slli + addi + slli + addi
1215 // Though movptr() has already 4-byte aligned with or without RVC,
1216 // We need to prevent from further changes by explicitly calculating the size.
1217 const int movptr_size = 6 * NativeInstruction::instruction_size;
1218 current_offset += movptr_size;
1219 // to make sure the address of jal 4-byte aligned.
1220 return align_up(current_offset, alignment_required()) - current_offset;
1221 }
1222
1223 //=============================================================================
1224
1225 #ifndef PRODUCT
1226 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1227 assert_cond(st != NULL);
1228 st->print("BREAKPOINT");
1229 }
1230 #endif
1231
1232 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 C2_MacroAssembler _masm(&cbuf);
1234 Assembler::CompressibleRegion cr(&_masm);
1235 __ ebreak();
1236 }
1237
1238 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1239 return MachNode::size(ra_);
1240 }
1241
1242 //=============================================================================
1243
1244 #ifndef PRODUCT
1245 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1246 st->print("nop \t# %d bytes pad for loops and calls", _count);
1247 }
1248 #endif
1249
1250 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1251 C2_MacroAssembler _masm(&cbuf);
1252 Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
1253 for (int i = 0; i < _count; i++) {
1254 __ nop();
1255 }
1256 }
1257
1258 uint MachNopNode::size(PhaseRegAlloc*) const {
1259 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1260 }
1261
1262 //=============================================================================
1263 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1264
1265 int ConstantTable::calculate_table_base_offset() const {
1266 return 0; // absolute addressing, no offset
1267 }
1268
1269 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1270 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1271 ShouldNotReachHere();
1272 }
1273
1274 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1275 // Empty encoding
1276 }
1277
1278 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1279 return 0;
1280 }
1281
1282 #ifndef PRODUCT
1283 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1284 assert_cond(st != NULL);
1285 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1286 }
1287 #endif
1288
1289 #ifndef PRODUCT
1290 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1291 assert_cond(st != NULL && ra_ != NULL);
1292 Compile* C = ra_->C;
1293
1294 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1295
1296 if (C->output()->need_stack_bang(framesize)) {
1297 st->print("# stack bang size=%d\n\t", framesize);
1298 }
1299
1300 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1301 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1302 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1303 st->print("sub sp, sp, #%d\n\t", framesize);
1304
1305 if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
1306 st->print("ld t0, [guard]\n\t");
1307 st->print("membar LoadLoad\n\t");
1308 st->print("ld t1, [xthread, #thread_disarmed_offset]\n\t");
1309 st->print("beq t0, t1, skip\n\t");
1310 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1311 st->print("j skip\n\t");
1312 st->print("guard: int\n\t");
1313 st->print("skip:\n\t");
1314 }
1315 }
1316 #endif
1317
1318 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1319 assert_cond(ra_ != NULL);
1320 Compile* C = ra_->C;
1321 C2_MacroAssembler _masm(&cbuf);
1322
1323 // n.b. frame size includes space for return pc and fp
1324 const int framesize = C->output()->frame_size_in_bytes();
1325
1326 // insert a nop at the start of the prolog so we can patch in a
1327 // branch if we need to invalidate the method later
1328 MacroAssembler::assert_alignment(__ pc());
1329 __ nop();
1330
1331 assert_cond(C != NULL);
1332
1333 if (C->clinit_barrier_on_entry()) {
1334 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1335
1336 Label L_skip_barrier;
1337
1338 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1339 __ clinit_barrier(t1, t0, &L_skip_barrier);
1340 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1341 __ bind(L_skip_barrier);
1342 }
1343
1344 int bangsize = C->output()->bang_size_in_bytes();
1345 if (C->output()->need_stack_bang(bangsize)) {
1346 __ generate_stack_overflow_check(bangsize);
1347 }
1348
1349 __ build_frame(framesize);
1350
1351 if (C->stub_function() == NULL) {
1352 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1353 bs->nmethod_entry_barrier(&_masm);
1354 }
1355
1356 if (VerifyStackAtCalls) {
1357 Unimplemented();
1358 }
1359
1360 C->output()->set_frame_complete(cbuf.insts_size());
1361
1362 if (C->has_mach_constant_base_node()) {
1363 // NOTE: We set the table base offset here because users might be
1364 // emitted before MachConstantBaseNode.
1365 ConstantTable& constant_table = C->output()->constant_table();
1366 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1367 }
1368 }
1369
1370 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1371 {
1372 assert_cond(ra_ != NULL);
1373 return MachNode::size(ra_); // too many variables; just compute it
1374 // the hard way
1375 }
1376
1377 int MachPrologNode::reloc() const
1378 {
1379 return 0;
1380 }
1381
1382 //=============================================================================
1383
1384 #ifndef PRODUCT
1385 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1386 assert_cond(st != NULL && ra_ != NULL);
1387 Compile* C = ra_->C;
1388 assert_cond(C != NULL);
1389 int framesize = C->output()->frame_size_in_bytes();
1390
1391 st->print("# pop frame %d\n\t", framesize);
1392
1393 if (framesize == 0) {
1394 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1395 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1396 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1397 } else {
1398 st->print("add sp, sp, #%d\n\t", framesize);
1399 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1400 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1401 }
1402
1403 if (do_polling() && C->is_method_compilation()) {
1404 st->print("# test polling word\n\t");
1405 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1406 st->print("bgtu sp, t0, #slow_path");
1407 }
1408 }
1409 #endif
1410
1411 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1412 assert_cond(ra_ != NULL);
1413 Compile* C = ra_->C;
1414 C2_MacroAssembler _masm(&cbuf);
1415 assert_cond(C != NULL);
1416 int framesize = C->output()->frame_size_in_bytes();
1417
1418 __ remove_frame(framesize);
1419
1420 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1421 __ reserved_stack_check();
1422 }
1423
1424 if (do_polling() && C->is_method_compilation()) {
1425 Label dummy_label;
1426 Label* code_stub = &dummy_label;
1427 if (!C->output()->in_scratch_emit_size()) {
1428 code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
1429 }
1430 __ relocate(relocInfo::poll_return_type);
1431 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1432 }
1433 }
1434
1435 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1436 assert_cond(ra_ != NULL);
1437 // Variable size. Determine dynamically.
1438 return MachNode::size(ra_);
1439 }
1440
1441 int MachEpilogNode::reloc() const {
1442 // Return number of relocatable values contained in this instruction.
1443 return 1; // 1 for polling page.
1444 }
1445 const Pipeline * MachEpilogNode::pipeline() const {
1446 return MachNode::pipeline_class();
1447 }
1448
1449 //=============================================================================
1450
1451 // Figure out which register class each belongs in: rc_int, rc_float or
1452 // rc_stack.
1453 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1454
1455 static enum RC rc_class(OptoReg::Name reg) {
1456
1457 if (reg == OptoReg::Bad) {
1458 return rc_bad;
1459 }
1460
1461 // we have 30 int registers * 2 halves
1462 // (t0 and t1 are omitted)
1463 int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2);
1464 if (reg < slots_of_int_registers) {
1465 return rc_int;
1466 }
1467
1468 // we have 32 float register * 2 halves
1469 int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers;
1470 if (reg < slots_of_int_registers + slots_of_float_registers) {
1471 return rc_float;
1472 }
1473
1474 // we have 32 vector register * 4 halves
1475 int slots_of_vector_registers = VectorRegisterImpl::max_slots_per_register * VectorRegisterImpl::number_of_registers;
1476 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1477 return rc_vector;
1478 }
1479
1480 // Between vector regs & stack is the flags regs.
1481 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1482
1483 return rc_stack;
1484 }
1485
1486 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1487 assert_cond(ra_ != NULL);
1488 Compile* C = ra_->C;
1489
1490 // Get registers to move.
1491 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1492 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1493 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1494 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1495
1496 enum RC src_hi_rc = rc_class(src_hi);
1497 enum RC src_lo_rc = rc_class(src_lo);
1498 enum RC dst_hi_rc = rc_class(dst_hi);
1499 enum RC dst_lo_rc = rc_class(dst_lo);
1500
1501 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1502
1503 if (src_hi != OptoReg::Bad) {
1504 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1505 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1506 "expected aligned-adjacent pairs");
1507 }
1508
1509 if (src_lo == dst_lo && src_hi == dst_hi) {
1510 return 0; // Self copy, no move.
1511 }
1512
1513 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1514 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1515 int src_offset = ra_->reg2offset(src_lo);
1516 int dst_offset = ra_->reg2offset(dst_lo);
1517
1518 if (bottom_type()->isa_vect() != NULL) {
1519 uint ireg = ideal_reg();
1520 if (ireg == Op_VecA && cbuf) {
1521 C2_MacroAssembler _masm(cbuf);
1522 Assembler::CompressibleRegion cr(&_masm);
1523 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1524 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1525 // stack to stack
1526 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1527 vector_reg_size_in_bytes);
1528 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1529 // vpr to stack
1530 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1531 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1532 // stack to vpr
1533 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1534 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1535 // vpr to vpr
1536 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1537 } else {
1538 ShouldNotReachHere();
1539 }
1540 }
1541 } else if (cbuf != NULL) {
1542 C2_MacroAssembler _masm(cbuf);
1543 Assembler::CompressibleRegion cr(&_masm);
1544 switch (src_lo_rc) {
1545 case rc_int:
1546 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1547 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1548 __ zero_extend(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1549 } else {
1550 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1551 }
1552 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1553 if (is64) {
1554 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1555 as_Register(Matcher::_regEncode[src_lo]));
1556 } else {
1557 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1558 as_Register(Matcher::_regEncode[src_lo]));
1559 }
1560 } else { // gpr --> stack spill
1561 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1562 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1563 }
1564 break;
1565 case rc_float:
1566 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1567 if (is64) {
1568 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1569 as_FloatRegister(Matcher::_regEncode[src_lo]));
1570 } else {
1571 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1572 as_FloatRegister(Matcher::_regEncode[src_lo]));
1573 }
1574 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1575 if (is64) {
1576 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1577 as_FloatRegister(Matcher::_regEncode[src_lo]));
1578 } else {
1579 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1580 as_FloatRegister(Matcher::_regEncode[src_lo]));
1581 }
1582 } else { // fpr --> stack spill
1583 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1584 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1585 is64, dst_offset);
1586 }
1587 break;
1588 case rc_stack:
1589 if (dst_lo_rc == rc_int) { // stack --> gpr load
1590 if (this->ideal_reg() == Op_RegI) {
1591 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1592 } else { // // zero extended for narrow oop or klass
1593 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1594 }
1595 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1596 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1597 is64, src_offset);
1598 } else { // stack --> stack copy
1599 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1600 if (this->ideal_reg() == Op_RegI) {
1601 __ unspill(t0, is64, src_offset);
1602 } else { // zero extended for narrow oop or klass
1603 __ unspillu(t0, is64, src_offset);
1604 }
1605 __ spill(t0, is64, dst_offset);
1606 }
1607 break;
1608 default:
1609 ShouldNotReachHere();
1610 }
1611 }
1612
1613 if (st != NULL) {
1614 st->print("spill ");
1615 if (src_lo_rc == rc_stack) {
1616 st->print("[sp, #%d] -> ", src_offset);
1617 } else {
1618 st->print("%s -> ", Matcher::regName[src_lo]);
1619 }
1620 if (dst_lo_rc == rc_stack) {
1621 st->print("[sp, #%d]", dst_offset);
1622 } else {
1623 st->print("%s", Matcher::regName[dst_lo]);
1624 }
1625 if (bottom_type()->isa_vect() != NULL) {
1626 int vsize = 0;
1627 if (ideal_reg() == Op_VecA) {
1628 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1629 } else {
1630 ShouldNotReachHere();
1631 }
1632 st->print("\t# vector spill size = %d", vsize);
1633 } else {
1634 st->print("\t# spill size = %d", is64 ? 64 : 32);
1635 }
1636 }
1637
1638 return 0;
1639 }
1640
1641 #ifndef PRODUCT
1642 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1643 if (ra_ == NULL) {
1644 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1645 } else {
1646 implementation(NULL, ra_, false, st);
1647 }
1648 }
1649 #endif
1650
1651 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1652 implementation(&cbuf, ra_, false, NULL);
1653 }
1654
1655 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1656 return MachNode::size(ra_);
1657 }
1658
1659 //=============================================================================
1660
1661 #ifndef PRODUCT
1662 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1663 assert_cond(ra_ != NULL && st != NULL);
1664 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1665 int reg = ra_->get_reg_first(this);
1666 st->print("add %s, sp, #%d\t# box lock",
1667 Matcher::regName[reg], offset);
1668 }
1669 #endif
1670
1671 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1672 C2_MacroAssembler _masm(&cbuf);
1673
1674 assert_cond(ra_ != NULL);
1675 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1676 int reg = ra_->get_encode(this);
1677
1678 if (is_imm_in_range(offset, 12, 0)) {
1679 __ addi(as_Register(reg), sp, offset);
1680 } else if (is_imm_in_range(offset, 32, 0)) {
1681 __ li32(t0, offset);
1682 __ add(as_Register(reg), sp, t0);
1683 } else {
1684 ShouldNotReachHere();
1685 }
1686 }
1687
1688 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1689 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1690 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1691
1692 if (is_imm_in_range(offset, 12, 0)) {
1693 return NativeInstruction::instruction_size;
1694 } else {
1695 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1696 }
1697 }
1698
1699 //=============================================================================
1700
1701 #ifndef PRODUCT
1702 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1703 {
1704 assert_cond(st != NULL);
1705 st->print_cr("# MachUEPNode");
1706 if (UseCompressedClassPointers) {
1707 st->print_cr("\tlwu t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1708 if (CompressedKlassPointers::shift() != 0) {
1709 st->print_cr("\tdecode_klass_not_null t0, t0");
1710 }
1711 } else {
1712 st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1713 }
1714 st->print_cr("\tbeq t0, t1, ic_hit");
1715 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1716 st->print_cr("\tic_hit:");
1717 }
1718 #endif
1719
1720 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1721 {
1722 // This is the unverified entry point.
1723 C2_MacroAssembler _masm(&cbuf);
1724
1725 Label skip;
1726 __ cmp_klass(j_rarg0, t1, t0, t2 /* call-clobbered t2 as a tmp */, skip);
1727 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1728 __ bind(skip);
1729
1730 // These NOPs are critical so that verified entry point is properly
1731 // 4 bytes aligned for patching by NativeJump::patch_verified_entry()
1732 __ align(NativeInstruction::instruction_size);
1733 }
1734
1735 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1736 {
1737 assert_cond(ra_ != NULL);
1738 return MachNode::size(ra_);
1739 }
1740
1741 // REQUIRED EMIT CODE
1742
1743 //=============================================================================
1744
1745 // Emit exception handler code.
1746 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
1747 {
1748 // la_patchable t0, #exception_blob_entry_point
1749 // jr (offset)t0
1750 // or
1751 // j #exception_blob_entry_point
1752 // Note that the code buffer's insts_mark is always relative to insts.
1753 // That's why we must use the macroassembler to generate a handler.
1754 C2_MacroAssembler _masm(&cbuf);
1755 address base = __ start_a_stub(size_exception_handler());
1756 if (base == NULL) {
1757 ciEnv::current()->record_failure("CodeCache is full");
1758 return 0; // CodeBuffer::expand failed
1759 }
1760 int offset = __ offset();
1761 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1762 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1763 __ end_a_stub();
1764 return offset;
1765 }
1766
1767 // Emit deopt handler code.
1768 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
1769 {
1770 // Note that the code buffer's insts_mark is always relative to insts.
1771 // That's why we must use the macroassembler to generate a handler.
1772 C2_MacroAssembler _masm(&cbuf);
1773 address base = __ start_a_stub(size_deopt_handler());
1774 if (base == NULL) {
1775 ciEnv::current()->record_failure("CodeCache is full");
1776 return 0; // CodeBuffer::expand failed
1777 }
1778 int offset = __ offset();
1779
1780 __ auipc(ra, 0);
1781 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1782
1783 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1784 __ end_a_stub();
1785 return offset;
1786
1787 }
1788 // REQUIRED MATCHER CODE
1789
1790 //=============================================================================
1791
1792 const bool Matcher::match_rule_supported(int opcode) {
1793 if (!has_match_rule(opcode)) {
1794 return false;
1795 }
1796
1797 switch (opcode) {
1798 case Op_CacheWB: // fall through
1799 case Op_CacheWBPreSync: // fall through
1800 case Op_CacheWBPostSync:
1801 if (!VM_Version::supports_data_cache_line_flush()) {
1802 return false;
1803 }
1804 break;
1805
1806 case Op_StrCompressedCopy: // fall through
1807 case Op_StrInflatedCopy: // fall through
1808 case Op_HasNegatives:
1809 return UseRVV;
1810
1811 case Op_EncodeISOArray:
1812 return UseRVV && SpecialEncodeISOArray;
1813
1814 case Op_PopCountI:
1815 case Op_PopCountL:
1816 return UsePopCountInstruction;
1817
1818 case Op_RotateRight:
1819 case Op_RotateLeft:
1820 case Op_CountLeadingZerosI:
1821 case Op_CountLeadingZerosL:
1822 case Op_CountTrailingZerosI:
1823 case Op_CountTrailingZerosL:
1824 return UseZbb;
1825 }
1826
1827 return true; // Per default match rules are supported.
1828 }
1829
1830 // Identify extra cases that we might want to provide match rules for vector nodes and
1831 // other intrinsics guarded with vector length (vlen) and element type (bt).
1832 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
1833 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
1834 return false;
1835 }
1836
1837 return op_vec_supported(opcode);
1838 }
1839
1840 const RegMask* Matcher::predicate_reg_mask(void) {
1841 return NULL;
1842 }
1843
1844 const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
1845 return NULL;
1846 }
1847
1848 // Vector calling convention not yet implemented.
1849 const bool Matcher::supports_vector_calling_convention(void) {
1850 return false;
1851 }
1852
1853 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1854 Unimplemented();
1855 return OptoRegPair(0, 0);
1856 }
1857
1858 // Is this branch offset short enough that a short branch can be used?
1859 //
1860 // NOTE: If the platform does not provide any short branch variants, then
1861 // this method should return false for offset 0.
1862 // |---label(L1)-----|
1863 // |-----------------|
1864 // |-----------------|----------eq: float-------------------
1865 // |-----------------| // far_cmpD_branch | cmpD_branch
1866 // |------- ---------| feq; | feq;
1867 // |-far_cmpD_branch-| beqz done; | bnez L;
1868 // |-----------------| j L; |
1869 // |-----------------| bind(done); |
1870 // |-----------------|--------------------------------------
1871 // |-----------------| // so shortBrSize = br_size - 4;
1872 // |-----------------| // so offs = offset - shortBrSize + 4;
1873 // |---label(L2)-----|
1874 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1875 // The passed offset is relative to address of the branch.
1876 int shortBrSize = br_size - 4;
1877 int offs = offset - shortBrSize + 4;
1878 return (-4096 <= offs && offs < 4096);
1879 }
1880
1881 // Vector width in bytes.
1882 const int Matcher::vector_width_in_bytes(BasicType bt) {
1883 if (UseRVV) {
1884 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1885 // MaxVectorSize == VM_Version::_initial_vector_length
1886 return MaxVectorSize;
1887 }
1888 return 0;
1889 }
1890
1891 // Limits on vector size (number of elements) loaded into vector.
1892 const int Matcher::max_vector_size(const BasicType bt) {
1893 return vector_width_in_bytes(bt) / type2aelembytes(bt);
1894 }
1895 const int Matcher::min_vector_size(const BasicType bt) {
1896 return max_vector_size(bt);
1897 }
1898
1899 // Vector ideal reg.
1900 const uint Matcher::vector_ideal_reg(int len) {
1901 assert(MaxVectorSize >= len, "");
1902 if (UseRVV) {
1903 return Op_VecA;
1904 }
1905
1906 ShouldNotReachHere();
1907 return 0;
1908 }
1909
1910 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
1911 return Matcher::max_vector_size(bt);
1912 }
1913
1914 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
1915 ShouldNotReachHere(); // generic vector operands not supported
1916 return NULL;
1917 }
1918
1919 bool Matcher::is_generic_reg2reg_move(MachNode* m) {
1920 ShouldNotReachHere(); // generic vector operands not supported
1921 return false;
1922 }
1923
1924 bool Matcher::is_generic_vector(MachOper* opnd) {
1925 ShouldNotReachHere(); // generic vector operands not supported
1926 return false;
1927 }
1928
1929 // Return whether or not this register is ever used as an argument.
1930 // This function is used on startup to build the trampoline stubs in
1931 // generateOptoStub. Registers not mentioned will be killed by the VM
1932 // call in the trampoline, and arguments in those registers not be
1933 // available to the callee.
1934 bool Matcher::can_be_java_arg(int reg)
1935 {
1936 return
1937 reg == R10_num || reg == R10_H_num ||
1938 reg == R11_num || reg == R11_H_num ||
1939 reg == R12_num || reg == R12_H_num ||
1940 reg == R13_num || reg == R13_H_num ||
1941 reg == R14_num || reg == R14_H_num ||
1942 reg == R15_num || reg == R15_H_num ||
1943 reg == R16_num || reg == R16_H_num ||
1944 reg == R17_num || reg == R17_H_num ||
1945 reg == F10_num || reg == F10_H_num ||
1946 reg == F11_num || reg == F11_H_num ||
1947 reg == F12_num || reg == F12_H_num ||
1948 reg == F13_num || reg == F13_H_num ||
1949 reg == F14_num || reg == F14_H_num ||
1950 reg == F15_num || reg == F15_H_num ||
1951 reg == F16_num || reg == F16_H_num ||
1952 reg == F17_num || reg == F17_H_num;
1953 }
1954
1955 bool Matcher::is_spillable_arg(int reg)
1956 {
1957 return can_be_java_arg(reg);
1958 }
1959
1960 const int Matcher::float_pressure(int default_pressure_threshold) {
1961 return default_pressure_threshold;
1962 }
1963
1964 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
1965 return false;
1966 }
1967
1968 RegMask Matcher::divI_proj_mask() {
1969 ShouldNotReachHere();
1970 return RegMask();
1971 }
1972
1973 // Register for MODI projection of divmodI.
1974 RegMask Matcher::modI_proj_mask() {
1975 ShouldNotReachHere();
1976 return RegMask();
1977 }
1978
1979 // Register for DIVL projection of divmodL.
1980 RegMask Matcher::divL_proj_mask() {
1981 ShouldNotReachHere();
1982 return RegMask();
1983 }
1984
1985 // Register for MODL projection of divmodL.
1986 RegMask Matcher::modL_proj_mask() {
1987 ShouldNotReachHere();
1988 return RegMask();
1989 }
1990
1991 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1992 return FP_REG_mask();
1993 }
1994
1995 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
1996 assert_cond(addp != NULL);
1997 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
1998 Node* u = addp->fast_out(i);
1999 if (u != NULL && u->is_Mem()) {
2000 int opsize = u->as_Mem()->memory_size();
2001 assert(opsize > 0, "unexpected memory operand size");
2002 if (u->as_Mem()->memory_size() != (1 << shift)) {
2003 return false;
2004 }
2005 }
2006 }
2007 return true;
2008 }
2009
2010 // Should the Matcher clone input 'm' of node 'n'?
2011 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2012 assert_cond(m != NULL);
2013 if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
2014 mstack.push(m, Visit); // m = ShiftCntV
2015 return true;
2016 }
2017 return false;
2018 }
2019
2020 // Should the Matcher clone shifts on addressing modes, expecting them
2021 // to be subsumed into complex addressing expressions or compute them
2022 // into registers?
2023 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2024 return clone_base_plus_offset_address(m, mstack, address_visited);
2025 }
2026
2027 %}
2028
2029
2030
2031 //----------ENCODING BLOCK-----------------------------------------------------
2032 // This block specifies the encoding classes used by the compiler to
2033 // output byte streams. Encoding classes are parameterized macros
2034 // used by Machine Instruction Nodes in order to generate the bit
2035 // encoding of the instruction. Operands specify their base encoding
2036 // interface with the interface keyword. There are currently
2037 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2038 // COND_INTER. REG_INTER causes an operand to generate a function
2039 // which returns its register number when queried. CONST_INTER causes
2040 // an operand to generate a function which returns the value of the
2041 // constant when queried. MEMORY_INTER causes an operand to generate
2042 // four functions which return the Base Register, the Index Register,
2043 // the Scale Value, and the Offset Value of the operand when queried.
2044 // COND_INTER causes an operand to generate six functions which return
2045 // the encoding code (ie - encoding bits for the instruction)
2046 // associated with each basic boolean condition for a conditional
2047 // instruction.
2048 //
2049 // Instructions specify two basic values for encoding. Again, a
2050 // function is available to check if the constant displacement is an
2051 // oop. They use the ins_encode keyword to specify their encoding
2052 // classes (which must be a sequence of enc_class names, and their
2053 // parameters, specified in the encoding block), and they use the
2054 // opcode keyword to specify, in order, their primary, secondary, and
2055 // tertiary opcode. Only the opcode sections which a particular
2056 // instruction needs for encoding need to be specified.
2057 encode %{
2058 // BEGIN Non-volatile memory access
2059
2060 enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
2061 C2_MacroAssembler _masm(&cbuf);
2062 Assembler::CompressibleRegion cr(&_masm);
2063 int64_t con = (int64_t)$src$$constant;
2064 Register dst_reg = as_Register($dst$$reg);
2065 __ li(dst_reg, con);
2066 %}
2067
2068 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2069 C2_MacroAssembler _masm(&cbuf);
2070 Register dst_reg = as_Register($dst$$reg);
2071 address con = (address)$src$$constant;
2072 if (con == NULL || con == (address)1) {
2073 ShouldNotReachHere();
2074 } else {
2075 relocInfo::relocType rtype = $src->constant_reloc();
2076 if (rtype == relocInfo::oop_type) {
2077 __ movoop(dst_reg, (jobject)con, /*immediate*/true);
2078 } else if (rtype == relocInfo::metadata_type) {
2079 __ mov_metadata(dst_reg, (Metadata*)con);
2080 } else {
2081 assert(rtype == relocInfo::none, "unexpected reloc type");
2082 __ li(dst_reg, $src$$constant);
2083 }
2084 }
2085 %}
2086
2087 enc_class riscv_enc_mov_p1(iRegP dst) %{
2088 C2_MacroAssembler _masm(&cbuf);
2089 Assembler::CompressibleRegion cr(&_masm);
2090 Register dst_reg = as_Register($dst$$reg);
2091 __ li(dst_reg, 1);
2092 %}
2093
2094 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2095 C2_MacroAssembler _masm(&cbuf);
2096 __ load_byte_map_base($dst$$Register);
2097 %}
2098
2099 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2100 C2_MacroAssembler _masm(&cbuf);
2101 Register dst_reg = as_Register($dst$$reg);
2102 address con = (address)$src$$constant;
2103 if (con == NULL) {
2104 ShouldNotReachHere();
2105 } else {
2106 relocInfo::relocType rtype = $src->constant_reloc();
2107 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2108 __ set_narrow_oop(dst_reg, (jobject)con);
2109 }
2110 %}
2111
2112 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2113 C2_MacroAssembler _masm(&cbuf);
2114 Register dst_reg = as_Register($dst$$reg);
2115 __ mv(dst_reg, zr);
2116 %}
2117
2118 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2119 C2_MacroAssembler _masm(&cbuf);
2120 Register dst_reg = as_Register($dst$$reg);
2121 address con = (address)$src$$constant;
2122 if (con == NULL) {
2123 ShouldNotReachHere();
2124 } else {
2125 relocInfo::relocType rtype = $src->constant_reloc();
2126 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2127 __ set_narrow_klass(dst_reg, (Klass *)con);
2128 }
2129 %}
2130
2131 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2132 C2_MacroAssembler _masm(&cbuf);
2133 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2134 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2135 /*result as bool*/ true);
2136 %}
2137
2138 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2139 C2_MacroAssembler _masm(&cbuf);
2140 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2141 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2142 /*result as bool*/ true);
2143 %}
2144
2145 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2146 C2_MacroAssembler _masm(&cbuf);
2147 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2148 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2149 /*result as bool*/ true);
2150 %}
2151
2152 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2153 C2_MacroAssembler _masm(&cbuf);
2154 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2155 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2156 /*result as bool*/ true);
2157 %}
2158
2159 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2160 C2_MacroAssembler _masm(&cbuf);
2161 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2162 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2163 /*result as bool*/ true);
2164 %}
2165
2166 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2167 C2_MacroAssembler _masm(&cbuf);
2168 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2169 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2170 /*result as bool*/ true);
2171 %}
2172
2173 // compare and branch instruction encodings
2174
2175 enc_class riscv_enc_j(label lbl) %{
2176 C2_MacroAssembler _masm(&cbuf);
2177 Label* L = $lbl$$label;
2178 __ j(*L);
2179 %}
2180
2181 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2182 C2_MacroAssembler _masm(&cbuf);
2183 Label* L = $lbl$$label;
2184 switch ($cmp$$cmpcode) {
2185 case(BoolTest::ge):
2186 __ j(*L);
2187 break;
2188 case(BoolTest::lt):
2189 break;
2190 default:
2191 Unimplemented();
2192 }
2193 %}
2194
2195 // call instruction encodings
2196
2197 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2198 Register sub_reg = as_Register($sub$$reg);
2199 Register super_reg = as_Register($super$$reg);
2200 Register temp_reg = as_Register($temp$$reg);
2201 Register result_reg = as_Register($result$$reg);
2202 Register cr_reg = t1;
2203
2204 Label miss;
2205 Label done;
2206 C2_MacroAssembler _masm(&cbuf);
2207 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2208 NULL, &miss);
2209 if ($primary) {
2210 __ mv(result_reg, zr);
2211 } else {
2212 __ mv(cr_reg, zr);
2213 __ j(done);
2214 }
2215
2216 __ bind(miss);
2217 if (!$primary) {
2218 __ li(cr_reg, 1);
2219 }
2220
2221 __ bind(done);
2222 %}
2223
2224 enc_class riscv_enc_java_static_call(method meth) %{
2225 C2_MacroAssembler _masm(&cbuf);
2226
2227 address addr = (address)$meth$$method;
2228 address call = NULL;
2229 assert_cond(addr != NULL);
2230 if (!_method) {
2231 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2232 call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
2233 if (call == NULL) {
2234 ciEnv::current()->record_failure("CodeCache is full");
2235 return;
2236 }
2237 } else {
2238 int method_index = resolved_method_index(cbuf);
2239 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2240 : static_call_Relocation::spec(method_index);
2241 call = __ trampoline_call(Address(addr, rspec), &cbuf);
2242 if (call == NULL) {
2243 ciEnv::current()->record_failure("CodeCache is full");
2244 return;
2245 }
2246
2247 // Emit stub for static call
2248 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2249 if (stub == NULL) {
2250 ciEnv::current()->record_failure("CodeCache is full");
2251 return;
2252 }
2253 }
2254 %}
2255
2256 enc_class riscv_enc_java_dynamic_call(method meth) %{
2257 C2_MacroAssembler _masm(&cbuf);
2258 int method_index = resolved_method_index(cbuf);
2259 address call = __ ic_call((address)$meth$$method, method_index);
2260 if (call == NULL) {
2261 ciEnv::current()->record_failure("CodeCache is full");
2262 return;
2263 }
2264 %}
2265
2266 enc_class riscv_enc_call_epilog() %{
2267 C2_MacroAssembler _masm(&cbuf);
2268 if (VerifyStackAtCalls) {
2269 // Check that stack depth is unchanged: find majik cookie on stack
2270 __ call_Unimplemented();
2271 }
2272 %}
2273
2274 enc_class riscv_enc_java_to_runtime(method meth) %{
2275 C2_MacroAssembler _masm(&cbuf);
2276
2277 // some calls to generated routines (arraycopy code) are scheduled
2278 // by C2 as runtime calls. if so we can call them using a jr (they
2279 // will be in a reachable segment) otherwise we have to use a jalr
2280 // which loads the absolute address into a register.
2281 address entry = (address)$meth$$method;
2282 CodeBlob *cb = CodeCache::find_blob(entry);
2283 if (cb != NULL) {
2284 address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
2285 if (call == NULL) {
2286 ciEnv::current()->record_failure("CodeCache is full");
2287 return;
2288 }
2289 } else {
2290 Label retaddr;
2291 __ la(t1, retaddr);
2292 __ la(t0, RuntimeAddress(entry));
2293 // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
2294 __ addi(sp, sp, -2 * wordSize);
2295 __ sd(t1, Address(sp, wordSize));
2296 __ jalr(t0);
2297 __ bind(retaddr);
2298 __ addi(sp, sp, 2 * wordSize);
2299 }
2300 %}
2301
2302 // using the cr register as the bool result: 0 for success; others failed.
2303 enc_class riscv_enc_fast_lock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
2304 C2_MacroAssembler _masm(&cbuf);
2305 Register flag = t1;
2306 Register oop = as_Register($object$$reg);
2307 Register box = as_Register($box$$reg);
2308 Register disp_hdr = as_Register($tmp1$$reg);
2309 Register tmp = as_Register($tmp2$$reg);
2310 Label cont;
2311 Label object_has_monitor;
2312
2313 assert_different_registers(oop, box, tmp, disp_hdr, t0);
2314
2315 // Load markWord from object into displaced_header.
2316 __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
2317
2318 if (DiagnoseSyncOnValueBasedClasses != 0) {
2319 __ load_klass(flag, oop);
2320 __ lwu(flag, Address(flag, Klass::access_flags_offset()));
2321 __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
2322 __ bnez(flag, cont, true /* is_far */);
2323 }
2324
2325 if (UseBiasedLocking && !UseOptoBiasInlining) {
2326 __ biased_locking_enter(box, oop, disp_hdr, tmp, true, cont, NULL /* slow_case */, NULL, flag);
2327 }
2328
2329 // Check for existing monitor
2330 __ andi(t0, disp_hdr, markWord::monitor_value);
2331 __ bnez(t0, object_has_monitor);
2332
2333 // Set tmp to be (markWord of object | UNLOCK_VALUE).
2334 __ ori(tmp, disp_hdr, markWord::unlocked_value);
2335
2336 // Initialize the box. (Must happen before we update the object mark!)
2337 __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2338
2339 // Compare object markWord with an unlocked value (tmp) and if
2340 // equal exchange the stack address of our box with object markWord.
2341 // On failure disp_hdr contains the possibly locked markWord.
2342 __ cmpxchg(/*memory address*/oop, /*expected value*/tmp, /*new value*/box, Assembler::int64, Assembler::aq,
2343 Assembler::rl, /*result*/disp_hdr);
2344 __ mv(flag, zr);
2345 __ beq(disp_hdr, tmp, cont); // prepare zero flag and goto cont if we won the cas
2346
2347 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2348
2349 // If the compare-and-exchange succeeded, then we found an unlocked
2350 // object, will have now locked it will continue at label cont
2351 // We did not see an unlocked object so try the fast recursive case.
2352
2353 // Check if the owner is self by comparing the value in the
2354 // markWord of object (disp_hdr) with the stack pointer.
2355 __ sub(disp_hdr, disp_hdr, sp);
2356 __ li(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markWord::lock_mask_in_place));
2357 // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont,
2358 // hence we can store 0 as the displaced header in the box, which indicates that it is a
2359 // recursive lock.
2360 __ andr(tmp/*==0?*/, disp_hdr, tmp);
2361 __ sd(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2362 __ mv(flag, tmp); // we can use the value of tmp as the result here
2363
2364 __ j(cont);
2365
2366 // Handle existing monitor.
2367 __ bind(object_has_monitor);
2368 // The object's monitor m is unlocked iff m->owner == NULL,
2369 // otherwise m->owner may contain a thread or a stack address.
2370 //
2371 // Try to CAS m->owner from NULL to current thread.
2372 __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
2373 __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
2374 Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
2375
2376 // Store a non-null value into the box to avoid looking like a re-entrant
2377 // lock. The fast-path monitor unlock code checks for
2378 // markWord::monitor_value so use markWord::unused_mark which has the
2379 // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
2380 __ mv(tmp, (address)markWord::unused_mark().value());
2381 __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2382
2383 __ beqz(flag, cont); // CAS success means locking succeeded
2384
2385 __ bne(flag, xthread, cont); // Check for recursive locking
2386
2387 // Recursive lock case
2388 __ mv(flag, zr);
2389 __ ld(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
2390 __ add(tmp, tmp, 1u);
2391 __ sd(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
2392
2393 __ bind(cont);
2394 %}
2395
2396 // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
2397 enc_class riscv_enc_fast_unlock(iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2) %{
2398 C2_MacroAssembler _masm(&cbuf);
2399 Register flag = t1;
2400 Register oop = as_Register($object$$reg);
2401 Register box = as_Register($box$$reg);
2402 Register disp_hdr = as_Register($tmp1$$reg);
2403 Register tmp = as_Register($tmp2$$reg);
2404 Label cont;
2405 Label object_has_monitor;
2406
2407 assert_different_registers(oop, box, tmp, disp_hdr, flag);
2408
2409 if (UseBiasedLocking && !UseOptoBiasInlining) {
2410 __ biased_locking_exit(oop, tmp, cont, flag);
2411 }
2412
2413 // Find the lock address and load the displaced header from the stack.
2414 __ ld(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
2415
2416 // If the displaced header is 0, we have a recursive unlock.
2417 __ mv(flag, disp_hdr);
2418 __ beqz(disp_hdr, cont);
2419
2420 // Handle existing monitor.
2421 __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
2422 __ andi(t0, disp_hdr, markWord::monitor_value);
2423 __ bnez(t0, object_has_monitor);
2424
2425 // Check if it is still a light weight lock, this is true if we
2426 // see the stack address of the basicLock in the markWord of the
2427 // object.
2428
2429 __ cmpxchg(/*memory address*/oop, /*expected value*/box, /*new value*/disp_hdr, Assembler::int64, Assembler::relaxed,
2430 Assembler::rl, /*result*/tmp);
2431 __ xorr(flag, box, tmp); // box == tmp if cas succeeds
2432 __ j(cont);
2433
2434 assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2435
2436 // Handle existing monitor.
2437 __ bind(object_has_monitor);
2438 STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
2439 __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
2440 __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
2441
2442 Label notRecursive;
2443 __ beqz(disp_hdr, notRecursive); // Will be 0 if not recursive.
2444
2445 // Recursive lock
2446 __ addi(disp_hdr, disp_hdr, -1);
2447 __ sd(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
2448 __ mv(flag, zr);
2449 __ j(cont);
2450
2451 __ bind(notRecursive);
2452 __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
2453 __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
2454 __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
2455 __ bnez(flag, cont);
2456 // need a release store here
2457 __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
2458 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
2459 __ sd(zr, Address(tmp)); // set unowned
2460
2461 __ bind(cont);
2462 %}
2463
2464 // arithmetic encodings
2465
2466 enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
2467 C2_MacroAssembler _masm(&cbuf);
2468 Register dst_reg = as_Register($dst$$reg);
2469 Register src1_reg = as_Register($src1$$reg);
2470 Register src2_reg = as_Register($src2$$reg);
2471 __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
2472 %}
2473
2474 enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
2475 C2_MacroAssembler _masm(&cbuf);
2476 Register dst_reg = as_Register($dst$$reg);
2477 Register src1_reg = as_Register($src1$$reg);
2478 Register src2_reg = as_Register($src2$$reg);
2479 __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
2480 %}
2481
2482 enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
2483 C2_MacroAssembler _masm(&cbuf);
2484 Register dst_reg = as_Register($dst$$reg);
2485 Register src1_reg = as_Register($src1$$reg);
2486 Register src2_reg = as_Register($src2$$reg);
2487 __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
2488 %}
2489
2490 enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
2491 C2_MacroAssembler _masm(&cbuf);
2492 Register dst_reg = as_Register($dst$$reg);
2493 Register src1_reg = as_Register($src1$$reg);
2494 Register src2_reg = as_Register($src2$$reg);
2495 __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
2496 %}
2497
2498 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2499 C2_MacroAssembler _masm(&cbuf);
2500 Assembler::CompressibleRegion cr(&_masm);
2501 Register target_reg = as_Register($jump_target$$reg);
2502 __ jr(target_reg);
2503 %}
2504
2505 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2506 C2_MacroAssembler _masm(&cbuf);
2507 Assembler::CompressibleRegion cr(&_masm);
2508 Register target_reg = as_Register($jump_target$$reg);
2509 // exception oop should be in x10
2510 // ret addr has been popped into ra
2511 // callee expects it in x13
2512 __ mv(x13, ra);
2513 __ jr(target_reg);
2514 %}
2515
2516 enc_class riscv_enc_rethrow() %{
2517 C2_MacroAssembler _masm(&cbuf);
2518 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2519 %}
2520
2521 enc_class riscv_enc_ret() %{
2522 C2_MacroAssembler _masm(&cbuf);
2523 Assembler::CompressibleRegion cr(&_masm);
2524 __ ret();
2525 %}
2526
2527 %}
2528
2529 //----------FRAME--------------------------------------------------------------
2530 // Definition of frame structure and management information.
2531 //
2532 // S T A C K L A Y O U T Allocators stack-slot number
2533 // | (to get allocators register number
2534 // G Owned by | | v add OptoReg::stack0())
2535 // r CALLER | |
2536 // o | +--------+ pad to even-align allocators stack-slot
2537 // w V | pad0 | numbers; owned by CALLER
2538 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2539 // h ^ | in | 5
2540 // | | args | 4 Holes in incoming args owned by SELF
2541 // | | | | 3
2542 // | | +--------+
2543 // V | | old out| Empty on Intel, window on Sparc
2544 // | old |preserve| Must be even aligned.
2545 // | SP-+--------+----> Matcher::_old_SP, even aligned
2546 // | | in | 3 area for Intel ret address
2547 // Owned by |preserve| Empty on Sparc.
2548 // SELF +--------+
2549 // | | pad2 | 2 pad to align old SP
2550 // | +--------+ 1
2551 // | | locks | 0
2552 // | +--------+----> OptoReg::stack0(), even aligned
2553 // | | pad1 | 11 pad to align new SP
2554 // | +--------+
2555 // | | | 10
2556 // | | spills | 9 spills
2557 // V | | 8 (pad0 slot for callee)
2558 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2559 // ^ | out | 7
2560 // | | args | 6 Holes in outgoing args owned by CALLEE
2561 // Owned by +--------+
2562 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2563 // | new |preserve| Must be even-aligned.
2564 // | SP-+--------+----> Matcher::_new_SP, even aligned
2565 // | | |
2566 //
2567 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2568 // known from SELF's arguments and the Java calling convention.
2569 // Region 6-7 is determined per call site.
2570 // Note 2: If the calling convention leaves holes in the incoming argument
2571 // area, those holes are owned by SELF. Holes in the outgoing area
2572 // are owned by the CALLEE. Holes should not be nessecary in the
2573 // incoming area, as the Java calling convention is completely under
2574 // the control of the AD file. Doubles can be sorted and packed to
2575 // avoid holes. Holes in the outgoing arguments may be nessecary for
2576 // varargs C calling conventions.
2577 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2578 // even aligned with pad0 as needed.
2579 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2580 // (the latter is true on Intel but is it false on RISCV?)
2581 // region 6-11 is even aligned; it may be padded out more so that
2582 // the region from SP to FP meets the minimum stack alignment.
2583 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2584 // alignment. Region 11, pad1, may be dynamically extended so that
2585 // SP meets the minimum alignment.
2586
2587 frame %{
2588 // These three registers define part of the calling convention
2589 // between compiled code and the interpreter.
2590
2591 // Inline Cache Register or methodOop for I2C.
2592 inline_cache_reg(R31);
2593
2594 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2595 cisc_spilling_operand_name(indOffset);
2596
2597 // Number of stack slots consumed by locking an object
2598 // generate Compile::sync_stack_slots
2599 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2600 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2601
2602 // Compiled code's Frame Pointer
2603 frame_pointer(R2);
2604
2605 // Interpreter stores its frame pointer in a register which is
2606 // stored to the stack by I2CAdaptors.
2607 // I2CAdaptors convert from interpreted java to compiled java.
2608 interpreter_frame_pointer(R8);
2609
2610 // Stack alignment requirement
2611 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2612
2613 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2614 // for calls to C. Supports the var-args backing area for register parms.
2615 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2616
2617 // The after-PROLOG location of the return address. Location of
2618 // return address specifies a type (REG or STACK) and a number
2619 // representing the register number (i.e. - use a register name) or
2620 // stack slot.
2621 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2622 // Otherwise, it is above the locks and verification slot and alignment word
2623 // TODO this may well be correct but need to check why that - 2 is there
2624 // ppc port uses 0 but we definitely need to allow for fixed_slots
2625 // which folds in the space used for monitors
2626 return_addr(STACK - 2 +
2627 align_up((Compile::current()->in_preserve_stack_slots() +
2628 Compile::current()->fixed_slots()),
2629 stack_alignment_in_slots()));
2630
2631 // Location of compiled Java return values. Same as C for now.
2632 return_value
2633 %{
2634 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2635 "only return normal values");
2636
2637 static const int lo[Op_RegL + 1] = { // enum name
2638 0, // Op_Node
2639 0, // Op_Set
2640 R10_num, // Op_RegN
2641 R10_num, // Op_RegI
2642 R10_num, // Op_RegP
2643 F10_num, // Op_RegF
2644 F10_num, // Op_RegD
2645 R10_num // Op_RegL
2646 };
2647
2648 static const int hi[Op_RegL + 1] = { // enum name
2649 0, // Op_Node
2650 0, // Op_Set
2651 OptoReg::Bad, // Op_RegN
2652 OptoReg::Bad, // Op_RegI
2653 R10_H_num, // Op_RegP
2654 OptoReg::Bad, // Op_RegF
2655 F10_H_num, // Op_RegD
2656 R10_H_num // Op_RegL
2657 };
2658
2659 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2660 %}
2661 %}
2662
2663 //----------ATTRIBUTES---------------------------------------------------------
2664 //----------Operand Attributes-------------------------------------------------
2665 op_attrib op_cost(1); // Required cost attribute
2666
2667 //----------Instruction Attributes---------------------------------------------
2668 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2669 ins_attrib ins_size(32); // Required size attribute (in bits)
2670 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2671 // a non-matching short branch variant
2672 // of some long branch?
2673 ins_attrib ins_alignment(4); // Required alignment attribute (must
2674 // be a power of 2) specifies the
2675 // alignment that some part of the
2676 // instruction (not necessarily the
2677 // start) requires. If > 1, a
2678 // compute_padding() function must be
2679 // provided for the instruction
2680
2681 //----------OPERANDS-----------------------------------------------------------
2682 // Operand definitions must precede instruction definitions for correct parsing
2683 // in the ADLC because operands constitute user defined types which are used in
2684 // instruction definitions.
2685
2686 //----------Simple Operands----------------------------------------------------
2687
2688 // Integer operands 32 bit
2689 // 32 bit immediate
2690 operand immI()
2691 %{
2692 match(ConI);
2693
2694 op_cost(0);
2695 format %{ %}
2696 interface(CONST_INTER);
2697 %}
2698
2699 // 32 bit zero
2700 operand immI0()
2701 %{
2702 predicate(n->get_int() == 0);
2703 match(ConI);
2704
2705 op_cost(0);
2706 format %{ %}
2707 interface(CONST_INTER);
2708 %}
2709
2710 // 32 bit unit increment
2711 operand immI_1()
2712 %{
2713 predicate(n->get_int() == 1);
2714 match(ConI);
2715
2716 op_cost(0);
2717 format %{ %}
2718 interface(CONST_INTER);
2719 %}
2720
2721 // 32 bit unit decrement
2722 operand immI_M1()
2723 %{
2724 predicate(n->get_int() == -1);
2725 match(ConI);
2726
2727 op_cost(0);
2728 format %{ %}
2729 interface(CONST_INTER);
2730 %}
2731
2732 // Unsigned Integer Immediate: 6-bit int, greater than 32
2733 operand uimmI6_ge32() %{
2734 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2735 match(ConI);
2736 op_cost(0);
2737 format %{ %}
2738 interface(CONST_INTER);
2739 %}
2740
2741 operand immI_le_4()
2742 %{
2743 predicate(n->get_int() <= 4);
2744 match(ConI);
2745
2746 op_cost(0);
2747 format %{ %}
2748 interface(CONST_INTER);
2749 %}
2750
2751 operand immI_16()
2752 %{
2753 predicate(n->get_int() == 16);
2754 match(ConI);
2755 op_cost(0);
2756 format %{ %}
2757 interface(CONST_INTER);
2758 %}
2759
2760 operand immI_24()
2761 %{
2762 predicate(n->get_int() == 24);
2763 match(ConI);
2764 op_cost(0);
2765 format %{ %}
2766 interface(CONST_INTER);
2767 %}
2768
2769 operand immI_31()
2770 %{
2771 predicate(n->get_int() == 31);
2772 match(ConI);
2773
2774 op_cost(0);
2775 format %{ %}
2776 interface(CONST_INTER);
2777 %}
2778
2779 operand immI_63()
2780 %{
2781 predicate(n->get_int() == 63);
2782 match(ConI);
2783
2784 op_cost(0);
2785 format %{ %}
2786 interface(CONST_INTER);
2787 %}
2788
2789 // 32 bit integer valid for add immediate
2790 operand immIAdd()
2791 %{
2792 predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
2793 match(ConI);
2794 op_cost(0);
2795 format %{ %}
2796 interface(CONST_INTER);
2797 %}
2798
2799 // 32 bit integer valid for sub immediate
2800 operand immISub()
2801 %{
2802 predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
2803 match(ConI);
2804 op_cost(0);
2805 format %{ %}
2806 interface(CONST_INTER);
2807 %}
2808
2809 // 5 bit signed value.
2810 operand immI5()
2811 %{
2812 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2813 match(ConI);
2814
2815 op_cost(0);
2816 format %{ %}
2817 interface(CONST_INTER);
2818 %}
2819
2820 // 5 bit signed value (simm5)
2821 operand immL5()
2822 %{
2823 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2824 match(ConL);
2825
2826 op_cost(0);
2827 format %{ %}
2828 interface(CONST_INTER);
2829 %}
2830
2831 // Integer operands 64 bit
2832 // 64 bit immediate
2833 operand immL()
2834 %{
2835 match(ConL);
2836
2837 op_cost(0);
2838 format %{ %}
2839 interface(CONST_INTER);
2840 %}
2841
2842 // 64 bit zero
2843 operand immL0()
2844 %{
2845 predicate(n->get_long() == 0);
2846 match(ConL);
2847
2848 op_cost(0);
2849 format %{ %}
2850 interface(CONST_INTER);
2851 %}
2852
2853 // Pointer operands
2854 // Pointer Immediate
2855 operand immP()
2856 %{
2857 match(ConP);
2858
2859 op_cost(0);
2860 format %{ %}
2861 interface(CONST_INTER);
2862 %}
2863
2864 // NULL Pointer Immediate
2865 operand immP0()
2866 %{
2867 predicate(n->get_ptr() == 0);
2868 match(ConP);
2869
2870 op_cost(0);
2871 format %{ %}
2872 interface(CONST_INTER);
2873 %}
2874
2875 // Pointer Immediate One
2876 // this is used in object initialization (initial object header)
2877 operand immP_1()
2878 %{
2879 predicate(n->get_ptr() == 1);
2880 match(ConP);
2881
2882 op_cost(0);
2883 format %{ %}
2884 interface(CONST_INTER);
2885 %}
2886
2887 // Card Table Byte Map Base
2888 operand immByteMapBase()
2889 %{
2890 // Get base of card map
2891 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2892 (CardTable::CardValue*)n->get_ptr() ==
2893 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2894 match(ConP);
2895
2896 op_cost(0);
2897 format %{ %}
2898 interface(CONST_INTER);
2899 %}
2900
2901 // Int Immediate: low 16-bit mask
2902 operand immI_16bits()
2903 %{
2904 predicate(n->get_int() == 0xFFFF);
2905 match(ConI);
2906 op_cost(0);
2907 format %{ %}
2908 interface(CONST_INTER);
2909 %}
2910
2911 operand immIpowerOf2() %{
2912 predicate(is_power_of_2((juint)(n->get_int())));
2913 match(ConI);
2914 op_cost(0);
2915 format %{ %}
2916 interface(CONST_INTER);
2917 %}
2918
2919 // Long Immediate: low 32-bit mask
2920 operand immL_32bits()
2921 %{
2922 predicate(n->get_long() == 0xFFFFFFFFL);
2923 match(ConL);
2924 op_cost(0);
2925 format %{ %}
2926 interface(CONST_INTER);
2927 %}
2928
2929 // 64 bit unit decrement
2930 operand immL_M1()
2931 %{
2932 predicate(n->get_long() == -1);
2933 match(ConL);
2934
2935 op_cost(0);
2936 format %{ %}
2937 interface(CONST_INTER);
2938 %}
2939
2940
2941 // 32 bit offset of pc in thread anchor
2942
2943 operand immL_pc_off()
2944 %{
2945 predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
2946 in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
2947 match(ConL);
2948
2949 op_cost(0);
2950 format %{ %}
2951 interface(CONST_INTER);
2952 %}
2953
2954 // 64 bit integer valid for add immediate
2955 operand immLAdd()
2956 %{
2957 predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
2958 match(ConL);
2959 op_cost(0);
2960 format %{ %}
2961 interface(CONST_INTER);
2962 %}
2963
2964 // 64 bit integer valid for sub immediate
2965 operand immLSub()
2966 %{
2967 predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
2968 match(ConL);
2969 op_cost(0);
2970 format %{ %}
2971 interface(CONST_INTER);
2972 %}
2973
2974 // Narrow pointer operands
2975 // Narrow Pointer Immediate
2976 operand immN()
2977 %{
2978 match(ConN);
2979
2980 op_cost(0);
2981 format %{ %}
2982 interface(CONST_INTER);
2983 %}
2984
2985 // Narrow NULL Pointer Immediate
2986 operand immN0()
2987 %{
2988 predicate(n->get_narrowcon() == 0);
2989 match(ConN);
2990
2991 op_cost(0);
2992 format %{ %}
2993 interface(CONST_INTER);
2994 %}
2995
2996 operand immNKlass()
2997 %{
2998 match(ConNKlass);
2999
3000 op_cost(0);
3001 format %{ %}
3002 interface(CONST_INTER);
3003 %}
3004
3005 // Float and Double operands
3006 // Double Immediate
3007 operand immD()
3008 %{
3009 match(ConD);
3010 op_cost(0);
3011 format %{ %}
3012 interface(CONST_INTER);
3013 %}
3014
3015 // Double Immediate: +0.0d
3016 operand immD0()
3017 %{
3018 predicate(jlong_cast(n->getd()) == 0);
3019 match(ConD);
3020
3021 op_cost(0);
3022 format %{ %}
3023 interface(CONST_INTER);
3024 %}
3025
3026 // Float Immediate
3027 operand immF()
3028 %{
3029 match(ConF);
3030 op_cost(0);
3031 format %{ %}
3032 interface(CONST_INTER);
3033 %}
3034
3035 // Float Immediate: +0.0f.
3036 operand immF0()
3037 %{
3038 predicate(jint_cast(n->getf()) == 0);
3039 match(ConF);
3040
3041 op_cost(0);
3042 format %{ %}
3043 interface(CONST_INTER);
3044 %}
3045
3046 operand immIOffset()
3047 %{
3048 predicate(is_imm_in_range(n->get_int(), 12, 0));
3049 match(ConI);
3050 op_cost(0);
3051 format %{ %}
3052 interface(CONST_INTER);
3053 %}
3054
3055 operand immLOffset()
3056 %{
3057 predicate(is_imm_in_range(n->get_long(), 12, 0));
3058 match(ConL);
3059 op_cost(0);
3060 format %{ %}
3061 interface(CONST_INTER);
3062 %}
3063
3064 // Scale values
3065 operand immIScale()
3066 %{
3067 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3068 match(ConI);
3069
3070 op_cost(0);
3071 format %{ %}
3072 interface(CONST_INTER);
3073 %}
3074
3075 // Integer 32 bit Register Operands
3076 operand iRegI()
3077 %{
3078 constraint(ALLOC_IN_RC(any_reg32));
3079 match(RegI);
3080 match(iRegINoSp);
3081 op_cost(0);
3082 format %{ %}
3083 interface(REG_INTER);
3084 %}
3085
3086 // Integer 32 bit Register not Special
3087 operand iRegINoSp()
3088 %{
3089 constraint(ALLOC_IN_RC(no_special_reg32));
3090 match(RegI);
3091 op_cost(0);
3092 format %{ %}
3093 interface(REG_INTER);
3094 %}
3095
3096 // Register R10 only
3097 operand iRegI_R10()
3098 %{
3099 constraint(ALLOC_IN_RC(int_r10_reg));
3100 match(RegI);
3101 match(iRegINoSp);
3102 op_cost(0);
3103 format %{ %}
3104 interface(REG_INTER);
3105 %}
3106
3107 // Register R12 only
3108 operand iRegI_R12()
3109 %{
3110 constraint(ALLOC_IN_RC(int_r12_reg));
3111 match(RegI);
3112 match(iRegINoSp);
3113 op_cost(0);
3114 format %{ %}
3115 interface(REG_INTER);
3116 %}
3117
3118 // Register R13 only
3119 operand iRegI_R13()
3120 %{
3121 constraint(ALLOC_IN_RC(int_r13_reg));
3122 match(RegI);
3123 match(iRegINoSp);
3124 op_cost(0);
3125 format %{ %}
3126 interface(REG_INTER);
3127 %}
3128
3129 // Register R14 only
3130 operand iRegI_R14()
3131 %{
3132 constraint(ALLOC_IN_RC(int_r14_reg));
3133 match(RegI);
3134 match(iRegINoSp);
3135 op_cost(0);
3136 format %{ %}
3137 interface(REG_INTER);
3138 %}
3139
3140 // Integer 64 bit Register Operands
3141 operand iRegL()
3142 %{
3143 constraint(ALLOC_IN_RC(any_reg));
3144 match(RegL);
3145 match(iRegLNoSp);
3146 op_cost(0);
3147 format %{ %}
3148 interface(REG_INTER);
3149 %}
3150
3151 // Integer 64 bit Register not Special
3152 operand iRegLNoSp()
3153 %{
3154 constraint(ALLOC_IN_RC(no_special_reg));
3155 match(RegL);
3156 match(iRegL_R10);
3157 format %{ %}
3158 interface(REG_INTER);
3159 %}
3160
3161 // Long 64 bit Register R28 only
3162 operand iRegL_R28()
3163 %{
3164 constraint(ALLOC_IN_RC(r28_reg));
3165 match(RegL);
3166 match(iRegLNoSp);
3167 op_cost(0);
3168 format %{ %}
3169 interface(REG_INTER);
3170 %}
3171
3172 // Long 64 bit Register R29 only
3173 operand iRegL_R29()
3174 %{
3175 constraint(ALLOC_IN_RC(r29_reg));
3176 match(RegL);
3177 match(iRegLNoSp);
3178 op_cost(0);
3179 format %{ %}
3180 interface(REG_INTER);
3181 %}
3182
3183 // Long 64 bit Register R30 only
3184 operand iRegL_R30()
3185 %{
3186 constraint(ALLOC_IN_RC(r30_reg));
3187 match(RegL);
3188 match(iRegLNoSp);
3189 op_cost(0);
3190 format %{ %}
3191 interface(REG_INTER);
3192 %}
3193
3194 // Pointer Register Operands
3195 // Pointer Register
3196 operand iRegP()
3197 %{
3198 constraint(ALLOC_IN_RC(ptr_reg));
3199 match(RegP);
3200 match(iRegPNoSp);
3201 match(iRegP_R10);
3202 match(iRegP_R15);
3203 match(javaThread_RegP);
3204 op_cost(0);
3205 format %{ %}
3206 interface(REG_INTER);
3207 %}
3208
3209 // Pointer 64 bit Register not Special
3210 operand iRegPNoSp()
3211 %{
3212 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3213 match(RegP);
3214 op_cost(0);
3215 format %{ %}
3216 interface(REG_INTER);
3217 %}
3218
3219 operand iRegP_R10()
3220 %{
3221 constraint(ALLOC_IN_RC(r10_reg));
3222 match(RegP);
3223 // match(iRegP);
3224 match(iRegPNoSp);
3225 op_cost(0);
3226 format %{ %}
3227 interface(REG_INTER);
3228 %}
3229
3230 // Pointer 64 bit Register R11 only
3231 operand iRegP_R11()
3232 %{
3233 constraint(ALLOC_IN_RC(r11_reg));
3234 match(RegP);
3235 match(iRegPNoSp);
3236 op_cost(0);
3237 format %{ %}
3238 interface(REG_INTER);
3239 %}
3240
3241 operand iRegP_R12()
3242 %{
3243 constraint(ALLOC_IN_RC(r12_reg));
3244 match(RegP);
3245 // match(iRegP);
3246 match(iRegPNoSp);
3247 op_cost(0);
3248 format %{ %}
3249 interface(REG_INTER);
3250 %}
3251
3252 // Pointer 64 bit Register R13 only
3253 operand iRegP_R13()
3254 %{
3255 constraint(ALLOC_IN_RC(r13_reg));
3256 match(RegP);
3257 match(iRegPNoSp);
3258 op_cost(0);
3259 format %{ %}
3260 interface(REG_INTER);
3261 %}
3262
3263 operand iRegP_R14()
3264 %{
3265 constraint(ALLOC_IN_RC(r14_reg));
3266 match(RegP);
3267 // match(iRegP);
3268 match(iRegPNoSp);
3269 op_cost(0);
3270 format %{ %}
3271 interface(REG_INTER);
3272 %}
3273
3274 operand iRegP_R15()
3275 %{
3276 constraint(ALLOC_IN_RC(r15_reg));
3277 match(RegP);
3278 // match(iRegP);
3279 match(iRegPNoSp);
3280 op_cost(0);
3281 format %{ %}
3282 interface(REG_INTER);
3283 %}
3284
3285 operand iRegP_R16()
3286 %{
3287 constraint(ALLOC_IN_RC(r16_reg));
3288 match(RegP);
3289 // match(iRegP);
3290 match(iRegPNoSp);
3291 op_cost(0);
3292 format %{ %}
3293 interface(REG_INTER);
3294 %}
3295
3296 // Pointer 64 bit Register R28 only
3297 operand iRegP_R28()
3298 %{
3299 constraint(ALLOC_IN_RC(r28_reg));
3300 match(RegP);
3301 match(iRegPNoSp);
3302 op_cost(0);
3303 format %{ %}
3304 interface(REG_INTER);
3305 %}
3306
3307 // Pointer Register Operands
3308 // Narrow Pointer Register
3309 operand iRegN()
3310 %{
3311 constraint(ALLOC_IN_RC(any_reg32));
3312 match(RegN);
3313 match(iRegNNoSp);
3314 op_cost(0);
3315 format %{ %}
3316 interface(REG_INTER);
3317 %}
3318
3319 // Integer 64 bit Register not Special
3320 operand iRegNNoSp()
3321 %{
3322 constraint(ALLOC_IN_RC(no_special_reg32));
3323 match(RegN);
3324 op_cost(0);
3325 format %{ %}
3326 interface(REG_INTER);
3327 %}
3328
3329 // heap base register -- used for encoding immN0
3330 operand iRegIHeapbase()
3331 %{
3332 constraint(ALLOC_IN_RC(heapbase_reg));
3333 match(RegI);
3334 op_cost(0);
3335 format %{ %}
3336 interface(REG_INTER);
3337 %}
3338
3339 // Long 64 bit Register R10 only
3340 operand iRegL_R10()
3341 %{
3342 constraint(ALLOC_IN_RC(r10_reg));
3343 match(RegL);
3344 match(iRegLNoSp);
3345 op_cost(0);
3346 format %{ %}
3347 interface(REG_INTER);
3348 %}
3349
3350 // Float Register
3351 // Float register operands
3352 operand fRegF()
3353 %{
3354 constraint(ALLOC_IN_RC(float_reg));
3355 match(RegF);
3356
3357 op_cost(0);
3358 format %{ %}
3359 interface(REG_INTER);
3360 %}
3361
3362 // Double Register
3363 // Double register operands
3364 operand fRegD()
3365 %{
3366 constraint(ALLOC_IN_RC(double_reg));
3367 match(RegD);
3368
3369 op_cost(0);
3370 format %{ %}
3371 interface(REG_INTER);
3372 %}
3373
3374 // Generic vector class. This will be used for
3375 // all vector operands.
3376 operand vReg()
3377 %{
3378 constraint(ALLOC_IN_RC(vectora_reg));
3379 match(VecA);
3380 op_cost(0);
3381 format %{ %}
3382 interface(REG_INTER);
3383 %}
3384
3385 operand vReg_V1()
3386 %{
3387 constraint(ALLOC_IN_RC(v1_reg));
3388 match(VecA);
3389 match(vReg);
3390 op_cost(0);
3391 format %{ %}
3392 interface(REG_INTER);
3393 %}
3394
3395 operand vReg_V2()
3396 %{
3397 constraint(ALLOC_IN_RC(v2_reg));
3398 match(VecA);
3399 match(vReg);
3400 op_cost(0);
3401 format %{ %}
3402 interface(REG_INTER);
3403 %}
3404
3405 operand vReg_V3()
3406 %{
3407 constraint(ALLOC_IN_RC(v3_reg));
3408 match(VecA);
3409 match(vReg);
3410 op_cost(0);
3411 format %{ %}
3412 interface(REG_INTER);
3413 %}
3414
3415 operand vReg_V4()
3416 %{
3417 constraint(ALLOC_IN_RC(v4_reg));
3418 match(VecA);
3419 match(vReg);
3420 op_cost(0);
3421 format %{ %}
3422 interface(REG_INTER);
3423 %}
3424
3425 operand vReg_V5()
3426 %{
3427 constraint(ALLOC_IN_RC(v5_reg));
3428 match(VecA);
3429 match(vReg);
3430 op_cost(0);
3431 format %{ %}
3432 interface(REG_INTER);
3433 %}
3434
3435 // Java Thread Register
3436 operand javaThread_RegP(iRegP reg)
3437 %{
3438 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3439 match(reg);
3440 op_cost(0);
3441 format %{ %}
3442 interface(REG_INTER);
3443 %}
3444
3445 //----------Memory Operands----------------------------------------------------
3446 // RISCV has only base_plus_offset and literal address mode, so no need to use
3447 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3448 operand indirect(iRegP reg)
3449 %{
3450 constraint(ALLOC_IN_RC(ptr_reg));
3451 match(reg);
3452 op_cost(0);
3453 format %{ "[$reg]" %}
3454 interface(MEMORY_INTER) %{
3455 base($reg);
3456 index(0xffffffff);
3457 scale(0x0);
3458 disp(0x0);
3459 %}
3460 %}
3461
3462 operand indOffI(iRegP reg, immIOffset off)
3463 %{
3464 constraint(ALLOC_IN_RC(ptr_reg));
3465 match(AddP reg off);
3466 op_cost(0);
3467 format %{ "[$reg, $off]" %}
3468 interface(MEMORY_INTER) %{
3469 base($reg);
3470 index(0xffffffff);
3471 scale(0x0);
3472 disp($off);
3473 %}
3474 %}
3475
3476 operand indOffL(iRegP reg, immLOffset off)
3477 %{
3478 constraint(ALLOC_IN_RC(ptr_reg));
3479 match(AddP reg off);
3480 op_cost(0);
3481 format %{ "[$reg, $off]" %}
3482 interface(MEMORY_INTER) %{
3483 base($reg);
3484 index(0xffffffff);
3485 scale(0x0);
3486 disp($off);
3487 %}
3488 %}
3489
3490 operand indirectN(iRegN reg)
3491 %{
3492 predicate(CompressedOops::shift() == 0);
3493 constraint(ALLOC_IN_RC(ptr_reg));
3494 match(DecodeN reg);
3495 op_cost(0);
3496 format %{ "[$reg]\t# narrow" %}
3497 interface(MEMORY_INTER) %{
3498 base($reg);
3499 index(0xffffffff);
3500 scale(0x0);
3501 disp(0x0);
3502 %}
3503 %}
3504
3505 operand indOffIN(iRegN reg, immIOffset off)
3506 %{
3507 predicate(CompressedOops::shift() == 0);
3508 constraint(ALLOC_IN_RC(ptr_reg));
3509 match(AddP (DecodeN reg) off);
3510 op_cost(0);
3511 format %{ "[$reg, $off]\t# narrow" %}
3512 interface(MEMORY_INTER) %{
3513 base($reg);
3514 index(0xffffffff);
3515 scale(0x0);
3516 disp($off);
3517 %}
3518 %}
3519
3520 operand indOffLN(iRegN reg, immLOffset off)
3521 %{
3522 predicate(CompressedOops::shift() == 0);
3523 constraint(ALLOC_IN_RC(ptr_reg));
3524 match(AddP (DecodeN reg) off);
3525 op_cost(0);
3526 format %{ "[$reg, $off]\t# narrow" %}
3527 interface(MEMORY_INTER) %{
3528 base($reg);
3529 index(0xffffffff);
3530 scale(0x0);
3531 disp($off);
3532 %}
3533 %}
3534
3535 // RISCV opto stubs need to write to the pc slot in the thread anchor
3536 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
3537 %{
3538 constraint(ALLOC_IN_RC(ptr_reg));
3539 match(AddP reg off);
3540 op_cost(0);
3541 format %{ "[$reg, $off]" %}
3542 interface(MEMORY_INTER) %{
3543 base($reg);
3544 index(0xffffffff);
3545 scale(0x0);
3546 disp($off);
3547 %}
3548 %}
3549
3550
3551 //----------Special Memory Operands--------------------------------------------
3552 // Stack Slot Operand - This operand is used for loading and storing temporary
3553 // values on the stack where a match requires a value to
3554 // flow through memory.
3555 operand stackSlotI(sRegI reg)
3556 %{
3557 constraint(ALLOC_IN_RC(stack_slots));
3558 // No match rule because this operand is only generated in matching
3559 // match(RegI);
3560 format %{ "[$reg]" %}
3561 interface(MEMORY_INTER) %{
3562 base(0x02); // RSP
3563 index(0xffffffff); // No Index
3564 scale(0x0); // No Scale
3565 disp($reg); // Stack Offset
3566 %}
3567 %}
3568
3569 operand stackSlotF(sRegF reg)
3570 %{
3571 constraint(ALLOC_IN_RC(stack_slots));
3572 // No match rule because this operand is only generated in matching
3573 // match(RegF);
3574 format %{ "[$reg]" %}
3575 interface(MEMORY_INTER) %{
3576 base(0x02); // RSP
3577 index(0xffffffff); // No Index
3578 scale(0x0); // No Scale
3579 disp($reg); // Stack Offset
3580 %}
3581 %}
3582
3583 operand stackSlotD(sRegD reg)
3584 %{
3585 constraint(ALLOC_IN_RC(stack_slots));
3586 // No match rule because this operand is only generated in matching
3587 // match(RegD);
3588 format %{ "[$reg]" %}
3589 interface(MEMORY_INTER) %{
3590 base(0x02); // RSP
3591 index(0xffffffff); // No Index
3592 scale(0x0); // No Scale
3593 disp($reg); // Stack Offset
3594 %}
3595 %}
3596
3597 operand stackSlotL(sRegL reg)
3598 %{
3599 constraint(ALLOC_IN_RC(stack_slots));
3600 // No match rule because this operand is only generated in matching
3601 // match(RegL);
3602 format %{ "[$reg]" %}
3603 interface(MEMORY_INTER) %{
3604 base(0x02); // RSP
3605 index(0xffffffff); // No Index
3606 scale(0x0); // No Scale
3607 disp($reg); // Stack Offset
3608 %}
3609 %}
3610
3611 // Special operand allowing long args to int ops to be truncated for free
3612
3613 operand iRegL2I(iRegL reg) %{
3614
3615 op_cost(0);
3616
3617 match(ConvL2I reg);
3618
3619 format %{ "l2i($reg)" %}
3620
3621 interface(REG_INTER)
3622 %}
3623
3624
3625 // Comparison Operands
3626 // NOTE: Label is a predefined operand which should not be redefined in
3627 // the AD file. It is generically handled within the ADLC.
3628
3629 //----------Conditional Branch Operands----------------------------------------
3630 // Comparison Op - This is the operation of the comparison, and is limited to
3631 // the following set of codes:
3632 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3633 //
3634 // Other attributes of the comparison, such as unsignedness, are specified
3635 // by the comparison instruction that sets a condition code flags register.
3636 // That result is represented by a flags operand whose subtype is appropriate
3637 // to the unsignedness (etc.) of the comparison.
3638 //
3639 // Later, the instruction which matches both the Comparison Op (a Bool) and
3640 // the flags (produced by the Cmp) specifies the coding of the comparison op
3641 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3642
3643
3644 // used for signed integral comparisons and fp comparisons
3645 operand cmpOp()
3646 %{
3647 match(Bool);
3648
3649 format %{ "" %}
3650
3651 // the values in interface derives from struct BoolTest::mask
3652 interface(COND_INTER) %{
3653 equal(0x0, "eq");
3654 greater(0x1, "gt");
3655 overflow(0x2, "overflow");
3656 less(0x3, "lt");
3657 not_equal(0x4, "ne");
3658 less_equal(0x5, "le");
3659 no_overflow(0x6, "no_overflow");
3660 greater_equal(0x7, "ge");
3661 %}
3662 %}
3663
3664 // used for unsigned integral comparisons
3665 operand cmpOpU()
3666 %{
3667 match(Bool);
3668
3669 format %{ "" %}
3670 // the values in interface derives from struct BoolTest::mask
3671 interface(COND_INTER) %{
3672 equal(0x0, "eq");
3673 greater(0x1, "gtu");
3674 overflow(0x2, "overflow");
3675 less(0x3, "ltu");
3676 not_equal(0x4, "ne");
3677 less_equal(0x5, "leu");
3678 no_overflow(0x6, "no_overflow");
3679 greater_equal(0x7, "geu");
3680 %}
3681 %}
3682
3683 // used for certain integral comparisons which can be
3684 // converted to bxx instructions
3685 operand cmpOpEqNe()
3686 %{
3687 match(Bool);
3688 op_cost(0);
3689 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3690 n->as_Bool()->_test._test == BoolTest::eq);
3691
3692 format %{ "" %}
3693 interface(COND_INTER) %{
3694 equal(0x0, "eq");
3695 greater(0x1, "gt");
3696 overflow(0x2, "overflow");
3697 less(0x3, "lt");
3698 not_equal(0x4, "ne");
3699 less_equal(0x5, "le");
3700 no_overflow(0x6, "no_overflow");
3701 greater_equal(0x7, "ge");
3702 %}
3703 %}
3704
3705 operand cmpOpULtGe()
3706 %{
3707 match(Bool);
3708 op_cost(0);
3709 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3710 n->as_Bool()->_test._test == BoolTest::ge);
3711
3712 format %{ "" %}
3713 interface(COND_INTER) %{
3714 equal(0x0, "eq");
3715 greater(0x1, "gtu");
3716 overflow(0x2, "overflow");
3717 less(0x3, "ltu");
3718 not_equal(0x4, "ne");
3719 less_equal(0x5, "leu");
3720 no_overflow(0x6, "no_overflow");
3721 greater_equal(0x7, "geu");
3722 %}
3723 %}
3724
3725 operand cmpOpUEqNeLeGt()
3726 %{
3727 match(Bool);
3728 op_cost(0);
3729 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3730 n->as_Bool()->_test._test == BoolTest::eq ||
3731 n->as_Bool()->_test._test == BoolTest::le ||
3732 n->as_Bool()->_test._test == BoolTest::gt);
3733
3734 format %{ "" %}
3735 interface(COND_INTER) %{
3736 equal(0x0, "eq");
3737 greater(0x1, "gtu");
3738 overflow(0x2, "overflow");
3739 less(0x3, "ltu");
3740 not_equal(0x4, "ne");
3741 less_equal(0x5, "leu");
3742 no_overflow(0x6, "no_overflow");
3743 greater_equal(0x7, "geu");
3744 %}
3745 %}
3746
3747
3748 // Flags register, used as output of compare logic
3749 operand rFlagsReg()
3750 %{
3751 constraint(ALLOC_IN_RC(reg_flags));
3752 match(RegFlags);
3753
3754 op_cost(0);
3755 format %{ "RFLAGS" %}
3756 interface(REG_INTER);
3757 %}
3758
3759 // Special Registers
3760
3761 // Method Register
3762 operand inline_cache_RegP(iRegP reg)
3763 %{
3764 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3765 match(reg);
3766 match(iRegPNoSp);
3767 op_cost(0);
3768 format %{ %}
3769 interface(REG_INTER);
3770 %}
3771
3772 //----------OPERAND CLASSES----------------------------------------------------
3773 // Operand Classes are groups of operands that are used as to simplify
3774 // instruction definitions by not requiring the AD writer to specify
3775 // separate instructions for every form of operand when the
3776 // instruction accepts multiple operand types with the same basic
3777 // encoding and format. The classic case of this is memory operands.
3778
3779 // memory is used to define read/write location for load/store
3780 // instruction defs. we can turn a memory op into an Address
3781
3782 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3783
3784 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3785 // operations. it allows the src to be either an iRegI or a (ConvL2I
3786 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3787 // can be elided because the 32-bit instruction will just employ the
3788 // lower 32 bits anyway.
3789 //
3790 // n.b. this does not elide all L2I conversions. if the truncated
3791 // value is consumed by more than one operation then the ConvL2I
3792 // cannot be bundled into the consuming nodes so an l2i gets planted
3793 // (actually a mvw $dst $src) and the downstream instructions consume
3794 // the result of the l2i as an iRegI input. That's a shame since the
3795 // mvw is actually redundant but its not too costly.
3796
3797 opclass iRegIorL2I(iRegI, iRegL2I);
3798 opclass iRegIorL(iRegI, iRegL);
3799 opclass iRegNorP(iRegN, iRegP);
3800 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3801 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3802 opclass immIorL(immI, immL);
3803
3804 //----------PIPELINE-----------------------------------------------------------
3805 // Rules which define the behavior of the target architectures pipeline.
3806
3807 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3808 //pipe_desc(ID, EX, MEM, WR);
3809 #define ID S0
3810 #define EX S1
3811 #define MEM S2
3812 #define WR S3
3813
3814 // Integer ALU reg operation
3815 pipeline %{
3816
3817 attributes %{
3818 // RISC-V instructions are of fixed length
3819 fixed_size_instructions; // Fixed size instructions TODO does
3820 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3821 // RISC-V instructions come in 32-bit word units
3822 instruction_unit_size = 4; // An instruction is 4 bytes long
3823 instruction_fetch_unit_size = 64; // The processor fetches one line
3824 instruction_fetch_units = 1; // of 64 bytes
3825
3826 // List of nop instructions
3827 nops( MachNop );
3828 %}
3829
3830 // We don't use an actual pipeline model so don't care about resources
3831 // or description. we do use pipeline classes to introduce fixed
3832 // latencies
3833
3834 //----------RESOURCES----------------------------------------------------------
3835 // Resources are the functional units available to the machine
3836
3837 // Generic RISC-V pipeline
3838 // 1 decoder
3839 // 1 instruction decoded per cycle
3840 // 1 load/store ops per cycle, 1 branch, 1 FPU
3841 // 1 mul, 1 div
3842
3843 resources ( DECODE,
3844 ALU,
3845 MUL,
3846 DIV,
3847 BRANCH,
3848 LDST,
3849 FPU);
3850
3851 //----------PIPELINE DESCRIPTION-----------------------------------------------
3852 // Pipeline Description specifies the stages in the machine's pipeline
3853
3854 // Define the pipeline as a generic 6 stage pipeline
3855 pipe_desc(S0, S1, S2, S3, S4, S5);
3856
3857 //----------PIPELINE CLASSES---------------------------------------------------
3858 // Pipeline Classes describe the stages in which input and output are
3859 // referenced by the hardware pipeline.
3860
3861 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3862 %{
3863 single_instruction;
3864 src1 : S1(read);
3865 src2 : S2(read);
3866 dst : S5(write);
3867 DECODE : ID;
3868 FPU : S5;
3869 %}
3870
3871 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3872 %{
3873 src1 : S1(read);
3874 src2 : S2(read);
3875 dst : S5(write);
3876 DECODE : ID;
3877 FPU : S5;
3878 %}
3879
3880 pipe_class fp_uop_s(fRegF dst, fRegF src)
3881 %{
3882 single_instruction;
3883 src : S1(read);
3884 dst : S5(write);
3885 DECODE : ID;
3886 FPU : S5;
3887 %}
3888
3889 pipe_class fp_uop_d(fRegD dst, fRegD src)
3890 %{
3891 single_instruction;
3892 src : S1(read);
3893 dst : S5(write);
3894 DECODE : ID;
3895 FPU : S5;
3896 %}
3897
3898 pipe_class fp_d2f(fRegF dst, fRegD src)
3899 %{
3900 single_instruction;
3901 src : S1(read);
3902 dst : S5(write);
3903 DECODE : ID;
3904 FPU : S5;
3905 %}
3906
3907 pipe_class fp_f2d(fRegD dst, fRegF src)
3908 %{
3909 single_instruction;
3910 src : S1(read);
3911 dst : S5(write);
3912 DECODE : ID;
3913 FPU : S5;
3914 %}
3915
3916 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3917 %{
3918 single_instruction;
3919 src : S1(read);
3920 dst : S5(write);
3921 DECODE : ID;
3922 FPU : S5;
3923 %}
3924
3925 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3926 %{
3927 single_instruction;
3928 src : S1(read);
3929 dst : S5(write);
3930 DECODE : ID;
3931 FPU : S5;
3932 %}
3933
3934 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
3935 %{
3936 single_instruction;
3937 src : S1(read);
3938 dst : S5(write);
3939 DECODE : ID;
3940 FPU : S5;
3941 %}
3942
3943 pipe_class fp_l2f(fRegF dst, iRegL src)
3944 %{
3945 single_instruction;
3946 src : S1(read);
3947 dst : S5(write);
3948 DECODE : ID;
3949 FPU : S5;
3950 %}
3951
3952 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
3953 %{
3954 single_instruction;
3955 src : S1(read);
3956 dst : S5(write);
3957 DECODE : ID;
3958 FPU : S5;
3959 %}
3960
3961 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
3962 %{
3963 single_instruction;
3964 src : S1(read);
3965 dst : S5(write);
3966 DECODE : ID;
3967 FPU : S5;
3968 %}
3969
3970 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
3971 %{
3972 single_instruction;
3973 src : S1(read);
3974 dst : S5(write);
3975 DECODE : ID;
3976 FPU : S5;
3977 %}
3978
3979 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
3980 %{
3981 single_instruction;
3982 src : S1(read);
3983 dst : S5(write);
3984 DECODE : ID;
3985 FPU : S5;
3986 %}
3987
3988 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
3989 %{
3990 single_instruction;
3991 src1 : S1(read);
3992 src2 : S2(read);
3993 dst : S5(write);
3994 DECODE : ID;
3995 FPU : S5;
3996 %}
3997
3998 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
3999 %{
4000 single_instruction;
4001 src1 : S1(read);
4002 src2 : S2(read);
4003 dst : S5(write);
4004 DECODE : ID;
4005 FPU : S5;
4006 %}
4007
4008 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
4009 %{
4010 single_instruction;
4011 src1 : S1(read);
4012 src2 : S2(read);
4013 dst : S5(write);
4014 DECODE : ID;
4015 FPU : S5;
4016 %}
4017
4018 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
4019 %{
4020 single_instruction;
4021 src1 : S1(read);
4022 src2 : S2(read);
4023 dst : S5(write);
4024 DECODE : ID;
4025 FPU : S5;
4026 %}
4027
4028 pipe_class fp_load_constant_s(fRegF dst)
4029 %{
4030 single_instruction;
4031 dst : S5(write);
4032 DECODE : ID;
4033 FPU : S5;
4034 %}
4035
4036 pipe_class fp_load_constant_d(fRegD dst)
4037 %{
4038 single_instruction;
4039 dst : S5(write);
4040 DECODE : ID;
4041 FPU : S5;
4042 %}
4043
4044 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4045 %{
4046 single_instruction;
4047 mem : S1(read);
4048 dst : S5(write);
4049 DECODE : ID;
4050 LDST : MEM;
4051 %}
4052
4053 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4054 %{
4055 single_instruction;
4056 mem : S1(read);
4057 dst : S5(write);
4058 DECODE : ID;
4059 LDST : MEM;
4060 %}
4061
4062 pipe_class fp_store_reg_s(fRegF src, memory mem)
4063 %{
4064 single_instruction;
4065 src : S1(read);
4066 mem : S5(write);
4067 DECODE : ID;
4068 LDST : MEM;
4069 %}
4070
4071 pipe_class fp_store_reg_d(fRegD src, memory mem)
4072 %{
4073 single_instruction;
4074 src : S1(read);
4075 mem : S5(write);
4076 DECODE : ID;
4077 LDST : MEM;
4078 %}
4079
4080 //------- Integer ALU operations --------------------------
4081
4082 // Integer ALU reg-reg operation
4083 // Operands needs in ID, result generated in EX
4084 // E.g. ADD Rd, Rs1, Rs2
4085 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4086 %{
4087 single_instruction;
4088 dst : EX(write);
4089 src1 : ID(read);
4090 src2 : ID(read);
4091 DECODE : ID;
4092 ALU : EX;
4093 %}
4094
4095 // Integer ALU reg operation with constant shift
4096 // E.g. SLLI Rd, Rs1, #shift
4097 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4098 %{
4099 single_instruction;
4100 dst : EX(write);
4101 src1 : ID(read);
4102 DECODE : ID;
4103 ALU : EX;
4104 %}
4105
4106 // Integer ALU reg-reg operation with variable shift
4107 // both operands must be available in ID
4108 // E.g. SLL Rd, Rs1, Rs2
4109 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4110 %{
4111 single_instruction;
4112 dst : EX(write);
4113 src1 : ID(read);
4114 src2 : ID(read);
4115 DECODE : ID;
4116 ALU : EX;
4117 %}
4118
4119 // Integer ALU reg operation
4120 // E.g. NEG Rd, Rs2
4121 pipe_class ialu_reg(iRegI dst, iRegI src)
4122 %{
4123 single_instruction;
4124 dst : EX(write);
4125 src : ID(read);
4126 DECODE : ID;
4127 ALU : EX;
4128 %}
4129
4130 // Integer ALU reg immediate operation
4131 // E.g. ADDI Rd, Rs1, #imm
4132 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4133 %{
4134 single_instruction;
4135 dst : EX(write);
4136 src1 : ID(read);
4137 DECODE : ID;
4138 ALU : EX;
4139 %}
4140
4141 // Integer ALU immediate operation (no source operands)
4142 // E.g. LI Rd, #imm
4143 pipe_class ialu_imm(iRegI dst)
4144 %{
4145 single_instruction;
4146 dst : EX(write);
4147 DECODE : ID;
4148 ALU : EX;
4149 %}
4150
4151 //------- Multiply pipeline operations --------------------
4152
4153 // Multiply reg-reg
4154 // E.g. MULW Rd, Rs1, Rs2
4155 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4156 %{
4157 single_instruction;
4158 dst : WR(write);
4159 src1 : ID(read);
4160 src2 : ID(read);
4161 DECODE : ID;
4162 MUL : WR;
4163 %}
4164
4165 // E.g. MUL RD, Rs1, Rs2
4166 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4167 %{
4168 single_instruction;
4169 fixed_latency(3); // Maximum latency for 64 bit mul
4170 dst : WR(write);
4171 src1 : ID(read);
4172 src2 : ID(read);
4173 DECODE : ID;
4174 MUL : WR;
4175 %}
4176
4177 //------- Divide pipeline operations --------------------
4178
4179 // E.g. DIVW Rd, Rs1, Rs2
4180 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4181 %{
4182 single_instruction;
4183 fixed_latency(8); // Maximum latency for 32 bit divide
4184 dst : WR(write);
4185 src1 : ID(read);
4186 src2 : ID(read);
4187 DECODE : ID;
4188 DIV : WR;
4189 %}
4190
4191 // E.g. DIV RD, Rs1, Rs2
4192 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4193 %{
4194 single_instruction;
4195 fixed_latency(16); // Maximum latency for 64 bit divide
4196 dst : WR(write);
4197 src1 : ID(read);
4198 src2 : ID(read);
4199 DECODE : ID;
4200 DIV : WR;
4201 %}
4202
4203 //------- Load pipeline operations ------------------------
4204
4205 // Load - reg, mem
4206 // E.g. LA Rd, mem
4207 pipe_class iload_reg_mem(iRegI dst, memory mem)
4208 %{
4209 single_instruction;
4210 dst : WR(write);
4211 mem : ID(read);
4212 DECODE : ID;
4213 LDST : MEM;
4214 %}
4215
4216 // Load - reg, reg
4217 // E.g. LD Rd, Rs
4218 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4219 %{
4220 single_instruction;
4221 dst : WR(write);
4222 src : ID(read);
4223 DECODE : ID;
4224 LDST : MEM;
4225 %}
4226
4227 //------- Store pipeline operations -----------------------
4228
4229 // Store - zr, mem
4230 // E.g. SD zr, mem
4231 pipe_class istore_mem(memory mem)
4232 %{
4233 single_instruction;
4234 mem : ID(read);
4235 DECODE : ID;
4236 LDST : MEM;
4237 %}
4238
4239 // Store - reg, mem
4240 // E.g. SD Rs, mem
4241 pipe_class istore_reg_mem(iRegI src, memory mem)
4242 %{
4243 single_instruction;
4244 mem : ID(read);
4245 src : EX(read);
4246 DECODE : ID;
4247 LDST : MEM;
4248 %}
4249
4250 // Store - reg, reg
4251 // E.g. SD Rs2, Rs1
4252 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4253 %{
4254 single_instruction;
4255 dst : ID(read);
4256 src : EX(read);
4257 DECODE : ID;
4258 LDST : MEM;
4259 %}
4260
4261 //------- Control transfer pipeline operations ------------
4262
4263 // Branch
4264 pipe_class pipe_branch()
4265 %{
4266 single_instruction;
4267 DECODE : ID;
4268 BRANCH : EX;
4269 %}
4270
4271 // Branch
4272 pipe_class pipe_branch_reg(iRegI src)
4273 %{
4274 single_instruction;
4275 src : ID(read);
4276 DECODE : ID;
4277 BRANCH : EX;
4278 %}
4279
4280 // Compare & Branch
4281 // E.g. BEQ Rs1, Rs2, L
4282 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4283 %{
4284 single_instruction;
4285 src1 : ID(read);
4286 src2 : ID(read);
4287 DECODE : ID;
4288 BRANCH : EX;
4289 %}
4290
4291 // E.g. BEQZ Rs, L
4292 pipe_class pipe_cmpz_branch(iRegI src)
4293 %{
4294 single_instruction;
4295 src : ID(read);
4296 DECODE : ID;
4297 BRANCH : EX;
4298 %}
4299
4300 //------- Synchronisation operations ----------------------
4301 // Any operation requiring serialization
4302 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4303 pipe_class pipe_serial()
4304 %{
4305 single_instruction;
4306 force_serialization;
4307 fixed_latency(16);
4308 DECODE : ID;
4309 LDST : MEM;
4310 %}
4311
4312 pipe_class pipe_slow()
4313 %{
4314 instruction_count(10);
4315 multiple_bundles;
4316 force_serialization;
4317 fixed_latency(16);
4318 DECODE : ID;
4319 LDST : MEM;
4320 %}
4321
4322 // Empty pipeline class
4323 pipe_class pipe_class_empty()
4324 %{
4325 single_instruction;
4326 fixed_latency(0);
4327 %}
4328
4329 // Default pipeline class.
4330 pipe_class pipe_class_default()
4331 %{
4332 single_instruction;
4333 fixed_latency(2);
4334 %}
4335
4336 // Pipeline class for compares.
4337 pipe_class pipe_class_compare()
4338 %{
4339 single_instruction;
4340 fixed_latency(16);
4341 %}
4342
4343 // Pipeline class for memory operations.
4344 pipe_class pipe_class_memory()
4345 %{
4346 single_instruction;
4347 fixed_latency(16);
4348 %}
4349
4350 // Pipeline class for call.
4351 pipe_class pipe_class_call()
4352 %{
4353 single_instruction;
4354 fixed_latency(100);
4355 %}
4356
4357 // Define the class for the Nop node.
4358 define %{
4359 MachNop = pipe_class_empty;
4360 %}
4361 %}
4362 //----------INSTRUCTIONS-------------------------------------------------------
4363 //
4364 // match -- States which machine-independent subtree may be replaced
4365 // by this instruction.
4366 // ins_cost -- The estimated cost of this instruction is used by instruction
4367 // selection to identify a minimum cost tree of machine
4368 // instructions that matches a tree of machine-independent
4369 // instructions.
4370 // format -- A string providing the disassembly for this instruction.
4371 // The value of an instruction's operand may be inserted
4372 // by referring to it with a '$' prefix.
4373 // opcode -- Three instruction opcodes may be provided. These are referred
4374 // to within an encode class as $primary, $secondary, and $tertiary
4375 // rrspectively. The primary opcode is commonly used to
4376 // indicate the type of machine instruction, while secondary
4377 // and tertiary are often used for prefix options or addressing
4378 // modes.
4379 // ins_encode -- A list of encode classes with parameters. The encode class
4380 // name must have been defined in an 'enc_class' specification
4381 // in the encode section of the architecture description.
4382
4383 // ============================================================================
4384 // Memory (Load/Store) Instructions
4385
4386 // Load Instructions
4387
4388 // Load Byte (8 bit signed)
4389 instruct loadB(iRegINoSp dst, memory mem)
4390 %{
4391 match(Set dst (LoadB mem));
4392
4393 ins_cost(LOAD_COST);
4394 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4395
4396 ins_encode %{
4397 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4398 %}
4399
4400 ins_pipe(iload_reg_mem);
4401 %}
4402
4403 // Load Byte (8 bit signed) into long
4404 instruct loadB2L(iRegLNoSp dst, memory mem)
4405 %{
4406 match(Set dst (ConvI2L (LoadB mem)));
4407
4408 ins_cost(LOAD_COST);
4409 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4410
4411 ins_encode %{
4412 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4413 %}
4414
4415 ins_pipe(iload_reg_mem);
4416 %}
4417
4418 // Load Byte (8 bit unsigned)
4419 instruct loadUB(iRegINoSp dst, memory mem)
4420 %{
4421 match(Set dst (LoadUB mem));
4422
4423 ins_cost(LOAD_COST);
4424 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4425
4426 ins_encode %{
4427 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4428 %}
4429
4430 ins_pipe(iload_reg_mem);
4431 %}
4432
4433 // Load Byte (8 bit unsigned) into long
4434 instruct loadUB2L(iRegLNoSp dst, memory mem)
4435 %{
4436 match(Set dst (ConvI2L (LoadUB mem)));
4437
4438 ins_cost(LOAD_COST);
4439 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4440
4441 ins_encode %{
4442 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4443 %}
4444
4445 ins_pipe(iload_reg_mem);
4446 %}
4447
4448 // Load Short (16 bit signed)
4449 instruct loadS(iRegINoSp dst, memory mem)
4450 %{
4451 match(Set dst (LoadS mem));
4452
4453 ins_cost(LOAD_COST);
4454 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4455
4456 ins_encode %{
4457 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4458 %}
4459
4460 ins_pipe(iload_reg_mem);
4461 %}
4462
4463 // Load Short (16 bit signed) into long
4464 instruct loadS2L(iRegLNoSp dst, memory mem)
4465 %{
4466 match(Set dst (ConvI2L (LoadS mem)));
4467
4468 ins_cost(LOAD_COST);
4469 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4470
4471 ins_encode %{
4472 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4473 %}
4474
4475 ins_pipe(iload_reg_mem);
4476 %}
4477
4478 // Load Char (16 bit unsigned)
4479 instruct loadUS(iRegINoSp dst, memory mem)
4480 %{
4481 match(Set dst (LoadUS mem));
4482
4483 ins_cost(LOAD_COST);
4484 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4485
4486 ins_encode %{
4487 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4488 %}
4489
4490 ins_pipe(iload_reg_mem);
4491 %}
4492
4493 // Load Short/Char (16 bit unsigned) into long
4494 instruct loadUS2L(iRegLNoSp dst, memory mem)
4495 %{
4496 match(Set dst (ConvI2L (LoadUS mem)));
4497
4498 ins_cost(LOAD_COST);
4499 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4500
4501 ins_encode %{
4502 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4503 %}
4504
4505 ins_pipe(iload_reg_mem);
4506 %}
4507
4508 // Load Integer (32 bit signed)
4509 instruct loadI(iRegINoSp dst, memory mem)
4510 %{
4511 match(Set dst (LoadI mem));
4512
4513 ins_cost(LOAD_COST);
4514 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4515
4516 ins_encode %{
4517 Assembler::CompressibleRegion cr(&_masm);
4518 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4519 %}
4520
4521 ins_pipe(iload_reg_mem);
4522 %}
4523
4524 // Load Integer (32 bit signed) into long
4525 instruct loadI2L(iRegLNoSp dst, memory mem)
4526 %{
4527 match(Set dst (ConvI2L (LoadI mem)));
4528
4529 ins_cost(LOAD_COST);
4530 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4531
4532 ins_encode %{
4533 Assembler::CompressibleRegion cr(&_masm);
4534 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4535 %}
4536
4537 ins_pipe(iload_reg_mem);
4538 %}
4539
4540 // Load Integer (32 bit unsigned) into long
4541 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4542 %{
4543 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4544
4545 ins_cost(LOAD_COST);
4546 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4547
4548 ins_encode %{
4549 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4550 %}
4551
4552 ins_pipe(iload_reg_mem);
4553 %}
4554
4555 // Load Long (64 bit signed)
4556 instruct loadL(iRegLNoSp dst, memory mem)
4557 %{
4558 match(Set dst (LoadL mem));
4559
4560 ins_cost(LOAD_COST);
4561 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4562
4563 ins_encode %{
4564 Assembler::CompressibleRegion cr(&_masm);
4565 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4566 %}
4567
4568 ins_pipe(iload_reg_mem);
4569 %}
4570
4571 // Load Range
4572 instruct loadRange(iRegINoSp dst, memory mem)
4573 %{
4574 match(Set dst (LoadRange mem));
4575
4576 ins_cost(LOAD_COST);
4577 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4578
4579 ins_encode %{
4580 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4581 %}
4582
4583 ins_pipe(iload_reg_mem);
4584 %}
4585
4586 // Load Pointer
4587 instruct loadP(iRegPNoSp dst, memory mem)
4588 %{
4589 match(Set dst (LoadP mem));
4590 predicate(n->as_Load()->barrier_data() == 0);
4591
4592 ins_cost(LOAD_COST);
4593 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4594
4595 ins_encode %{
4596 Assembler::CompressibleRegion cr(&_masm);
4597 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4598 %}
4599
4600 ins_pipe(iload_reg_mem);
4601 %}
4602
4603 // Load Compressed Pointer
4604 instruct loadN(iRegNNoSp dst, memory mem)
4605 %{
4606 match(Set dst (LoadN mem));
4607
4608 ins_cost(LOAD_COST);
4609 format %{ "lwu $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
4610
4611 ins_encode %{
4612 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4613 %}
4614
4615 ins_pipe(iload_reg_mem);
4616 %}
4617
4618 // Load Klass Pointer
4619 instruct loadKlass(iRegPNoSp dst, memory mem)
4620 %{
4621 match(Set dst (LoadKlass mem));
4622
4623 ins_cost(LOAD_COST);
4624 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4625
4626 ins_encode %{
4627 Assembler::CompressibleRegion cr(&_masm);
4628 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4629 %}
4630
4631 ins_pipe(iload_reg_mem);
4632 %}
4633
4634 // Load Narrow Klass Pointer
4635 instruct loadNKlass(iRegNNoSp dst, memory mem)
4636 %{
4637 match(Set dst (LoadNKlass mem));
4638
4639 ins_cost(LOAD_COST);
4640 format %{ "lwu $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
4641
4642 ins_encode %{
4643 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4644 %}
4645
4646 ins_pipe(iload_reg_mem);
4647 %}
4648
4649 // Load Float
4650 instruct loadF(fRegF dst, memory mem)
4651 %{
4652 match(Set dst (LoadF mem));
4653
4654 ins_cost(LOAD_COST);
4655 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4656
4657 ins_encode %{
4658 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4659 %}
4660
4661 ins_pipe(fp_load_mem_s);
4662 %}
4663
4664 // Load Double
4665 instruct loadD(fRegD dst, memory mem)
4666 %{
4667 match(Set dst (LoadD mem));
4668
4669 ins_cost(LOAD_COST);
4670 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4671
4672 ins_encode %{
4673 Assembler::CompressibleRegion cr(&_masm);
4674 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4675 %}
4676
4677 ins_pipe(fp_load_mem_d);
4678 %}
4679
4680 // Load Int Constant
4681 instruct loadConI(iRegINoSp dst, immI src)
4682 %{
4683 match(Set dst src);
4684
4685 ins_cost(ALU_COST);
4686 format %{ "li $dst, $src\t# int, #@loadConI" %}
4687
4688 ins_encode(riscv_enc_li_imm(dst, src));
4689
4690 ins_pipe(ialu_imm);
4691 %}
4692
4693 // Load Long Constant
4694 instruct loadConL(iRegLNoSp dst, immL src)
4695 %{
4696 match(Set dst src);
4697
4698 ins_cost(ALU_COST);
4699 format %{ "li $dst, $src\t# long, #@loadConL" %}
4700
4701 ins_encode(riscv_enc_li_imm(dst, src));
4702
4703 ins_pipe(ialu_imm);
4704 %}
4705
4706 // Load Pointer Constant
4707 instruct loadConP(iRegPNoSp dst, immP con)
4708 %{
4709 match(Set dst con);
4710
4711 ins_cost(ALU_COST);
4712 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4713
4714 ins_encode(riscv_enc_mov_p(dst, con));
4715
4716 ins_pipe(ialu_imm);
4717 %}
4718
4719 // Load Null Pointer Constant
4720 instruct loadConP0(iRegPNoSp dst, immP0 con)
4721 %{
4722 match(Set dst con);
4723
4724 ins_cost(ALU_COST);
4725 format %{ "mv $dst, $con\t# NULL ptr, #@loadConP0" %}
4726
4727 ins_encode(riscv_enc_mov_zero(dst));
4728
4729 ins_pipe(ialu_imm);
4730 %}
4731
4732 // Load Pointer Constant One
4733 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4734 %{
4735 match(Set dst con);
4736
4737 ins_cost(ALU_COST);
4738 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4739
4740 ins_encode(riscv_enc_mov_p1(dst));
4741
4742 ins_pipe(ialu_imm);
4743 %}
4744
4745 // Load Byte Map Base Constant
4746 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4747 %{
4748 match(Set dst con);
4749 ins_cost(ALU_COST);
4750 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4751
4752 ins_encode(riscv_enc_mov_byte_map_base(dst));
4753
4754 ins_pipe(ialu_imm);
4755 %}
4756
4757 // Load Narrow Pointer Constant
4758 instruct loadConN(iRegNNoSp dst, immN con)
4759 %{
4760 match(Set dst con);
4761
4762 ins_cost(ALU_COST * 4);
4763 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4764
4765 ins_encode(riscv_enc_mov_n(dst, con));
4766
4767 ins_pipe(ialu_imm);
4768 %}
4769
4770 // Load Narrow Null Pointer Constant
4771 instruct loadConN0(iRegNNoSp dst, immN0 con)
4772 %{
4773 match(Set dst con);
4774
4775 ins_cost(ALU_COST);
4776 format %{ "mv $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
4777
4778 ins_encode(riscv_enc_mov_zero(dst));
4779
4780 ins_pipe(ialu_imm);
4781 %}
4782
4783 // Load Narrow Klass Constant
4784 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4785 %{
4786 match(Set dst con);
4787
4788 ins_cost(ALU_COST * 6);
4789 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4790
4791 ins_encode(riscv_enc_mov_nk(dst, con));
4792
4793 ins_pipe(ialu_imm);
4794 %}
4795
4796 // Load Float Constant
4797 instruct loadConF(fRegF dst, immF con) %{
4798 match(Set dst con);
4799
4800 ins_cost(LOAD_COST);
4801 format %{
4802 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4803 %}
4804
4805 ins_encode %{
4806 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4807 %}
4808
4809 ins_pipe(fp_load_constant_s);
4810 %}
4811
4812 instruct loadConF0(fRegF dst, immF0 con) %{
4813 match(Set dst con);
4814
4815 ins_cost(XFER_COST);
4816
4817 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4818
4819 ins_encode %{
4820 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4821 %}
4822
4823 ins_pipe(fp_load_constant_s);
4824 %}
4825
4826 // Load Double Constant
4827 instruct loadConD(fRegD dst, immD con) %{
4828 match(Set dst con);
4829
4830 ins_cost(LOAD_COST);
4831 format %{
4832 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4833 %}
4834
4835 ins_encode %{
4836 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4837 %}
4838
4839 ins_pipe(fp_load_constant_d);
4840 %}
4841
4842 instruct loadConD0(fRegD dst, immD0 con) %{
4843 match(Set dst con);
4844
4845 ins_cost(XFER_COST);
4846
4847 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4848
4849 ins_encode %{
4850 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4851 %}
4852
4853 ins_pipe(fp_load_constant_d);
4854 %}
4855
4856 // Store Instructions
4857 // Store CMS card-mark Immediate
4858 instruct storeimmCM0(immI0 zero, memory mem)
4859 %{
4860 match(Set mem (StoreCM mem zero));
4861
4862 ins_cost(STORE_COST);
4863 format %{ "storestore (elided)\n\t"
4864 "sb zr, $mem\t# byte, #@storeimmCM0" %}
4865
4866 ins_encode %{
4867 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4868 %}
4869
4870 ins_pipe(istore_mem);
4871 %}
4872
4873 // Store CMS card-mark Immediate with intervening StoreStore
4874 // needed when using CMS with no conditional card marking
4875 instruct storeimmCM0_ordered(immI0 zero, memory mem)
4876 %{
4877 match(Set mem (StoreCM mem zero));
4878
4879 ins_cost(ALU_COST + STORE_COST);
4880 format %{ "membar(StoreStore)\n\t"
4881 "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
4882
4883 ins_encode %{
4884 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
4885 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4886 %}
4887
4888 ins_pipe(istore_mem);
4889 %}
4890
4891 // Store Byte
4892 instruct storeB(iRegIorL2I src, memory mem)
4893 %{
4894 match(Set mem (StoreB mem src));
4895
4896 ins_cost(STORE_COST);
4897 format %{ "sb $src, $mem\t# byte, #@storeB" %}
4898
4899 ins_encode %{
4900 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4901 %}
4902
4903 ins_pipe(istore_reg_mem);
4904 %}
4905
4906 instruct storeimmB0(immI0 zero, memory mem)
4907 %{
4908 match(Set mem (StoreB mem zero));
4909
4910 ins_cost(STORE_COST);
4911 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
4912
4913 ins_encode %{
4914 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
4915 %}
4916
4917 ins_pipe(istore_mem);
4918 %}
4919
4920 // Store Char/Short
4921 instruct storeC(iRegIorL2I src, memory mem)
4922 %{
4923 match(Set mem (StoreC mem src));
4924
4925 ins_cost(STORE_COST);
4926 format %{ "sh $src, $mem\t# short, #@storeC" %}
4927
4928 ins_encode %{
4929 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4930 %}
4931
4932 ins_pipe(istore_reg_mem);
4933 %}
4934
4935 instruct storeimmC0(immI0 zero, memory mem)
4936 %{
4937 match(Set mem (StoreC mem zero));
4938
4939 ins_cost(STORE_COST);
4940 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
4941
4942 ins_encode %{
4943 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
4944 %}
4945
4946 ins_pipe(istore_mem);
4947 %}
4948
4949 // Store Integer
4950 instruct storeI(iRegIorL2I src, memory mem)
4951 %{
4952 match(Set mem(StoreI mem src));
4953
4954 ins_cost(STORE_COST);
4955 format %{ "sw $src, $mem\t# int, #@storeI" %}
4956
4957 ins_encode %{
4958 Assembler::CompressibleRegion cr(&_masm);
4959 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4960 %}
4961
4962 ins_pipe(istore_reg_mem);
4963 %}
4964
4965 instruct storeimmI0(immI0 zero, memory mem)
4966 %{
4967 match(Set mem(StoreI mem zero));
4968
4969 ins_cost(STORE_COST);
4970 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
4971
4972 ins_encode %{
4973 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
4974 %}
4975
4976 ins_pipe(istore_mem);
4977 %}
4978
4979 // Store Long (64 bit signed)
4980 instruct storeL(iRegL src, memory mem)
4981 %{
4982 match(Set mem (StoreL mem src));
4983
4984 ins_cost(STORE_COST);
4985 format %{ "sd $src, $mem\t# long, #@storeL" %}
4986
4987 ins_encode %{
4988 Assembler::CompressibleRegion cr(&_masm);
4989 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
4990 %}
4991
4992 ins_pipe(istore_reg_mem);
4993 %}
4994
4995 // Store Long (64 bit signed)
4996 instruct storeimmL0(immL0 zero, memory mem)
4997 %{
4998 match(Set mem (StoreL mem zero));
4999
5000 ins_cost(STORE_COST);
5001 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5002
5003 ins_encode %{
5004 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5005 %}
5006
5007 ins_pipe(istore_mem);
5008 %}
5009
5010 // Store Pointer
5011 instruct storeP(iRegP src, memory mem)
5012 %{
5013 match(Set mem (StoreP mem src));
5014
5015 ins_cost(STORE_COST);
5016 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5017
5018 ins_encode %{
5019 Assembler::CompressibleRegion cr(&_masm);
5020 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5021 %}
5022
5023 ins_pipe(istore_reg_mem);
5024 %}
5025
5026 // Store Pointer
5027 instruct storeimmP0(immP0 zero, memory mem)
5028 %{
5029 match(Set mem (StoreP mem zero));
5030
5031 ins_cost(STORE_COST);
5032 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5033
5034 ins_encode %{
5035 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5036 %}
5037
5038 ins_pipe(istore_mem);
5039 %}
5040
5041 // Store Compressed Pointer
5042 instruct storeN(iRegN src, memory mem)
5043 %{
5044 match(Set mem (StoreN mem src));
5045
5046 ins_cost(STORE_COST);
5047 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5048
5049 ins_encode %{
5050 Assembler::CompressibleRegion cr(&_masm);
5051 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5052 %}
5053
5054 ins_pipe(istore_reg_mem);
5055 %}
5056
5057 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
5058 %{
5059 match(Set mem (StoreN mem zero));
5060
5061 ins_cost(STORE_COST);
5062 format %{ "sw rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
5063
5064 ins_encode %{
5065 __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
5066 %}
5067
5068 ins_pipe(istore_reg_mem);
5069 %}
5070
5071 // Store Float
5072 instruct storeF(fRegF src, memory mem)
5073 %{
5074 match(Set mem (StoreF mem src));
5075
5076 ins_cost(STORE_COST);
5077 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5078
5079 ins_encode %{
5080 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5081 %}
5082
5083 ins_pipe(fp_store_reg_s);
5084 %}
5085
5086 // Store Double
5087 instruct storeD(fRegD src, memory mem)
5088 %{
5089 match(Set mem (StoreD mem src));
5090
5091 ins_cost(STORE_COST);
5092 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5093
5094 ins_encode %{
5095 Assembler::CompressibleRegion cr(&_masm);
5096 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5097 %}
5098
5099 ins_pipe(fp_store_reg_d);
5100 %}
5101
5102 // Store Compressed Klass Pointer
5103 instruct storeNKlass(iRegN src, memory mem)
5104 %{
5105 match(Set mem (StoreNKlass mem src));
5106
5107 ins_cost(STORE_COST);
5108 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5109
5110 ins_encode %{
5111 Assembler::CompressibleRegion cr(&_masm);
5112 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5113 %}
5114
5115 ins_pipe(istore_reg_mem);
5116 %}
5117
5118 // ============================================================================
5119 // Atomic operation instructions
5120 //
5121 // Intel and SPARC both implement Ideal Node LoadPLocked and
5122 // Store{PIL}Conditional instructions using a normal load for the
5123 // LoadPLocked and a CAS for the Store{PIL}Conditional.
5124 //
5125 // The ideal code appears only to use LoadPLocked/storePConditional as a
5126 // pair to lock object allocations from Eden space when not using
5127 // TLABs.
5128 //
5129 // There does not appear to be a Load{IL}Locked Ideal Node and the
5130 // Ideal code appears to use Store{IL}Conditional as an alias for CAS
5131 // and to use StoreIConditional only for 32-bit and StoreLConditional
5132 // only for 64-bit.
5133 //
5134 // We implement LoadPLocked and storePConditional instructions using,
5135 // respectively the RISCV hw load-reserve and store-conditional
5136 // instructions. Whereas we must implement each of
5137 // Store{IL}Conditional using a CAS which employs a pair of
5138 // instructions comprising a load-reserve followed by a
5139 // store-conditional.
5140
5141
5142 // Locked-load (load reserved) of the current heap-top
5143 // used when updating the eden heap top
5144 // implemented using lr_d on RISCV64
5145 instruct loadPLocked(iRegPNoSp dst, indirect mem)
5146 %{
5147 match(Set dst (LoadPLocked mem));
5148
5149 ins_cost(ALU_COST * 2 + LOAD_COST);
5150
5151 format %{ "lr.d $dst, $mem\t# ptr load reserved, #@loadPLocked" %}
5152
5153 ins_encode %{
5154 __ la(t0, Address(as_Register($mem$$base), $mem$$disp));
5155 __ lr_d($dst$$Register, t0, Assembler::aq);
5156 %}
5157
5158 ins_pipe(pipe_serial);
5159 %}
5160
5161 // Conditional-store of the updated heap-top.
5162 // Used during allocation of the shared heap.
5163 // implemented using sc_d on RISCV64.
5164 instruct storePConditional(memory heap_top_ptr, iRegP oldval, iRegP newval, rFlagsReg cr)
5165 %{
5166 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
5167
5168 ins_cost(ALU_COST * 2 + STORE_COST);
5169
5170 format %{
5171 "sc_d t1, $newval $heap_top_ptr,\t# ptr store conditional, #@storePConditional"
5172 %}
5173
5174 ins_encode %{
5175 __ la(t0, Address(as_Register($heap_top_ptr$$base), $heap_top_ptr$$disp));
5176 __ sc_d($cr$$Register, $newval$$Register, t0, Assembler::rl);
5177 %}
5178
5179 ins_pipe(pipe_serial);
5180 %}
5181
5182 instruct storeLConditional(indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr)
5183 %{
5184 match(Set cr (StoreLConditional mem (Binary oldval newval)));
5185
5186 ins_cost(LOAD_COST + STORE_COST + 2 * BRANCH_COST);
5187
5188 format %{
5189 "cmpxchg t1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
5190 "xorr $cr, $cr, $oldval\t# $cr == 0 on successful write, #@storeLConditional"
5191 %}
5192
5193 ins_encode %{
5194 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5195 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $cr$$Register);
5196 __ xorr($cr$$Register,$cr$$Register, $oldval$$Register);
5197 %}
5198
5199 ins_pipe(pipe_slow);
5200 %}
5201
5202 // storeIConditional also has acquire semantics, for no better reason
5203 // than matching storeLConditional.
5204 instruct storeIConditional(indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr)
5205 %{
5206 match(Set cr (StoreIConditional mem (Binary oldval newval)));
5207
5208 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2);
5209
5210 format %{
5211 "cmpxchgw t1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
5212 "xorr $cr, $cr, $oldval\t# $cr == 0 on successful write, #@storeIConditional"
5213 %}
5214
5215 ins_encode %{
5216 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5217 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $cr$$Register);
5218 __ xorr($cr$$Register,$cr$$Register, $oldval$$Register);
5219 %}
5220
5221 ins_pipe(pipe_slow);
5222 %}
5223
5224 // standard CompareAndSwapX when we are using barriers
5225 // these have higher priority than the rules selected by a predicate
5226 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5227 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5228 %{
5229 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5230
5231 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5232
5233 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5234
5235 format %{
5236 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5237 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5238 %}
5239
5240 ins_encode %{
5241 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5242 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5243 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5244 %}
5245
5246 ins_pipe(pipe_slow);
5247 %}
5248
5249 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5250 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5251 %{
5252 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5253
5254 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5255
5256 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5257
5258 format %{
5259 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5260 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5261 %}
5262
5263 ins_encode %{
5264 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5265 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5266 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5267 %}
5268
5269 ins_pipe(pipe_slow);
5270 %}
5271
5272 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5273 %{
5274 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5275
5276 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5277
5278 format %{
5279 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5280 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5281 %}
5282
5283 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5284
5285 ins_pipe(pipe_slow);
5286 %}
5287
5288 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5289 %{
5290 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5291
5292 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5293
5294 format %{
5295 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5296 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5297 %}
5298
5299 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5300
5301 ins_pipe(pipe_slow);
5302 %}
5303
5304 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5305 %{
5306 predicate(n->as_LoadStore()->barrier_data() == 0);
5307
5308 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5309
5310 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5311
5312 format %{
5313 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5314 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5315 %}
5316
5317 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5318
5319 ins_pipe(pipe_slow);
5320 %}
5321
5322 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5323 %{
5324 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5325
5326 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5327
5328 format %{
5329 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5330 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5331 %}
5332
5333 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5334
5335 ins_pipe(pipe_slow);
5336 %}
5337
5338 // alternative CompareAndSwapX when we are eliding barriers
5339 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5340 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5341 %{
5342 predicate(needs_acquiring_load_reserved(n));
5343
5344 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5345
5346 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5347
5348 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5349
5350 format %{
5351 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5352 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5353 %}
5354
5355 ins_encode %{
5356 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5357 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5358 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5359 %}
5360
5361 ins_pipe(pipe_slow);
5362 %}
5363
5364 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5365 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5366 %{
5367 predicate(needs_acquiring_load_reserved(n));
5368
5369 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5370
5371 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5372
5373 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5374
5375 format %{
5376 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5377 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5378 %}
5379
5380 ins_encode %{
5381 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5382 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5383 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5384 %}
5385
5386 ins_pipe(pipe_slow);
5387 %}
5388
5389 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5390 %{
5391 predicate(needs_acquiring_load_reserved(n));
5392
5393 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5394
5395 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5396
5397 format %{
5398 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5399 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5400 %}
5401
5402 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5403
5404 ins_pipe(pipe_slow);
5405 %}
5406
5407 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5408 %{
5409 predicate(needs_acquiring_load_reserved(n));
5410
5411 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5412
5413 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5414
5415 format %{
5416 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5417 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5418 %}
5419
5420 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5421
5422 ins_pipe(pipe_slow);
5423 %}
5424
5425 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5426 %{
5427 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5428
5429 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5430
5431 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5432
5433 format %{
5434 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5435 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5436 %}
5437
5438 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5439
5440 ins_pipe(pipe_slow);
5441 %}
5442
5443 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5444 %{
5445 predicate(needs_acquiring_load_reserved(n));
5446
5447 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5448
5449 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5450
5451 format %{
5452 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5453 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5454 %}
5455
5456 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5457
5458 ins_pipe(pipe_slow);
5459 %}
5460
5461 // Sundry CAS operations. Note that release is always true,
5462 // regardless of the memory ordering of the CAS. This is because we
5463 // need the volatile case to be sequentially consistent but there is
5464 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5465 // can't check the type of memory ordering here, so we always emit a
5466 // sc_d(w) with rl bit set.
5467 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5468 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5469 %{
5470 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5471
5472 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5473
5474 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5475
5476 format %{
5477 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5478 %}
5479
5480 ins_encode %{
5481 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5482 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5483 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5484 %}
5485
5486 ins_pipe(pipe_slow);
5487 %}
5488
5489 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5490 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5491 %{
5492 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5493
5494 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5495
5496 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5497
5498 format %{
5499 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5500 %}
5501
5502 ins_encode %{
5503 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5504 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5505 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5506 %}
5507
5508 ins_pipe(pipe_slow);
5509 %}
5510
5511 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5512 %{
5513 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5514
5515 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5516
5517 effect(TEMP_DEF res);
5518
5519 format %{
5520 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5521 %}
5522
5523 ins_encode %{
5524 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5525 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5526 %}
5527
5528 ins_pipe(pipe_slow);
5529 %}
5530
5531 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5532 %{
5533 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5534
5535 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5536
5537 effect(TEMP_DEF res);
5538
5539 format %{
5540 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5541 %}
5542
5543 ins_encode %{
5544 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5545 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5546 %}
5547
5548 ins_pipe(pipe_slow);
5549 %}
5550
5551 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5552 %{
5553 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5554
5555 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5556
5557 effect(TEMP_DEF res);
5558
5559 format %{
5560 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5561 %}
5562
5563 ins_encode %{
5564 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5565 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5566 %}
5567
5568 ins_pipe(pipe_slow);
5569 %}
5570
5571 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5572 %{
5573 predicate(n->as_LoadStore()->barrier_data() == 0);
5574 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5575
5576 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5577
5578 effect(TEMP_DEF res);
5579
5580 format %{
5581 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5582 %}
5583
5584 ins_encode %{
5585 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5586 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5587 %}
5588
5589 ins_pipe(pipe_slow);
5590 %}
5591
5592 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5593 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5594 %{
5595 predicate(needs_acquiring_load_reserved(n));
5596
5597 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5598
5599 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5600
5601 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5602
5603 format %{
5604 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5605 %}
5606
5607 ins_encode %{
5608 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5609 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5610 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5611 %}
5612
5613 ins_pipe(pipe_slow);
5614 %}
5615
5616 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5617 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5618 %{
5619 predicate(needs_acquiring_load_reserved(n));
5620
5621 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5622
5623 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5624
5625 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5626
5627 format %{
5628 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5629 %}
5630
5631 ins_encode %{
5632 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5633 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5634 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5635 %}
5636
5637 ins_pipe(pipe_slow);
5638 %}
5639
5640 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5641 %{
5642 predicate(needs_acquiring_load_reserved(n));
5643
5644 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5645
5646 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5647
5648 effect(TEMP_DEF res);
5649
5650 format %{
5651 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5652 %}
5653
5654 ins_encode %{
5655 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5656 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5657 %}
5658
5659 ins_pipe(pipe_slow);
5660 %}
5661
5662 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5663 %{
5664 predicate(needs_acquiring_load_reserved(n));
5665
5666 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5667
5668 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5669
5670 effect(TEMP_DEF res);
5671
5672 format %{
5673 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5674 %}
5675
5676 ins_encode %{
5677 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5678 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5679 %}
5680
5681 ins_pipe(pipe_slow);
5682 %}
5683
5684 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5685 %{
5686 predicate(needs_acquiring_load_reserved(n));
5687
5688 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5689
5690 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5691
5692 effect(TEMP_DEF res);
5693
5694 format %{
5695 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5696 %}
5697
5698 ins_encode %{
5699 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5700 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5701 %}
5702
5703 ins_pipe(pipe_slow);
5704 %}
5705
5706 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5707 %{
5708 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5709
5710 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5711
5712 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5713
5714 effect(TEMP_DEF res);
5715
5716 format %{
5717 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5718 %}
5719
5720 ins_encode %{
5721 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5722 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5723 %}
5724
5725 ins_pipe(pipe_slow);
5726 %}
5727
5728 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5729 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5730 %{
5731 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5732
5733 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5734
5735 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5736
5737 format %{
5738 "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5739 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapB"
5740 %}
5741
5742 ins_encode %{
5743 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5744 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5745 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5746 __ xori($res$$Register, $res$$Register, 1);
5747 %}
5748
5749 ins_pipe(pipe_slow);
5750 %}
5751
5752 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5753 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5754 %{
5755 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5756
5757 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5758
5759 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5760
5761 format %{
5762 "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5763 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapS"
5764 %}
5765
5766 ins_encode %{
5767 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5768 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5769 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5770 __ xori($res$$Register, $res$$Register, 1);
5771 %}
5772
5773 ins_pipe(pipe_slow);
5774 %}
5775
5776 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5777 %{
5778 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5779
5780 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5781
5782 format %{
5783 "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5784 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapI"
5785 %}
5786
5787 ins_encode %{
5788 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5789 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5790 __ xori($res$$Register, $res$$Register, 1);
5791 %}
5792
5793 ins_pipe(pipe_slow);
5794 %}
5795
5796 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5797 %{
5798 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5799
5800 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5801
5802 format %{
5803 "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5804 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapL"
5805 %}
5806
5807 ins_encode %{
5808 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5809 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5810 __ xori($res$$Register, $res$$Register, 1);
5811 %}
5812
5813 ins_pipe(pipe_slow);
5814 %}
5815
5816 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5817 %{
5818 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5819
5820 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5821
5822 format %{
5823 "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5824 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapN"
5825 %}
5826
5827 ins_encode %{
5828 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5829 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5830 __ xori($res$$Register, $res$$Register, 1);
5831 %}
5832
5833 ins_pipe(pipe_slow);
5834 %}
5835
5836 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5837 %{
5838 predicate(n->as_LoadStore()->barrier_data() == 0);
5839 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5840
5841 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5842
5843 format %{
5844 "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5845 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapP"
5846 %}
5847
5848 ins_encode %{
5849 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5850 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5851 __ xori($res$$Register, $res$$Register, 1);
5852 %}
5853
5854 ins_pipe(pipe_slow);
5855 %}
5856
5857 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5858 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5859 %{
5860 predicate(needs_acquiring_load_reserved(n));
5861
5862 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5863
5864 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5865
5866 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5867
5868 format %{
5869 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5870 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapBAcq"
5871 %}
5872
5873 ins_encode %{
5874 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5875 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5876 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5877 __ xori($res$$Register, $res$$Register, 1);
5878 %}
5879
5880 ins_pipe(pipe_slow);
5881 %}
5882
5883 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5884 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5885 %{
5886 predicate(needs_acquiring_load_reserved(n));
5887
5888 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5889
5890 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5891
5892 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5893
5894 format %{
5895 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5896 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapSAcq"
5897 %}
5898
5899 ins_encode %{
5900 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5901 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5902 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5903 __ xori($res$$Register, $res$$Register, 1);
5904 %}
5905
5906 ins_pipe(pipe_slow);
5907 %}
5908
5909 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5910 %{
5911 predicate(needs_acquiring_load_reserved(n));
5912
5913 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5914
5915 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5916
5917 format %{
5918 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5919 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapIAcq"
5920 %}
5921
5922 ins_encode %{
5923 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5924 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5925 __ xori($res$$Register, $res$$Register, 1);
5926 %}
5927
5928 ins_pipe(pipe_slow);
5929 %}
5930
5931 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5932 %{
5933 predicate(needs_acquiring_load_reserved(n));
5934
5935 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5936
5937 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5938
5939 format %{
5940 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5941 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapLAcq"
5942 %}
5943
5944 ins_encode %{
5945 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5946 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5947 __ xori($res$$Register, $res$$Register, 1);
5948 %}
5949
5950 ins_pipe(pipe_slow);
5951 %}
5952
5953 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5954 %{
5955 predicate(needs_acquiring_load_reserved(n));
5956
5957 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5958
5959 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5960
5961 format %{
5962 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5963 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapNAcq"
5964 %}
5965
5966 ins_encode %{
5967 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5968 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5969 __ xori($res$$Register, $res$$Register, 1);
5970 %}
5971
5972 ins_pipe(pipe_slow);
5973 %}
5974
5975 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5976 %{
5977 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5978
5979 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5980
5981 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5982
5983 format %{
5984 "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5985 "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
5986 %}
5987
5988 ins_encode %{
5989 __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5990 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5991 __ xori($res$$Register, $res$$Register, 1);
5992 %}
5993
5994 ins_pipe(pipe_slow);
5995 %}
5996
5997 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
5998 %{
5999 match(Set prev (GetAndSetI mem newv));
6000
6001 ins_cost(ALU_COST);
6002
6003 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6004
6005 ins_encode %{
6006 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6007 %}
6008
6009 ins_pipe(pipe_serial);
6010 %}
6011
6012 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6013 %{
6014 match(Set prev (GetAndSetL mem newv));
6015
6016 ins_cost(ALU_COST);
6017
6018 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6019
6020 ins_encode %{
6021 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6022 %}
6023
6024 ins_pipe(pipe_serial);
6025 %}
6026
6027 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6028 %{
6029 match(Set prev (GetAndSetN mem newv));
6030
6031 ins_cost(ALU_COST);
6032
6033 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6034
6035 ins_encode %{
6036 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6037 %}
6038
6039 ins_pipe(pipe_serial);
6040 %}
6041
6042 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6043 %{
6044 predicate(n->as_LoadStore()->barrier_data() == 0);
6045 match(Set prev (GetAndSetP mem newv));
6046
6047 ins_cost(ALU_COST);
6048
6049 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6050
6051 ins_encode %{
6052 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6053 %}
6054
6055 ins_pipe(pipe_serial);
6056 %}
6057
6058 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6059 %{
6060 predicate(needs_acquiring_load_reserved(n));
6061
6062 match(Set prev (GetAndSetI mem newv));
6063
6064 ins_cost(ALU_COST);
6065
6066 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6067
6068 ins_encode %{
6069 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6070 %}
6071
6072 ins_pipe(pipe_serial);
6073 %}
6074
6075 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6076 %{
6077 predicate(needs_acquiring_load_reserved(n));
6078
6079 match(Set prev (GetAndSetL mem newv));
6080
6081 ins_cost(ALU_COST);
6082
6083 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6084
6085 ins_encode %{
6086 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6087 %}
6088
6089 ins_pipe(pipe_serial);
6090 %}
6091
6092 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6093 %{
6094 predicate(needs_acquiring_load_reserved(n));
6095
6096 match(Set prev (GetAndSetN mem newv));
6097
6098 ins_cost(ALU_COST);
6099
6100 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6101
6102 ins_encode %{
6103 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6104 %}
6105
6106 ins_pipe(pipe_serial);
6107 %}
6108
6109 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6110 %{
6111 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6112
6113 match(Set prev (GetAndSetP mem newv));
6114
6115 ins_cost(ALU_COST);
6116
6117 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6118
6119 ins_encode %{
6120 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6121 %}
6122
6123 ins_pipe(pipe_serial);
6124 %}
6125
6126 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6127 %{
6128 match(Set newval (GetAndAddL mem incr));
6129
6130 ins_cost(ALU_COST);
6131
6132 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6133
6134 ins_encode %{
6135 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6136 %}
6137
6138 ins_pipe(pipe_serial);
6139 %}
6140
6141 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6142 %{
6143 predicate(n->as_LoadStore()->result_not_used());
6144
6145 match(Set dummy (GetAndAddL mem incr));
6146
6147 ins_cost(ALU_COST);
6148
6149 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6150
6151 ins_encode %{
6152 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6153 %}
6154
6155 ins_pipe(pipe_serial);
6156 %}
6157
6158 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6159 %{
6160 match(Set newval (GetAndAddL mem incr));
6161
6162 ins_cost(ALU_COST);
6163
6164 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6165
6166 ins_encode %{
6167 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6168 %}
6169
6170 ins_pipe(pipe_serial);
6171 %}
6172
6173 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6174 %{
6175 predicate(n->as_LoadStore()->result_not_used());
6176
6177 match(Set dummy (GetAndAddL mem incr));
6178
6179 ins_cost(ALU_COST);
6180
6181 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6182
6183 ins_encode %{
6184 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6185 %}
6186
6187 ins_pipe(pipe_serial);
6188 %}
6189
6190 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6191 %{
6192 match(Set newval (GetAndAddI mem incr));
6193
6194 ins_cost(ALU_COST);
6195
6196 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6197
6198 ins_encode %{
6199 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6200 %}
6201
6202 ins_pipe(pipe_serial);
6203 %}
6204
6205 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6206 %{
6207 predicate(n->as_LoadStore()->result_not_used());
6208
6209 match(Set dummy (GetAndAddI mem incr));
6210
6211 ins_cost(ALU_COST);
6212
6213 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6214
6215 ins_encode %{
6216 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6217 %}
6218
6219 ins_pipe(pipe_serial);
6220 %}
6221
6222 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6223 %{
6224 match(Set newval (GetAndAddI mem incr));
6225
6226 ins_cost(ALU_COST);
6227
6228 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6229
6230 ins_encode %{
6231 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6232 %}
6233
6234 ins_pipe(pipe_serial);
6235 %}
6236
6237 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6238 %{
6239 predicate(n->as_LoadStore()->result_not_used());
6240
6241 match(Set dummy (GetAndAddI mem incr));
6242
6243 ins_cost(ALU_COST);
6244
6245 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6246
6247 ins_encode %{
6248 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6249 %}
6250
6251 ins_pipe(pipe_serial);
6252 %}
6253
6254 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6255 %{
6256 predicate(needs_acquiring_load_reserved(n));
6257
6258 match(Set newval (GetAndAddL mem incr));
6259
6260 ins_cost(ALU_COST);
6261
6262 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6263
6264 ins_encode %{
6265 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6266 %}
6267
6268 ins_pipe(pipe_serial);
6269 %}
6270
6271 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6272 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6273
6274 match(Set dummy (GetAndAddL mem incr));
6275
6276 ins_cost(ALU_COST);
6277
6278 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6279
6280 ins_encode %{
6281 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6282 %}
6283
6284 ins_pipe(pipe_serial);
6285 %}
6286
6287 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6288 %{
6289 predicate(needs_acquiring_load_reserved(n));
6290
6291 match(Set newval (GetAndAddL mem incr));
6292
6293 ins_cost(ALU_COST);
6294
6295 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6296
6297 ins_encode %{
6298 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6299 %}
6300
6301 ins_pipe(pipe_serial);
6302 %}
6303
6304 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6305 %{
6306 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6307
6308 match(Set dummy (GetAndAddL mem incr));
6309
6310 ins_cost(ALU_COST);
6311
6312 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6313
6314 ins_encode %{
6315 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6316 %}
6317
6318 ins_pipe(pipe_serial);
6319 %}
6320
6321 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6322 %{
6323 predicate(needs_acquiring_load_reserved(n));
6324
6325 match(Set newval (GetAndAddI mem incr));
6326
6327 ins_cost(ALU_COST);
6328
6329 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6330
6331 ins_encode %{
6332 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6333 %}
6334
6335 ins_pipe(pipe_serial);
6336 %}
6337
6338 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6339 %{
6340 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6341
6342 match(Set dummy (GetAndAddI mem incr));
6343
6344 ins_cost(ALU_COST);
6345
6346 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6347
6348 ins_encode %{
6349 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6350 %}
6351
6352 ins_pipe(pipe_serial);
6353 %}
6354
6355 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6356 %{
6357 predicate(needs_acquiring_load_reserved(n));
6358
6359 match(Set newval (GetAndAddI mem incr));
6360
6361 ins_cost(ALU_COST);
6362
6363 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6364
6365 ins_encode %{
6366 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6367 %}
6368
6369 ins_pipe(pipe_serial);
6370 %}
6371
6372 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6373 %{
6374 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6375
6376 match(Set dummy (GetAndAddI mem incr));
6377
6378 ins_cost(ALU_COST);
6379
6380 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6381
6382 ins_encode %{
6383 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6384 %}
6385
6386 ins_pipe(pipe_serial);
6387 %}
6388
6389 // ============================================================================
6390 // Arithmetic Instructions
6391 //
6392
6393 // Integer Addition
6394
6395 // TODO
6396 // these currently employ operations which do not set CR and hence are
6397 // not flagged as killing CR but we would like to isolate the cases
6398 // where we want to set flags from those where we don't. need to work
6399 // out how to do that.
6400 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6401 match(Set dst (AddI src1 src2));
6402
6403 ins_cost(ALU_COST);
6404 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6405
6406 ins_encode %{
6407 Assembler::CompressibleRegion cr(&_masm);
6408 __ addw(as_Register($dst$$reg),
6409 as_Register($src1$$reg),
6410 as_Register($src2$$reg));
6411 %}
6412
6413 ins_pipe(ialu_reg_reg);
6414 %}
6415
6416 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6417 match(Set dst (AddI src1 src2));
6418
6419 ins_cost(ALU_COST);
6420 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6421
6422 ins_encode %{
6423 Assembler::CompressibleRegion cr(&_masm);
6424 int32_t con = (int32_t)$src2$$constant;
6425 __ addiw(as_Register($dst$$reg),
6426 as_Register($src1$$reg),
6427 $src2$$constant);
6428 %}
6429
6430 ins_pipe(ialu_reg_imm);
6431 %}
6432
6433 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6434 match(Set dst (AddI (ConvL2I src1) src2));
6435
6436 ins_cost(ALU_COST);
6437 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6438
6439 ins_encode %{
6440 Assembler::CompressibleRegion cr(&_masm);
6441 __ addiw(as_Register($dst$$reg),
6442 as_Register($src1$$reg),
6443 $src2$$constant);
6444 %}
6445
6446 ins_pipe(ialu_reg_imm);
6447 %}
6448
6449 // Pointer Addition
6450 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6451 match(Set dst (AddP src1 src2));
6452
6453 ins_cost(ALU_COST);
6454 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6455
6456 ins_encode %{
6457 Assembler::CompressibleRegion cr(&_masm);
6458 __ add(as_Register($dst$$reg),
6459 as_Register($src1$$reg),
6460 as_Register($src2$$reg));
6461 %}
6462
6463 ins_pipe(ialu_reg_reg);
6464 %}
6465
6466 // If we shift more than 32 bits, we need not convert I2L.
6467 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6468 match(Set dst (LShiftL (ConvI2L src) scale));
6469 ins_cost(ALU_COST);
6470 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6471
6472 ins_encode %{
6473 Assembler::CompressibleRegion cr(&_masm);
6474 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6475 %}
6476
6477 ins_pipe(ialu_reg_shift);
6478 %}
6479
6480 // Pointer Immediate Addition
6481 // n.b. this needs to be more expensive than using an indirect memory
6482 // operand
6483 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6484 match(Set dst (AddP src1 src2));
6485 ins_cost(ALU_COST);
6486 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6487
6488 ins_encode %{
6489 Assembler::CompressibleRegion cr(&_masm);
6490 // src2 is imm, so actually call the addi
6491 __ add(as_Register($dst$$reg),
6492 as_Register($src1$$reg),
6493 $src2$$constant);
6494 %}
6495
6496 ins_pipe(ialu_reg_imm);
6497 %}
6498
6499 // Long Addition
6500 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6501 match(Set dst (AddL src1 src2));
6502 ins_cost(ALU_COST);
6503 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6504
6505 ins_encode %{
6506 Assembler::CompressibleRegion cr(&_masm);
6507 __ add(as_Register($dst$$reg),
6508 as_Register($src1$$reg),
6509 as_Register($src2$$reg));
6510 %}
6511
6512 ins_pipe(ialu_reg_reg);
6513 %}
6514
6515 // No constant pool entries requiredLong Immediate Addition.
6516 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6517 match(Set dst (AddL src1 src2));
6518 ins_cost(ALU_COST);
6519 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6520
6521 ins_encode %{
6522 Assembler::CompressibleRegion cr(&_masm);
6523 // src2 is imm, so actually call the addi
6524 __ add(as_Register($dst$$reg),
6525 as_Register($src1$$reg),
6526 $src2$$constant);
6527 %}
6528
6529 ins_pipe(ialu_reg_imm);
6530 %}
6531
6532 // Integer Subtraction
6533 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6534 match(Set dst (SubI src1 src2));
6535
6536 ins_cost(ALU_COST);
6537 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6538
6539 ins_encode %{
6540 Assembler::CompressibleRegion cr(&_masm);
6541 __ subw(as_Register($dst$$reg),
6542 as_Register($src1$$reg),
6543 as_Register($src2$$reg));
6544 %}
6545
6546 ins_pipe(ialu_reg_reg);
6547 %}
6548
6549 // Immediate Subtraction
6550 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6551 match(Set dst (SubI src1 src2));
6552
6553 ins_cost(ALU_COST);
6554 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6555
6556 ins_encode %{
6557 Assembler::CompressibleRegion cr(&_masm);
6558 // src2 is imm, so actually call the addiw
6559 __ subw(as_Register($dst$$reg),
6560 as_Register($src1$$reg),
6561 $src2$$constant);
6562 %}
6563
6564 ins_pipe(ialu_reg_imm);
6565 %}
6566
6567 // Long Subtraction
6568 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6569 match(Set dst (SubL src1 src2));
6570 ins_cost(ALU_COST);
6571 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6572
6573 ins_encode %{
6574 Assembler::CompressibleRegion cr(&_masm);
6575 __ sub(as_Register($dst$$reg),
6576 as_Register($src1$$reg),
6577 as_Register($src2$$reg));
6578 %}
6579
6580 ins_pipe(ialu_reg_reg);
6581 %}
6582
6583 // No constant pool entries requiredLong Immediate Subtraction.
6584 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6585 match(Set dst (SubL src1 src2));
6586 ins_cost(ALU_COST);
6587 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6588
6589 ins_encode %{
6590 Assembler::CompressibleRegion cr(&_masm);
6591 // src2 is imm, so actually call the addi
6592 __ sub(as_Register($dst$$reg),
6593 as_Register($src1$$reg),
6594 $src2$$constant);
6595 %}
6596
6597 ins_pipe(ialu_reg_imm);
6598 %}
6599
6600 // Integer Negation (special case for sub)
6601
6602 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6603 match(Set dst (SubI zero src));
6604 ins_cost(ALU_COST);
6605 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6606
6607 ins_encode %{
6608 // actually call the subw
6609 __ negw(as_Register($dst$$reg),
6610 as_Register($src$$reg));
6611 %}
6612
6613 ins_pipe(ialu_reg);
6614 %}
6615
6616 // Long Negation
6617
6618 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6619 match(Set dst (SubL zero src));
6620 ins_cost(ALU_COST);
6621 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6622
6623 ins_encode %{
6624 // actually call the sub
6625 __ neg(as_Register($dst$$reg),
6626 as_Register($src$$reg));
6627 %}
6628
6629 ins_pipe(ialu_reg);
6630 %}
6631
6632 // Integer Multiply
6633
6634 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6635 match(Set dst (MulI src1 src2));
6636 ins_cost(IMUL_COST);
6637 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6638
6639 //this means 2 word multi, and no sign extend to 64 bits
6640 ins_encode %{
6641 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6642 __ mulw(as_Register($dst$$reg),
6643 as_Register($src1$$reg),
6644 as_Register($src2$$reg));
6645 %}
6646
6647 ins_pipe(imul_reg_reg);
6648 %}
6649
6650 // Long Multiply
6651
6652 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6653 match(Set dst (MulL src1 src2));
6654 ins_cost(IMUL_COST);
6655 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6656
6657 ins_encode %{
6658 __ mul(as_Register($dst$$reg),
6659 as_Register($src1$$reg),
6660 as_Register($src2$$reg));
6661 %}
6662
6663 ins_pipe(lmul_reg_reg);
6664 %}
6665
6666 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6667 %{
6668 match(Set dst (MulHiL src1 src2));
6669 ins_cost(IMUL_COST);
6670 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6671
6672 ins_encode %{
6673 __ mulh(as_Register($dst$$reg),
6674 as_Register($src1$$reg),
6675 as_Register($src2$$reg));
6676 %}
6677
6678 ins_pipe(lmul_reg_reg);
6679 %}
6680
6681 // Integer Divide
6682
6683 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6684 match(Set dst (DivI src1 src2));
6685 ins_cost(IDIVSI_COST);
6686 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6687
6688 ins_encode(riscv_enc_divw(dst, src1, src2));
6689 ins_pipe(idiv_reg_reg);
6690 %}
6691
6692 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6693 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6694 ins_cost(ALU_COST);
6695 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6696
6697 ins_encode %{
6698 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6699 %}
6700 ins_pipe(ialu_reg_shift);
6701 %}
6702
6703 // Long Divide
6704
6705 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6706 match(Set dst (DivL src1 src2));
6707 ins_cost(IDIVDI_COST);
6708 format %{ "div $dst, $src1, $src2\t#@divL" %}
6709
6710 ins_encode(riscv_enc_div(dst, src1, src2));
6711 ins_pipe(ldiv_reg_reg);
6712 %}
6713
6714 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6715 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6716 ins_cost(ALU_COST);
6717 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6718
6719 ins_encode %{
6720 Assembler::CompressibleRegion cr(&_masm);
6721 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6722 %}
6723 ins_pipe(ialu_reg_shift);
6724 %}
6725
6726 // Integer Remainder
6727
6728 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6729 match(Set dst (ModI src1 src2));
6730 ins_cost(IDIVSI_COST);
6731 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6732
6733 ins_encode(riscv_enc_modw(dst, src1, src2));
6734 ins_pipe(ialu_reg_reg);
6735 %}
6736
6737 // Long Remainder
6738
6739 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6740 match(Set dst (ModL src1 src2));
6741 ins_cost(IDIVDI_COST);
6742 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6743
6744 ins_encode(riscv_enc_mod(dst, src1, src2));
6745 ins_pipe(ialu_reg_reg);
6746 %}
6747
6748 // Integer Shifts
6749
6750 // Shift Left Register
6751 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6752 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6753 match(Set dst (LShiftI src1 src2));
6754 ins_cost(ALU_COST);
6755 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6756
6757 ins_encode %{
6758 __ sllw(as_Register($dst$$reg),
6759 as_Register($src1$$reg),
6760 as_Register($src2$$reg));
6761 %}
6762
6763 ins_pipe(ialu_reg_reg_vshift);
6764 %}
6765
6766 // Shift Left Immediate
6767 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6768 match(Set dst (LShiftI src1 src2));
6769 ins_cost(ALU_COST);
6770 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6771
6772 ins_encode %{
6773 // the shift amount is encoded in the lower
6774 // 5 bits of the I-immediate field for RV32I
6775 __ slliw(as_Register($dst$$reg),
6776 as_Register($src1$$reg),
6777 (unsigned) $src2$$constant & 0x1f);
6778 %}
6779
6780 ins_pipe(ialu_reg_shift);
6781 %}
6782
6783 // Shift Right Logical Register
6784 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6785 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6786 match(Set dst (URShiftI src1 src2));
6787 ins_cost(ALU_COST);
6788 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6789
6790 ins_encode %{
6791 __ srlw(as_Register($dst$$reg),
6792 as_Register($src1$$reg),
6793 as_Register($src2$$reg));
6794 %}
6795
6796 ins_pipe(ialu_reg_reg_vshift);
6797 %}
6798
6799 // Shift Right Logical Immediate
6800 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6801 match(Set dst (URShiftI src1 src2));
6802 ins_cost(ALU_COST);
6803 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6804
6805 ins_encode %{
6806 // the shift amount is encoded in the lower
6807 // 6 bits of the I-immediate field for RV64I
6808 __ srliw(as_Register($dst$$reg),
6809 as_Register($src1$$reg),
6810 (unsigned) $src2$$constant & 0x1f);
6811 %}
6812
6813 ins_pipe(ialu_reg_shift);
6814 %}
6815
6816 // Shift Right Arithmetic Register
6817 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6818 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6819 match(Set dst (RShiftI src1 src2));
6820 ins_cost(ALU_COST);
6821 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6822
6823 ins_encode %{
6824 // riscv will sign-ext dst high 32 bits
6825 __ sraw(as_Register($dst$$reg),
6826 as_Register($src1$$reg),
6827 as_Register($src2$$reg));
6828 %}
6829
6830 ins_pipe(ialu_reg_reg_vshift);
6831 %}
6832
6833 // Shift Right Arithmetic Immediate
6834 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6835 match(Set dst (RShiftI src1 src2));
6836 ins_cost(ALU_COST);
6837 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6838
6839 ins_encode %{
6840 // riscv will sign-ext dst high 32 bits
6841 __ sraiw(as_Register($dst$$reg),
6842 as_Register($src1$$reg),
6843 (unsigned) $src2$$constant & 0x1f);
6844 %}
6845
6846 ins_pipe(ialu_reg_shift);
6847 %}
6848
6849 // Long Shifts
6850
6851 // Shift Left Register
6852 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6853 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6854 match(Set dst (LShiftL src1 src2));
6855
6856 ins_cost(ALU_COST);
6857 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6858
6859 ins_encode %{
6860 __ sll(as_Register($dst$$reg),
6861 as_Register($src1$$reg),
6862 as_Register($src2$$reg));
6863 %}
6864
6865 ins_pipe(ialu_reg_reg_vshift);
6866 %}
6867
6868 // Shift Left Immediate
6869 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6870 match(Set dst (LShiftL src1 src2));
6871
6872 ins_cost(ALU_COST);
6873 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6874
6875 ins_encode %{
6876 Assembler::CompressibleRegion cr(&_masm);
6877 // the shift amount is encoded in the lower
6878 // 6 bits of the I-immediate field for RV64I
6879 __ slli(as_Register($dst$$reg),
6880 as_Register($src1$$reg),
6881 (unsigned) $src2$$constant & 0x3f);
6882 %}
6883
6884 ins_pipe(ialu_reg_shift);
6885 %}
6886
6887 // Shift Right Logical Register
6888 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6889 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6890 match(Set dst (URShiftL src1 src2));
6891
6892 ins_cost(ALU_COST);
6893 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6894
6895 ins_encode %{
6896 __ srl(as_Register($dst$$reg),
6897 as_Register($src1$$reg),
6898 as_Register($src2$$reg));
6899 %}
6900
6901 ins_pipe(ialu_reg_reg_vshift);
6902 %}
6903
6904 // Shift Right Logical Immediate
6905 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6906 match(Set dst (URShiftL src1 src2));
6907
6908 ins_cost(ALU_COST);
6909 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6910
6911 ins_encode %{
6912 Assembler::CompressibleRegion cr(&_masm);
6913 // the shift amount is encoded in the lower
6914 // 6 bits of the I-immediate field for RV64I
6915 __ srli(as_Register($dst$$reg),
6916 as_Register($src1$$reg),
6917 (unsigned) $src2$$constant & 0x3f);
6918 %}
6919
6920 ins_pipe(ialu_reg_shift);
6921 %}
6922
6923 // A special-case pattern for card table stores.
6924 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
6925 match(Set dst (URShiftL (CastP2X src1) src2));
6926
6927 ins_cost(ALU_COST);
6928 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
6929
6930 ins_encode %{
6931 Assembler::CompressibleRegion cr(&_masm);
6932 // the shift amount is encoded in the lower
6933 // 6 bits of the I-immediate field for RV64I
6934 __ srli(as_Register($dst$$reg),
6935 as_Register($src1$$reg),
6936 (unsigned) $src2$$constant & 0x3f);
6937 %}
6938
6939 ins_pipe(ialu_reg_shift);
6940 %}
6941
6942 // Shift Right Arithmetic Register
6943 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6944 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6945 match(Set dst (RShiftL src1 src2));
6946
6947 ins_cost(ALU_COST);
6948 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
6949
6950 ins_encode %{
6951 __ sra(as_Register($dst$$reg),
6952 as_Register($src1$$reg),
6953 as_Register($src2$$reg));
6954 %}
6955
6956 ins_pipe(ialu_reg_reg_vshift);
6957 %}
6958
6959 // Shift Right Arithmetic Immediate
6960 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6961 match(Set dst (RShiftL src1 src2));
6962
6963 ins_cost(ALU_COST);
6964 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
6965
6966 ins_encode %{
6967 Assembler::CompressibleRegion cr(&_masm);
6968 // the shift amount is encoded in the lower
6969 // 6 bits of the I-immediate field for RV64I
6970 __ srai(as_Register($dst$$reg),
6971 as_Register($src1$$reg),
6972 (unsigned) $src2$$constant & 0x3f);
6973 %}
6974
6975 ins_pipe(ialu_reg_shift);
6976 %}
6977
6978 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
6979 match(Set dst (XorI src1 m1));
6980 ins_cost(ALU_COST);
6981 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
6982
6983 ins_encode %{
6984 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
6985 %}
6986
6987 ins_pipe(ialu_reg);
6988 %}
6989
6990 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
6991 match(Set dst (XorL src1 m1));
6992 ins_cost(ALU_COST);
6993 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
6994
6995 ins_encode %{
6996 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
6997 %}
6998
6999 ins_pipe(ialu_reg);
7000 %}
7001
7002
7003 // ============================================================================
7004 // Floating Point Arithmetic Instructions
7005
7006 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7007 match(Set dst (AddF src1 src2));
7008
7009 ins_cost(FMUL_SINGLE_COST);
7010 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7011
7012 ins_encode %{
7013 __ fadd_s(as_FloatRegister($dst$$reg),
7014 as_FloatRegister($src1$$reg),
7015 as_FloatRegister($src2$$reg));
7016 %}
7017
7018 ins_pipe(fp_dop_reg_reg_s);
7019 %}
7020
7021 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7022 match(Set dst (AddD src1 src2));
7023
7024 ins_cost(FMUL_DOUBLE_COST);
7025 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7026
7027 ins_encode %{
7028 __ fadd_d(as_FloatRegister($dst$$reg),
7029 as_FloatRegister($src1$$reg),
7030 as_FloatRegister($src2$$reg));
7031 %}
7032
7033 ins_pipe(fp_dop_reg_reg_d);
7034 %}
7035
7036 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7037 match(Set dst (SubF src1 src2));
7038
7039 ins_cost(FMUL_SINGLE_COST);
7040 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7041
7042 ins_encode %{
7043 __ fsub_s(as_FloatRegister($dst$$reg),
7044 as_FloatRegister($src1$$reg),
7045 as_FloatRegister($src2$$reg));
7046 %}
7047
7048 ins_pipe(fp_dop_reg_reg_s);
7049 %}
7050
7051 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7052 match(Set dst (SubD src1 src2));
7053
7054 ins_cost(FMUL_DOUBLE_COST);
7055 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7056
7057 ins_encode %{
7058 __ fsub_d(as_FloatRegister($dst$$reg),
7059 as_FloatRegister($src1$$reg),
7060 as_FloatRegister($src2$$reg));
7061 %}
7062
7063 ins_pipe(fp_dop_reg_reg_d);
7064 %}
7065
7066 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7067 match(Set dst (MulF src1 src2));
7068
7069 ins_cost(FMUL_SINGLE_COST);
7070 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7071
7072 ins_encode %{
7073 __ fmul_s(as_FloatRegister($dst$$reg),
7074 as_FloatRegister($src1$$reg),
7075 as_FloatRegister($src2$$reg));
7076 %}
7077
7078 ins_pipe(fp_dop_reg_reg_s);
7079 %}
7080
7081 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7082 match(Set dst (MulD src1 src2));
7083
7084 ins_cost(FMUL_DOUBLE_COST);
7085 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7086
7087 ins_encode %{
7088 __ fmul_d(as_FloatRegister($dst$$reg),
7089 as_FloatRegister($src1$$reg),
7090 as_FloatRegister($src2$$reg));
7091 %}
7092
7093 ins_pipe(fp_dop_reg_reg_d);
7094 %}
7095
7096 // src1 * src2 + src3
7097 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7098 predicate(UseFMA);
7099 match(Set dst (FmaF src3 (Binary src1 src2)));
7100
7101 ins_cost(FMUL_SINGLE_COST);
7102 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7103
7104 ins_encode %{
7105 __ fmadd_s(as_FloatRegister($dst$$reg),
7106 as_FloatRegister($src1$$reg),
7107 as_FloatRegister($src2$$reg),
7108 as_FloatRegister($src3$$reg));
7109 %}
7110
7111 ins_pipe(pipe_class_default);
7112 %}
7113
7114 // src1 * src2 + src3
7115 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7116 predicate(UseFMA);
7117 match(Set dst (FmaD src3 (Binary src1 src2)));
7118
7119 ins_cost(FMUL_DOUBLE_COST);
7120 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7121
7122 ins_encode %{
7123 __ fmadd_d(as_FloatRegister($dst$$reg),
7124 as_FloatRegister($src1$$reg),
7125 as_FloatRegister($src2$$reg),
7126 as_FloatRegister($src3$$reg));
7127 %}
7128
7129 ins_pipe(pipe_class_default);
7130 %}
7131
7132 // src1 * src2 - src3
7133 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7134 predicate(UseFMA);
7135 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7136
7137 ins_cost(FMUL_SINGLE_COST);
7138 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7139
7140 ins_encode %{
7141 __ fmsub_s(as_FloatRegister($dst$$reg),
7142 as_FloatRegister($src1$$reg),
7143 as_FloatRegister($src2$$reg),
7144 as_FloatRegister($src3$$reg));
7145 %}
7146
7147 ins_pipe(pipe_class_default);
7148 %}
7149
7150 // src1 * src2 - src3
7151 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7152 predicate(UseFMA);
7153 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7154
7155 ins_cost(FMUL_DOUBLE_COST);
7156 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7157
7158 ins_encode %{
7159 __ fmsub_d(as_FloatRegister($dst$$reg),
7160 as_FloatRegister($src1$$reg),
7161 as_FloatRegister($src2$$reg),
7162 as_FloatRegister($src3$$reg));
7163 %}
7164
7165 ins_pipe(pipe_class_default);
7166 %}
7167
7168 // -src1 * src2 + src3
7169 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7170 predicate(UseFMA);
7171 match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
7172 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7173
7174 ins_cost(FMUL_SINGLE_COST);
7175 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7176
7177 ins_encode %{
7178 __ fnmsub_s(as_FloatRegister($dst$$reg),
7179 as_FloatRegister($src1$$reg),
7180 as_FloatRegister($src2$$reg),
7181 as_FloatRegister($src3$$reg));
7182 %}
7183
7184 ins_pipe(pipe_class_default);
7185 %}
7186
7187 // -src1 * src2 + src3
7188 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7189 predicate(UseFMA);
7190 match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
7191 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7192
7193 ins_cost(FMUL_DOUBLE_COST);
7194 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7195
7196 ins_encode %{
7197 __ fnmsub_d(as_FloatRegister($dst$$reg),
7198 as_FloatRegister($src1$$reg),
7199 as_FloatRegister($src2$$reg),
7200 as_FloatRegister($src3$$reg));
7201 %}
7202
7203 ins_pipe(pipe_class_default);
7204 %}
7205
7206 // -src1 * src2 - src3
7207 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7208 predicate(UseFMA);
7209 match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
7210 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7211
7212 ins_cost(FMUL_SINGLE_COST);
7213 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7214
7215 ins_encode %{
7216 __ fnmadd_s(as_FloatRegister($dst$$reg),
7217 as_FloatRegister($src1$$reg),
7218 as_FloatRegister($src2$$reg),
7219 as_FloatRegister($src3$$reg));
7220 %}
7221
7222 ins_pipe(pipe_class_default);
7223 %}
7224
7225 // -src1 * src2 - src3
7226 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7227 predicate(UseFMA);
7228 match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
7229 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7230
7231 ins_cost(FMUL_DOUBLE_COST);
7232 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7233
7234 ins_encode %{
7235 __ fnmadd_d(as_FloatRegister($dst$$reg),
7236 as_FloatRegister($src1$$reg),
7237 as_FloatRegister($src2$$reg),
7238 as_FloatRegister($src3$$reg));
7239 %}
7240
7241 ins_pipe(pipe_class_default);
7242 %}
7243
7244 // Math.max(FF)F
7245 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7246 match(Set dst (MaxF src1 src2));
7247 effect(TEMP_DEF dst);
7248
7249 format %{ "maxF $dst, $src1, $src2" %}
7250
7251 ins_encode %{
7252 __ minmax_FD(as_FloatRegister($dst$$reg),
7253 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7254 false /* is_double */, false /* is_min */);
7255 %}
7256
7257 ins_pipe(fp_dop_reg_reg_s);
7258 %}
7259
7260 // Math.min(FF)F
7261 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7262 match(Set dst (MinF src1 src2));
7263 effect(TEMP_DEF dst);
7264
7265 format %{ "minF $dst, $src1, $src2" %}
7266
7267 ins_encode %{
7268 __ minmax_FD(as_FloatRegister($dst$$reg),
7269 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7270 false /* is_double */, true /* is_min */);
7271 %}
7272
7273 ins_pipe(fp_dop_reg_reg_s);
7274 %}
7275
7276 // Math.max(DD)D
7277 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7278 match(Set dst (MaxD src1 src2));
7279 effect(TEMP_DEF dst);
7280
7281 format %{ "maxD $dst, $src1, $src2" %}
7282
7283 ins_encode %{
7284 __ minmax_FD(as_FloatRegister($dst$$reg),
7285 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7286 true /* is_double */, false /* is_min */);
7287 %}
7288
7289 ins_pipe(fp_dop_reg_reg_d);
7290 %}
7291
7292 // Math.min(DD)D
7293 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7294 match(Set dst (MinD src1 src2));
7295 effect(TEMP_DEF dst);
7296
7297 format %{ "minD $dst, $src1, $src2" %}
7298
7299 ins_encode %{
7300 __ minmax_FD(as_FloatRegister($dst$$reg),
7301 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7302 true /* is_double */, true /* is_min */);
7303 %}
7304
7305 ins_pipe(fp_dop_reg_reg_d);
7306 %}
7307
7308 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7309 match(Set dst (DivF src1 src2));
7310
7311 ins_cost(FDIV_COST);
7312 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7313
7314 ins_encode %{
7315 __ fdiv_s(as_FloatRegister($dst$$reg),
7316 as_FloatRegister($src1$$reg),
7317 as_FloatRegister($src2$$reg));
7318 %}
7319
7320 ins_pipe(fp_div_s);
7321 %}
7322
7323 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7324 match(Set dst (DivD src1 src2));
7325
7326 ins_cost(FDIV_COST);
7327 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7328
7329 ins_encode %{
7330 __ fdiv_d(as_FloatRegister($dst$$reg),
7331 as_FloatRegister($src1$$reg),
7332 as_FloatRegister($src2$$reg));
7333 %}
7334
7335 ins_pipe(fp_div_d);
7336 %}
7337
7338 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7339 match(Set dst (NegF src));
7340
7341 ins_cost(XFER_COST);
7342 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7343
7344 ins_encode %{
7345 __ fneg_s(as_FloatRegister($dst$$reg),
7346 as_FloatRegister($src$$reg));
7347 %}
7348
7349 ins_pipe(fp_uop_s);
7350 %}
7351
7352 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7353 match(Set dst (NegD src));
7354
7355 ins_cost(XFER_COST);
7356 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7357
7358 ins_encode %{
7359 __ fneg_d(as_FloatRegister($dst$$reg),
7360 as_FloatRegister($src$$reg));
7361 %}
7362
7363 ins_pipe(fp_uop_d);
7364 %}
7365
7366 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7367 match(Set dst (AbsI src));
7368
7369 ins_cost(ALU_COST * 3);
7370 format %{
7371 "sraiw t0, $src, 0x1f\n\t"
7372 "addw $dst, $src, t0\n\t"
7373 "xorr $dst, $dst, t0\t#@absI_reg"
7374 %}
7375
7376 ins_encode %{
7377 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7378 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7379 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7380 %}
7381
7382 ins_pipe(ialu_reg_reg);
7383 %}
7384
7385 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7386 match(Set dst (AbsL src));
7387
7388 ins_cost(ALU_COST * 3);
7389 format %{
7390 "srai t0, $src, 0x3f\n\t"
7391 "add $dst, $src, t0\n\t"
7392 "xorr $dst, $dst, t0\t#@absL_reg"
7393 %}
7394
7395 ins_encode %{
7396 __ srai(t0, as_Register($src$$reg), 0x3f);
7397 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7398 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7399 %}
7400
7401 ins_pipe(ialu_reg_reg);
7402 %}
7403
7404 instruct absF_reg(fRegF dst, fRegF src) %{
7405 match(Set dst (AbsF src));
7406
7407 ins_cost(XFER_COST);
7408 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7409 ins_encode %{
7410 __ fabs_s(as_FloatRegister($dst$$reg),
7411 as_FloatRegister($src$$reg));
7412 %}
7413
7414 ins_pipe(fp_uop_s);
7415 %}
7416
7417 instruct absD_reg(fRegD dst, fRegD src) %{
7418 match(Set dst (AbsD src));
7419
7420 ins_cost(XFER_COST);
7421 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7422 ins_encode %{
7423 __ fabs_d(as_FloatRegister($dst$$reg),
7424 as_FloatRegister($src$$reg));
7425 %}
7426
7427 ins_pipe(fp_uop_d);
7428 %}
7429
7430 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7431 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7432
7433 ins_cost(FSQRT_COST);
7434 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7435 ins_encode %{
7436 __ fsqrt_s(as_FloatRegister($dst$$reg),
7437 as_FloatRegister($src$$reg));
7438 %}
7439
7440 ins_pipe(fp_sqrt_s);
7441 %}
7442
7443 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7444 match(Set dst (SqrtD src));
7445
7446 ins_cost(FSQRT_COST);
7447 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7448 ins_encode %{
7449 __ fsqrt_d(as_FloatRegister($dst$$reg),
7450 as_FloatRegister($src$$reg));
7451 %}
7452
7453 ins_pipe(fp_sqrt_d);
7454 %}
7455
7456 // Arithmetic Instructions End
7457
7458 // ============================================================================
7459 // Logical Instructions
7460
7461 // Register And
7462 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7463 match(Set dst (AndI src1 src2));
7464
7465 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7466
7467 ins_cost(ALU_COST);
7468 ins_encode %{
7469 Assembler::CompressibleRegion cr(&_masm);
7470 __ andr(as_Register($dst$$reg),
7471 as_Register($src1$$reg),
7472 as_Register($src2$$reg));
7473 %}
7474
7475 ins_pipe(ialu_reg_reg);
7476 %}
7477
7478 // Immediate And
7479 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7480 match(Set dst (AndI src1 src2));
7481
7482 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7483
7484 ins_cost(ALU_COST);
7485 ins_encode %{
7486 Assembler::CompressibleRegion cr(&_masm);
7487 __ andi(as_Register($dst$$reg),
7488 as_Register($src1$$reg),
7489 (int32_t)($src2$$constant));
7490 %}
7491
7492 ins_pipe(ialu_reg_imm);
7493 %}
7494
7495 // Register Or
7496 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7497 match(Set dst (OrI src1 src2));
7498
7499 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7500
7501 ins_cost(ALU_COST);
7502 ins_encode %{
7503 Assembler::CompressibleRegion cr(&_masm);
7504 __ orr(as_Register($dst$$reg),
7505 as_Register($src1$$reg),
7506 as_Register($src2$$reg));
7507 %}
7508
7509 ins_pipe(ialu_reg_reg);
7510 %}
7511
7512 // Immediate Or
7513 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7514 match(Set dst (OrI src1 src2));
7515
7516 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7517
7518 ins_cost(ALU_COST);
7519 ins_encode %{
7520 __ ori(as_Register($dst$$reg),
7521 as_Register($src1$$reg),
7522 (int32_t)($src2$$constant));
7523 %}
7524
7525 ins_pipe(ialu_reg_imm);
7526 %}
7527
7528 // Register Xor
7529 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7530 match(Set dst (XorI src1 src2));
7531
7532 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7533
7534 ins_cost(ALU_COST);
7535 ins_encode %{
7536 Assembler::CompressibleRegion cr(&_masm);
7537 __ xorr(as_Register($dst$$reg),
7538 as_Register($src1$$reg),
7539 as_Register($src2$$reg));
7540 %}
7541
7542 ins_pipe(ialu_reg_reg);
7543 %}
7544
7545 // Immediate Xor
7546 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7547 match(Set dst (XorI src1 src2));
7548
7549 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7550
7551 ins_cost(ALU_COST);
7552 ins_encode %{
7553 __ xori(as_Register($dst$$reg),
7554 as_Register($src1$$reg),
7555 (int32_t)($src2$$constant));
7556 %}
7557
7558 ins_pipe(ialu_reg_imm);
7559 %}
7560
7561 // Register And Long
7562 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7563 match(Set dst (AndL src1 src2));
7564
7565 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7566
7567 ins_cost(ALU_COST);
7568 ins_encode %{
7569 Assembler::CompressibleRegion cr(&_masm);
7570 __ andr(as_Register($dst$$reg),
7571 as_Register($src1$$reg),
7572 as_Register($src2$$reg));
7573 %}
7574
7575 ins_pipe(ialu_reg_reg);
7576 %}
7577
7578 // Immediate And Long
7579 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7580 match(Set dst (AndL src1 src2));
7581
7582 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7583
7584 ins_cost(ALU_COST);
7585 ins_encode %{
7586 Assembler::CompressibleRegion cr(&_masm);
7587 __ andi(as_Register($dst$$reg),
7588 as_Register($src1$$reg),
7589 (int32_t)($src2$$constant));
7590 %}
7591
7592 ins_pipe(ialu_reg_imm);
7593 %}
7594
7595 // Register Or Long
7596 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7597 match(Set dst (OrL src1 src2));
7598
7599 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7600
7601 ins_cost(ALU_COST);
7602 ins_encode %{
7603 Assembler::CompressibleRegion cr(&_masm);
7604 __ orr(as_Register($dst$$reg),
7605 as_Register($src1$$reg),
7606 as_Register($src2$$reg));
7607 %}
7608
7609 ins_pipe(ialu_reg_reg);
7610 %}
7611
7612 // Immediate Or Long
7613 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7614 match(Set dst (OrL src1 src2));
7615
7616 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7617
7618 ins_cost(ALU_COST);
7619 ins_encode %{
7620 __ ori(as_Register($dst$$reg),
7621 as_Register($src1$$reg),
7622 (int32_t)($src2$$constant));
7623 %}
7624
7625 ins_pipe(ialu_reg_imm);
7626 %}
7627
7628 // Register Xor Long
7629 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7630 match(Set dst (XorL src1 src2));
7631
7632 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7633
7634 ins_cost(ALU_COST);
7635 ins_encode %{
7636 Assembler::CompressibleRegion cr(&_masm);
7637 __ xorr(as_Register($dst$$reg),
7638 as_Register($src1$$reg),
7639 as_Register($src2$$reg));
7640 %}
7641
7642 ins_pipe(ialu_reg_reg);
7643 %}
7644
7645 // Immediate Xor Long
7646 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7647 match(Set dst (XorL src1 src2));
7648
7649 ins_cost(ALU_COST);
7650 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7651
7652 ins_encode %{
7653 __ xori(as_Register($dst$$reg),
7654 as_Register($src1$$reg),
7655 (int32_t)($src2$$constant));
7656 %}
7657
7658 ins_pipe(ialu_reg_imm);
7659 %}
7660
7661 // ============================================================================
7662 // BSWAP Instructions
7663
7664 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
7665 match(Set dst (ReverseBytesI src));
7666 effect(TEMP cr);
7667
7668 ins_cost(ALU_COST * 13);
7669 format %{ "revb_w_w $dst, $src\t#@bytes_reverse_int" %}
7670
7671 ins_encode %{
7672 __ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
7673 %}
7674
7675 ins_pipe(ialu_reg);
7676 %}
7677
7678 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
7679 match(Set dst (ReverseBytesL src));
7680 effect(TEMP cr);
7681
7682 ins_cost(ALU_COST * 29);
7683 format %{ "revb $dst, $src\t#@bytes_reverse_long" %}
7684
7685 ins_encode %{
7686 __ revb(as_Register($dst$$reg), as_Register($src$$reg));
7687 %}
7688
7689 ins_pipe(ialu_reg);
7690 %}
7691
7692 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
7693 match(Set dst (ReverseBytesUS src));
7694
7695 ins_cost(ALU_COST * 5);
7696 format %{ "revb_h_h_u $dst, $src\t#@bytes_reverse_unsigned_short" %}
7697
7698 ins_encode %{
7699 __ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
7700 %}
7701
7702 ins_pipe(ialu_reg);
7703 %}
7704
7705 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
7706 match(Set dst (ReverseBytesS src));
7707
7708 ins_cost(ALU_COST * 5);
7709 format %{ "revb_h_h $dst, $src\t#@bytes_reverse_short" %}
7710
7711 ins_encode %{
7712 __ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
7713 %}
7714
7715 ins_pipe(ialu_reg);
7716 %}
7717
7718 // ============================================================================
7719 // MemBar Instruction
7720
7721 instruct load_fence() %{
7722 match(LoadFence);
7723 ins_cost(ALU_COST);
7724
7725 format %{ "#@load_fence" %}
7726
7727 ins_encode %{
7728 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7729 %}
7730 ins_pipe(pipe_serial);
7731 %}
7732
7733 instruct membar_acquire() %{
7734 match(MemBarAcquire);
7735 ins_cost(ALU_COST);
7736
7737 format %{ "#@membar_acquire\n\t"
7738 "fence ir iorw" %}
7739
7740 ins_encode %{
7741 __ block_comment("membar_acquire");
7742 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7743 %}
7744
7745 ins_pipe(pipe_serial);
7746 %}
7747
7748 instruct membar_acquire_lock() %{
7749 match(MemBarAcquireLock);
7750 ins_cost(0);
7751
7752 format %{ "#@membar_acquire_lock (elided)" %}
7753
7754 ins_encode %{
7755 __ block_comment("membar_acquire_lock (elided)");
7756 %}
7757
7758 ins_pipe(pipe_serial);
7759 %}
7760
7761 instruct store_fence() %{
7762 match(StoreFence);
7763 ins_cost(ALU_COST);
7764
7765 format %{ "#@store_fence" %}
7766
7767 ins_encode %{
7768 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7769 %}
7770 ins_pipe(pipe_serial);
7771 %}
7772
7773 instruct membar_release() %{
7774 match(MemBarRelease);
7775 ins_cost(ALU_COST);
7776
7777 format %{ "#@membar_release\n\t"
7778 "fence iorw ow" %}
7779
7780 ins_encode %{
7781 __ block_comment("membar_release");
7782 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7783 %}
7784 ins_pipe(pipe_serial);
7785 %}
7786
7787 instruct membar_storestore() %{
7788 match(MemBarStoreStore);
7789 ins_cost(ALU_COST);
7790
7791 format %{ "MEMBAR-store-store\t#@membar_storestore" %}
7792
7793 ins_encode %{
7794 __ membar(MacroAssembler::StoreStore);
7795 %}
7796 ins_pipe(pipe_serial);
7797 %}
7798
7799 instruct membar_release_lock() %{
7800 match(MemBarReleaseLock);
7801 ins_cost(0);
7802
7803 format %{ "#@membar_release_lock (elided)" %}
7804
7805 ins_encode %{
7806 __ block_comment("membar_release_lock (elided)");
7807 %}
7808
7809 ins_pipe(pipe_serial);
7810 %}
7811
7812 instruct membar_volatile() %{
7813 match(MemBarVolatile);
7814 ins_cost(ALU_COST);
7815
7816 format %{ "#@membar_volatile\n\t"
7817 "fence iorw iorw"%}
7818
7819 ins_encode %{
7820 __ block_comment("membar_volatile");
7821 __ membar(MacroAssembler::StoreLoad);
7822 %}
7823
7824 ins_pipe(pipe_serial);
7825 %}
7826
7827 // ============================================================================
7828 // Cast Instructions (Java-level type cast)
7829
7830 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7831 match(Set dst (CastX2P src));
7832
7833 ins_cost(ALU_COST);
7834 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
7835
7836 ins_encode %{
7837 Assembler::CompressibleRegion cr(&_masm);
7838 if ($dst$$reg != $src$$reg) {
7839 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7840 }
7841 %}
7842
7843 ins_pipe(ialu_reg);
7844 %}
7845
7846 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7847 match(Set dst (CastP2X src));
7848
7849 ins_cost(ALU_COST);
7850 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
7851
7852 ins_encode %{
7853 Assembler::CompressibleRegion cr(&_masm);
7854 if ($dst$$reg != $src$$reg) {
7855 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
7856 }
7857 %}
7858
7859 ins_pipe(ialu_reg);
7860 %}
7861
7862 instruct castPP(iRegPNoSp dst)
7863 %{
7864 match(Set dst (CastPP dst));
7865 ins_cost(0);
7866
7867 size(0);
7868 format %{ "# castPP of $dst, #@castPP" %}
7869 ins_encode(/* empty encoding */);
7870 ins_pipe(pipe_class_empty);
7871 %}
7872
7873 instruct castLL(iRegL dst)
7874 %{
7875 match(Set dst (CastLL dst));
7876
7877 size(0);
7878 format %{ "# castLL of $dst, #@castLL" %}
7879 ins_encode(/* empty encoding */);
7880 ins_cost(0);
7881 ins_pipe(pipe_class_empty);
7882 %}
7883
7884 instruct castII(iRegI dst)
7885 %{
7886 match(Set dst (CastII dst));
7887
7888 size(0);
7889 format %{ "# castII of $dst, #@castII" %}
7890 ins_encode(/* empty encoding */);
7891 ins_cost(0);
7892 ins_pipe(pipe_class_empty);
7893 %}
7894
7895 instruct checkCastPP(iRegPNoSp dst)
7896 %{
7897 match(Set dst (CheckCastPP dst));
7898
7899 size(0);
7900 ins_cost(0);
7901 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
7902 ins_encode(/* empty encoding */);
7903 ins_pipe(pipe_class_empty);
7904 %}
7905
7906 instruct castFF(fRegF dst)
7907 %{
7908 match(Set dst (CastFF dst));
7909
7910 size(0);
7911 format %{ "# castFF of $dst" %}
7912 ins_encode(/* empty encoding */);
7913 ins_cost(0);
7914 ins_pipe(pipe_class_empty);
7915 %}
7916
7917 instruct castDD(fRegD dst)
7918 %{
7919 match(Set dst (CastDD dst));
7920
7921 size(0);
7922 format %{ "# castDD of $dst" %}
7923 ins_encode(/* empty encoding */);
7924 ins_cost(0);
7925 ins_pipe(pipe_class_empty);
7926 %}
7927
7928 instruct castVV(vReg dst)
7929 %{
7930 match(Set dst (CastVV dst));
7931
7932 size(0);
7933 format %{ "# castVV of $dst" %}
7934 ins_encode(/* empty encoding */);
7935 ins_cost(0);
7936 ins_pipe(pipe_class_empty);
7937 %}
7938
7939 // ============================================================================
7940 // Convert Instructions
7941
7942 // int to bool
7943 instruct convI2Bool(iRegINoSp dst, iRegI src)
7944 %{
7945 match(Set dst (Conv2B src));
7946
7947 ins_cost(ALU_COST);
7948 format %{ "snez $dst, $src\t#@convI2Bool" %}
7949
7950 ins_encode %{
7951 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
7952 %}
7953
7954 ins_pipe(ialu_reg);
7955 %}
7956
7957 // pointer to bool
7958 instruct convP2Bool(iRegINoSp dst, iRegP src)
7959 %{
7960 match(Set dst (Conv2B src));
7961
7962 ins_cost(ALU_COST);
7963 format %{ "snez $dst, $src\t#@convP2Bool" %}
7964
7965 ins_encode %{
7966 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
7967 %}
7968
7969 ins_pipe(ialu_reg);
7970 %}
7971
7972 // int <-> long
7973
7974 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
7975 %{
7976 match(Set dst (ConvI2L src));
7977
7978 ins_cost(ALU_COST);
7979 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
7980 ins_encode %{
7981 __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
7982 %}
7983 ins_pipe(ialu_reg);
7984 %}
7985
7986 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
7987 match(Set dst (ConvL2I src));
7988
7989 ins_cost(ALU_COST);
7990 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
7991
7992 ins_encode %{
7993 __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
7994 %}
7995
7996 ins_pipe(ialu_reg);
7997 %}
7998
7999 // int to unsigned long (Zero-extend)
8000 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8001 %{
8002 match(Set dst (AndL (ConvI2L src) mask));
8003
8004 ins_cost(ALU_COST * 2);
8005 format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8006
8007 ins_encode %{
8008 Assembler::CompressibleRegion cr(&_masm);
8009 __ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
8010 %}
8011
8012 ins_pipe(ialu_reg_shift);
8013 %}
8014
8015 // float <-> double
8016
8017 instruct convF2D_reg(fRegD dst, fRegF src) %{
8018 match(Set dst (ConvF2D src));
8019
8020 ins_cost(XFER_COST);
8021 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8022
8023 ins_encode %{
8024 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8025 %}
8026
8027 ins_pipe(fp_f2d);
8028 %}
8029
8030 instruct convD2F_reg(fRegF dst, fRegD src) %{
8031 match(Set dst (ConvD2F src));
8032
8033 ins_cost(XFER_COST);
8034 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8035
8036 ins_encode %{
8037 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8038 %}
8039
8040 ins_pipe(fp_d2f);
8041 %}
8042
8043 // float <-> int
8044
8045 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8046 match(Set dst (ConvF2I src));
8047
8048 ins_cost(XFER_COST);
8049 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8050
8051 ins_encode %{
8052 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8053 %}
8054
8055 ins_pipe(fp_f2i);
8056 %}
8057
8058 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8059 match(Set dst (ConvI2F src));
8060
8061 ins_cost(XFER_COST);
8062 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8063
8064 ins_encode %{
8065 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8066 %}
8067
8068 ins_pipe(fp_i2f);
8069 %}
8070
8071 // float <-> long
8072
8073 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8074 match(Set dst (ConvF2L src));
8075
8076 ins_cost(XFER_COST);
8077 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8078
8079 ins_encode %{
8080 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8081 %}
8082
8083 ins_pipe(fp_f2l);
8084 %}
8085
8086 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8087 match(Set dst (ConvL2F src));
8088
8089 ins_cost(XFER_COST);
8090 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8091
8092 ins_encode %{
8093 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8094 %}
8095
8096 ins_pipe(fp_l2f);
8097 %}
8098
8099 // double <-> int
8100
8101 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8102 match(Set dst (ConvD2I src));
8103
8104 ins_cost(XFER_COST);
8105 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8106
8107 ins_encode %{
8108 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8109 %}
8110
8111 ins_pipe(fp_d2i);
8112 %}
8113
8114 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8115 match(Set dst (ConvI2D src));
8116
8117 ins_cost(XFER_COST);
8118 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8119
8120 ins_encode %{
8121 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8122 %}
8123
8124 ins_pipe(fp_i2d);
8125 %}
8126
8127 // double <-> long
8128
8129 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8130 match(Set dst (ConvD2L src));
8131
8132 ins_cost(XFER_COST);
8133 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8134
8135 ins_encode %{
8136 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8137 %}
8138
8139 ins_pipe(fp_d2l);
8140 %}
8141
8142 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8143 match(Set dst (ConvL2D src));
8144
8145 ins_cost(XFER_COST);
8146 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8147
8148 ins_encode %{
8149 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8150 %}
8151
8152 ins_pipe(fp_l2d);
8153 %}
8154
8155 // Convert oop into int for vectors alignment masking
8156 instruct convP2I(iRegINoSp dst, iRegP src) %{
8157 match(Set dst (ConvL2I (CastP2X src)));
8158
8159 ins_cost(ALU_COST * 2);
8160 format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8161
8162 ins_encode %{
8163 Assembler::CompressibleRegion cr(&_masm);
8164 __ zero_extend($dst$$Register, $src$$Register, 32);
8165 %}
8166
8167 ins_pipe(ialu_reg);
8168 %}
8169
8170 // Convert compressed oop into int for vectors alignment masking
8171 // in case of 32bit oops (heap < 4Gb).
8172 instruct convN2I(iRegINoSp dst, iRegN src)
8173 %{
8174 predicate(CompressedOops::shift() == 0);
8175 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8176
8177 ins_cost(ALU_COST);
8178 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8179
8180 ins_encode %{
8181 Assembler::CompressibleRegion cr(&_masm);
8182 __ mv($dst$$Register, $src$$Register);
8183 %}
8184
8185 ins_pipe(ialu_reg);
8186 %}
8187
8188 // Convert oop pointer into compressed form
8189 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8190 match(Set dst (EncodeP src));
8191 ins_cost(ALU_COST);
8192 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8193 ins_encode %{
8194 Register s = $src$$Register;
8195 Register d = $dst$$Register;
8196 __ encode_heap_oop(d, s);
8197 %}
8198 ins_pipe(ialu_reg);
8199 %}
8200
8201 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8202 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8203 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8204 match(Set dst (DecodeN src));
8205
8206 ins_cost(0);
8207 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8208 ins_encode %{
8209 Register s = $src$$Register;
8210 Register d = $dst$$Register;
8211 __ decode_heap_oop(d, s);
8212 %}
8213 ins_pipe(ialu_reg);
8214 %}
8215
8216 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8217 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8218 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8219 match(Set dst (DecodeN src));
8220
8221 ins_cost(0);
8222 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8223 ins_encode %{
8224 Register s = $src$$Register;
8225 Register d = $dst$$Register;
8226 __ decode_heap_oop_not_null(d, s);
8227 %}
8228 ins_pipe(ialu_reg);
8229 %}
8230
8231 // Convert klass pointer into compressed form.
8232 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8233 match(Set dst (EncodePKlass src));
8234
8235 ins_cost(ALU_COST);
8236 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8237
8238 ins_encode %{
8239 Register src_reg = as_Register($src$$reg);
8240 Register dst_reg = as_Register($dst$$reg);
8241 __ encode_klass_not_null(dst_reg, src_reg, t0);
8242 %}
8243
8244 ins_pipe(ialu_reg);
8245 %}
8246
8247 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8248 match(Set dst (DecodeNKlass src));
8249
8250 effect(TEMP tmp);
8251
8252 ins_cost(ALU_COST);
8253 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8254
8255 ins_encode %{
8256 Register src_reg = as_Register($src$$reg);
8257 Register dst_reg = as_Register($dst$$reg);
8258 Register tmp_reg = as_Register($tmp$$reg);
8259 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8260 %}
8261
8262 ins_pipe(ialu_reg);
8263 %}
8264
8265 // stack <-> reg and reg <-> reg shuffles with no conversion
8266
8267 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8268
8269 match(Set dst (MoveF2I src));
8270
8271 effect(DEF dst, USE src);
8272
8273 ins_cost(LOAD_COST);
8274
8275 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8276
8277 ins_encode %{
8278 Assembler::CompressibleRegion cr(&_masm);
8279 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8280 %}
8281
8282 ins_pipe(iload_reg_reg);
8283
8284 %}
8285
8286 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8287
8288 match(Set dst (MoveI2F src));
8289
8290 effect(DEF dst, USE src);
8291
8292 ins_cost(LOAD_COST);
8293
8294 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8295
8296 ins_encode %{
8297 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8298 %}
8299
8300 ins_pipe(pipe_class_memory);
8301
8302 %}
8303
8304 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8305
8306 match(Set dst (MoveD2L src));
8307
8308 effect(DEF dst, USE src);
8309
8310 ins_cost(LOAD_COST);
8311
8312 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8313
8314 ins_encode %{
8315 Assembler::CompressibleRegion cr(&_masm);
8316 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8317 %}
8318
8319 ins_pipe(iload_reg_reg);
8320
8321 %}
8322
8323 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8324
8325 match(Set dst (MoveL2D src));
8326
8327 effect(DEF dst, USE src);
8328
8329 ins_cost(LOAD_COST);
8330
8331 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8332
8333 ins_encode %{
8334 Assembler::CompressibleRegion cr(&_masm);
8335 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8336 %}
8337
8338 ins_pipe(pipe_class_memory);
8339
8340 %}
8341
8342 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8343
8344 match(Set dst (MoveF2I src));
8345
8346 effect(DEF dst, USE src);
8347
8348 ins_cost(STORE_COST);
8349
8350 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8351
8352 ins_encode %{
8353 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8354 %}
8355
8356 ins_pipe(pipe_class_memory);
8357
8358 %}
8359
8360 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8361
8362 match(Set dst (MoveI2F src));
8363
8364 effect(DEF dst, USE src);
8365
8366 ins_cost(STORE_COST);
8367
8368 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8369
8370 ins_encode %{
8371 Assembler::CompressibleRegion cr(&_masm);
8372 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8373 %}
8374
8375 ins_pipe(istore_reg_reg);
8376
8377 %}
8378
8379 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8380
8381 match(Set dst (MoveD2L src));
8382
8383 effect(DEF dst, USE src);
8384
8385 ins_cost(STORE_COST);
8386
8387 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8388
8389 ins_encode %{
8390 Assembler::CompressibleRegion cr(&_masm);
8391 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8392 %}
8393
8394 ins_pipe(pipe_class_memory);
8395
8396 %}
8397
8398 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8399
8400 match(Set dst (MoveL2D src));
8401
8402 effect(DEF dst, USE src);
8403
8404 ins_cost(STORE_COST);
8405
8406 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8407
8408 ins_encode %{
8409 Assembler::CompressibleRegion cr(&_masm);
8410 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8411 %}
8412
8413 ins_pipe(istore_reg_reg);
8414
8415 %}
8416
8417 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8418
8419 match(Set dst (MoveF2I src));
8420
8421 effect(DEF dst, USE src);
8422
8423 ins_cost(XFER_COST);
8424
8425 format %{ "fmv.x.w $dst, $src\t#@MoveL2D_reg_stack" %}
8426
8427 ins_encode %{
8428 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8429 %}
8430
8431 ins_pipe(fp_f2i);
8432
8433 %}
8434
8435 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8436
8437 match(Set dst (MoveI2F src));
8438
8439 effect(DEF dst, USE src);
8440
8441 ins_cost(XFER_COST);
8442
8443 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8444
8445 ins_encode %{
8446 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8447 %}
8448
8449 ins_pipe(fp_i2f);
8450
8451 %}
8452
8453 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8454
8455 match(Set dst (MoveD2L src));
8456
8457 effect(DEF dst, USE src);
8458
8459 ins_cost(XFER_COST);
8460
8461 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8462
8463 ins_encode %{
8464 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8465 %}
8466
8467 ins_pipe(fp_d2l);
8468
8469 %}
8470
8471 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8472
8473 match(Set dst (MoveL2D src));
8474
8475 effect(DEF dst, USE src);
8476
8477 ins_cost(XFER_COST);
8478
8479 format %{ "fmv.d.x $dst, $src\t#@MoveD2L_reg_reg" %}
8480
8481 ins_encode %{
8482 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8483 %}
8484
8485 ins_pipe(fp_l2d);
8486 %}
8487
8488 // ============================================================================
8489 // Compare Instructions which set the result float comparisons in dest register.
8490
8491 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8492 %{
8493 match(Set dst (CmpF3 op1 op2));
8494
8495 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8496 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8497 "bgtz $dst, done\n\t"
8498 "feq.s $dst, $op1, $op2\n\t"
8499 "addi $dst, $dst, -1\t#@cmpF3_reg_reg"
8500 %}
8501
8502 ins_encode %{
8503 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8504 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8505 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8506 %}
8507
8508 ins_pipe(pipe_class_default);
8509 %}
8510
8511 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8512 %{
8513 match(Set dst (CmpD3 op1 op2));
8514
8515 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8516 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8517 "bgtz $dst, done\n\t"
8518 "feq.d $dst, $op1, $op2\n\t"
8519 "addi $dst, $dst, -1\t#@cmpD3_reg_reg"
8520 %}
8521
8522 ins_encode %{
8523 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8524 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8525 %}
8526
8527 ins_pipe(pipe_class_default);
8528 %}
8529
8530 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8531 %{
8532 match(Set dst (CmpL3 op1 op2));
8533
8534 ins_cost(ALU_COST * 3 + BRANCH_COST);
8535 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8536 "bnez $dst, done\n\t"
8537 "slt $dst, $op1, $op2\n\t"
8538 "neg $dst, $dst\t#@cmpL3_reg_reg"
8539 %}
8540 ins_encode %{
8541 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8542 __ mv(as_Register($dst$$reg), t0);
8543 %}
8544
8545 ins_pipe(pipe_class_default);
8546 %}
8547
8548 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
8549 %{
8550 match(Set dst (CmpLTMask p q));
8551
8552 ins_cost(2 * ALU_COST);
8553
8554 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
8555 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
8556 %}
8557
8558 ins_encode %{
8559 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
8560 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
8561 %}
8562
8563 ins_pipe(ialu_reg_reg);
8564 %}
8565
8566 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
8567 %{
8568 match(Set dst (CmpLTMask op zero));
8569
8570 ins_cost(ALU_COST);
8571
8572 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
8573
8574 ins_encode %{
8575 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
8576 %}
8577
8578 ins_pipe(ialu_reg_shift);
8579 %}
8580
8581
8582 // ============================================================================
8583 // Max and Min
8584
8585 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
8586 %{
8587 match(Set dst (MinI dst src));
8588
8589 ins_cost(BRANCH_COST + ALU_COST);
8590 format %{
8591 "ble $dst, $src, skip\t#@minI_reg_reg\n\t"
8592 "mv $dst, $src\n\t"
8593 "skip:"
8594 %}
8595
8596 ins_encode %{
8597 Label Lskip;
8598 __ ble(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
8599 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8600 __ bind(Lskip);
8601 %}
8602
8603 ins_pipe(pipe_class_compare);
8604 %}
8605
8606 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
8607 %{
8608 match(Set dst (MaxI dst src));
8609
8610 ins_cost(BRANCH_COST + ALU_COST);
8611 format %{
8612 "bge $dst, $src, skip\t#@maxI_reg_reg\n\t"
8613 "mv $dst, $src\n\t"
8614 "skip:"
8615 %}
8616
8617 ins_encode %{
8618 Label Lskip;
8619 __ bge(as_Register($dst$$reg), as_Register($src$$reg), Lskip);
8620 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8621 __ bind(Lskip);
8622 %}
8623
8624 ins_pipe(pipe_class_compare);
8625 %}
8626
8627 // special case for comparing with zero
8628 // n.b. this is selected in preference to the rule above because it
8629 // avoids loading constant 0 into a source register
8630
8631 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
8632 %{
8633 match(Set dst (MinI dst zero));
8634 match(Set dst (MinI zero dst));
8635
8636 ins_cost(BRANCH_COST + ALU_COST);
8637 format %{
8638 "blez $dst, skip\t#@minI_reg_zero\n\t"
8639 "mv $dst, zr\n\t"
8640 "skip:"
8641 %}
8642
8643 ins_encode %{
8644 Label Lskip;
8645 __ blez(as_Register($dst$$reg), Lskip);
8646 __ mv(as_Register($dst$$reg), zr);
8647 __ bind(Lskip);
8648 %}
8649
8650 ins_pipe(pipe_class_compare);
8651 %}
8652
8653 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
8654 %{
8655 match(Set dst (MaxI dst zero));
8656 match(Set dst (MaxI zero dst));
8657
8658 ins_cost(BRANCH_COST + ALU_COST);
8659 format %{
8660 "bgez $dst, skip\t#@maxI_reg_zero\n\t"
8661 "mv $dst, zr\n\t"
8662 "skip:"
8663 %}
8664
8665 ins_encode %{
8666 Label Lskip;
8667 __ bgez(as_Register($dst$$reg), Lskip);
8668 __ mv(as_Register($dst$$reg), zr);
8669 __ bind(Lskip);
8670 %}
8671
8672 ins_pipe(pipe_class_compare);
8673 %}
8674
8675 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8676 %{
8677 match(Set dst (MinI src1 src2));
8678
8679 effect(DEF dst, USE src1, USE src2);
8680
8681 ins_cost(BRANCH_COST + ALU_COST * 2);
8682 format %{
8683 "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
8684 "mv $dst, $src2\n\t"
8685 "j Ldone\n\t"
8686 "bind Lsrc1\n\t"
8687 "mv $dst, $src1\n\t"
8688 "bind\t#@minI_rReg"
8689 %}
8690
8691 ins_encode %{
8692 Label Lsrc1, Ldone;
8693 __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8694 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8695 __ j(Ldone);
8696 __ bind(Lsrc1);
8697 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8698 __ bind(Ldone);
8699 %}
8700
8701 ins_pipe(pipe_class_compare);
8702 %}
8703
8704 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
8705 %{
8706 match(Set dst (MaxI src1 src2));
8707
8708 effect(DEF dst, USE src1, USE src2);
8709
8710 ins_cost(BRANCH_COST + ALU_COST * 2);
8711 format %{
8712 "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
8713 "mv $dst, $src2\n\t"
8714 "j Ldone\n\t"
8715 "bind Lsrc1\n\t"
8716 "mv $dst, $src1\n\t"
8717 "bind\t#@maxI_rReg"
8718 %}
8719
8720 ins_encode %{
8721 Label Lsrc1, Ldone;
8722 __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
8723 __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
8724 __ j(Ldone);
8725 __ bind(Lsrc1);
8726 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
8727 __ bind(Ldone);
8728
8729 %}
8730
8731 ins_pipe(pipe_class_compare);
8732 %}
8733
8734 // ============================================================================
8735 // Branch Instructions
8736 // Direct Branch.
8737 instruct branch(label lbl)
8738 %{
8739 match(Goto);
8740
8741 effect(USE lbl);
8742
8743 ins_cost(BRANCH_COST);
8744 format %{ "j $lbl\t#@branch" %}
8745
8746 ins_encode(riscv_enc_j(lbl));
8747
8748 ins_pipe(pipe_branch);
8749 %}
8750
8751 // ============================================================================
8752 // Compare and Branch Instructions
8753
8754 // Patterns for short (< 12KiB) variants
8755
8756 // Compare flags and branch near instructions.
8757 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
8758 match(If cmp cr);
8759 effect(USE lbl);
8760
8761 ins_cost(BRANCH_COST);
8762 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
8763
8764 ins_encode %{
8765 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
8766 %}
8767 ins_pipe(pipe_cmpz_branch);
8768 ins_short_branch(1);
8769 %}
8770
8771 // Compare signed int and branch near instructions
8772 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8773 %{
8774 // Same match rule as `far_cmpI_branch'.
8775 match(If cmp (CmpI op1 op2));
8776
8777 effect(USE lbl);
8778
8779 ins_cost(BRANCH_COST);
8780
8781 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
8782
8783 ins_encode %{
8784 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8785 %}
8786
8787 ins_pipe(pipe_cmp_branch);
8788 ins_short_branch(1);
8789 %}
8790
8791 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
8792 %{
8793 // Same match rule as `far_cmpI_loop'.
8794 match(CountedLoopEnd cmp (CmpI op1 op2));
8795
8796 effect(USE lbl);
8797
8798 ins_cost(BRANCH_COST);
8799
8800 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
8801
8802 ins_encode %{
8803 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8804 %}
8805
8806 ins_pipe(pipe_cmp_branch);
8807 ins_short_branch(1);
8808 %}
8809
8810 // Compare unsigned int and branch near instructions
8811 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
8812 %{
8813 // Same match rule as `far_cmpU_branch'.
8814 match(If cmp (CmpU op1 op2));
8815
8816 effect(USE lbl);
8817
8818 ins_cost(BRANCH_COST);
8819
8820 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
8821
8822 ins_encode %{
8823 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8824 as_Register($op2$$reg), *($lbl$$label));
8825 %}
8826
8827 ins_pipe(pipe_cmp_branch);
8828 ins_short_branch(1);
8829 %}
8830
8831 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
8832 %{
8833 // Same match rule as `far_cmpU_loop'.
8834 match(CountedLoopEnd cmp (CmpU op1 op2));
8835
8836 effect(USE lbl);
8837
8838 ins_cost(BRANCH_COST);
8839
8840 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_loop" %}
8841
8842 ins_encode %{
8843 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8844 as_Register($op2$$reg), *($lbl$$label));
8845 %}
8846
8847 ins_pipe(pipe_cmp_branch);
8848 ins_short_branch(1);
8849 %}
8850
8851 // Compare signed long and branch near instructions
8852 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
8853 %{
8854 // Same match rule as `far_cmpL_branch'.
8855 match(If cmp (CmpL op1 op2));
8856
8857 effect(USE lbl);
8858
8859 ins_cost(BRANCH_COST);
8860
8861 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
8862
8863 ins_encode %{
8864 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8865 %}
8866
8867 ins_pipe(pipe_cmp_branch);
8868 ins_short_branch(1);
8869 %}
8870
8871 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
8872 %{
8873 // Same match rule as `far_cmpL_loop'.
8874 match(CountedLoopEnd cmp (CmpL op1 op2));
8875
8876 effect(USE lbl);
8877
8878 ins_cost(BRANCH_COST);
8879
8880 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
8881
8882 ins_encode %{
8883 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
8884 %}
8885
8886 ins_pipe(pipe_cmp_branch);
8887 ins_short_branch(1);
8888 %}
8889
8890 // Compare unsigned long and branch near instructions
8891 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
8892 %{
8893 // Same match rule as `far_cmpUL_branch'.
8894 match(If cmp (CmpUL op1 op2));
8895
8896 effect(USE lbl);
8897
8898 ins_cost(BRANCH_COST);
8899 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
8900
8901 ins_encode %{
8902 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8903 as_Register($op2$$reg), *($lbl$$label));
8904 %}
8905
8906 ins_pipe(pipe_cmp_branch);
8907 ins_short_branch(1);
8908 %}
8909
8910 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
8911 %{
8912 // Same match rule as `far_cmpUL_loop'.
8913 match(CountedLoopEnd cmp (CmpUL op1 op2));
8914
8915 effect(USE lbl);
8916
8917 ins_cost(BRANCH_COST);
8918 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_loop" %}
8919
8920 ins_encode %{
8921 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8922 as_Register($op2$$reg), *($lbl$$label));
8923 %}
8924
8925 ins_pipe(pipe_cmp_branch);
8926 ins_short_branch(1);
8927 %}
8928
8929 // Compare pointer and branch near instructions
8930 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
8931 %{
8932 // Same match rule as `far_cmpP_branch'.
8933 match(If cmp (CmpP op1 op2));
8934
8935 effect(USE lbl);
8936
8937 ins_cost(BRANCH_COST);
8938
8939 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
8940
8941 ins_encode %{
8942 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8943 as_Register($op2$$reg), *($lbl$$label));
8944 %}
8945
8946 ins_pipe(pipe_cmp_branch);
8947 ins_short_branch(1);
8948 %}
8949
8950 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
8951 %{
8952 // Same match rule as `far_cmpP_loop'.
8953 match(CountedLoopEnd cmp (CmpP op1 op2));
8954
8955 effect(USE lbl);
8956
8957 ins_cost(BRANCH_COST);
8958
8959 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_loop" %}
8960
8961 ins_encode %{
8962 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8963 as_Register($op2$$reg), *($lbl$$label));
8964 %}
8965
8966 ins_pipe(pipe_cmp_branch);
8967 ins_short_branch(1);
8968 %}
8969
8970 // Compare narrow pointer and branch near instructions
8971 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
8972 %{
8973 // Same match rule as `far_cmpN_branch'.
8974 match(If cmp (CmpN op1 op2));
8975
8976 effect(USE lbl);
8977
8978 ins_cost(BRANCH_COST);
8979
8980 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
8981
8982 ins_encode %{
8983 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
8984 as_Register($op2$$reg), *($lbl$$label));
8985 %}
8986
8987 ins_pipe(pipe_cmp_branch);
8988 ins_short_branch(1);
8989 %}
8990
8991 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
8992 %{
8993 // Same match rule as `far_cmpN_loop'.
8994 match(CountedLoopEnd cmp (CmpN op1 op2));
8995
8996 effect(USE lbl);
8997
8998 ins_cost(BRANCH_COST);
8999
9000 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_loop" %}
9001
9002 ins_encode %{
9003 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9004 as_Register($op2$$reg), *($lbl$$label));
9005 %}
9006
9007 ins_pipe(pipe_cmp_branch);
9008 ins_short_branch(1);
9009 %}
9010
9011 // Compare float and branch near instructions
9012 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9013 %{
9014 // Same match rule as `far_cmpF_branch'.
9015 match(If cmp (CmpF op1 op2));
9016
9017 effect(USE lbl);
9018
9019 ins_cost(XFER_COST + BRANCH_COST);
9020 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9021
9022 ins_encode %{
9023 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9024 %}
9025
9026 ins_pipe(pipe_class_compare);
9027 ins_short_branch(1);
9028 %}
9029
9030 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9031 %{
9032 // Same match rule as `far_cmpF_loop'.
9033 match(CountedLoopEnd cmp (CmpF op1 op2));
9034 effect(USE lbl);
9035
9036 ins_cost(XFER_COST + BRANCH_COST);
9037 format %{ "float_b$cmp $op1, $op2, $lbl\t#@cmpF_loop"%}
9038
9039 ins_encode %{
9040 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9041 %}
9042
9043 ins_pipe(pipe_class_compare);
9044 ins_short_branch(1);
9045 %}
9046
9047 // Compare double and branch near instructions
9048 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9049 %{
9050 // Same match rule as `far_cmpD_branch'.
9051 match(If cmp (CmpD op1 op2));
9052 effect(USE lbl);
9053
9054 ins_cost(XFER_COST + BRANCH_COST);
9055 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9056
9057 ins_encode %{
9058 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9059 as_FloatRegister($op2$$reg), *($lbl$$label));
9060 %}
9061
9062 ins_pipe(pipe_class_compare);
9063 ins_short_branch(1);
9064 %}
9065
9066 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9067 %{
9068 // Same match rule as `far_cmpD_loop'.
9069 match(CountedLoopEnd cmp (CmpD op1 op2));
9070 effect(USE lbl);
9071
9072 ins_cost(XFER_COST + BRANCH_COST);
9073 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_loop"%}
9074
9075 ins_encode %{
9076 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9077 as_FloatRegister($op2$$reg), *($lbl$$label));
9078 %}
9079
9080 ins_pipe(pipe_class_compare);
9081 ins_short_branch(1);
9082 %}
9083
9084 // Compare signed int with zero and branch near instructions
9085 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9086 %{
9087 // Same match rule as `far_cmpI_reg_imm0_branch'.
9088 match(If cmp (CmpI op1 zero));
9089
9090 effect(USE op1, USE lbl);
9091
9092 ins_cost(BRANCH_COST);
9093 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9094
9095 ins_encode %{
9096 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9097 %}
9098
9099 ins_pipe(pipe_cmpz_branch);
9100 ins_short_branch(1);
9101 %}
9102
9103 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9104 %{
9105 // Same match rule as `far_cmpI_reg_imm0_loop'.
9106 match(CountedLoopEnd cmp (CmpI op1 zero));
9107
9108 effect(USE op1, USE lbl);
9109
9110 ins_cost(BRANCH_COST);
9111
9112 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9113
9114 ins_encode %{
9115 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9116 %}
9117
9118 ins_pipe(pipe_cmpz_branch);
9119 ins_short_branch(1);
9120 %}
9121
9122 // Compare unsigned int with zero and branch near instructions
9123 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9124 %{
9125 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9126 match(If cmp (CmpU op1 zero));
9127
9128 effect(USE op1, USE lbl);
9129
9130 ins_cost(BRANCH_COST);
9131
9132 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9133
9134 ins_encode %{
9135 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9136 %}
9137
9138 ins_pipe(pipe_cmpz_branch);
9139 ins_short_branch(1);
9140 %}
9141
9142 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9143 %{
9144 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
9145 match(CountedLoopEnd cmp (CmpU op1 zero));
9146
9147 effect(USE op1, USE lbl);
9148
9149 ins_cost(BRANCH_COST);
9150
9151 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
9152
9153
9154 ins_encode %{
9155 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9156 %}
9157
9158 ins_pipe(pipe_cmpz_branch);
9159 ins_short_branch(1);
9160 %}
9161
9162 // Compare signed long with zero and branch near instructions
9163 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9164 %{
9165 // Same match rule as `far_cmpL_reg_imm0_branch'.
9166 match(If cmp (CmpL op1 zero));
9167
9168 effect(USE op1, USE lbl);
9169
9170 ins_cost(BRANCH_COST);
9171
9172 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9173
9174 ins_encode %{
9175 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9176 %}
9177
9178 ins_pipe(pipe_cmpz_branch);
9179 ins_short_branch(1);
9180 %}
9181
9182 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9183 %{
9184 // Same match rule as `far_cmpL_reg_imm0_loop'.
9185 match(CountedLoopEnd cmp (CmpL op1 zero));
9186
9187 effect(USE op1, USE lbl);
9188
9189 ins_cost(BRANCH_COST);
9190
9191 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9192
9193 ins_encode %{
9194 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9195 %}
9196
9197 ins_pipe(pipe_cmpz_branch);
9198 ins_short_branch(1);
9199 %}
9200
9201 // Compare unsigned long with zero and branch near instructions
9202 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9203 %{
9204 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9205 match(If cmp (CmpUL op1 zero));
9206
9207 effect(USE op1, USE lbl);
9208
9209 ins_cost(BRANCH_COST);
9210
9211 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9212
9213 ins_encode %{
9214 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9215 %}
9216
9217 ins_pipe(pipe_cmpz_branch);
9218 ins_short_branch(1);
9219 %}
9220
9221 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9222 %{
9223 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
9224 match(CountedLoopEnd cmp (CmpUL op1 zero));
9225
9226 effect(USE op1, USE lbl);
9227
9228 ins_cost(BRANCH_COST);
9229
9230 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
9231
9232 ins_encode %{
9233 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9234 %}
9235
9236 ins_pipe(pipe_cmpz_branch);
9237 ins_short_branch(1);
9238 %}
9239
9240 // Compare pointer with zero and branch near instructions
9241 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9242 // Same match rule as `far_cmpP_reg_imm0_branch'.
9243 match(If cmp (CmpP op1 zero));
9244 effect(USE lbl);
9245
9246 ins_cost(BRANCH_COST);
9247 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9248
9249 ins_encode %{
9250 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9251 %}
9252
9253 ins_pipe(pipe_cmpz_branch);
9254 ins_short_branch(1);
9255 %}
9256
9257 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9258 // Same match rule as `far_cmpP_reg_imm0_loop'.
9259 match(CountedLoopEnd cmp (CmpP op1 zero));
9260 effect(USE lbl);
9261
9262 ins_cost(BRANCH_COST);
9263 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
9264
9265 ins_encode %{
9266 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9267 %}
9268
9269 ins_pipe(pipe_cmpz_branch);
9270 ins_short_branch(1);
9271 %}
9272
9273 // Compare narrow pointer with zero and branch near instructions
9274 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9275 // Same match rule as `far_cmpN_reg_imm0_branch'.
9276 match(If cmp (CmpN op1 zero));
9277 effect(USE lbl);
9278
9279 ins_cost(BRANCH_COST);
9280
9281 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9282
9283 ins_encode %{
9284 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9285 %}
9286
9287 ins_pipe(pipe_cmpz_branch);
9288 ins_short_branch(1);
9289 %}
9290
9291 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9292 // Same match rule as `far_cmpN_reg_imm0_loop'.
9293 match(CountedLoopEnd cmp (CmpN op1 zero));
9294 effect(USE lbl);
9295
9296 ins_cost(BRANCH_COST);
9297
9298 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
9299
9300 ins_encode %{
9301 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9302 %}
9303
9304 ins_pipe(pipe_cmpz_branch);
9305 ins_short_branch(1);
9306 %}
9307
9308 // Compare narrow pointer with pointer zero and branch near instructions
9309 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9310 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9311 match(If cmp (CmpP (DecodeN op1) zero));
9312 effect(USE lbl);
9313
9314 ins_cost(BRANCH_COST);
9315 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9316
9317 ins_encode %{
9318 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9319 %}
9320
9321 ins_pipe(pipe_cmpz_branch);
9322 ins_short_branch(1);
9323 %}
9324
9325 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9326 // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
9327 match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
9328 effect(USE lbl);
9329
9330 ins_cost(BRANCH_COST);
9331 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
9332
9333 ins_encode %{
9334 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9335 %}
9336
9337 ins_pipe(pipe_cmpz_branch);
9338 ins_short_branch(1);
9339 %}
9340
9341 // Patterns for far (20KiB) variants
9342
9343 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9344 match(If cmp cr);
9345 effect(USE lbl);
9346
9347 ins_cost(BRANCH_COST);
9348 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9349
9350 ins_encode %{
9351 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9352 %}
9353
9354 ins_pipe(pipe_cmpz_branch);
9355 %}
9356
9357 // Compare signed int and branch far instructions
9358 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9359 match(If cmp (CmpI op1 op2));
9360 effect(USE lbl);
9361
9362 ins_cost(BRANCH_COST * 2);
9363
9364 // the format instruction [far_b$cmp] here is be used as two insructions
9365 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9366 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9367
9368 ins_encode %{
9369 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9370 %}
9371
9372 ins_pipe(pipe_cmp_branch);
9373 %}
9374
9375 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9376 match(CountedLoopEnd cmp (CmpI op1 op2));
9377 effect(USE lbl);
9378
9379 ins_cost(BRANCH_COST * 2);
9380 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9381
9382 ins_encode %{
9383 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9384 %}
9385
9386 ins_pipe(pipe_cmp_branch);
9387 %}
9388
9389 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9390 match(If cmp (CmpU op1 op2));
9391 effect(USE lbl);
9392
9393 ins_cost(BRANCH_COST * 2);
9394 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9395
9396 ins_encode %{
9397 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9398 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9399 %}
9400
9401 ins_pipe(pipe_cmp_branch);
9402 %}
9403
9404 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9405 match(CountedLoopEnd cmp (CmpU op1 op2));
9406 effect(USE lbl);
9407
9408 ins_cost(BRANCH_COST * 2);
9409 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
9410
9411 ins_encode %{
9412 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9413 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9414 %}
9415
9416 ins_pipe(pipe_cmp_branch);
9417 %}
9418
9419 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9420 match(If cmp (CmpL op1 op2));
9421 effect(USE lbl);
9422
9423 ins_cost(BRANCH_COST * 2);
9424 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9425
9426 ins_encode %{
9427 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9428 %}
9429
9430 ins_pipe(pipe_cmp_branch);
9431 %}
9432
9433 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9434 match(CountedLoopEnd cmp (CmpL op1 op2));
9435 effect(USE lbl);
9436
9437 ins_cost(BRANCH_COST * 2);
9438 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9439
9440 ins_encode %{
9441 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9442 %}
9443
9444 ins_pipe(pipe_cmp_branch);
9445 %}
9446
9447 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9448 match(If cmp (CmpUL op1 op2));
9449 effect(USE lbl);
9450
9451 ins_cost(BRANCH_COST * 2);
9452 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9453
9454 ins_encode %{
9455 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9456 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9457 %}
9458
9459 ins_pipe(pipe_cmp_branch);
9460 %}
9461
9462 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9463 match(CountedLoopEnd cmp (CmpUL op1 op2));
9464 effect(USE lbl);
9465
9466 ins_cost(BRANCH_COST * 2);
9467 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
9468
9469 ins_encode %{
9470 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9471 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9472 %}
9473
9474 ins_pipe(pipe_cmp_branch);
9475 %}
9476
9477 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9478 %{
9479 match(If cmp (CmpP op1 op2));
9480
9481 effect(USE lbl);
9482
9483 ins_cost(BRANCH_COST * 2);
9484
9485 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9486
9487 ins_encode %{
9488 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9489 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9490 %}
9491
9492 ins_pipe(pipe_cmp_branch);
9493 %}
9494
9495 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9496 %{
9497 match(CountedLoopEnd cmp (CmpP op1 op2));
9498
9499 effect(USE lbl);
9500
9501 ins_cost(BRANCH_COST * 2);
9502
9503 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_loop" %}
9504
9505 ins_encode %{
9506 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9507 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9508 %}
9509
9510 ins_pipe(pipe_cmp_branch);
9511 %}
9512
9513 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9514 %{
9515 match(If cmp (CmpN op1 op2));
9516
9517 effect(USE lbl);
9518
9519 ins_cost(BRANCH_COST * 2);
9520
9521 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9522
9523 ins_encode %{
9524 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9525 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9526 %}
9527
9528 ins_pipe(pipe_cmp_branch);
9529 %}
9530
9531 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9532 %{
9533 match(CountedLoopEnd cmp (CmpN op1 op2));
9534
9535 effect(USE lbl);
9536
9537 ins_cost(BRANCH_COST * 2);
9538
9539 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_loop" %}
9540
9541 ins_encode %{
9542 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9543 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9544 %}
9545
9546 ins_pipe(pipe_cmp_branch);
9547 %}
9548
9549 // Float compare and branch instructions
9550 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9551 %{
9552 match(If cmp (CmpF op1 op2));
9553
9554 effect(USE lbl);
9555
9556 ins_cost(XFER_COST + BRANCH_COST * 2);
9557 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9558
9559 ins_encode %{
9560 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9561 *($lbl$$label), /* is_far */ true);
9562 %}
9563
9564 ins_pipe(pipe_class_compare);
9565 %}
9566
9567 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9568 %{
9569 match(CountedLoopEnd cmp (CmpF op1 op2));
9570 effect(USE lbl);
9571
9572 ins_cost(XFER_COST + BRANCH_COST * 2);
9573 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_loop"%}
9574
9575 ins_encode %{
9576 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9577 *($lbl$$label), /* is_far */ true);
9578 %}
9579
9580 ins_pipe(pipe_class_compare);
9581 %}
9582
9583 // Double compare and branch instructions
9584 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9585 %{
9586 match(If cmp (CmpD op1 op2));
9587 effect(USE lbl);
9588
9589 ins_cost(XFER_COST + BRANCH_COST * 2);
9590 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9591
9592 ins_encode %{
9593 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9594 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9595 %}
9596
9597 ins_pipe(pipe_class_compare);
9598 %}
9599
9600 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9601 %{
9602 match(CountedLoopEnd cmp (CmpD op1 op2));
9603 effect(USE lbl);
9604
9605 ins_cost(XFER_COST + BRANCH_COST * 2);
9606 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_loop"%}
9607
9608 ins_encode %{
9609 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9610 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9611 %}
9612
9613 ins_pipe(pipe_class_compare);
9614 %}
9615
9616 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9617 %{
9618 match(If cmp (CmpI op1 zero));
9619
9620 effect(USE op1, USE lbl);
9621
9622 ins_cost(BRANCH_COST * 2);
9623
9624 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9625
9626 ins_encode %{
9627 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9628 %}
9629
9630 ins_pipe(pipe_cmpz_branch);
9631 %}
9632
9633 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9634 %{
9635 match(CountedLoopEnd cmp (CmpI op1 zero));
9636
9637 effect(USE op1, USE lbl);
9638
9639 ins_cost(BRANCH_COST * 2);
9640
9641 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9642
9643 ins_encode %{
9644 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9645 %}
9646
9647 ins_pipe(pipe_cmpz_branch);
9648 %}
9649
9650 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9651 %{
9652 match(If cmp (CmpU op1 zero));
9653
9654 effect(USE op1, USE lbl);
9655
9656 ins_cost(BRANCH_COST * 2);
9657
9658 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9659
9660 ins_encode %{
9661 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9662 %}
9663
9664 ins_pipe(pipe_cmpz_branch);
9665 %}
9666
9667 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9668 %{
9669 match(CountedLoopEnd cmp (CmpU op1 zero));
9670
9671 effect(USE op1, USE lbl);
9672
9673 ins_cost(BRANCH_COST * 2);
9674
9675 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
9676
9677
9678 ins_encode %{
9679 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9680 %}
9681
9682 ins_pipe(pipe_cmpz_branch);
9683 %}
9684
9685 // compare lt/ge unsigned instructs has no short instruct with same match
9686 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9687 %{
9688 match(If cmp (CmpU op1 zero));
9689
9690 effect(USE op1, USE lbl);
9691
9692 ins_cost(BRANCH_COST);
9693
9694 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9695
9696 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9697
9698 ins_pipe(pipe_cmpz_branch);
9699 %}
9700
9701 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9702 %{
9703 match(CountedLoopEnd cmp (CmpU op1 zero));
9704
9705 effect(USE op1, USE lbl);
9706
9707 ins_cost(BRANCH_COST);
9708
9709 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
9710
9711 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9712
9713 ins_pipe(pipe_cmpz_branch);
9714 %}
9715
9716 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9717 %{
9718 match(If cmp (CmpL op1 zero));
9719
9720 effect(USE op1, USE lbl);
9721
9722 ins_cost(BRANCH_COST * 2);
9723
9724 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9725
9726 ins_encode %{
9727 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9728 %}
9729
9730 ins_pipe(pipe_cmpz_branch);
9731 %}
9732
9733 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9734 %{
9735 match(CountedLoopEnd cmp (CmpL op1 zero));
9736
9737 effect(USE op1, USE lbl);
9738
9739 ins_cost(BRANCH_COST * 2);
9740
9741 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9742
9743 ins_encode %{
9744 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9745 %}
9746
9747 ins_pipe(pipe_cmpz_branch);
9748 %}
9749
9750 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9751 %{
9752 match(If cmp (CmpUL op1 zero));
9753
9754 effect(USE op1, USE lbl);
9755
9756 ins_cost(BRANCH_COST * 2);
9757
9758 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9759
9760 ins_encode %{
9761 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9762 %}
9763
9764 ins_pipe(pipe_cmpz_branch);
9765 %}
9766
9767 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9768 %{
9769 match(CountedLoopEnd cmp (CmpUL op1 zero));
9770
9771 effect(USE op1, USE lbl);
9772
9773 ins_cost(BRANCH_COST * 2);
9774
9775 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
9776
9777 ins_encode %{
9778 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9779 %}
9780
9781 ins_pipe(pipe_cmpz_branch);
9782 %}
9783
9784 // compare lt/ge unsigned instructs has no short instruct with same match
9785 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9786 %{
9787 match(If cmp (CmpUL op1 zero));
9788
9789 effect(USE op1, USE lbl);
9790
9791 ins_cost(BRANCH_COST);
9792
9793 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9794
9795 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9796
9797 ins_pipe(pipe_cmpz_branch);
9798 %}
9799
9800 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9801 %{
9802 match(CountedLoopEnd cmp (CmpUL op1 zero));
9803
9804 effect(USE op1, USE lbl);
9805
9806 ins_cost(BRANCH_COST);
9807
9808 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
9809
9810 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9811
9812 ins_pipe(pipe_cmpz_branch);
9813 %}
9814
9815 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9816 match(If cmp (CmpP op1 zero));
9817 effect(USE lbl);
9818
9819 ins_cost(BRANCH_COST * 2);
9820 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9821
9822 ins_encode %{
9823 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9824 %}
9825
9826 ins_pipe(pipe_cmpz_branch);
9827 %}
9828
9829 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9830 match(CountedLoopEnd cmp (CmpP op1 zero));
9831 effect(USE lbl);
9832
9833 ins_cost(BRANCH_COST * 2);
9834 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
9835
9836 ins_encode %{
9837 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9838 %}
9839
9840 ins_pipe(pipe_cmpz_branch);
9841 %}
9842
9843 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9844 match(If cmp (CmpN op1 zero));
9845 effect(USE lbl);
9846
9847 ins_cost(BRANCH_COST * 2);
9848
9849 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9850
9851 ins_encode %{
9852 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9853 %}
9854
9855 ins_pipe(pipe_cmpz_branch);
9856 %}
9857
9858 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9859 match(CountedLoopEnd cmp (CmpN op1 zero));
9860 effect(USE lbl);
9861
9862 ins_cost(BRANCH_COST * 2);
9863
9864 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
9865
9866 ins_encode %{
9867 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9868 %}
9869
9870 ins_pipe(pipe_cmpz_branch);
9871 %}
9872
9873 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9874 match(If cmp (CmpP (DecodeN op1) zero));
9875 effect(USE lbl);
9876
9877 ins_cost(BRANCH_COST * 2);
9878 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9879
9880 ins_encode %{
9881 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9882 %}
9883
9884 ins_pipe(pipe_cmpz_branch);
9885 %}
9886
9887 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9888 match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
9889 effect(USE lbl);
9890
9891 ins_cost(BRANCH_COST * 2);
9892 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
9893
9894 ins_encode %{
9895 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9896 %}
9897
9898 ins_pipe(pipe_cmpz_branch);
9899 %}
9900
9901 // ============================================================================
9902 // Conditional Move Instructions
9903 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9904 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9905 ins_cost(ALU_COST + BRANCH_COST);
9906
9907 format %{
9908 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
9909 %}
9910
9911 ins_encode %{
9912 __ enc_cmove($cop$$cmpcode,
9913 as_Register($op1$$reg), as_Register($op2$$reg),
9914 as_Register($dst$$reg), as_Register($src$$reg));
9915 %}
9916
9917 ins_pipe(pipe_class_compare);
9918 %}
9919
9920 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9921 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9922 ins_cost(ALU_COST + BRANCH_COST);
9923
9924 format %{
9925 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
9926 %}
9927
9928 ins_encode %{
9929 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9930 as_Register($op1$$reg), as_Register($op2$$reg),
9931 as_Register($dst$$reg), as_Register($src$$reg));
9932 %}
9933
9934 ins_pipe(pipe_class_compare);
9935 %}
9936
9937 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9938 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9939 ins_cost(ALU_COST + BRANCH_COST);
9940
9941 format %{
9942 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
9943 %}
9944
9945 ins_encode %{
9946 __ enc_cmove($cop$$cmpcode,
9947 as_Register($op1$$reg), as_Register($op2$$reg),
9948 as_Register($dst$$reg), as_Register($src$$reg));
9949 %}
9950
9951 ins_pipe(pipe_class_compare);
9952 %}
9953
9954 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
9955 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9956 ins_cost(ALU_COST + BRANCH_COST);
9957
9958 format %{
9959 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
9960 %}
9961
9962 ins_encode %{
9963 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9964 as_Register($op1$$reg), as_Register($op2$$reg),
9965 as_Register($dst$$reg), as_Register($src$$reg));
9966 %}
9967
9968 ins_pipe(pipe_class_compare);
9969 %}
9970
9971 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
9972 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
9973 ins_cost(ALU_COST + BRANCH_COST);
9974
9975 format %{
9976 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
9977 %}
9978
9979 ins_encode %{
9980 __ enc_cmove($cop$$cmpcode,
9981 as_Register($op1$$reg), as_Register($op2$$reg),
9982 as_Register($dst$$reg), as_Register($src$$reg));
9983 %}
9984
9985 ins_pipe(pipe_class_compare);
9986 %}
9987
9988 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
9989 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9990 ins_cost(ALU_COST + BRANCH_COST);
9991
9992 format %{
9993 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
9994 %}
9995
9996 ins_encode %{
9997 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9998 as_Register($op1$$reg), as_Register($op2$$reg),
9999 as_Register($dst$$reg), as_Register($src$$reg));
10000 %}
10001
10002 ins_pipe(pipe_class_compare);
10003 %}
10004
10005 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10006 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10007 ins_cost(ALU_COST + BRANCH_COST);
10008
10009 format %{
10010 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10011 %}
10012
10013 ins_encode %{
10014 __ enc_cmove($cop$$cmpcode,
10015 as_Register($op1$$reg), as_Register($op2$$reg),
10016 as_Register($dst$$reg), as_Register($src$$reg));
10017 %}
10018
10019 ins_pipe(pipe_class_compare);
10020 %}
10021
10022 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10023 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10024 ins_cost(ALU_COST + BRANCH_COST);
10025
10026 format %{
10027 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10028 %}
10029
10030 ins_encode %{
10031 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10032 as_Register($op1$$reg), as_Register($op2$$reg),
10033 as_Register($dst$$reg), as_Register($src$$reg));
10034 %}
10035
10036 ins_pipe(pipe_class_compare);
10037 %}
10038
10039 // ============================================================================
10040 // Procedure Call/Return Instructions
10041
10042 // Call Java Static Instruction
10043 // Note: If this code changes, the corresponding ret_addr_offset() and
10044 // compute_padding() functions will have to be adjusted.
10045 instruct CallStaticJavaDirect(method meth)
10046 %{
10047 match(CallStaticJava);
10048
10049 effect(USE meth);
10050
10051 ins_cost(BRANCH_COST);
10052
10053 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10054
10055 ins_encode(riscv_enc_java_static_call(meth),
10056 riscv_enc_call_epilog);
10057
10058 ins_pipe(pipe_class_call);
10059 ins_alignment(4);
10060 %}
10061
10062 // TO HERE
10063
10064 // Call Java Dynamic Instruction
10065 // Note: If this code changes, the corresponding ret_addr_offset() and
10066 // compute_padding() functions will have to be adjusted.
10067 instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
10068 %{
10069 match(CallDynamicJava);
10070
10071 effect(USE meth, KILL cr);
10072
10073 ins_cost(BRANCH_COST + ALU_COST * 6);
10074
10075 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10076
10077 ins_encode(riscv_enc_java_dynamic_call(meth),
10078 riscv_enc_call_epilog);
10079
10080 ins_pipe(pipe_class_call);
10081 ins_alignment(4);
10082 %}
10083
10084 // Call Runtime Instruction
10085
10086 instruct CallRuntimeDirect(method meth, rFlagsReg cr)
10087 %{
10088 match(CallRuntime);
10089
10090 effect(USE meth, KILL cr);
10091
10092 ins_cost(BRANCH_COST);
10093
10094 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10095
10096 ins_encode(riscv_enc_java_to_runtime(meth));
10097
10098 ins_pipe(pipe_class_call);
10099 %}
10100
10101 // Call Runtime Instruction
10102
10103 instruct CallLeafDirect(method meth, rFlagsReg cr)
10104 %{
10105 match(CallLeaf);
10106
10107 effect(USE meth, KILL cr);
10108
10109 ins_cost(BRANCH_COST);
10110
10111 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10112
10113 ins_encode(riscv_enc_java_to_runtime(meth));
10114
10115 ins_pipe(pipe_class_call);
10116 %}
10117
10118 // Call Runtime Instruction
10119
10120 instruct CallLeafNoFPDirect(method meth, rFlagsReg cr)
10121 %{
10122 match(CallLeafNoFP);
10123
10124 effect(USE meth, KILL cr);
10125
10126 ins_cost(BRANCH_COST);
10127
10128 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10129
10130 ins_encode(riscv_enc_java_to_runtime(meth));
10131
10132 ins_pipe(pipe_class_call);
10133 %}
10134
10135 // ============================================================================
10136 // Partial Subtype Check
10137 //
10138 // superklass array for an instance of the superklass. Set a hidden
10139 // internal cache on a hit (cache is checked with exposed code in
10140 // gen_subtype_check()). Return zero for a hit. The encoding
10141 // ALSO sets flags.
10142
10143 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10144 %{
10145 match(Set result (PartialSubtypeCheck sub super));
10146 effect(KILL tmp, KILL cr);
10147
10148 ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10149 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10150
10151 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10152
10153 opcode(0x1); // Force zero of result reg on hit
10154
10155 ins_pipe(pipe_class_memory);
10156 %}
10157
10158 instruct partialSubtypeCheckVsZero(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp,
10159 immP0 zero, rFlagsReg cr)
10160 %{
10161 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10162 effect(KILL tmp, KILL result);
10163
10164 ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10165 format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
10166
10167 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10168
10169 opcode(0x0); // Don't zero result reg on hit
10170
10171 ins_pipe(pipe_class_memory);
10172 %}
10173
10174 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10175 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10176 %{
10177 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10178 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10179 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10180
10181 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10182 ins_encode %{
10183 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10184 __ string_compare($str1$$Register, $str2$$Register,
10185 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10186 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10187 StrIntrinsicNode::UU);
10188 %}
10189 ins_pipe(pipe_class_memory);
10190 %}
10191
10192 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10193 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10194 %{
10195 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10196 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10197 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10198
10199 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10200 ins_encode %{
10201 __ string_compare($str1$$Register, $str2$$Register,
10202 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10203 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10204 StrIntrinsicNode::LL);
10205 %}
10206 ins_pipe(pipe_class_memory);
10207 %}
10208
10209 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10210 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10211 %{
10212 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10213 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10214 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10215
10216 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10217 ins_encode %{
10218 __ string_compare($str1$$Register, $str2$$Register,
10219 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10220 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10221 StrIntrinsicNode::UL);
10222 %}
10223 ins_pipe(pipe_class_memory);
10224 %}
10225
10226 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10227 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10228 rFlagsReg cr)
10229 %{
10230 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10231 match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10232 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10233
10234 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10235 ins_encode %{
10236 __ string_compare($str1$$Register, $str2$$Register,
10237 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10238 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10239 StrIntrinsicNode::LU);
10240 %}
10241 ins_pipe(pipe_class_memory);
10242 %}
10243
10244 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10245 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10246 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10247 %{
10248 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10249 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10250 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10251 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10252
10253 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10254 ins_encode %{
10255 __ string_indexof($str1$$Register, $str2$$Register,
10256 $cnt1$$Register, $cnt2$$Register,
10257 $tmp1$$Register, $tmp2$$Register,
10258 $tmp3$$Register, $tmp4$$Register,
10259 $tmp5$$Register, $tmp6$$Register,
10260 $result$$Register, StrIntrinsicNode::UU);
10261 %}
10262 ins_pipe(pipe_class_memory);
10263 %}
10264
10265 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10266 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10267 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10268 %{
10269 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10270 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10271 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10272 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10273
10274 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10275 ins_encode %{
10276 __ string_indexof($str1$$Register, $str2$$Register,
10277 $cnt1$$Register, $cnt2$$Register,
10278 $tmp1$$Register, $tmp2$$Register,
10279 $tmp3$$Register, $tmp4$$Register,
10280 $tmp5$$Register, $tmp6$$Register,
10281 $result$$Register, StrIntrinsicNode::LL);
10282 %}
10283 ins_pipe(pipe_class_memory);
10284 %}
10285
10286 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10287 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10288 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10289 %{
10290 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10291 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10292 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10293 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10294 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10295
10296 ins_encode %{
10297 __ string_indexof($str1$$Register, $str2$$Register,
10298 $cnt1$$Register, $cnt2$$Register,
10299 $tmp1$$Register, $tmp2$$Register,
10300 $tmp3$$Register, $tmp4$$Register,
10301 $tmp5$$Register, $tmp6$$Register,
10302 $result$$Register, StrIntrinsicNode::UL);
10303 %}
10304 ins_pipe(pipe_class_memory);
10305 %}
10306
10307 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10308 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10309 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10310 %{
10311 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10312 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10313 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10314 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10315
10316 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10317
10318 ins_encode %{
10319 int icnt2 = (int)$int_cnt2$$constant;
10320 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10321 $cnt1$$Register, zr,
10322 $tmp1$$Register, $tmp2$$Register,
10323 $tmp3$$Register, $tmp4$$Register,
10324 icnt2, $result$$Register, StrIntrinsicNode::UU);
10325 %}
10326 ins_pipe(pipe_class_memory);
10327 %}
10328
10329 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10330 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10331 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10332 %{
10333 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10334 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10335 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10336 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10337
10338 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10339 ins_encode %{
10340 int icnt2 = (int)$int_cnt2$$constant;
10341 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10342 $cnt1$$Register, zr,
10343 $tmp1$$Register, $tmp2$$Register,
10344 $tmp3$$Register, $tmp4$$Register,
10345 icnt2, $result$$Register, StrIntrinsicNode::LL);
10346 %}
10347 ins_pipe(pipe_class_memory);
10348 %}
10349
10350 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10351 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10352 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10353 %{
10354 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10355 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10356 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10357 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10358
10359 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10360 ins_encode %{
10361 int icnt2 = (int)$int_cnt2$$constant;
10362 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10363 $cnt1$$Register, zr,
10364 $tmp1$$Register, $tmp2$$Register,
10365 $tmp3$$Register, $tmp4$$Register,
10366 icnt2, $result$$Register, StrIntrinsicNode::UL);
10367 %}
10368 ins_pipe(pipe_class_memory);
10369 %}
10370
10371 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10372 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10373 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10374 %{
10375 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10376 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10377 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10378 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10379
10380 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10381 ins_encode %{
10382 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10383 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10384 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10385 %}
10386 ins_pipe(pipe_class_memory);
10387 %}
10388
10389
10390 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10391 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10392 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10393 %{
10394 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10395 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10396 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10397 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10398
10399 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10400 ins_encode %{
10401 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10402 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10403 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10404 %}
10405 ins_pipe(pipe_class_memory);
10406 %}
10407
10408 // clearing of an array
10409 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy)
10410 %{
10411 predicate(!UseRVV);
10412 match(Set dummy (ClearArray cnt base));
10413 effect(USE_KILL cnt, USE_KILL base);
10414
10415 ins_cost(4 * DEFAULT_COST);
10416 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10417
10418 ins_encode %{
10419 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10420 if (tpc == NULL) {
10421 ciEnv::current()->record_failure("CodeCache is full");
10422 return;
10423 }
10424 %}
10425
10426 ins_pipe(pipe_class_memory);
10427 %}
10428
10429 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10430 %{
10431 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10432 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10433 match(Set dummy (ClearArray cnt base));
10434 effect(USE_KILL base, KILL cr);
10435
10436 ins_cost(4 * DEFAULT_COST);
10437 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10438
10439 ins_encode %{
10440 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10441 %}
10442
10443 ins_pipe(pipe_class_memory);
10444 %}
10445
10446 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10447 iRegI_R10 result, rFlagsReg cr)
10448 %{
10449 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10450 match(Set result (StrEquals (Binary str1 str2) cnt));
10451 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10452
10453 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10454 ins_encode %{
10455 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10456 __ string_equals($str1$$Register, $str2$$Register,
10457 $result$$Register, $cnt$$Register, 1);
10458 %}
10459 ins_pipe(pipe_class_memory);
10460 %}
10461
10462 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10463 iRegI_R10 result, rFlagsReg cr)
10464 %{
10465 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10466 match(Set result (StrEquals (Binary str1 str2) cnt));
10467 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10468
10469 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10470 ins_encode %{
10471 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10472 __ string_equals($str1$$Register, $str2$$Register,
10473 $result$$Register, $cnt$$Register, 2);
10474 %}
10475 ins_pipe(pipe_class_memory);
10476 %}
10477
10478 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10479 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10480 iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10481 %{
10482 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10483 match(Set result (AryEq ary1 ary2));
10484 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10485
10486 format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp5" %}
10487 ins_encode %{
10488 __ arrays_equals($ary1$$Register, $ary2$$Register,
10489 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10490 $result$$Register, $tmp5$$Register, 1);
10491 %}
10492 ins_pipe(pipe_class_memory);
10493 %}
10494
10495 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10496 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10497 iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10498 %{
10499 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10500 match(Set result (AryEq ary1 ary2));
10501 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10502
10503 format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp5" %}
10504 ins_encode %{
10505 __ arrays_equals($ary1$$Register, $ary2$$Register,
10506 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10507 $result$$Register, $tmp5$$Register, 2);
10508 %}
10509 ins_pipe(pipe_class_memory);
10510 %}
10511
10512 // ============================================================================
10513 // Safepoint Instructions
10514
10515 instruct safePoint(iRegP poll)
10516 %{
10517 match(SafePoint poll);
10518
10519 ins_cost(2 * LOAD_COST);
10520 format %{
10521 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10522 %}
10523 ins_encode %{
10524 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10525 %}
10526 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10527 %}
10528
10529 // ============================================================================
10530 // This name is KNOWN by the ADLC and cannot be changed.
10531 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10532 // for this guy.
10533 instruct tlsLoadP(javaThread_RegP dst)
10534 %{
10535 match(Set dst (ThreadLocal));
10536
10537 ins_cost(0);
10538
10539 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10540
10541 size(0);
10542
10543 ins_encode( /*empty*/ );
10544
10545 ins_pipe(pipe_class_empty);
10546 %}
10547
10548 // inlined locking and unlocking
10549 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10550 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10551 %{
10552 match(Set cr (FastLock object box));
10553 effect(TEMP tmp1, TEMP tmp2);
10554
10555 ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10556 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2, #@cmpFastLock" %}
10557
10558 ins_encode(riscv_enc_fast_lock(object, box, tmp1, tmp2));
10559
10560 ins_pipe(pipe_serial);
10561 %}
10562
10563 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10564 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10565 %{
10566 match(Set cr (FastUnlock object box));
10567 effect(TEMP tmp1, TEMP tmp2);
10568
10569 ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10570 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10571
10572 ins_encode(riscv_enc_fast_unlock(object, box, tmp1, tmp2));
10573
10574 ins_pipe(pipe_serial);
10575 %}
10576
10577 // Tail Call; Jump from runtime stub to Java code.
10578 // Also known as an 'interprocedural jump'.
10579 // Target of jump will eventually return to caller.
10580 // TailJump below removes the return address.
10581 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10582 %{
10583 match(TailCall jump_target method_oop);
10584
10585 ins_cost(BRANCH_COST);
10586
10587 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10588
10589 ins_encode(riscv_enc_tail_call(jump_target));
10590
10591 ins_pipe(pipe_class_call);
10592 %}
10593
10594 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10595 %{
10596 match(TailJump jump_target ex_oop);
10597
10598 ins_cost(ALU_COST + BRANCH_COST);
10599
10600 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10601
10602 ins_encode(riscv_enc_tail_jmp(jump_target));
10603
10604 ins_pipe(pipe_class_call);
10605 %}
10606
10607 // Create exception oop: created by stack-crawling runtime code.
10608 // Created exception is now available to this handler, and is setup
10609 // just prior to jumping to this handler. No code emitted.
10610 instruct CreateException(iRegP_R10 ex_oop)
10611 %{
10612 match(Set ex_oop (CreateEx));
10613
10614 ins_cost(0);
10615 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10616
10617 size(0);
10618
10619 ins_encode( /*empty*/ );
10620
10621 ins_pipe(pipe_class_empty);
10622 %}
10623
10624 // Rethrow exception: The exception oop will come in the first
10625 // argument position. Then JUMP (not call) to the rethrow stub code.
10626 instruct RethrowException()
10627 %{
10628 match(Rethrow);
10629
10630 ins_cost(BRANCH_COST);
10631
10632 format %{ "j rethrow_stub\t#@RethrowException" %}
10633
10634 ins_encode(riscv_enc_rethrow());
10635
10636 ins_pipe(pipe_class_call);
10637 %}
10638
10639 // Return Instruction
10640 // epilog node loads ret address into ra as part of frame pop
10641 instruct Ret()
10642 %{
10643 match(Return);
10644
10645 ins_cost(BRANCH_COST);
10646 format %{ "ret\t// return register, #@Ret" %}
10647
10648 ins_encode(riscv_enc_ret());
10649
10650 ins_pipe(pipe_branch);
10651 %}
10652
10653 // Die now.
10654 instruct ShouldNotReachHere() %{
10655 match(Halt);
10656
10657 ins_cost(BRANCH_COST);
10658
10659 format %{ "#@ShouldNotReachHere" %}
10660
10661 ins_encode %{
10662 if (is_reachable()) {
10663 __ stop(_halt_reason);
10664 }
10665 %}
10666
10667 ins_pipe(pipe_class_default);
10668 %}
10669
10670
10671 //----------PEEPHOLE RULES-----------------------------------------------------
10672 // These must follow all instruction definitions as they use the names
10673 // defined in the instructions definitions.
10674 //
10675 // peepmatch ( root_instr_name [preceding_instruction]* );
10676 //
10677 // peepconstraint %{
10678 // (instruction_number.operand_name relational_op instruction_number.operand_name
10679 // [, ...] );
10680 // // instruction numbers are zero-based using left to right order in peepmatch
10681 //
10682 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10683 // // provide an instruction_number.operand_name for each operand that appears
10684 // // in the replacement instruction's match rule
10685 //
10686 // ---------VM FLAGS---------------------------------------------------------
10687 //
10688 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10689 //
10690 // Each peephole rule is given an identifying number starting with zero and
10691 // increasing by one in the order seen by the parser. An individual peephole
10692 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10693 // on the command-line.
10694 //
10695 // ---------CURRENT LIMITATIONS----------------------------------------------
10696 //
10697 // Only match adjacent instructions in same basic block
10698 // Only equality constraints
10699 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10700 // Only one replacement instruction
10701 //
10702 //----------SMARTSPILL RULES---------------------------------------------------
10703 // These must follow all instruction definitions as they use the names
10704 // defined in the instructions definitions.
10705
10706 // Local Variables:
10707 // mode: c++
10708 // End: