1 /*
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 3  * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
 4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 6  * This code is free software; you can redistribute it and/or modify it
 7  * under the terms of the GNU General Public License version 2 only, as
 8  * published by the Free Software Foundation.
 9  *
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11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * version 2 for more details (a copy is included in the LICENSE file that
14  * accompanied this code).
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16  * You should have received a copy of the GNU General Public License version
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25 
26 #ifndef CPU_RISCV_VMREG_RISCV_HPP
27 #define CPU_RISCV_VMREG_RISCV_HPP
28 
29 inline bool is_Register() {
30   return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
31 }
32 
33 inline bool is_FloatRegister() {
34   return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
35 }
36 
37 inline bool is_VectorRegister() {
38   return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_vpr;
39 }
40 
41 inline Register as_Register() {
42   assert(is_Register(), "must be");
43   return ::as_Register(value() / RegisterImpl::max_slots_per_register);
44 }
45 
46 inline FloatRegister as_FloatRegister() {
47   assert(is_FloatRegister() && is_even(value()), "must be");
48   return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) /
49                             FloatRegisterImpl::max_slots_per_register);
50 }
51 
52 inline VectorRegister as_VectorRegister() {
53   assert(is_VectorRegister() && ((value() & (VectorRegisterImpl::max_slots_per_register - 1)) == 0), "must be");
54   return ::as_VectorRegister((value() - ConcreteRegisterImpl::max_fpr) /
55                              VectorRegisterImpl::max_slots_per_register);
56 }
57 
58 inline bool is_concrete() {
59   assert(is_reg(), "must be");
60   if (is_VectorRegister()) {
61     int base = value() - ConcreteRegisterImpl::max_fpr;
62     return (base % VectorRegisterImpl::max_slots_per_register) == 0;
63   } else {
64     return is_even(value());
65   }
66 }
67 
68 #endif // CPU_RISCV_VMREG_RISCV_HPP