1 /*
 2  * Copyright (c) 2006, 2020, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
 4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 5  *
 6  * This code is free software; you can redistribute it and/or modify it
 7  * under the terms of the GNU General Public License version 2 only, as
 8  * published by the Free Software Foundation.
 9  *
10  * This code is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * version 2 for more details (a copy is included in the LICENSE file that
14  * accompanied this code).
15  *
16  * You should have received a copy of the GNU General Public License version
17  * 2 along with this work; if not, write to the Free Software Foundation,
18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19  *
20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21  * or visit www.oracle.com if you need additional information or have any
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24  */
25 
26 #ifndef CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP
27 #define CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP
28 
29 inline VMReg RegisterImpl::as_VMReg() {
30   if (this == noreg) {
31     return VMRegImpl::Bad();
32   }
33   return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register);
34 }
35 
36 inline VMReg FloatRegisterImpl::as_VMReg() {
37   return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) +
38                              ConcreteRegisterImpl::max_gpr);
39 }
40 
41 inline VMReg VectorRegisterImpl::as_VMReg() {
42   return VMRegImpl::as_VMReg((encoding() * VectorRegisterImpl::max_slots_per_register) +
43                              ConcreteRegisterImpl::max_fpr);
44 }
45 
46 #endif // CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP