1 /*
2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
171 }
172 #endif // PRODUCT
173
174
175 bool LIR_OprDesc::is_oop() const {
176 if (is_pointer()) {
177 return pointer()->is_oop_pointer();
178 } else {
179 OprType t= type_field();
180 assert(t != unknown_type, "not set");
181 return t == object_type;
182 }
183 }
184
185
186
187 void LIR_Op2::verify() const {
188 #ifdef ASSERT
189 switch (code()) {
190 case lir_cmove:
191 case lir_xchg:
192 break;
193
194 default:
195 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
196 "can't produce oops from arith");
197 }
198
199 if (TwoOperandLIRForm) {
200
201 #ifdef ASSERT
202 bool threeOperandForm = false;
203 #ifdef S390
204 // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
205 threeOperandForm =
206 code() == lir_shl ||
207 ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
208 #endif
209 #endif
210
221 case lir_shr:
222 assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
223 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
224 break;
225
226 // special handling for lir_ushr because of write barriers
227 case lir_ushr:
228 assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
229 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
230 break;
231
232 default:
233 break;
234 }
235 }
236 #endif
237 }
238
239
240 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block)
241 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
242 , _cond(cond)
243 , _label(block->label())
244 , _block(block)
245 , _ublock(NULL)
246 , _stub(NULL) {
247 }
248
249 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, CodeStub* stub) :
250 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
251 , _cond(cond)
252 , _label(stub->entry())
253 , _block(NULL)
254 , _ublock(NULL)
255 , _stub(stub) {
256 }
257
258 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock)
259 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
260 , _cond(cond)
261 , _label(block->label())
262 , _block(block)
263 , _ublock(ublock)
264 , _stub(NULL)
265 {
266 }
267
268 void LIR_OpBranch::change_block(BlockBegin* b) {
269 assert(_block != NULL, "must have old block");
270 assert(_block->label() == label(), "must be equal");
271
272 _block = b;
273 _label = b->label();
274 }
275
276 void LIR_OpBranch::change_ublock(BlockBegin* b) {
277 assert(_ublock != NULL, "must have old block");
278 _ublock = b;
279 }
280
281 void LIR_OpBranch::negate_cond() {
282 switch (_cond) {
283 case lir_cond_equal: _cond = lir_cond_notEqual; break;
284 case lir_cond_notEqual: _cond = lir_cond_equal; break;
285 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
286 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
287 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
288 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
289 default: ShouldNotReachHere();
290 }
291 }
292
293
294 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
295 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
296 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
297 CodeStub* stub)
298
299 : LIR_Op(code, result, NULL)
300 , _object(object)
301 , _array(LIR_OprFact::illegalOpr)
302 , _klass(klass)
303 , _tmp1(tmp1)
304 , _tmp2(tmp2)
305 , _tmp3(tmp3)
306 , _fast_check(fast_check)
307 , _info_for_patch(info_for_patch)
308 , _info_for_exception(info_for_exception)
496
497 assert(opConvert->_info == NULL, "must be");
498 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
499 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
500 #ifdef PPC32
501 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
502 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
503 #endif
504 do_stub(opConvert->_stub);
505
506 break;
507 }
508
509 // LIR_OpBranch;
510 case lir_branch: // may have info, input and result register always invalid
511 case lir_cond_float_branch: // may have info, input and result register always invalid
512 {
513 assert(op->as_OpBranch() != NULL, "must be");
514 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
515
516 if (opBranch->_info != NULL) do_info(opBranch->_info);
517 assert(opBranch->_result->is_illegal(), "not used");
518 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
519
520 break;
521 }
522
523
524 // LIR_OpAllocObj
525 case lir_alloc_object:
526 {
527 assert(op->as_OpAllocObj() != NULL, "must be");
528 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
529
530 if (opAllocObj->_info) do_info(opAllocObj->_info);
531 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
532 do_temp(opAllocObj->_opr);
533 }
534 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
535 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
584 if (op2->_info) do_info(op2->_info);
585 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
586 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
587 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
588 if (op2->_result->is_valid()) do_output(op2->_result);
589 if (op->code() == lir_xchg || op->code() == lir_xadd) {
590 // on ARM and PPC, return value is loaded first so could
591 // destroy inputs. On other platforms that implement those
592 // (x86, sparc), the extra constrainsts are harmless.
593 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
594 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
595 }
596
597 break;
598 }
599
600 // special handling for cmove: right input operand must not be equal
601 // to the result operand, otherwise the backend fails
602 case lir_cmove:
603 {
604 assert(op->as_Op2() != NULL, "must be");
605 LIR_Op2* op2 = (LIR_Op2*)op;
606
607 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
608 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
609 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
610
611 do_input(op2->_opr1);
612 do_input(op2->_opr2);
613 do_temp(op2->_opr2);
614 do_output(op2->_result);
615
616 break;
617 }
618
619 // vspecial handling for strict operations: register input operands
620 // as temp to guarantee that they do not overlap with other
621 // registers
622 case lir_mul:
623 case lir_div:
624 {
625 assert(op->as_Op2() != NULL, "must be");
626 LIR_Op2* op2 = (LIR_Op2*)op;
627
628 assert(op2->_info == NULL, "not used");
629 assert(op2->_opr1->is_valid(), "used");
630 assert(op2->_opr2->is_valid(), "used");
631 assert(op2->_result->is_valid(), "used");
632 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
633 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
634
1025 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1026 masm->emit_alloc_array(this);
1027 masm->append_code_stub(stub());
1028 }
1029
1030 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1031 masm->emit_opTypeCheck(this);
1032 if (stub()) {
1033 masm->append_code_stub(stub());
1034 }
1035 }
1036
1037 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1038 masm->emit_compare_and_swap(this);
1039 }
1040
1041 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1042 masm->emit_op3(this);
1043 }
1044
1045 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1046 masm->emit_lock(this);
1047 if (stub()) {
1048 masm->append_code_stub(stub());
1049 }
1050 }
1051
1052 #ifdef ASSERT
1053 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1054 masm->emit_assert(this);
1055 }
1056 #endif
1057
1058 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1059 masm->emit_delay(this);
1060 }
1061
1062 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1063 masm->emit_profile_call(this);
1064 }
1065
1066 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1067 masm->emit_profile_type(this);
1068 }
1069
1070 // LIR_List
1071 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1072 : _operations(8)
1073 , _compilation(compilation)
1074 #ifndef PRODUCT
1075 , _block(block)
1076 #endif
1077 #ifdef ASSERT
1078 , _file(NULL)
1079 , _line(0)
1080 #endif
1081 { }
1082
1083
1084 #ifdef ASSERT
1085 void LIR_List::set_file_and_line(const char * file, int line) {
1086 const char * f = strrchr(file, '/');
1087 if (f == NULL) f = strrchr(file, '\\');
1088 if (f == NULL) {
1089 f = file;
1090 } else {
1091 f++;
1092 }
1093 _file = f;
1094 _line = line;
1095 }
1096 #endif
1097
1098
1099 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1100 assert(this == buffer->lir_list(), "wrong lir list");
1101 const int n = _operations.length();
1102
1103 if (buffer->number_of_ops() > 0) {
1104 // increase size of instructions list
1105 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1106 // insert ops from buffer into instructions list
1107 int op_index = buffer->number_of_ops() - 1;
1108 int ip_index = buffer->number_of_insertion_points() - 1;
1109 int from_index = n - 1;
1110 int to_index = _operations.length() - 1;
1111 for (; ip_index >= 0; ip_index --) {
1112 int index = buffer->index_at(ip_index);
1113 // make room after insertion point
1114 while (index < from_index) {
1115 _operations.at_put(to_index --, _operations.at(from_index --));
1116 }
1117 // insert ops from buffer
1650 case lir_pop: s = "pop"; break;
1651 case lir_null_check: s = "null_check"; break;
1652 case lir_return: s = "return"; break;
1653 case lir_safepoint: s = "safepoint"; break;
1654 case lir_leal: s = "leal"; break;
1655 case lir_branch: s = "branch"; break;
1656 case lir_cond_float_branch: s = "flt_cond_br"; break;
1657 case lir_move: s = "move"; break;
1658 case lir_roundfp: s = "roundfp"; break;
1659 case lir_rtcall: s = "rtcall"; break;
1660 case lir_throw: s = "throw"; break;
1661 case lir_unwind: s = "unwind"; break;
1662 case lir_convert: s = "convert"; break;
1663 case lir_alloc_object: s = "alloc_obj"; break;
1664 case lir_monaddr: s = "mon_addr"; break;
1665 // LIR_Op2
1666 case lir_cmp: s = "cmp"; break;
1667 case lir_cmp_l2i: s = "cmp_l2i"; break;
1668 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1669 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1670 case lir_cmove: s = "cmove"; break;
1671 case lir_add: s = "add"; break;
1672 case lir_sub: s = "sub"; break;
1673 case lir_mul: s = "mul"; break;
1674 case lir_div: s = "div"; break;
1675 case lir_rem: s = "rem"; break;
1676 case lir_abs: s = "abs"; break;
1677 case lir_neg: s = "neg"; break;
1678 case lir_sqrt: s = "sqrt"; break;
1679 case lir_logic_and: s = "logic_and"; break;
1680 case lir_logic_or: s = "logic_or"; break;
1681 case lir_logic_xor: s = "logic_xor"; break;
1682 case lir_shl: s = "shift_left"; break;
1683 case lir_shr: s = "shift_right"; break;
1684 case lir_ushr: s = "ushift_right"; break;
1685 case lir_alloc_array: s = "alloc_array"; break;
1686 case lir_xadd: s = "xadd"; break;
1687 case lir_xchg: s = "xchg"; break;
1688 // LIR_Op3
1689 case lir_idiv: s = "idiv"; break;
1808 void LIR_OpRTCall::print_instr(outputStream* out) const {
1809 intx a = (intx)addr();
1810 out->print("%s", Runtime1::name_for_address(addr()));
1811 out->print(" ");
1812 tmp()->print(out);
1813 }
1814
1815 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1816 switch(code) {
1817 case lir_patch_none: break;
1818 case lir_patch_low: out->print("[patch_low]"); break;
1819 case lir_patch_high: out->print("[patch_high]"); break;
1820 case lir_patch_normal: out->print("[patch_normal]"); break;
1821 default: ShouldNotReachHere();
1822 }
1823 }
1824
1825 // LIR_OpBranch
1826 void LIR_OpBranch::print_instr(outputStream* out) const {
1827 print_condition(out, cond()); out->print(" ");
1828 if (block() != NULL) {
1829 out->print("[B%d] ", block()->block_id());
1830 } else if (stub() != NULL) {
1831 out->print("[");
1832 stub()->print_name(out);
1833 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1834 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1835 } else {
1836 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1837 }
1838 if (ublock() != NULL) {
1839 out->print("unordered: [B%d] ", ublock()->block_id());
1840 }
1841 }
1842
1843 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1844 switch(cond) {
1845 case lir_cond_equal: out->print("[EQ]"); break;
1846 case lir_cond_notEqual: out->print("[NE]"); break;
1847 case lir_cond_less: out->print("[LT]"); break;
1894 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1895 klass()->print(out); out->print(" ");
1896 obj()->print(out); out->print(" ");
1897 tmp1()->print(out); out->print(" ");
1898 tmp2()->print(out); out->print(" ");
1899 tmp3()->print(out); out->print(" ");
1900 tmp4()->print(out); out->print(" ");
1901 out->print("[hdr:%d]", header_size()); out->print(" ");
1902 out->print("[obj:%d]", object_size()); out->print(" ");
1903 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1904 }
1905
1906 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1907 _opr->print(out); out->print(" ");
1908 tmp()->print(out); out->print(" ");
1909 result_opr()->print(out); out->print(" ");
1910 }
1911
1912 // LIR_Op2
1913 void LIR_Op2::print_instr(outputStream* out) const {
1914 if (code() == lir_cmove || code() == lir_cmp) {
1915 print_condition(out, condition()); out->print(" ");
1916 }
1917 in_opr1()->print(out); out->print(" ");
1918 in_opr2()->print(out); out->print(" ");
1919 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
1920 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
1921 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
1922 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
1923 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
1924 result_opr()->print(out);
1925 }
1926
1927 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1928 klass()->print(out); out->print(" ");
1929 len()->print(out); out->print(" ");
1930 obj()->print(out); out->print(" ");
1931 tmp1()->print(out); out->print(" ");
1932 tmp2()->print(out); out->print(" ");
1933 tmp3()->print(out); out->print(" ");
1934 tmp4()->print(out); out->print(" ");
1945 if (code() != lir_store_check) {
1946 klass()->print_name_on(out); out->print(" ");
1947 if (fast_check()) out->print("fast_check ");
1948 }
1949 tmp1()->print(out); out->print(" ");
1950 tmp2()->print(out); out->print(" ");
1951 tmp3()->print(out); out->print(" ");
1952 result_opr()->print(out); out->print(" ");
1953 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
1954 }
1955
1956
1957 // LIR_Op3
1958 void LIR_Op3::print_instr(outputStream* out) const {
1959 in_opr1()->print(out); out->print(" ");
1960 in_opr2()->print(out); out->print(" ");
1961 in_opr3()->print(out); out->print(" ");
1962 result_opr()->print(out);
1963 }
1964
1965
1966 void LIR_OpLock::print_instr(outputStream* out) const {
1967 hdr_opr()->print(out); out->print(" ");
1968 obj_opr()->print(out); out->print(" ");
1969 lock_opr()->print(out); out->print(" ");
1970 if (_scratch->is_valid()) {
1971 _scratch->print(out); out->print(" ");
1972 }
1973 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1974 }
1975
1976 #ifdef ASSERT
1977 void LIR_OpAssert::print_instr(outputStream* out) const {
1978 print_condition(out, condition()); out->print(" ");
1979 in_opr1()->print(out); out->print(" ");
1980 in_opr2()->print(out); out->print(", \"");
1981 out->print("%s", msg()); out->print("\"");
1982 }
1983 #endif
1984
|
1 /*
2 * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
171 }
172 #endif // PRODUCT
173
174
175 bool LIR_OprDesc::is_oop() const {
176 if (is_pointer()) {
177 return pointer()->is_oop_pointer();
178 } else {
179 OprType t= type_field();
180 assert(t != unknown_type, "not set");
181 return t == object_type;
182 }
183 }
184
185
186
187 void LIR_Op2::verify() const {
188 #ifdef ASSERT
189 switch (code()) {
190 case lir_cmove:
191 #ifdef RISCV
192 assert(false, "lir_cmove is LIR_Op4 on RISCV");
193 #endif
194 case lir_xchg:
195 break;
196
197 default:
198 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
199 "can't produce oops from arith");
200 }
201
202 if (TwoOperandLIRForm) {
203
204 #ifdef ASSERT
205 bool threeOperandForm = false;
206 #ifdef S390
207 // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
208 threeOperandForm =
209 code() == lir_shl ||
210 ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
211 #endif
212 #endif
213
224 case lir_shr:
225 assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
226 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
227 break;
228
229 // special handling for lir_ushr because of write barriers
230 case lir_ushr:
231 assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
232 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
233 break;
234
235 default:
236 break;
237 }
238 }
239 #endif
240 }
241
242
243 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block)
244 #ifdef RISCV
245 : LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
246 #else
247 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
248 , _cond(cond)
249 #endif
250 , _label(block->label())
251 , _block(block)
252 , _ublock(NULL)
253 , _stub(NULL) {
254 }
255
256 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, CodeStub* stub) :
257 #ifdef RISCV
258 LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
259 #else
260 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
261 , _cond(cond)
262 #endif
263 , _label(stub->entry())
264 , _block(NULL)
265 , _ublock(NULL)
266 , _stub(stub) {
267 }
268
269 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock)
270 #ifdef RISCV
271 : LIR_Op2(lir_cond_float_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
272 #else
273 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
274 , _cond(cond)
275 #endif
276 , _label(block->label())
277 , _block(block)
278 , _ublock(ublock)
279 , _stub(NULL)
280 {
281 }
282
283 void LIR_OpBranch::change_block(BlockBegin* b) {
284 assert(_block != NULL, "must have old block");
285 assert(_block->label() == label(), "must be equal");
286
287 _block = b;
288 _label = b->label();
289 }
290
291 void LIR_OpBranch::change_ublock(BlockBegin* b) {
292 assert(_ublock != NULL, "must have old block");
293 _ublock = b;
294 }
295
296 void LIR_OpBranch::negate_cond() {
297 switch (cond()) {
298 case lir_cond_equal: set_cond(lir_cond_notEqual); break;
299 case lir_cond_notEqual: set_cond(lir_cond_equal); break;
300 case lir_cond_less: set_cond(lir_cond_greaterEqual); break;
301 case lir_cond_lessEqual: set_cond(lir_cond_greater); break;
302 case lir_cond_greaterEqual: set_cond(lir_cond_less); break;
303 case lir_cond_greater: set_cond(lir_cond_lessEqual); break;
304 default: ShouldNotReachHere();
305 }
306 }
307
308
309 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
310 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
311 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
312 CodeStub* stub)
313
314 : LIR_Op(code, result, NULL)
315 , _object(object)
316 , _array(LIR_OprFact::illegalOpr)
317 , _klass(klass)
318 , _tmp1(tmp1)
319 , _tmp2(tmp2)
320 , _tmp3(tmp3)
321 , _fast_check(fast_check)
322 , _info_for_patch(info_for_patch)
323 , _info_for_exception(info_for_exception)
511
512 assert(opConvert->_info == NULL, "must be");
513 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
514 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
515 #ifdef PPC32
516 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
517 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
518 #endif
519 do_stub(opConvert->_stub);
520
521 break;
522 }
523
524 // LIR_OpBranch;
525 case lir_branch: // may have info, input and result register always invalid
526 case lir_cond_float_branch: // may have info, input and result register always invalid
527 {
528 assert(op->as_OpBranch() != NULL, "must be");
529 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
530
531 #ifdef RISCV
532 assert(opBranch->_tmp1->is_illegal() && opBranch->_tmp2->is_illegal() &&
533 opBranch->_tmp3->is_illegal() && opBranch->_tmp4->is_illegal() &&
534 opBranch->_tmp5->is_illegal(), "not used");
535
536 if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
537 if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
538 #endif
539
540 if (opBranch->_info != NULL) do_info(opBranch->_info);
541 assert(opBranch->_result->is_illegal(), "not used");
542 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
543
544 break;
545 }
546
547
548 // LIR_OpAllocObj
549 case lir_alloc_object:
550 {
551 assert(op->as_OpAllocObj() != NULL, "must be");
552 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
553
554 if (opAllocObj->_info) do_info(opAllocObj->_info);
555 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
556 do_temp(opAllocObj->_opr);
557 }
558 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
559 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
608 if (op2->_info) do_info(op2->_info);
609 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
610 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
611 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
612 if (op2->_result->is_valid()) do_output(op2->_result);
613 if (op->code() == lir_xchg || op->code() == lir_xadd) {
614 // on ARM and PPC, return value is loaded first so could
615 // destroy inputs. On other platforms that implement those
616 // (x86, sparc), the extra constrainsts are harmless.
617 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
618 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
619 }
620
621 break;
622 }
623
624 // special handling for cmove: right input operand must not be equal
625 // to the result operand, otherwise the backend fails
626 case lir_cmove:
627 {
628 #ifdef RISCV
629 assert(op->as_Op4() != NULL, "must be");
630 LIR_Op4* op4 = (LIR_Op4*)op;
631
632 assert(op4->_info == NULL && op4->_tmp1->is_illegal() && op4->_tmp2->is_illegal() &&
633 op4->_tmp3->is_illegal() && op4->_tmp4->is_illegal() && op4->_tmp5->is_illegal(), "not used");
634 assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_result->is_valid(), "used");
635
636 do_input(op4->_opr1);
637 do_input(op4->_opr2);
638 if (op4->_opr3->is_valid()) do_input(op4->_opr3);
639 if (op4->_opr4->is_valid()) do_input(op4->_opr4);
640 do_temp(op4->_opr2);
641 do_output(op4->_result);
642 #else
643 assert(op->as_Op2() != NULL, "must be");
644 LIR_Op2* op2 = (LIR_Op2*)op;
645
646 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
647 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
648 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
649
650 do_input(op2->_opr1);
651 do_input(op2->_opr2);
652 do_temp(op2->_opr2);
653 do_output(op2->_result);
654 #endif
655
656 break;
657 }
658
659 // vspecial handling for strict operations: register input operands
660 // as temp to guarantee that they do not overlap with other
661 // registers
662 case lir_mul:
663 case lir_div:
664 {
665 assert(op->as_Op2() != NULL, "must be");
666 LIR_Op2* op2 = (LIR_Op2*)op;
667
668 assert(op2->_info == NULL, "not used");
669 assert(op2->_opr1->is_valid(), "used");
670 assert(op2->_opr2->is_valid(), "used");
671 assert(op2->_result->is_valid(), "used");
672 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
673 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
674
1065 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1066 masm->emit_alloc_array(this);
1067 masm->append_code_stub(stub());
1068 }
1069
1070 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1071 masm->emit_opTypeCheck(this);
1072 if (stub()) {
1073 masm->append_code_stub(stub());
1074 }
1075 }
1076
1077 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1078 masm->emit_compare_and_swap(this);
1079 }
1080
1081 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1082 masm->emit_op3(this);
1083 }
1084
1085 #ifdef RISCV
1086 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1087 masm->emit_op4(this);
1088 }
1089 #endif
1090
1091 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1092 masm->emit_lock(this);
1093 if (stub()) {
1094 masm->append_code_stub(stub());
1095 }
1096 }
1097
1098 #ifdef ASSERT
1099 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1100 masm->emit_assert(this);
1101 }
1102 #endif
1103
1104 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1105 masm->emit_delay(this);
1106 }
1107
1108 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1109 masm->emit_profile_call(this);
1110 }
1111
1112 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1113 masm->emit_profile_type(this);
1114 }
1115
1116 // LIR_List
1117 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1118 : _operations(8)
1119 , _compilation(compilation)
1120 #ifndef PRODUCT
1121 , _block(block)
1122 #endif
1123 #ifdef ASSERT
1124 , _file(NULL)
1125 , _line(0)
1126 #endif
1127 #ifdef RISCV
1128 , _cmp_opr1(LIR_OprFact::illegalOpr)
1129 , _cmp_opr2(LIR_OprFact::illegalOpr)
1130 #endif
1131 { }
1132
1133
1134 #ifdef ASSERT
1135 void LIR_List::set_file_and_line(const char * file, int line) {
1136 const char * f = strrchr(file, '/');
1137 if (f == NULL) f = strrchr(file, '\\');
1138 if (f == NULL) {
1139 f = file;
1140 } else {
1141 f++;
1142 }
1143 _file = f;
1144 _line = line;
1145 }
1146 #endif
1147
1148 #ifdef RISCV
1149 void LIR_List::set_cmp_oprs(LIR_Op* op) {
1150 switch (op->code()) {
1151 case lir_cmp:
1152 _cmp_opr1 = op->as_Op2()->in_opr1();
1153 _cmp_opr2 = op->as_Op2()->in_opr2();
1154 break;
1155 case lir_branch: // fall through
1156 case lir_cond_float_branch:
1157 assert(op->as_OpBranch()->cond() == lir_cond_always ||
1158 (_cmp_opr1 != LIR_OprFact::illegalOpr && _cmp_opr2 != LIR_OprFact::illegalOpr),
1159 "conditional branches must have legal operands");
1160 if (op->as_OpBranch()->cond() != lir_cond_always) {
1161 op->as_Op2()->set_in_opr1(_cmp_opr1);
1162 op->as_Op2()->set_in_opr2(_cmp_opr2);
1163 }
1164 break;
1165 case lir_cmove:
1166 op->as_Op4()->set_in_opr3(_cmp_opr1);
1167 op->as_Op4()->set_in_opr4(_cmp_opr2);
1168 break;
1169 #if INCLUDE_ZGC
1170 case lir_zloadbarrier_test:
1171 _cmp_opr1 = FrameMap::as_opr(t1);
1172 _cmp_opr2 = LIR_OprFact::intConst(0);
1173 break;
1174 #endif
1175 default:
1176 break;
1177 }
1178 }
1179 #endif
1180
1181 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1182 assert(this == buffer->lir_list(), "wrong lir list");
1183 const int n = _operations.length();
1184
1185 if (buffer->number_of_ops() > 0) {
1186 // increase size of instructions list
1187 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1188 // insert ops from buffer into instructions list
1189 int op_index = buffer->number_of_ops() - 1;
1190 int ip_index = buffer->number_of_insertion_points() - 1;
1191 int from_index = n - 1;
1192 int to_index = _operations.length() - 1;
1193 for (; ip_index >= 0; ip_index --) {
1194 int index = buffer->index_at(ip_index);
1195 // make room after insertion point
1196 while (index < from_index) {
1197 _operations.at_put(to_index --, _operations.at(from_index --));
1198 }
1199 // insert ops from buffer
1732 case lir_pop: s = "pop"; break;
1733 case lir_null_check: s = "null_check"; break;
1734 case lir_return: s = "return"; break;
1735 case lir_safepoint: s = "safepoint"; break;
1736 case lir_leal: s = "leal"; break;
1737 case lir_branch: s = "branch"; break;
1738 case lir_cond_float_branch: s = "flt_cond_br"; break;
1739 case lir_move: s = "move"; break;
1740 case lir_roundfp: s = "roundfp"; break;
1741 case lir_rtcall: s = "rtcall"; break;
1742 case lir_throw: s = "throw"; break;
1743 case lir_unwind: s = "unwind"; break;
1744 case lir_convert: s = "convert"; break;
1745 case lir_alloc_object: s = "alloc_obj"; break;
1746 case lir_monaddr: s = "mon_addr"; break;
1747 // LIR_Op2
1748 case lir_cmp: s = "cmp"; break;
1749 case lir_cmp_l2i: s = "cmp_l2i"; break;
1750 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1751 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1752 // cmove is a LIR_Op4 on RISCV
1753 case lir_cmove: s = "cmove"; break;
1754 case lir_add: s = "add"; break;
1755 case lir_sub: s = "sub"; break;
1756 case lir_mul: s = "mul"; break;
1757 case lir_div: s = "div"; break;
1758 case lir_rem: s = "rem"; break;
1759 case lir_abs: s = "abs"; break;
1760 case lir_neg: s = "neg"; break;
1761 case lir_sqrt: s = "sqrt"; break;
1762 case lir_logic_and: s = "logic_and"; break;
1763 case lir_logic_or: s = "logic_or"; break;
1764 case lir_logic_xor: s = "logic_xor"; break;
1765 case lir_shl: s = "shift_left"; break;
1766 case lir_shr: s = "shift_right"; break;
1767 case lir_ushr: s = "ushift_right"; break;
1768 case lir_alloc_array: s = "alloc_array"; break;
1769 case lir_xadd: s = "xadd"; break;
1770 case lir_xchg: s = "xchg"; break;
1771 // LIR_Op3
1772 case lir_idiv: s = "idiv"; break;
1891 void LIR_OpRTCall::print_instr(outputStream* out) const {
1892 intx a = (intx)addr();
1893 out->print("%s", Runtime1::name_for_address(addr()));
1894 out->print(" ");
1895 tmp()->print(out);
1896 }
1897
1898 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1899 switch(code) {
1900 case lir_patch_none: break;
1901 case lir_patch_low: out->print("[patch_low]"); break;
1902 case lir_patch_high: out->print("[patch_high]"); break;
1903 case lir_patch_normal: out->print("[patch_normal]"); break;
1904 default: ShouldNotReachHere();
1905 }
1906 }
1907
1908 // LIR_OpBranch
1909 void LIR_OpBranch::print_instr(outputStream* out) const {
1910 print_condition(out, cond()); out->print(" ");
1911 #ifdef RISCV
1912 in_opr1()->print(out); out->print(" ");
1913 in_opr2()->print(out); out->print(" ");
1914 #endif
1915 if (block() != NULL) {
1916 out->print("[B%d] ", block()->block_id());
1917 } else if (stub() != NULL) {
1918 out->print("[");
1919 stub()->print_name(out);
1920 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1921 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1922 } else {
1923 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1924 }
1925 if (ublock() != NULL) {
1926 out->print("unordered: [B%d] ", ublock()->block_id());
1927 }
1928 }
1929
1930 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1931 switch(cond) {
1932 case lir_cond_equal: out->print("[EQ]"); break;
1933 case lir_cond_notEqual: out->print("[NE]"); break;
1934 case lir_cond_less: out->print("[LT]"); break;
1981 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1982 klass()->print(out); out->print(" ");
1983 obj()->print(out); out->print(" ");
1984 tmp1()->print(out); out->print(" ");
1985 tmp2()->print(out); out->print(" ");
1986 tmp3()->print(out); out->print(" ");
1987 tmp4()->print(out); out->print(" ");
1988 out->print("[hdr:%d]", header_size()); out->print(" ");
1989 out->print("[obj:%d]", object_size()); out->print(" ");
1990 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1991 }
1992
1993 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1994 _opr->print(out); out->print(" ");
1995 tmp()->print(out); out->print(" ");
1996 result_opr()->print(out); out->print(" ");
1997 }
1998
1999 // LIR_Op2
2000 void LIR_Op2::print_instr(outputStream* out) const {
2001 #ifdef RISCV
2002 if (code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch) {
2003 #else
2004 if (code() == lir_cmove || code() == lir_cmp) {
2005 #endif
2006 print_condition(out, condition()); out->print(" ");
2007 }
2008 in_opr1()->print(out); out->print(" ");
2009 in_opr2()->print(out); out->print(" ");
2010 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2011 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2012 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2013 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2014 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2015 result_opr()->print(out);
2016 }
2017
2018 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2019 klass()->print(out); out->print(" ");
2020 len()->print(out); out->print(" ");
2021 obj()->print(out); out->print(" ");
2022 tmp1()->print(out); out->print(" ");
2023 tmp2()->print(out); out->print(" ");
2024 tmp3()->print(out); out->print(" ");
2025 tmp4()->print(out); out->print(" ");
2036 if (code() != lir_store_check) {
2037 klass()->print_name_on(out); out->print(" ");
2038 if (fast_check()) out->print("fast_check ");
2039 }
2040 tmp1()->print(out); out->print(" ");
2041 tmp2()->print(out); out->print(" ");
2042 tmp3()->print(out); out->print(" ");
2043 result_opr()->print(out); out->print(" ");
2044 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2045 }
2046
2047
2048 // LIR_Op3
2049 void LIR_Op3::print_instr(outputStream* out) const {
2050 in_opr1()->print(out); out->print(" ");
2051 in_opr2()->print(out); out->print(" ");
2052 in_opr3()->print(out); out->print(" ");
2053 result_opr()->print(out);
2054 }
2055
2056 #ifdef RISCV
2057 // LIR_Op4
2058 void LIR_Op4::print_instr(outputStream* out) const {
2059 print_condition(out, condition()); out->print(" ");
2060 in_opr1()->print(out); out->print(" ");
2061 in_opr2()->print(out); out->print(" ");
2062 in_opr3()->print(out); out->print(" ");
2063 in_opr4()->print(out); out->print(" ");
2064 result_opr()->print(out);
2065 }
2066 #endif
2067
2068 void LIR_OpLock::print_instr(outputStream* out) const {
2069 hdr_opr()->print(out); out->print(" ");
2070 obj_opr()->print(out); out->print(" ");
2071 lock_opr()->print(out); out->print(" ");
2072 if (_scratch->is_valid()) {
2073 _scratch->print(out); out->print(" ");
2074 }
2075 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2076 }
2077
2078 #ifdef ASSERT
2079 void LIR_OpAssert::print_instr(outputStream* out) const {
2080 print_condition(out, condition()); out->print(" ");
2081 in_opr1()->print(out); out->print(" ");
2082 in_opr2()->print(out); out->print(", \"");
2083 out->print("%s", msg()); out->print("\"");
2084 }
2085 #endif
2086
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