1 /*
2 * Copyright (c) 2005, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CFGPrinter.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_FrameMap.hpp"
30 #include "c1/c1_IR.hpp"
31 #include "c1/c1_LIRGenerator.hpp"
32 #include "c1/c1_LinearScan.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "code/vmreg.inline.hpp"
35 #include "runtime/timerTrace.hpp"
36 #include "utilities/bitMap.inline.hpp"
37
38 #ifndef PRODUCT
39
40 static LinearScanStatistic _stat_before_alloc;
41 static LinearScanStatistic _stat_after_asign;
42 static LinearScanStatistic _stat_final;
43
44 static LinearScanTimers _total_timer;
45
46 // helper macro for short definition of timer
47 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
48
49 #else
50 #define TIME_LINEAR_SCAN(timer_name)
51 #endif
52
53 #ifdef ASSERT
54
55 // helper macro for short definition of trace-output inside code
56 #define TRACE_LINEAR_SCAN(level, code) \
57 if (TraceLinearScanLevel >= level) { \
58 code; \
59 }
60 #else
61 #define TRACE_LINEAR_SCAN(level, code)
62 #endif
63
64 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
65 #ifdef _LP64
66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1};
67 #else
68 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
69 #endif
70
71
72 // Implementation of LinearScan
73
74 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
75 : _compilation(ir->compilation())
76 , _ir(ir)
77 , _gen(gen)
78 , _frame_map(frame_map)
79 , _cached_blocks(*ir->linear_scan_order())
80 , _num_virtual_regs(gen->max_virtual_register_number())
81 , _has_fpu_registers(false)
82 , _num_calls(-1)
83 , _max_spills(0)
84 , _unused_spill_slot(-1)
85 , _intervals(0) // initialized later with correct length
86 , _new_intervals_from_allocation(NULL)
87 , _sorted_intervals(NULL)
88 , _needs_full_resort(false)
89 , _lir_ops(0) // initialized later with correct length
90 , _block_of_op(0) // initialized later with correct length
91 , _has_info(0)
92 , _has_call(0)
93 , _interval_in_loop(0) // initialized later with correct length
94 , _scope_value_cache(0) // initialized later with correct length
95 #ifdef IA32
96 , _fpu_stack_allocator(NULL)
97 #endif
98 {
99 assert(this->ir() != NULL, "check if valid");
100 assert(this->compilation() != NULL, "check if valid");
101 assert(this->gen() != NULL, "check if valid");
102 assert(this->frame_map() != NULL, "check if valid");
103 }
104
105
106 // ********** functions for converting LIR-Operands to register numbers
107 //
108 // Emulate a flat register file comprising physical integer registers,
109 // physical floating-point registers and virtual registers, in that order.
110 // Virtual registers already have appropriate numbers, since V0 is
111 // the number of physical registers.
112 // Returns -1 for hi word if opr is a single word operand.
113 //
114 // Note: the inverse operation (calculating an operand for register numbers)
115 // is done in calc_operand_for_interval()
116
117 int LinearScan::reg_num(LIR_Opr opr) {
118 assert(opr->is_register(), "should not call this otherwise");
119
120 if (opr->is_virtual_register()) {
121 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
122 return opr->vreg_number();
123 } else if (opr->is_single_cpu()) {
124 return opr->cpu_regnr();
125 } else if (opr->is_double_cpu()) {
126 return opr->cpu_regnrLo();
127 #ifdef X86
128 } else if (opr->is_single_xmm()) {
129 return opr->fpu_regnr() + pd_first_xmm_reg;
130 } else if (opr->is_double_xmm()) {
131 return opr->fpu_regnrLo() + pd_first_xmm_reg;
132 #endif
133 } else if (opr->is_single_fpu()) {
134 return opr->fpu_regnr() + pd_first_fpu_reg;
135 } else if (opr->is_double_fpu()) {
136 return opr->fpu_regnrLo() + pd_first_fpu_reg;
137 } else {
138 ShouldNotReachHere();
139 return -1;
140 }
141 }
142
143 int LinearScan::reg_numHi(LIR_Opr opr) {
144 assert(opr->is_register(), "should not call this otherwise");
145
146 if (opr->is_virtual_register()) {
147 return -1;
148 } else if (opr->is_single_cpu()) {
149 return -1;
150 } else if (opr->is_double_cpu()) {
151 return opr->cpu_regnrHi();
152 #ifdef X86
153 } else if (opr->is_single_xmm()) {
154 return -1;
155 } else if (opr->is_double_xmm()) {
156 return -1;
157 #endif
158 } else if (opr->is_single_fpu()) {
159 return -1;
160 } else if (opr->is_double_fpu()) {
161 return opr->fpu_regnrHi() + pd_first_fpu_reg;
162 } else {
163 ShouldNotReachHere();
164 return -1;
165 }
166 }
167
168
169 // ********** functions for classification of intervals
170
171 bool LinearScan::is_precolored_interval(const Interval* i) {
172 return i->reg_num() < LinearScan::nof_regs;
173 }
174
175 bool LinearScan::is_virtual_interval(const Interval* i) {
176 return i->reg_num() >= LIR_OprDesc::vreg_base;
177 }
178
179 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
180 return i->reg_num() < LinearScan::nof_cpu_regs;
181 }
182
183 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
184 #if defined(__SOFTFP__) || defined(E500V2)
185 return i->reg_num() >= LIR_OprDesc::vreg_base;
186 #else
187 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
188 #endif // __SOFTFP__ or E500V2
189 }
190
191 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
192 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
193 }
194
195 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
196 #if defined(__SOFTFP__) || defined(E500V2)
197 return false;
198 #else
199 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
200 #endif // __SOFTFP__ or E500V2
201 }
202
203 bool LinearScan::is_in_fpu_register(const Interval* i) {
204 // fixed intervals not needed for FPU stack allocation
205 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
206 }
207
208 bool LinearScan::is_oop_interval(const Interval* i) {
209 // fixed intervals never contain oops
210 return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
211 }
212
213
214 // ********** General helper functions
215
216 // compute next unused stack index that can be used for spilling
217 int LinearScan::allocate_spill_slot(bool double_word) {
218 int spill_slot;
219 if (double_word) {
220 if ((_max_spills & 1) == 1) {
221 // alignment of double-word values
222 // the hole because of the alignment is filled with the next single-word value
223 assert(_unused_spill_slot == -1, "wasting a spill slot");
224 _unused_spill_slot = _max_spills;
225 _max_spills++;
226 }
227 spill_slot = _max_spills;
228 _max_spills += 2;
229
230 } else if (_unused_spill_slot != -1) {
231 // re-use hole that was the result of a previous double-word alignment
232 spill_slot = _unused_spill_slot;
233 _unused_spill_slot = -1;
234
235 } else {
236 spill_slot = _max_spills;
237 _max_spills++;
238 }
239
240 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
241
242 // if too many slots used, bailout compilation.
243 if (result > 2000) {
244 bailout("too many stack slots used");
245 }
246
247 return result;
248 }
249
250 void LinearScan::assign_spill_slot(Interval* it) {
251 // assign the canonical spill slot of the parent (if a part of the interval
252 // is already spilled) or allocate a new spill slot
253 if (it->canonical_spill_slot() >= 0) {
254 it->assign_reg(it->canonical_spill_slot());
255 } else {
256 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
257 it->set_canonical_spill_slot(spill);
258 it->assign_reg(spill);
259 }
260 }
261
262 void LinearScan::propagate_spill_slots() {
263 if (!frame_map()->finalize_frame(max_spills())) {
264 bailout("frame too large");
265 }
266 }
267
268 // create a new interval with a predefined reg_num
269 // (only used for parent intervals that are created during the building phase)
270 Interval* LinearScan::create_interval(int reg_num) {
271 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
272
273 Interval* interval = new Interval(reg_num);
274 _intervals.at_put(reg_num, interval);
275
276 // assign register number for precolored intervals
277 if (reg_num < LIR_OprDesc::vreg_base) {
278 interval->assign_reg(reg_num);
279 }
280 return interval;
281 }
282
283 // assign a new reg_num to the interval and append it to the list of intervals
284 // (only used for child intervals that are created during register allocation)
285 void LinearScan::append_interval(Interval* it) {
286 it->set_reg_num(_intervals.length());
287 _intervals.append(it);
288 IntervalList* new_intervals = _new_intervals_from_allocation;
289 if (new_intervals == NULL) {
290 new_intervals = _new_intervals_from_allocation = new IntervalList();
291 }
292 new_intervals->append(it);
293 }
294
295 // copy the vreg-flags if an interval is split
296 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
297 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
298 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
299 }
300 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
301 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
302 }
303
304 // Note: do not copy the must_start_in_memory flag because it is not necessary for child
305 // intervals (only the very beginning of the interval must be in memory)
306 }
307
308
309 // ********** spill move optimization
310 // eliminate moves from register to stack if stack slot is known to be correct
311
312 // called during building of intervals
313 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
314 assert(interval->is_split_parent(), "can only be called for split parents");
315
316 switch (interval->spill_state()) {
317 case noDefinitionFound:
318 assert(interval->spill_definition_pos() == -1, "must no be set before");
319 interval->set_spill_definition_pos(def_pos);
320 interval->set_spill_state(oneDefinitionFound);
321 break;
322
323 case oneDefinitionFound:
324 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
325 if (def_pos < interval->spill_definition_pos() - 2) {
326 // second definition found, so no spill optimization possible for this interval
327 interval->set_spill_state(noOptimization);
328 } else {
329 // two consecutive definitions (because of two-operand LIR form)
330 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
331 }
332 break;
333
334 case noOptimization:
335 // nothing to do
336 break;
337
338 default:
339 assert(false, "other states not allowed at this time");
340 }
341 }
342
343 // called during register allocation
344 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
345 switch (interval->spill_state()) {
346 case oneDefinitionFound: {
347 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
348 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
349
350 if (def_loop_depth < spill_loop_depth) {
351 // the loop depth of the spilling position is higher then the loop depth
352 // at the definition of the interval -> move write to memory out of loop
353 // by storing at definitin of the interval
354 interval->set_spill_state(storeAtDefinition);
355 } else {
356 // the interval is currently spilled only once, so for now there is no
357 // reason to store the interval at the definition
358 interval->set_spill_state(oneMoveInserted);
359 }
360 break;
361 }
362
363 case oneMoveInserted: {
364 // the interval is spilled more then once, so it is better to store it to
365 // memory at the definition
366 interval->set_spill_state(storeAtDefinition);
367 break;
368 }
369
370 case storeAtDefinition:
371 case startInMemory:
372 case noOptimization:
373 case noDefinitionFound:
374 // nothing to do
375 break;
376
377 default:
378 assert(false, "other states not allowed at this time");
379 }
380 }
381
382
383 bool LinearScan::must_store_at_definition(const Interval* i) {
384 return i->is_split_parent() && i->spill_state() == storeAtDefinition;
385 }
386
387 // called once before asignment of register numbers
388 void LinearScan::eliminate_spill_moves() {
389 TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
390 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
391
392 // collect all intervals that must be stored after their definion.
393 // the list is sorted by Interval::spill_definition_pos
394 Interval* interval;
395 Interval* temp_list;
396 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
397
398 #ifdef ASSERT
399 Interval* prev = NULL;
400 Interval* temp = interval;
401 while (temp != Interval::end()) {
402 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
403 if (prev != NULL) {
404 assert(temp->from() >= prev->from(), "intervals not sorted");
405 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
406 }
407
408 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
409 assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
410 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
411
412 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
413
414 temp = temp->next();
415 }
416 #endif
417
418 LIR_InsertionBuffer insertion_buffer;
419 int num_blocks = block_count();
420 for (int i = 0; i < num_blocks; i++) {
421 BlockBegin* block = block_at(i);
422 LIR_OpList* instructions = block->lir()->instructions_list();
423 int num_inst = instructions->length();
424 bool has_new = false;
425
426 // iterate all instructions of the block. skip the first because it is always a label
427 for (int j = 1; j < num_inst; j++) {
428 LIR_Op* op = instructions->at(j);
429 int op_id = op->id();
430
431 if (op_id == -1) {
432 // remove move from register to stack if the stack slot is guaranteed to be correct.
433 // only moves that have been inserted by LinearScan can be removed.
434 assert(op->code() == lir_move, "only moves can have a op_id of -1");
435 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
436 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
437
438 LIR_Op1* op1 = (LIR_Op1*)op;
439 Interval* interval = interval_at(op1->result_opr()->vreg_number());
440
441 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
442 // move target is a stack slot that is always correct, so eliminate instruction
443 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
444 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
445 }
446
447 } else {
448 // insert move from register to stack just after the beginning of the interval
449 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
450 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
451
452 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
453 if (!has_new) {
454 // prepare insertion buffer (appended when all instructions of the block are processed)
455 insertion_buffer.init(block->lir());
456 has_new = true;
457 }
458
459 LIR_Opr from_opr = operand_for_interval(interval);
460 LIR_Opr to_opr = canonical_spill_opr(interval);
461 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
462 assert(to_opr->is_stack(), "to operand must be a stack slot");
463
464 insertion_buffer.move(j, from_opr, to_opr);
465 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
466
467 interval = interval->next();
468 }
469 }
470 } // end of instruction iteration
471
472 if (has_new) {
473 block->lir()->append(&insertion_buffer);
474 }
475 } // end of block iteration
476
477 assert(interval == Interval::end(), "missed an interval");
478 }
479
480
481 // ********** Phase 1: number all instructions in all blocks
482 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
483
484 void LinearScan::number_instructions() {
485 {
486 // dummy-timer to measure the cost of the timer itself
487 // (this time is then subtracted from all other timers to get the real value)
488 TIME_LINEAR_SCAN(timer_do_nothing);
489 }
490 TIME_LINEAR_SCAN(timer_number_instructions);
491
492 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
493 int num_blocks = block_count();
494 int num_instructions = 0;
495 int i;
496 for (i = 0; i < num_blocks; i++) {
497 num_instructions += block_at(i)->lir()->instructions_list()->length();
498 }
499
500 // initialize with correct length
501 _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
502 _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
503
504 int op_id = 0;
505 int idx = 0;
506
507 for (i = 0; i < num_blocks; i++) {
508 BlockBegin* block = block_at(i);
509 block->set_first_lir_instruction_id(op_id);
510 LIR_OpList* instructions = block->lir()->instructions_list();
511
512 int num_inst = instructions->length();
513 for (int j = 0; j < num_inst; j++) {
514 LIR_Op* op = instructions->at(j);
515 op->set_id(op_id);
516
517 _lir_ops.at_put(idx, op);
518 _block_of_op.at_put(idx, block);
519 assert(lir_op_with_id(op_id) == op, "must match");
520
521 idx++;
522 op_id += 2; // numbering of lir_ops by two
523 }
524 block->set_last_lir_instruction_id(op_id - 2);
525 }
526 assert(idx == num_instructions, "must match");
527 assert(idx * 2 == op_id, "must match");
528
529 _has_call.initialize(num_instructions);
530 _has_info.initialize(num_instructions);
531 }
532
533
534 // ********** Phase 2: compute local live sets separately for each block
535 // (sets live_gen and live_kill for each block)
536
537 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
538 LIR_Opr opr = value->operand();
539 Constant* con = value->as_Constant();
540
541 // check some asumptions about debug information
542 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
543 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
544 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
545
546 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
547 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
548 int reg = opr->vreg_number();
549 if (!live_kill.at(reg)) {
550 live_gen.set_bit(reg);
551 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
552 }
553 }
554 }
555
556
557 void LinearScan::compute_local_live_sets() {
558 TIME_LINEAR_SCAN(timer_compute_local_live_sets);
559
560 int num_blocks = block_count();
561 int live_size = live_set_size();
562 bool local_has_fpu_registers = false;
563 int local_num_calls = 0;
564 LIR_OpVisitState visitor;
565
566 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
567
568 // iterate all blocks
569 for (int i = 0; i < num_blocks; i++) {
570 BlockBegin* block = block_at(i);
571
572 ResourceBitMap live_gen(live_size);
573 ResourceBitMap live_kill(live_size);
574
575 if (block->is_set(BlockBegin::exception_entry_flag)) {
576 // Phi functions at the begin of an exception handler are
577 // implicitly defined (= killed) at the beginning of the block.
578 for_each_phi_fun(block, phi,
579 if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
580 );
581 }
582
583 LIR_OpList* instructions = block->lir()->instructions_list();
584 int num_inst = instructions->length();
585
586 // iterate all instructions of the block. skip the first because it is always a label
587 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
588 for (int j = 1; j < num_inst; j++) {
589 LIR_Op* op = instructions->at(j);
590
591 // visit operation to collect all operands
592 visitor.visit(op);
593
594 if (visitor.has_call()) {
595 _has_call.set_bit(op->id() >> 1);
596 local_num_calls++;
597 }
598 if (visitor.info_count() > 0) {
599 _has_info.set_bit(op->id() >> 1);
600 }
601
602 // iterate input operands of instruction
603 int k, n, reg;
604 n = visitor.opr_count(LIR_OpVisitState::inputMode);
605 for (k = 0; k < n; k++) {
606 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
607 assert(opr->is_register(), "visitor should only return register operands");
608
609 if (opr->is_virtual_register()) {
610 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
611 reg = opr->vreg_number();
612 if (!live_kill.at(reg)) {
613 live_gen.set_bit(reg);
614 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
615 }
616 if (block->loop_index() >= 0) {
617 local_interval_in_loop.set_bit(reg, block->loop_index());
618 }
619 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
620 }
621
622 #ifdef ASSERT
623 // fixed intervals are never live at block boundaries, so
624 // they need not be processed in live sets.
625 // this is checked by these assertions to be sure about it.
626 // the entry block may have incoming values in registers, which is ok.
627 if (!opr->is_virtual_register() && block != ir()->start()) {
628 reg = reg_num(opr);
629 if (is_processed_reg_num(reg)) {
630 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
631 }
632 reg = reg_numHi(opr);
633 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
634 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
635 }
636 }
637 #endif
638 }
639
640 // Add uses of live locals from interpreter's point of view for proper debug information generation
641 n = visitor.info_count();
642 for (k = 0; k < n; k++) {
643 CodeEmitInfo* info = visitor.info_at(k);
644 ValueStack* stack = info->stack();
645 for_each_state_value(stack, value,
646 set_live_gen_kill(value, op, live_gen, live_kill);
647 local_has_fpu_registers = local_has_fpu_registers || value->type()->is_float_kind();
648 );
649 }
650
651 // iterate temp operands of instruction
652 n = visitor.opr_count(LIR_OpVisitState::tempMode);
653 for (k = 0; k < n; k++) {
654 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
655 assert(opr->is_register(), "visitor should only return register operands");
656
657 if (opr->is_virtual_register()) {
658 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
659 reg = opr->vreg_number();
660 live_kill.set_bit(reg);
661 if (block->loop_index() >= 0) {
662 local_interval_in_loop.set_bit(reg, block->loop_index());
663 }
664 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
665 }
666
667 #ifdef ASSERT
668 // fixed intervals are never live at block boundaries, so
669 // they need not be processed in live sets
670 // process them only in debug mode so that this can be checked
671 if (!opr->is_virtual_register()) {
672 reg = reg_num(opr);
673 if (is_processed_reg_num(reg)) {
674 live_kill.set_bit(reg_num(opr));
675 }
676 reg = reg_numHi(opr);
677 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
678 live_kill.set_bit(reg);
679 }
680 }
681 #endif
682 }
683
684 // iterate output operands of instruction
685 n = visitor.opr_count(LIR_OpVisitState::outputMode);
686 for (k = 0; k < n; k++) {
687 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
688 assert(opr->is_register(), "visitor should only return register operands");
689
690 if (opr->is_virtual_register()) {
691 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
692 reg = opr->vreg_number();
693 live_kill.set_bit(reg);
694 if (block->loop_index() >= 0) {
695 local_interval_in_loop.set_bit(reg, block->loop_index());
696 }
697 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
698 }
699
700 #ifdef ASSERT
701 // fixed intervals are never live at block boundaries, so
702 // they need not be processed in live sets
703 // process them only in debug mode so that this can be checked
704 if (!opr->is_virtual_register()) {
705 reg = reg_num(opr);
706 if (is_processed_reg_num(reg)) {
707 live_kill.set_bit(reg_num(opr));
708 }
709 reg = reg_numHi(opr);
710 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
711 live_kill.set_bit(reg);
712 }
713 }
714 #endif
715 }
716 } // end of instruction iteration
717
718 block->set_live_gen (live_gen);
719 block->set_live_kill(live_kill);
720 block->set_live_in (ResourceBitMap(live_size));
721 block->set_live_out (ResourceBitMap(live_size));
722
723 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
724 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
725 } // end of block iteration
726
727 // propagate local calculated information into LinearScan object
728 _has_fpu_registers = local_has_fpu_registers;
729 compilation()->set_has_fpu_code(local_has_fpu_registers);
730
731 _num_calls = local_num_calls;
732 _interval_in_loop = local_interval_in_loop;
733 }
734
735
736 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
737 // (sets live_in and live_out for each block)
738
739 void LinearScan::compute_global_live_sets() {
740 TIME_LINEAR_SCAN(timer_compute_global_live_sets);
741
742 int num_blocks = block_count();
743 bool change_occurred;
744 bool change_occurred_in_block;
745 int iteration_count = 0;
746 ResourceBitMap live_out(live_set_size()); // scratch set for calculations
747
748 // Perform a backward dataflow analysis to compute live_out and live_in for each block.
749 // The loop is executed until a fixpoint is reached (no changes in an iteration)
750 // Exception handlers must be processed because not all live values are
751 // present in the state array, e.g. because of global value numbering
752 do {
753 change_occurred = false;
754
755 // iterate all blocks in reverse order
756 for (int i = num_blocks - 1; i >= 0; i--) {
757 BlockBegin* block = block_at(i);
758
759 change_occurred_in_block = false;
760
761 // live_out(block) is the union of live_in(sux), for successors sux of block
762 int n = block->number_of_sux();
763 int e = block->number_of_exception_handlers();
764 if (n + e > 0) {
765 // block has successors
766 if (n > 0) {
767 live_out.set_from(block->sux_at(0)->live_in());
768 for (int j = 1; j < n; j++) {
769 live_out.set_union(block->sux_at(j)->live_in());
770 }
771 } else {
772 live_out.clear();
773 }
774 for (int j = 0; j < e; j++) {
775 live_out.set_union(block->exception_handler_at(j)->live_in());
776 }
777
778 if (!block->live_out().is_same(live_out)) {
779 // A change occurred. Swap the old and new live out sets to avoid copying.
780 ResourceBitMap temp = block->live_out();
781 block->set_live_out(live_out);
782 live_out = temp;
783
784 change_occurred = true;
785 change_occurred_in_block = true;
786 }
787 }
788
789 if (iteration_count == 0 || change_occurred_in_block) {
790 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
791 // note: live_in has to be computed only in first iteration or if live_out has changed!
792 ResourceBitMap live_in = block->live_in();
793 live_in.set_from(block->live_out());
794 live_in.set_difference(block->live_kill());
795 live_in.set_union(block->live_gen());
796 }
797
798 #ifdef ASSERT
799 if (TraceLinearScanLevel >= 4) {
800 char c = ' ';
801 if (iteration_count == 0 || change_occurred_in_block) {
802 c = '*';
803 }
804 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
805 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
806 }
807 #endif
808 }
809 iteration_count++;
810
811 if (change_occurred && iteration_count > 50) {
812 BAILOUT("too many iterations in compute_global_live_sets");
813 }
814 } while (change_occurred);
815
816
817 #ifdef ASSERT
818 // check that fixed intervals are not live at block boundaries
819 // (live set must be empty at fixed intervals)
820 for (int i = 0; i < num_blocks; i++) {
821 BlockBegin* block = block_at(i);
822 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
823 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty");
824 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
825 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
826 }
827 }
828 #endif
829
830 // check that the live_in set of the first block is empty
831 ResourceBitMap live_in_args(ir()->start()->live_in().size());
832 if (!ir()->start()->live_in().is_same(live_in_args)) {
833 #ifdef ASSERT
834 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
835 tty->print_cr("affected registers:");
836 print_bitmap(ir()->start()->live_in());
837
838 // print some additional information to simplify debugging
839 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
840 if (ir()->start()->live_in().at(i)) {
841 Instruction* instr = gen()->instruction_for_vreg(i);
842 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
843
844 for (int j = 0; j < num_blocks; j++) {
845 BlockBegin* block = block_at(j);
846 if (block->live_gen().at(i)) {
847 tty->print_cr(" used in block B%d", block->block_id());
848 }
849 if (block->live_kill().at(i)) {
850 tty->print_cr(" defined in block B%d", block->block_id());
851 }
852 }
853 }
854 }
855
856 #endif
857 // when this fails, virtual registers are used before they are defined.
858 assert(false, "live_in set of first block must be empty");
859 // bailout of if this occurs in product mode.
860 bailout("live_in set of first block not empty");
861 }
862 }
863
864
865 // ********** Phase 4: build intervals
866 // (fills the list _intervals)
867
868 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
869 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
870 LIR_Opr opr = value->operand();
871 Constant* con = value->as_Constant();
872
873 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
874 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
875 add_use(opr, from, to, use_kind);
876 }
877 }
878
879
880 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
881 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
882 assert(opr->is_register(), "should not be called otherwise");
883
884 if (opr->is_virtual_register()) {
885 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
886 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
887
888 } else {
889 int reg = reg_num(opr);
890 if (is_processed_reg_num(reg)) {
891 add_def(reg, def_pos, use_kind, opr->type_register());
892 }
893 reg = reg_numHi(opr);
894 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
895 add_def(reg, def_pos, use_kind, opr->type_register());
896 }
897 }
898 }
899
900 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
901 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
902 assert(opr->is_register(), "should not be called otherwise");
903
904 if (opr->is_virtual_register()) {
905 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
906 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
907
908 } else {
909 int reg = reg_num(opr);
910 if (is_processed_reg_num(reg)) {
911 add_use(reg, from, to, use_kind, opr->type_register());
912 }
913 reg = reg_numHi(opr);
914 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
915 add_use(reg, from, to, use_kind, opr->type_register());
916 }
917 }
918 }
919
920 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
921 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
922 assert(opr->is_register(), "should not be called otherwise");
923
924 if (opr->is_virtual_register()) {
925 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
926 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
927
928 } else {
929 int reg = reg_num(opr);
930 if (is_processed_reg_num(reg)) {
931 add_temp(reg, temp_pos, use_kind, opr->type_register());
932 }
933 reg = reg_numHi(opr);
934 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
935 add_temp(reg, temp_pos, use_kind, opr->type_register());
936 }
937 }
938 }
939
940
941 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
942 Interval* interval = interval_at(reg_num);
943 if (interval != NULL) {
944 assert(interval->reg_num() == reg_num, "wrong interval");
945
946 if (type != T_ILLEGAL) {
947 interval->set_type(type);
948 }
949
950 Range* r = interval->first();
951 if (r->from() <= def_pos) {
952 // Update the starting point (when a range is first created for a use, its
953 // start is the beginning of the current block until a def is encountered.)
954 r->set_from(def_pos);
955 interval->add_use_pos(def_pos, use_kind);
956
957 } else {
958 // Dead value - make vacuous interval
959 // also add use_kind for dead intervals
960 interval->add_range(def_pos, def_pos + 1);
961 interval->add_use_pos(def_pos, use_kind);
962 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
963 }
964
965 } else {
966 // Dead value - make vacuous interval
967 // also add use_kind for dead intervals
968 interval = create_interval(reg_num);
969 if (type != T_ILLEGAL) {
970 interval->set_type(type);
971 }
972
973 interval->add_range(def_pos, def_pos + 1);
974 interval->add_use_pos(def_pos, use_kind);
975 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
976 }
977
978 change_spill_definition_pos(interval, def_pos);
979 if (use_kind == noUse && interval->spill_state() <= startInMemory) {
980 // detection of method-parameters and roundfp-results
981 // TODO: move this directly to position where use-kind is computed
982 interval->set_spill_state(startInMemory);
983 }
984 }
985
986 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
987 Interval* interval = interval_at(reg_num);
988 if (interval == NULL) {
989 interval = create_interval(reg_num);
990 }
991 assert(interval->reg_num() == reg_num, "wrong interval");
992
993 if (type != T_ILLEGAL) {
994 interval->set_type(type);
995 }
996
997 interval->add_range(from, to);
998 interval->add_use_pos(to, use_kind);
999 }
1000
1001 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1002 Interval* interval = interval_at(reg_num);
1003 if (interval == NULL) {
1004 interval = create_interval(reg_num);
1005 }
1006 assert(interval->reg_num() == reg_num, "wrong interval");
1007
1008 if (type != T_ILLEGAL) {
1009 interval->set_type(type);
1010 }
1011
1012 interval->add_range(temp_pos, temp_pos + 1);
1013 interval->add_use_pos(temp_pos, use_kind);
1014 }
1015
1016
1017 // the results of this functions are used for optimizing spilling and reloading
1018 // if the functions return shouldHaveRegister and the interval is spilled,
1019 // it is not reloaded to a register.
1020 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1021 if (op->code() == lir_move) {
1022 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1023 LIR_Op1* move = (LIR_Op1*)op;
1024 LIR_Opr res = move->result_opr();
1025 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1026
1027 if (result_in_memory) {
1028 // Begin of an interval with must_start_in_memory set.
1029 // This interval will always get a stack slot first, so return noUse.
1030 return noUse;
1031
1032 } else if (move->in_opr()->is_stack()) {
1033 // method argument (condition must be equal to handle_method_arguments)
1034 return noUse;
1035
1036 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1037 // Move from register to register
1038 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1039 // special handling of phi-function moves inside osr-entry blocks
1040 // input operand must have a register instead of output operand (leads to better register allocation)
1041 return shouldHaveRegister;
1042 }
1043 }
1044 }
1045
1046 if (opr->is_virtual() &&
1047 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1048 // result is a stack-slot, so prevent immediate reloading
1049 return noUse;
1050 }
1051
1052 // all other operands require a register
1053 return mustHaveRegister;
1054 }
1055
1056 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1057 if (op->code() == lir_move) {
1058 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1059 LIR_Op1* move = (LIR_Op1*)op;
1060 LIR_Opr res = move->result_opr();
1061 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1062
1063 if (result_in_memory) {
1064 // Move to an interval with must_start_in_memory set.
1065 // To avoid moves from stack to stack (not allowed) force the input operand to a register
1066 return mustHaveRegister;
1067
1068 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1069 // Move from register to register
1070 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1071 // special handling of phi-function moves inside osr-entry blocks
1072 // input operand must have a register instead of output operand (leads to better register allocation)
1073 return mustHaveRegister;
1074 }
1075
1076 // The input operand is not forced to a register (moves from stack to register are allowed),
1077 // but it is faster if the input operand is in a register
1078 return shouldHaveRegister;
1079 }
1080 }
1081
1082
1083 #if defined(X86) || defined(S390)
1084 if (op->code() == lir_cmove) {
1085 // conditional moves can handle stack operands
1086 assert(op->result_opr()->is_register(), "result must always be in a register");
1087 return shouldHaveRegister;
1088 }
1089
1090 // optimizations for second input operand of arithmehtic operations on Intel
1091 // this operand is allowed to be on the stack in some cases
1092 BasicType opr_type = opr->type_register();
1093 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1094 if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1095 // SSE float instruction (T_DOUBLE only supported with SSE2)
1096 switch (op->code()) {
1097 case lir_cmp:
1098 case lir_add:
1099 case lir_sub:
1100 case lir_mul:
1101 case lir_div:
1102 {
1103 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1104 LIR_Op2* op2 = (LIR_Op2*)op;
1105 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1106 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1107 return shouldHaveRegister;
1108 }
1109 }
1110 default:
1111 break;
1112 }
1113 } else {
1114 // FPU stack float instruction
1115 switch (op->code()) {
1116 case lir_add:
1117 case lir_sub:
1118 case lir_mul:
1119 case lir_div:
1120 {
1121 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122 LIR_Op2* op2 = (LIR_Op2*)op;
1123 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125 return shouldHaveRegister;
1126 }
1127 }
1128 default:
1129 break;
1130 }
1131 }
1132 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1133 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1134 // T_OBJECT doesn't get spilled along with T_LONG.
1135 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1136 // integer instruction (note: long operands must always be in register)
1137 switch (op->code()) {
1138 case lir_cmp:
1139 case lir_add:
1140 case lir_sub:
1141 case lir_logic_and:
1142 case lir_logic_or:
1143 case lir_logic_xor:
1144 {
1145 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1146 LIR_Op2* op2 = (LIR_Op2*)op;
1147 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149 return shouldHaveRegister;
1150 }
1151 }
1152 default:
1153 break;
1154 }
1155 }
1156 #endif // X86 || S390
1157
1158 // all other operands require a register
1159 return mustHaveRegister;
1160 }
1161
1162
1163 void LinearScan::handle_method_arguments(LIR_Op* op) {
1164 // special handling for method arguments (moves from stack to virtual register):
1165 // the interval gets no register assigned, but the stack slot.
1166 // it is split before the first use by the register allocator.
1167
1168 if (op->code() == lir_move) {
1169 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1170 LIR_Op1* move = (LIR_Op1*)op;
1171
1172 if (move->in_opr()->is_stack()) {
1173 #ifdef ASSERT
1174 int arg_size = compilation()->method()->arg_size();
1175 LIR_Opr o = move->in_opr();
1176 if (o->is_single_stack()) {
1177 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1178 } else if (o->is_double_stack()) {
1179 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1180 } else {
1181 ShouldNotReachHere();
1182 }
1183
1184 assert(move->id() > 0, "invalid id");
1185 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1186 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1187
1188 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1189 #endif
1190
1191 Interval* interval = interval_at(reg_num(move->result_opr()));
1192
1193 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1194 interval->set_canonical_spill_slot(stack_slot);
1195 interval->assign_reg(stack_slot);
1196 }
1197 }
1198 }
1199
1200 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1201 // special handling for doubleword move from memory to register:
1202 // in this case the registers of the input address and the result
1203 // registers must not overlap -> add a temp range for the input registers
1204 if (op->code() == lir_move) {
1205 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1206 LIR_Op1* move = (LIR_Op1*)op;
1207
1208 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1209 LIR_Address* address = move->in_opr()->as_address_ptr();
1210 if (address != NULL) {
1211 if (address->base()->is_valid()) {
1212 add_temp(address->base(), op->id(), noUse);
1213 }
1214 if (address->index()->is_valid()) {
1215 add_temp(address->index(), op->id(), noUse);
1216 }
1217 }
1218 }
1219 }
1220 }
1221
1222 void LinearScan::add_register_hints(LIR_Op* op) {
1223 switch (op->code()) {
1224 case lir_move: // fall through
1225 case lir_convert: {
1226 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1227 LIR_Op1* move = (LIR_Op1*)op;
1228
1229 LIR_Opr move_from = move->in_opr();
1230 LIR_Opr move_to = move->result_opr();
1231
1232 if (move_to->is_register() && move_from->is_register()) {
1233 Interval* from = interval_at(reg_num(move_from));
1234 Interval* to = interval_at(reg_num(move_to));
1235 if (from != NULL && to != NULL) {
1236 to->set_register_hint(from);
1237 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1238 }
1239 }
1240 break;
1241 }
1242 case lir_cmove: {
1243 #ifdef RISCV
1244 assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4");
1245 LIR_Op4* cmove = (LIR_Op4*)op;
1246 #else
1247 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1248 LIR_Op2* cmove = (LIR_Op2*)op;
1249 #endif
1250
1251 LIR_Opr move_from = cmove->in_opr1();
1252 LIR_Opr move_to = cmove->result_opr();
1253
1254 if (move_to->is_register() && move_from->is_register()) {
1255 Interval* from = interval_at(reg_num(move_from));
1256 Interval* to = interval_at(reg_num(move_to));
1257 if (from != NULL && to != NULL) {
1258 to->set_register_hint(from);
1259 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1260 }
1261 }
1262 break;
1263 }
1264 default:
1265 break;
1266 }
1267 }
1268
1269
1270 void LinearScan::build_intervals() {
1271 TIME_LINEAR_SCAN(timer_build_intervals);
1272
1273 // initialize interval list with expected number of intervals
1274 // (32 is added to have some space for split children without having to resize the list)
1275 _intervals = IntervalList(num_virtual_regs() + 32);
1276 // initialize all slots that are used by build_intervals
1277 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1278
1279 // create a list with all caller-save registers (cpu, fpu, xmm)
1280 // when an instruction is a call, a temp range is created for all these registers
1281 int num_caller_save_registers = 0;
1282 int caller_save_registers[LinearScan::nof_regs];
1283
1284 int i;
1285 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1286 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1287 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1288 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1289 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1290 }
1291
1292 // temp ranges for fpu registers are only created when the method has
1293 // virtual fpu operands. Otherwise no allocation for fpu registers is
1294 // performed and so the temp ranges would be useless
1295 if (has_fpu_registers()) {
1296 #ifdef X86
1297 if (UseSSE < 2) {
1298 #endif // X86
1299 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1300 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1301 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1302 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1303 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1304 }
1305 #ifdef X86
1306 }
1307 #endif // X86
1308
1309 #ifdef X86
1310 if (UseSSE > 0) {
1311 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1312 for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1313 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1314 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1315 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1316 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1317 }
1318 }
1319 #endif // X86
1320 }
1321 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1322
1323
1324 LIR_OpVisitState visitor;
1325
1326 // iterate all blocks in reverse order
1327 for (i = block_count() - 1; i >= 0; i--) {
1328 BlockBegin* block = block_at(i);
1329 LIR_OpList* instructions = block->lir()->instructions_list();
1330 int block_from = block->first_lir_instruction_id();
1331 int block_to = block->last_lir_instruction_id();
1332
1333 assert(block_from == instructions->at(0)->id(), "must be");
1334 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be");
1335
1336 // Update intervals for registers live at the end of this block;
1337 ResourceBitMap live = block->live_out();
1338 int size = (int)live.size();
1339 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1340 assert(live.at(number), "should not stop here otherwise");
1341 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1342 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1343
1344 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1345
1346 // add special use positions for loop-end blocks when the
1347 // interval is used anywhere inside this loop. It's possible
1348 // that the block was part of a non-natural loop, so it might
1349 // have an invalid loop index.
1350 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1351 block->loop_index() != -1 &&
1352 is_interval_in_loop(number, block->loop_index())) {
1353 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1354 }
1355 }
1356
1357 // iterate all instructions of the block in reverse order.
1358 // skip the first instruction because it is always a label
1359 // definitions of intervals are processed before uses
1360 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1361 for (int j = instructions->length() - 1; j >= 1; j--) {
1362 LIR_Op* op = instructions->at(j);
1363 int op_id = op->id();
1364
1365 // visit operation to collect all operands
1366 visitor.visit(op);
1367
1368 // add a temp range for each register if operation destroys caller-save registers
1369 if (visitor.has_call()) {
1370 for (int k = 0; k < num_caller_save_registers; k++) {
1371 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1372 }
1373 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1374 }
1375
1376 // Add any platform dependent temps
1377 pd_add_temps(op);
1378
1379 // visit definitions (output and temp operands)
1380 int k, n;
1381 n = visitor.opr_count(LIR_OpVisitState::outputMode);
1382 for (k = 0; k < n; k++) {
1383 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1384 assert(opr->is_register(), "visitor should only return register operands");
1385 add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1386 }
1387
1388 n = visitor.opr_count(LIR_OpVisitState::tempMode);
1389 for (k = 0; k < n; k++) {
1390 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1391 assert(opr->is_register(), "visitor should only return register operands");
1392 add_temp(opr, op_id, mustHaveRegister);
1393 }
1394
1395 // visit uses (input operands)
1396 n = visitor.opr_count(LIR_OpVisitState::inputMode);
1397 for (k = 0; k < n; k++) {
1398 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1399 assert(opr->is_register(), "visitor should only return register operands");
1400 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1401 }
1402
1403 // Add uses of live locals from interpreter's point of view for proper
1404 // debug information generation
1405 // Treat these operands as temp values (if the life range is extended
1406 // to a call site, the value would be in a register at the call otherwise)
1407 n = visitor.info_count();
1408 for (k = 0; k < n; k++) {
1409 CodeEmitInfo* info = visitor.info_at(k);
1410 ValueStack* stack = info->stack();
1411 for_each_state_value(stack, value,
1412 add_use(value, block_from, op_id + 1, noUse);
1413 );
1414 }
1415
1416 // special steps for some instructions (especially moves)
1417 handle_method_arguments(op);
1418 handle_doubleword_moves(op);
1419 add_register_hints(op);
1420
1421 } // end of instruction iteration
1422 } // end of block iteration
1423
1424
1425 // add the range [0, 1[ to all fixed intervals
1426 // -> the register allocator need not handle unhandled fixed intervals
1427 for (int n = 0; n < LinearScan::nof_regs; n++) {
1428 Interval* interval = interval_at(n);
1429 if (interval != NULL) {
1430 interval->add_range(0, 1);
1431 }
1432 }
1433 }
1434
1435
1436 // ********** Phase 5: actual register allocation
1437
1438 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1439 if (*a != NULL) {
1440 if (*b != NULL) {
1441 return (*a)->from() - (*b)->from();
1442 } else {
1443 return -1;
1444 }
1445 } else {
1446 if (*b != NULL) {
1447 return 1;
1448 } else {
1449 return 0;
1450 }
1451 }
1452 }
1453
1454 #ifndef PRODUCT
1455 int interval_cmp(Interval* const& l, Interval* const& r) {
1456 return l->from() - r->from();
1457 }
1458
1459 bool find_interval(Interval* interval, IntervalArray* intervals) {
1460 bool found;
1461 int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1462
1463 if (!found) {
1464 return false;
1465 }
1466
1467 int from = interval->from();
1468
1469 // The index we've found using binary search is pointing to an interval
1470 // that is defined in the same place as the interval we were looking for.
1471 // So now we have to look around that index and find exact interval.
1472 for (int i = idx; i >= 0; i--) {
1473 if (intervals->at(i) == interval) {
1474 return true;
1475 }
1476 if (intervals->at(i)->from() != from) {
1477 break;
1478 }
1479 }
1480
1481 for (int i = idx + 1; i < intervals->length(); i++) {
1482 if (intervals->at(i) == interval) {
1483 return true;
1484 }
1485 if (intervals->at(i)->from() != from) {
1486 break;
1487 }
1488 }
1489
1490 return false;
1491 }
1492
1493 bool LinearScan::is_sorted(IntervalArray* intervals) {
1494 int from = -1;
1495 int null_count = 0;
1496
1497 for (int i = 0; i < intervals->length(); i++) {
1498 Interval* it = intervals->at(i);
1499 if (it != NULL) {
1500 assert(from <= it->from(), "Intervals are unordered");
1501 from = it->from();
1502 } else {
1503 null_count++;
1504 }
1505 }
1506
1507 assert(null_count == 0, "Sorted intervals should not contain nulls");
1508
1509 null_count = 0;
1510
1511 for (int i = 0; i < interval_count(); i++) {
1512 Interval* interval = interval_at(i);
1513 if (interval != NULL) {
1514 assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1515 } else {
1516 null_count++;
1517 }
1518 }
1519
1520 assert(interval_count() - null_count == intervals->length(),
1521 "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1522
1523 return true;
1524 }
1525 #endif
1526
1527 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1528 if (*prev != NULL) {
1529 (*prev)->set_next(interval);
1530 } else {
1531 *first = interval;
1532 }
1533 *prev = interval;
1534 }
1535
1536 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1537 assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1538
1539 *list1 = *list2 = Interval::end();
1540
1541 Interval* list1_prev = NULL;
1542 Interval* list2_prev = NULL;
1543 Interval* v;
1544
1545 const int n = _sorted_intervals->length();
1546 for (int i = 0; i < n; i++) {
1547 v = _sorted_intervals->at(i);
1548 if (v == NULL) continue;
1549
1550 if (is_list1(v)) {
1551 add_to_list(list1, &list1_prev, v);
1552 } else if (is_list2 == NULL || is_list2(v)) {
1553 add_to_list(list2, &list2_prev, v);
1554 }
1555 }
1556
1557 if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1558 if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1559
1560 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1561 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1562 }
1563
1564
1565 void LinearScan::sort_intervals_before_allocation() {
1566 TIME_LINEAR_SCAN(timer_sort_intervals_before);
1567
1568 if (_needs_full_resort) {
1569 // There is no known reason why this should occur but just in case...
1570 assert(false, "should never occur");
1571 // Re-sort existing interval list because an Interval::from() has changed
1572 _sorted_intervals->sort(interval_cmp);
1573 _needs_full_resort = false;
1574 }
1575
1576 IntervalList* unsorted_list = &_intervals;
1577 int unsorted_len = unsorted_list->length();
1578 int sorted_len = 0;
1579 int unsorted_idx;
1580 int sorted_idx = 0;
1581 int sorted_from_max = -1;
1582
1583 // calc number of items for sorted list (sorted list must not contain NULL values)
1584 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1585 if (unsorted_list->at(unsorted_idx) != NULL) {
1586 sorted_len++;
1587 }
1588 }
1589 IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1590
1591 // special sorting algorithm: the original interval-list is almost sorted,
1592 // only some intervals are swapped. So this is much faster than a complete QuickSort
1593 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1594 Interval* cur_interval = unsorted_list->at(unsorted_idx);
1595
1596 if (cur_interval != NULL) {
1597 int cur_from = cur_interval->from();
1598
1599 if (sorted_from_max <= cur_from) {
1600 sorted_list->at_put(sorted_idx++, cur_interval);
1601 sorted_from_max = cur_interval->from();
1602 } else {
1603 // the asumption that the intervals are already sorted failed,
1604 // so this interval must be sorted in manually
1605 int j;
1606 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1607 sorted_list->at_put(j + 1, sorted_list->at(j));
1608 }
1609 sorted_list->at_put(j + 1, cur_interval);
1610 sorted_idx++;
1611 }
1612 }
1613 }
1614 _sorted_intervals = sorted_list;
1615 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1616 }
1617
1618 void LinearScan::sort_intervals_after_allocation() {
1619 TIME_LINEAR_SCAN(timer_sort_intervals_after);
1620
1621 if (_needs_full_resort) {
1622 // Re-sort existing interval list because an Interval::from() has changed
1623 _sorted_intervals->sort(interval_cmp);
1624 _needs_full_resort = false;
1625 }
1626
1627 IntervalArray* old_list = _sorted_intervals;
1628 IntervalList* new_list = _new_intervals_from_allocation;
1629 int old_len = old_list->length();
1630 int new_len = new_list == NULL ? 0 : new_list->length();
1631
1632 if (new_len == 0) {
1633 // no intervals have been added during allocation, so sorted list is already up to date
1634 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1635 return;
1636 }
1637
1638 // conventional sort-algorithm for new intervals
1639 new_list->sort(interval_cmp);
1640
1641 // merge old and new list (both already sorted) into one combined list
1642 int combined_list_len = old_len + new_len;
1643 IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1644 int old_idx = 0;
1645 int new_idx = 0;
1646
1647 while (old_idx + new_idx < old_len + new_len) {
1648 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1649 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1650 old_idx++;
1651 } else {
1652 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1653 new_idx++;
1654 }
1655 }
1656
1657 _sorted_intervals = combined_list;
1658 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1659 }
1660
1661
1662 void LinearScan::allocate_registers() {
1663 TIME_LINEAR_SCAN(timer_allocate_registers);
1664
1665 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1666 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1667
1668 // collect cpu intervals
1669 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals,
1670 is_precolored_cpu_interval, is_virtual_cpu_interval);
1671
1672 // collect fpu intervals
1673 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals,
1674 is_precolored_fpu_interval, is_virtual_fpu_interval);
1675 // this fpu interval collection cannot be moved down below with the allocation section as
1676 // the cpu_lsw.walk() changes interval positions.
1677
1678 if (!has_fpu_registers()) {
1679 #ifdef ASSERT
1680 assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1681 #else
1682 if (not_precolored_fpu_intervals != Interval::end()) {
1683 BAILOUT("missed an uncolored fpu interval");
1684 }
1685 #endif
1686 }
1687
1688 // allocate cpu registers
1689 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1690 cpu_lsw.walk();
1691 cpu_lsw.finish_allocation();
1692
1693 if (has_fpu_registers()) {
1694 // allocate fpu registers
1695 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1696 fpu_lsw.walk();
1697 fpu_lsw.finish_allocation();
1698 }
1699 }
1700
1701
1702 // ********** Phase 6: resolve data flow
1703 // (insert moves at edges between blocks if intervals have been split)
1704
1705 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1706 // instead of returning NULL
1707 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1708 Interval* result = interval->split_child_at_op_id(op_id, mode);
1709 if (result != NULL) {
1710 return result;
1711 }
1712
1713 assert(false, "must find an interval, but do a clean bailout in product mode");
1714 result = new Interval(LIR_OprDesc::vreg_base);
1715 result->assign_reg(0);
1716 result->set_type(T_INT);
1717 BAILOUT_("LinearScan: interval is NULL", result);
1718 }
1719
1720
1721 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1722 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1723 assert(interval_at(reg_num) != NULL, "no interval found");
1724
1725 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1726 }
1727
1728 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1729 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1730 assert(interval_at(reg_num) != NULL, "no interval found");
1731
1732 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1733 }
1734
1735 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1736 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1737 assert(interval_at(reg_num) != NULL, "no interval found");
1738
1739 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1740 }
1741
1742
1743 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1744 DEBUG_ONLY(move_resolver.check_empty());
1745
1746 const int size = live_set_size();
1747 const ResourceBitMap live_at_edge = to_block->live_in();
1748
1749 // visit all registers where the live_at_edge bit is set
1750 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1751 assert(r < num_virtual_regs(), "live information set for not exisiting interval");
1752 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1753
1754 Interval* from_interval = interval_at_block_end(from_block, r);
1755 Interval* to_interval = interval_at_block_begin(to_block, r);
1756
1757 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1758 // need to insert move instruction
1759 move_resolver.add_mapping(from_interval, to_interval);
1760 }
1761 }
1762 }
1763
1764
1765 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1766 if (from_block->number_of_sux() <= 1) {
1767 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1768
1769 LIR_OpList* instructions = from_block->lir()->instructions_list();
1770 LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1771 if (branch != NULL) {
1772 // insert moves before branch
1773 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1774 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1775 } else {
1776 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1777 }
1778
1779 } else {
1780 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1781 #ifdef ASSERT
1782 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1783
1784 // because the number of predecessor edges matches the number of
1785 // successor edges, blocks which are reached by switch statements
1786 // may have be more than one predecessor but it will be guaranteed
1787 // that all predecessors will be the same.
1788 for (int i = 0; i < to_block->number_of_preds(); i++) {
1789 assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1790 }
1791 #endif
1792
1793 move_resolver.set_insert_position(to_block->lir(), 0);
1794 }
1795 }
1796
1797
1798 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1799 void LinearScan::resolve_data_flow() {
1800 TIME_LINEAR_SCAN(timer_resolve_data_flow);
1801
1802 int num_blocks = block_count();
1803 MoveResolver move_resolver(this);
1804 ResourceBitMap block_completed(num_blocks);
1805 ResourceBitMap already_resolved(num_blocks);
1806
1807 int i;
1808 for (i = 0; i < num_blocks; i++) {
1809 BlockBegin* block = block_at(i);
1810
1811 // check if block has only one predecessor and only one successor
1812 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1813 LIR_OpList* instructions = block->lir()->instructions_list();
1814 assert(instructions->at(0)->code() == lir_label, "block must start with label");
1815 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1816 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1817
1818 // check if block is empty (only label and branch)
1819 if (instructions->length() == 2) {
1820 BlockBegin* pred = block->pred_at(0);
1821 BlockBegin* sux = block->sux_at(0);
1822
1823 // prevent optimization of two consecutive blocks
1824 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1825 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1826 block_completed.set_bit(block->linear_scan_number());
1827
1828 // directly resolve between pred and sux (without looking at the empty block between)
1829 resolve_collect_mappings(pred, sux, move_resolver);
1830 if (move_resolver.has_mappings()) {
1831 move_resolver.set_insert_position(block->lir(), 0);
1832 move_resolver.resolve_and_append_moves();
1833 }
1834 }
1835 }
1836 }
1837 }
1838
1839
1840 for (i = 0; i < num_blocks; i++) {
1841 if (!block_completed.at(i)) {
1842 BlockBegin* from_block = block_at(i);
1843 already_resolved.set_from(block_completed);
1844
1845 int num_sux = from_block->number_of_sux();
1846 for (int s = 0; s < num_sux; s++) {
1847 BlockBegin* to_block = from_block->sux_at(s);
1848
1849 // check for duplicate edges between the same blocks (can happen with switch blocks)
1850 if (!already_resolved.at(to_block->linear_scan_number())) {
1851 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1852 already_resolved.set_bit(to_block->linear_scan_number());
1853
1854 // collect all intervals that have been split between from_block and to_block
1855 resolve_collect_mappings(from_block, to_block, move_resolver);
1856 if (move_resolver.has_mappings()) {
1857 resolve_find_insert_pos(from_block, to_block, move_resolver);
1858 move_resolver.resolve_and_append_moves();
1859 }
1860 }
1861 }
1862 }
1863 }
1864 }
1865
1866
1867 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1868 if (interval_at(reg_num) == NULL) {
1869 // if a phi function is never used, no interval is created -> ignore this
1870 return;
1871 }
1872
1873 Interval* interval = interval_at_block_begin(block, reg_num);
1874 int reg = interval->assigned_reg();
1875 int regHi = interval->assigned_regHi();
1876
1877 if ((reg < nof_regs && interval->always_in_memory()) ||
1878 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1879 // the interval is split to get a short range that is located on the stack
1880 // in the following two cases:
1881 // * the interval started in memory (e.g. method parameter), but is currently in a register
1882 // this is an optimization for exception handling that reduces the number of moves that
1883 // are necessary for resolving the states when an exception uses this exception handler
1884 // * the interval would be on the fpu stack at the begin of the exception handler
1885 // this is not allowed because of the complicated fpu stack handling on Intel
1886
1887 // range that will be spilled to memory
1888 int from_op_id = block->first_lir_instruction_id();
1889 int to_op_id = from_op_id + 1; // short live range of length 1
1890 assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1891 "no split allowed between exception entry and first instruction");
1892
1893 if (interval->from() != from_op_id) {
1894 // the part before from_op_id is unchanged
1895 interval = interval->split(from_op_id);
1896 interval->assign_reg(reg, regHi);
1897 append_interval(interval);
1898 } else {
1899 _needs_full_resort = true;
1900 }
1901 assert(interval->from() == from_op_id, "must be true now");
1902
1903 Interval* spilled_part = interval;
1904 if (interval->to() != to_op_id) {
1905 // the part after to_op_id is unchanged
1906 spilled_part = interval->split_from_start(to_op_id);
1907 append_interval(spilled_part);
1908 move_resolver.add_mapping(spilled_part, interval);
1909 }
1910 assign_spill_slot(spilled_part);
1911
1912 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1913 }
1914 }
1915
1916 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1917 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1918 DEBUG_ONLY(move_resolver.check_empty());
1919
1920 // visit all registers where the live_in bit is set
1921 int size = live_set_size();
1922 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1923 resolve_exception_entry(block, r, move_resolver);
1924 }
1925
1926 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1927 for_each_phi_fun(block, phi,
1928 if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1929 );
1930
1931 if (move_resolver.has_mappings()) {
1932 // insert moves after first instruction
1933 move_resolver.set_insert_position(block->lir(), 0);
1934 move_resolver.resolve_and_append_moves();
1935 }
1936 }
1937
1938
1939 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1940 if (interval_at(reg_num) == NULL) {
1941 // if a phi function is never used, no interval is created -> ignore this
1942 return;
1943 }
1944
1945 // the computation of to_interval is equal to resolve_collect_mappings,
1946 // but from_interval is more complicated because of phi functions
1947 BlockBegin* to_block = handler->entry_block();
1948 Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1949
1950 if (phi != NULL) {
1951 // phi function of the exception entry block
1952 // no moves are created for this phi function in the LIR_Generator, so the
1953 // interval at the throwing instruction must be searched using the operands
1954 // of the phi function
1955 Value from_value = phi->operand_at(handler->phi_operand());
1956
1957 // with phi functions it can happen that the same from_value is used in
1958 // multiple mappings, so notify move-resolver that this is allowed
1959 move_resolver.set_multiple_reads_allowed();
1960
1961 Constant* con = from_value->as_Constant();
1962 if (con != NULL && (!con->is_pinned() || con->operand()->is_constant())) {
1963 // Need a mapping from constant to interval if unpinned (may have no register) or if the operand is a constant (no register).
1964 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1965 } else {
1966 // search split child at the throwing op_id
1967 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1968 move_resolver.add_mapping(from_interval, to_interval);
1969 }
1970 } else {
1971 // no phi function, so use reg_num also for from_interval
1972 // search split child at the throwing op_id
1973 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1974 if (from_interval != to_interval) {
1975 // optimization to reduce number of moves: when to_interval is on stack and
1976 // the stack slot is known to be always correct, then no move is necessary
1977 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1978 move_resolver.add_mapping(from_interval, to_interval);
1979 }
1980 }
1981 }
1982 }
1983
1984 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1985 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1986
1987 DEBUG_ONLY(move_resolver.check_empty());
1988 assert(handler->lir_op_id() == -1, "already processed this xhandler");
1989 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1990 assert(handler->entry_code() == NULL, "code already present");
1991
1992 // visit all registers where the live_in bit is set
1993 BlockBegin* block = handler->entry_block();
1994 int size = live_set_size();
1995 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1996 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1997 }
1998
1999 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
2000 for_each_phi_fun(block, phi,
2001 if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
2002 );
2003
2004 if (move_resolver.has_mappings()) {
2005 LIR_List* entry_code = new LIR_List(compilation());
2006 move_resolver.set_insert_position(entry_code, 0);
2007 move_resolver.resolve_and_append_moves();
2008
2009 entry_code->jump(handler->entry_block());
2010 handler->set_entry_code(entry_code);
2011 }
2012 }
2013
2014
2015 void LinearScan::resolve_exception_handlers() {
2016 MoveResolver move_resolver(this);
2017 LIR_OpVisitState visitor;
2018 int num_blocks = block_count();
2019
2020 int i;
2021 for (i = 0; i < num_blocks; i++) {
2022 BlockBegin* block = block_at(i);
2023 if (block->is_set(BlockBegin::exception_entry_flag)) {
2024 resolve_exception_entry(block, move_resolver);
2025 }
2026 }
2027
2028 for (i = 0; i < num_blocks; i++) {
2029 BlockBegin* block = block_at(i);
2030 LIR_List* ops = block->lir();
2031 int num_ops = ops->length();
2032
2033 // iterate all instructions of the block. skip the first because it is always a label
2034 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2035 for (int j = 1; j < num_ops; j++) {
2036 LIR_Op* op = ops->at(j);
2037 int op_id = op->id();
2038
2039 if (op_id != -1 && has_info(op_id)) {
2040 // visit operation to collect all operands
2041 visitor.visit(op);
2042 assert(visitor.info_count() > 0, "should not visit otherwise");
2043
2044 XHandlers* xhandlers = visitor.all_xhandler();
2045 int n = xhandlers->length();
2046 for (int k = 0; k < n; k++) {
2047 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2048 }
2049
2050 #ifdef ASSERT
2051 } else {
2052 visitor.visit(op);
2053 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2054 #endif
2055 }
2056 }
2057 }
2058 }
2059
2060
2061 // ********** Phase 7: assign register numbers back to LIR
2062 // (includes computation of debug information and oop maps)
2063
2064 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2065 VMReg reg = interval->cached_vm_reg();
2066 if (!reg->is_valid() ) {
2067 reg = vm_reg_for_operand(operand_for_interval(interval));
2068 interval->set_cached_vm_reg(reg);
2069 }
2070 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2071 return reg;
2072 }
2073
2074 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2075 assert(opr->is_oop(), "currently only implemented for oop operands");
2076 return frame_map()->regname(opr);
2077 }
2078
2079
2080 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2081 LIR_Opr opr = interval->cached_opr();
2082 if (opr->is_illegal()) {
2083 opr = calc_operand_for_interval(interval);
2084 interval->set_cached_opr(opr);
2085 }
2086
2087 assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2088 return opr;
2089 }
2090
2091 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2092 int assigned_reg = interval->assigned_reg();
2093 BasicType type = interval->type();
2094
2095 if (assigned_reg >= nof_regs) {
2096 // stack slot
2097 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2098 return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2099
2100 } else {
2101 // register
2102 switch (type) {
2103 case T_OBJECT: {
2104 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2105 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2106 return LIR_OprFact::single_cpu_oop(assigned_reg);
2107 }
2108
2109 case T_ADDRESS: {
2110 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2111 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2112 return LIR_OprFact::single_cpu_address(assigned_reg);
2113 }
2114
2115 case T_METADATA: {
2116 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2117 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2118 return LIR_OprFact::single_cpu_metadata(assigned_reg);
2119 }
2120
2121 #ifdef __SOFTFP__
2122 case T_FLOAT: // fall through
2123 #endif // __SOFTFP__
2124 case T_INT: {
2125 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2126 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2127 return LIR_OprFact::single_cpu(assigned_reg);
2128 }
2129
2130 #ifdef __SOFTFP__
2131 case T_DOUBLE: // fall through
2132 #endif // __SOFTFP__
2133 case T_LONG: {
2134 int assigned_regHi = interval->assigned_regHi();
2135 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2136 assert(num_physical_regs(T_LONG) == 1 ||
2137 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2138
2139 assert(assigned_reg != assigned_regHi, "invalid allocation");
2140 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2141 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2142 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2143 if (requires_adjacent_regs(T_LONG)) {
2144 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2145 }
2146
2147 #ifdef _LP64
2148 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2149 #else
2150 #if defined(PPC32)
2151 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2152 #else
2153 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2154 #endif // PPC32
2155 #endif // LP64
2156 }
2157
2158 #ifndef __SOFTFP__
2159 case T_FLOAT: {
2160 #ifdef X86
2161 if (UseSSE >= 1) {
2162 int last_xmm_reg = pd_last_xmm_reg;
2163 #ifdef _LP64
2164 if (UseAVX < 3) {
2165 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2166 }
2167 #endif // LP64
2168 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2169 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2170 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2171 }
2172 #endif // X86
2173
2174 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2175 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2176 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2177 }
2178
2179 case T_DOUBLE: {
2180 #ifdef X86
2181 if (UseSSE >= 2) {
2182 int last_xmm_reg = pd_last_xmm_reg;
2183 #ifdef _LP64
2184 if (UseAVX < 3) {
2185 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2186 }
2187 #endif // LP64
2188 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2189 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2190 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2191 }
2192 #endif // X86
2193
2194 #if defined(ARM32)
2195 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2196 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2197 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2198 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2199 #else
2200 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2201 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2202 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2203 #endif
2204 return result;
2205 }
2206 #endif // __SOFTFP__
2207
2208 default: {
2209 ShouldNotReachHere();
2210 return LIR_OprFact::illegalOpr;
2211 }
2212 }
2213 }
2214 }
2215
2216 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2217 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2218 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2219 }
2220
2221 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2222 assert(opr->is_virtual(), "should not call this otherwise");
2223
2224 Interval* interval = interval_at(opr->vreg_number());
2225 assert(interval != NULL, "interval must exist");
2226
2227 if (op_id != -1) {
2228 #ifdef ASSERT
2229 BlockBegin* block = block_of_op_with_id(op_id);
2230 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2231 // check if spill moves could have been appended at the end of this block, but
2232 // before the branch instruction. So the split child information for this branch would
2233 // be incorrect.
2234 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2235 if (branch != NULL) {
2236 if (block->live_out().at(opr->vreg_number())) {
2237 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2238 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2239 }
2240 }
2241 }
2242 #endif
2243
2244 // operands are not changed when an interval is split during allocation,
2245 // so search the right interval here
2246 interval = split_child_at_op_id(interval, op_id, mode);
2247 }
2248
2249 LIR_Opr res = operand_for_interval(interval);
2250
2251 #ifdef X86
2252 // new semantic for is_last_use: not only set on definite end of interval,
2253 // but also before hole
2254 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2255 // last use information is completely correct
2256 // information is only needed for fpu stack allocation
2257 if (res->is_fpu_register()) {
2258 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2259 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2260 res = res->make_last_use();
2261 }
2262 }
2263 #endif
2264
2265 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2266
2267 return res;
2268 }
2269
2270
2271 #ifdef ASSERT
2272 // some methods used to check correctness of debug information
2273
2274 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2275 if (values == NULL) {
2276 return;
2277 }
2278
2279 for (int i = 0; i < values->length(); i++) {
2280 ScopeValue* value = values->at(i);
2281
2282 if (value->is_location()) {
2283 Location location = ((LocationValue*)value)->location();
2284 assert(location.where() == Location::on_stack, "value is in register");
2285 }
2286 }
2287 }
2288
2289 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2290 if (values == NULL) {
2291 return;
2292 }
2293
2294 for (int i = 0; i < values->length(); i++) {
2295 MonitorValue* value = values->at(i);
2296
2297 if (value->owner()->is_location()) {
2298 Location location = ((LocationValue*)value->owner())->location();
2299 assert(location.where() == Location::on_stack, "owner is in register");
2300 }
2301 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2302 }
2303 }
2304
2305 void assert_equal(Location l1, Location l2) {
2306 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2307 }
2308
2309 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2310 if (v1->is_location()) {
2311 assert(v2->is_location(), "");
2312 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2313 } else if (v1->is_constant_int()) {
2314 assert(v2->is_constant_int(), "");
2315 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2316 } else if (v1->is_constant_double()) {
2317 assert(v2->is_constant_double(), "");
2318 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2319 } else if (v1->is_constant_long()) {
2320 assert(v2->is_constant_long(), "");
2321 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2322 } else if (v1->is_constant_oop()) {
2323 assert(v2->is_constant_oop(), "");
2324 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2325 } else {
2326 ShouldNotReachHere();
2327 }
2328 }
2329
2330 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2331 assert_equal(m1->owner(), m2->owner());
2332 assert_equal(m1->basic_lock(), m2->basic_lock());
2333 }
2334
2335 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2336 assert(d1->scope() == d2->scope(), "not equal");
2337 assert(d1->bci() == d2->bci(), "not equal");
2338
2339 if (d1->locals() != NULL) {
2340 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2341 assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2342 for (int i = 0; i < d1->locals()->length(); i++) {
2343 assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2344 }
2345 } else {
2346 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2347 }
2348
2349 if (d1->expressions() != NULL) {
2350 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2351 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2352 for (int i = 0; i < d1->expressions()->length(); i++) {
2353 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2354 }
2355 } else {
2356 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2357 }
2358
2359 if (d1->monitors() != NULL) {
2360 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2361 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2362 for (int i = 0; i < d1->monitors()->length(); i++) {
2363 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2364 }
2365 } else {
2366 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2367 }
2368
2369 if (d1->caller() != NULL) {
2370 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2371 assert_equal(d1->caller(), d2->caller());
2372 } else {
2373 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2374 }
2375 }
2376
2377 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2378 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2379 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2380 switch (code) {
2381 case Bytecodes::_ifnull : // fall through
2382 case Bytecodes::_ifnonnull : // fall through
2383 case Bytecodes::_ifeq : // fall through
2384 case Bytecodes::_ifne : // fall through
2385 case Bytecodes::_iflt : // fall through
2386 case Bytecodes::_ifge : // fall through
2387 case Bytecodes::_ifgt : // fall through
2388 case Bytecodes::_ifle : // fall through
2389 case Bytecodes::_if_icmpeq : // fall through
2390 case Bytecodes::_if_icmpne : // fall through
2391 case Bytecodes::_if_icmplt : // fall through
2392 case Bytecodes::_if_icmpge : // fall through
2393 case Bytecodes::_if_icmpgt : // fall through
2394 case Bytecodes::_if_icmple : // fall through
2395 case Bytecodes::_if_acmpeq : // fall through
2396 case Bytecodes::_if_acmpne :
2397 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2398 break;
2399 default:
2400 break;
2401 }
2402 }
2403 }
2404
2405 #endif // ASSERT
2406
2407
2408 IntervalWalker* LinearScan::init_compute_oop_maps() {
2409 // setup lists of potential oops for walking
2410 Interval* oop_intervals;
2411 Interval* non_oop_intervals;
2412
2413 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2414
2415 // intervals that have no oops inside need not to be processed
2416 // to ensure a walking until the last instruction id, add a dummy interval
2417 // with a high operation id
2418 non_oop_intervals = new Interval(any_reg);
2419 non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2420
2421 return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2422 }
2423
2424
2425 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2426 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2427
2428 // walk before the current operation -> intervals that start at
2429 // the operation (= output operands of the operation) are not
2430 // included in the oop map
2431 iw->walk_before(op->id());
2432
2433 int frame_size = frame_map()->framesize();
2434 int arg_count = frame_map()->oop_map_arg_count();
2435 OopMap* map = new OopMap(frame_size, arg_count);
2436
2437 // Iterate through active intervals
2438 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2439 int assigned_reg = interval->assigned_reg();
2440
2441 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2442 assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2443 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2444
2445 // Check if this range covers the instruction. Intervals that
2446 // start or end at the current operation are not included in the
2447 // oop map, except in the case of patching moves. For patching
2448 // moves, any intervals which end at this instruction are included
2449 // in the oop map since we may safepoint while doing the patch
2450 // before we've consumed the inputs.
2451 if (op->is_patching() || op->id() < interval->current_to()) {
2452
2453 // caller-save registers must not be included into oop-maps at calls
2454 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2455
2456 VMReg name = vm_reg_for_interval(interval);
2457 set_oop(map, name);
2458
2459 // Spill optimization: when the stack value is guaranteed to be always correct,
2460 // then it must be added to the oop map even if the interval is currently in a register
2461 if (interval->always_in_memory() &&
2462 op->id() > interval->spill_definition_pos() &&
2463 interval->assigned_reg() != interval->canonical_spill_slot()) {
2464 assert(interval->spill_definition_pos() > 0, "position not set correctly");
2465 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2466 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2467
2468 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2469 }
2470 }
2471 }
2472
2473 // add oops from lock stack
2474 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2475 int locks_count = info->stack()->total_locks_size();
2476 for (int i = 0; i < locks_count; i++) {
2477 set_oop(map, frame_map()->monitor_object_regname(i));
2478 }
2479
2480 return map;
2481 }
2482
2483
2484 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2485 assert(visitor.info_count() > 0, "no oop map needed");
2486
2487 // compute oop_map only for first CodeEmitInfo
2488 // because it is (in most cases) equal for all other infos of the same operation
2489 CodeEmitInfo* first_info = visitor.info_at(0);
2490 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2491
2492 for (int i = 0; i < visitor.info_count(); i++) {
2493 CodeEmitInfo* info = visitor.info_at(i);
2494 OopMap* oop_map = first_oop_map;
2495
2496 // compute worst case interpreter size in case of a deoptimization
2497 _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2498
2499 if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2500 // this info has a different number of locks then the precomputed oop map
2501 // (possible for lock and unlock instructions) -> compute oop map with
2502 // correct lock information
2503 oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2504 }
2505
2506 if (info->_oop_map == NULL) {
2507 info->_oop_map = oop_map;
2508 } else {
2509 // a CodeEmitInfo can not be shared between different LIR-instructions
2510 // because interval splitting can occur anywhere between two instructions
2511 // and so the oop maps must be different
2512 // -> check if the already set oop_map is exactly the one calculated for this operation
2513 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2514 }
2515 }
2516 }
2517
2518
2519 // frequently used constants
2520 // Allocate them with new so they are never destroyed (otherwise, a
2521 // forced exit could destroy these objects while they are still in
2522 // use).
2523 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2524 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2525 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue((jint)0);
2526 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2527 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2528 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2529
2530 void LinearScan::init_compute_debug_info() {
2531 // cache for frequently used scope values
2532 // (cpu registers and stack slots)
2533 int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2534 _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2535 }
2536
2537 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2538 Location loc;
2539 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2540 bailout("too large frame");
2541 }
2542 ScopeValue* object_scope_value = new LocationValue(loc);
2543
2544 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2545 bailout("too large frame");
2546 }
2547 return new MonitorValue(object_scope_value, loc);
2548 }
2549
2550 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2551 Location loc;
2552 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2553 bailout("too large frame");
2554 }
2555 return new LocationValue(loc);
2556 }
2557
2558
2559 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2560 assert(opr->is_constant(), "should not be called otherwise");
2561
2562 LIR_Const* c = opr->as_constant_ptr();
2563 BasicType t = c->type();
2564 switch (t) {
2565 case T_OBJECT: {
2566 jobject value = c->as_jobject();
2567 if (value == NULL) {
2568 scope_values->append(_oop_null_scope_value);
2569 } else {
2570 scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2571 }
2572 return 1;
2573 }
2574
2575 case T_INT: // fall through
2576 case T_FLOAT: {
2577 int value = c->as_jint_bits();
2578 switch (value) {
2579 case -1: scope_values->append(_int_m1_scope_value); break;
2580 case 0: scope_values->append(_int_0_scope_value); break;
2581 case 1: scope_values->append(_int_1_scope_value); break;
2582 case 2: scope_values->append(_int_2_scope_value); break;
2583 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2584 }
2585 return 1;
2586 }
2587
2588 case T_LONG: // fall through
2589 case T_DOUBLE: {
2590 #ifdef _LP64
2591 scope_values->append(_int_0_scope_value);
2592 scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2593 #else
2594 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2595 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2596 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2597 } else {
2598 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2599 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2600 }
2601 #endif
2602 return 2;
2603 }
2604
2605 case T_ADDRESS: {
2606 #ifdef _LP64
2607 scope_values->append(new ConstantLongValue(c->as_jint()));
2608 #else
2609 scope_values->append(new ConstantIntValue(c->as_jint()));
2610 #endif
2611 return 1;
2612 }
2613
2614 default:
2615 ShouldNotReachHere();
2616 return -1;
2617 }
2618 }
2619
2620 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2621 if (opr->is_single_stack()) {
2622 int stack_idx = opr->single_stack_ix();
2623 bool is_oop = opr->is_oop_register();
2624 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2625
2626 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2627 if (sv == NULL) {
2628 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2629 sv = location_for_name(stack_idx, loc_type);
2630 _scope_value_cache.at_put(cache_idx, sv);
2631 }
2632
2633 // check if cached value is correct
2634 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2635
2636 scope_values->append(sv);
2637 return 1;
2638
2639 } else if (opr->is_single_cpu()) {
2640 bool is_oop = opr->is_oop_register();
2641 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2642 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2643
2644 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2645 if (sv == NULL) {
2646 Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2647 VMReg rname = frame_map()->regname(opr);
2648 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2649 _scope_value_cache.at_put(cache_idx, sv);
2650 }
2651
2652 // check if cached value is correct
2653 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2654
2655 scope_values->append(sv);
2656 return 1;
2657
2658 #ifdef X86
2659 } else if (opr->is_single_xmm()) {
2660 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2661 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2662
2663 scope_values->append(sv);
2664 return 1;
2665 #endif
2666
2667 } else if (opr->is_single_fpu()) {
2668 #ifdef IA32
2669 // the exact location of fpu stack values is only known
2670 // during fpu stack allocation, so the stack allocator object
2671 // must be present
2672 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2673 assert(_fpu_stack_allocator != NULL, "must be present");
2674 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2675 #elif defined(AMD64)
2676 assert(false, "FPU not used on x86-64");
2677 #endif
2678
2679 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2680 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2681 #ifndef __SOFTFP__
2682 #ifndef VM_LITTLE_ENDIAN
2683 // On S390 a (single precision) float value occupies only the high
2684 // word of the full double register. So when the double register is
2685 // stored to memory (e.g. by the RegisterSaver), then the float value
2686 // is found at offset 0. I.e. the code below is not needed on S390.
2687 #ifndef S390
2688 if (! float_saved_as_double) {
2689 // On big endian system, we may have an issue if float registers use only
2690 // the low half of the (same) double registers.
2691 // Both the float and the double could have the same regnr but would correspond
2692 // to two different addresses once saved.
2693
2694 // get next safely (no assertion checks)
2695 VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2696 if (next->is_reg() &&
2697 (next->as_FloatRegister() == rname->as_FloatRegister())) {
2698 // the back-end does use the same numbering for the double and the float
2699 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2700 }
2701 }
2702 #endif // !S390
2703 #endif
2704 #endif
2705 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2706
2707 scope_values->append(sv);
2708 return 1;
2709
2710 } else {
2711 // double-size operands
2712
2713 ScopeValue* first;
2714 ScopeValue* second;
2715
2716 if (opr->is_double_stack()) {
2717 #ifdef _LP64
2718 Location loc1;
2719 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2720 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2721 bailout("too large frame");
2722 }
2723
2724 first = new LocationValue(loc1);
2725 second = _int_0_scope_value;
2726 #else
2727 Location loc1, loc2;
2728 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2729 bailout("too large frame");
2730 }
2731 first = new LocationValue(loc1);
2732 second = new LocationValue(loc2);
2733 #endif // _LP64
2734
2735 } else if (opr->is_double_cpu()) {
2736 #ifdef _LP64
2737 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2738 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2739 second = _int_0_scope_value;
2740 #else
2741 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2742 VMReg rname_second = opr->as_register_hi()->as_VMReg();
2743
2744 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2745 // lo/hi and swapped relative to first and second, so swap them
2746 VMReg tmp = rname_first;
2747 rname_first = rname_second;
2748 rname_second = tmp;
2749 }
2750
2751 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2752 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2753 #endif //_LP64
2754
2755
2756 #ifdef X86
2757 } else if (opr->is_double_xmm()) {
2758 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2759 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
2760 # ifdef _LP64
2761 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2762 second = _int_0_scope_value;
2763 # else
2764 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2765 // %%% This is probably a waste but we'll keep things as they were for now
2766 if (true) {
2767 VMReg rname_second = rname_first->next();
2768 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2769 }
2770 # endif
2771 #endif
2772
2773 } else if (opr->is_double_fpu()) {
2774 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2775 // the double as float registers in the native ordering. On X86,
2776 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2777 // the low-order word of the double and fpu_regnrLo + 1 is the
2778 // name for the other half. *first and *second must represent the
2779 // least and most significant words, respectively.
2780
2781 #ifdef IA32
2782 // the exact location of fpu stack values is only known
2783 // during fpu stack allocation, so the stack allocator object
2784 // must be present
2785 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2786 assert(_fpu_stack_allocator != NULL, "must be present");
2787 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2788
2789 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2790 #endif
2791 #ifdef AMD64
2792 assert(false, "FPU not used on x86-64");
2793 #endif
2794 #ifdef ARM32
2795 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2796 #endif
2797 #ifdef PPC32
2798 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2799 #endif
2800
2801 #ifdef VM_LITTLE_ENDIAN
2802 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2803 #else
2804 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2805 #endif
2806
2807 #ifdef _LP64
2808 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2809 second = _int_0_scope_value;
2810 #else
2811 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2812 // %%% This is probably a waste but we'll keep things as they were for now
2813 if (true) {
2814 VMReg rname_second = rname_first->next();
2815 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2816 }
2817 #endif
2818
2819 } else {
2820 ShouldNotReachHere();
2821 first = NULL;
2822 second = NULL;
2823 }
2824
2825 assert(first != NULL && second != NULL, "must be set");
2826 // The convention the interpreter uses is that the second local
2827 // holds the first raw word of the native double representation.
2828 // This is actually reasonable, since locals and stack arrays
2829 // grow downwards in all implementations.
2830 // (If, on some machine, the interpreter's Java locals or stack
2831 // were to grow upwards, the embedded doubles would be word-swapped.)
2832 scope_values->append(second);
2833 scope_values->append(first);
2834 return 2;
2835 }
2836 }
2837
2838
2839 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2840 if (value != NULL) {
2841 LIR_Opr opr = value->operand();
2842 Constant* con = value->as_Constant();
2843
2844 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2845 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2846
2847 if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2848 // Unpinned constants may have a virtual operand for a part of the lifetime
2849 // or may be illegal when it was optimized away,
2850 // so always use a constant operand
2851 opr = LIR_OprFact::value_type(con->type());
2852 }
2853 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2854
2855 if (opr->is_virtual()) {
2856 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2857
2858 BlockBegin* block = block_of_op_with_id(op_id);
2859 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2860 // generating debug information for the last instruction of a block.
2861 // if this instruction is a branch, spill moves are inserted before this branch
2862 // and so the wrong operand would be returned (spill moves at block boundaries are not
2863 // considered in the live ranges of intervals)
2864 // Solution: use the first op_id of the branch target block instead.
2865 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2866 if (block->live_out().at(opr->vreg_number())) {
2867 op_id = block->sux_at(0)->first_lir_instruction_id();
2868 mode = LIR_OpVisitState::outputMode;
2869 }
2870 }
2871 }
2872
2873 // Get current location of operand
2874 // The operand must be live because debug information is considered when building the intervals
2875 // if the interval is not live, color_lir_opr will cause an assertion failure
2876 opr = color_lir_opr(opr, op_id, mode);
2877 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2878
2879 // Append to ScopeValue array
2880 return append_scope_value_for_operand(opr, scope_values);
2881
2882 } else {
2883 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2884 assert(opr->is_constant(), "operand must be constant");
2885
2886 return append_scope_value_for_constant(opr, scope_values);
2887 }
2888 } else {
2889 // append a dummy value because real value not needed
2890 scope_values->append(_illegal_value);
2891 return 1;
2892 }
2893 }
2894
2895
2896 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2897 IRScopeDebugInfo* caller_debug_info = NULL;
2898
2899 ValueStack* caller_state = cur_state->caller_state();
2900 if (caller_state != NULL) {
2901 // process recursively to compute outermost scope first
2902 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2903 }
2904
2905 // initialize these to null.
2906 // If we don't need deopt info or there are no locals, expressions or monitors,
2907 // then these get recorded as no information and avoids the allocation of 0 length arrays.
2908 GrowableArray<ScopeValue*>* locals = NULL;
2909 GrowableArray<ScopeValue*>* expressions = NULL;
2910 GrowableArray<MonitorValue*>* monitors = NULL;
2911
2912 // describe local variable values
2913 int nof_locals = cur_state->locals_size();
2914 if (nof_locals > 0) {
2915 locals = new GrowableArray<ScopeValue*>(nof_locals);
2916
2917 int pos = 0;
2918 while (pos < nof_locals) {
2919 assert(pos < cur_state->locals_size(), "why not?");
2920
2921 Value local = cur_state->local_at(pos);
2922 pos += append_scope_value(op_id, local, locals);
2923
2924 assert(locals->length() == pos, "must match");
2925 }
2926 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2927 assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2928 } else if (cur_scope->method()->max_locals() > 0) {
2929 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2930 nof_locals = cur_scope->method()->max_locals();
2931 locals = new GrowableArray<ScopeValue*>(nof_locals);
2932 for(int i = 0; i < nof_locals; i++) {
2933 locals->append(_illegal_value);
2934 }
2935 }
2936
2937 // describe expression stack
2938 int nof_stack = cur_state->stack_size();
2939 if (nof_stack > 0) {
2940 expressions = new GrowableArray<ScopeValue*>(nof_stack);
2941
2942 int pos = 0;
2943 while (pos < nof_stack) {
2944 Value expression = cur_state->stack_at_inc(pos);
2945 append_scope_value(op_id, expression, expressions);
2946
2947 assert(expressions->length() == pos, "must match");
2948 }
2949 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2950 }
2951
2952 // describe monitors
2953 int nof_locks = cur_state->locks_size();
2954 if (nof_locks > 0) {
2955 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2956 monitors = new GrowableArray<MonitorValue*>(nof_locks);
2957 for (int i = 0; i < nof_locks; i++) {
2958 monitors->append(location_for_monitor_index(lock_offset + i));
2959 }
2960 }
2961
2962 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2963 }
2964
2965
2966 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2967 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2968
2969 IRScope* innermost_scope = info->scope();
2970 ValueStack* innermost_state = info->stack();
2971
2972 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2973
2974 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2975
2976 if (info->_scope_debug_info == NULL) {
2977 // compute debug information
2978 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2979 } else {
2980 // debug information already set. Check that it is correct from the current point of view
2981 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2982 }
2983 }
2984
2985
2986 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2987 LIR_OpVisitState visitor;
2988 int num_inst = instructions->length();
2989 bool has_dead = false;
2990
2991 for (int j = 0; j < num_inst; j++) {
2992 LIR_Op* op = instructions->at(j);
2993 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves
2994 has_dead = true;
2995 continue;
2996 }
2997 int op_id = op->id();
2998
2999 // visit instruction to get list of operands
3000 visitor.visit(op);
3001
3002 // iterate all modes of the visitor and process all virtual operands
3003 for_each_visitor_mode(mode) {
3004 int n = visitor.opr_count(mode);
3005 for (int k = 0; k < n; k++) {
3006 LIR_Opr opr = visitor.opr_at(mode, k);
3007 if (opr->is_virtual_register()) {
3008 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
3009 }
3010 }
3011 }
3012
3013 if (visitor.info_count() > 0) {
3014 // exception handling
3015 if (compilation()->has_exception_handlers()) {
3016 XHandlers* xhandlers = visitor.all_xhandler();
3017 int n = xhandlers->length();
3018 for (int k = 0; k < n; k++) {
3019 XHandler* handler = xhandlers->handler_at(k);
3020 if (handler->entry_code() != NULL) {
3021 assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3022 }
3023 }
3024 } else {
3025 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3026 }
3027
3028 // compute oop map
3029 assert(iw != NULL, "needed for compute_oop_map");
3030 compute_oop_map(iw, visitor, op);
3031
3032 // compute debug information
3033 if (!use_fpu_stack_allocation()) {
3034 // compute debug information if fpu stack allocation is not needed.
3035 // when fpu stack allocation is needed, the debug information can not
3036 // be computed here because the exact location of fpu operands is not known
3037 // -> debug information is created inside the fpu stack allocator
3038 int n = visitor.info_count();
3039 for (int k = 0; k < n; k++) {
3040 compute_debug_info(visitor.info_at(k), op_id);
3041 }
3042 }
3043 }
3044
3045 #ifdef ASSERT
3046 // make sure we haven't made the op invalid.
3047 op->verify();
3048 #endif
3049
3050 // remove useless moves
3051 if (op->code() == lir_move) {
3052 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3053 LIR_Op1* move = (LIR_Op1*)op;
3054 LIR_Opr src = move->in_opr();
3055 LIR_Opr dst = move->result_opr();
3056 if (dst == src ||
3057 (!dst->is_pointer() && !src->is_pointer() &&
3058 src->is_same_register(dst))) {
3059 instructions->at_put(j, NULL);
3060 has_dead = true;
3061 }
3062 }
3063 }
3064
3065 if (has_dead) {
3066 // iterate all instructions of the block and remove all null-values.
3067 int insert_point = 0;
3068 for (int j = 0; j < num_inst; j++) {
3069 LIR_Op* op = instructions->at(j);
3070 if (op != NULL) {
3071 if (insert_point != j) {
3072 instructions->at_put(insert_point, op);
3073 }
3074 insert_point++;
3075 }
3076 }
3077 instructions->trunc_to(insert_point);
3078 }
3079 }
3080
3081 void LinearScan::assign_reg_num() {
3082 TIME_LINEAR_SCAN(timer_assign_reg_num);
3083
3084 init_compute_debug_info();
3085 IntervalWalker* iw = init_compute_oop_maps();
3086
3087 int num_blocks = block_count();
3088 for (int i = 0; i < num_blocks; i++) {
3089 BlockBegin* block = block_at(i);
3090 assign_reg_num(block->lir()->instructions_list(), iw);
3091 }
3092 }
3093
3094
3095 void LinearScan::do_linear_scan() {
3096 NOT_PRODUCT(_total_timer.begin_method());
3097
3098 number_instructions();
3099
3100 NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3101
3102 compute_local_live_sets();
3103 compute_global_live_sets();
3104 CHECK_BAILOUT();
3105
3106 build_intervals();
3107 CHECK_BAILOUT();
3108 sort_intervals_before_allocation();
3109
3110 NOT_PRODUCT(print_intervals("Before Register Allocation"));
3111 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3112
3113 allocate_registers();
3114 CHECK_BAILOUT();
3115
3116 resolve_data_flow();
3117 if (compilation()->has_exception_handlers()) {
3118 resolve_exception_handlers();
3119 }
3120 // fill in number of spill slots into frame_map
3121 propagate_spill_slots();
3122 CHECK_BAILOUT();
3123
3124 NOT_PRODUCT(print_intervals("After Register Allocation"));
3125 NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3126
3127 sort_intervals_after_allocation();
3128
3129 DEBUG_ONLY(verify());
3130
3131 eliminate_spill_moves();
3132 assign_reg_num();
3133 CHECK_BAILOUT();
3134
3135 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3136 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3137
3138 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3139
3140 if (use_fpu_stack_allocation()) {
3141 allocate_fpu_stack(); // Only has effect on Intel
3142 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3143 }
3144 }
3145
3146 #ifndef RISCV
3147 // Disable these optimizations on riscv temporarily, because it does not
3148 // work when the comparison operands are bound to branches or cmoves.
3149 { TIME_LINEAR_SCAN(timer_optimize_lir);
3150
3151 EdgeMoveOptimizer::optimize(ir()->code());
3152 ControlFlowOptimizer::optimize(ir()->code());
3153 // check that cfg is still correct after optimizations
3154 ir()->verify();
3155 }
3156 #endif
3157
3158 NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3159 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3160 NOT_PRODUCT(_total_timer.end_method(this));
3161 }
3162
3163
3164 // ********** Printing functions
3165
3166 #ifndef PRODUCT
3167
3168 void LinearScan::print_timers(double total) {
3169 _total_timer.print(total);
3170 }
3171
3172 void LinearScan::print_statistics() {
3173 _stat_before_alloc.print("before allocation");
3174 _stat_after_asign.print("after assignment of register");
3175 _stat_final.print("after optimization");
3176 }
3177
3178 void LinearScan::print_bitmap(BitMap& b) {
3179 for (unsigned int i = 0; i < b.size(); i++) {
3180 if (b.at(i)) tty->print("%d ", i);
3181 }
3182 tty->cr();
3183 }
3184
3185 void LinearScan::print_intervals(const char* label) {
3186 if (TraceLinearScanLevel >= 1) {
3187 int i;
3188 tty->cr();
3189 tty->print_cr("%s", label);
3190
3191 for (i = 0; i < interval_count(); i++) {
3192 Interval* interval = interval_at(i);
3193 if (interval != NULL) {
3194 interval->print();
3195 }
3196 }
3197
3198 tty->cr();
3199 tty->print_cr("--- Basic Blocks ---");
3200 for (i = 0; i < block_count(); i++) {
3201 BlockBegin* block = block_at(i);
3202 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3203 }
3204 tty->cr();
3205 tty->cr();
3206 }
3207
3208 if (PrintCFGToFile) {
3209 CFGPrinter::print_intervals(&_intervals, label);
3210 }
3211 }
3212
3213 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3214 if (TraceLinearScanLevel >= level) {
3215 tty->cr();
3216 tty->print_cr("%s", label);
3217 print_LIR(ir()->linear_scan_order());
3218 tty->cr();
3219 }
3220
3221 if (level == 1 && PrintCFGToFile) {
3222 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3223 }
3224 }
3225
3226 void LinearScan::print_reg_num(outputStream* out, int reg_num) {
3227 if (reg_num == -1) {
3228 out->print("[ANY]");
3229 return;
3230 } else if (reg_num >= LIR_OprDesc::vreg_base) {
3231 out->print("[VREG %d]", reg_num);
3232 return;
3233 }
3234
3235 LIR_Opr opr = get_operand(reg_num);
3236 assert(opr->is_valid(), "unknown register");
3237 opr->print(out);
3238 }
3239
3240 LIR_Opr LinearScan::get_operand(int reg_num) {
3241 LIR_Opr opr = LIR_OprFact::illegal();
3242
3243 #ifdef X86
3244 int last_xmm_reg = pd_last_xmm_reg;
3245 #ifdef _LP64
3246 if (UseAVX < 3) {
3247 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
3248 }
3249 #endif
3250 #endif
3251 if (reg_num >= pd_first_cpu_reg && reg_num <= pd_last_cpu_reg) {
3252 opr = LIR_OprFact::single_cpu(reg_num);
3253 } else if (reg_num >= pd_first_fpu_reg && reg_num <= pd_last_fpu_reg) {
3254 opr = LIR_OprFact::single_fpu(reg_num - pd_first_fpu_reg);
3255 #ifdef X86
3256 } else if (reg_num >= pd_first_xmm_reg && reg_num <= last_xmm_reg) {
3257 opr = LIR_OprFact::single_xmm(reg_num - pd_first_xmm_reg);
3258 #endif
3259 } else {
3260 // reg_num == -1 or a virtual register, return the illegal operand
3261 }
3262 return opr;
3263 }
3264
3265 Interval* LinearScan::find_interval_at(int reg_num) const {
3266 if (reg_num < 0 || reg_num >= _intervals.length()) {
3267 return NULL;
3268 }
3269 return interval_at(reg_num);
3270 }
3271
3272 #endif // PRODUCT
3273
3274
3275 // ********** verification functions for allocation
3276 // (check that all intervals have a correct register and that no registers are overwritten)
3277 #ifdef ASSERT
3278
3279 void LinearScan::verify() {
3280 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3281 verify_intervals();
3282
3283 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3284 verify_no_oops_in_fixed_intervals();
3285
3286 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3287 verify_constants();
3288
3289 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3290 verify_registers();
3291
3292 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3293 }
3294
3295 void LinearScan::verify_intervals() {
3296 int len = interval_count();
3297 bool has_error = false;
3298
3299 for (int i = 0; i < len; i++) {
3300 Interval* i1 = interval_at(i);
3301 if (i1 == NULL) continue;
3302
3303 i1->check_split_children();
3304
3305 if (i1->reg_num() != i) {
3306 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3307 has_error = true;
3308 }
3309
3310 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3311 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3312 has_error = true;
3313 }
3314
3315 if (i1->assigned_reg() == any_reg) {
3316 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3317 has_error = true;
3318 }
3319
3320 if (i1->assigned_reg() == i1->assigned_regHi()) {
3321 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3322 has_error = true;
3323 }
3324
3325 if (!is_processed_reg_num(i1->assigned_reg())) {
3326 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3327 has_error = true;
3328 }
3329
3330 // special intervals that are created in MoveResolver
3331 // -> ignore them because the range information has no meaning there
3332 if (i1->from() == 1 && i1->to() == 2) continue;
3333
3334 if (i1->first() == Range::end()) {
3335 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3336 has_error = true;
3337 }
3338
3339 for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3340 if (r->from() >= r->to()) {
3341 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3342 has_error = true;
3343 }
3344 }
3345
3346 for (int j = i + 1; j < len; j++) {
3347 Interval* i2 = interval_at(j);
3348 if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3349
3350 int r1 = i1->assigned_reg();
3351 int r1Hi = i1->assigned_regHi();
3352 int r2 = i2->assigned_reg();
3353 int r2Hi = i2->assigned_regHi();
3354 if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3355 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3356 i1->print(); tty->cr();
3357 i2->print(); tty->cr();
3358 has_error = true;
3359 }
3360 }
3361 }
3362
3363 assert(has_error == false, "register allocation invalid");
3364 }
3365
3366
3367 void LinearScan::verify_no_oops_in_fixed_intervals() {
3368 Interval* fixed_intervals;
3369 Interval* other_intervals;
3370 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3371
3372 // to ensure a walking until the last instruction id, add a dummy interval
3373 // with a high operation id
3374 other_intervals = new Interval(any_reg);
3375 other_intervals->add_range(max_jint - 2, max_jint - 1);
3376 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3377
3378 LIR_OpVisitState visitor;
3379 for (int i = 0; i < block_count(); i++) {
3380 BlockBegin* block = block_at(i);
3381
3382 LIR_OpList* instructions = block->lir()->instructions_list();
3383
3384 for (int j = 0; j < instructions->length(); j++) {
3385 LIR_Op* op = instructions->at(j);
3386 int op_id = op->id();
3387
3388 visitor.visit(op);
3389
3390 if (visitor.info_count() > 0) {
3391 iw->walk_before(op->id());
3392 bool check_live = true;
3393 if (op->code() == lir_move) {
3394 LIR_Op1* move = (LIR_Op1*)op;
3395 check_live = (move->patch_code() == lir_patch_none);
3396 }
3397 LIR_OpBranch* branch = op->as_OpBranch();
3398 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3399 // Don't bother checking the stub in this case since the
3400 // exception stub will never return to normal control flow.
3401 check_live = false;
3402 }
3403
3404 // Make sure none of the fixed registers is live across an
3405 // oopmap since we can't handle that correctly.
3406 if (check_live) {
3407 for (Interval* interval = iw->active_first(fixedKind);
3408 interval != Interval::end();
3409 interval = interval->next()) {
3410 if (interval->current_to() > op->id() + 1) {
3411 // This interval is live out of this op so make sure
3412 // that this interval represents some value that's
3413 // referenced by this op either as an input or output.
3414 bool ok = false;
3415 for_each_visitor_mode(mode) {
3416 int n = visitor.opr_count(mode);
3417 for (int k = 0; k < n; k++) {
3418 LIR_Opr opr = visitor.opr_at(mode, k);
3419 if (opr->is_fixed_cpu()) {
3420 if (interval_at(reg_num(opr)) == interval) {
3421 ok = true;
3422 break;
3423 }
3424 int hi = reg_numHi(opr);
3425 if (hi != -1 && interval_at(hi) == interval) {
3426 ok = true;
3427 break;
3428 }
3429 }
3430 }
3431 }
3432 assert(ok, "fixed intervals should never be live across an oopmap point");
3433 }
3434 }
3435 }
3436 }
3437
3438 // oop-maps at calls do not contain registers, so check is not needed
3439 if (!visitor.has_call()) {
3440
3441 for_each_visitor_mode(mode) {
3442 int n = visitor.opr_count(mode);
3443 for (int k = 0; k < n; k++) {
3444 LIR_Opr opr = visitor.opr_at(mode, k);
3445
3446 if (opr->is_fixed_cpu() && opr->is_oop()) {
3447 // operand is a non-virtual cpu register and contains an oop
3448 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3449
3450 Interval* interval = interval_at(reg_num(opr));
3451 assert(interval != NULL, "no interval");
3452
3453 if (mode == LIR_OpVisitState::inputMode) {
3454 if (interval->to() >= op_id + 1) {
3455 assert(interval->to() < op_id + 2 ||
3456 interval->has_hole_between(op_id, op_id + 2),
3457 "oop input operand live after instruction");
3458 }
3459 } else if (mode == LIR_OpVisitState::outputMode) {
3460 if (interval->from() <= op_id - 1) {
3461 assert(interval->has_hole_between(op_id - 1, op_id),
3462 "oop input operand live after instruction");
3463 }
3464 }
3465 }
3466 }
3467 }
3468 }
3469 }
3470 }
3471 }
3472
3473
3474 void LinearScan::verify_constants() {
3475 int num_regs = num_virtual_regs();
3476 int size = live_set_size();
3477 int num_blocks = block_count();
3478
3479 for (int i = 0; i < num_blocks; i++) {
3480 BlockBegin* block = block_at(i);
3481 ResourceBitMap live_at_edge = block->live_in();
3482
3483 // visit all registers where the live_at_edge bit is set
3484 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3485 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3486
3487 Value value = gen()->instruction_for_vreg(r);
3488
3489 assert(value != NULL, "all intervals live across block boundaries must have Value");
3490 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3491 assert(value->operand()->vreg_number() == r, "register number must match");
3492 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3493 }
3494 }
3495 }
3496
3497
3498 class RegisterVerifier: public StackObj {
3499 private:
3500 LinearScan* _allocator;
3501 BlockList _work_list; // all blocks that must be processed
3502 IntervalsList _saved_states; // saved information of previous check
3503
3504 // simplified access to methods of LinearScan
3505 Compilation* compilation() const { return _allocator->compilation(); }
3506 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); }
3507 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); }
3508
3509 // currently, only registers are processed
3510 int state_size() { return LinearScan::nof_regs; }
3511
3512 // accessors
3513 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3514 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3515 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3516
3517 // helper functions
3518 IntervalList* copy(IntervalList* input_state);
3519 void state_put(IntervalList* input_state, int reg, Interval* interval);
3520 bool check_state(IntervalList* input_state, int reg, Interval* interval);
3521
3522 void process_block(BlockBegin* block);
3523 void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3524 void process_successor(BlockBegin* block, IntervalList* input_state);
3525 void process_operations(LIR_List* ops, IntervalList* input_state);
3526
3527 public:
3528 RegisterVerifier(LinearScan* allocator)
3529 : _allocator(allocator)
3530 , _work_list(16)
3531 , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3532 { }
3533
3534 void verify(BlockBegin* start);
3535 };
3536
3537
3538 // entry function from LinearScan that starts the verification
3539 void LinearScan::verify_registers() {
3540 RegisterVerifier verifier(this);
3541 verifier.verify(block_at(0));
3542 }
3543
3544
3545 void RegisterVerifier::verify(BlockBegin* start) {
3546 // setup input registers (method arguments) for first block
3547 int input_state_len = state_size();
3548 IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3549 CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3550 for (int n = 0; n < args->length(); n++) {
3551 LIR_Opr opr = args->at(n);
3552 if (opr->is_register()) {
3553 Interval* interval = interval_at(reg_num(opr));
3554
3555 if (interval->assigned_reg() < state_size()) {
3556 input_state->at_put(interval->assigned_reg(), interval);
3557 }
3558 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3559 input_state->at_put(interval->assigned_regHi(), interval);
3560 }
3561 }
3562 }
3563
3564 set_state_for_block(start, input_state);
3565 add_to_work_list(start);
3566
3567 // main loop for verification
3568 do {
3569 BlockBegin* block = _work_list.at(0);
3570 _work_list.remove_at(0);
3571
3572 process_block(block);
3573 } while (!_work_list.is_empty());
3574 }
3575
3576 void RegisterVerifier::process_block(BlockBegin* block) {
3577 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3578
3579 // must copy state because it is modified
3580 IntervalList* input_state = copy(state_for_block(block));
3581
3582 if (TraceLinearScanLevel >= 4) {
3583 tty->print_cr("Input-State of intervals:");
3584 tty->print(" ");
3585 for (int i = 0; i < state_size(); i++) {
3586 if (input_state->at(i) != NULL) {
3587 tty->print(" %4d", input_state->at(i)->reg_num());
3588 } else {
3589 tty->print(" __");
3590 }
3591 }
3592 tty->cr();
3593 tty->cr();
3594 }
3595
3596 // process all operations of the block
3597 process_operations(block->lir(), input_state);
3598
3599 // iterate all successors
3600 for (int i = 0; i < block->number_of_sux(); i++) {
3601 process_successor(block->sux_at(i), input_state);
3602 }
3603 }
3604
3605 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3606 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3607
3608 // must copy state because it is modified
3609 input_state = copy(input_state);
3610
3611 if (xhandler->entry_code() != NULL) {
3612 process_operations(xhandler->entry_code(), input_state);
3613 }
3614 process_successor(xhandler->entry_block(), input_state);
3615 }
3616
3617 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3618 IntervalList* saved_state = state_for_block(block);
3619
3620 if (saved_state != NULL) {
3621 // this block was already processed before.
3622 // check if new input_state is consistent with saved_state
3623
3624 bool saved_state_correct = true;
3625 for (int i = 0; i < state_size(); i++) {
3626 if (input_state->at(i) != saved_state->at(i)) {
3627 // current input_state and previous saved_state assume a different
3628 // interval in this register -> assume that this register is invalid
3629 if (saved_state->at(i) != NULL) {
3630 // invalidate old calculation only if it assumed that
3631 // register was valid. when the register was already invalid,
3632 // then the old calculation was correct.
3633 saved_state_correct = false;
3634 saved_state->at_put(i, NULL);
3635
3636 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3637 }
3638 }
3639 }
3640
3641 if (saved_state_correct) {
3642 // already processed block with correct input_state
3643 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3644 } else {
3645 // must re-visit this block
3646 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3647 add_to_work_list(block);
3648 }
3649
3650 } else {
3651 // block was not processed before, so set initial input_state
3652 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3653
3654 set_state_for_block(block, copy(input_state));
3655 add_to_work_list(block);
3656 }
3657 }
3658
3659
3660 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3661 IntervalList* copy_state = new IntervalList(input_state->length());
3662 copy_state->appendAll(input_state);
3663 return copy_state;
3664 }
3665
3666 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3667 if (reg != LinearScan::any_reg && reg < state_size()) {
3668 if (interval != NULL) {
3669 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num()));
3670 } else if (input_state->at(reg) != NULL) {
3671 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg));
3672 }
3673
3674 input_state->at_put(reg, interval);
3675 }
3676 }
3677
3678 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3679 if (reg != LinearScan::any_reg && reg < state_size()) {
3680 if (input_state->at(reg) != interval) {
3681 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3682 return true;
3683 }
3684 }
3685 return false;
3686 }
3687
3688 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3689 // visit all instructions of the block
3690 LIR_OpVisitState visitor;
3691 bool has_error = false;
3692
3693 for (int i = 0; i < ops->length(); i++) {
3694 LIR_Op* op = ops->at(i);
3695 visitor.visit(op);
3696
3697 TRACE_LINEAR_SCAN(4, op->print_on(tty));
3698
3699 // check if input operands are correct
3700 int j;
3701 int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3702 for (j = 0; j < n; j++) {
3703 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3704 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3705 Interval* interval = interval_at(reg_num(opr));
3706 if (op->id() != -1) {
3707 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3708 }
3709
3710 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent());
3711 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3712
3713 // When an operand is marked with is_last_use, then the fpu stack allocator
3714 // removes the register from the fpu stack -> the register contains no value
3715 if (opr->is_last_use()) {
3716 state_put(input_state, interval->assigned_reg(), NULL);
3717 state_put(input_state, interval->assigned_regHi(), NULL);
3718 }
3719 }
3720 }
3721
3722 // invalidate all caller save registers at calls
3723 if (visitor.has_call()) {
3724 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3725 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3726 }
3727 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3728 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3729 }
3730
3731 #ifdef X86
3732 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3733 for (j = 0; j < num_caller_save_xmm_regs; j++) {
3734 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3735 }
3736 #endif
3737 }
3738
3739 // process xhandler before output and temp operands
3740 XHandlers* xhandlers = visitor.all_xhandler();
3741 n = xhandlers->length();
3742 for (int k = 0; k < n; k++) {
3743 process_xhandler(xhandlers->handler_at(k), input_state);
3744 }
3745
3746 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3747 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3748 for (j = 0; j < n; j++) {
3749 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3750 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3751 Interval* interval = interval_at(reg_num(opr));
3752 if (op->id() != -1) {
3753 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3754 }
3755
3756 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3757 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3758 }
3759 }
3760
3761 // set output operands
3762 n = visitor.opr_count(LIR_OpVisitState::outputMode);
3763 for (j = 0; j < n; j++) {
3764 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3765 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3766 Interval* interval = interval_at(reg_num(opr));
3767 if (op->id() != -1) {
3768 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3769 }
3770
3771 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3772 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3773 }
3774 }
3775 }
3776 assert(has_error == false, "Error in register allocation");
3777 }
3778
3779 #endif // ASSERT
3780
3781
3782
3783 // **** Implementation of MoveResolver ******************************
3784
3785 MoveResolver::MoveResolver(LinearScan* allocator) :
3786 _allocator(allocator),
3787 _insert_list(NULL),
3788 _insert_idx(-1),
3789 _insertion_buffer(),
3790 _mapping_from(8),
3791 _mapping_from_opr(8),
3792 _mapping_to(8),
3793 _multiple_reads_allowed(false)
3794 {
3795 for (int i = 0; i < LinearScan::nof_regs; i++) {
3796 _register_blocked[i] = 0;
3797 }
3798 DEBUG_ONLY(check_empty());
3799 }
3800
3801
3802 #ifdef ASSERT
3803
3804 void MoveResolver::check_empty() {
3805 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3806 for (int i = 0; i < LinearScan::nof_regs; i++) {
3807 assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3808 }
3809 assert(_multiple_reads_allowed == false, "must have default value");
3810 }
3811
3812 void MoveResolver::verify_before_resolve() {
3813 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3814 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3815 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3816
3817 int i, j;
3818 if (!_multiple_reads_allowed) {
3819 for (i = 0; i < _mapping_from.length(); i++) {
3820 for (j = i + 1; j < _mapping_from.length(); j++) {
3821 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3822 }
3823 }
3824 }
3825
3826 for (i = 0; i < _mapping_to.length(); i++) {
3827 for (j = i + 1; j < _mapping_to.length(); j++) {
3828 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3829 }
3830 }
3831
3832
3833 ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3834 if (!_multiple_reads_allowed) {
3835 for (i = 0; i < _mapping_from.length(); i++) {
3836 Interval* it = _mapping_from.at(i);
3837 if (it != NULL) {
3838 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3839 used_regs.set_bit(it->assigned_reg());
3840
3841 if (it->assigned_regHi() != LinearScan::any_reg) {
3842 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3843 used_regs.set_bit(it->assigned_regHi());
3844 }
3845 }
3846 }
3847 }
3848
3849 used_regs.clear();
3850 for (i = 0; i < _mapping_to.length(); i++) {
3851 Interval* it = _mapping_to.at(i);
3852 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3853 used_regs.set_bit(it->assigned_reg());
3854
3855 if (it->assigned_regHi() != LinearScan::any_reg) {
3856 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3857 used_regs.set_bit(it->assigned_regHi());
3858 }
3859 }
3860
3861 used_regs.clear();
3862 for (i = 0; i < _mapping_from.length(); i++) {
3863 Interval* it = _mapping_from.at(i);
3864 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3865 used_regs.set_bit(it->assigned_reg());
3866 }
3867 }
3868 for (i = 0; i < _mapping_to.length(); i++) {
3869 Interval* it = _mapping_to.at(i);
3870 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3871 }
3872 }
3873
3874 #endif // ASSERT
3875
3876
3877 // mark assigned_reg and assigned_regHi of the interval as blocked
3878 void MoveResolver::block_registers(Interval* it) {
3879 int reg = it->assigned_reg();
3880 if (reg < LinearScan::nof_regs) {
3881 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3882 set_register_blocked(reg, 1);
3883 }
3884 reg = it->assigned_regHi();
3885 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3886 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3887 set_register_blocked(reg, 1);
3888 }
3889 }
3890
3891 // mark assigned_reg and assigned_regHi of the interval as unblocked
3892 void MoveResolver::unblock_registers(Interval* it) {
3893 int reg = it->assigned_reg();
3894 if (reg < LinearScan::nof_regs) {
3895 assert(register_blocked(reg) > 0, "register already marked as unused");
3896 set_register_blocked(reg, -1);
3897 }
3898 reg = it->assigned_regHi();
3899 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3900 assert(register_blocked(reg) > 0, "register already marked as unused");
3901 set_register_blocked(reg, -1);
3902 }
3903 }
3904
3905 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3906 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3907 int from_reg = -1;
3908 int from_regHi = -1;
3909 if (from != NULL) {
3910 from_reg = from->assigned_reg();
3911 from_regHi = from->assigned_regHi();
3912 }
3913
3914 int reg = to->assigned_reg();
3915 if (reg < LinearScan::nof_regs) {
3916 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3917 return false;
3918 }
3919 }
3920 reg = to->assigned_regHi();
3921 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3922 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3923 return false;
3924 }
3925 }
3926
3927 return true;
3928 }
3929
3930
3931 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3932 assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3933 _insertion_buffer.init(list);
3934 }
3935
3936 void MoveResolver::append_insertion_buffer() {
3937 if (_insertion_buffer.initialized()) {
3938 _insertion_buffer.lir_list()->append(&_insertion_buffer);
3939 }
3940 assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3941
3942 _insert_list = NULL;
3943 _insert_idx = -1;
3944 }
3945
3946 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3947 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3948 assert(from_interval->type() == to_interval->type(), "move between different types");
3949 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3950 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3951
3952 LIR_Opr from_opr = get_virtual_register(from_interval);
3953 LIR_Opr to_opr = get_virtual_register(to_interval);
3954
3955 if (!_multiple_reads_allowed) {
3956 // the last_use flag is an optimization for FPU stack allocation. When the same
3957 // input interval is used in more than one move, then it is too difficult to determine
3958 // if this move is really the last use.
3959 from_opr = from_opr->make_last_use();
3960 }
3961 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3962
3963 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3964 }
3965
3966 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3967 assert(from_opr->type() == to_interval->type(), "move between different types");
3968 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3969 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3970
3971 LIR_Opr to_opr = get_virtual_register(to_interval);
3972 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3973
3974 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3975 }
3976
3977 LIR_Opr MoveResolver::get_virtual_register(Interval* interval) {
3978 // Add a little fudge factor for the bailout since the bailout is only checked periodically. This allows us to hand out
3979 // a few extra registers before we really run out which helps to avoid to trip over assertions.
3980 int reg_num = interval->reg_num();
3981 if (reg_num + 20 >= LIR_OprDesc::vreg_max) {
3982 _allocator->bailout("out of virtual registers in linear scan");
3983 if (reg_num + 2 >= LIR_OprDesc::vreg_max) {
3984 // Wrap it around and continue until bailout really happens to avoid hitting assertions.
3985 reg_num = LIR_OprDesc::vreg_base;
3986 }
3987 }
3988 LIR_Opr vreg = LIR_OprFact::virtual_register(reg_num, interval->type());
3989 assert(vreg != LIR_OprFact::illegal(), "ran out of virtual registers");
3990 return vreg;
3991 }
3992
3993 void MoveResolver::resolve_mappings() {
3994 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3995 DEBUG_ONLY(verify_before_resolve());
3996
3997 // Block all registers that are used as input operands of a move.
3998 // When a register is blocked, no move to this register is emitted.
3999 // This is necessary for detecting cycles in moves.
4000 int i;
4001 for (i = _mapping_from.length() - 1; i >= 0; i--) {
4002 Interval* from_interval = _mapping_from.at(i);
4003 if (from_interval != NULL) {
4004 block_registers(from_interval);
4005 }
4006 }
4007
4008 int spill_candidate = -1;
4009 while (_mapping_from.length() > 0) {
4010 bool processed_interval = false;
4011
4012 for (i = _mapping_from.length() - 1; i >= 0; i--) {
4013 Interval* from_interval = _mapping_from.at(i);
4014 Interval* to_interval = _mapping_to.at(i);
4015
4016 if (save_to_process_move(from_interval, to_interval)) {
4017 // this inverval can be processed because target is free
4018 if (from_interval != NULL) {
4019 insert_move(from_interval, to_interval);
4020 unblock_registers(from_interval);
4021 } else {
4022 insert_move(_mapping_from_opr.at(i), to_interval);
4023 }
4024 _mapping_from.remove_at(i);
4025 _mapping_from_opr.remove_at(i);
4026 _mapping_to.remove_at(i);
4027
4028 processed_interval = true;
4029 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
4030 // this interval cannot be processed now because target is not free
4031 // it starts in a register, so it is a possible candidate for spilling
4032 spill_candidate = i;
4033 }
4034 }
4035
4036 if (!processed_interval) {
4037 // no move could be processed because there is a cycle in the move list
4038 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
4039 guarantee(spill_candidate != -1, "no interval in register for spilling found");
4040
4041 // create a new spill interval and assign a stack slot to it
4042 Interval* from_interval = _mapping_from.at(spill_candidate);
4043 Interval* spill_interval = new Interval(-1);
4044 spill_interval->set_type(from_interval->type());
4045
4046 // add a dummy range because real position is difficult to calculate
4047 // Note: this range is a special case when the integrity of the allocation is checked
4048 spill_interval->add_range(1, 2);
4049
4050 // do not allocate a new spill slot for temporary interval, but
4051 // use spill slot assigned to from_interval. Otherwise moves from
4052 // one stack slot to another can happen (not allowed by LIR_Assembler
4053 int spill_slot = from_interval->canonical_spill_slot();
4054 if (spill_slot < 0) {
4055 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
4056 from_interval->set_canonical_spill_slot(spill_slot);
4057 }
4058 spill_interval->assign_reg(spill_slot);
4059 allocator()->append_interval(spill_interval);
4060
4061 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
4062
4063 // insert a move from register to stack and update the mapping
4064 insert_move(from_interval, spill_interval);
4065 _mapping_from.at_put(spill_candidate, spill_interval);
4066 unblock_registers(from_interval);
4067 }
4068 }
4069
4070 // reset to default value
4071 _multiple_reads_allowed = false;
4072
4073 // check that all intervals have been processed
4074 DEBUG_ONLY(check_empty());
4075 }
4076
4077
4078 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4079 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4080 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4081
4082 create_insertion_buffer(insert_list);
4083 _insert_list = insert_list;
4084 _insert_idx = insert_idx;
4085 }
4086
4087 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4088 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4089
4090 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4091 // insert position changed -> resolve current mappings
4092 resolve_mappings();
4093 }
4094
4095 if (insert_list != _insert_list) {
4096 // block changed -> append insertion_buffer because it is
4097 // bound to a specific block and create a new insertion_buffer
4098 append_insertion_buffer();
4099 create_insertion_buffer(insert_list);
4100 }
4101
4102 _insert_list = insert_list;
4103 _insert_idx = insert_idx;
4104 }
4105
4106 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4107 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4108
4109 _mapping_from.append(from_interval);
4110 _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4111 _mapping_to.append(to_interval);
4112 }
4113
4114
4115 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4116 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4117 assert(from_opr->is_constant(), "only for constants");
4118
4119 _mapping_from.append(NULL);
4120 _mapping_from_opr.append(from_opr);
4121 _mapping_to.append(to_interval);
4122 }
4123
4124 void MoveResolver::resolve_and_append_moves() {
4125 if (has_mappings()) {
4126 resolve_mappings();
4127 }
4128 append_insertion_buffer();
4129 }
4130
4131
4132
4133 // **** Implementation of Range *************************************
4134
4135 Range::Range(int from, int to, Range* next) :
4136 _from(from),
4137 _to(to),
4138 _next(next)
4139 {
4140 }
4141
4142 // initialize sentinel
4143 Range* Range::_end = NULL;
4144 void Range::initialize(Arena* arena) {
4145 _end = new (arena) Range(max_jint, max_jint, NULL);
4146 }
4147
4148 int Range::intersects_at(Range* r2) const {
4149 const Range* r1 = this;
4150
4151 assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4152 assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4153
4154 do {
4155 if (r1->from() < r2->from()) {
4156 if (r1->to() <= r2->from()) {
4157 r1 = r1->next(); if (r1 == _end) return -1;
4158 } else {
4159 return r2->from();
4160 }
4161 } else if (r2->from() < r1->from()) {
4162 if (r2->to() <= r1->from()) {
4163 r2 = r2->next(); if (r2 == _end) return -1;
4164 } else {
4165 return r1->from();
4166 }
4167 } else { // r1->from() == r2->from()
4168 if (r1->from() == r1->to()) {
4169 r1 = r1->next(); if (r1 == _end) return -1;
4170 } else if (r2->from() == r2->to()) {
4171 r2 = r2->next(); if (r2 == _end) return -1;
4172 } else {
4173 return r1->from();
4174 }
4175 }
4176 } while (true);
4177 }
4178
4179 #ifndef PRODUCT
4180 void Range::print(outputStream* out) const {
4181 out->print("[%d, %d[ ", _from, _to);
4182 }
4183 #endif
4184
4185
4186
4187 // **** Implementation of Interval **********************************
4188
4189 // initialize sentinel
4190 Interval* Interval::_end = NULL;
4191 void Interval::initialize(Arena* arena) {
4192 Range::initialize(arena);
4193 _end = new (arena) Interval(-1);
4194 }
4195
4196 Interval::Interval(int reg_num) :
4197 _reg_num(reg_num),
4198 _type(T_ILLEGAL),
4199 _first(Range::end()),
4200 _use_pos_and_kinds(12),
4201 _current(Range::end()),
4202 _next(_end),
4203 _state(invalidState),
4204 _assigned_reg(LinearScan::any_reg),
4205 _assigned_regHi(LinearScan::any_reg),
4206 _cached_to(-1),
4207 _cached_opr(LIR_OprFact::illegalOpr),
4208 _cached_vm_reg(VMRegImpl::Bad()),
4209 _split_children(NULL),
4210 _canonical_spill_slot(-1),
4211 _insert_move_when_activated(false),
4212 _spill_state(noDefinitionFound),
4213 _spill_definition_pos(-1),
4214 _register_hint(NULL)
4215 {
4216 _split_parent = this;
4217 _current_split_child = this;
4218 }
4219
4220 int Interval::calc_to() {
4221 assert(_first != Range::end(), "interval has no range");
4222
4223 Range* r = _first;
4224 while (r->next() != Range::end()) {
4225 r = r->next();
4226 }
4227 return r->to();
4228 }
4229
4230
4231 #ifdef ASSERT
4232 // consistency check of split-children
4233 void Interval::check_split_children() {
4234 if (_split_children != NULL && _split_children->length() > 0) {
4235 assert(is_split_parent(), "only split parents can have children");
4236
4237 for (int i = 0; i < _split_children->length(); i++) {
4238 Interval* i1 = _split_children->at(i);
4239
4240 assert(i1->split_parent() == this, "not a split child of this interval");
4241 assert(i1->type() == type(), "must be equal for all split children");
4242 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4243
4244 for (int j = i + 1; j < _split_children->length(); j++) {
4245 Interval* i2 = _split_children->at(j);
4246
4247 assert(i1->reg_num() != i2->reg_num(), "same register number");
4248
4249 if (i1->from() < i2->from()) {
4250 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4251 } else {
4252 assert(i2->from() < i1->from(), "intervals start at same op_id");
4253 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4254 }
4255 }
4256 }
4257 }
4258 }
4259 #endif // ASSERT
4260
4261 Interval* Interval::register_hint(bool search_split_child) const {
4262 if (!search_split_child) {
4263 return _register_hint;
4264 }
4265
4266 if (_register_hint != NULL) {
4267 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4268
4269 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4270 return _register_hint;
4271
4272 } else if (_register_hint->_split_children != NULL && _register_hint->_split_children->length() > 0) {
4273 // search the first split child that has a register assigned
4274 int len = _register_hint->_split_children->length();
4275 for (int i = 0; i < len; i++) {
4276 Interval* cur = _register_hint->_split_children->at(i);
4277
4278 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4279 return cur;
4280 }
4281 }
4282 }
4283 }
4284
4285 // no hint interval found that has a register assigned
4286 return NULL;
4287 }
4288
4289
4290 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4291 assert(is_split_parent(), "can only be called for split parents");
4292 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4293
4294 Interval* result;
4295 if (_split_children == NULL || _split_children->length() == 0) {
4296 result = this;
4297 } else {
4298 result = NULL;
4299 int len = _split_children->length();
4300
4301 // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4302 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4303
4304 int i;
4305 for (i = 0; i < len; i++) {
4306 Interval* cur = _split_children->at(i);
4307 if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4308 if (i > 0) {
4309 // exchange current split child to start of list (faster access for next call)
4310 _split_children->at_put(i, _split_children->at(0));
4311 _split_children->at_put(0, cur);
4312 }
4313
4314 // interval found
4315 result = cur;
4316 break;
4317 }
4318 }
4319
4320 #ifdef ASSERT
4321 for (i = 0; i < len; i++) {
4322 Interval* tmp = _split_children->at(i);
4323 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4324 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4325 result->print();
4326 tmp->print();
4327 assert(false, "two valid result intervals found");
4328 }
4329 }
4330 #endif
4331 }
4332
4333 assert(result != NULL, "no matching interval found");
4334 assert(result->covers(op_id, mode), "op_id not covered by interval");
4335
4336 return result;
4337 }
4338
4339
4340 // returns the last split child that ends before the given op_id
4341 Interval* Interval::split_child_before_op_id(int op_id) {
4342 assert(op_id >= 0, "invalid op_id");
4343
4344 Interval* parent = split_parent();
4345 Interval* result = NULL;
4346
4347 assert(parent->_split_children != NULL, "no split children available");
4348 int len = parent->_split_children->length();
4349 assert(len > 0, "no split children available");
4350
4351 for (int i = len - 1; i >= 0; i--) {
4352 Interval* cur = parent->_split_children->at(i);
4353 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4354 result = cur;
4355 }
4356 }
4357
4358 assert(result != NULL, "no split child found");
4359 return result;
4360 }
4361
4362
4363 // Note: use positions are sorted descending -> first use has highest index
4364 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4365 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4366
4367 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4368 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4369 return _use_pos_and_kinds.at(i);
4370 }
4371 }
4372 return max_jint;
4373 }
4374
4375 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4376 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4377
4378 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4379 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4380 return _use_pos_and_kinds.at(i);
4381 }
4382 }
4383 return max_jint;
4384 }
4385
4386 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4387 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4388
4389 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4390 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4391 return _use_pos_and_kinds.at(i);
4392 }
4393 }
4394 return max_jint;
4395 }
4396
4397 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4398 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4399
4400 int prev = 0;
4401 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4402 if (_use_pos_and_kinds.at(i) > from) {
4403 return prev;
4404 }
4405 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4406 prev = _use_pos_and_kinds.at(i);
4407 }
4408 }
4409 return prev;
4410 }
4411
4412 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4413 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4414
4415 // do not add use positions for precolored intervals because
4416 // they are never used
4417 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4418 #ifdef ASSERT
4419 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4420 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4421 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4422 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4423 if (i > 0) {
4424 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4425 }
4426 }
4427 #endif
4428
4429 // Note: add_use is called in descending order, so list gets sorted
4430 // automatically by just appending new use positions
4431 int len = _use_pos_and_kinds.length();
4432 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4433 _use_pos_and_kinds.append(pos);
4434 _use_pos_and_kinds.append(use_kind);
4435 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4436 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4437 _use_pos_and_kinds.at_put(len - 1, use_kind);
4438 }
4439 }
4440 }
4441
4442 void Interval::add_range(int from, int to) {
4443 assert(from < to, "invalid range");
4444 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4445 assert(from <= first()->to(), "not inserting at begin of interval");
4446
4447 if (first()->from() <= to) {
4448 // join intersecting ranges
4449 first()->set_from(MIN2(from, first()->from()));
4450 first()->set_to (MAX2(to, first()->to()));
4451 } else {
4452 // insert new range
4453 _first = new Range(from, to, first());
4454 }
4455 }
4456
4457 Interval* Interval::new_split_child() {
4458 // allocate new interval
4459 Interval* result = new Interval(-1);
4460 result->set_type(type());
4461
4462 Interval* parent = split_parent();
4463 result->_split_parent = parent;
4464 result->set_register_hint(parent);
4465
4466 // insert new interval in children-list of parent
4467 if (parent->_split_children == NULL) {
4468 assert(is_split_parent(), "list must be initialized at first split");
4469
4470 parent->_split_children = new IntervalList(4);
4471 parent->_split_children->append(this);
4472 }
4473 parent->_split_children->append(result);
4474
4475 return result;
4476 }
4477
4478 // split this interval at the specified position and return
4479 // the remainder as a new interval.
4480 //
4481 // when an interval is split, a bi-directional link is established between the original interval
4482 // (the split parent) and the intervals that are split off this interval (the split children)
4483 // When a split child is split again, the new created interval is also a direct child
4484 // of the original parent (there is no tree of split children stored, but a flat list)
4485 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4486 //
4487 // Note: The new interval has no valid reg_num
4488 Interval* Interval::split(int split_pos) {
4489 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4490
4491 // allocate new interval
4492 Interval* result = new_split_child();
4493
4494 // split the ranges
4495 Range* prev = NULL;
4496 Range* cur = _first;
4497 while (cur != Range::end() && cur->to() <= split_pos) {
4498 prev = cur;
4499 cur = cur->next();
4500 }
4501 assert(cur != Range::end(), "split interval after end of last range");
4502
4503 if (cur->from() < split_pos) {
4504 result->_first = new Range(split_pos, cur->to(), cur->next());
4505 cur->set_to(split_pos);
4506 cur->set_next(Range::end());
4507
4508 } else {
4509 assert(prev != NULL, "split before start of first range");
4510 result->_first = cur;
4511 prev->set_next(Range::end());
4512 }
4513 result->_current = result->_first;
4514 _cached_to = -1; // clear cached value
4515
4516 // split list of use positions
4517 int total_len = _use_pos_and_kinds.length();
4518 int start_idx = total_len - 2;
4519 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4520 start_idx -= 2;
4521 }
4522
4523 intStack new_use_pos_and_kinds(total_len - start_idx);
4524 int i;
4525 for (i = start_idx + 2; i < total_len; i++) {
4526 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4527 }
4528
4529 _use_pos_and_kinds.trunc_to(start_idx + 2);
4530 result->_use_pos_and_kinds = _use_pos_and_kinds;
4531 _use_pos_and_kinds = new_use_pos_and_kinds;
4532
4533 #ifdef ASSERT
4534 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4535 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4536 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4537
4538 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4539 assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4540 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4541 }
4542 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4543 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4544 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4545 }
4546 #endif
4547
4548 return result;
4549 }
4550
4551 // split this interval at the specified position and return
4552 // the head as a new interval (the original interval is the tail)
4553 //
4554 // Currently, only the first range can be split, and the new interval
4555 // must not have split positions
4556 Interval* Interval::split_from_start(int split_pos) {
4557 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4558 assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4559 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4560 assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4561
4562 // allocate new interval
4563 Interval* result = new_split_child();
4564
4565 // the new created interval has only one range (checked by assertion above),
4566 // so the splitting of the ranges is very simple
4567 result->add_range(_first->from(), split_pos);
4568
4569 if (split_pos == _first->to()) {
4570 assert(_first->next() != Range::end(), "must not be at end");
4571 _first = _first->next();
4572 } else {
4573 _first->set_from(split_pos);
4574 }
4575
4576 return result;
4577 }
4578
4579
4580 // returns true if the op_id is inside the interval
4581 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4582 Range* cur = _first;
4583
4584 while (cur != Range::end() && cur->to() < op_id) {
4585 cur = cur->next();
4586 }
4587 if (cur != Range::end()) {
4588 assert(cur->to() != cur->next()->from(), "ranges not separated");
4589
4590 if (mode == LIR_OpVisitState::outputMode) {
4591 return cur->from() <= op_id && op_id < cur->to();
4592 } else {
4593 return cur->from() <= op_id && op_id <= cur->to();
4594 }
4595 }
4596 return false;
4597 }
4598
4599 // returns true if the interval has any hole between hole_from and hole_to
4600 // (even if the hole has only the length 1)
4601 bool Interval::has_hole_between(int hole_from, int hole_to) {
4602 assert(hole_from < hole_to, "check");
4603 assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4604
4605 Range* cur = _first;
4606 while (cur != Range::end()) {
4607 assert(cur->to() < cur->next()->from(), "no space between ranges");
4608
4609 // hole-range starts before this range -> hole
4610 if (hole_from < cur->from()) {
4611 return true;
4612
4613 // hole-range completely inside this range -> no hole
4614 } else if (hole_to <= cur->to()) {
4615 return false;
4616
4617 // overlapping of hole-range with this range -> hole
4618 } else if (hole_from <= cur->to()) {
4619 return true;
4620 }
4621
4622 cur = cur->next();
4623 }
4624
4625 return false;
4626 }
4627
4628 // Check if there is an intersection with any of the split children of 'interval'
4629 bool Interval::intersects_any_children_of(Interval* interval) const {
4630 if (interval->_split_children != NULL) {
4631 for (int i = 0; i < interval->_split_children->length(); i++) {
4632 if (intersects(interval->_split_children->at(i))) {
4633 return true;
4634 }
4635 }
4636 }
4637 return false;
4638 }
4639
4640
4641 #ifndef PRODUCT
4642 void Interval::print_on(outputStream* out, bool is_cfg_printer) const {
4643 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4644 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4645
4646 const char* type_name;
4647 if (reg_num() < LIR_OprDesc::vreg_base) {
4648 type_name = "fixed";
4649 } else {
4650 type_name = type2name(type());
4651 }
4652 out->print("%d %s ", reg_num(), type_name);
4653
4654 if (is_cfg_printer) {
4655 // Special version for compatibility with C1 Visualizer.
4656 LIR_Opr opr = LinearScan::get_operand(reg_num());
4657 if (opr->is_valid()) {
4658 out->print("\"");
4659 opr->print(out);
4660 out->print("\" ");
4661 }
4662 } else {
4663 // Improved output for normal debugging.
4664 if (reg_num() < LIR_OprDesc::vreg_base) {
4665 LinearScan::print_reg_num(out, assigned_reg());
4666 } else if (assigned_reg() != -1 && (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4667 LinearScan::calc_operand_for_interval(this)->print(out);
4668 } else {
4669 // Virtual register that has no assigned register yet.
4670 out->print("[ANY]");
4671 }
4672 out->print(" ");
4673 }
4674 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4675
4676 // print ranges
4677 Range* cur = _first;
4678 while (cur != Range::end()) {
4679 cur->print(out);
4680 cur = cur->next();
4681 assert(cur != NULL, "range list not closed with range sentinel");
4682 }
4683
4684 // print use positions
4685 int prev = 0;
4686 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4687 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4688 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4689 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4690
4691 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4692 prev = _use_pos_and_kinds.at(i);
4693 }
4694
4695 out->print(" \"%s\"", SpillState2Name[spill_state()]);
4696 out->cr();
4697 }
4698
4699 void Interval::print_parent() const {
4700 if (_split_parent != this) {
4701 _split_parent->print_on(tty);
4702 } else {
4703 tty->print_cr("Parent: this");
4704 }
4705 }
4706
4707 void Interval::print_children() const {
4708 if (_split_children == NULL) {
4709 tty->print_cr("Children: []");
4710 } else {
4711 tty->print_cr("Children:");
4712 for (int i = 0; i < _split_children->length(); i++) {
4713 tty->print("%d: ", i);
4714 _split_children->at(i)->print_on(tty);
4715 }
4716 }
4717 }
4718 #endif // NOT PRODUCT
4719
4720
4721
4722
4723 // **** Implementation of IntervalWalker ****************************
4724
4725 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4726 : _compilation(allocator->compilation())
4727 , _allocator(allocator)
4728 {
4729 _unhandled_first[fixedKind] = unhandled_fixed_first;
4730 _unhandled_first[anyKind] = unhandled_any_first;
4731 _active_first[fixedKind] = Interval::end();
4732 _inactive_first[fixedKind] = Interval::end();
4733 _active_first[anyKind] = Interval::end();
4734 _inactive_first[anyKind] = Interval::end();
4735 _current_position = -1;
4736 _current = NULL;
4737 next_interval();
4738 }
4739
4740
4741 // append interval in order of current range from()
4742 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4743 Interval* prev = NULL;
4744 Interval* cur = *list;
4745 while (cur->current_from() < interval->current_from()) {
4746 prev = cur; cur = cur->next();
4747 }
4748 if (prev == NULL) {
4749 *list = interval;
4750 } else {
4751 prev->set_next(interval);
4752 }
4753 interval->set_next(cur);
4754 }
4755
4756 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4757 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4758
4759 Interval* prev = NULL;
4760 Interval* cur = *list;
4761 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4762 prev = cur; cur = cur->next();
4763 }
4764 if (prev == NULL) {
4765 *list = interval;
4766 } else {
4767 prev->set_next(interval);
4768 }
4769 interval->set_next(cur);
4770 }
4771
4772
4773 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4774 while (*list != Interval::end() && *list != i) {
4775 list = (*list)->next_addr();
4776 }
4777 if (*list != Interval::end()) {
4778 assert(*list == i, "check");
4779 *list = (*list)->next();
4780 return true;
4781 } else {
4782 return false;
4783 }
4784 }
4785
4786 void IntervalWalker::remove_from_list(Interval* i) {
4787 bool deleted;
4788
4789 if (i->state() == activeState) {
4790 deleted = remove_from_list(active_first_addr(anyKind), i);
4791 } else {
4792 assert(i->state() == inactiveState, "invalid state");
4793 deleted = remove_from_list(inactive_first_addr(anyKind), i);
4794 }
4795
4796 assert(deleted, "interval has not been found in list");
4797 }
4798
4799
4800 void IntervalWalker::walk_to(IntervalState state, int from) {
4801 assert (state == activeState || state == inactiveState, "wrong state");
4802 for_each_interval_kind(kind) {
4803 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4804 Interval* next = *prev;
4805 while (next->current_from() <= from) {
4806 Interval* cur = next;
4807 next = cur->next();
4808
4809 bool range_has_changed = false;
4810 while (cur->current_to() <= from) {
4811 cur->next_range();
4812 range_has_changed = true;
4813 }
4814
4815 // also handle move from inactive list to active list
4816 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4817
4818 if (range_has_changed) {
4819 // remove cur from list
4820 *prev = next;
4821 if (cur->current_at_end()) {
4822 // move to handled state (not maintained as a list)
4823 cur->set_state(handledState);
4824 DEBUG_ONLY(interval_moved(cur, kind, state, handledState);)
4825 } else if (cur->current_from() <= from){
4826 // sort into active list
4827 append_sorted(active_first_addr(kind), cur);
4828 cur->set_state(activeState);
4829 if (*prev == cur) {
4830 assert(state == activeState, "check");
4831 prev = cur->next_addr();
4832 }
4833 DEBUG_ONLY(interval_moved(cur, kind, state, activeState);)
4834 } else {
4835 // sort into inactive list
4836 append_sorted(inactive_first_addr(kind), cur);
4837 cur->set_state(inactiveState);
4838 if (*prev == cur) {
4839 assert(state == inactiveState, "check");
4840 prev = cur->next_addr();
4841 }
4842 DEBUG_ONLY(interval_moved(cur, kind, state, inactiveState);)
4843 }
4844 } else {
4845 prev = cur->next_addr();
4846 continue;
4847 }
4848 }
4849 }
4850 }
4851
4852
4853 void IntervalWalker::next_interval() {
4854 IntervalKind kind;
4855 Interval* any = _unhandled_first[anyKind];
4856 Interval* fixed = _unhandled_first[fixedKind];
4857
4858 if (any != Interval::end()) {
4859 // intervals may start at same position -> prefer fixed interval
4860 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4861
4862 assert (kind == fixedKind && fixed->from() <= any->from() ||
4863 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!");
4864 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4865
4866 } else if (fixed != Interval::end()) {
4867 kind = fixedKind;
4868 } else {
4869 _current = NULL; return;
4870 }
4871 _current_kind = kind;
4872 _current = _unhandled_first[kind];
4873 _unhandled_first[kind] = _current->next();
4874 _current->set_next(Interval::end());
4875 _current->rewind_range();
4876 }
4877
4878
4879 void IntervalWalker::walk_to(int lir_op_id) {
4880 assert(_current_position <= lir_op_id, "can not walk backwards");
4881 while (current() != NULL) {
4882 bool is_active = current()->from() <= lir_op_id;
4883 int id = is_active ? current()->from() : lir_op_id;
4884
4885 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4886
4887 // set _current_position prior to call of walk_to
4888 _current_position = id;
4889
4890 // call walk_to even if _current_position == id
4891 walk_to(activeState, id);
4892 walk_to(inactiveState, id);
4893
4894 if (is_active) {
4895 current()->set_state(activeState);
4896 if (activate_current()) {
4897 append_sorted(active_first_addr(current_kind()), current());
4898 DEBUG_ONLY(interval_moved(current(), current_kind(), unhandledState, activeState);)
4899 }
4900
4901 next_interval();
4902 } else {
4903 return;
4904 }
4905 }
4906 }
4907
4908 #ifdef ASSERT
4909 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4910 if (TraceLinearScanLevel >= 4) {
4911 #define print_state(state) \
4912 switch(state) {\
4913 case unhandledState: tty->print("unhandled"); break;\
4914 case activeState: tty->print("active"); break;\
4915 case inactiveState: tty->print("inactive"); break;\
4916 case handledState: tty->print("handled"); break;\
4917 default: ShouldNotReachHere(); \
4918 }
4919
4920 print_state(from); tty->print(" to "); print_state(to);
4921 tty->fill_to(23);
4922 interval->print();
4923
4924 #undef print_state
4925 }
4926 }
4927 #endif // ASSERT
4928
4929 // **** Implementation of LinearScanWalker **************************
4930
4931 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4932 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4933 , _move_resolver(allocator)
4934 {
4935 for (int i = 0; i < LinearScan::nof_regs; i++) {
4936 _spill_intervals[i] = new IntervalList(2);
4937 }
4938 }
4939
4940
4941 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4942 for (int i = _first_reg; i <= _last_reg; i++) {
4943 _use_pos[i] = max_jint;
4944
4945 if (!only_process_use_pos) {
4946 _block_pos[i] = max_jint;
4947 _spill_intervals[i]->clear();
4948 }
4949 }
4950 }
4951
4952 inline void LinearScanWalker::exclude_from_use(int reg) {
4953 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4954 if (reg >= _first_reg && reg <= _last_reg) {
4955 _use_pos[reg] = 0;
4956 }
4957 }
4958 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4959 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4960
4961 exclude_from_use(i->assigned_reg());
4962 exclude_from_use(i->assigned_regHi());
4963 }
4964
4965 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4966 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4967
4968 if (reg >= _first_reg && reg <= _last_reg) {
4969 if (_use_pos[reg] > use_pos) {
4970 _use_pos[reg] = use_pos;
4971 }
4972 if (!only_process_use_pos) {
4973 _spill_intervals[reg]->append(i);
4974 }
4975 }
4976 }
4977 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4978 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4979 if (use_pos != -1) {
4980 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4981 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4982 }
4983 }
4984
4985 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4986 if (reg >= _first_reg && reg <= _last_reg) {
4987 if (_block_pos[reg] > block_pos) {
4988 _block_pos[reg] = block_pos;
4989 }
4990 if (_use_pos[reg] > block_pos) {
4991 _use_pos[reg] = block_pos;
4992 }
4993 }
4994 }
4995 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4996 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4997 if (block_pos != -1) {
4998 set_block_pos(i->assigned_reg(), i, block_pos);
4999 set_block_pos(i->assigned_regHi(), i, block_pos);
5000 }
5001 }
5002
5003
5004 void LinearScanWalker::free_exclude_active_fixed() {
5005 Interval* list = active_first(fixedKind);
5006 while (list != Interval::end()) {
5007 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
5008 exclude_from_use(list);
5009 list = list->next();
5010 }
5011 }
5012
5013 void LinearScanWalker::free_exclude_active_any() {
5014 Interval* list = active_first(anyKind);
5015 while (list != Interval::end()) {
5016 exclude_from_use(list);
5017 list = list->next();
5018 }
5019 }
5020
5021 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
5022 Interval* list = inactive_first(fixedKind);
5023 while (list != Interval::end()) {
5024 if (cur->to() <= list->current_from()) {
5025 assert(list->current_intersects_at(cur) == -1, "must not intersect");
5026 set_use_pos(list, list->current_from(), true);
5027 } else {
5028 set_use_pos(list, list->current_intersects_at(cur), true);
5029 }
5030 list = list->next();
5031 }
5032 }
5033
5034 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
5035 Interval* list = inactive_first(anyKind);
5036 while (list != Interval::end()) {
5037 set_use_pos(list, list->current_intersects_at(cur), true);
5038 list = list->next();
5039 }
5040 }
5041
5042 void LinearScanWalker::spill_exclude_active_fixed() {
5043 Interval* list = active_first(fixedKind);
5044 while (list != Interval::end()) {
5045 exclude_from_use(list);
5046 list = list->next();
5047 }
5048 }
5049
5050 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
5051 Interval* list = inactive_first(fixedKind);
5052 while (list != Interval::end()) {
5053 if (cur->to() > list->current_from()) {
5054 set_block_pos(list, list->current_intersects_at(cur));
5055 } else {
5056 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5057 }
5058
5059 list = list->next();
5060 }
5061 }
5062
5063 void LinearScanWalker::spill_collect_active_any() {
5064 Interval* list = active_first(anyKind);
5065 while (list != Interval::end()) {
5066 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5067 list = list->next();
5068 }
5069 }
5070
5071 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5072 Interval* list = inactive_first(anyKind);
5073 while (list != Interval::end()) {
5074 if (list->current_intersects(cur)) {
5075 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5076 }
5077 list = list->next();
5078 }
5079 }
5080
5081
5082 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5083 // output all moves here. When source and target are equal, the move is
5084 // optimized away later in assign_reg_nums
5085
5086 op_id = (op_id + 1) & ~1;
5087 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5088 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5089
5090 // calculate index of instruction inside instruction list of current block
5091 // the minimal index (for a block with no spill moves) can be calculated because the
5092 // numbering of instructions is known.
5093 // When the block already contains spill moves, the index must be increased until the
5094 // correct index is reached.
5095 LIR_OpList* list = op_block->lir()->instructions_list();
5096 int index = (op_id - list->at(0)->id()) / 2;
5097 assert(list->at(index)->id() <= op_id, "error in calculation");
5098
5099 while (list->at(index)->id() != op_id) {
5100 index++;
5101 assert(0 <= index && index < list->length(), "index out of bounds");
5102 }
5103 assert(1 <= index && index < list->length(), "index out of bounds");
5104 assert(list->at(index)->id() == op_id, "error in calculation");
5105
5106 // insert new instruction before instruction at position index
5107 _move_resolver.move_insert_position(op_block->lir(), index - 1);
5108 _move_resolver.add_mapping(src_it, dst_it);
5109 }
5110
5111
5112 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5113 int from_block_nr = min_block->linear_scan_number();
5114 int to_block_nr = max_block->linear_scan_number();
5115
5116 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5117 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5118 assert(from_block_nr < to_block_nr, "must cross block boundary");
5119
5120 // Try to split at end of max_block. If this would be after
5121 // max_split_pos, then use the begin of max_block
5122 int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5123 if (optimal_split_pos > max_split_pos) {
5124 optimal_split_pos = max_block->first_lir_instruction_id();
5125 }
5126
5127 int min_loop_depth = max_block->loop_depth();
5128 for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5129 BlockBegin* cur = block_at(i);
5130
5131 if (cur->loop_depth() < min_loop_depth) {
5132 // block with lower loop-depth found -> split at the end of this block
5133 min_loop_depth = cur->loop_depth();
5134 optimal_split_pos = cur->last_lir_instruction_id() + 2;
5135 }
5136 }
5137 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5138
5139 return optimal_split_pos;
5140 }
5141
5142
5143 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5144 int optimal_split_pos = -1;
5145 if (min_split_pos == max_split_pos) {
5146 // trivial case, no optimization of split position possible
5147 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
5148 optimal_split_pos = min_split_pos;
5149
5150 } else {
5151 assert(min_split_pos < max_split_pos, "must be true then");
5152 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5153
5154 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5155 // beginning of a block, then min_split_pos is also a possible split position.
5156 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5157 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5158
5159 // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5160 // when an interval ends at the end of the last block of the method
5161 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5162 // block at this op_id)
5163 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5164
5165 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5166 if (min_block == max_block) {
5167 // split position cannot be moved to block boundary, so split as late as possible
5168 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5169 optimal_split_pos = max_split_pos;
5170
5171 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5172 // Do not move split position if the interval has a hole before max_split_pos.
5173 // Intervals resulting from Phi-Functions have more than one definition (marked
5174 // as mustHaveRegister) with a hole before each definition. When the register is needed
5175 // for the second definition, an earlier reloading is unnecessary.
5176 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
5177 optimal_split_pos = max_split_pos;
5178
5179 } else {
5180 // seach optimal block boundary between min_split_pos and max_split_pos
5181 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5182
5183 if (do_loop_optimization) {
5184 // Loop optimization: if a loop-end marker is found between min- and max-position,
5185 // then split before this loop
5186 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5187 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
5188
5189 assert(loop_end_pos > min_split_pos, "invalid order");
5190 if (loop_end_pos < max_split_pos) {
5191 // loop-end marker found between min- and max-position
5192 // if it is not the end marker for the same loop as the min-position, then move
5193 // the max-position to this loop block.
5194 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5195 // of the interval (normally, only mustHaveRegister causes a reloading)
5196 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5197
5198 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5199 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5200
5201 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5202 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5203 optimal_split_pos = -1;
5204 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary"));
5205 } else {
5206 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful"));
5207 }
5208 }
5209 }
5210
5211 if (optimal_split_pos == -1) {
5212 // not calculated by loop optimization
5213 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5214 }
5215 }
5216 }
5217 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos));
5218
5219 return optimal_split_pos;
5220 }
5221
5222
5223 /*
5224 split an interval at the optimal position between min_split_pos and
5225 max_split_pos in two parts:
5226 1) the left part has already a location assigned
5227 2) the right part is sorted into to the unhandled-list
5228 */
5229 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5230 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print());
5231 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5232
5233 assert(it->from() < min_split_pos, "cannot split at start of interval");
5234 assert(current_position() < min_split_pos, "cannot split before current position");
5235 assert(min_split_pos <= max_split_pos, "invalid order");
5236 assert(max_split_pos <= it->to(), "cannot split after end of interval");
5237
5238 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5239
5240 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5241 assert(optimal_split_pos <= it->to(), "cannot split after end of interval");
5242 assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5243
5244 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5245 // the split position would be just before the end of the interval
5246 // -> no split at all necessary
5247 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
5248 return;
5249 }
5250
5251 // must calculate this before the actual split is performed and before split position is moved to odd op_id
5252 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5253
5254 if (!allocator()->is_block_begin(optimal_split_pos)) {
5255 // move position before actual instruction (odd op_id)
5256 optimal_split_pos = (optimal_split_pos - 1) | 1;
5257 }
5258
5259 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5260 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5261 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5262
5263 Interval* split_part = it->split(optimal_split_pos);
5264
5265 allocator()->append_interval(split_part);
5266 allocator()->copy_register_flags(it, split_part);
5267 split_part->set_insert_move_when_activated(move_necessary);
5268 append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5269
5270 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5271 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5272 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print());
5273 }
5274
5275 /*
5276 split an interval at the optimal position between min_split_pos and
5277 max_split_pos in two parts:
5278 1) the left part has already a location assigned
5279 2) the right part is always on the stack and therefore ignored in further processing
5280 */
5281 void LinearScanWalker::split_for_spilling(Interval* it) {
5282 // calculate allowed range of splitting position
5283 int max_split_pos = current_position();
5284 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5285
5286 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print());
5287 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5288
5289 assert(it->state() == activeState, "why spill interval that is not active?");
5290 assert(it->from() <= min_split_pos, "cannot split before start of interval");
5291 assert(min_split_pos <= max_split_pos, "invalid order");
5292 assert(max_split_pos < it->to(), "cannot split at end end of interval");
5293 assert(current_position() < it->to(), "interval must not end before current position");
5294
5295 if (min_split_pos == it->from()) {
5296 // the whole interval is never used, so spill it entirely to memory
5297 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
5298 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5299
5300 allocator()->assign_spill_slot(it);
5301 allocator()->change_spill_state(it, min_split_pos);
5302
5303 // Also kick parent intervals out of register to memory when they have no use
5304 // position. This avoids short interval in register surrounded by intervals in
5305 // memory -> avoid useless moves from memory to register and back
5306 Interval* parent = it;
5307 while (parent != NULL && parent->is_split_child()) {
5308 parent = parent->split_child_before_op_id(parent->from());
5309
5310 if (parent->assigned_reg() < LinearScan::nof_regs) {
5311 if (parent->first_usage(shouldHaveRegister) == max_jint) {
5312 // parent is never used, so kick it out of its assigned register
5313 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
5314 allocator()->assign_spill_slot(parent);
5315 } else {
5316 // do not go further back because the register is actually used by the interval
5317 parent = NULL;
5318 }
5319 }
5320 }
5321
5322 } else {
5323 // search optimal split pos, split interval and spill only the right hand part
5324 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5325
5326 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5327 assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5328 assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5329
5330 if (!allocator()->is_block_begin(optimal_split_pos)) {
5331 // move position before actual instruction (odd op_id)
5332 optimal_split_pos = (optimal_split_pos - 1) | 1;
5333 }
5334
5335 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5336 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5337 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5338
5339 Interval* spilled_part = it->split(optimal_split_pos);
5340 allocator()->append_interval(spilled_part);
5341 allocator()->assign_spill_slot(spilled_part);
5342 allocator()->change_spill_state(spilled_part, optimal_split_pos);
5343
5344 if (!allocator()->is_block_begin(optimal_split_pos)) {
5345 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5346 insert_move(optimal_split_pos, it, spilled_part);
5347 }
5348
5349 // the current_split_child is needed later when moves are inserted for reloading
5350 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5351 spilled_part->make_current_split_child();
5352
5353 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts"));
5354 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5355 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print());
5356 }
5357 }
5358
5359
5360 void LinearScanWalker::split_stack_interval(Interval* it) {
5361 int min_split_pos = current_position() + 1;
5362 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5363
5364 split_before_usage(it, min_split_pos, max_split_pos);
5365 }
5366
5367 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5368 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5369 int max_split_pos = register_available_until;
5370
5371 split_before_usage(it, min_split_pos, max_split_pos);
5372 }
5373
5374 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5375 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5376
5377 int current_pos = current_position();
5378 if (it->state() == inactiveState) {
5379 // the interval is currently inactive, so no spill slot is needed for now.
5380 // when the split part is activated, the interval has a new chance to get a register,
5381 // so in the best case no stack slot is necessary
5382 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5383 split_before_usage(it, current_pos + 1, current_pos + 1);
5384
5385 } else {
5386 // search the position where the interval must have a register and split
5387 // at the optimal position before.
5388 // The new created part is added to the unhandled list and will get a register
5389 // when it is activated
5390 int min_split_pos = current_pos + 1;
5391 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5392
5393 split_before_usage(it, min_split_pos, max_split_pos);
5394
5395 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5396 split_for_spilling(it);
5397 }
5398 }
5399
5400 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5401 int min_full_reg = any_reg;
5402 int max_partial_reg = any_reg;
5403
5404 for (int i = _first_reg; i <= _last_reg; i++) {
5405 if (i == ignore_reg) {
5406 // this register must be ignored
5407
5408 } else if (_use_pos[i] >= interval_to) {
5409 // this register is free for the full interval
5410 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5411 min_full_reg = i;
5412 }
5413 } else if (_use_pos[i] > reg_needed_until) {
5414 // this register is at least free until reg_needed_until
5415 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5416 max_partial_reg = i;
5417 }
5418 }
5419 }
5420
5421 if (min_full_reg != any_reg) {
5422 return min_full_reg;
5423 } else if (max_partial_reg != any_reg) {
5424 *need_split = true;
5425 return max_partial_reg;
5426 } else {
5427 return any_reg;
5428 }
5429 }
5430
5431 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5432 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5433
5434 int min_full_reg = any_reg;
5435 int max_partial_reg = any_reg;
5436
5437 for (int i = _first_reg; i < _last_reg; i+=2) {
5438 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5439 // this register is free for the full interval
5440 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5441 min_full_reg = i;
5442 }
5443 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5444 // this register is at least free until reg_needed_until
5445 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5446 max_partial_reg = i;
5447 }
5448 }
5449 }
5450
5451 if (min_full_reg != any_reg) {
5452 return min_full_reg;
5453 } else if (max_partial_reg != any_reg) {
5454 *need_split = true;
5455 return max_partial_reg;
5456 } else {
5457 return any_reg;
5458 }
5459 }
5460
5461 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5462 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5463
5464 init_use_lists(true);
5465 free_exclude_active_fixed();
5466 free_exclude_active_any();
5467 free_collect_inactive_fixed(cur);
5468 free_collect_inactive_any(cur);
5469 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5470
5471 // _use_pos contains the start of the next interval that has this register assigned
5472 // (either as a fixed register or a normal allocated register in the past)
5473 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5474 #ifdef ASSERT
5475 if (TraceLinearScanLevel >= 4) {
5476 tty->print_cr(" state of registers:");
5477 for (int i = _first_reg; i <= _last_reg; i++) {
5478 tty->print(" reg %d (", i);
5479 LinearScan::print_reg_num(i);
5480 tty->print_cr("): use_pos: %d", _use_pos[i]);
5481 }
5482 }
5483 #endif
5484
5485 int hint_reg, hint_regHi;
5486 Interval* register_hint = cur->register_hint();
5487 if (register_hint != NULL) {
5488 hint_reg = register_hint->assigned_reg();
5489 hint_regHi = register_hint->assigned_regHi();
5490
5491 if (_num_phys_regs == 2 && allocator()->is_precolored_cpu_interval(register_hint)) {
5492 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5493 hint_regHi = hint_reg + 1; // connect e.g. eax-edx
5494 }
5495 #ifdef ASSERT
5496 if (TraceLinearScanLevel >= 4) {
5497 tty->print(" hint registers %d (", hint_reg);
5498 LinearScan::print_reg_num(hint_reg);
5499 tty->print("), %d (", hint_regHi);
5500 LinearScan::print_reg_num(hint_regHi);
5501 tty->print(") from interval ");
5502 register_hint->print();
5503 }
5504 #endif
5505 } else {
5506 hint_reg = any_reg;
5507 hint_regHi = any_reg;
5508 }
5509 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5510 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5511
5512 // the register must be free at least until this position
5513 int reg_needed_until = cur->from() + 1;
5514 int interval_to = cur->to();
5515
5516 bool need_split = false;
5517 int split_pos;
5518 int reg;
5519 int regHi = any_reg;
5520
5521 if (_adjacent_regs) {
5522 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5523 regHi = reg + 1;
5524 if (reg == any_reg) {
5525 return false;
5526 }
5527 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5528
5529 } else {
5530 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5531 if (reg == any_reg) {
5532 return false;
5533 }
5534 split_pos = _use_pos[reg];
5535
5536 if (_num_phys_regs == 2) {
5537 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5538
5539 if (_use_pos[reg] < interval_to && regHi == any_reg) {
5540 // do not split interval if only one register can be assigned until the split pos
5541 // (when one register is found for the whole interval, split&spill is only
5542 // performed for the hi register)
5543 return false;
5544
5545 } else if (regHi != any_reg) {
5546 split_pos = MIN2(split_pos, _use_pos[regHi]);
5547
5548 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5549 if (reg > regHi) {
5550 int temp = reg;
5551 reg = regHi;
5552 regHi = temp;
5553 }
5554 }
5555 }
5556 }
5557
5558 cur->assign_reg(reg, regHi);
5559 #ifdef ASSERT
5560 if (TraceLinearScanLevel >= 2) {
5561 tty->print(" selected registers %d (", reg);
5562 LinearScan::print_reg_num(reg);
5563 tty->print("), %d (", regHi);
5564 LinearScan::print_reg_num(regHi);
5565 tty->print_cr(")");
5566 }
5567 #endif
5568 assert(split_pos > 0, "invalid split_pos");
5569 if (need_split) {
5570 // register not available for full interval, so split it
5571 split_when_partial_register_available(cur, split_pos);
5572 }
5573
5574 // only return true if interval is completely assigned
5575 return _num_phys_regs == 1 || regHi != any_reg;
5576 }
5577
5578
5579 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5580 int max_reg = any_reg;
5581
5582 for (int i = _first_reg; i <= _last_reg; i++) {
5583 if (i == ignore_reg) {
5584 // this register must be ignored
5585
5586 } else if (_use_pos[i] > reg_needed_until) {
5587 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5588 max_reg = i;
5589 }
5590 }
5591 }
5592
5593 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5594 *need_split = true;
5595 }
5596
5597 return max_reg;
5598 }
5599
5600 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5601 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5602
5603 int max_reg = any_reg;
5604
5605 for (int i = _first_reg; i < _last_reg; i+=2) {
5606 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5607 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5608 max_reg = i;
5609 }
5610 }
5611 }
5612
5613 if (max_reg != any_reg &&
5614 (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5615 *need_split = true;
5616 }
5617
5618 return max_reg;
5619 }
5620
5621 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5622 assert(reg != any_reg, "no register assigned");
5623
5624 for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5625 Interval* it = _spill_intervals[reg]->at(i);
5626 remove_from_list(it);
5627 split_and_spill_interval(it);
5628 }
5629
5630 if (regHi != any_reg) {
5631 IntervalList* processed = _spill_intervals[reg];
5632 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5633 Interval* it = _spill_intervals[regHi]->at(i);
5634 if (processed->find(it) == -1) {
5635 remove_from_list(it);
5636 split_and_spill_interval(it);
5637 }
5638 }
5639 }
5640 }
5641
5642
5643 // Split an Interval and spill it to memory so that cur can be placed in a register
5644 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5645 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5646
5647 // collect current usage of registers
5648 init_use_lists(false);
5649 spill_exclude_active_fixed();
5650 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5651 spill_block_inactive_fixed(cur);
5652 spill_collect_active_any();
5653 spill_collect_inactive_any(cur);
5654
5655 #ifdef ASSERT
5656 if (TraceLinearScanLevel >= 4) {
5657 tty->print_cr(" state of registers:");
5658 for (int i = _first_reg; i <= _last_reg; i++) {
5659 tty->print(" reg %d(", i);
5660 LinearScan::print_reg_num(i);
5661 tty->print("): use_pos: %d, block_pos: %d, intervals: ", _use_pos[i], _block_pos[i]);
5662 for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5663 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5664 }
5665 tty->cr();
5666 }
5667 }
5668 #endif
5669
5670 // the register must be free at least until this position
5671 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5672 int interval_to = cur->to();
5673 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5674
5675 int split_pos = 0;
5676 int use_pos = 0;
5677 bool need_split = false;
5678 int reg, regHi;
5679
5680 if (_adjacent_regs) {
5681 reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5682 regHi = reg + 1;
5683
5684 if (reg != any_reg) {
5685 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5686 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5687 }
5688 } else {
5689 reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5690 regHi = any_reg;
5691
5692 if (reg != any_reg) {
5693 use_pos = _use_pos[reg];
5694 split_pos = _block_pos[reg];
5695
5696 if (_num_phys_regs == 2) {
5697 if (cur->assigned_reg() != any_reg) {
5698 regHi = reg;
5699 reg = cur->assigned_reg();
5700 } else {
5701 regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5702 if (regHi != any_reg) {
5703 use_pos = MIN2(use_pos, _use_pos[regHi]);
5704 split_pos = MIN2(split_pos, _block_pos[regHi]);
5705 }
5706 }
5707
5708 if (regHi != any_reg && reg > regHi) {
5709 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5710 int temp = reg;
5711 reg = regHi;
5712 regHi = temp;
5713 }
5714 }
5715 }
5716 }
5717
5718 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5719 // the first use of cur is later than the spilling position -> spill cur
5720 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5721
5722 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5723 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5724 // assign a reasonable register and do a bailout in product mode to avoid errors
5725 allocator()->assign_spill_slot(cur);
5726 BAILOUT("LinearScan: no register found");
5727 }
5728
5729 split_and_spill_interval(cur);
5730 } else {
5731 #ifdef ASSERT
5732 if (TraceLinearScanLevel >= 4) {
5733 tty->print("decided to use register %d (", reg);
5734 LinearScan::print_reg_num(reg);
5735 tty->print("), %d (", regHi);
5736 LinearScan::print_reg_num(regHi);
5737 tty->print_cr(")");
5738 }
5739 #endif
5740 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5741 assert(split_pos > 0, "invalid split_pos");
5742 assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5743
5744 cur->assign_reg(reg, regHi);
5745 if (need_split) {
5746 // register not available for full interval, so split it
5747 split_when_partial_register_available(cur, split_pos);
5748 }
5749
5750 // perform splitting and spilling for all affected intervalls
5751 split_and_spill_intersecting_intervals(reg, regHi);
5752 }
5753 }
5754
5755 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5756 #ifdef X86
5757 // fast calculation of intervals that can never get a register because the
5758 // the next instruction is a call that blocks all registers
5759 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5760
5761 // check if this interval is the result of a split operation
5762 // (an interval got a register until this position)
5763 int pos = cur->from();
5764 if ((pos & 1) == 1) {
5765 // the current instruction is a call that blocks all registers
5766 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5767 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
5768
5769 // safety check that there is really no register available
5770 assert(alloc_free_reg(cur) == false, "found a register for this interval");
5771 return true;
5772 }
5773
5774 }
5775 #endif
5776 return false;
5777 }
5778
5779 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5780 BasicType type = cur->type();
5781 _num_phys_regs = LinearScan::num_physical_regs(type);
5782 _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5783
5784 if (pd_init_regs_for_alloc(cur)) {
5785 // the appropriate register range was selected.
5786 } else if (type == T_FLOAT || type == T_DOUBLE) {
5787 _first_reg = pd_first_fpu_reg;
5788 _last_reg = pd_last_fpu_reg;
5789 } else {
5790 _first_reg = pd_first_cpu_reg;
5791 _last_reg = FrameMap::last_cpu_reg();
5792 }
5793
5794 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5795 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5796 }
5797
5798
5799 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5800 if (op->code() != lir_move) {
5801 return false;
5802 }
5803 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5804
5805 LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5806 LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5807 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5808 }
5809
5810 // optimization (especially for phi functions of nested loops):
5811 // assign same spill slot to non-intersecting intervals
5812 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5813 if (cur->is_split_child()) {
5814 // optimization is only suitable for split parents
5815 return;
5816 }
5817
5818 Interval* register_hint = cur->register_hint(false);
5819 if (register_hint == NULL) {
5820 // cur is not the target of a move, otherwise register_hint would be set
5821 return;
5822 }
5823 assert(register_hint->is_split_parent(), "register hint must be split parent");
5824
5825 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5826 // combining the stack slots for intervals where spill move optimization is applied
5827 // is not benefitial and would cause problems
5828 return;
5829 }
5830
5831 int begin_pos = cur->from();
5832 int end_pos = cur->to();
5833 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5834 // safety check that lir_op_with_id is allowed
5835 return;
5836 }
5837
5838 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5839 // cur and register_hint are not connected with two moves
5840 return;
5841 }
5842
5843 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5844 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5845 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5846 // register_hint must be split, otherwise the re-writing of use positions does not work
5847 return;
5848 }
5849
5850 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5851 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5852 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5853 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5854
5855 if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5856 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5857 return;
5858 }
5859 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5860 assert(!cur->intersects(register_hint), "cur should not intersect register_hint");
5861
5862 if (cur->intersects_any_children_of(register_hint)) {
5863 // Bail out if cur intersects any split children of register_hint, which have the same spill slot as their parent. An overlap of two intervals with
5864 // the same spill slot could result in a situation where both intervals are spilled at the same time to the same stack location which is not correct.
5865 return;
5866 }
5867
5868 // modify intervals such that cur gets the same stack slot as register_hint
5869 // delete use positions to prevent the intervals to get a register at beginning
5870 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5871 cur->remove_first_use_pos();
5872 end_hint->remove_first_use_pos();
5873 }
5874
5875
5876 // allocate a physical register or memory location to an interval
5877 bool LinearScanWalker::activate_current() {
5878 Interval* cur = current();
5879 bool result = true;
5880
5881 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print());
5882 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5883
5884 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5885 // activating an interval that has a stack slot assigned -> split it at first use position
5886 // used for method parameters
5887 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
5888
5889 split_stack_interval(cur);
5890 result = false;
5891
5892 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5893 // activating an interval that must start in a stack slot, but may get a register later
5894 // used for lir_roundfp: rounding is done by store to stack and reload later
5895 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
5896 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5897
5898 allocator()->assign_spill_slot(cur);
5899 split_stack_interval(cur);
5900 result = false;
5901
5902 } else if (cur->assigned_reg() == any_reg) {
5903 // interval has not assigned register -> normal allocation
5904 // (this is the normal case for most intervals)
5905 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register"));
5906
5907 // assign same spill slot to non-intersecting intervals
5908 combine_spilled_intervals(cur);
5909
5910 init_vars_for_alloc(cur);
5911 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5912 // no empty register available.
5913 // split and spill another interval so that this interval gets a register
5914 alloc_locked_reg(cur);
5915 }
5916
5917 // spilled intervals need not be move to active-list
5918 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5919 result = false;
5920 }
5921 }
5922
5923 // load spilled values that become active from stack slot to register
5924 if (cur->insert_move_when_activated()) {
5925 assert(cur->is_split_child(), "must be");
5926 assert(cur->current_split_child() != NULL, "must be");
5927 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5928 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5929
5930 insert_move(cur->from(), cur->current_split_child(), cur);
5931 }
5932 cur->make_current_split_child();
5933
5934 return result; // true = interval is moved to active list
5935 }
5936
5937
5938 // Implementation of EdgeMoveOptimizer
5939
5940 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5941 _edge_instructions(4),
5942 _edge_instructions_idx(4)
5943 {
5944 }
5945
5946 void EdgeMoveOptimizer::optimize(BlockList* code) {
5947 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5948
5949 // ignore the first block in the list (index 0 is not processed)
5950 for (int i = code->length() - 1; i >= 1; i--) {
5951 BlockBegin* block = code->at(i);
5952
5953 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5954 optimizer.optimize_moves_at_block_end(block);
5955 }
5956 if (block->number_of_sux() == 2) {
5957 optimizer.optimize_moves_at_block_begin(block);
5958 }
5959 }
5960 }
5961
5962
5963 // clear all internal data structures
5964 void EdgeMoveOptimizer::init_instructions() {
5965 _edge_instructions.clear();
5966 _edge_instructions_idx.clear();
5967 }
5968
5969 // append a lir-instruction-list and the index of the current operation in to the list
5970 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5971 _edge_instructions.append(instructions);
5972 _edge_instructions_idx.append(instructions_idx);
5973 }
5974
5975 // return the current operation of the given edge (predecessor or successor)
5976 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5977 LIR_OpList* instructions = _edge_instructions.at(edge);
5978 int idx = _edge_instructions_idx.at(edge);
5979
5980 if (idx < instructions->length()) {
5981 return instructions->at(idx);
5982 } else {
5983 return NULL;
5984 }
5985 }
5986
5987 // removes the current operation of the given edge (predecessor or successor)
5988 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5989 LIR_OpList* instructions = _edge_instructions.at(edge);
5990 int idx = _edge_instructions_idx.at(edge);
5991 instructions->remove_at(idx);
5992
5993 if (decrement_index) {
5994 _edge_instructions_idx.at_put(edge, idx - 1);
5995 }
5996 }
5997
5998
5999 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
6000 if (op1 == NULL || op2 == NULL) {
6001 // at least one block is already empty -> no optimization possible
6002 return true;
6003 }
6004
6005 if (op1->code() == lir_move && op2->code() == lir_move) {
6006 assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
6007 assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
6008 LIR_Op1* move1 = (LIR_Op1*)op1;
6009 LIR_Op1* move2 = (LIR_Op1*)op2;
6010 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
6011 // these moves are exactly equal and can be optimized
6012 return false;
6013 }
6014
6015 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
6016 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
6017 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
6018 LIR_Op1* fxch1 = (LIR_Op1*)op1;
6019 LIR_Op1* fxch2 = (LIR_Op1*)op2;
6020 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
6021 // equal FPU stack operations can be optimized
6022 return false;
6023 }
6024
6025 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
6026 // equal FPU stack operations can be optimized
6027 return false;
6028 }
6029
6030 // no optimization possible
6031 return true;
6032 }
6033
6034 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
6035 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
6036
6037 if (block->is_predecessor(block)) {
6038 // currently we can't handle this correctly.
6039 return;
6040 }
6041
6042 init_instructions();
6043 int num_preds = block->number_of_preds();
6044 assert(num_preds > 1, "do not call otherwise");
6045 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6046
6047 // setup a list with the lir-instructions of all predecessors
6048 int i;
6049 for (i = 0; i < num_preds; i++) {
6050 BlockBegin* pred = block->pred_at(i);
6051 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6052
6053 if (pred->number_of_sux() != 1) {
6054 // this can happen with switch-statements where multiple edges are between
6055 // the same blocks.
6056 return;
6057 }
6058
6059 assert(pred->number_of_sux() == 1, "can handle only one successor");
6060 assert(pred->sux_at(0) == block, "invalid control flow");
6061 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6062 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6063 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6064
6065 if (pred_instructions->last()->info() != NULL) {
6066 // can not optimize instructions when debug info is needed
6067 return;
6068 }
6069
6070 // ignore the unconditional branch at the end of the block
6071 append_instructions(pred_instructions, pred_instructions->length() - 2);
6072 }
6073
6074
6075 // process lir-instructions while all predecessors end with the same instruction
6076 while (true) {
6077 LIR_Op* op = instruction_at(0);
6078 for (i = 1; i < num_preds; i++) {
6079 if (operations_different(op, instruction_at(i))) {
6080 // these instructions are different and cannot be optimized ->
6081 // no further optimization possible
6082 return;
6083 }
6084 }
6085
6086 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
6087
6088 // insert the instruction at the beginning of the current block
6089 block->lir()->insert_before(1, op);
6090
6091 // delete the instruction at the end of all predecessors
6092 for (i = 0; i < num_preds; i++) {
6093 remove_cur_instruction(i, true);
6094 }
6095 }
6096 }
6097
6098
6099 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6100 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6101
6102 init_instructions();
6103 int num_sux = block->number_of_sux();
6104
6105 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6106
6107 assert(num_sux == 2, "method should not be called otherwise");
6108 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6109 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6110 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6111
6112 if (cur_instructions->last()->info() != NULL) {
6113 // can no optimize instructions when debug info is needed
6114 return;
6115 }
6116
6117 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6118 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6119 // not a valid case for optimization
6120 // currently, only blocks that end with two branches (conditional branch followed
6121 // by unconditional branch) are optimized
6122 return;
6123 }
6124
6125 // now it is guaranteed that the block ends with two branch instructions.
6126 // the instructions are inserted at the end of the block before these two branches
6127 int insert_idx = cur_instructions->length() - 2;
6128
6129 int i;
6130 #ifdef ASSERT
6131 for (i = insert_idx - 1; i >= 0; i--) {
6132 LIR_Op* op = cur_instructions->at(i);
6133 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6134 assert(false, "block with two successors can have only two branch instructions");
6135 }
6136 }
6137 #endif
6138
6139 // setup a list with the lir-instructions of all successors
6140 for (i = 0; i < num_sux; i++) {
6141 BlockBegin* sux = block->sux_at(i);
6142 LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6143
6144 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6145
6146 if (sux->number_of_preds() != 1) {
6147 // this can happen with switch-statements where multiple edges are between
6148 // the same blocks.
6149 return;
6150 }
6151 assert(sux->pred_at(0) == block, "invalid control flow");
6152 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6153
6154 // ignore the label at the beginning of the block
6155 append_instructions(sux_instructions, 1);
6156 }
6157
6158 // process lir-instructions while all successors begin with the same instruction
6159 while (true) {
6160 LIR_Op* op = instruction_at(0);
6161 for (i = 1; i < num_sux; i++) {
6162 if (operations_different(op, instruction_at(i))) {
6163 // these instructions are different and cannot be optimized ->
6164 // no further optimization possible
6165 return;
6166 }
6167 }
6168
6169 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6170
6171 // insert instruction at end of current block
6172 block->lir()->insert_before(insert_idx, op);
6173 insert_idx++;
6174
6175 // delete the instructions at the beginning of all successors
6176 for (i = 0; i < num_sux; i++) {
6177 remove_cur_instruction(i, false);
6178 }
6179 }
6180 }
6181
6182
6183 // Implementation of ControlFlowOptimizer
6184
6185 ControlFlowOptimizer::ControlFlowOptimizer() :
6186 _original_preds(4)
6187 {
6188 }
6189
6190 void ControlFlowOptimizer::optimize(BlockList* code) {
6191 ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6192
6193 // push the OSR entry block to the end so that we're not jumping over it.
6194 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6195 if (osr_entry) {
6196 int index = osr_entry->linear_scan_number();
6197 assert(code->at(index) == osr_entry, "wrong index");
6198 code->remove_at(index);
6199 code->append(osr_entry);
6200 }
6201
6202 optimizer.reorder_short_loops(code);
6203 optimizer.delete_empty_blocks(code);
6204 optimizer.delete_unnecessary_jumps(code);
6205 optimizer.delete_jumps_to_return(code);
6206 }
6207
6208 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6209 int i = header_idx + 1;
6210 int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6211 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6212 i++;
6213 }
6214
6215 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6216 int end_idx = i - 1;
6217 BlockBegin* end_block = code->at(end_idx);
6218
6219 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6220 // short loop from header_idx to end_idx found -> reorder blocks such that
6221 // the header_block is the last block instead of the first block of the loop
6222 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6223 end_idx - header_idx + 1,
6224 header_block->block_id(), end_block->block_id()));
6225
6226 for (int j = header_idx; j < end_idx; j++) {
6227 code->at_put(j, code->at(j + 1));
6228 }
6229 code->at_put(end_idx, header_block);
6230
6231 // correct the flags so that any loop alignment occurs in the right place.
6232 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6233 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6234 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6235 }
6236 }
6237 }
6238
6239 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6240 for (int i = code->length() - 1; i >= 0; i--) {
6241 BlockBegin* block = code->at(i);
6242
6243 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6244 reorder_short_loop(code, block, i);
6245 }
6246 }
6247
6248 DEBUG_ONLY(verify(code));
6249 }
6250
6251 // only blocks with exactly one successor can be deleted. Such blocks
6252 // must always end with an unconditional branch to this successor
6253 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6254 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6255 return false;
6256 }
6257
6258 LIR_OpList* instructions = block->lir()->instructions_list();
6259
6260 assert(instructions->length() >= 2, "block must have label and branch");
6261 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6262 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6263 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6264 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6265
6266 // block must have exactly one successor
6267
6268 if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6269 return true;
6270 }
6271 return false;
6272 }
6273
6274 // substitute branch targets in all branch-instructions of this blocks
6275 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6276 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6277
6278 LIR_OpList* instructions = block->lir()->instructions_list();
6279
6280 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6281 for (int i = instructions->length() - 1; i >= 1; i--) {
6282 LIR_Op* op = instructions->at(i);
6283
6284 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6285 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6286 LIR_OpBranch* branch = (LIR_OpBranch*)op;
6287
6288 if (branch->block() == target_from) {
6289 branch->change_block(target_to);
6290 }
6291 if (branch->ublock() == target_from) {
6292 branch->change_ublock(target_to);
6293 }
6294 }
6295 }
6296 }
6297
6298 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6299 int old_pos = 0;
6300 int new_pos = 0;
6301 int num_blocks = code->length();
6302
6303 while (old_pos < num_blocks) {
6304 BlockBegin* block = code->at(old_pos);
6305
6306 if (can_delete_block(block)) {
6307 BlockBegin* new_target = block->sux_at(0);
6308
6309 // propagate backward branch target flag for correct code alignment
6310 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6311 new_target->set(BlockBegin::backward_branch_target_flag);
6312 }
6313
6314 // collect a list with all predecessors that contains each predecessor only once
6315 // the predecessors of cur are changed during the substitution, so a copy of the
6316 // predecessor list is necessary
6317 int j;
6318 _original_preds.clear();
6319 for (j = block->number_of_preds() - 1; j >= 0; j--) {
6320 BlockBegin* pred = block->pred_at(j);
6321 if (_original_preds.find(pred) == -1) {
6322 _original_preds.append(pred);
6323 }
6324 }
6325
6326 for (j = _original_preds.length() - 1; j >= 0; j--) {
6327 BlockBegin* pred = _original_preds.at(j);
6328 substitute_branch_target(pred, block, new_target);
6329 pred->substitute_sux(block, new_target);
6330 }
6331 } else {
6332 // adjust position of this block in the block list if blocks before
6333 // have been deleted
6334 if (new_pos != old_pos) {
6335 code->at_put(new_pos, code->at(old_pos));
6336 }
6337 new_pos++;
6338 }
6339 old_pos++;
6340 }
6341 code->trunc_to(new_pos);
6342
6343 DEBUG_ONLY(verify(code));
6344 }
6345
6346 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6347 // skip the last block because there a branch is always necessary
6348 for (int i = code->length() - 2; i >= 0; i--) {
6349 BlockBegin* block = code->at(i);
6350 LIR_OpList* instructions = block->lir()->instructions_list();
6351
6352 LIR_Op* last_op = instructions->last();
6353 if (last_op->code() == lir_branch) {
6354 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6355 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6356
6357 assert(last_branch->block() != NULL, "last branch must always have a block as target");
6358 assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6359
6360 if (last_branch->info() == NULL) {
6361 if (last_branch->block() == code->at(i + 1)) {
6362
6363 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6364
6365 // delete last branch instruction
6366 instructions->trunc_to(instructions->length() - 1);
6367
6368 } else {
6369 LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6370 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6371 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6372 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6373
6374 if (prev_branch->stub() == NULL) {
6375
6376 LIR_Op2* prev_cmp = NULL;
6377 // There might be a cmove inserted for profiling which depends on the same
6378 // compare. If we change the condition of the respective compare, we have
6379 // to take care of this cmove as well.
6380 #ifdef RISCV
6381 LIR_Op4* prev_cmove = NULL;
6382 #else
6383 LIR_Op2* prev_cmove = NULL;
6384 #endif
6385
6386 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6387 prev_op = instructions->at(j);
6388 // check for the cmove
6389 if (prev_op->code() == lir_cmove) {
6390 #ifdef RISCV
6391 assert(prev_op->as_Op4() != NULL, "cmove must be of type LIR_Op4");
6392 prev_cmove = (LIR_Op4*)prev_op;
6393 #else
6394 assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6395 prev_cmove = (LIR_Op2*)prev_op;
6396 #endif
6397 assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6398 }
6399 if (prev_op->code() == lir_cmp) {
6400 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6401 prev_cmp = (LIR_Op2*)prev_op;
6402 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6403 }
6404 }
6405 // Guarantee because it is dereferenced below.
6406 guarantee(prev_cmp != NULL, "should have found comp instruction for branch");
6407 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6408
6409 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6410
6411 // eliminate a conditional branch to the immediate successor
6412 prev_branch->change_block(last_branch->block());
6413 prev_branch->negate_cond();
6414 prev_cmp->set_condition(prev_branch->cond());
6415 instructions->trunc_to(instructions->length() - 1);
6416 // if we do change the condition, we have to change the cmove as well
6417 if (prev_cmove != NULL) {
6418 prev_cmove->set_condition(prev_branch->cond());
6419 LIR_Opr t = prev_cmove->in_opr1();
6420 prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6421 prev_cmove->set_in_opr2(t);
6422 }
6423 }
6424 }
6425 }
6426 }
6427 }
6428 }
6429 }
6430
6431 DEBUG_ONLY(verify(code));
6432 }
6433
6434 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6435 #ifdef ASSERT
6436 ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6437 #endif
6438
6439 for (int i = code->length() - 1; i >= 0; i--) {
6440 BlockBegin* block = code->at(i);
6441 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6442 LIR_Op* cur_last_op = cur_instructions->last();
6443
6444 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6445 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6446 // the block contains only a label and a return
6447 // if a predecessor ends with an unconditional jump to this block, then the jump
6448 // can be replaced with a return instruction
6449 //
6450 // Note: the original block with only a return statement cannot be deleted completely
6451 // because the predecessors might have other (conditional) jumps to this block
6452 // -> this may lead to unnecesary return instructions in the final code
6453
6454 assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6455 assert(block->number_of_sux() == 0 ||
6456 (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6457 "blocks that end with return must not have successors");
6458
6459 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6460 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6461
6462 for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6463 BlockBegin* pred = block->pred_at(j);
6464 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6465 LIR_Op* pred_last_op = pred_instructions->last();
6466
6467 if (pred_last_op->code() == lir_branch) {
6468 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6469 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6470
6471 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6472 // replace the jump to a return with a direct return
6473 // Note: currently the edge between the blocks is not deleted
6474 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_OpReturn(return_opr));
6475 #ifdef ASSERT
6476 return_converted.set_bit(pred->block_id());
6477 #endif
6478 }
6479 }
6480 }
6481 }
6482 }
6483 }
6484
6485
6486 #ifdef ASSERT
6487 void ControlFlowOptimizer::verify(BlockList* code) {
6488 for (int i = 0; i < code->length(); i++) {
6489 BlockBegin* block = code->at(i);
6490 LIR_OpList* instructions = block->lir()->instructions_list();
6491
6492 int j;
6493 for (j = 0; j < instructions->length(); j++) {
6494 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6495
6496 if (op_branch != NULL) {
6497 assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6498 assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6499 }
6500 }
6501
6502 for (j = 0; j < block->number_of_sux() - 1; j++) {
6503 BlockBegin* sux = block->sux_at(j);
6504 assert(code->find(sux) != -1, "successor not valid");
6505 }
6506
6507 for (j = 0; j < block->number_of_preds() - 1; j++) {
6508 BlockBegin* pred = block->pred_at(j);
6509 assert(code->find(pred) != -1, "successor not valid");
6510 }
6511 }
6512 }
6513 #endif
6514
6515
6516 #ifndef PRODUCT
6517
6518 // Implementation of LinearStatistic
6519
6520 const char* LinearScanStatistic::counter_name(int counter_idx) {
6521 switch (counter_idx) {
6522 case counter_method: return "compiled methods";
6523 case counter_fpu_method: return "methods using fpu";
6524 case counter_loop_method: return "methods with loops";
6525 case counter_exception_method:return "methods with xhandler";
6526
6527 case counter_loop: return "loops";
6528 case counter_block: return "blocks";
6529 case counter_loop_block: return "blocks inside loop";
6530 case counter_exception_block: return "exception handler entries";
6531 case counter_interval: return "intervals";
6532 case counter_fixed_interval: return "fixed intervals";
6533 case counter_range: return "ranges";
6534 case counter_fixed_range: return "fixed ranges";
6535 case counter_use_pos: return "use positions";
6536 case counter_fixed_use_pos: return "fixed use positions";
6537 case counter_spill_slots: return "spill slots";
6538
6539 // counter for classes of lir instructions
6540 case counter_instruction: return "total instructions";
6541 case counter_label: return "labels";
6542 case counter_entry: return "method entries";
6543 case counter_return: return "method returns";
6544 case counter_call: return "method calls";
6545 case counter_move: return "moves";
6546 case counter_cmp: return "compare";
6547 case counter_cond_branch: return "conditional branches";
6548 case counter_uncond_branch: return "unconditional branches";
6549 case counter_stub_branch: return "branches to stub";
6550 case counter_alu: return "artithmetic + logic";
6551 case counter_alloc: return "allocations";
6552 case counter_sync: return "synchronisation";
6553 case counter_throw: return "throw";
6554 case counter_unwind: return "unwind";
6555 case counter_typecheck: return "type+null-checks";
6556 case counter_fpu_stack: return "fpu-stack";
6557 case counter_misc_inst: return "other instructions";
6558 case counter_other_inst: return "misc. instructions";
6559
6560 // counter for different types of moves
6561 case counter_move_total: return "total moves";
6562 case counter_move_reg_reg: return "register->register";
6563 case counter_move_reg_stack: return "register->stack";
6564 case counter_move_stack_reg: return "stack->register";
6565 case counter_move_stack_stack:return "stack->stack";
6566 case counter_move_reg_mem: return "register->memory";
6567 case counter_move_mem_reg: return "memory->register";
6568 case counter_move_const_any: return "constant->any";
6569
6570 case blank_line_1: return "";
6571 case blank_line_2: return "";
6572
6573 default: ShouldNotReachHere(); return "";
6574 }
6575 }
6576
6577 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6578 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6579 return counter_method;
6580 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6581 return counter_block;
6582 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6583 return counter_instruction;
6584 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6585 return counter_move_total;
6586 }
6587 return invalid_counter;
6588 }
6589
6590 LinearScanStatistic::LinearScanStatistic() {
6591 for (int i = 0; i < number_of_counters; i++) {
6592 _counters_sum[i] = 0;
6593 _counters_max[i] = -1;
6594 }
6595
6596 }
6597
6598 // add the method-local numbers to the total sum
6599 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6600 for (int i = 0; i < number_of_counters; i++) {
6601 _counters_sum[i] += method_statistic._counters_sum[i];
6602 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6603 }
6604 }
6605
6606 void LinearScanStatistic::print(const char* title) {
6607 if (CountLinearScan || TraceLinearScanLevel > 0) {
6608 tty->cr();
6609 tty->print_cr("***** LinearScan statistic - %s *****", title);
6610
6611 for (int i = 0; i < number_of_counters; i++) {
6612 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6613 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6614
6615 LinearScanStatistic::Counter cntr = base_counter(i);
6616 if (cntr != invalid_counter) {
6617 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6618 } else {
6619 tty->print(" ");
6620 }
6621
6622 if (_counters_max[i] >= 0) {
6623 tty->print("%8d", _counters_max[i]);
6624 }
6625 }
6626 tty->cr();
6627 }
6628 }
6629 }
6630
6631 void LinearScanStatistic::collect(LinearScan* allocator) {
6632 inc_counter(counter_method);
6633 if (allocator->has_fpu_registers()) {
6634 inc_counter(counter_fpu_method);
6635 }
6636 if (allocator->num_loops() > 0) {
6637 inc_counter(counter_loop_method);
6638 }
6639 inc_counter(counter_loop, allocator->num_loops());
6640 inc_counter(counter_spill_slots, allocator->max_spills());
6641
6642 int i;
6643 for (i = 0; i < allocator->interval_count(); i++) {
6644 Interval* cur = allocator->interval_at(i);
6645
6646 if (cur != NULL) {
6647 inc_counter(counter_interval);
6648 inc_counter(counter_use_pos, cur->num_use_positions());
6649 if (LinearScan::is_precolored_interval(cur)) {
6650 inc_counter(counter_fixed_interval);
6651 inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6652 }
6653
6654 Range* range = cur->first();
6655 while (range != Range::end()) {
6656 inc_counter(counter_range);
6657 if (LinearScan::is_precolored_interval(cur)) {
6658 inc_counter(counter_fixed_range);
6659 }
6660 range = range->next();
6661 }
6662 }
6663 }
6664
6665 bool has_xhandlers = false;
6666 // Note: only count blocks that are in code-emit order
6667 for (i = 0; i < allocator->ir()->code()->length(); i++) {
6668 BlockBegin* cur = allocator->ir()->code()->at(i);
6669
6670 inc_counter(counter_block);
6671 if (cur->loop_depth() > 0) {
6672 inc_counter(counter_loop_block);
6673 }
6674 if (cur->is_set(BlockBegin::exception_entry_flag)) {
6675 inc_counter(counter_exception_block);
6676 has_xhandlers = true;
6677 }
6678
6679 LIR_OpList* instructions = cur->lir()->instructions_list();
6680 for (int j = 0; j < instructions->length(); j++) {
6681 LIR_Op* op = instructions->at(j);
6682
6683 inc_counter(counter_instruction);
6684
6685 switch (op->code()) {
6686 case lir_label: inc_counter(counter_label); break;
6687 case lir_std_entry:
6688 case lir_osr_entry: inc_counter(counter_entry); break;
6689 case lir_return: inc_counter(counter_return); break;
6690
6691 case lir_rtcall:
6692 case lir_static_call:
6693 case lir_optvirtual_call: inc_counter(counter_call); break;
6694
6695 case lir_move: {
6696 inc_counter(counter_move);
6697 inc_counter(counter_move_total);
6698
6699 LIR_Opr in = op->as_Op1()->in_opr();
6700 LIR_Opr res = op->as_Op1()->result_opr();
6701 if (in->is_register()) {
6702 if (res->is_register()) {
6703 inc_counter(counter_move_reg_reg);
6704 } else if (res->is_stack()) {
6705 inc_counter(counter_move_reg_stack);
6706 } else if (res->is_address()) {
6707 inc_counter(counter_move_reg_mem);
6708 } else {
6709 ShouldNotReachHere();
6710 }
6711 } else if (in->is_stack()) {
6712 if (res->is_register()) {
6713 inc_counter(counter_move_stack_reg);
6714 } else {
6715 inc_counter(counter_move_stack_stack);
6716 }
6717 } else if (in->is_address()) {
6718 assert(res->is_register(), "must be");
6719 inc_counter(counter_move_mem_reg);
6720 } else if (in->is_constant()) {
6721 inc_counter(counter_move_const_any);
6722 } else {
6723 ShouldNotReachHere();
6724 }
6725 break;
6726 }
6727
6728 case lir_cmp: inc_counter(counter_cmp); break;
6729
6730 case lir_branch:
6731 case lir_cond_float_branch: {
6732 LIR_OpBranch* branch = op->as_OpBranch();
6733 if (branch->block() == NULL) {
6734 inc_counter(counter_stub_branch);
6735 } else if (branch->cond() == lir_cond_always) {
6736 inc_counter(counter_uncond_branch);
6737 } else {
6738 inc_counter(counter_cond_branch);
6739 }
6740 break;
6741 }
6742
6743 case lir_neg:
6744 case lir_add:
6745 case lir_sub:
6746 case lir_mul:
6747 case lir_div:
6748 case lir_rem:
6749 case lir_sqrt:
6750 case lir_abs:
6751 case lir_log10:
6752 case lir_logic_and:
6753 case lir_logic_or:
6754 case lir_logic_xor:
6755 case lir_shl:
6756 case lir_shr:
6757 case lir_ushr: inc_counter(counter_alu); break;
6758
6759 case lir_alloc_object:
6760 case lir_alloc_array: inc_counter(counter_alloc); break;
6761
6762 case lir_monaddr:
6763 case lir_lock:
6764 case lir_unlock: inc_counter(counter_sync); break;
6765
6766 case lir_throw: inc_counter(counter_throw); break;
6767
6768 case lir_unwind: inc_counter(counter_unwind); break;
6769
6770 case lir_null_check:
6771 case lir_leal:
6772 case lir_instanceof:
6773 case lir_checkcast:
6774 case lir_store_check: inc_counter(counter_typecheck); break;
6775
6776 case lir_fpop_raw:
6777 case lir_fxch:
6778 case lir_fld: inc_counter(counter_fpu_stack); break;
6779
6780 case lir_nop:
6781 case lir_push:
6782 case lir_pop:
6783 case lir_convert:
6784 case lir_roundfp:
6785 case lir_cmove: inc_counter(counter_misc_inst); break;
6786
6787 default: inc_counter(counter_other_inst); break;
6788 }
6789 }
6790 }
6791
6792 if (has_xhandlers) {
6793 inc_counter(counter_exception_method);
6794 }
6795 }
6796
6797 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6798 if (CountLinearScan || TraceLinearScanLevel > 0) {
6799
6800 LinearScanStatistic local_statistic = LinearScanStatistic();
6801
6802 local_statistic.collect(allocator);
6803 global_statistic.sum_up(local_statistic);
6804
6805 if (TraceLinearScanLevel > 2) {
6806 local_statistic.print("current local statistic");
6807 }
6808 }
6809 }
6810
6811
6812 // Implementation of LinearTimers
6813
6814 LinearScanTimers::LinearScanTimers() {
6815 for (int i = 0; i < number_of_timers; i++) {
6816 timer(i)->reset();
6817 }
6818 }
6819
6820 const char* LinearScanTimers::timer_name(int idx) {
6821 switch (idx) {
6822 case timer_do_nothing: return "Nothing (Time Check)";
6823 case timer_number_instructions: return "Number Instructions";
6824 case timer_compute_local_live_sets: return "Local Live Sets";
6825 case timer_compute_global_live_sets: return "Global Live Sets";
6826 case timer_build_intervals: return "Build Intervals";
6827 case timer_sort_intervals_before: return "Sort Intervals Before";
6828 case timer_allocate_registers: return "Allocate Registers";
6829 case timer_resolve_data_flow: return "Resolve Data Flow";
6830 case timer_sort_intervals_after: return "Sort Intervals After";
6831 case timer_eliminate_spill_moves: return "Spill optimization";
6832 case timer_assign_reg_num: return "Assign Reg Num";
6833 case timer_allocate_fpu_stack: return "Allocate FPU Stack";
6834 case timer_optimize_lir: return "Optimize LIR";
6835 default: ShouldNotReachHere(); return "";
6836 }
6837 }
6838
6839 void LinearScanTimers::begin_method() {
6840 if (TimeEachLinearScan) {
6841 // reset all timers to measure only current method
6842 for (int i = 0; i < number_of_timers; i++) {
6843 timer(i)->reset();
6844 }
6845 }
6846 }
6847
6848 void LinearScanTimers::end_method(LinearScan* allocator) {
6849 if (TimeEachLinearScan) {
6850
6851 double c = timer(timer_do_nothing)->seconds();
6852 double total = 0;
6853 for (int i = 1; i < number_of_timers; i++) {
6854 total += timer(i)->seconds() - c;
6855 }
6856
6857 if (total >= 0.0005) {
6858 // print all information in one line for automatic processing
6859 tty->print("@"); allocator->compilation()->method()->print_name();
6860
6861 tty->print("@ %d ", allocator->compilation()->method()->code_size());
6862 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6863 tty->print("@ %d ", allocator->block_count());
6864 tty->print("@ %d ", allocator->num_virtual_regs());
6865 tty->print("@ %d ", allocator->interval_count());
6866 tty->print("@ %d ", allocator->_num_calls);
6867 tty->print("@ %d ", allocator->num_loops());
6868
6869 tty->print("@ %6.6f ", total);
6870 for (int i = 1; i < number_of_timers; i++) {
6871 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6872 }
6873 tty->cr();
6874 }
6875 }
6876 }
6877
6878 void LinearScanTimers::print(double total_time) {
6879 if (TimeLinearScan) {
6880 // correction value: sum of dummy-timer that only measures the time that
6881 // is necesary to start and stop itself
6882 double c = timer(timer_do_nothing)->seconds();
6883
6884 for (int i = 0; i < number_of_timers; i++) {
6885 double t = timer(i)->seconds();
6886 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6887 }
6888 }
6889 }
6890
6891 #endif // #ifndef PRODUCT