src/hotspot/share/c1/c1_LinearScan.cpp

@@ -1,7 +1,7 @@
  /*
-  * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved.
+  * Copyright (c) 2005, 2022, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.

@@ -1238,12 +1238,17 @@
          }
        }
        break;
      }
      case lir_cmove: {
+ #ifdef RISCV
+       assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4");
+       LIR_Op4* cmove = (LIR_Op4*)op;
+ #else
        assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
        LIR_Op2* cmove = (LIR_Op2*)op;
+ #endif
  
        LIR_Opr move_from = cmove->in_opr1();
        LIR_Opr move_to = cmove->result_opr();
  
        if (move_to->is_register() && move_from->is_register()) {

@@ -3136,17 +3141,21 @@
        allocate_fpu_stack(); // Only has effect on Intel
        NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
      }
    }
  
+ #ifndef RISCV
+   // Disable these optimizations on riscv temporarily, because it does not
+   // work when the comparison operands are bound to branches or cmoves.
    { TIME_LINEAR_SCAN(timer_optimize_lir);
  
      EdgeMoveOptimizer::optimize(ir()->code());
      ControlFlowOptimizer::optimize(ir()->code());
      // check that cfg is still correct after optimizations
      ir()->verify();
    }
+ #endif
  
    NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
    NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
    NOT_PRODUCT(_total_timer.end_method(this));
  }

@@ -6366,18 +6375,27 @@
  
                LIR_Op2* prev_cmp = NULL;
                // There might be a cmove inserted for profiling which depends on the same
                // compare. If we change the condition of the respective compare, we have
                // to take care of this cmove as well.
+ #ifdef RISCV
+               LIR_Op4* prev_cmove = NULL;
+ #else
                LIR_Op2* prev_cmove = NULL;
+ #endif
  
                for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
                  prev_op = instructions->at(j);
                  // check for the cmove
                  if (prev_op->code() == lir_cmove) {
+ #ifdef RISCV
+                   assert(prev_op->as_Op4() != NULL, "cmove must be of type LIR_Op4");
+                   prev_cmove = (LIR_Op4*)prev_op;
+ #else
                    assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
                    prev_cmove = (LIR_Op2*)prev_op;
+ #endif
                    assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
                  }
                  if (prev_op->code() == lir_cmp) {
                    assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
                    prev_cmp = (LIR_Op2*)prev_op;