1 /*
2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, Red Hat Inc.
4 * Copyright (c) 2021, Huawei Technologies Co., Ltd. All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 package sun.jvm.hotspot.debugger.riscv64;
28
29 import java.lang.annotation.Native;
30
31 import sun.jvm.hotspot.debugger.*;
32 import sun.jvm.hotspot.debugger.cdbg.*;
33
34 /** Specifies the thread context on riscv64 platforms; only a sub-portion
35 * of the context is guaranteed to be present on all operating
36 * systems. */
37
38 public abstract class RISCV64ThreadContext implements ThreadContext {
39 // Taken from /usr/include/asm/sigcontext.h on Linux/RISCV64.
40
41 // /*
42 // * Signal context structure - contains all info to do with the state
43 // * before the signal handler was invoked.
44 // */
45 // struct sigcontext {
46 // struct user_regs_struct sc_regs;
47 // union __riscv_fp_state sc_fpregs;
48 // };
49 //
50 // struct user_regs_struct {
51 // unsigned long pc;
52 // unsigned long ra;
53 // unsigned long sp;
54 // unsigned long gp;
55 // unsigned long tp;
56 // unsigned long t0;
57 // unsigned long t1;
58 // unsigned long t2;
59 // unsigned long s0;
60 // unsigned long s1;
61 // unsigned long a0;
62 // unsigned long a1;
63 // unsigned long a2;
64 // unsigned long a3;
65 // unsigned long a4;
66 // unsigned long a5;
67 // unsigned long a6;
68 // unsigned long a7;
69 // unsigned long s2;
70 // unsigned long s3;
71 // unsigned long s4;
72 // unsigned long s5;
73 // unsigned long s6;
74 // unsigned long s7;
75 // unsigned long s8;
76 // unsigned long s9;
77 // unsigned long s10;
78 // unsigned long s11;
79 // unsigned long t3;
80 // unsigned long t4;
81 // unsigned long t5;
82 // unsigned long t6;
83 // };
84
85 // NOTE: the indices for the various registers must be maintained as
86 // listed across various operating systems. However, only a small
87 // subset of the registers' values are guaranteed to be present (and
88 // must be present for the SA's stack walking to work)
89
90 // One instance of the Native annotation is enough to trigger header generation
91 // for this file.
92 @Native
93 public static final int R0 = 0;
94 public static final int R1 = 1;
95 public static final int R2 = 2;
96 public static final int R3 = 3;
97 public static final int R4 = 4;
98 public static final int R5 = 5;
99 public static final int R6 = 6;
100 public static final int R7 = 7;
101 public static final int R8 = 8;
102 public static final int R9 = 9;
103 public static final int R10 = 10;
104 public static final int R11 = 11;
105 public static final int R12 = 12;
106 public static final int R13 = 13;
107 public static final int R14 = 14;
108 public static final int R15 = 15;
109 public static final int R16 = 16;
110 public static final int R17 = 17;
111 public static final int R18 = 18;
112 public static final int R19 = 19;
113 public static final int R20 = 20;
114 public static final int R21 = 21;
115 public static final int R22 = 22;
116 public static final int R23 = 23;
117 public static final int R24 = 24;
118 public static final int R25 = 25;
119 public static final int R26 = 26;
120 public static final int R27 = 27;
121 public static final int R28 = 28;
122 public static final int R29 = 29;
123 public static final int R30 = 30;
124 public static final int R31 = 31;
125
126 public static final int NPRGREG = 32;
127
128 public static final int PC = R0;
129 public static final int LR = R1;
130 public static final int SP = R2;
131 public static final int FP = R8;
132
133 private long[] data;
134
135 public RISCV64ThreadContext() {
136 data = new long[NPRGREG];
137 }
138
139 public int getNumRegisters() {
140 return NPRGREG;
141 }
142
143 public String getRegisterName(int index) {
144 switch (index) {
145 case LR: return "lr";
146 case SP: return "sp";
147 case PC: return "pc";
148 default:
149 return "r" + index;
150 }
151 }
152
153 public void setRegister(int index, long value) {
154 data[index] = value;
155 }
156
157 public long getRegister(int index) {
158 return data[index];
159 }
160
161 public CFrame getTopFrame(Debugger dbg) {
162 return null;
163 }
164
165 /** This can't be implemented in this class since we would have to
166 * tie the implementation to, for example, the debugging system */
167 public abstract void setRegisterAsAddress(int index, Address value);
168
169 /** This can't be implemented in this class since we would have to
170 * tie the implementation to, for example, the debugging system */
171 public abstract Address getRegisterAsAddress(int index);
172 }