1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/gc_globals.hpp"
  40 #include "nativeInst_aarch64.hpp"
  41 #include "oops/objArrayKlass.hpp"
  42 #include "runtime/frame.inline.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 #include "vmreg_aarch64.inline.hpp"
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
  99 
 100 
 101 LIR_Opr LIR_Assembler::receiverOpr() {
 102   return FrameMap::receiver_opr;
 103 }
 104 
 105 LIR_Opr LIR_Assembler::osrBufferPointer() {
 106   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 107 }
 108 
 109 //--------------fpu register translations-----------------------
 110 
 111 
 112 address LIR_Assembler::float_constant(float f) {
 113   address const_addr = __ float_constant(f);
 114   if (const_addr == NULL) {
 115     bailout("const section overflow");
 116     return __ code()->consts()->start();
 117   } else {
 118     return const_addr;
 119   }
 120 }
 121 
 122 
 123 address LIR_Assembler::double_constant(double d) {
 124   address const_addr = __ double_constant(d);
 125   if (const_addr == NULL) {
 126     bailout("const section overflow");
 127     return __ code()->consts()->start();
 128   } else {
 129     return const_addr;
 130   }
 131 }
 132 
 133 address LIR_Assembler::int_constant(jlong n) {
 134   address const_addr = __ long_constant(n);
 135   if (const_addr == NULL) {
 136     bailout("const section overflow");
 137     return __ code()->consts()->start();
 138   } else {
 139     return const_addr;
 140   }
 141 }
 142 
 143 void LIR_Assembler::breakpoint() { Unimplemented(); }
 144 
 145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 146 
 147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 148 
 149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 150 //-------------------------------------------
 151 
 152 static Register as_reg(LIR_Opr op) {
 153   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 154 }
 155 
 156 static jlong as_long(LIR_Opr data) {
 157   jlong result;
 158   switch (data->type()) {
 159   case T_INT:
 160     result = (data->as_jint());
 161     break;
 162   case T_LONG:
 163     result = (data->as_jlong());
 164     break;
 165   default:
 166     ShouldNotReachHere();
 167     result = 0;  // unreachable
 168   }
 169   return result;
 170 }
 171 
 172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 173   Register base = addr->base()->as_pointer_register();
 174   LIR_Opr opr = addr->index();
 175   if (opr->is_cpu_register()) {
 176     Register index;
 177     if (opr->is_single_cpu())
 178       index = opr->as_register();
 179     else
 180       index = opr->as_register_lo();
 181     assert(addr->disp() == 0, "must be");
 182     switch(opr->type()) {
 183       case T_INT:
 184         return Address(base, index, Address::sxtw(addr->scale()));
 185       case T_LONG:
 186         return Address(base, index, Address::lsl(addr->scale()));
 187       default:
 188         ShouldNotReachHere();
 189       }
 190   } else  {
 191     intptr_t addr_offset = intptr_t(addr->disp());
 192     if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
 193       return Address(base, addr_offset, Address::lsl(addr->scale()));
 194     else {
 195       __ mov(tmp, addr_offset);
 196       return Address(base, tmp, Address::lsl(addr->scale()));
 197     }
 198   }
 199   return Address();
 200 }
 201 
 202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 203   ShouldNotReachHere();
 204   return Address();
 205 }
 206 
 207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 208   return as_Address(addr, rscratch1);
 209 }
 210 
 211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 212   return as_Address(addr, rscratch1);  // Ouch
 213   // FIXME: This needs to be much more clever.  See x86.
 214 }
 215 
 216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 217 // not encodable as a base + (immediate) offset, generate an explicit address
 218 // calculation to hold the address in a temporary register.
 219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 220   precond(size == 4 || size == 8);
 221   Address addr = frame_map()->address_for_slot(index, adjust);
 222   precond(addr.getMode() == Address::base_plus_offset);
 223   precond(addr.base() == sp);
 224   precond(addr.offset() > 0);
 225   uint mask = size - 1;
 226   assert((addr.offset() & mask) == 0, "scaled offsets only");
 227   return __ legitimize_address(addr, size, tmp);
 228 }
 229 
 230 void LIR_Assembler::osr_entry() {
 231   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 232   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 233   ValueStack* entry_state = osr_entry->state();
 234   int number_of_locks = entry_state->locks_size();
 235 
 236   // we jump here if osr happens with the interpreter
 237   // state set up to continue at the beginning of the
 238   // loop that triggered osr - in particular, we have
 239   // the following registers setup:
 240   //
 241   // r2: osr buffer
 242   //
 243 
 244   // build frame
 245   ciMethod* m = compilation()->method();
 246   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 247 
 248   // OSR buffer is
 249   //
 250   // locals[nlocals-1..0]
 251   // monitors[0..number_of_locks]
 252   //
 253   // locals is a direct copy of the interpreter frame so in the osr buffer
 254   // so first slot in the local array is the last local from the interpreter
 255   // and last slot is local[0] (receiver) from the interpreter
 256   //
 257   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 258   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 259   // in the interpreter frame (the method lock if a sync method)
 260 
 261   // Initialize monitors in the compiled activation.
 262   //   r2: pointer to osr buffer
 263   //
 264   // All other registers are dead at this point and the locals will be
 265   // copied into place by code emitted in the IR.
 266 
 267   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 268   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 269     int monitor_offset = BytesPerWord * method()->max_locals() +
 270       (2 * BytesPerWord) * (number_of_locks - 1);
 271     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 272     // the OSR buffer using 2 word entries: first the lock and then
 273     // the oop.
 274     for (int i = 0; i < number_of_locks; i++) {
 275       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 276 #ifdef ASSERT
 277       // verify the interpreter's monitor has a non-null object
 278       {
 279         Label L;
 280         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 281         __ cbnz(rscratch1, L);
 282         __ stop("locked object is NULL");
 283         __ bind(L);
 284       }
 285 #endif
 286       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 287       __ str(r19, frame_map()->address_for_monitor_lock(i));
 288       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 289       __ str(r19, frame_map()->address_for_monitor_object(i));
 290     }
 291   }
 292 }
 293 
 294 
 295 // inline cache check; done before the frame is built.
 296 int LIR_Assembler::check_icache() {
 297   Register receiver = FrameMap::receiver_opr->as_register();
 298   Register ic_klass = IC_Klass;
 299   int start_offset = __ offset();
 300   __ inline_cache_check(receiver, ic_klass);
 301 
 302   // if icache check fails, then jump to runtime routine
 303   // Note: RECEIVER must still contain the receiver!
 304   Label dont;
 305   __ br(Assembler::EQ, dont);
 306   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 307 
 308   // We align the verified entry point unless the method body
 309   // (including its inline cache check) will fit in a single 64-byte
 310   // icache line.
 311   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 312     // force alignment after the cache check.
 313     __ align(CodeEntryAlignment);
 314   }
 315 
 316   __ bind(dont);
 317   return start_offset;
 318 }
 319 
 320 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 321   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 322   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 323 
 324   Label L_skip_barrier;
 325 
 326   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 327   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 328   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 329   __ bind(L_skip_barrier);
 330 }
 331 
 332 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 333   if (o == NULL) {
 334     __ mov(reg, zr);
 335   } else {
 336     __ movoop(reg, o, /*immediate*/true);
 337   }
 338 }
 339 
 340 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 341   address target = NULL;
 342   relocInfo::relocType reloc_type = relocInfo::none;
 343 
 344   switch (patching_id(info)) {
 345   case PatchingStub::access_field_id:
 346     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 347     reloc_type = relocInfo::section_word_type;
 348     break;
 349   case PatchingStub::load_klass_id:
 350     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 351     reloc_type = relocInfo::metadata_type;
 352     break;
 353   case PatchingStub::load_mirror_id:
 354     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 355     reloc_type = relocInfo::oop_type;
 356     break;
 357   case PatchingStub::load_appendix_id:
 358     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 359     reloc_type = relocInfo::oop_type;
 360     break;
 361   default: ShouldNotReachHere();
 362   }
 363 
 364   __ far_call(RuntimeAddress(target));
 365   add_call_info_here(info);
 366 }
 367 
 368 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 369   deoptimize_trap(info);
 370 }
 371 
 372 
 373 // This specifies the rsp decrement needed to build the frame
 374 int LIR_Assembler::initial_frame_size_in_bytes() const {
 375   // if rounding, must let FrameMap know!
 376 
 377   return in_bytes(frame_map()->framesize_in_bytes());
 378 }
 379 
 380 
 381 int LIR_Assembler::emit_exception_handler() {
 382   // if the last instruction is a call (typically to do a throw which
 383   // is coming at the end after block reordering) the return address
 384   // must still point into the code area in order to avoid assertion
 385   // failures when searching for the corresponding bci => add a nop
 386   // (was bug 5/14/1999 - gri)
 387   __ nop();
 388 
 389   // generate code for exception handler
 390   address handler_base = __ start_a_stub(exception_handler_size());
 391   if (handler_base == NULL) {
 392     // not enough space left for the handler
 393     bailout("exception handler overflow");
 394     return -1;
 395   }
 396 
 397   int offset = code_offset();
 398 
 399   // the exception oop and pc are in r0, and r3
 400   // no other registers need to be preserved, so invalidate them
 401   __ invalidate_registers(false, true, true, false, true, true);
 402 
 403   // check that there is really an exception
 404   __ verify_not_null_oop(r0);
 405 
 406   // search an exception handler (r0: exception oop, r3: throwing pc)
 407   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 408   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 409   __ end_a_stub();
 410 
 411   return offset;
 412 }
 413 
 414 
 415 // Emit the code to remove the frame from the stack in the exception
 416 // unwind path.
 417 int LIR_Assembler::emit_unwind_handler() {
 418 #ifndef PRODUCT
 419   if (CommentedAssembly) {
 420     _masm->block_comment("Unwind handler");
 421   }
 422 #endif
 423 
 424   int offset = code_offset();
 425 
 426   // Fetch the exception from TLS and clear out exception related thread state
 427   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 428   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 429   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 430 
 431   __ bind(_unwind_handler_entry);
 432   __ verify_not_null_oop(r0);
 433   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 434     __ mov(r19, r0);  // Preserve the exception
 435   }
 436 
 437   // Preform needed unlocking
 438   MonitorExitStub* stub = NULL;
 439   if (method()->is_synchronized()) {
 440     monitor_address(0, FrameMap::r0_opr);
 441     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 442     __ unlock_object(r5, r4, r0, *stub->entry());
 443     __ bind(*stub->continuation());
 444   }
 445 
 446   if (compilation()->env()->dtrace_method_probes()) {
 447     __ mov(c_rarg0, rthread);
 448     __ mov_metadata(c_rarg1, method()->constant_encoding());
 449     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 450   }
 451 
 452   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 453     __ mov(r0, r19);  // Restore the exception
 454   }
 455 
 456   // remove the activation and dispatch to the unwind handler
 457   __ block_comment("remove_frame and dispatch to the unwind handler");
 458   __ remove_frame(initial_frame_size_in_bytes());
 459   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 460 
 461   // Emit the slow path assembly
 462   if (stub != NULL) {
 463     stub->emit_code(this);
 464   }
 465 
 466   return offset;
 467 }
 468 
 469 
 470 int LIR_Assembler::emit_deopt_handler() {
 471   // if the last instruction is a call (typically to do a throw which
 472   // is coming at the end after block reordering) the return address
 473   // must still point into the code area in order to avoid assertion
 474   // failures when searching for the corresponding bci => add a nop
 475   // (was bug 5/14/1999 - gri)
 476   __ nop();
 477 
 478   // generate code for exception handler
 479   address handler_base = __ start_a_stub(deopt_handler_size());
 480   if (handler_base == NULL) {
 481     // not enough space left for the handler
 482     bailout("deopt handler overflow");
 483     return -1;
 484   }
 485 
 486   int offset = code_offset();
 487 
 488   __ adr(lr, pc());
 489   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 490   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 491   __ end_a_stub();
 492 
 493   return offset;
 494 }
 495 
 496 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 497   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 498   int pc_offset = code_offset();
 499   flush_debug_info(pc_offset);
 500   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 501   if (info->exception_handlers() != NULL) {
 502     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 503   }
 504 }
 505 
 506 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 507   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 508 
 509   // Pop the stack before the safepoint code
 510   __ remove_frame(initial_frame_size_in_bytes());
 511 
 512   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 513     __ reserved_stack_check();
 514   }
 515 
 516   code_stub->set_safepoint_offset(__ offset());
 517   __ relocate(relocInfo::poll_return_type);
 518   __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
 519   __ ret(lr);
 520 }
 521 
 522 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 523   guarantee(info != NULL, "Shouldn't be NULL");
 524   __ get_polling_page(rscratch1, relocInfo::poll_type);
 525   add_debug_info_for_branch(info);  // This isn't just debug info:
 526                                     // it's the oop map
 527   __ read_polling_page(rscratch1, relocInfo::poll_type);
 528   return __ offset();
 529 }
 530 
 531 
 532 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 533   if (from_reg == r31_sp)
 534     from_reg = sp;
 535   if (to_reg == r31_sp)
 536     to_reg = sp;
 537   __ mov(to_reg, from_reg);
 538 }
 539 
 540 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 541 
 542 
 543 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 544   assert(src->is_constant(), "should not call otherwise");
 545   assert(dest->is_register(), "should not call otherwise");
 546   LIR_Const* c = src->as_constant_ptr();
 547 
 548   switch (c->type()) {
 549     case T_INT: {
 550       assert(patch_code == lir_patch_none, "no patching handled here");
 551       __ movw(dest->as_register(), c->as_jint());
 552       break;
 553     }
 554 
 555     case T_ADDRESS: {
 556       assert(patch_code == lir_patch_none, "no patching handled here");
 557       __ mov(dest->as_register(), c->as_jint());
 558       break;
 559     }
 560 
 561     case T_LONG: {
 562       assert(patch_code == lir_patch_none, "no patching handled here");
 563       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 564       break;
 565     }
 566 
 567     case T_OBJECT: {
 568         if (patch_code == lir_patch_none) {
 569           jobject2reg(c->as_jobject(), dest->as_register());
 570         } else {
 571           jobject2reg_with_patching(dest->as_register(), info);
 572         }
 573       break;
 574     }
 575 
 576     case T_METADATA: {
 577       if (patch_code != lir_patch_none) {
 578         klass2reg_with_patching(dest->as_register(), info);
 579       } else {
 580         __ mov_metadata(dest->as_register(), c->as_metadata());
 581       }
 582       break;
 583     }
 584 
 585     case T_FLOAT: {
 586       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 587         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 588       } else {
 589         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 590         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 591       }
 592       break;
 593     }
 594 
 595     case T_DOUBLE: {
 596       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 597         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 598       } else {
 599         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 600         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 601       }
 602       break;
 603     }
 604 
 605     default:
 606       ShouldNotReachHere();
 607   }
 608 }
 609 
 610 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 611   LIR_Const* c = src->as_constant_ptr();
 612   switch (c->type()) {
 613   case T_OBJECT:
 614     {
 615       if (! c->as_jobject())
 616         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 617       else {
 618         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 619         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 620       }
 621     }
 622     break;
 623   case T_ADDRESS:
 624     {
 625       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 626       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 627     }
 628   case T_INT:
 629   case T_FLOAT:
 630     {
 631       Register reg = zr;
 632       if (c->as_jint_bits() == 0)
 633         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 634       else {
 635         __ movw(rscratch1, c->as_jint_bits());
 636         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 637       }
 638     }
 639     break;
 640   case T_LONG:
 641   case T_DOUBLE:
 642     {
 643       Register reg = zr;
 644       if (c->as_jlong_bits() == 0)
 645         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 646                                                  lo_word_offset_in_bytes));
 647       else {
 648         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 649         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 650                                                         lo_word_offset_in_bytes));
 651       }
 652     }
 653     break;
 654   default:
 655     ShouldNotReachHere();
 656   }
 657 }
 658 
 659 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 660   assert(src->is_constant(), "should not call otherwise");
 661   LIR_Const* c = src->as_constant_ptr();
 662   LIR_Address* to_addr = dest->as_address_ptr();
 663 
 664   void (Assembler::* insn)(Register Rt, const Address &adr);
 665 
 666   switch (type) {
 667   case T_ADDRESS:
 668     assert(c->as_jint() == 0, "should be");
 669     insn = &Assembler::str;
 670     break;
 671   case T_LONG:
 672     assert(c->as_jlong() == 0, "should be");
 673     insn = &Assembler::str;
 674     break;
 675   case T_INT:
 676     assert(c->as_jint() == 0, "should be");
 677     insn = &Assembler::strw;
 678     break;
 679   case T_OBJECT:
 680   case T_ARRAY:
 681     assert(c->as_jobject() == 0, "should be");
 682     if (UseCompressedOops && !wide) {
 683       insn = &Assembler::strw;
 684     } else {
 685       insn = &Assembler::str;
 686     }
 687     break;
 688   case T_CHAR:
 689   case T_SHORT:
 690     assert(c->as_jint() == 0, "should be");
 691     insn = &Assembler::strh;
 692     break;
 693   case T_BOOLEAN:
 694   case T_BYTE:
 695     assert(c->as_jint() == 0, "should be");
 696     insn = &Assembler::strb;
 697     break;
 698   default:
 699     ShouldNotReachHere();
 700     insn = &Assembler::str;  // unreachable
 701   }
 702 
 703   if (info) add_debug_info_for_null_check_here(info);
 704   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 705 }
 706 
 707 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 708   assert(src->is_register(), "should not call otherwise");
 709   assert(dest->is_register(), "should not call otherwise");
 710 
 711   // move between cpu-registers
 712   if (dest->is_single_cpu()) {
 713     if (src->type() == T_LONG) {
 714       // Can do LONG -> OBJECT
 715       move_regs(src->as_register_lo(), dest->as_register());
 716       return;
 717     }
 718     assert(src->is_single_cpu(), "must match");
 719     if (src->type() == T_OBJECT) {
 720       __ verify_oop(src->as_register());
 721     }
 722     move_regs(src->as_register(), dest->as_register());
 723 
 724   } else if (dest->is_double_cpu()) {
 725     if (is_reference_type(src->type())) {
 726       // Surprising to me but we can see move of a long to t_object
 727       __ verify_oop(src->as_register());
 728       move_regs(src->as_register(), dest->as_register_lo());
 729       return;
 730     }
 731     assert(src->is_double_cpu(), "must match");
 732     Register f_lo = src->as_register_lo();
 733     Register f_hi = src->as_register_hi();
 734     Register t_lo = dest->as_register_lo();
 735     Register t_hi = dest->as_register_hi();
 736     assert(f_hi == f_lo, "must be same");
 737     assert(t_hi == t_lo, "must be same");
 738     move_regs(f_lo, t_lo);
 739 
 740   } else if (dest->is_single_fpu()) {
 741     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 742 
 743   } else if (dest->is_double_fpu()) {
 744     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 745 
 746   } else {
 747     ShouldNotReachHere();
 748   }
 749 }
 750 
 751 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 752   precond(src->is_register() && dest->is_stack());
 753 
 754   uint const c_sz32 = sizeof(uint32_t);
 755   uint const c_sz64 = sizeof(uint64_t);
 756 
 757   if (src->is_single_cpu()) {
 758     int index = dest->single_stack_ix();
 759     if (is_reference_type(type)) {
 760       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 761       __ verify_oop(src->as_register());
 762     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 763       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 764     } else {
 765       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 766     }
 767 
 768   } else if (src->is_double_cpu()) {
 769     int index = dest->double_stack_ix();
 770     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 771     __ str(src->as_register_lo(), dest_addr_LO);
 772 
 773   } else if (src->is_single_fpu()) {
 774     int index = dest->single_stack_ix();
 775     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 776 
 777   } else if (src->is_double_fpu()) {
 778     int index = dest->double_stack_ix();
 779     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 780 
 781   } else {
 782     ShouldNotReachHere();
 783   }
 784 }
 785 
 786 
 787 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 788   LIR_Address* to_addr = dest->as_address_ptr();
 789   PatchingStub* patch = NULL;
 790   Register compressed_src = rscratch1;
 791 
 792   if (patch_code != lir_patch_none) {
 793     deoptimize_trap(info);
 794     return;
 795   }
 796 
 797   if (is_reference_type(type)) {
 798     __ verify_oop(src->as_register());
 799 
 800     if (UseCompressedOops && !wide) {
 801       __ encode_heap_oop(compressed_src, src->as_register());
 802     } else {
 803       compressed_src = src->as_register();
 804     }
 805   }
 806 
 807   int null_check_here = code_offset();
 808   switch (type) {
 809     case T_FLOAT: {
 810       __ strs(src->as_float_reg(), as_Address(to_addr));
 811       break;
 812     }
 813 
 814     case T_DOUBLE: {
 815       __ strd(src->as_double_reg(), as_Address(to_addr));
 816       break;
 817     }
 818 
 819     case T_ARRAY:   // fall through
 820     case T_OBJECT:  // fall through
 821       if (UseCompressedOops && !wide) {
 822         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 823       } else {
 824          __ str(compressed_src, as_Address(to_addr));
 825       }
 826       break;
 827     case T_METADATA:
 828       // We get here to store a method pointer to the stack to pass to
 829       // a dtrace runtime call. This can't work on 64 bit with
 830       // compressed klass ptrs: T_METADATA can be a compressed klass
 831       // ptr or a 64 bit method pointer.
 832       ShouldNotReachHere();
 833       __ str(src->as_register(), as_Address(to_addr));
 834       break;
 835     case T_ADDRESS:
 836       __ str(src->as_register(), as_Address(to_addr));
 837       break;
 838     case T_INT:
 839       __ strw(src->as_register(), as_Address(to_addr));
 840       break;
 841 
 842     case T_LONG: {
 843       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 844       break;
 845     }
 846 
 847     case T_BYTE:    // fall through
 848     case T_BOOLEAN: {
 849       __ strb(src->as_register(), as_Address(to_addr));
 850       break;
 851     }
 852 
 853     case T_CHAR:    // fall through
 854     case T_SHORT:
 855       __ strh(src->as_register(), as_Address(to_addr));
 856       break;
 857 
 858     default:
 859       ShouldNotReachHere();
 860   }
 861   if (info != NULL) {
 862     add_debug_info_for_null_check(null_check_here, info);
 863   }
 864 }
 865 
 866 
 867 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 868   precond(src->is_stack() && dest->is_register());
 869 
 870   uint const c_sz32 = sizeof(uint32_t);
 871   uint const c_sz64 = sizeof(uint64_t);
 872 
 873   if (dest->is_single_cpu()) {
 874     int index = src->single_stack_ix();
 875     if (is_reference_type(type)) {
 876       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 877       __ verify_oop(dest->as_register());
 878     } else if (type == T_METADATA || type == T_ADDRESS) {
 879       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 880     } else {
 881       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 882     }
 883 
 884   } else if (dest->is_double_cpu()) {
 885     int index = src->double_stack_ix();
 886     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 887     __ ldr(dest->as_register_lo(), src_addr_LO);
 888 
 889   } else if (dest->is_single_fpu()) {
 890     int index = src->single_stack_ix();
 891     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 892 
 893   } else if (dest->is_double_fpu()) {
 894     int index = src->double_stack_ix();
 895     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 896 
 897   } else {
 898     ShouldNotReachHere();
 899   }
 900 }
 901 
 902 
 903 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 904   address target = NULL;
 905   relocInfo::relocType reloc_type = relocInfo::none;
 906 
 907   switch (patching_id(info)) {
 908   case PatchingStub::access_field_id:
 909     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 910     reloc_type = relocInfo::section_word_type;
 911     break;
 912   case PatchingStub::load_klass_id:
 913     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 914     reloc_type = relocInfo::metadata_type;
 915     break;
 916   case PatchingStub::load_mirror_id:
 917     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 918     reloc_type = relocInfo::oop_type;
 919     break;
 920   case PatchingStub::load_appendix_id:
 921     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 922     reloc_type = relocInfo::oop_type;
 923     break;
 924   default: ShouldNotReachHere();
 925   }
 926 
 927   __ far_call(RuntimeAddress(target));
 928   add_call_info_here(info);
 929 }
 930 
 931 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 932 
 933   LIR_Opr temp;
 934   if (type == T_LONG || type == T_DOUBLE)
 935     temp = FrameMap::rscratch1_long_opr;
 936   else
 937     temp = FrameMap::rscratch1_opr;
 938 
 939   stack2reg(src, temp, src->type());
 940   reg2stack(temp, dest, dest->type(), false);
 941 }
 942 
 943 
 944 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 945   LIR_Address* addr = src->as_address_ptr();
 946   LIR_Address* from_addr = src->as_address_ptr();
 947 
 948   if (addr->base()->type() == T_OBJECT) {
 949     __ verify_oop(addr->base()->as_pointer_register());
 950   }
 951 
 952   if (patch_code != lir_patch_none) {
 953     deoptimize_trap(info);
 954     return;
 955   }
 956 
 957   if (info != NULL) {
 958     add_debug_info_for_null_check_here(info);
 959   }
 960   int null_check_here = code_offset();
 961   switch (type) {
 962     case T_FLOAT: {
 963       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 964       break;
 965     }
 966 
 967     case T_DOUBLE: {
 968       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 969       break;
 970     }
 971 
 972     case T_ARRAY:   // fall through
 973     case T_OBJECT:  // fall through
 974       if (UseCompressedOops && !wide) {
 975         __ ldrw(dest->as_register(), as_Address(from_addr));
 976       } else {
 977          __ ldr(dest->as_register(), as_Address(from_addr));
 978       }
 979       break;
 980     case T_METADATA:
 981       // We get here to store a method pointer to the stack to pass to
 982       // a dtrace runtime call. This can't work on 64 bit with
 983       // compressed klass ptrs: T_METADATA can be a compressed klass
 984       // ptr or a 64 bit method pointer.
 985       ShouldNotReachHere();
 986       __ ldr(dest->as_register(), as_Address(from_addr));
 987       break;
 988     case T_ADDRESS:
 989       __ ldr(dest->as_register(), as_Address(from_addr));
 990       break;
 991     case T_INT:
 992       __ ldrw(dest->as_register(), as_Address(from_addr));
 993       break;
 994 
 995     case T_LONG: {
 996       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
 997       break;
 998     }
 999 
1000     case T_BYTE:
1001       __ ldrsb(dest->as_register(), as_Address(from_addr));
1002       break;
1003     case T_BOOLEAN: {
1004       __ ldrb(dest->as_register(), as_Address(from_addr));
1005       break;
1006     }
1007 
1008     case T_CHAR:
1009       __ ldrh(dest->as_register(), as_Address(from_addr));
1010       break;
1011     case T_SHORT:
1012       __ ldrsh(dest->as_register(), as_Address(from_addr));
1013       break;
1014 
1015     default:
1016       ShouldNotReachHere();
1017   }
1018 
1019   if (is_reference_type(type)) {
1020     if (UseCompressedOops && !wide) {
1021       __ decode_heap_oop(dest->as_register());
1022     }
1023 
1024     if (!UseZGC) {
1025       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1026       __ verify_oop(dest->as_register());
1027     }
1028   }
1029 }
1030 
1031 
1032 int LIR_Assembler::array_element_size(BasicType type) const {
1033   int elem_size = type2aelembytes(type);
1034   return exact_log2(elem_size);
1035 }
1036 
1037 
1038 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1039   switch (op->code()) {
1040   case lir_idiv:
1041   case lir_irem:
1042     arithmetic_idiv(op->code(),
1043                     op->in_opr1(),
1044                     op->in_opr2(),
1045                     op->in_opr3(),
1046                     op->result_opr(),
1047                     op->info());
1048     break;
1049   case lir_fmad:
1050     __ fmaddd(op->result_opr()->as_double_reg(),
1051               op->in_opr1()->as_double_reg(),
1052               op->in_opr2()->as_double_reg(),
1053               op->in_opr3()->as_double_reg());
1054     break;
1055   case lir_fmaf:
1056     __ fmadds(op->result_opr()->as_float_reg(),
1057               op->in_opr1()->as_float_reg(),
1058               op->in_opr2()->as_float_reg(),
1059               op->in_opr3()->as_float_reg());
1060     break;
1061   default:      ShouldNotReachHere(); break;
1062   }
1063 }
1064 
1065 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1066 #ifdef ASSERT
1067   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1068   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1069   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1070 #endif
1071 
1072   if (op->cond() == lir_cond_always) {
1073     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1074     __ b(*(op->label()));
1075   } else {
1076     Assembler::Condition acond;
1077     if (op->code() == lir_cond_float_branch) {
1078       bool is_unordered = (op->ublock() == op->block());
1079       // Assembler::EQ does not permit unordered branches, so we add
1080       // another branch here.  Likewise, Assembler::NE does not permit
1081       // ordered branches.
1082       if ((is_unordered && op->cond() == lir_cond_equal)
1083           || (!is_unordered && op->cond() == lir_cond_notEqual))
1084         __ br(Assembler::VS, *(op->ublock()->label()));
1085       switch(op->cond()) {
1086       case lir_cond_equal:        acond = Assembler::EQ; break;
1087       case lir_cond_notEqual:     acond = Assembler::NE; break;
1088       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1089       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1090       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1091       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1092       default:                    ShouldNotReachHere();
1093         acond = Assembler::EQ;  // unreachable
1094       }
1095     } else {
1096       switch (op->cond()) {
1097         case lir_cond_equal:        acond = Assembler::EQ; break;
1098         case lir_cond_notEqual:     acond = Assembler::NE; break;
1099         case lir_cond_less:         acond = Assembler::LT; break;
1100         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1101         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1102         case lir_cond_greater:      acond = Assembler::GT; break;
1103         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1104         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1105         default:                    ShouldNotReachHere();
1106           acond = Assembler::EQ;  // unreachable
1107       }
1108     }
1109     __ br(acond,*(op->label()));
1110   }
1111 }
1112 
1113 
1114 
1115 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1116   LIR_Opr src  = op->in_opr();
1117   LIR_Opr dest = op->result_opr();
1118 
1119   switch (op->bytecode()) {
1120     case Bytecodes::_i2f:
1121       {
1122         __ scvtfws(dest->as_float_reg(), src->as_register());
1123         break;
1124       }
1125     case Bytecodes::_i2d:
1126       {
1127         __ scvtfwd(dest->as_double_reg(), src->as_register());
1128         break;
1129       }
1130     case Bytecodes::_l2d:
1131       {
1132         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1133         break;
1134       }
1135     case Bytecodes::_l2f:
1136       {
1137         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1138         break;
1139       }
1140     case Bytecodes::_f2d:
1141       {
1142         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1143         break;
1144       }
1145     case Bytecodes::_d2f:
1146       {
1147         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1148         break;
1149       }
1150     case Bytecodes::_i2c:
1151       {
1152         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1153         break;
1154       }
1155     case Bytecodes::_i2l:
1156       {
1157         __ sxtw(dest->as_register_lo(), src->as_register());
1158         break;
1159       }
1160     case Bytecodes::_i2s:
1161       {
1162         __ sxth(dest->as_register(), src->as_register());
1163         break;
1164       }
1165     case Bytecodes::_i2b:
1166       {
1167         __ sxtb(dest->as_register(), src->as_register());
1168         break;
1169       }
1170     case Bytecodes::_l2i:
1171       {
1172         _masm->block_comment("FIXME: This could be a no-op");
1173         __ uxtw(dest->as_register(), src->as_register_lo());
1174         break;
1175       }
1176     case Bytecodes::_d2l:
1177       {
1178         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1179         break;
1180       }
1181     case Bytecodes::_f2i:
1182       {
1183         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1184         break;
1185       }
1186     case Bytecodes::_f2l:
1187       {
1188         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1189         break;
1190       }
1191     case Bytecodes::_d2i:
1192       {
1193         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1194         break;
1195       }
1196     default: ShouldNotReachHere();
1197   }
1198 }
1199 
1200 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1201   if (op->init_check()) {
1202     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1203                                InstanceKlass::init_state_offset()));
1204     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1205     add_debug_info_for_null_check_here(op->stub()->info());
1206     __ br(Assembler::NE, *op->stub()->entry());
1207   }
1208   __ allocate_object(op->obj()->as_register(),
1209                      op->tmp1()->as_register(),
1210                      op->tmp2()->as_register(),
1211                      op->header_size(),
1212                      op->object_size(),
1213                      op->klass()->as_register(),
1214                      *op->stub()->entry());
1215   __ bind(*op->stub()->continuation());
1216 }
1217 
1218 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1219   Register len =  op->len()->as_register();
1220   __ uxtw(len, len);
1221 
1222   if (UseSlowPath ||
1223       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1224       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1225     __ b(*op->stub()->entry());
1226   } else {
1227     Register tmp1 = op->tmp1()->as_register();
1228     Register tmp2 = op->tmp2()->as_register();
1229     Register tmp3 = op->tmp3()->as_register();
1230     if (len == tmp1) {
1231       tmp1 = tmp3;
1232     } else if (len == tmp2) {
1233       tmp2 = tmp3;
1234     } else if (len == tmp3) {
1235       // everything is ok
1236     } else {
1237       __ mov(tmp3, len);
1238     }
1239     __ allocate_array(op->obj()->as_register(),
1240                       len,
1241                       tmp1,
1242                       tmp2,
1243                       arrayOopDesc::header_size(op->type()),
1244                       array_element_size(op->type()),
1245                       op->klass()->as_register(),
1246                       *op->stub()->entry());
1247   }
1248   __ bind(*op->stub()->continuation());
1249 }
1250 
1251 void LIR_Assembler::type_profile_helper(Register mdo,
1252                                         ciMethodData *md, ciProfileData *data,
1253                                         Register recv, Label* update_done) {
1254   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1255     Label next_test;
1256     // See if the receiver is receiver[n].
1257     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1258     __ ldr(rscratch1, Address(rscratch2));
1259     __ cmp(recv, rscratch1);
1260     __ br(Assembler::NE, next_test);
1261     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1262     __ addptr(data_addr, DataLayout::counter_increment);
1263     __ b(*update_done);
1264     __ bind(next_test);
1265   }
1266 
1267   // Didn't find receiver; find next empty slot and fill it in
1268   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1269     Label next_test;
1270     __ lea(rscratch2,
1271            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1272     Address recv_addr(rscratch2);
1273     __ ldr(rscratch1, recv_addr);
1274     __ cbnz(rscratch1, next_test);
1275     __ str(recv, recv_addr);
1276     __ mov(rscratch1, DataLayout::counter_increment);
1277     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1278     __ str(rscratch1, Address(rscratch2));
1279     __ b(*update_done);
1280     __ bind(next_test);
1281   }
1282 }
1283 
1284 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1285   // we always need a stub for the failure case.
1286   CodeStub* stub = op->stub();
1287   Register obj = op->object()->as_register();
1288   Register k_RInfo = op->tmp1()->as_register();
1289   Register klass_RInfo = op->tmp2()->as_register();
1290   Register dst = op->result_opr()->as_register();
1291   ciKlass* k = op->klass();
1292   Register Rtmp1 = noreg;
1293 
1294   // check if it needs to be profiled
1295   ciMethodData* md;
1296   ciProfileData* data;
1297 
1298   const bool should_profile = op->should_profile();
1299 
1300   if (should_profile) {
1301     ciMethod* method = op->profiled_method();
1302     assert(method != NULL, "Should have method");
1303     int bci = op->profiled_bci();
1304     md = method->method_data_or_null();
1305     assert(md != NULL, "Sanity");
1306     data = md->bci_to_data(bci);
1307     assert(data != NULL,                "need data for type check");
1308     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1309   }
1310   Label profile_cast_success, profile_cast_failure;
1311   Label *success_target = should_profile ? &profile_cast_success : success;
1312   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1313 
1314   if (obj == k_RInfo) {
1315     k_RInfo = dst;
1316   } else if (obj == klass_RInfo) {
1317     klass_RInfo = dst;
1318   }
1319   if (k->is_loaded() && !UseCompressedClassPointers) {
1320     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1321   } else {
1322     Rtmp1 = op->tmp3()->as_register();
1323     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1324   }
1325 
1326   assert_different_registers(obj, k_RInfo, klass_RInfo);
1327 
1328     if (should_profile) {
1329       Label not_null;
1330       __ cbnz(obj, not_null);
1331       // Object is null; update MDO and exit
1332       Register mdo  = klass_RInfo;
1333       __ mov_metadata(mdo, md->constant_encoding());
1334       Address data_addr
1335         = __ form_address(rscratch2, mdo,
1336                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1337                           0);
1338       __ ldrb(rscratch1, data_addr);
1339       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1340       __ strb(rscratch1, data_addr);
1341       __ b(*obj_is_null);
1342       __ bind(not_null);
1343     } else {
1344       __ cbz(obj, *obj_is_null);
1345     }
1346 
1347   if (!k->is_loaded()) {
1348     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1349   } else {
1350     __ mov_metadata(k_RInfo, k->constant_encoding());
1351   }
1352   __ verify_oop(obj);
1353 
1354   if (op->fast_check()) {
1355     // get object class
1356     // not a safepoint as obj null check happens earlier
1357     __ load_klass(rscratch1, obj);
1358     __ cmp( rscratch1, k_RInfo);
1359 
1360     __ br(Assembler::NE, *failure_target);
1361     // successful cast, fall through to profile or jump
1362   } else {
1363     // get object class
1364     // not a safepoint as obj null check happens earlier
1365     __ load_klass(klass_RInfo, obj);
1366     if (k->is_loaded()) {
1367       // See if we get an immediate positive hit
1368       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1369       __ cmp(k_RInfo, rscratch1);
1370       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1371         __ br(Assembler::NE, *failure_target);
1372         // successful cast, fall through to profile or jump
1373       } else {
1374         // See if we get an immediate positive hit
1375         __ br(Assembler::EQ, *success_target);
1376         // check for self
1377         __ cmp(klass_RInfo, k_RInfo);
1378         __ br(Assembler::EQ, *success_target);
1379 
1380         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1381         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1382         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1383         // result is a boolean
1384         __ cbzw(klass_RInfo, *failure_target);
1385         // successful cast, fall through to profile or jump
1386       }
1387     } else {
1388       // perform the fast part of the checking logic
1389       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1390       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1391       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1392       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1393       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1394       // result is a boolean
1395       __ cbz(k_RInfo, *failure_target);
1396       // successful cast, fall through to profile or jump
1397     }
1398   }
1399   if (should_profile) {
1400     Register mdo  = klass_RInfo, recv = k_RInfo;
1401     __ bind(profile_cast_success);
1402     __ mov_metadata(mdo, md->constant_encoding());
1403     __ load_klass(recv, obj);
1404     Label update_done;
1405     type_profile_helper(mdo, md, data, recv, success);
1406     __ b(*success);
1407 
1408     __ bind(profile_cast_failure);
1409     __ mov_metadata(mdo, md->constant_encoding());
1410     Address counter_addr
1411       = __ form_address(rscratch2, mdo,
1412                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1413                         0);
1414     __ ldr(rscratch1, counter_addr);
1415     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1416     __ str(rscratch1, counter_addr);
1417     __ b(*failure);
1418   }
1419   __ b(*success);
1420 }
1421 
1422 
1423 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1424   const bool should_profile = op->should_profile();
1425 
1426   LIR_Code code = op->code();
1427   if (code == lir_store_check) {
1428     Register value = op->object()->as_register();
1429     Register array = op->array()->as_register();
1430     Register k_RInfo = op->tmp1()->as_register();
1431     Register klass_RInfo = op->tmp2()->as_register();
1432     Register Rtmp1 = op->tmp3()->as_register();
1433 
1434     CodeStub* stub = op->stub();
1435 
1436     // check if it needs to be profiled
1437     ciMethodData* md;
1438     ciProfileData* data;
1439 
1440     if (should_profile) {
1441       ciMethod* method = op->profiled_method();
1442       assert(method != NULL, "Should have method");
1443       int bci = op->profiled_bci();
1444       md = method->method_data_or_null();
1445       assert(md != NULL, "Sanity");
1446       data = md->bci_to_data(bci);
1447       assert(data != NULL,                "need data for type check");
1448       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1449     }
1450     Label profile_cast_success, profile_cast_failure, done;
1451     Label *success_target = should_profile ? &profile_cast_success : &done;
1452     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1453 
1454     if (should_profile) {
1455       Label not_null;
1456       __ cbnz(value, not_null);
1457       // Object is null; update MDO and exit
1458       Register mdo  = klass_RInfo;
1459       __ mov_metadata(mdo, md->constant_encoding());
1460       Address data_addr
1461         = __ form_address(rscratch2, mdo,
1462                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1463                           0);
1464       __ ldrb(rscratch1, data_addr);
1465       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1466       __ strb(rscratch1, data_addr);
1467       __ b(done);
1468       __ bind(not_null);
1469     } else {
1470       __ cbz(value, done);
1471     }
1472 
1473     add_debug_info_for_null_check_here(op->info_for_exception());
1474     __ load_klass(k_RInfo, array);
1475     __ load_klass(klass_RInfo, value);
1476 
1477     // get instance klass (it's already uncompressed)
1478     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1479     // perform the fast part of the checking logic
1480     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1481     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1482     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1483     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1484     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1485     // result is a boolean
1486     __ cbzw(k_RInfo, *failure_target);
1487     // fall through to the success case
1488 
1489     if (should_profile) {
1490       Register mdo  = klass_RInfo, recv = k_RInfo;
1491       __ bind(profile_cast_success);
1492       __ mov_metadata(mdo, md->constant_encoding());
1493       __ load_klass(recv, value);
1494       Label update_done;
1495       type_profile_helper(mdo, md, data, recv, &done);
1496       __ b(done);
1497 
1498       __ bind(profile_cast_failure);
1499       __ mov_metadata(mdo, md->constant_encoding());
1500       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1501       __ lea(rscratch2, counter_addr);
1502       __ ldr(rscratch1, Address(rscratch2));
1503       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1504       __ str(rscratch1, Address(rscratch2));
1505       __ b(*stub->entry());
1506     }
1507 
1508     __ bind(done);
1509   } else if (code == lir_checkcast) {
1510     Register obj = op->object()->as_register();
1511     Register dst = op->result_opr()->as_register();
1512     Label success;
1513     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1514     __ bind(success);
1515     if (dst != obj) {
1516       __ mov(dst, obj);
1517     }
1518   } else if (code == lir_instanceof) {
1519     Register obj = op->object()->as_register();
1520     Register dst = op->result_opr()->as_register();
1521     Label success, failure, done;
1522     emit_typecheck_helper(op, &success, &failure, &failure);
1523     __ bind(failure);
1524     __ mov(dst, zr);
1525     __ b(done);
1526     __ bind(success);
1527     __ mov(dst, 1);
1528     __ bind(done);
1529   } else {
1530     ShouldNotReachHere();
1531   }
1532 }
1533 
1534 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1535   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1536   __ cset(rscratch1, Assembler::NE);
1537   __ membar(__ AnyAny);
1538 }
1539 
1540 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1541   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1542   __ cset(rscratch1, Assembler::NE);
1543   __ membar(__ AnyAny);
1544 }
1545 
1546 
1547 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1548   assert(VM_Version::supports_cx8(), "wrong machine");
1549   Register addr;
1550   if (op->addr()->is_register()) {
1551     addr = as_reg(op->addr());
1552   } else {
1553     assert(op->addr()->is_address(), "what else?");
1554     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1555     assert(addr_ptr->disp() == 0, "need 0 disp");
1556     assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1557     addr = as_reg(addr_ptr->base());
1558   }
1559   Register newval = as_reg(op->new_value());
1560   Register cmpval = as_reg(op->cmp_value());
1561 
1562   if (op->code() == lir_cas_obj) {
1563     if (UseCompressedOops) {
1564       Register t1 = op->tmp1()->as_register();
1565       assert(op->tmp1()->is_valid(), "must be");
1566       __ encode_heap_oop(t1, cmpval);
1567       cmpval = t1;
1568       __ encode_heap_oop(rscratch2, newval);
1569       newval = rscratch2;
1570       casw(addr, newval, cmpval);
1571     } else {
1572       casl(addr, newval, cmpval);
1573     }
1574   } else if (op->code() == lir_cas_int) {
1575     casw(addr, newval, cmpval);
1576   } else {
1577     casl(addr, newval, cmpval);
1578   }
1579 }
1580 
1581 
1582 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1583                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1584   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1585 
1586   Assembler::Condition acond, ncond;
1587   switch (condition) {
1588   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1589   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1590   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1591   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1592   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1593   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1594   case lir_cond_belowEqual:
1595   case lir_cond_aboveEqual:
1596   default:                    ShouldNotReachHere();
1597     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1598   }
1599 
1600   assert(result->is_single_cpu() || result->is_double_cpu(),
1601          "expect single register for result");
1602   if (opr1->is_constant() && opr2->is_constant()
1603       && opr1->type() == T_INT && opr2->type() == T_INT) {
1604     jint val1 = opr1->as_jint();
1605     jint val2 = opr2->as_jint();
1606     if (val1 == 0 && val2 == 1) {
1607       __ cset(result->as_register(), ncond);
1608       return;
1609     } else if (val1 == 1 && val2 == 0) {
1610       __ cset(result->as_register(), acond);
1611       return;
1612     }
1613   }
1614 
1615   if (opr1->is_constant() && opr2->is_constant()
1616       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1617     jlong val1 = opr1->as_jlong();
1618     jlong val2 = opr2->as_jlong();
1619     if (val1 == 0 && val2 == 1) {
1620       __ cset(result->as_register_lo(), ncond);
1621       return;
1622     } else if (val1 == 1 && val2 == 0) {
1623       __ cset(result->as_register_lo(), acond);
1624       return;
1625     }
1626   }
1627 
1628   if (opr1->is_stack()) {
1629     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1630     opr1 = FrameMap::rscratch1_opr;
1631   } else if (opr1->is_constant()) {
1632     LIR_Opr tmp
1633       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1634     const2reg(opr1, tmp, lir_patch_none, NULL);
1635     opr1 = tmp;
1636   }
1637 
1638   if (opr2->is_stack()) {
1639     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1640     opr2 = FrameMap::rscratch2_opr;
1641   } else if (opr2->is_constant()) {
1642     LIR_Opr tmp
1643       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1644     const2reg(opr2, tmp, lir_patch_none, NULL);
1645     opr2 = tmp;
1646   }
1647 
1648   if (result->type() == T_LONG)
1649     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1650   else
1651     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1652 }
1653 
1654 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1655   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1656 
1657   if (left->is_single_cpu()) {
1658     Register lreg = left->as_register();
1659     Register dreg = as_reg(dest);
1660 
1661     if (right->is_single_cpu()) {
1662       // cpu register - cpu register
1663 
1664       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1665              "should be");
1666       Register rreg = right->as_register();
1667       switch (code) {
1668       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1669       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1670       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1671       default:      ShouldNotReachHere();
1672       }
1673 
1674     } else if (right->is_double_cpu()) {
1675       Register rreg = right->as_register_lo();
1676       // single_cpu + double_cpu: can happen with obj+long
1677       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1678       switch (code) {
1679       case lir_add: __ add(dreg, lreg, rreg); break;
1680       case lir_sub: __ sub(dreg, lreg, rreg); break;
1681       default: ShouldNotReachHere();
1682       }
1683     } else if (right->is_constant()) {
1684       // cpu register - constant
1685       jlong c;
1686 
1687       // FIXME.  This is fugly: we really need to factor all this logic.
1688       switch(right->type()) {
1689       case T_LONG:
1690         c = right->as_constant_ptr()->as_jlong();
1691         break;
1692       case T_INT:
1693       case T_ADDRESS:
1694         c = right->as_constant_ptr()->as_jint();
1695         break;
1696       default:
1697         ShouldNotReachHere();
1698         c = 0;  // unreachable
1699         break;
1700       }
1701 
1702       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1703       if (c == 0 && dreg == lreg) {
1704         COMMENT("effective nop elided");
1705         return;
1706       }
1707       switch(left->type()) {
1708       case T_INT:
1709         switch (code) {
1710         case lir_add: __ addw(dreg, lreg, c); break;
1711         case lir_sub: __ subw(dreg, lreg, c); break;
1712         default: ShouldNotReachHere();
1713         }
1714         break;
1715       case T_OBJECT:
1716       case T_ADDRESS:
1717         switch (code) {
1718         case lir_add: __ add(dreg, lreg, c); break;
1719         case lir_sub: __ sub(dreg, lreg, c); break;
1720         default: ShouldNotReachHere();
1721         }
1722         break;
1723       default:
1724         ShouldNotReachHere();
1725       }
1726     } else {
1727       ShouldNotReachHere();
1728     }
1729 
1730   } else if (left->is_double_cpu()) {
1731     Register lreg_lo = left->as_register_lo();
1732 
1733     if (right->is_double_cpu()) {
1734       // cpu register - cpu register
1735       Register rreg_lo = right->as_register_lo();
1736       switch (code) {
1737       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1738       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1739       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1740       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1741       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1742       default:
1743         ShouldNotReachHere();
1744       }
1745 
1746     } else if (right->is_constant()) {
1747       jlong c = right->as_constant_ptr()->as_jlong();
1748       Register dreg = as_reg(dest);
1749       switch (code) {
1750         case lir_add:
1751         case lir_sub:
1752           if (c == 0 && dreg == lreg_lo) {
1753             COMMENT("effective nop elided");
1754             return;
1755           }
1756           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1757           break;
1758         case lir_div:
1759           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1760           if (c == 1) {
1761             // move lreg_lo to dreg if divisor is 1
1762             __ mov(dreg, lreg_lo);
1763           } else {
1764             unsigned int shift = log2i_exact(c);
1765             // use rscratch1 as intermediate result register
1766             __ asr(rscratch1, lreg_lo, 63);
1767             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1768             __ asr(dreg, rscratch1, shift);
1769           }
1770           break;
1771         case lir_rem:
1772           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1773           if (c == 1) {
1774             // move 0 to dreg if divisor is 1
1775             __ mov(dreg, zr);
1776           } else {
1777             // use rscratch1 as intermediate result register
1778             __ negs(rscratch1, lreg_lo);
1779             __ andr(dreg, lreg_lo, c - 1);
1780             __ andr(rscratch1, rscratch1, c - 1);
1781             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1782           }
1783           break;
1784         default:
1785           ShouldNotReachHere();
1786       }
1787     } else {
1788       ShouldNotReachHere();
1789     }
1790   } else if (left->is_single_fpu()) {
1791     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1792     switch (code) {
1793     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1794     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1795     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1796     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1797     default:
1798       ShouldNotReachHere();
1799     }
1800   } else if (left->is_double_fpu()) {
1801     if (right->is_double_fpu()) {
1802       // fpu register - fpu register
1803       switch (code) {
1804       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1805       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1806       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1807       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1808       default:
1809         ShouldNotReachHere();
1810       }
1811     } else {
1812       if (right->is_constant()) {
1813         ShouldNotReachHere();
1814       }
1815       ShouldNotReachHere();
1816     }
1817   } else if (left->is_single_stack() || left->is_address()) {
1818     assert(left == dest, "left and dest must be equal");
1819     ShouldNotReachHere();
1820   } else {
1821     ShouldNotReachHere();
1822   }
1823 }
1824 
1825 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1826 
1827 
1828 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1829   switch(code) {
1830   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1831   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1832   default      : ShouldNotReachHere();
1833   }
1834 }
1835 
1836 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1837 
1838   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1839   Register Rleft = left->is_single_cpu() ? left->as_register() :
1840                                            left->as_register_lo();
1841    if (dst->is_single_cpu()) {
1842      Register Rdst = dst->as_register();
1843      if (right->is_constant()) {
1844        switch (code) {
1845          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1846          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1847          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1848          default: ShouldNotReachHere(); break;
1849        }
1850      } else {
1851        Register Rright = right->is_single_cpu() ? right->as_register() :
1852                                                   right->as_register_lo();
1853        switch (code) {
1854          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1855          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1856          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1857          default: ShouldNotReachHere(); break;
1858        }
1859      }
1860    } else {
1861      Register Rdst = dst->as_register_lo();
1862      if (right->is_constant()) {
1863        switch (code) {
1864          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1865          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1866          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1867          default: ShouldNotReachHere(); break;
1868        }
1869      } else {
1870        Register Rright = right->is_single_cpu() ? right->as_register() :
1871                                                   right->as_register_lo();
1872        switch (code) {
1873          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1874          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1875          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1876          default: ShouldNotReachHere(); break;
1877        }
1878      }
1879    }
1880 }
1881 
1882 
1883 
1884 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1885 
1886   // opcode check
1887   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1888   bool is_irem = (code == lir_irem);
1889 
1890   // operand check
1891   assert(left->is_single_cpu(),   "left must be register");
1892   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1893   assert(result->is_single_cpu(), "result must be register");
1894   Register lreg = left->as_register();
1895   Register dreg = result->as_register();
1896 
1897   // power-of-2 constant check and codegen
1898   if (right->is_constant()) {
1899     int c = right->as_constant_ptr()->as_jint();
1900     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1901     if (is_irem) {
1902       if (c == 1) {
1903         // move 0 to dreg if divisor is 1
1904         __ movw(dreg, zr);
1905       } else {
1906         // use rscratch1 as intermediate result register
1907         __ negsw(rscratch1, lreg);
1908         __ andw(dreg, lreg, c - 1);
1909         __ andw(rscratch1, rscratch1, c - 1);
1910         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1911       }
1912     } else {
1913       if (c == 1) {
1914         // move lreg to dreg if divisor is 1
1915         __ movw(dreg, lreg);
1916       } else {
1917         unsigned int shift = exact_log2(c);
1918         // use rscratch1 as intermediate result register
1919         __ asrw(rscratch1, lreg, 31);
1920         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1921         __ asrw(dreg, rscratch1, shift);
1922       }
1923     }
1924   } else {
1925     Register rreg = right->as_register();
1926     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1927   }
1928 }
1929 
1930 
1931 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1932   if (opr1->is_constant() && opr2->is_single_cpu()) {
1933     // tableswitch
1934     Register reg = as_reg(opr2);
1935     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1936     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1937   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1938     Register reg1 = as_reg(opr1);
1939     if (opr2->is_single_cpu()) {
1940       // cpu register - cpu register
1941       Register reg2 = opr2->as_register();
1942       if (is_reference_type(opr1->type())) {
1943         __ cmpoop(reg1, reg2);
1944       } else {
1945         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1946         __ cmpw(reg1, reg2);
1947       }
1948       return;
1949     }
1950     if (opr2->is_double_cpu()) {
1951       // cpu register - cpu register
1952       Register reg2 = opr2->as_register_lo();
1953       __ cmp(reg1, reg2);
1954       return;
1955     }
1956 
1957     if (opr2->is_constant()) {
1958       bool is_32bit = false; // width of register operand
1959       jlong imm;
1960 
1961       switch(opr2->type()) {
1962       case T_INT:
1963         imm = opr2->as_constant_ptr()->as_jint();
1964         is_32bit = true;
1965         break;
1966       case T_LONG:
1967         imm = opr2->as_constant_ptr()->as_jlong();
1968         break;
1969       case T_ADDRESS:
1970         imm = opr2->as_constant_ptr()->as_jint();
1971         break;
1972       case T_METADATA:
1973         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1974         break;
1975       case T_OBJECT:
1976       case T_ARRAY:
1977         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1978         __ cmpoop(reg1, rscratch1);
1979         return;
1980       default:
1981         ShouldNotReachHere();
1982         imm = 0;  // unreachable
1983         break;
1984       }
1985 
1986       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1987         if (is_32bit)
1988           __ cmpw(reg1, imm);
1989         else
1990           __ subs(zr, reg1, imm);
1991         return;
1992       } else {
1993         __ mov(rscratch1, imm);
1994         if (is_32bit)
1995           __ cmpw(reg1, rscratch1);
1996         else
1997           __ cmp(reg1, rscratch1);
1998         return;
1999       }
2000     } else
2001       ShouldNotReachHere();
2002   } else if (opr1->is_single_fpu()) {
2003     FloatRegister reg1 = opr1->as_float_reg();
2004     assert(opr2->is_single_fpu(), "expect single float register");
2005     FloatRegister reg2 = opr2->as_float_reg();
2006     __ fcmps(reg1, reg2);
2007   } else if (opr1->is_double_fpu()) {
2008     FloatRegister reg1 = opr1->as_double_reg();
2009     assert(opr2->is_double_fpu(), "expect double float register");
2010     FloatRegister reg2 = opr2->as_double_reg();
2011     __ fcmpd(reg1, reg2);
2012   } else {
2013     ShouldNotReachHere();
2014   }
2015 }
2016 
2017 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2018   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2019     bool is_unordered_less = (code == lir_ucmp_fd2i);
2020     if (left->is_single_fpu()) {
2021       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2022     } else if (left->is_double_fpu()) {
2023       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2024     } else {
2025       ShouldNotReachHere();
2026     }
2027   } else if (code == lir_cmp_l2i) {
2028     Label done;
2029     __ cmp(left->as_register_lo(), right->as_register_lo());
2030     __ mov(dst->as_register(), (uint64_t)-1L);
2031     __ br(Assembler::LT, done);
2032     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2033     __ bind(done);
2034   } else {
2035     ShouldNotReachHere();
2036   }
2037 }
2038 
2039 
2040 void LIR_Assembler::align_call(LIR_Code code) {  }
2041 
2042 
2043 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2044   address call = __ trampoline_call(Address(op->addr(), rtype));
2045   if (call == NULL) {
2046     bailout("trampoline stub overflow");
2047     return;
2048   }
2049   add_call_info(code_offset(), op->info());
2050 }
2051 
2052 
2053 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2054   address call = __ ic_call(op->addr());
2055   if (call == NULL) {
2056     bailout("trampoline stub overflow");
2057     return;
2058   }
2059   add_call_info(code_offset(), op->info());
2060 }
2061 
2062 void LIR_Assembler::emit_static_call_stub() {
2063   address call_pc = __ pc();
2064   address stub = __ start_a_stub(call_stub_size());
2065   if (stub == NULL) {
2066     bailout("static call stub overflow");
2067     return;
2068   }
2069 
2070   int start = __ offset();
2071 
2072   __ relocate(static_stub_Relocation::spec(call_pc));
2073   __ emit_static_call_stub();
2074 
2075   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2076         <= call_stub_size(), "stub too big");
2077   __ end_a_stub();
2078 }
2079 
2080 
2081 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2082   assert(exceptionOop->as_register() == r0, "must match");
2083   assert(exceptionPC->as_register() == r3, "must match");
2084 
2085   // exception object is not added to oop map by LinearScan
2086   // (LinearScan assumes that no oops are in fixed registers)
2087   info->add_register_oop(exceptionOop);
2088   Runtime1::StubID unwind_id;
2089 
2090   // get current pc information
2091   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2092   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2093     // As no instructions have been generated yet for this LIR node it's
2094     // possible that an oop map already exists for the current offset.
2095     // In that case insert an dummy NOP here to ensure all oop map PCs
2096     // are unique. See JDK-8237483.
2097     __ nop();
2098   }
2099   int pc_for_athrow_offset = __ offset();
2100   InternalAddress pc_for_athrow(__ pc());
2101   __ adr(exceptionPC->as_register(), pc_for_athrow);
2102   add_call_info(pc_for_athrow_offset, info); // for exception handler
2103 
2104   __ verify_not_null_oop(r0);
2105   // search an exception handler (r0: exception oop, r3: throwing pc)
2106   if (compilation()->has_fpu_code()) {
2107     unwind_id = Runtime1::handle_exception_id;
2108   } else {
2109     unwind_id = Runtime1::handle_exception_nofpu_id;
2110   }
2111   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2112 
2113   // FIXME: enough room for two byte trap   ????
2114   __ nop();
2115 }
2116 
2117 
2118 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2119   assert(exceptionOop->as_register() == r0, "must match");
2120 
2121   __ b(_unwind_handler_entry);
2122 }
2123 
2124 
2125 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2126   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2127   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2128 
2129   switch (left->type()) {
2130     case T_INT: {
2131       switch (code) {
2132       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2133       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2134       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2135       default:
2136         ShouldNotReachHere();
2137         break;
2138       }
2139       break;
2140     case T_LONG:
2141     case T_ADDRESS:
2142     case T_OBJECT:
2143       switch (code) {
2144       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2145       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2146       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2147       default:
2148         ShouldNotReachHere();
2149         break;
2150       }
2151       break;
2152     default:
2153       ShouldNotReachHere();
2154       break;
2155     }
2156   }
2157 }
2158 
2159 
2160 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2161   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2162   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2163 
2164   switch (left->type()) {
2165     case T_INT: {
2166       switch (code) {
2167       case lir_shl:  __ lslw (dreg, lreg, count); break;
2168       case lir_shr:  __ asrw (dreg, lreg, count); break;
2169       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2170       default:
2171         ShouldNotReachHere();
2172         break;
2173       }
2174       break;
2175     case T_LONG:
2176     case T_ADDRESS:
2177     case T_OBJECT:
2178       switch (code) {
2179       case lir_shl:  __ lsl (dreg, lreg, count); break;
2180       case lir_shr:  __ asr (dreg, lreg, count); break;
2181       case lir_ushr: __ lsr (dreg, lreg, count); break;
2182       default:
2183         ShouldNotReachHere();
2184         break;
2185       }
2186       break;
2187     default:
2188       ShouldNotReachHere();
2189       break;
2190     }
2191   }
2192 }
2193 
2194 
2195 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2196   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2197   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2198   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2199   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2200 }
2201 
2202 
2203 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2204   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2205   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2206   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2207   __ mov (rscratch1, c);
2208   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2209 }
2210 
2211 
2212 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2213   ShouldNotReachHere();
2214   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2215   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2216   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2217   __ lea(rscratch1, __ constant_oop_address(o));
2218   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2219 }
2220 
2221 
2222 // This code replaces a call to arraycopy; no exception may
2223 // be thrown in this code, they must be thrown in the System.arraycopy
2224 // activation frame; we could save some checks if this would not be the case
2225 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2226   ciArrayKlass* default_type = op->expected_type();
2227   Register src = op->src()->as_register();
2228   Register dst = op->dst()->as_register();
2229   Register src_pos = op->src_pos()->as_register();
2230   Register dst_pos = op->dst_pos()->as_register();
2231   Register length  = op->length()->as_register();
2232   Register tmp = op->tmp()->as_register();
2233 
2234   CodeStub* stub = op->stub();
2235   int flags = op->flags();
2236   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2237   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2238 
2239   // if we don't know anything, just go through the generic arraycopy
2240   if (default_type == NULL // || basic_type == T_OBJECT
2241       ) {
2242     Label done;
2243     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2244 
2245     // Save the arguments in case the generic arraycopy fails and we
2246     // have to fall back to the JNI stub
2247     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2248     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2249     __ str(src,              Address(sp, 4*BytesPerWord));
2250 
2251     address copyfunc_addr = StubRoutines::generic_arraycopy();
2252     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2253 
2254     // The arguments are in java calling convention so we shift them
2255     // to C convention
2256     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2257     __ mov(c_rarg0, j_rarg0);
2258     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2259     __ mov(c_rarg1, j_rarg1);
2260     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2261     __ mov(c_rarg2, j_rarg2);
2262     assert_different_registers(c_rarg3, j_rarg4);
2263     __ mov(c_rarg3, j_rarg3);
2264     __ mov(c_rarg4, j_rarg4);
2265 #ifndef PRODUCT
2266     if (PrintC1Statistics) {
2267       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2268     }
2269 #endif
2270     __ far_call(RuntimeAddress(copyfunc_addr));
2271 
2272     __ cbz(r0, *stub->continuation());
2273 
2274     // Reload values from the stack so they are where the stub
2275     // expects them.
2276     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2277     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2278     __ ldr(src,              Address(sp, 4*BytesPerWord));
2279 
2280     // r0 is -1^K where K == partial copied count
2281     __ eonw(rscratch1, r0, zr);
2282     // adjust length down and src/end pos up by partial copied count
2283     __ subw(length, length, rscratch1);
2284     __ addw(src_pos, src_pos, rscratch1);
2285     __ addw(dst_pos, dst_pos, rscratch1);
2286     __ b(*stub->entry());
2287 
2288     __ bind(*stub->continuation());
2289     return;
2290   }
2291 
2292   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2293 
2294   int elem_size = type2aelembytes(basic_type);
2295   int scale = exact_log2(elem_size);
2296 
2297   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2298   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2299   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2300   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2301 
2302   // test for NULL
2303   if (flags & LIR_OpArrayCopy::src_null_check) {
2304     __ cbz(src, *stub->entry());
2305   }
2306   if (flags & LIR_OpArrayCopy::dst_null_check) {
2307     __ cbz(dst, *stub->entry());
2308   }
2309 
2310   // If the compiler was not able to prove that exact type of the source or the destination
2311   // of the arraycopy is an array type, check at runtime if the source or the destination is
2312   // an instance type.
2313   if (flags & LIR_OpArrayCopy::type_check) {
2314     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2315       __ load_klass(tmp, dst);
2316       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2317       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2318       __ br(Assembler::GE, *stub->entry());
2319     }
2320 
2321     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2322       __ load_klass(tmp, src);
2323       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2324       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2325       __ br(Assembler::GE, *stub->entry());
2326     }
2327   }
2328 
2329   // check if negative
2330   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2331     __ cmpw(src_pos, 0);
2332     __ br(Assembler::LT, *stub->entry());
2333   }
2334   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2335     __ cmpw(dst_pos, 0);
2336     __ br(Assembler::LT, *stub->entry());
2337   }
2338 
2339   if (flags & LIR_OpArrayCopy::length_positive_check) {
2340     __ cmpw(length, 0);
2341     __ br(Assembler::LT, *stub->entry());
2342   }
2343 
2344   if (flags & LIR_OpArrayCopy::src_range_check) {
2345     __ addw(tmp, src_pos, length);
2346     __ ldrw(rscratch1, src_length_addr);
2347     __ cmpw(tmp, rscratch1);
2348     __ br(Assembler::HI, *stub->entry());
2349   }
2350   if (flags & LIR_OpArrayCopy::dst_range_check) {
2351     __ addw(tmp, dst_pos, length);
2352     __ ldrw(rscratch1, dst_length_addr);
2353     __ cmpw(tmp, rscratch1);
2354     __ br(Assembler::HI, *stub->entry());
2355   }
2356 
2357   if (flags & LIR_OpArrayCopy::type_check) {
2358     // We don't know the array types are compatible
2359     if (basic_type != T_OBJECT) {
2360       // Simple test for basic type arrays
2361       if (UseCompressedClassPointers) {
2362         __ ldrw(tmp, src_klass_addr);
2363         __ ldrw(rscratch1, dst_klass_addr);
2364         __ cmpw(tmp, rscratch1);
2365       } else {
2366         __ ldr(tmp, src_klass_addr);
2367         __ ldr(rscratch1, dst_klass_addr);
2368         __ cmp(tmp, rscratch1);
2369       }
2370       __ br(Assembler::NE, *stub->entry());
2371     } else {
2372       // For object arrays, if src is a sub class of dst then we can
2373       // safely do the copy.
2374       Label cont, slow;
2375 
2376 #define PUSH(r1, r2)                                    \
2377       stp(r1, r2, __ pre(sp, -2 * wordSize));
2378 
2379 #define POP(r1, r2)                                     \
2380       ldp(r1, r2, __ post(sp, 2 * wordSize));
2381 
2382       __ PUSH(src, dst);
2383 
2384       __ load_klass(src, src);
2385       __ load_klass(dst, dst);
2386 
2387       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2388 
2389       __ PUSH(src, dst);
2390       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2391       __ POP(src, dst);
2392 
2393       __ cbnz(src, cont);
2394 
2395       __ bind(slow);
2396       __ POP(src, dst);
2397 
2398       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2399       if (copyfunc_addr != NULL) { // use stub if available
2400         // src is not a sub class of dst so we have to do a
2401         // per-element check.
2402 
2403         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2404         if ((flags & mask) != mask) {
2405           // Check that at least both of them object arrays.
2406           assert(flags & mask, "one of the two should be known to be an object array");
2407 
2408           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2409             __ load_klass(tmp, src);
2410           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2411             __ load_klass(tmp, dst);
2412           }
2413           int lh_offset = in_bytes(Klass::layout_helper_offset());
2414           Address klass_lh_addr(tmp, lh_offset);
2415           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2416           __ ldrw(rscratch1, klass_lh_addr);
2417           __ mov(rscratch2, objArray_lh);
2418           __ eorw(rscratch1, rscratch1, rscratch2);
2419           __ cbnzw(rscratch1, *stub->entry());
2420         }
2421 
2422        // Spill because stubs can use any register they like and it's
2423        // easier to restore just those that we care about.
2424         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2425         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2426         __ str(src,              Address(sp, 4*BytesPerWord));
2427 
2428         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2429         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2430         assert_different_registers(c_rarg0, dst, dst_pos, length);
2431         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2432         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2433         assert_different_registers(c_rarg1, dst, length);
2434         __ uxtw(c_rarg2, length);
2435         assert_different_registers(c_rarg2, dst);
2436 
2437         __ load_klass(c_rarg4, dst);
2438         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2439         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2440         __ far_call(RuntimeAddress(copyfunc_addr));
2441 
2442 #ifndef PRODUCT
2443         if (PrintC1Statistics) {
2444           Label failed;
2445           __ cbnz(r0, failed);
2446           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2447           __ bind(failed);
2448         }
2449 #endif
2450 
2451         __ cbz(r0, *stub->continuation());
2452 
2453 #ifndef PRODUCT
2454         if (PrintC1Statistics) {
2455           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2456         }
2457 #endif
2458         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2459 
2460         // Restore previously spilled arguments
2461         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2462         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2463         __ ldr(src,              Address(sp, 4*BytesPerWord));
2464 
2465         // return value is -1^K where K is partial copied count
2466         __ eonw(rscratch1, r0, zr);
2467         // adjust length down and src/end pos up by partial copied count
2468         __ subw(length, length, rscratch1);
2469         __ addw(src_pos, src_pos, rscratch1);
2470         __ addw(dst_pos, dst_pos, rscratch1);
2471       }
2472 
2473       __ b(*stub->entry());
2474 
2475       __ bind(cont);
2476       __ POP(src, dst);
2477     }
2478   }
2479 
2480 #ifdef ASSERT
2481   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2482     // Sanity check the known type with the incoming class.  For the
2483     // primitive case the types must match exactly with src.klass and
2484     // dst.klass each exactly matching the default type.  For the
2485     // object array case, if no type check is needed then either the
2486     // dst type is exactly the expected type and the src type is a
2487     // subtype which we can't check or src is the same array as dst
2488     // but not necessarily exactly of type default_type.
2489     Label known_ok, halt;
2490     __ mov_metadata(tmp, default_type->constant_encoding());
2491     if (UseCompressedClassPointers) {
2492       __ encode_klass_not_null(tmp);
2493     }
2494 
2495     if (basic_type != T_OBJECT) {
2496 
2497       if (UseCompressedClassPointers) {
2498         __ ldrw(rscratch1, dst_klass_addr);
2499         __ cmpw(tmp, rscratch1);
2500       } else {
2501         __ ldr(rscratch1, dst_klass_addr);
2502         __ cmp(tmp, rscratch1);
2503       }
2504       __ br(Assembler::NE, halt);
2505       if (UseCompressedClassPointers) {
2506         __ ldrw(rscratch1, src_klass_addr);
2507         __ cmpw(tmp, rscratch1);
2508       } else {
2509         __ ldr(rscratch1, src_klass_addr);
2510         __ cmp(tmp, rscratch1);
2511       }
2512       __ br(Assembler::EQ, known_ok);
2513     } else {
2514       if (UseCompressedClassPointers) {
2515         __ ldrw(rscratch1, dst_klass_addr);
2516         __ cmpw(tmp, rscratch1);
2517       } else {
2518         __ ldr(rscratch1, dst_klass_addr);
2519         __ cmp(tmp, rscratch1);
2520       }
2521       __ br(Assembler::EQ, known_ok);
2522       __ cmp(src, dst);
2523       __ br(Assembler::EQ, known_ok);
2524     }
2525     __ bind(halt);
2526     __ stop("incorrect type information in arraycopy");
2527     __ bind(known_ok);
2528   }
2529 #endif
2530 
2531 #ifndef PRODUCT
2532   if (PrintC1Statistics) {
2533     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2534   }
2535 #endif
2536 
2537   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2538   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2539   assert_different_registers(c_rarg0, dst, dst_pos, length);
2540   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2541   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2542   assert_different_registers(c_rarg1, dst, length);
2543   __ uxtw(c_rarg2, length);
2544   assert_different_registers(c_rarg2, dst);
2545 
2546   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2547   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2548   const char *name;
2549   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2550 
2551  CodeBlob *cb = CodeCache::find_blob(entry);
2552  if (cb) {
2553    __ far_call(RuntimeAddress(entry));
2554  } else {
2555    __ call_VM_leaf(entry, 3);
2556  }
2557 
2558   __ bind(*stub->continuation());
2559 }
2560 
2561 
2562 
2563 
2564 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2565   Register obj = op->obj_opr()->as_register();  // may not be an oop
2566   Register hdr = op->hdr_opr()->as_register();
2567   Register lock = op->lock_opr()->as_register();
2568   if (!UseFastLocking) {
2569     __ b(*op->stub()->entry());
2570   } else if (op->code() == lir_lock) {
2571     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2572     // add debug info for NullPointerException only if one is possible
2573     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2574     if (op->info() != NULL) {
2575       add_debug_info_for_null_check(null_check_offset, op->info());
2576     }
2577     // done
2578   } else if (op->code() == lir_unlock) {
2579     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2580     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2581   } else {
2582     Unimplemented();
2583   }
2584   __ bind(*op->stub()->continuation());
2585 }
2586 
2587 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2588   Register obj = op->obj()->as_pointer_register();
2589   Register result = op->result_opr()->as_pointer_register();
2590 
2591   CodeEmitInfo* info = op->info();
2592   if (info != NULL) {
2593     add_debug_info_for_null_check_here(info);
2594   }
2595 
2596   if (UseCompressedClassPointers) {
2597     __ ldrw(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2598     __ decode_klass_not_null(result);
2599   } else {
2600     __ ldr(result, Address (obj, oopDesc::klass_offset_in_bytes()));
2601   }
2602 }
2603 
2604 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2605   ciMethod* method = op->profiled_method();
2606   int bci          = op->profiled_bci();
2607   ciMethod* callee = op->profiled_callee();
2608 
2609   // Update counter for all call types
2610   ciMethodData* md = method->method_data_or_null();
2611   assert(md != NULL, "Sanity");
2612   ciProfileData* data = md->bci_to_data(bci);
2613   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2614   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2615   Register mdo  = op->mdo()->as_register();
2616   __ mov_metadata(mdo, md->constant_encoding());
2617   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2618   // Perform additional virtual call profiling for invokevirtual and
2619   // invokeinterface bytecodes
2620   if (op->should_profile_receiver_type()) {
2621     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2622     Register recv = op->recv()->as_register();
2623     assert_different_registers(mdo, recv);
2624     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2625     ciKlass* known_klass = op->known_holder();
2626     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2627       // We know the type that will be seen at this call site; we can
2628       // statically update the MethodData* rather than needing to do
2629       // dynamic tests on the receiver type
2630 
2631       // NOTE: we should probably put a lock around this search to
2632       // avoid collisions by concurrent compilations
2633       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2634       uint i;
2635       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2636         ciKlass* receiver = vc_data->receiver(i);
2637         if (known_klass->equals(receiver)) {
2638           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2639           __ addptr(data_addr, DataLayout::counter_increment);
2640           return;
2641         }
2642       }
2643 
2644       // Receiver type not found in profile data; select an empty slot
2645 
2646       // Note that this is less efficient than it should be because it
2647       // always does a write to the receiver part of the
2648       // VirtualCallData rather than just the first time
2649       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2650         ciKlass* receiver = vc_data->receiver(i);
2651         if (receiver == NULL) {
2652           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2653           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2654           __ lea(rscratch2, recv_addr);
2655           __ str(rscratch1, Address(rscratch2));
2656           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2657           __ addptr(data_addr, DataLayout::counter_increment);
2658           return;
2659         }
2660       }
2661     } else {
2662       __ load_klass(recv, recv);
2663       Label update_done;
2664       type_profile_helper(mdo, md, data, recv, &update_done);
2665       // Receiver did not match any saved receiver and there is no empty row for it.
2666       // Increment total counter to indicate polymorphic case.
2667       __ addptr(counter_addr, DataLayout::counter_increment);
2668 
2669       __ bind(update_done);
2670     }
2671   } else {
2672     // Static call
2673     __ addptr(counter_addr, DataLayout::counter_increment);
2674   }
2675 }
2676 
2677 
2678 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2679   Unimplemented();
2680 }
2681 
2682 
2683 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2684   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2685 }
2686 
2687 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2688   assert(op->crc()->is_single_cpu(),  "crc must be register");
2689   assert(op->val()->is_single_cpu(),  "byte value must be register");
2690   assert(op->result_opr()->is_single_cpu(), "result must be register");
2691   Register crc = op->crc()->as_register();
2692   Register val = op->val()->as_register();
2693   Register res = op->result_opr()->as_register();
2694 
2695   assert_different_registers(val, crc, res);
2696   uint64_t offset;
2697   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2698   if (offset) __ add(res, res, offset);
2699 
2700   __ mvnw(crc, crc); // ~crc
2701   __ update_byte_crc32(crc, val, res);
2702   __ mvnw(res, crc); // ~crc
2703 }
2704 
2705 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2706   COMMENT("emit_profile_type {");
2707   Register obj = op->obj()->as_register();
2708   Register tmp = op->tmp()->as_pointer_register();
2709   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2710   ciKlass* exact_klass = op->exact_klass();
2711   intptr_t current_klass = op->current_klass();
2712   bool not_null = op->not_null();
2713   bool no_conflict = op->no_conflict();
2714 
2715   Label update, next, none;
2716 
2717   bool do_null = !not_null;
2718   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2719   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2720 
2721   assert(do_null || do_update, "why are we here?");
2722   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2723   assert(mdo_addr.base() != rscratch1, "wrong register");
2724 
2725   __ verify_oop(obj);
2726 
2727   if (tmp != obj) {
2728     __ mov(tmp, obj);
2729   }
2730   if (do_null) {
2731     __ cbnz(tmp, update);
2732     if (!TypeEntries::was_null_seen(current_klass)) {
2733       __ ldr(rscratch2, mdo_addr);
2734       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2735       __ str(rscratch2, mdo_addr);
2736     }
2737     if (do_update) {
2738 #ifndef ASSERT
2739       __ b(next);
2740     }
2741 #else
2742       __ b(next);
2743     }
2744   } else {
2745     __ cbnz(tmp, update);
2746     __ stop("unexpected null obj");
2747 #endif
2748   }
2749 
2750   __ bind(update);
2751 
2752   if (do_update) {
2753 #ifdef ASSERT
2754     if (exact_klass != NULL) {
2755       Label ok;
2756       __ load_klass(tmp, tmp);
2757       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2758       __ eor(rscratch1, tmp, rscratch1);
2759       __ cbz(rscratch1, ok);
2760       __ stop("exact klass and actual klass differ");
2761       __ bind(ok);
2762     }
2763 #endif
2764     if (!no_conflict) {
2765       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2766         if (exact_klass != NULL) {
2767           __ mov_metadata(tmp, exact_klass->constant_encoding());
2768         } else {
2769           __ load_klass(tmp, tmp);
2770         }
2771 
2772         __ ldr(rscratch2, mdo_addr);
2773         __ eor(tmp, tmp, rscratch2);
2774         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2775         // klass seen before, nothing to do. The unknown bit may have been
2776         // set already but no need to check.
2777         __ cbz(rscratch1, next);
2778 
2779         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2780 
2781         if (TypeEntries::is_type_none(current_klass)) {
2782           __ cbz(rscratch2, none);
2783           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2784           __ br(Assembler::EQ, none);
2785           // There is a chance that the checks above (re-reading profiling
2786           // data from memory) fail if another thread has just set the
2787           // profiling to this obj's klass
2788           __ dmb(Assembler::ISHLD);
2789           __ ldr(rscratch2, mdo_addr);
2790           __ eor(tmp, tmp, rscratch2);
2791           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2792           __ cbz(rscratch1, next);
2793         }
2794       } else {
2795         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2796                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2797 
2798         __ ldr(tmp, mdo_addr);
2799         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2800       }
2801 
2802       // different than before. Cannot keep accurate profile.
2803       __ ldr(rscratch2, mdo_addr);
2804       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2805       __ str(rscratch2, mdo_addr);
2806 
2807       if (TypeEntries::is_type_none(current_klass)) {
2808         __ b(next);
2809 
2810         __ bind(none);
2811         // first time here. Set profile type.
2812         __ str(tmp, mdo_addr);
2813       }
2814     } else {
2815       // There's a single possible klass at this profile point
2816       assert(exact_klass != NULL, "should be");
2817       if (TypeEntries::is_type_none(current_klass)) {
2818         __ mov_metadata(tmp, exact_klass->constant_encoding());
2819         __ ldr(rscratch2, mdo_addr);
2820         __ eor(tmp, tmp, rscratch2);
2821         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2822         __ cbz(rscratch1, next);
2823 #ifdef ASSERT
2824         {
2825           Label ok;
2826           __ ldr(rscratch1, mdo_addr);
2827           __ cbz(rscratch1, ok);
2828           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2829           __ br(Assembler::EQ, ok);
2830           // may have been set by another thread
2831           __ dmb(Assembler::ISHLD);
2832           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2833           __ ldr(rscratch2, mdo_addr);
2834           __ eor(rscratch2, rscratch1, rscratch2);
2835           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2836           __ cbz(rscratch2, ok);
2837 
2838           __ stop("unexpected profiling mismatch");
2839           __ bind(ok);
2840         }
2841 #endif
2842         // first time here. Set profile type.
2843         __ str(tmp, mdo_addr);
2844       } else {
2845         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2846                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2847 
2848         __ ldr(tmp, mdo_addr);
2849         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2850 
2851         __ orr(tmp, tmp, TypeEntries::type_unknown);
2852         __ str(tmp, mdo_addr);
2853         // FIXME: Write barrier needed here?
2854       }
2855     }
2856 
2857     __ bind(next);
2858   }
2859   COMMENT("} emit_profile_type");
2860 }
2861 
2862 
2863 void LIR_Assembler::align_backward_branch_target() {
2864 }
2865 
2866 
2867 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2868   // tmp must be unused
2869   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2870 
2871   if (left->is_single_cpu()) {
2872     assert(dest->is_single_cpu(), "expect single result reg");
2873     __ negw(dest->as_register(), left->as_register());
2874   } else if (left->is_double_cpu()) {
2875     assert(dest->is_double_cpu(), "expect double result reg");
2876     __ neg(dest->as_register_lo(), left->as_register_lo());
2877   } else if (left->is_single_fpu()) {
2878     assert(dest->is_single_fpu(), "expect single float result reg");
2879     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2880   } else {
2881     assert(left->is_double_fpu(), "expect double float operand reg");
2882     assert(dest->is_double_fpu(), "expect double float result reg");
2883     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2884   }
2885 }
2886 
2887 
2888 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2889   if (patch_code != lir_patch_none) {
2890     deoptimize_trap(info);
2891     return;
2892   }
2893 
2894   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2895 }
2896 
2897 
2898 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2899   assert(!tmp->is_valid(), "don't need temporary");
2900 
2901   CodeBlob *cb = CodeCache::find_blob(dest);
2902   if (cb) {
2903     __ far_call(RuntimeAddress(dest));
2904   } else {
2905     __ mov(rscratch1, RuntimeAddress(dest));
2906     __ blr(rscratch1);
2907   }
2908 
2909   if (info != NULL) {
2910     add_call_info_here(info);
2911   }
2912 }
2913 
2914 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2915   if (dest->is_address() || src->is_address()) {
2916     move_op(src, dest, type, lir_patch_none, info,
2917             /*pop_fpu_stack*/false, /*wide*/false);
2918   } else {
2919     ShouldNotReachHere();
2920   }
2921 }
2922 
2923 #ifdef ASSERT
2924 // emit run-time assertion
2925 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2926   assert(op->code() == lir_assert, "must be");
2927 
2928   if (op->in_opr1()->is_valid()) {
2929     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2930     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2931   } else {
2932     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2933     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2934   }
2935 
2936   Label ok;
2937   if (op->condition() != lir_cond_always) {
2938     Assembler::Condition acond = Assembler::AL;
2939     switch (op->condition()) {
2940       case lir_cond_equal:        acond = Assembler::EQ;  break;
2941       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2942       case lir_cond_less:         acond = Assembler::LT;  break;
2943       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2944       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2945       case lir_cond_greater:      acond = Assembler::GT;  break;
2946       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2947       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2948       default:                    ShouldNotReachHere();
2949     }
2950     __ br(acond, ok);
2951   }
2952   if (op->halt()) {
2953     const char* str = __ code_string(op->msg());
2954     __ stop(str);
2955   } else {
2956     breakpoint();
2957   }
2958   __ bind(ok);
2959 }
2960 #endif
2961 
2962 #ifndef PRODUCT
2963 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2964 #else
2965 #define COMMENT(x)
2966 #endif
2967 
2968 void LIR_Assembler::membar() {
2969   COMMENT("membar");
2970   __ membar(MacroAssembler::AnyAny);
2971 }
2972 
2973 void LIR_Assembler::membar_acquire() {
2974   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2975 }
2976 
2977 void LIR_Assembler::membar_release() {
2978   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2979 }
2980 
2981 void LIR_Assembler::membar_loadload() {
2982   __ membar(Assembler::LoadLoad);
2983 }
2984 
2985 void LIR_Assembler::membar_storestore() {
2986   __ membar(MacroAssembler::StoreStore);
2987 }
2988 
2989 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2990 
2991 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2992 
2993 void LIR_Assembler::on_spin_wait() {
2994   __ spin_wait();
2995 }
2996 
2997 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2998   __ mov(result_reg->as_register(), rthread);
2999 }
3000 
3001 
3002 void LIR_Assembler::peephole(LIR_List *lir) {
3003 #if 0
3004   if (tableswitch_count >= max_tableswitches)
3005     return;
3006 
3007   /*
3008     This finite-state automaton recognizes sequences of compare-and-
3009     branch instructions.  We will turn them into a tableswitch.  You
3010     could argue that C1 really shouldn't be doing this sort of
3011     optimization, but without it the code is really horrible.
3012   */
3013 
3014   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3015   int first_key, last_key = -2147483648;
3016   int next_key = 0;
3017   int start_insn = -1;
3018   int last_insn = -1;
3019   Register reg = noreg;
3020   LIR_Opr reg_opr;
3021   state = start_s;
3022 
3023   LIR_OpList* inst = lir->instructions_list();
3024   for (int i = 0; i < inst->length(); i++) {
3025     LIR_Op* op = inst->at(i);
3026     switch (state) {
3027     case start_s:
3028       first_key = -1;
3029       start_insn = i;
3030       switch (op->code()) {
3031       case lir_cmp:
3032         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3033         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3034         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3035             && opr2->is_constant()
3036             && opr2->type() == T_INT) {
3037           reg_opr = opr1;
3038           reg = opr1->as_register();
3039           first_key = opr2->as_constant_ptr()->as_jint();
3040           next_key = first_key + 1;
3041           state = cmp_s;
3042           goto next_state;
3043         }
3044         break;
3045       }
3046       break;
3047     case cmp_s:
3048       switch (op->code()) {
3049       case lir_branch:
3050         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3051           state = beq_s;
3052           last_insn = i;
3053           goto next_state;
3054         }
3055       }
3056       state = start_s;
3057       break;
3058     case beq_s:
3059       switch (op->code()) {
3060       case lir_cmp: {
3061         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3062         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3063         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3064             && opr1->as_register() == reg
3065             && opr2->is_constant()
3066             && opr2->type() == T_INT
3067             && opr2->as_constant_ptr()->as_jint() == next_key) {
3068           last_key = next_key;
3069           next_key++;
3070           state = cmp_s;
3071           goto next_state;
3072         }
3073       }
3074       }
3075       last_key = next_key;
3076       state = start_s;
3077       break;
3078     default:
3079       assert(false, "impossible state");
3080     }
3081     if (state == start_s) {
3082       if (first_key < last_key - 5L && reg != noreg) {
3083         {
3084           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3085           //        reg->encoding(),
3086           //        start_insn, first_key, last_key);
3087           //   for (int i = 0; i < inst->length(); i++) {
3088           //     inst->at(i)->print();
3089           //     tty->print("\n");
3090           //   }
3091           //   tty->print("\n");
3092         }
3093 
3094         struct tableswitch *sw = &switches[tableswitch_count];
3095         sw->_insn_index = start_insn, sw->_first_key = first_key,
3096           sw->_last_key = last_key, sw->_reg = reg;
3097         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3098         {
3099           // Insert the new table of branches
3100           int offset = last_insn;
3101           for (int n = first_key; n < last_key; n++) {
3102             inst->insert_before
3103               (last_insn + 1,
3104                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3105                                 inst->at(offset)->as_OpBranch()->label()));
3106             offset -= 2, i++;
3107           }
3108         }
3109         // Delete all the old compare-and-branch instructions
3110         for (int n = first_key; n < last_key; n++) {
3111           inst->remove_at(start_insn);
3112           inst->remove_at(start_insn);
3113         }
3114         // Insert the tableswitch instruction
3115         inst->insert_before(start_insn,
3116                             new LIR_Op2(lir_cmp, lir_cond_always,
3117                                         LIR_OprFact::intConst(tableswitch_count),
3118                                         reg_opr));
3119         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3120         tableswitch_count++;
3121       }
3122       reg = noreg;
3123       last_key = -2147483648;
3124     }
3125   next_state:
3126     ;
3127   }
3128 #endif
3129 }
3130 
3131 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3132   Address addr = as_Address(src->as_address_ptr());
3133   BasicType type = src->type();
3134   bool is_oop = is_reference_type(type);
3135 
3136   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3137   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3138 
3139   switch(type) {
3140   case T_INT:
3141     xchg = &MacroAssembler::atomic_xchgalw;
3142     add = &MacroAssembler::atomic_addalw;
3143     break;
3144   case T_LONG:
3145     xchg = &MacroAssembler::atomic_xchgal;
3146     add = &MacroAssembler::atomic_addal;
3147     break;
3148   case T_OBJECT:
3149   case T_ARRAY:
3150     if (UseCompressedOops) {
3151       xchg = &MacroAssembler::atomic_xchgalw;
3152       add = &MacroAssembler::atomic_addalw;
3153     } else {
3154       xchg = &MacroAssembler::atomic_xchgal;
3155       add = &MacroAssembler::atomic_addal;
3156     }
3157     break;
3158   default:
3159     ShouldNotReachHere();
3160     xchg = &MacroAssembler::atomic_xchgal;
3161     add = &MacroAssembler::atomic_addal; // unreachable
3162   }
3163 
3164   switch (code) {
3165   case lir_xadd:
3166     {
3167       RegisterOrConstant inc;
3168       Register tmp = as_reg(tmp_op);
3169       Register dst = as_reg(dest);
3170       if (data->is_constant()) {
3171         inc = RegisterOrConstant(as_long(data));
3172         assert_different_registers(dst, addr.base(), tmp,
3173                                    rscratch1, rscratch2);
3174       } else {
3175         inc = RegisterOrConstant(as_reg(data));
3176         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3177                                    rscratch1, rscratch2);
3178       }
3179       __ lea(tmp, addr);
3180       (_masm->*add)(dst, inc, tmp);
3181       break;
3182     }
3183   case lir_xchg:
3184     {
3185       Register tmp = tmp_op->as_register();
3186       Register obj = as_reg(data);
3187       Register dst = as_reg(dest);
3188       if (is_oop && UseCompressedOops) {
3189         __ encode_heap_oop(rscratch2, obj);
3190         obj = rscratch2;
3191       }
3192       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3193       __ lea(tmp, addr);
3194       (_masm->*xchg)(dst, obj, tmp);
3195       if (is_oop && UseCompressedOops) {
3196         __ decode_heap_oop(dst);
3197       }
3198     }
3199     break;
3200   default:
3201     ShouldNotReachHere();
3202   }
3203   __ membar(__ AnyAny);
3204 }
3205 
3206 #undef __