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src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

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1565   if (op->code() == lir_cas_obj) {
1566     if (UseCompressedOops) {
1567       Register t1 = op->tmp1()->as_register();
1568       assert(op->tmp1()->is_valid(), "must be");
1569       __ encode_heap_oop(t1, cmpval);
1570       cmpval = t1;
1571       __ encode_heap_oop(rscratch2, newval);
1572       newval = rscratch2;
1573       casw(addr, newval, cmpval);
1574     } else {
1575       casl(addr, newval, cmpval);
1576     }
1577   } else if (op->code() == lir_cas_int) {
1578     casw(addr, newval, cmpval);
1579   } else {
1580     casl(addr, newval, cmpval);
1581   }
1582 }
1583 
1584 
1585 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {


1586 
1587   Assembler::Condition acond, ncond;
1588   switch (condition) {
1589   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1590   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1591   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1592   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1593   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1594   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1595   case lir_cond_belowEqual:
1596   case lir_cond_aboveEqual:
1597   default:                    ShouldNotReachHere();
1598     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1599   }
1600 
1601   assert(result->is_single_cpu() || result->is_double_cpu(),
1602          "expect single register for result");
1603   if (opr1->is_constant() && opr2->is_constant()
1604       && opr1->type() == T_INT && opr2->type() == T_INT) {
1605     jint val1 = opr1->as_jint();

1565   if (op->code() == lir_cas_obj) {
1566     if (UseCompressedOops) {
1567       Register t1 = op->tmp1()->as_register();
1568       assert(op->tmp1()->is_valid(), "must be");
1569       __ encode_heap_oop(t1, cmpval);
1570       cmpval = t1;
1571       __ encode_heap_oop(rscratch2, newval);
1572       newval = rscratch2;
1573       casw(addr, newval, cmpval);
1574     } else {
1575       casl(addr, newval, cmpval);
1576     }
1577   } else if (op->code() == lir_cas_int) {
1578     casw(addr, newval, cmpval);
1579   } else {
1580     casl(addr, newval, cmpval);
1581   }
1582 }
1583 
1584 
1585 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1586                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1587   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1588 
1589   Assembler::Condition acond, ncond;
1590   switch (condition) {
1591   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1592   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1593   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1594   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1595   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1596   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1597   case lir_cond_belowEqual:
1598   case lir_cond_aboveEqual:
1599   default:                    ShouldNotReachHere();
1600     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1601   }
1602 
1603   assert(result->is_single_cpu() || result->is_double_cpu(),
1604          "expect single register for result");
1605   if (opr1->is_constant() && opr2->is_constant()
1606       && opr1->type() == T_INT && opr2->type() == T_INT) {
1607     jint val1 = opr1->as_jint();
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