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src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

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1562   if (op->code() == lir_cas_obj) {
1563     if (UseCompressedOops) {
1564       Register t1 = op->tmp1()->as_register();
1565       assert(op->tmp1()->is_valid(), "must be");
1566       __ encode_heap_oop(t1, cmpval);
1567       cmpval = t1;
1568       __ encode_heap_oop(rscratch2, newval);
1569       newval = rscratch2;
1570       casw(addr, newval, cmpval);
1571     } else {
1572       casl(addr, newval, cmpval);
1573     }
1574   } else if (op->code() == lir_cas_int) {
1575     casw(addr, newval, cmpval);
1576   } else {
1577     casl(addr, newval, cmpval);
1578   }
1579 }
1580 
1581 
1582 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {


1583 
1584   Assembler::Condition acond, ncond;
1585   switch (condition) {
1586   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1587   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1588   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1589   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1590   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1591   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1592   case lir_cond_belowEqual:
1593   case lir_cond_aboveEqual:
1594   default:                    ShouldNotReachHere();
1595     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1596   }
1597 
1598   assert(result->is_single_cpu() || result->is_double_cpu(),
1599          "expect single register for result");
1600   if (opr1->is_constant() && opr2->is_constant()
1601       && opr1->type() == T_INT && opr2->type() == T_INT) {
1602     jint val1 = opr1->as_jint();

1562   if (op->code() == lir_cas_obj) {
1563     if (UseCompressedOops) {
1564       Register t1 = op->tmp1()->as_register();
1565       assert(op->tmp1()->is_valid(), "must be");
1566       __ encode_heap_oop(t1, cmpval);
1567       cmpval = t1;
1568       __ encode_heap_oop(rscratch2, newval);
1569       newval = rscratch2;
1570       casw(addr, newval, cmpval);
1571     } else {
1572       casl(addr, newval, cmpval);
1573     }
1574   } else if (op->code() == lir_cas_int) {
1575     casw(addr, newval, cmpval);
1576   } else {
1577     casl(addr, newval, cmpval);
1578   }
1579 }
1580 
1581 
1582 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1583                           LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1584   assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1585 
1586   Assembler::Condition acond, ncond;
1587   switch (condition) {
1588   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1589   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1590   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1591   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1592   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1593   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1594   case lir_cond_belowEqual:
1595   case lir_cond_aboveEqual:
1596   default:                    ShouldNotReachHere();
1597     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1598   }
1599 
1600   assert(result->is_single_cpu() || result->is_double_cpu(),
1601          "expect single register for result");
1602   if (opr1->is_constant() && opr2->is_constant()
1603       && opr1->type() == T_INT && opr2->type() == T_INT) {
1604     jint val1 = opr1->as_jint();
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