1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/collectedHeap.hpp"
  36 #include "memory/universe.hpp"
  37 #include "nativeInst_ppc.hpp"
  38 #include "oops/compressedOops.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.inline.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "runtime/stubRoutines.hpp"
  44 #include "runtime/vm_version.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 
  47 #define __ _masm->
  48 
  49 
  50 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
  51 
  52 
  53 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  54   Unimplemented(); return false; // Currently not used on this platform.
  55 }
  56 
  57 
  58 LIR_Opr LIR_Assembler::receiverOpr() {
  59   return FrameMap::R3_oop_opr;
  60 }
  61 
  62 
  63 LIR_Opr LIR_Assembler::osrBufferPointer() {
  64   return FrameMap::R3_opr;
  65 }
  66 
  67 
  68 // This specifies the stack pointer decrement needed to build the frame.
  69 int LIR_Assembler::initial_frame_size_in_bytes() const {
  70   return in_bytes(frame_map()->framesize_in_bytes());
  71 }
  72 
  73 
  74 // Inline cache check: the inline cached class is in inline_cache_reg;
  75 // we fetch the class of the receiver and compare it with the cached class.
  76 // If they do not match we jump to slow case.
  77 int LIR_Assembler::check_icache() {
  78   int offset = __ offset();
  79   __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
  80   return offset;
  81 }
  82 
  83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
  84   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
  85 
  86   Label L_skip_barrier;
  87   Register klass = R20;
  88 
  89   metadata2reg(method->holder()->constant_encoding(), klass);
  90   __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
  91 
  92   __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
  93   __ mtctr(klass);
  94   __ bctr();
  95 
  96   __ bind(L_skip_barrier);
  97 }
  98 
  99 void LIR_Assembler::osr_entry() {
 100   // On-stack-replacement entry sequence:
 101   //
 102   //   1. Create a new compiled activation.
 103   //   2. Initialize local variables in the compiled activation. The expression
 104   //      stack must be empty at the osr_bci; it is not initialized.
 105   //   3. Jump to the continuation address in compiled code to resume execution.
 106 
 107   // OSR entry point
 108   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 109   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 110   ValueStack* entry_state = osr_entry->end()->state();
 111   int number_of_locks = entry_state->locks_size();
 112 
 113   // Create a frame for the compiled activation.
 114   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 115 
 116   // OSR buffer is
 117   //
 118   // locals[nlocals-1..0]
 119   // monitors[number_of_locks-1..0]
 120   //
 121   // Locals is a direct copy of the interpreter frame so in the osr buffer
 122   // the first slot in the local array is the last local from the interpreter
 123   // and the last slot is local[0] (receiver) from the interpreter.
 124   //
 125   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 126   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 127   // in the interpreter frame (the method lock if a sync method).
 128 
 129   // Initialize monitors in the compiled activation.
 130   //   R3: pointer to osr buffer
 131   //
 132   // All other registers are dead at this point and the locals will be
 133   // copied into place by code emitted in the IR.
 134 
 135   Register OSR_buf = osrBufferPointer()->as_register();
 136   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 137     int monitor_offset = BytesPerWord * method()->max_locals() +
 138       (2 * BytesPerWord) * (number_of_locks - 1);
 139     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 140     // the OSR buffer using 2 word entries: first the lock and then
 141     // the oop.
 142     for (int i = 0; i < number_of_locks; i++) {
 143       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 144 #ifdef ASSERT
 145       // Verify the interpreter's monitor has a non-null object.
 146       {
 147         Label L;
 148         __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 149         __ cmpdi(CCR0, R0, 0);
 150         __ bne(CCR0, L);
 151         __ stop("locked object is NULL");
 152         __ bind(L);
 153       }
 154 #endif // ASSERT
 155       // Copy the lock field into the compiled activation.
 156       Address ml = frame_map()->address_for_monitor_lock(i),
 157               mo = frame_map()->address_for_monitor_object(i);
 158       assert(ml.index() == noreg && mo.index() == noreg, "sanity");
 159       __ ld(R0, slot_offset + 0, OSR_buf);
 160       __ std(R0, ml.disp(), ml.base());
 161       __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 162       __ std(R0, mo.disp(), mo.base());
 163     }
 164   }
 165 }
 166 
 167 
 168 int LIR_Assembler::emit_exception_handler() {
 169   // If the last instruction is a call (typically to do a throw which
 170   // is coming at the end after block reordering) the return address
 171   // must still point into the code area in order to avoid assertion
 172   // failures when searching for the corresponding bci => add a nop
 173   // (was bug 5/14/1999 - gri).
 174   __ nop();
 175 
 176   // Generate code for the exception handler.
 177   address handler_base = __ start_a_stub(exception_handler_size());
 178 
 179   if (handler_base == NULL) {
 180     // Not enough space left for the handler.
 181     bailout("exception handler overflow");
 182     return -1;
 183   }
 184 
 185   int offset = code_offset();
 186   address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
 187   //__ load_const_optimized(R0, entry_point);
 188   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
 189   __ mtctr(R0);
 190   __ bctr();
 191 
 192   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 193   __ end_a_stub();
 194 
 195   return offset;
 196 }
 197 
 198 
 199 // Emit the code to remove the frame from the stack in the exception
 200 // unwind path.
 201 int LIR_Assembler::emit_unwind_handler() {
 202   _masm->block_comment("Unwind handler");
 203 
 204   int offset = code_offset();
 205   bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
 206   const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
 207 
 208   // Fetch the exception from TLS and clear out exception related thread state.
 209   __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 210   __ li(R0, 0);
 211   __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 212   __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
 213 
 214   __ bind(_unwind_handler_entry);
 215   __ verify_not_null_oop(Rexception);
 216   if (preserve_exception) { __ mr(Rexception_save, Rexception); }
 217 
 218   // Perform needed unlocking
 219   MonitorExitStub* stub = NULL;
 220   if (method()->is_synchronized()) {
 221     monitor_address(0, FrameMap::R4_opr);
 222     stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
 223     __ unlock_object(R5, R6, R4, *stub->entry());
 224     __ bind(*stub->continuation());
 225   }
 226 
 227   if (compilation()->env()->dtrace_method_probes()) {
 228     Unimplemented();
 229   }
 230 
 231   // Dispatch to the unwind logic.
 232   address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
 233   //__ load_const_optimized(R0, unwind_stub);
 234   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
 235   if (preserve_exception) { __ mr(Rexception, Rexception_save); }
 236   __ mtctr(R0);
 237   __ bctr();
 238 
 239   // Emit the slow path assembly.
 240   if (stub != NULL) {
 241     stub->emit_code(this);
 242   }
 243 
 244   return offset;
 245 }
 246 
 247 
 248 int LIR_Assembler::emit_deopt_handler() {
 249   // If the last instruction is a call (typically to do a throw which
 250   // is coming at the end after block reordering) the return address
 251   // must still point into the code area in order to avoid assertion
 252   // failures when searching for the corresponding bci => add a nop
 253   // (was bug 5/14/1999 - gri).
 254   __ nop();
 255 
 256   // Generate code for deopt handler.
 257   address handler_base = __ start_a_stub(deopt_handler_size());
 258 
 259   if (handler_base == NULL) {
 260     // Not enough space left for the handler.
 261     bailout("deopt handler overflow");
 262     return -1;
 263   }
 264 
 265   int offset = code_offset();
 266   __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
 267 
 268   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 269   __ end_a_stub();
 270 
 271   return offset;
 272 }
 273 
 274 
 275 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 276   if (o == NULL) {
 277     __ li(reg, 0);
 278   } else {
 279     AddressLiteral addrlit = __ constant_oop_address(o);
 280     __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
 281   }
 282 }
 283 
 284 
 285 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 286   // Allocate a new index in table to hold the object once it's been patched.
 287   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 288   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 289 
 290   AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
 291   __ load_const(reg, addrlit, R0);
 292 
 293   patching_epilog(patch, lir_patch_normal, reg, info);
 294 }
 295 
 296 
 297 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
 298   AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
 299   __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
 300 }
 301 
 302 
 303 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 304   // Allocate a new index in table to hold the klass once it's been patched.
 305   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 306   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 307 
 308   AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
 309   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 310   __ load_const(reg, addrlit, R0);
 311 
 312   patching_epilog(patch, lir_patch_normal, reg, info);
 313 }
 314 
 315 
 316 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
 317   const bool is_int = result->is_single_cpu();
 318   Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
 319   Register Rdivisor  = noreg;
 320   Register Rscratch  = temp->as_register();
 321   Register Rresult   = is_int ? result->as_register() : result->as_register_lo();
 322   long divisor = -1;
 323 
 324   if (right->is_register()) {
 325     Rdivisor = is_int ? right->as_register() : right->as_register_lo();
 326   } else {
 327     divisor = is_int ? right->as_constant_ptr()->as_jint()
 328                      : right->as_constant_ptr()->as_jlong();
 329   }
 330 
 331   assert(Rdividend != Rscratch, "");
 332   assert(Rdivisor  != Rscratch, "");
 333   assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
 334 
 335   if (Rdivisor == noreg) {
 336     if (divisor == 1) { // stupid, but can happen
 337       if (code == lir_idiv) {
 338         __ mr_if_needed(Rresult, Rdividend);
 339       } else {
 340         __ li(Rresult, 0);
 341       }
 342 
 343     } else if (is_power_of_2(divisor)) {
 344       // Convert division by a power of two into some shifts and logical operations.
 345       int log2 = log2i_exact(divisor);
 346 
 347       // Round towards 0.
 348       if (divisor == 2) {
 349         if (is_int) {
 350           __ srwi(Rscratch, Rdividend, 31);
 351         } else {
 352           __ srdi(Rscratch, Rdividend, 63);
 353         }
 354       } else {
 355         if (is_int) {
 356           __ srawi(Rscratch, Rdividend, 31);
 357         } else {
 358           __ sradi(Rscratch, Rdividend, 63);
 359         }
 360         __ clrldi(Rscratch, Rscratch, 64-log2);
 361       }
 362       __ add(Rscratch, Rdividend, Rscratch);
 363 
 364       if (code == lir_idiv) {
 365         if (is_int) {
 366           __ srawi(Rresult, Rscratch, log2);
 367         } else {
 368           __ sradi(Rresult, Rscratch, log2);
 369         }
 370       } else { // lir_irem
 371         __ clrrdi(Rscratch, Rscratch, log2);
 372         __ sub(Rresult, Rdividend, Rscratch);
 373       }
 374 
 375     } else if (divisor == -1) {
 376       if (code == lir_idiv) {
 377         __ neg(Rresult, Rdividend);
 378       } else {
 379         __ li(Rresult, 0);
 380       }
 381 
 382     } else {
 383       __ load_const_optimized(Rscratch, divisor);
 384       if (code == lir_idiv) {
 385         if (is_int) {
 386           __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 387         } else {
 388           __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 389         }
 390       } else {
 391         assert(Rscratch != R0, "need both");
 392         if (is_int) {
 393           __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 394           __ mullw(Rscratch, R0, Rscratch);
 395         } else {
 396           __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 397           __ mulld(Rscratch, R0, Rscratch);
 398         }
 399         __ sub(Rresult, Rdividend, Rscratch);
 400       }
 401 
 402     }
 403     return;
 404   }
 405 
 406   Label regular, done;
 407   if (is_int) {
 408     __ cmpwi(CCR0, Rdivisor, -1);
 409   } else {
 410     __ cmpdi(CCR0, Rdivisor, -1);
 411   }
 412   __ bne(CCR0, regular);
 413   if (code == lir_idiv) {
 414     __ neg(Rresult, Rdividend);
 415     __ b(done);
 416     __ bind(regular);
 417     if (is_int) {
 418       __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 419     } else {
 420       __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 421     }
 422   } else { // lir_irem
 423     __ li(Rresult, 0);
 424     __ b(done);
 425     __ bind(regular);
 426     if (is_int) {
 427       __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 428       __ mullw(Rscratch, Rscratch, Rdivisor);
 429     } else {
 430       __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 431       __ mulld(Rscratch, Rscratch, Rdivisor);
 432     }
 433     __ sub(Rresult, Rdividend, Rscratch);
 434   }
 435   __ bind(done);
 436 }
 437 
 438 
 439 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 440   switch (op->code()) {
 441   case lir_idiv:
 442   case lir_irem:
 443     arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
 444                     op->result_opr(), op->info());
 445     break;
 446   case lir_fmad:
 447     __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
 448              op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
 449     break;
 450   case lir_fmaf:
 451     __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
 452               op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
 453     break;
 454   default: ShouldNotReachHere(); break;
 455   }
 456 }
 457 
 458 
 459 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 460 #ifdef ASSERT
 461   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 462   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 463   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 464   assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
 465 #endif
 466 
 467   Label *L = op->label();
 468   if (op->cond() == lir_cond_always) {
 469     __ b(*L);
 470   } else {
 471     Label done;
 472     bool is_unordered = false;
 473     if (op->code() == lir_cond_float_branch) {
 474       assert(op->ublock() != NULL, "must have unordered successor");
 475       is_unordered = true;
 476     } else {
 477       assert(op->code() == lir_branch, "just checking");
 478     }
 479 
 480     bool positive = false;
 481     Assembler::Condition cond = Assembler::equal;
 482     switch (op->cond()) {
 483       case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; is_unordered = false; break;
 484       case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; is_unordered = false; break;
 485       case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
 486       case lir_cond_belowEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 487       case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
 488       case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
 489       case lir_cond_aboveEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 490       case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
 491       default:                    ShouldNotReachHere();
 492     }
 493     int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
 494     int bi = Assembler::bi0(BOOL_RESULT, cond);
 495     if (is_unordered) {
 496       if (positive) {
 497         if (op->ublock() == op->block()) {
 498           __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
 499         }
 500       } else {
 501         if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
 502       }
 503     }
 504     __ bc_far_optimized(bo, bi, *L);
 505     __ bind(done);
 506   }
 507 }
 508 
 509 
 510 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 511   Bytecodes::Code code = op->bytecode();
 512   LIR_Opr src = op->in_opr(),
 513           dst = op->result_opr();
 514 
 515   switch(code) {
 516     case Bytecodes::_i2l: {
 517       __ extsw(dst->as_register_lo(), src->as_register());
 518       break;
 519     }
 520     case Bytecodes::_l2i: {
 521       __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
 522       break;
 523     }
 524     case Bytecodes::_i2b: {
 525       __ extsb(dst->as_register(), src->as_register());
 526       break;
 527     }
 528     case Bytecodes::_i2c: {
 529       __ clrldi(dst->as_register(), src->as_register(), 64-16);
 530       break;
 531     }
 532     case Bytecodes::_i2s: {
 533       __ extsh(dst->as_register(), src->as_register());
 534       break;
 535     }
 536     case Bytecodes::_i2d:
 537     case Bytecodes::_l2d: {
 538       bool src_in_memory = !VM_Version::has_mtfprd();
 539       FloatRegister rdst = dst->as_double_reg();
 540       FloatRegister rsrc;
 541       if (src_in_memory) {
 542         rsrc = src->as_double_reg(); // via mem
 543       } else {
 544         // move src to dst register
 545         if (code == Bytecodes::_i2d) {
 546           __ mtfprwa(rdst, src->as_register());
 547         } else {
 548           __ mtfprd(rdst, src->as_register_lo());
 549         }
 550         rsrc = rdst;
 551       }
 552       __ fcfid(rdst, rsrc);
 553       break;
 554     }
 555     case Bytecodes::_i2f:
 556     case Bytecodes::_l2f: {
 557       bool src_in_memory = !VM_Version::has_mtfprd();
 558       FloatRegister rdst = dst->as_float_reg();
 559       FloatRegister rsrc;
 560       if (src_in_memory) {
 561         rsrc = src->as_double_reg(); // via mem
 562       } else {
 563         // move src to dst register
 564         if (code == Bytecodes::_i2f) {
 565           __ mtfprwa(rdst, src->as_register());
 566         } else {
 567           __ mtfprd(rdst, src->as_register_lo());
 568         }
 569         rsrc = rdst;
 570       }
 571       if (VM_Version::has_fcfids()) {
 572         __ fcfids(rdst, rsrc);
 573       } else {
 574         assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
 575         __ fcfid(rdst, rsrc);
 576         __ frsp(rdst, rdst);
 577       }
 578       break;
 579     }
 580     case Bytecodes::_f2d: {
 581       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
 582       break;
 583     }
 584     case Bytecodes::_d2f: {
 585       __ frsp(dst->as_float_reg(), src->as_double_reg());
 586       break;
 587     }
 588     case Bytecodes::_d2i:
 589     case Bytecodes::_f2i: {
 590       bool dst_in_memory = !VM_Version::has_mtfprd();
 591       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
 592       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 593       Label L;
 594       // Result must be 0 if value is NaN; test by comparing value to itself.
 595       __ fcmpu(CCR0, rsrc, rsrc);
 596       if (dst_in_memory) {
 597         __ li(R0, 0); // 0 in case of NAN
 598         __ std(R0, addr.disp(), addr.base());
 599       } else {
 600         __ li(dst->as_register(), 0);
 601       }
 602       __ bso(CCR0, L);
 603       __ fctiwz(rsrc, rsrc); // USE_KILL
 604       if (dst_in_memory) {
 605         __ stfd(rsrc, addr.disp(), addr.base());
 606       } else {
 607         __ mffprd(dst->as_register(), rsrc);
 608       }
 609       __ bind(L);
 610       break;
 611     }
 612     case Bytecodes::_d2l:
 613     case Bytecodes::_f2l: {
 614       bool dst_in_memory = !VM_Version::has_mtfprd();
 615       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
 616       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 617       Label L;
 618       // Result must be 0 if value is NaN; test by comparing value to itself.
 619       __ fcmpu(CCR0, rsrc, rsrc);
 620       if (dst_in_memory) {
 621         __ li(R0, 0); // 0 in case of NAN
 622         __ std(R0, addr.disp(), addr.base());
 623       } else {
 624         __ li(dst->as_register_lo(), 0);
 625       }
 626       __ bso(CCR0, L);
 627       __ fctidz(rsrc, rsrc); // USE_KILL
 628       if (dst_in_memory) {
 629         __ stfd(rsrc, addr.disp(), addr.base());
 630       } else {
 631         __ mffprd(dst->as_register_lo(), rsrc);
 632       }
 633       __ bind(L);
 634       break;
 635     }
 636 
 637     default: ShouldNotReachHere();
 638   }
 639 }
 640 
 641 
 642 void LIR_Assembler::align_call(LIR_Code) {
 643   // do nothing since all instructions are word aligned on ppc
 644 }
 645 
 646 
 647 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
 648   int start_offset = __ offset();
 649   // Put the entry point as a constant into the constant pool.
 650   const address entry_point_toc_addr   = __ address_constant(target, RelocationHolder::none);
 651   if (entry_point_toc_addr == NULL) {
 652     bailout("const section overflow");
 653     return false;
 654   }
 655   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
 656 
 657   // Emit the trampoline stub which will be related to the branch-and-link below.
 658   address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
 659   if (!stub) {
 660     bailout("no space for trampoline stub");
 661     return false;
 662   }
 663   return true;
 664 }
 665 
 666 
 667 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 668   assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
 669 
 670   bool success = emit_trampoline_stub_for_call(op->addr());
 671   if (!success) { return; }
 672 
 673   __ relocate(rtype);
 674   // Note: At this point we do not have the address of the trampoline
 675   // stub, and the entry point might be too far away for bl, so __ pc()
 676   // serves as dummy and the bl will be patched later.
 677   __ code()->set_insts_mark();
 678   __ bl(__ pc());
 679   add_call_info(code_offset(), op->info());
 680 }
 681 
 682 
 683 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 684   __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
 685 
 686   // Virtual call relocation will point to ic load.
 687   address virtual_call_meta_addr = __ pc();
 688   // Load a clear inline cache.
 689   AddressLiteral empty_ic((address) Universe::non_oop_word());
 690   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
 691   if (!success) {
 692     bailout("const section overflow");
 693     return;
 694   }
 695   // Call to fixup routine. Fixup routine uses ScopeDesc info
 696   // to determine who we intended to call.
 697   __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
 698 
 699   success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
 700   if (!success) { return; }
 701 
 702   // Note: At this point we do not have the address of the trampoline
 703   // stub, and the entry point might be too far away for bl, so __ pc()
 704   // serves as dummy and the bl will be patched later.
 705   __ bl(__ pc());
 706   add_call_info(code_offset(), op->info());
 707 }
 708 
 709 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
 710   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
 711   __ null_check(addr, stub->entry());
 712   append_code_stub(stub);
 713 }
 714 
 715 
 716 // Attention: caller must encode oop if needed
 717 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
 718   int store_offset;
 719   if (!Assembler::is_simm16(offset)) {
 720     // For offsets larger than a simm16 we setup the offset.
 721     assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
 722     __ load_const_optimized(R0, offset);
 723     store_offset = store(from_reg, base, R0, type, wide);
 724   } else {
 725     store_offset = code_offset();
 726     switch (type) {
 727       case T_BOOLEAN: // fall through
 728       case T_BYTE  : __ stb(from_reg->as_register(), offset, base); break;
 729       case T_CHAR  :
 730       case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
 731       case T_INT   : __ stw(from_reg->as_register(), offset, base); break;
 732       case T_LONG  : __ std(from_reg->as_register_lo(), offset, base); break;
 733       case T_ADDRESS:
 734       case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
 735       case T_ARRAY : // fall through
 736       case T_OBJECT:
 737         {
 738           if (UseCompressedOops && !wide) {
 739             // Encoding done in caller
 740             __ stw(from_reg->as_register(), offset, base);
 741             __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
 742           } else {
 743             __ std(from_reg->as_register(), offset, base);
 744             __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
 745           }
 746           break;
 747         }
 748       case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
 749       case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
 750       default      : ShouldNotReachHere();
 751     }
 752   }
 753   return store_offset;
 754 }
 755 
 756 
 757 // Attention: caller must encode oop if needed
 758 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
 759   int store_offset = code_offset();
 760   switch (type) {
 761     case T_BOOLEAN: // fall through
 762     case T_BYTE  : __ stbx(from_reg->as_register(), base, disp); break;
 763     case T_CHAR  :
 764     case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
 765     case T_INT   : __ stwx(from_reg->as_register(), base, disp); break;
 766     case T_LONG  :
 767 #ifdef _LP64
 768       __ stdx(from_reg->as_register_lo(), base, disp);
 769 #else
 770       Unimplemented();
 771 #endif
 772       break;
 773     case T_ADDRESS:
 774       __ stdx(from_reg->as_register(), base, disp);
 775       break;
 776     case T_ARRAY : // fall through
 777     case T_OBJECT:
 778       {
 779         if (UseCompressedOops && !wide) {
 780           // Encoding done in caller.
 781           __ stwx(from_reg->as_register(), base, disp);
 782           __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 783         } else {
 784           __ stdx(from_reg->as_register(), base, disp);
 785           __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
 786         }
 787         break;
 788       }
 789     case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
 790     case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
 791     default      : ShouldNotReachHere();
 792   }
 793   return store_offset;
 794 }
 795 
 796 
 797 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
 798   int load_offset;
 799   if (!Assembler::is_simm16(offset)) {
 800     // For offsets larger than a simm16 we setup the offset.
 801     __ load_const_optimized(R0, offset);
 802     load_offset = load(base, R0, to_reg, type, wide);
 803   } else {
 804     load_offset = code_offset();
 805     switch(type) {
 806       case T_BOOLEAN: // fall through
 807       case T_BYTE  :   __ lbz(to_reg->as_register(), offset, base);
 808                        __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 809       case T_CHAR  :   __ lhz(to_reg->as_register(), offset, base); break;
 810       case T_SHORT :   __ lha(to_reg->as_register(), offset, base); break;
 811       case T_INT   :   __ lwa(to_reg->as_register(), offset, base); break;
 812       case T_LONG  :   __ ld(to_reg->as_register_lo(), offset, base); break;
 813       case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
 814       case T_ADDRESS:
 815         __ ld(to_reg->as_register(), offset, base);
 816         break;
 817       case T_ARRAY : // fall through
 818       case T_OBJECT:
 819         {
 820           if (UseCompressedOops && !wide) {
 821             __ lwz(to_reg->as_register(), offset, base);
 822             __ decode_heap_oop(to_reg->as_register());
 823           } else {
 824             __ ld(to_reg->as_register(), offset, base);
 825           }
 826           __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
 827           break;
 828         }
 829       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
 830       case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
 831       default      : ShouldNotReachHere();
 832     }
 833   }
 834   return load_offset;
 835 }
 836 
 837 
 838 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
 839   int load_offset = code_offset();
 840   switch(type) {
 841     case T_BOOLEAN: // fall through
 842     case T_BYTE  :  __ lbzx(to_reg->as_register(), base, disp);
 843                     __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 844     case T_CHAR  :  __ lhzx(to_reg->as_register(), base, disp); break;
 845     case T_SHORT :  __ lhax(to_reg->as_register(), base, disp); break;
 846     case T_INT   :  __ lwax(to_reg->as_register(), base, disp); break;
 847     case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
 848     case T_ARRAY : // fall through
 849     case T_OBJECT:
 850       {
 851         if (UseCompressedOops && !wide) {
 852           __ lwzx(to_reg->as_register(), base, disp);
 853           __ decode_heap_oop(to_reg->as_register());
 854         } else {
 855           __ ldx(to_reg->as_register(), base, disp);
 856         }
 857         __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
 858         break;
 859       }
 860     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;
 861     case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
 862     case T_LONG  :
 863 #ifdef _LP64
 864       __ ldx(to_reg->as_register_lo(), base, disp);
 865 #else
 866       Unimplemented();
 867 #endif
 868       break;
 869     default      : ShouldNotReachHere();
 870   }
 871   return load_offset;
 872 }
 873 
 874 
 875 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 876   LIR_Const* c = src->as_constant_ptr();
 877   Register src_reg = R0;
 878   switch (c->type()) {
 879     case T_INT:
 880     case T_FLOAT: {
 881       int value = c->as_jint_bits();
 882       __ load_const_optimized(src_reg, value);
 883       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 884       __ stw(src_reg, addr.disp(), addr.base());
 885       break;
 886     }
 887     case T_ADDRESS: {
 888       int value = c->as_jint_bits();
 889       __ load_const_optimized(src_reg, value);
 890       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 891       __ std(src_reg, addr.disp(), addr.base());
 892       break;
 893     }
 894     case T_OBJECT: {
 895       jobject2reg(c->as_jobject(), src_reg);
 896       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 897       __ std(src_reg, addr.disp(), addr.base());
 898       break;
 899     }
 900     case T_LONG:
 901     case T_DOUBLE: {
 902       int value = c->as_jlong_bits();
 903       __ load_const_optimized(src_reg, value);
 904       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
 905       __ std(src_reg, addr.disp(), addr.base());
 906       break;
 907     }
 908     default:
 909       Unimplemented();
 910   }
 911 }
 912 
 913 
 914 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 915   LIR_Const* c = src->as_constant_ptr();
 916   LIR_Address* addr = dest->as_address_ptr();
 917   Register base = addr->base()->as_pointer_register();
 918   LIR_Opr tmp = LIR_OprFact::illegalOpr;
 919   int offset = -1;
 920   // Null check for large offsets in LIRGenerator::do_StoreField.
 921   bool needs_explicit_null_check = !ImplicitNullChecks;
 922 
 923   if (info != NULL && needs_explicit_null_check) {
 924     explicit_null_check(base, info);
 925   }
 926 
 927   switch (c->type()) {
 928     case T_FLOAT: type = T_INT;
 929     case T_INT:
 930     case T_ADDRESS: {
 931       tmp = FrameMap::R0_opr;
 932       __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
 933       break;
 934     }
 935     case T_DOUBLE: type = T_LONG;
 936     case T_LONG: {
 937       tmp = FrameMap::R0_long_opr;
 938       __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
 939       break;
 940     }
 941     case T_OBJECT: {
 942       tmp = FrameMap::R0_opr;
 943       if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
 944         AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
 945         __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
 946         __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
 947         __ ori(R0, R0, oop_addr.value() & 0xffff);
 948       } else {
 949         jobject2reg(c->as_jobject(), R0);
 950       }
 951       break;
 952     }
 953     default:
 954       Unimplemented();
 955   }
 956 
 957   // Handle either reg+reg or reg+disp address.
 958   if (addr->index()->is_valid()) {
 959     assert(addr->disp() == 0, "must be zero");
 960     offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
 961   } else {
 962     assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
 963     offset = store(tmp, base, addr->disp(), type, wide);
 964   }
 965 
 966   if (info != NULL) {
 967     assert(offset != -1, "offset should've been set");
 968     if (!needs_explicit_null_check) {
 969       add_debug_info_for_null_check(offset, info);
 970     }
 971   }
 972 }
 973 
 974 
 975 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 976   LIR_Const* c = src->as_constant_ptr();
 977   LIR_Opr to_reg = dest;
 978 
 979   switch (c->type()) {
 980     case T_INT: {
 981       assert(patch_code == lir_patch_none, "no patching handled here");
 982       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
 983       break;
 984     }
 985     case T_ADDRESS: {
 986       assert(patch_code == lir_patch_none, "no patching handled here");
 987       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);  // Yes, as_jint ...
 988       break;
 989     }
 990     case T_LONG: {
 991       assert(patch_code == lir_patch_none, "no patching handled here");
 992       __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
 993       break;
 994     }
 995 
 996     case T_OBJECT: {
 997       if (patch_code == lir_patch_none) {
 998         jobject2reg(c->as_jobject(), to_reg->as_register());
 999       } else {
1000         jobject2reg_with_patching(to_reg->as_register(), info);
1001       }
1002       break;
1003     }
1004 
1005     case T_METADATA:
1006       {
1007         if (patch_code == lir_patch_none) {
1008           metadata2reg(c->as_metadata(), to_reg->as_register());
1009         } else {
1010           klass2reg_with_patching(to_reg->as_register(), info);
1011         }
1012       }
1013       break;
1014 
1015     case T_FLOAT:
1016       {
1017         if (to_reg->is_single_fpu()) {
1018           address const_addr = __ float_constant(c->as_jfloat());
1019           if (const_addr == NULL) {
1020             bailout("const section overflow");
1021             break;
1022           }
1023           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1024           __ relocate(rspec);
1025           __ load_const(R0, const_addr);
1026           __ lfsx(to_reg->as_float_reg(), R0);
1027         } else {
1028           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1029           __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1030         }
1031       }
1032       break;
1033 
1034     case T_DOUBLE:
1035       {
1036         if (to_reg->is_double_fpu()) {
1037           address const_addr = __ double_constant(c->as_jdouble());
1038           if (const_addr == NULL) {
1039             bailout("const section overflow");
1040             break;
1041           }
1042           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1043           __ relocate(rspec);
1044           __ load_const(R0, const_addr);
1045           __ lfdx(to_reg->as_double_reg(), R0);
1046         } else {
1047           assert(to_reg->is_double_cpu(), "Must be a long register.");
1048           __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1049         }
1050       }
1051       break;
1052 
1053     default:
1054       ShouldNotReachHere();
1055   }
1056 }
1057 
1058 
1059 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1060   Unimplemented(); return Address();
1061 }
1062 
1063 
1064 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1065   if (addr->index()->is_illegal()) {
1066     return (RegisterOrConstant)(addr->disp());
1067   } else {
1068     return (RegisterOrConstant)(addr->index()->as_pointer_register());
1069   }
1070 }
1071 
1072 
1073 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1074   const Register tmp = R0;
1075   switch (type) {
1076     case T_INT:
1077     case T_FLOAT: {
1078       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1079       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1080       __ lwz(tmp, from.disp(), from.base());
1081       __ stw(tmp, to.disp(), to.base());
1082       break;
1083     }
1084     case T_ADDRESS:
1085     case T_OBJECT: {
1086       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1087       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1088       __ ld(tmp, from.disp(), from.base());
1089       __ std(tmp, to.disp(), to.base());
1090       break;
1091     }
1092     case T_LONG:
1093     case T_DOUBLE: {
1094       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1095       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1096       __ ld(tmp, from.disp(), from.base());
1097       __ std(tmp, to.disp(), to.base());
1098       break;
1099     }
1100 
1101     default:
1102       ShouldNotReachHere();
1103   }
1104 }
1105 
1106 
1107 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1108   Unimplemented(); return Address();
1109 }
1110 
1111 
1112 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1113   Unimplemented(); return Address();
1114 }
1115 
1116 
1117 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1118                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1119 
1120   assert(type != T_METADATA, "load of metadata ptr not supported");
1121   LIR_Address* addr = src_opr->as_address_ptr();
1122   LIR_Opr to_reg = dest;
1123 
1124   Register src = addr->base()->as_pointer_register();
1125   Register disp_reg = noreg;
1126   int disp_value = addr->disp();
1127   bool needs_patching = (patch_code != lir_patch_none);
1128   // null check for large offsets in LIRGenerator::do_LoadField
1129   bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1130 
1131   if (info != NULL && needs_explicit_null_check) {
1132     explicit_null_check(src, info);
1133   }
1134 
1135   if (addr->base()->type() == T_OBJECT) {
1136     __ verify_oop(src, FILE_AND_LINE);
1137   }
1138 
1139   PatchingStub* patch = NULL;
1140   if (needs_patching) {
1141     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1142     assert(!to_reg->is_double_cpu() ||
1143            patch_code == lir_patch_none ||
1144            patch_code == lir_patch_normal, "patching doesn't match register");
1145   }
1146 
1147   if (addr->index()->is_illegal()) {
1148     if (!Assembler::is_simm16(disp_value)) {
1149       if (needs_patching) {
1150         __ load_const32(R0, 0); // patchable int
1151       } else {
1152         __ load_const_optimized(R0, disp_value);
1153       }
1154       disp_reg = R0;
1155     }
1156   } else {
1157     disp_reg = addr->index()->as_pointer_register();
1158     assert(disp_value == 0, "can't handle 3 operand addresses");
1159   }
1160 
1161   // Remember the offset of the load. The patching_epilog must be done
1162   // before the call to add_debug_info, otherwise the PcDescs don't get
1163   // entered in increasing order.
1164   int offset;
1165 
1166   if (disp_reg == noreg) {
1167     assert(Assembler::is_simm16(disp_value), "should have set this up");
1168     offset = load(src, disp_value, to_reg, type, wide);
1169   } else {
1170     offset = load(src, disp_reg, to_reg, type, wide);
1171   }
1172 
1173   if (patch != NULL) {
1174     patching_epilog(patch, patch_code, src, info);
1175   }
1176   if (info != NULL && !needs_explicit_null_check) {
1177     add_debug_info_for_null_check(offset, info);
1178   }
1179 }
1180 
1181 
1182 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1183   Address addr;
1184   if (src->is_single_word()) {
1185     addr = frame_map()->address_for_slot(src->single_stack_ix());
1186   } else if (src->is_double_word())  {
1187     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1188   }
1189 
1190   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1191 }
1192 
1193 
1194 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1195   Address addr;
1196   if (dest->is_single_word()) {
1197     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1198   } else if (dest->is_double_word())  {
1199     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1200   }
1201 
1202   store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1203 }
1204 
1205 
1206 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1207   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1208     if (from_reg->is_double_fpu()) {
1209       // double to double moves
1210       assert(to_reg->is_double_fpu(), "should match");
1211       __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1212     } else {
1213       // float to float moves
1214       assert(to_reg->is_single_fpu(), "should match");
1215       __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1216     }
1217   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1218     if (from_reg->is_double_cpu()) {
1219       __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1220     } else if (to_reg->is_double_cpu()) {
1221       // int to int moves
1222       __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1223     } else {
1224       // int to int moves
1225       __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1226     }
1227   } else {
1228     ShouldNotReachHere();
1229   }
1230   if (is_reference_type(to_reg->type())) {
1231     __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1232   }
1233 }
1234 
1235 
1236 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1237                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1238                             bool wide) {
1239   assert(type != T_METADATA, "store of metadata ptr not supported");
1240   LIR_Address* addr = dest->as_address_ptr();
1241 
1242   Register src = addr->base()->as_pointer_register();
1243   Register disp_reg = noreg;
1244   int disp_value = addr->disp();
1245   bool needs_patching = (patch_code != lir_patch_none);
1246   bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1247                       CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1248   bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1249   bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1250   // Null check for large offsets in LIRGenerator::do_StoreField.
1251   bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1252 
1253   if (info != NULL && needs_explicit_null_check) {
1254     explicit_null_check(src, info);
1255   }
1256 
1257   if (addr->base()->is_oop_register()) {
1258     __ verify_oop(src, FILE_AND_LINE);
1259   }
1260 
1261   PatchingStub* patch = NULL;
1262   if (needs_patching) {
1263     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1264     assert(!from_reg->is_double_cpu() ||
1265            patch_code == lir_patch_none ||
1266            patch_code == lir_patch_normal, "patching doesn't match register");
1267   }
1268 
1269   if (addr->index()->is_illegal()) {
1270     if (load_disp) {
1271       disp_reg = use_R29 ? R29_TOC : R0;
1272       if (needs_patching) {
1273         __ load_const32(disp_reg, 0); // patchable int
1274       } else {
1275         __ load_const_optimized(disp_reg, disp_value);
1276       }
1277     }
1278   } else {
1279     disp_reg = addr->index()->as_pointer_register();
1280     assert(disp_value == 0, "can't handle 3 operand addresses");
1281   }
1282 
1283   // remember the offset of the store. The patching_epilog must be done
1284   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1285   // entered in increasing order.
1286   int offset;
1287 
1288   if (compress_oop) {
1289     Register co = __ encode_heap_oop(R0, from_reg->as_register());
1290     from_reg = FrameMap::as_opr(co);
1291   }
1292 
1293   if (disp_reg == noreg) {
1294     assert(Assembler::is_simm16(disp_value), "should have set this up");
1295     offset = store(from_reg, src, disp_value, type, wide);
1296   } else {
1297     offset = store(from_reg, src, disp_reg, type, wide);
1298   }
1299 
1300   if (use_R29) {
1301     __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1302   }
1303 
1304   if (patch != NULL) {
1305     patching_epilog(patch, patch_code, src, info);
1306   }
1307 
1308   if (info != NULL && !needs_explicit_null_check) {
1309     add_debug_info_for_null_check(offset, info);
1310   }
1311 }
1312 
1313 
1314 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1315   const Register return_pc = R31;  // Must survive C-call to enable_stack_reserved_zone().
1316   const Register temp      = R12;
1317 
1318   // Pop the stack before the safepoint code.
1319   int frame_size = initial_frame_size_in_bytes();
1320   if (Assembler::is_simm(frame_size, 16)) {
1321     __ addi(R1_SP, R1_SP, frame_size);
1322   } else {
1323     __ pop_frame();
1324   }
1325 
1326   // Restore return pc relative to callers' sp.
1327   __ ld(return_pc, _abi0(lr), R1_SP);
1328   // Move return pc to LR.
1329   __ mtlr(return_pc);
1330 
1331   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1332     __ reserved_stack_check(return_pc);
1333   }
1334 
1335   // We need to mark the code position where the load from the safepoint
1336   // polling page was emitted as relocInfo::poll_return_type here.
1337   if (!UseSIGTRAP) {
1338     code_stub->set_safepoint_offset(__ offset());
1339     __ relocate(relocInfo::poll_return_type);
1340   }
1341   __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1342 
1343   // Return.
1344   __ blr();
1345 }
1346 
1347 
1348 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1349   const Register poll_addr = tmp->as_register();
1350   __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1351   if (info != NULL) {
1352     add_debug_info_for_branch(info);
1353   }
1354   int offset = __ offset();
1355   __ relocate(relocInfo::poll_type);
1356   __ load_from_polling_page(poll_addr);
1357 
1358   return offset;
1359 }
1360 
1361 
1362 void LIR_Assembler::emit_static_call_stub() {
1363   address call_pc = __ pc();
1364   address stub = __ start_a_stub(static_call_stub_size());
1365   if (stub == NULL) {
1366     bailout("static call stub overflow");
1367     return;
1368   }
1369 
1370   // For java_to_interp stubs we use R11_scratch1 as scratch register
1371   // and in call trampoline stubs we use R12_scratch2. This way we
1372   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1373   const Register reg_scratch = R11_scratch1;
1374 
1375   // Create a static stub relocation which relates this stub
1376   // with the call instruction at insts_call_instruction_offset in the
1377   // instructions code-section.
1378   int start = __ offset();
1379   __ relocate(static_stub_Relocation::spec(call_pc));
1380 
1381   // Now, create the stub's code:
1382   // - load the TOC
1383   // - load the inline cache oop from the constant pool
1384   // - load the call target from the constant pool
1385   // - call
1386   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1387   AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1388   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1389 
1390   if (ReoptimizeCallSequences) {
1391     __ b64_patchable((address)-1, relocInfo::none);
1392   } else {
1393     AddressLiteral a((address)-1);
1394     success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1395     __ mtctr(reg_scratch);
1396     __ bctr();
1397   }
1398   if (!success) {
1399     bailout("const section overflow");
1400     return;
1401   }
1402 
1403   assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1404   __ end_a_stub();
1405 }
1406 
1407 
1408 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1409   bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1410   if (opr1->is_single_fpu()) {
1411     __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1412   } else if (opr1->is_double_fpu()) {
1413     __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1414   } else if (opr1->is_single_cpu()) {
1415     if (opr2->is_constant()) {
1416       switch (opr2->as_constant_ptr()->type()) {
1417         case T_INT:
1418           {
1419             jint con = opr2->as_constant_ptr()->as_jint();
1420             if (unsigned_comp) {
1421               if (Assembler::is_uimm(con, 16)) {
1422                 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1423               } else {
1424                 __ load_const_optimized(R0, con);
1425                 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1426               }
1427             } else {
1428               if (Assembler::is_simm(con, 16)) {
1429                 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1430               } else {
1431                 __ load_const_optimized(R0, con);
1432                 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1433               }
1434             }
1435           }
1436           break;
1437 
1438         case T_OBJECT:
1439           // There are only equal/notequal comparisons on objects.
1440           {
1441             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1442             jobject con = opr2->as_constant_ptr()->as_jobject();
1443             if (con == NULL) {
1444               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1445             } else {
1446               jobject2reg(con, R0);
1447               __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1448             }
1449           }
1450           break;
1451 
1452         case T_METADATA:
1453           // We only need, for now, comparison with NULL for metadata.
1454           {
1455             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1456             Metadata* p = opr2->as_constant_ptr()->as_metadata();
1457             if (p == NULL) {
1458               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1459             } else {
1460               ShouldNotReachHere();
1461             }
1462           }
1463           break;
1464 
1465         default:
1466           ShouldNotReachHere();
1467           break;
1468       }
1469     } else {
1470       assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1471       if (is_reference_type(opr1->type())) {
1472         // There are only equal/notequal comparisons on objects.
1473         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1474         __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1475       } else {
1476         if (unsigned_comp) {
1477           __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1478         } else {
1479           __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1480         }
1481       }
1482     }
1483   } else if (opr1->is_double_cpu()) {
1484     if (opr2->is_constant()) {
1485       jlong con = opr2->as_constant_ptr()->as_jlong();
1486       if (unsigned_comp) {
1487         if (Assembler::is_uimm(con, 16)) {
1488           __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1489         } else {
1490           __ load_const_optimized(R0, con);
1491           __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1492         }
1493       } else {
1494         if (Assembler::is_simm(con, 16)) {
1495           __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1496         } else {
1497           __ load_const_optimized(R0, con);
1498           __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1499         }
1500       }
1501     } else if (opr2->is_register()) {
1502       if (unsigned_comp) {
1503         __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1504       } else {
1505         __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1506       }
1507     } else {
1508       ShouldNotReachHere();
1509     }
1510   } else {
1511     ShouldNotReachHere();
1512   }
1513 }
1514 
1515 
1516 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1517   const Register Rdst = dst->as_register();
1518   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1519     bool is_unordered_less = (code == lir_ucmp_fd2i);
1520     if (left->is_single_fpu()) {
1521       __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1522     } else if (left->is_double_fpu()) {
1523       __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1524     } else {
1525       ShouldNotReachHere();
1526     }
1527     __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1528   } else if (code == lir_cmp_l2i) {
1529     __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1530     __ set_cmp3(Rdst);  // set result as follows: <: -1, =: 0, >: 1
1531   } else {
1532     ShouldNotReachHere();
1533   }
1534 }
1535 
1536 
1537 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1538   if (src->is_constant()) {
1539     lasm->const2reg(src, dst, lir_patch_none, NULL);
1540   } else if (src->is_register()) {
1541     lasm->reg2reg(src, dst);
1542   } else if (src->is_stack()) {
1543     lasm->stack2reg(src, dst, dst->type());
1544   } else {
1545     ShouldNotReachHere();
1546   }
1547 }
1548 
1549 
1550 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1551   if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1552     load_to_reg(this, opr1, result); // Condition doesn't matter.
1553     return;
1554   }
1555 
1556   bool positive = false;
1557   Assembler::Condition cond = Assembler::equal;
1558   switch (condition) {
1559     case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; break;
1560     case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; break;
1561     case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
1562     case lir_cond_belowEqual:
1563     case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
1564     case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
1565     case lir_cond_aboveEqual:
1566     case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
1567     default:                    ShouldNotReachHere();
1568   }
1569 
1570   // Try to use isel on >=Power7.
1571   if (VM_Version::has_isel() && result->is_cpu_register()) {
1572     bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1573     const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1574 
1575     // We can use result_reg to load one operand if not already in register.
1576     Register first  = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1577              second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1578 
1579     if (first != second) {
1580       if (!o1_is_reg) {
1581         load_to_reg(this, opr1, result);
1582       }
1583 
1584       if (!o2_is_reg) {
1585         load_to_reg(this, opr2, result);
1586       }
1587 
1588       __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1589       return;
1590     }
1591   } // isel
1592 
1593   load_to_reg(this, opr1, result);
1594 
1595   Label skip;
1596   int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1597   int bi = Assembler::bi0(BOOL_RESULT, cond);
1598   __ bc(bo, bi, skip);
1599 
1600   load_to_reg(this, opr2, result);
1601   __ bind(skip);
1602 }
1603 
1604 
1605 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1606                              CodeEmitInfo* info, bool pop_fpu_stack) {
1607   assert(info == NULL, "unused on this code path");
1608   assert(left->is_register(), "wrong items state");
1609   assert(dest->is_register(), "wrong items state");
1610 
1611   if (right->is_register()) {
1612     if (dest->is_float_kind()) {
1613 
1614       FloatRegister lreg, rreg, res;
1615       if (right->is_single_fpu()) {
1616         lreg = left->as_float_reg();
1617         rreg = right->as_float_reg();
1618         res  = dest->as_float_reg();
1619         switch (code) {
1620           case lir_add: __ fadds(res, lreg, rreg); break;
1621           case lir_sub: __ fsubs(res, lreg, rreg); break;
1622           case lir_mul: __ fmuls(res, lreg, rreg); break;
1623           case lir_div: __ fdivs(res, lreg, rreg); break;
1624           default: ShouldNotReachHere();
1625         }
1626       } else {
1627         lreg = left->as_double_reg();
1628         rreg = right->as_double_reg();
1629         res  = dest->as_double_reg();
1630         switch (code) {
1631           case lir_add: __ fadd(res, lreg, rreg); break;
1632           case lir_sub: __ fsub(res, lreg, rreg); break;
1633           case lir_mul: __ fmul(res, lreg, rreg); break;
1634           case lir_div: __ fdiv(res, lreg, rreg); break;
1635           default: ShouldNotReachHere();
1636         }
1637       }
1638 
1639     } else if (dest->is_double_cpu()) {
1640 
1641       Register dst_lo = dest->as_register_lo();
1642       Register op1_lo = left->as_pointer_register();
1643       Register op2_lo = right->as_pointer_register();
1644 
1645       switch (code) {
1646         case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1647         case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1648         case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1649         default: ShouldNotReachHere();
1650       }
1651     } else {
1652       assert (right->is_single_cpu(), "Just Checking");
1653 
1654       Register lreg = left->as_register();
1655       Register res  = dest->as_register();
1656       Register rreg = right->as_register();
1657       switch (code) {
1658         case lir_add:  __ add  (res, lreg, rreg); break;
1659         case lir_sub:  __ sub  (res, lreg, rreg); break;
1660         case lir_mul:  __ mullw(res, lreg, rreg); break;
1661         default: ShouldNotReachHere();
1662       }
1663     }
1664   } else {
1665     assert (right->is_constant(), "must be constant");
1666 
1667     if (dest->is_single_cpu()) {
1668       Register lreg = left->as_register();
1669       Register res  = dest->as_register();
1670       int    simm16 = right->as_constant_ptr()->as_jint();
1671 
1672       switch (code) {
1673         case lir_sub:  assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1674                        simm16 = -simm16;
1675         case lir_add:  if (res == lreg && simm16 == 0) break;
1676                        __ addi(res, lreg, simm16); break;
1677         case lir_mul:  if (res == lreg && simm16 == 1) break;
1678                        __ mulli(res, lreg, simm16); break;
1679         default: ShouldNotReachHere();
1680       }
1681     } else {
1682       Register lreg = left->as_pointer_register();
1683       Register res  = dest->as_register_lo();
1684       long con = right->as_constant_ptr()->as_jlong();
1685       assert(Assembler::is_simm16(con), "must be simm16");
1686 
1687       switch (code) {
1688         case lir_sub:  assert(Assembler::is_simm16(-con), "cannot encode");  // see do_ArithmeticOp_Long
1689                        con = -con;
1690         case lir_add:  if (res == lreg && con == 0) break;
1691                        __ addi(res, lreg, (int)con); break;
1692         case lir_mul:  if (res == lreg && con == 1) break;
1693                        __ mulli(res, lreg, (int)con); break;
1694         default: ShouldNotReachHere();
1695       }
1696     }
1697   }
1698 }
1699 
1700 
1701 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1702   switch (code) {
1703     case lir_sqrt: {
1704       __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1705       break;
1706     }
1707     case lir_abs: {
1708       __ fabs(dest->as_double_reg(), value->as_double_reg());
1709       break;
1710     }
1711     default: {
1712       ShouldNotReachHere();
1713       break;
1714     }
1715   }
1716 }
1717 
1718 
1719 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1720   if (right->is_constant()) { // see do_LogicOp
1721     long uimm;
1722     Register d, l;
1723     if (dest->is_single_cpu()) {
1724       uimm = right->as_constant_ptr()->as_jint();
1725       d = dest->as_register();
1726       l = left->as_register();
1727     } else {
1728       uimm = right->as_constant_ptr()->as_jlong();
1729       d = dest->as_register_lo();
1730       l = left->as_register_lo();
1731     }
1732     long uimms  = (unsigned long)uimm >> 16,
1733          uimmss = (unsigned long)uimm >> 32;
1734 
1735     switch (code) {
1736       case lir_logic_and:
1737         if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1738           __ andi(d, l, uimm); // special cases
1739         } else if (uimms != 0) { __ andis_(d, l, uimms); }
1740         else { __ andi_(d, l, uimm); }
1741         break;
1742 
1743       case lir_logic_or:
1744         if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1745         else { __ ori(d, l, uimm); }
1746         break;
1747 
1748       case lir_logic_xor:
1749         if (uimm == -1) { __ nand(d, l, l); } // special case
1750         else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1751         else { __ xori(d, l, uimm); }
1752         break;
1753 
1754       default: ShouldNotReachHere();
1755     }
1756   } else {
1757     assert(right->is_register(), "right should be in register");
1758 
1759     if (dest->is_single_cpu()) {
1760       switch (code) {
1761         case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1762         case lir_logic_or:  __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1763         case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1764         default: ShouldNotReachHere();
1765       }
1766     } else {
1767       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1768                                                                         left->as_register_lo();
1769       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1770                                                                           right->as_register_lo();
1771 
1772       switch (code) {
1773         case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1774         case lir_logic_or:  __ orr (dest->as_register_lo(), l, r); break;
1775         case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1776         default: ShouldNotReachHere();
1777       }
1778     }
1779   }
1780 }
1781 
1782 
1783 int LIR_Assembler::shift_amount(BasicType t) {
1784   int elem_size = type2aelembytes(t);
1785   switch (elem_size) {
1786     case 1 : return 0;
1787     case 2 : return 1;
1788     case 4 : return 2;
1789     case 8 : return 3;
1790   }
1791   ShouldNotReachHere();
1792   return -1;
1793 }
1794 
1795 
1796 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1797   info->add_register_oop(exceptionOop);
1798 
1799   // Reuse the debug info from the safepoint poll for the throw op itself.
1800   address pc_for_athrow = __ pc();
1801   int pc_for_athrow_offset = __ offset();
1802   //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1803   //__ relocate(rspec);
1804   //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1805   __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1806   add_call_info(pc_for_athrow_offset, info); // for exception handler
1807 
1808   address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1809                                                                    : Runtime1::handle_exception_nofpu_id);
1810   //__ load_const_optimized(R0, stub);
1811   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1812   __ mtctr(R0);
1813   __ bctr();
1814 }
1815 
1816 
1817 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1818   // Note: Not used with EnableDebuggingOnDemand.
1819   assert(exceptionOop->as_register() == R3, "should match");
1820   __ b(_unwind_handler_entry);
1821 }
1822 
1823 
1824 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1825   Register src = op->src()->as_register();
1826   Register dst = op->dst()->as_register();
1827   Register src_pos = op->src_pos()->as_register();
1828   Register dst_pos = op->dst_pos()->as_register();
1829   Register length  = op->length()->as_register();
1830   Register tmp = op->tmp()->as_register();
1831   Register tmp2 = R0;
1832 
1833   int flags = op->flags();
1834   ciArrayKlass* default_type = op->expected_type();
1835   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1836   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1837 
1838   // Set up the arraycopy stub information.
1839   ArrayCopyStub* stub = op->stub();
1840   const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1841 
1842   // Always do stub if no type information is available. It's ok if
1843   // the known type isn't loaded since the code sanity checks
1844   // in debug mode and the type isn't required when we know the exact type
1845   // also check that the type is an array type.
1846   if (op->expected_type() == NULL) {
1847     assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1848            length->is_nonvolatile(), "must preserve");
1849     address copyfunc_addr = StubRoutines::generic_arraycopy();
1850     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1851 
1852     // 3 parms are int. Convert to long.
1853     __ mr(R3_ARG1, src);
1854     __ extsw(R4_ARG2, src_pos);
1855     __ mr(R5_ARG3, dst);
1856     __ extsw(R6_ARG4, dst_pos);
1857     __ extsw(R7_ARG5, length);
1858 
1859 #ifndef PRODUCT
1860     if (PrintC1Statistics) {
1861       address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1862       int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1863       __ lwz(R11_scratch1, simm16_offs, tmp);
1864       __ addi(R11_scratch1, R11_scratch1, 1);
1865       __ stw(R11_scratch1, simm16_offs, tmp);
1866     }
1867 #endif
1868     __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1869 
1870     __ nand(tmp, R3_RET, R3_RET);
1871     __ subf(length, tmp, length);
1872     __ add(src_pos, tmp, src_pos);
1873     __ add(dst_pos, tmp, dst_pos);
1874 
1875     __ cmpwi(CCR0, R3_RET, 0);
1876     __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1877     __ bind(*stub->continuation());
1878     return;
1879   }
1880 
1881   assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1882   Label cont, slow, copyfunc;
1883 
1884   bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1885                                         LIR_OpArrayCopy::dst_null_check |
1886                                         LIR_OpArrayCopy::src_pos_positive_check |
1887                                         LIR_OpArrayCopy::dst_pos_positive_check |
1888                                         LIR_OpArrayCopy::length_positive_check);
1889 
1890   // Use only one conditional branch for simple checks.
1891   if (simple_check_flag_set) {
1892     ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1893 
1894     // Make sure src and dst are non-null.
1895     if (flags & LIR_OpArrayCopy::src_null_check) {
1896       __ cmpdi(combined_check, src, 0);
1897       tmp_check = CCR0;
1898     }
1899 
1900     if (flags & LIR_OpArrayCopy::dst_null_check) {
1901       __ cmpdi(tmp_check, dst, 0);
1902       if (tmp_check != combined_check) {
1903         __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1904       }
1905       tmp_check = CCR0;
1906     }
1907 
1908     // Clear combined_check.eq if not already used.
1909     if (tmp_check == combined_check) {
1910       __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1911       tmp_check = CCR0;
1912     }
1913 
1914     if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1915       // Test src_pos register.
1916       __ cmpwi(tmp_check, src_pos, 0);
1917       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1918     }
1919 
1920     if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1921       // Test dst_pos register.
1922       __ cmpwi(tmp_check, dst_pos, 0);
1923       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1924     }
1925 
1926     if (flags & LIR_OpArrayCopy::length_positive_check) {
1927       // Make sure length isn't negative.
1928       __ cmpwi(tmp_check, length, 0);
1929       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1930     }
1931 
1932     __ beq(combined_check, slow);
1933   }
1934 
1935   // If the compiler was not able to prove that exact type of the source or the destination
1936   // of the arraycopy is an array type, check at runtime if the source or the destination is
1937   // an instance type.
1938   if (flags & LIR_OpArrayCopy::type_check) {
1939     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1940       __ load_klass(tmp, dst);
1941       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1942       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1943       __ bge(CCR0, slow);
1944     }
1945 
1946     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1947       __ load_klass(tmp, src);
1948       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1949       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1950       __ bge(CCR0, slow);
1951     }
1952   }
1953 
1954   // Higher 32bits must be null.
1955   __ extsw(length, length);
1956 
1957   __ extsw(src_pos, src_pos);
1958   if (flags & LIR_OpArrayCopy::src_range_check) {
1959     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1960     __ add(tmp, length, src_pos);
1961     __ cmpld(CCR0, tmp2, tmp);
1962     __ ble(CCR0, slow);
1963   }
1964 
1965   __ extsw(dst_pos, dst_pos);
1966   if (flags & LIR_OpArrayCopy::dst_range_check) {
1967     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1968     __ add(tmp, length, dst_pos);
1969     __ cmpld(CCR0, tmp2, tmp);
1970     __ ble(CCR0, slow);
1971   }
1972 
1973   int shift = shift_amount(basic_type);
1974 
1975   if (!(flags & LIR_OpArrayCopy::type_check)) {
1976     __ b(cont);
1977   } else {
1978     // We don't know the array types are compatible.
1979     if (basic_type != T_OBJECT) {
1980       // Simple test for basic type arrays.
1981       if (UseCompressedClassPointers) {
1982         // We don't need decode because we just need to compare.
1983         __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1984         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1985         __ cmpw(CCR0, tmp, tmp2);
1986       } else {
1987         __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1988         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1989         __ cmpd(CCR0, tmp, tmp2);
1990       }
1991       __ beq(CCR0, cont);
1992     } else {
1993       // For object arrays, if src is a sub class of dst then we can
1994       // safely do the copy.
1995       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1996 
1997       const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1998       assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1999 
2000       __ load_klass(sub_klass, src);
2001       __ load_klass(super_klass, dst);
2002 
2003       __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2004                                        &cont, copyfunc_addr != NULL ? &copyfunc : &slow, NULL);
2005 
2006       address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2007       //__ load_const_optimized(tmp, slow_stc, tmp2);
2008       __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2009       __ mtctr(tmp);
2010       __ bctrl(); // sets CR0
2011       __ beq(CCR0, cont);
2012 
2013       if (copyfunc_addr != NULL) { // Use stub if available.
2014         __ bind(copyfunc);
2015         // Src is not a sub class of dst so we have to do a
2016         // per-element check.
2017         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2018         if ((flags & mask) != mask) {
2019           assert(flags & mask, "one of the two should be known to be an object array");
2020 
2021           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2022             __ load_klass(tmp, src);
2023           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2024             __ load_klass(tmp, dst);
2025           }
2026 
2027           __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2028 
2029           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2030           __ load_const_optimized(tmp, objArray_lh);
2031           __ cmpw(CCR0, tmp, tmp2);
2032           __ bne(CCR0, slow);
2033         }
2034 
2035         Register src_ptr = R3_ARG1;
2036         Register dst_ptr = R4_ARG2;
2037         Register len     = R5_ARG3;
2038         Register chk_off = R6_ARG4;
2039         Register super_k = R7_ARG5;
2040 
2041         __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2042         __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2043         if (shift == 0) {
2044           __ add(src_ptr, src_pos, src_ptr);
2045           __ add(dst_ptr, dst_pos, dst_ptr);
2046         } else {
2047           __ sldi(tmp, src_pos, shift);
2048           __ sldi(tmp2, dst_pos, shift);
2049           __ add(src_ptr, tmp, src_ptr);
2050           __ add(dst_ptr, tmp2, dst_ptr);
2051         }
2052 
2053         __ load_klass(tmp, dst);
2054         __ mr(len, length);
2055 
2056         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2057         __ ld(super_k, ek_offset, tmp);
2058 
2059         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2060         __ lwz(chk_off, sco_offset, super_k);
2061 
2062         __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2063 
2064 #ifndef PRODUCT
2065         if (PrintC1Statistics) {
2066           Label failed;
2067           __ cmpwi(CCR0, R3_RET, 0);
2068           __ bne(CCR0, failed);
2069           address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2070           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2071           __ lwz(R11_scratch1, simm16_offs, tmp);
2072           __ addi(R11_scratch1, R11_scratch1, 1);
2073           __ stw(R11_scratch1, simm16_offs, tmp);
2074           __ bind(failed);
2075         }
2076 #endif
2077 
2078         __ nand(tmp, R3_RET, R3_RET);
2079         __ cmpwi(CCR0, R3_RET, 0);
2080         __ beq(CCR0, *stub->continuation());
2081 
2082 #ifndef PRODUCT
2083         if (PrintC1Statistics) {
2084           address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2085           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2086           __ lwz(R11_scratch1, simm16_offs, tmp);
2087           __ addi(R11_scratch1, R11_scratch1, 1);
2088           __ stw(R11_scratch1, simm16_offs, tmp);
2089         }
2090 #endif
2091 
2092         __ subf(length, tmp, length);
2093         __ add(src_pos, tmp, src_pos);
2094         __ add(dst_pos, tmp, dst_pos);
2095       }
2096     }
2097   }
2098   __ bind(slow);
2099   __ b(*stub->entry());
2100   __ bind(cont);
2101 
2102 #ifdef ASSERT
2103   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2104     // Sanity check the known type with the incoming class. For the
2105     // primitive case the types must match exactly with src.klass and
2106     // dst.klass each exactly matching the default type. For the
2107     // object array case, if no type check is needed then either the
2108     // dst type is exactly the expected type and the src type is a
2109     // subtype which we can't check or src is the same array as dst
2110     // but not necessarily exactly of type default_type.
2111     Label known_ok, halt;
2112     metadata2reg(op->expected_type()->constant_encoding(), tmp);
2113     if (UseCompressedClassPointers) {
2114       // Tmp holds the default type. It currently comes uncompressed after the
2115       // load of a constant, so encode it.
2116       __ encode_klass_not_null(tmp);
2117       // Load the raw value of the dst klass, since we will be comparing
2118       // uncompressed values directly.
2119       __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2120       __ cmpw(CCR0, tmp, tmp2);
2121       if (basic_type != T_OBJECT) {
2122         __ bne(CCR0, halt);
2123         // Load the raw value of the src klass.
2124         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2125         __ cmpw(CCR0, tmp, tmp2);
2126         __ beq(CCR0, known_ok);
2127       } else {
2128         __ beq(CCR0, known_ok);
2129         __ cmpw(CCR0, src, dst);
2130         __ beq(CCR0, known_ok);
2131       }
2132     } else {
2133       __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2134       __ cmpd(CCR0, tmp, tmp2);
2135       if (basic_type != T_OBJECT) {
2136         __ bne(CCR0, halt);
2137         // Load the raw value of the src klass.
2138         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2139         __ cmpd(CCR0, tmp, tmp2);
2140         __ beq(CCR0, known_ok);
2141       } else {
2142         __ beq(CCR0, known_ok);
2143         __ cmpd(CCR0, src, dst);
2144         __ beq(CCR0, known_ok);
2145       }
2146     }
2147     __ bind(halt);
2148     __ stop("incorrect type information in arraycopy");
2149     __ bind(known_ok);
2150   }
2151 #endif
2152 
2153 #ifndef PRODUCT
2154   if (PrintC1Statistics) {
2155     address counter = Runtime1::arraycopy_count_address(basic_type);
2156     int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2157     __ lwz(R11_scratch1, simm16_offs, tmp);
2158     __ addi(R11_scratch1, R11_scratch1, 1);
2159     __ stw(R11_scratch1, simm16_offs, tmp);
2160   }
2161 #endif
2162 
2163   Register src_ptr = R3_ARG1;
2164   Register dst_ptr = R4_ARG2;
2165   Register len     = R5_ARG3;
2166 
2167   __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2168   __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2169   if (shift == 0) {
2170     __ add(src_ptr, src_pos, src_ptr);
2171     __ add(dst_ptr, dst_pos, dst_ptr);
2172   } else {
2173     __ sldi(tmp, src_pos, shift);
2174     __ sldi(tmp2, dst_pos, shift);
2175     __ add(src_ptr, tmp, src_ptr);
2176     __ add(dst_ptr, tmp2, dst_ptr);
2177   }
2178 
2179   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2180   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2181   const char *name;
2182   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2183 
2184   // Arraycopy stubs takes a length in number of elements, so don't scale it.
2185   __ mr(len, length);
2186   __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2187 
2188   __ bind(*stub->continuation());
2189 }
2190 
2191 
2192 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2193   if (dest->is_single_cpu()) {
2194     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2195 #ifdef _LP64
2196     if (left->type() == T_OBJECT) {
2197       switch (code) {
2198         case lir_shl:  __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2199         case lir_shr:  __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2200         case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2201         default: ShouldNotReachHere();
2202       }
2203     } else
2204 #endif
2205       switch (code) {
2206         case lir_shl:  __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2207         case lir_shr:  __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2208         case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2209         default: ShouldNotReachHere();
2210       }
2211   } else {
2212     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2213     switch (code) {
2214       case lir_shl:  __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2215       case lir_shr:  __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2216       case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2217       default: ShouldNotReachHere();
2218     }
2219   }
2220 }
2221 
2222 
2223 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2224 #ifdef _LP64
2225   if (left->type() == T_OBJECT) {
2226     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2227     if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2228     else {
2229       switch (code) {
2230         case lir_shl:  __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2231         case lir_shr:  __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2232         case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2233         default: ShouldNotReachHere();
2234       }
2235     }
2236     return;
2237   }
2238 #endif
2239 
2240   if (dest->is_single_cpu()) {
2241     count = count & 0x1F; // Java spec
2242     if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2243     else {
2244       switch (code) {
2245         case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2246         case lir_shr:  __ srawi(dest->as_register(), left->as_register(), count); break;
2247         case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2248         default: ShouldNotReachHere();
2249       }
2250     }
2251   } else if (dest->is_double_cpu()) {
2252     count = count & 63; // Java spec
2253     if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2254     else {
2255       switch (code) {
2256         case lir_shl:  __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2257         case lir_shr:  __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2258         case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2259         default: ShouldNotReachHere();
2260       }
2261     }
2262   } else {
2263     ShouldNotReachHere();
2264   }
2265 }
2266 
2267 
2268 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2269   if (op->init_check()) {
2270     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2271       explicit_null_check(op->klass()->as_register(), op->stub()->info());
2272     } else {
2273       add_debug_info_for_null_check_here(op->stub()->info());
2274     }
2275     __ lbz(op->tmp1()->as_register(),
2276            in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2277     __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2278     __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2279   }
2280   __ allocate_object(op->obj()->as_register(),
2281                      op->tmp1()->as_register(),
2282                      op->tmp2()->as_register(),
2283                      op->tmp3()->as_register(),
2284                      op->header_size(),
2285                      op->object_size(),
2286                      op->klass()->as_register(),
2287                      *op->stub()->entry());
2288 
2289   __ bind(*op->stub()->continuation());
2290   __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2291 }
2292 
2293 
2294 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2295   LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2296   if (UseSlowPath ||
2297       (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2298       (!UseFastNewTypeArray   && (!is_reference_type(op->type())))) {
2299     __ b(*op->stub()->entry());
2300   } else {
2301     __ allocate_array(op->obj()->as_register(),
2302                       op->len()->as_register(),
2303                       op->tmp1()->as_register(),
2304                       op->tmp2()->as_register(),
2305                       op->tmp3()->as_register(),
2306                       arrayOopDesc::header_size(op->type()),
2307                       type2aelembytes(op->type()),
2308                       op->klass()->as_register(),
2309                       *op->stub()->entry());
2310   }
2311   __ bind(*op->stub()->continuation());
2312 }
2313 
2314 
2315 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2316                                         ciMethodData *md, ciProfileData *data,
2317                                         Register recv, Register tmp1, Label* update_done) {
2318   uint i;
2319   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2320     Label next_test;
2321     // See if the receiver is receiver[n].
2322     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2323     __ verify_klass_ptr(tmp1);
2324     __ cmpd(CCR0, recv, tmp1);
2325     __ bne(CCR0, next_test);
2326 
2327     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2328     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2329     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2330     __ b(*update_done);
2331 
2332     __ bind(next_test);
2333   }
2334 
2335   // Didn't find receiver; find next empty slot and fill it in.
2336   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2337     Label next_test;
2338     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2339     __ cmpdi(CCR0, tmp1, 0);
2340     __ bne(CCR0, next_test);
2341     __ li(tmp1, DataLayout::counter_increment);
2342     __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2343     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2344     __ b(*update_done);
2345 
2346     __ bind(next_test);
2347   }
2348 }
2349 
2350 
2351 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2352                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2353   md = method->method_data_or_null();
2354   assert(md != NULL, "Sanity");
2355   data = md->bci_to_data(bci);
2356   assert(data != NULL,       "need data for checkcast");
2357   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2358   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2359     // The offset is large so bias the mdo by the base of the slot so
2360     // that the ld can use simm16s to reference the slots of the data.
2361     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2362   }
2363 }
2364 
2365 
2366 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2367   const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2368   Register k_RInfo = op->tmp1()->as_register();
2369   Register klass_RInfo = op->tmp2()->as_register();
2370   Register Rtmp1 = op->tmp3()->as_register();
2371   Register dst = op->result_opr()->as_register();
2372   ciKlass* k = op->klass();
2373   bool should_profile = op->should_profile();
2374   // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2375   bool reg_conflict = false;
2376   if (obj == k_RInfo) {
2377     k_RInfo = dst;
2378     reg_conflict = true;
2379   } else if (obj == klass_RInfo) {
2380     klass_RInfo = dst;
2381     reg_conflict = true;
2382   } else if (obj == Rtmp1) {
2383     Rtmp1 = dst;
2384     reg_conflict = true;
2385   }
2386   assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2387 
2388   __ cmpdi(CCR0, obj, 0);
2389 
2390   ciMethodData* md = NULL;
2391   ciProfileData* data = NULL;
2392   int mdo_offset_bias = 0;
2393   if (should_profile) {
2394     ciMethod* method = op->profiled_method();
2395     assert(method != NULL, "Should have method");
2396     setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2397 
2398     Register mdo      = k_RInfo;
2399     Register data_val = Rtmp1;
2400     Label not_null;
2401     __ bne(CCR0, not_null);
2402     metadata2reg(md->constant_encoding(), mdo);
2403     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2404     __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2405     __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2406     __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2407     __ b(*obj_is_null);
2408     __ bind(not_null);
2409   } else {
2410     __ beq(CCR0, *obj_is_null);
2411   }
2412 
2413   // get object class
2414   __ load_klass(klass_RInfo, obj);
2415 
2416   if (k->is_loaded()) {
2417     metadata2reg(k->constant_encoding(), k_RInfo);
2418   } else {
2419     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2420   }
2421 
2422   Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2423   Label *failure_target = should_profile ? &profile_cast_failure : failure;
2424   Label *success_target = should_profile ? &profile_cast_success : success;
2425 
2426   if (op->fast_check()) {
2427     assert_different_registers(klass_RInfo, k_RInfo);
2428     __ cmpd(CCR0, k_RInfo, klass_RInfo);
2429     if (should_profile) {
2430       __ bne(CCR0, *failure_target);
2431       // Fall through to success case.
2432     } else {
2433       __ beq(CCR0, *success);
2434       // Fall through to failure case.
2435     }
2436   } else {
2437     bool need_slow_path = true;
2438     if (k->is_loaded()) {
2439       if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2440         need_slow_path = false;
2441       }
2442       // Perform the fast part of the checking logic.
2443       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2444                                        failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2445     } else {
2446       // Perform the fast part of the checking logic.
2447       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2448     }
2449     if (!need_slow_path) {
2450       if (!should_profile) { __ b(*success); }
2451     } else {
2452       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2453       address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2454       // Stub needs fixed registers (tmp1-3).
2455       Register original_k_RInfo = op->tmp1()->as_register();
2456       Register original_klass_RInfo = op->tmp2()->as_register();
2457       Register original_Rtmp1 = op->tmp3()->as_register();
2458       bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2459       bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2460       if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2461       __ mr_if_needed(original_k_RInfo, k_RInfo);
2462       __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2463       if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2464       //__ load_const_optimized(original_Rtmp1, entry, R0);
2465       __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2466       __ mtctr(original_Rtmp1);
2467       __ bctrl(); // sets CR0
2468       if (keep_obj_alive) {
2469         if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2470         __ mr(obj, dst);
2471       }
2472       if (should_profile) {
2473         __ bne(CCR0, *failure_target);
2474         if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2475         // Fall through to success case.
2476       } else {
2477         __ beq(CCR0, *success);
2478         // Fall through to failure case.
2479       }
2480     }
2481   }
2482 
2483   if (should_profile) {
2484     Register mdo = k_RInfo, recv = klass_RInfo;
2485     assert_different_registers(mdo, recv, Rtmp1);
2486     __ bind(profile_cast_success);
2487     metadata2reg(md->constant_encoding(), mdo);
2488     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2489     type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2490     __ b(*success);
2491 
2492     // Cast failure case.
2493     __ bind(profile_cast_failure);
2494     metadata2reg(md->constant_encoding(), mdo);
2495     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2496     __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2497     __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2498     __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2499   }
2500 
2501   __ bind(*failure);
2502 }
2503 
2504 
2505 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2506   LIR_Code code = op->code();
2507   if (code == lir_store_check) {
2508     Register value = op->object()->as_register();
2509     Register array = op->array()->as_register();
2510     Register k_RInfo = op->tmp1()->as_register();
2511     Register klass_RInfo = op->tmp2()->as_register();
2512     Register Rtmp1 = op->tmp3()->as_register();
2513     bool should_profile = op->should_profile();
2514 
2515     __ verify_oop(value, FILE_AND_LINE);
2516     CodeStub* stub = op->stub();
2517     // Check if it needs to be profiled.
2518     ciMethodData* md = NULL;
2519     ciProfileData* data = NULL;
2520     int mdo_offset_bias = 0;
2521     if (should_profile) {
2522       ciMethod* method = op->profiled_method();
2523       assert(method != NULL, "Should have method");
2524       setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2525     }
2526     Label profile_cast_success, failure, done;
2527     Label *success_target = should_profile ? &profile_cast_success : &done;
2528 
2529     __ cmpdi(CCR0, value, 0);
2530     if (should_profile) {
2531       Label not_null;
2532       __ bne(CCR0, not_null);
2533       Register mdo      = k_RInfo;
2534       Register data_val = Rtmp1;
2535       metadata2reg(md->constant_encoding(), mdo);
2536       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2537       __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2538       __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2539       __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2540       __ b(done);
2541       __ bind(not_null);
2542     } else {
2543       __ beq(CCR0, done);
2544     }
2545     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2546       explicit_null_check(array, op->info_for_exception());
2547     } else {
2548       add_debug_info_for_null_check_here(op->info_for_exception());
2549     }
2550     __ load_klass(k_RInfo, array);
2551     __ load_klass(klass_RInfo, value);
2552 
2553     // Get instance klass.
2554     __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2555     // Perform the fast part of the checking logic.
2556     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2557 
2558     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2559     const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2560     //__ load_const_optimized(R0, slow_path);
2561     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2562     __ mtctr(R0);
2563     __ bctrl(); // sets CR0
2564     if (!should_profile) {
2565       __ beq(CCR0, done);
2566       __ bind(failure);
2567     } else {
2568       __ bne(CCR0, failure);
2569       // Fall through to the success case.
2570 
2571       Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2572       assert_different_registers(value, mdo, recv, tmp1);
2573       __ bind(profile_cast_success);
2574       metadata2reg(md->constant_encoding(), mdo);
2575       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2576       __ load_klass(recv, value);
2577       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2578       __ b(done);
2579 
2580       // Cast failure case.
2581       __ bind(failure);
2582       metadata2reg(md->constant_encoding(), mdo);
2583       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2584       Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2585       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2586       __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2587       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2588     }
2589     __ b(*stub->entry());
2590     __ bind(done);
2591 
2592   } else if (code == lir_checkcast) {
2593     Label success, failure;
2594     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2595     __ b(*op->stub()->entry());
2596     __ align(32, 12);
2597     __ bind(success);
2598     __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2599   } else if (code == lir_instanceof) {
2600     Register dst = op->result_opr()->as_register();
2601     Label success, failure, done;
2602     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2603     __ li(dst, 0);
2604     __ b(done);
2605     __ align(32, 12);
2606     __ bind(success);
2607     __ li(dst, 1);
2608     __ bind(done);
2609   } else {
2610     ShouldNotReachHere();
2611   }
2612 }
2613 
2614 
2615 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2616   Register addr = op->addr()->as_pointer_register();
2617   Register cmp_value = noreg, new_value = noreg;
2618   bool is_64bit = false;
2619 
2620   if (op->code() == lir_cas_long) {
2621     cmp_value = op->cmp_value()->as_register_lo();
2622     new_value = op->new_value()->as_register_lo();
2623     is_64bit = true;
2624   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2625     cmp_value = op->cmp_value()->as_register();
2626     new_value = op->new_value()->as_register();
2627     if (op->code() == lir_cas_obj) {
2628       if (UseCompressedOops) {
2629         Register t1 = op->tmp1()->as_register();
2630         Register t2 = op->tmp2()->as_register();
2631         cmp_value = __ encode_heap_oop(t1, cmp_value);
2632         new_value = __ encode_heap_oop(t2, new_value);
2633       } else {
2634         is_64bit = true;
2635       }
2636     }
2637   } else {
2638     Unimplemented();
2639   }
2640 
2641   if (is_64bit) {
2642     __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2643                 MacroAssembler::MemBarNone,
2644                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2645                 noreg, NULL, /*check without ldarx first*/true);
2646   } else {
2647     __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2648                 MacroAssembler::MemBarNone,
2649                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2650                 noreg, /*check without ldarx first*/true);
2651   }
2652 
2653   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2654     __ isync();
2655   } else {
2656     __ sync();
2657   }
2658 }
2659 
2660 void LIR_Assembler::breakpoint() {
2661   __ illtrap();
2662 }
2663 
2664 
2665 void LIR_Assembler::push(LIR_Opr opr) {
2666   Unimplemented();
2667 }
2668 
2669 void LIR_Assembler::pop(LIR_Opr opr) {
2670   Unimplemented();
2671 }
2672 
2673 
2674 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2675   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2676   Register dst = dst_opr->as_register();
2677   Register reg = mon_addr.base();
2678   int offset = mon_addr.disp();
2679   // Compute pointer to BasicLock.
2680   __ add_const_optimized(dst, reg, offset);
2681 }
2682 
2683 
2684 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2685   Register obj = op->obj_opr()->as_register();
2686   Register hdr = op->hdr_opr()->as_register();
2687   Register lock = op->lock_opr()->as_register();
2688 
2689   // Obj may not be an oop.
2690   if (op->code() == lir_lock) {
2691     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2692     if (UseFastLocking) {
2693       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2694       // Add debug info for NullPointerException only if one is possible.
2695       if (op->info() != NULL) {
2696         if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2697           explicit_null_check(obj, op->info());
2698         } else {
2699           add_debug_info_for_null_check_here(op->info());
2700         }
2701       }
2702       __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2703     } else {
2704       // always do slow locking
2705       // note: The slow locking code could be inlined here, however if we use
2706       //       slow locking, speed doesn't matter anyway and this solution is
2707       //       simpler and requires less duplicated code - additionally, the
2708       //       slow locking code is the same in either case which simplifies
2709       //       debugging.
2710       __ b(*op->stub()->entry());
2711     }
2712   } else {
2713     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2714     if (UseFastLocking) {
2715       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2716       __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2717     } else {
2718       // always do slow unlocking
2719       // note: The slow unlocking code could be inlined here, however if we use
2720       //       slow unlocking, speed doesn't matter anyway and this solution is
2721       //       simpler and requires less duplicated code - additionally, the
2722       //       slow unlocking code is the same in either case which simplifies
2723       //       debugging.
2724       __ b(*op->stub()->entry());
2725     }
2726   }
2727   __ bind(*op->stub()->continuation());
2728 }
2729 
2730 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2731   Register obj = op->obj()->as_pointer_register();
2732   Register result = op->result_opr()->as_pointer_register();
2733 
2734   CodeEmitInfo* info = op->info();
2735   if (info != NULL) {
2736     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2737       explicit_null_check(obj, info);
2738     } else {
2739       add_debug_info_for_null_check_here(info);
2740     }
2741   }
2742 
2743   if (UseCompressedClassPointers) {
2744     __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2745     __ decode_klass_not_null(result);
2746   } else {
2747     __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2748   }
2749 }
2750 
2751 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2752   ciMethod* method = op->profiled_method();
2753   int bci          = op->profiled_bci();
2754   ciMethod* callee = op->profiled_callee();
2755 
2756   // Update counter for all call types.
2757   ciMethodData* md = method->method_data_or_null();
2758   assert(md != NULL, "Sanity");
2759   ciProfileData* data = md->bci_to_data(bci);
2760   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2761   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2762   Register mdo = op->mdo()->as_register();
2763 #ifdef _LP64
2764   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2765   Register tmp1 = op->tmp1()->as_register_lo();
2766 #else
2767   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2768   Register tmp1 = op->tmp1()->as_register();
2769 #endif
2770   metadata2reg(md->constant_encoding(), mdo);
2771   int mdo_offset_bias = 0;
2772   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2773                             data->size_in_bytes())) {
2774     // The offset is large so bias the mdo by the base of the slot so
2775     // that the ld can use simm16s to reference the slots of the data.
2776     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2777     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2778   }
2779 
2780   // Perform additional virtual call profiling for invokevirtual and
2781   // invokeinterface bytecodes
2782   if (op->should_profile_receiver_type()) {
2783     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2784     Register recv = op->recv()->as_register();
2785     assert_different_registers(mdo, tmp1, recv);
2786     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2787     ciKlass* known_klass = op->known_holder();
2788     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2789       // We know the type that will be seen at this call site; we can
2790       // statically update the MethodData* rather than needing to do
2791       // dynamic tests on the receiver type.
2792 
2793       // NOTE: we should probably put a lock around this search to
2794       // avoid collisions by concurrent compilations.
2795       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2796       uint i;
2797       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2798         ciKlass* receiver = vc_data->receiver(i);
2799         if (known_klass->equals(receiver)) {
2800           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2801           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2802           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2803           return;
2804         }
2805       }
2806 
2807       // Receiver type not found in profile data; select an empty slot.
2808 
2809       // Note that this is less efficient than it should be because it
2810       // always does a write to the receiver part of the
2811       // VirtualCallData rather than just the first time.
2812       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2813         ciKlass* receiver = vc_data->receiver(i);
2814         if (receiver == NULL) {
2815           metadata2reg(known_klass->constant_encoding(), tmp1);
2816           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2817 
2818           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2819           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2820           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2821           return;
2822         }
2823       }
2824     } else {
2825       __ load_klass(recv, recv);
2826       Label update_done;
2827       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2828       // Receiver did not match any saved receiver and there is no empty row for it.
2829       // Increment total counter to indicate polymorphic case.
2830       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2831       __ addi(tmp1, tmp1, DataLayout::counter_increment);
2832       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2833 
2834       __ bind(update_done);
2835     }
2836   } else {
2837     // Static call
2838     __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2839     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2840     __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2841   }
2842 }
2843 
2844 
2845 void LIR_Assembler::align_backward_branch_target() {
2846   __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2847 }
2848 
2849 
2850 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2851   Unimplemented();
2852 }
2853 
2854 
2855 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2856   // tmp must be unused
2857   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2858   assert(left->is_register(), "can only handle registers");
2859 
2860   if (left->is_single_cpu()) {
2861     __ neg(dest->as_register(), left->as_register());
2862   } else if (left->is_single_fpu()) {
2863     __ fneg(dest->as_float_reg(), left->as_float_reg());
2864   } else if (left->is_double_fpu()) {
2865     __ fneg(dest->as_double_reg(), left->as_double_reg());
2866   } else {
2867     assert (left->is_double_cpu(), "Must be a long");
2868     __ neg(dest->as_register_lo(), left->as_register_lo());
2869   }
2870 }
2871 
2872 
2873 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2874                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2875   // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2876   if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2877       dest == Runtime1::entry_for(Runtime1::new_multi_array_id   )) {
2878     //__ load_const_optimized(R0, dest);
2879     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2880     __ mtctr(R0);
2881     __ bctrl();
2882     assert(info != NULL, "sanity");
2883     add_call_info_here(info);
2884     return;
2885   }
2886 
2887   __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2888   if (info != NULL) {
2889     add_call_info_here(info);
2890   }
2891 }
2892 
2893 
2894 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2895   ShouldNotReachHere(); // Not needed on _LP64.
2896 }
2897 
2898 void LIR_Assembler::membar() {
2899   __ fence();
2900 }
2901 
2902 void LIR_Assembler::membar_acquire() {
2903   __ acquire();
2904 }
2905 
2906 void LIR_Assembler::membar_release() {
2907   __ release();
2908 }
2909 
2910 void LIR_Assembler::membar_loadload() {
2911   __ membar(Assembler::LoadLoad);
2912 }
2913 
2914 void LIR_Assembler::membar_storestore() {
2915   __ membar(Assembler::StoreStore);
2916 }
2917 
2918 void LIR_Assembler::membar_loadstore() {
2919   __ membar(Assembler::LoadStore);
2920 }
2921 
2922 void LIR_Assembler::membar_storeload() {
2923   __ membar(Assembler::StoreLoad);
2924 }
2925 
2926 void LIR_Assembler::on_spin_wait() {
2927   Unimplemented();
2928 }
2929 
2930 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2931   LIR_Address* addr = addr_opr->as_address_ptr();
2932   assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2933 
2934   if (addr->index()->is_illegal()) {
2935     if (patch_code != lir_patch_none) {
2936       PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2937       __ load_const32(R0, 0); // patchable int
2938       __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2939       patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2940     } else {
2941       __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2942     }
2943   } else {
2944     assert(patch_code == lir_patch_none, "Patch code not supported");
2945     assert(addr->disp() == 0, "can't have both: index and disp");
2946     __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2947   }
2948 }
2949 
2950 
2951 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2952   ShouldNotReachHere();
2953 }
2954 
2955 
2956 #ifdef ASSERT
2957 // Emit run-time assertion.
2958 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2959   Unimplemented();
2960 }
2961 #endif
2962 
2963 
2964 void LIR_Assembler::peephole(LIR_List* lir) {
2965   // Optimize instruction pairs before emitting.
2966   LIR_OpList* inst = lir->instructions_list();
2967   for (int i = 1; i < inst->length(); i++) {
2968     LIR_Op* op = inst->at(i);
2969 
2970     // 2 register-register-moves
2971     if (op->code() == lir_move) {
2972       LIR_Opr in2  = ((LIR_Op1*)op)->in_opr(),
2973               res2 = ((LIR_Op1*)op)->result_opr();
2974       if (in2->is_register() && res2->is_register()) {
2975         LIR_Op* prev = inst->at(i - 1);
2976         if (prev && prev->code() == lir_move) {
2977           LIR_Opr in1  = ((LIR_Op1*)prev)->in_opr(),
2978                   res1 = ((LIR_Op1*)prev)->result_opr();
2979           if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2980             inst->remove_at(i);
2981           }
2982         }
2983       }
2984     }
2985 
2986   }
2987   return;
2988 }
2989 
2990 
2991 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2992   const LIR_Address *addr = src->as_address_ptr();
2993   assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2994   const Register Rptr = addr->base()->as_pointer_register(),
2995                  Rtmp = tmp->as_register();
2996   Register Rco = noreg;
2997   if (UseCompressedOops && data->is_oop()) {
2998     Rco = __ encode_heap_oop(Rtmp, data->as_register());
2999   }
3000 
3001   Label Lretry;
3002   __ bind(Lretry);
3003 
3004   if (data->type() == T_INT) {
3005     const Register Rold = dest->as_register(),
3006                    Rsrc = data->as_register();
3007     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3008     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3009     if (code == lir_xadd) {
3010       __ add(Rtmp, Rsrc, Rold);
3011       __ stwcx_(Rtmp, Rptr);
3012     } else {
3013       __ stwcx_(Rsrc, Rptr);
3014     }
3015   } else if (data->is_oop()) {
3016     assert(code == lir_xchg, "xadd for oops");
3017     const Register Rold = dest->as_register();
3018     if (UseCompressedOops) {
3019       assert_different_registers(Rptr, Rold, Rco);
3020       __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3021       __ stwcx_(Rco, Rptr);
3022     } else {
3023       const Register Robj = data->as_register();
3024       assert_different_registers(Rptr, Rold, Robj);
3025       __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3026       __ stdcx_(Robj, Rptr);
3027     }
3028   } else if (data->type() == T_LONG) {
3029     const Register Rold = dest->as_register_lo(),
3030                    Rsrc = data->as_register_lo();
3031     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3032     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3033     if (code == lir_xadd) {
3034       __ add(Rtmp, Rsrc, Rold);
3035       __ stdcx_(Rtmp, Rptr);
3036     } else {
3037       __ stdcx_(Rsrc, Rptr);
3038     }
3039   } else {
3040     ShouldNotReachHere();
3041   }
3042 
3043   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3044     __ bne_predict_not_taken(CCR0, Lretry);
3045   } else {
3046     __ bne(                  CCR0, Lretry);
3047   }
3048 
3049   if (UseCompressedOops && data->is_oop()) {
3050     __ decode_heap_oop(dest->as_register());
3051   }
3052 }
3053 
3054 
3055 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3056   Register obj = op->obj()->as_register();
3057   Register tmp = op->tmp()->as_pointer_register();
3058   LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3059   ciKlass* exact_klass = op->exact_klass();
3060   intptr_t current_klass = op->current_klass();
3061   bool not_null = op->not_null();
3062   bool no_conflict = op->no_conflict();
3063 
3064   Label Lupdate, Ldo_update, Ldone;
3065 
3066   bool do_null = !not_null;
3067   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3068   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3069 
3070   assert(do_null || do_update, "why are we here?");
3071   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3072 
3073   __ verify_oop(obj, FILE_AND_LINE);
3074 
3075   if (do_null) {
3076     if (!TypeEntries::was_null_seen(current_klass)) {
3077       __ cmpdi(CCR0, obj, 0);
3078       __ bne(CCR0, Lupdate);
3079       __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3080       __ ori(R0, R0, TypeEntries::null_seen);
3081       if (do_update) {
3082         __ b(Ldo_update);
3083       } else {
3084         __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3085       }
3086     } else {
3087       if (do_update) {
3088         __ cmpdi(CCR0, obj, 0);
3089         __ beq(CCR0, Ldone);
3090       }
3091     }
3092 #ifdef ASSERT
3093   } else {
3094     __ cmpdi(CCR0, obj, 0);
3095     __ bne(CCR0, Lupdate);
3096     __ stop("unexpect null obj");
3097 #endif
3098   }
3099 
3100   __ bind(Lupdate);
3101   if (do_update) {
3102     Label Lnext;
3103     const Register klass = R29_TOC; // kill and reload
3104     bool klass_reg_used = false;
3105 #ifdef ASSERT
3106     if (exact_klass != NULL) {
3107       Label ok;
3108       klass_reg_used = true;
3109       __ load_klass(klass, obj);
3110       metadata2reg(exact_klass->constant_encoding(), R0);
3111       __ cmpd(CCR0, klass, R0);
3112       __ beq(CCR0, ok);
3113       __ stop("exact klass and actual klass differ");
3114       __ bind(ok);
3115     }
3116 #endif
3117 
3118     if (!no_conflict) {
3119       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3120         klass_reg_used = true;
3121         if (exact_klass != NULL) {
3122           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3123           metadata2reg(exact_klass->constant_encoding(), klass);
3124         } else {
3125           __ load_klass(klass, obj);
3126           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3127         }
3128 
3129         // Like InterpreterMacroAssembler::profile_obj_type
3130         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3131         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3132         __ cmpd(CCR1, R0, klass);
3133         // Klass seen before, nothing to do (regardless of unknown bit).
3134         //beq(CCR1, do_nothing);
3135 
3136         __ andi_(R0, klass, TypeEntries::type_unknown);
3137         // Already unknown. Nothing to do anymore.
3138         //bne(CCR0, do_nothing);
3139         __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3140         __ beq(CCR0, Lnext);
3141 
3142         if (TypeEntries::is_type_none(current_klass)) {
3143           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3144           __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3145           __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3146         }
3147 
3148       } else {
3149         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3150                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3151 
3152         __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3153         __ andi_(R0, tmp, TypeEntries::type_unknown);
3154         // Already unknown. Nothing to do anymore.
3155         __ bne(CCR0, Lnext);
3156       }
3157 
3158       // Different than before. Cannot keep accurate profile.
3159       __ ori(R0, tmp, TypeEntries::type_unknown);
3160     } else {
3161       // There's a single possible klass at this profile point
3162       assert(exact_klass != NULL, "should be");
3163       __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3164 
3165       if (TypeEntries::is_type_none(current_klass)) {
3166         klass_reg_used = true;
3167         metadata2reg(exact_klass->constant_encoding(), klass);
3168 
3169         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3170         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3171         __ cmpd(CCR1, R0, klass);
3172         // Klass seen before, nothing to do (regardless of unknown bit).
3173         __ beq(CCR1, Lnext);
3174 #ifdef ASSERT
3175         {
3176           Label ok;
3177           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3178           __ beq(CCR0, ok); // First time here.
3179 
3180           __ stop("unexpected profiling mismatch");
3181           __ bind(ok);
3182         }
3183 #endif
3184         // First time here. Set profile type.
3185         __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3186       } else {
3187         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3188                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3189 
3190         // Already unknown. Nothing to do anymore.
3191         __ andi_(R0, tmp, TypeEntries::type_unknown);
3192         __ bne(CCR0, Lnext);
3193 
3194         // Different than before. Cannot keep accurate profile.
3195         __ ori(R0, tmp, TypeEntries::type_unknown);
3196       }
3197     }
3198 
3199     __ bind(Ldo_update);
3200     __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3201 
3202     __ bind(Lnext);
3203     if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3204   }
3205   __ bind(Ldone);
3206 }
3207 
3208 
3209 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3210   assert(op->crc()->is_single_cpu(), "crc must be register");
3211   assert(op->val()->is_single_cpu(), "byte value must be register");
3212   assert(op->result_opr()->is_single_cpu(), "result must be register");
3213   Register crc = op->crc()->as_register();
3214   Register val = op->val()->as_register();
3215   Register res = op->result_opr()->as_register();
3216 
3217   assert_different_registers(val, crc, res);
3218 
3219   __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3220   __ kernel_crc32_singleByteReg(crc, val, res, true);
3221   __ mr(res, crc);
3222 }
3223 
3224 #undef __