1 /*
2 * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc/shared/collectedHeap.hpp"
36 #include "memory/universe.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/compressedOops.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/frame.inline.hpp"
41 #include "runtime/safepointMechanism.inline.hpp"
42 #include "runtime/sharedRuntime.hpp"
43 #include "runtime/stubRoutines.hpp"
44 #include "runtime/vm_version.hpp"
45 #include "utilities/powerOfTwo.hpp"
46
47 #define __ _masm->
48
49
50 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
51
52
53 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
54 Unimplemented(); return false; // Currently not used on this platform.
55 }
56
57
58 LIR_Opr LIR_Assembler::receiverOpr() {
59 return FrameMap::R3_oop_opr;
60 }
61
62
63 LIR_Opr LIR_Assembler::osrBufferPointer() {
64 return FrameMap::R3_opr;
65 }
66
67
68 // This specifies the stack pointer decrement needed to build the frame.
69 int LIR_Assembler::initial_frame_size_in_bytes() const {
70 return in_bytes(frame_map()->framesize_in_bytes());
71 }
72
73
74 // Inline cache check: the inline cached class is in inline_cache_reg;
75 // we fetch the class of the receiver and compare it with the cached class.
76 // If they do not match we jump to slow case.
77 int LIR_Assembler::check_icache() {
78 int offset = __ offset();
79 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
80 return offset;
81 }
82
83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
84 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
85
86 Label L_skip_barrier;
87 Register klass = R20;
88
89 metadata2reg(method->holder()->constant_encoding(), klass);
90 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
91
92 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
93 __ mtctr(klass);
94 __ bctr();
95
96 __ bind(L_skip_barrier);
97 }
98
99 void LIR_Assembler::osr_entry() {
100 // On-stack-replacement entry sequence:
101 //
102 // 1. Create a new compiled activation.
103 // 2. Initialize local variables in the compiled activation. The expression
104 // stack must be empty at the osr_bci; it is not initialized.
105 // 3. Jump to the continuation address in compiled code to resume execution.
106
107 // OSR entry point
108 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
109 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
110 ValueStack* entry_state = osr_entry->end()->state();
111 int number_of_locks = entry_state->locks_size();
112
113 // Create a frame for the compiled activation.
114 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
115
116 // OSR buffer is
117 //
118 // locals[nlocals-1..0]
119 // monitors[number_of_locks-1..0]
120 //
121 // Locals is a direct copy of the interpreter frame so in the osr buffer
122 // the first slot in the local array is the last local from the interpreter
123 // and the last slot is local[0] (receiver) from the interpreter.
124 //
125 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
126 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
127 // in the interpreter frame (the method lock if a sync method).
128
129 // Initialize monitors in the compiled activation.
130 // R3: pointer to osr buffer
131 //
132 // All other registers are dead at this point and the locals will be
133 // copied into place by code emitted in the IR.
134
135 Register OSR_buf = osrBufferPointer()->as_register();
136 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
137 int monitor_offset = BytesPerWord * method()->max_locals() +
138 (2 * BytesPerWord) * (number_of_locks - 1);
139 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
140 // the OSR buffer using 2 word entries: first the lock and then
141 // the oop.
142 for (int i = 0; i < number_of_locks; i++) {
143 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
144 #ifdef ASSERT
145 // Verify the interpreter's monitor has a non-null object.
146 {
147 Label L;
148 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
149 __ cmpdi(CCR0, R0, 0);
150 __ bne(CCR0, L);
151 __ stop("locked object is NULL");
152 __ bind(L);
153 }
154 #endif // ASSERT
155 // Copy the lock field into the compiled activation.
156 Address ml = frame_map()->address_for_monitor_lock(i),
157 mo = frame_map()->address_for_monitor_object(i);
158 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
159 __ ld(R0, slot_offset + 0, OSR_buf);
160 __ std(R0, ml.disp(), ml.base());
161 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
162 __ std(R0, mo.disp(), mo.base());
163 }
164 }
165 }
166
167
168 int LIR_Assembler::emit_exception_handler() {
169 // If the last instruction is a call (typically to do a throw which
170 // is coming at the end after block reordering) the return address
171 // must still point into the code area in order to avoid assertion
172 // failures when searching for the corresponding bci => add a nop
173 // (was bug 5/14/1999 - gri).
174 __ nop();
175
176 // Generate code for the exception handler.
177 address handler_base = __ start_a_stub(exception_handler_size());
178
179 if (handler_base == NULL) {
180 // Not enough space left for the handler.
181 bailout("exception handler overflow");
182 return -1;
183 }
184
185 int offset = code_offset();
186 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
187 //__ load_const_optimized(R0, entry_point);
188 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
189 __ mtctr(R0);
190 __ bctr();
191
192 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
193 __ end_a_stub();
194
195 return offset;
196 }
197
198
199 // Emit the code to remove the frame from the stack in the exception
200 // unwind path.
201 int LIR_Assembler::emit_unwind_handler() {
202 _masm->block_comment("Unwind handler");
203
204 int offset = code_offset();
205 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
206 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
207
208 // Fetch the exception from TLS and clear out exception related thread state.
209 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
210 __ li(R0, 0);
211 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
212 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
213
214 __ bind(_unwind_handler_entry);
215 __ verify_not_null_oop(Rexception);
216 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
217
218 // Perform needed unlocking
219 MonitorExitStub* stub = NULL;
220 if (method()->is_synchronized()) {
221 monitor_address(0, FrameMap::R4_opr);
222 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
223 __ unlock_object(R5, R6, R4, *stub->entry());
224 __ bind(*stub->continuation());
225 }
226
227 if (compilation()->env()->dtrace_method_probes()) {
228 Unimplemented();
229 }
230
231 // Dispatch to the unwind logic.
232 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
233 //__ load_const_optimized(R0, unwind_stub);
234 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
235 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
236 __ mtctr(R0);
237 __ bctr();
238
239 // Emit the slow path assembly.
240 if (stub != NULL) {
241 stub->emit_code(this);
242 }
243
244 return offset;
245 }
246
247
248 int LIR_Assembler::emit_deopt_handler() {
249 // If the last instruction is a call (typically to do a throw which
250 // is coming at the end after block reordering) the return address
251 // must still point into the code area in order to avoid assertion
252 // failures when searching for the corresponding bci => add a nop
253 // (was bug 5/14/1999 - gri).
254 __ nop();
255
256 // Generate code for deopt handler.
257 address handler_base = __ start_a_stub(deopt_handler_size());
258
259 if (handler_base == NULL) {
260 // Not enough space left for the handler.
261 bailout("deopt handler overflow");
262 return -1;
263 }
264
265 int offset = code_offset();
266 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
267
268 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
269 __ end_a_stub();
270
271 return offset;
272 }
273
274
275 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
276 if (o == NULL) {
277 __ li(reg, 0);
278 } else {
279 AddressLiteral addrlit = __ constant_oop_address(o);
280 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
281 }
282 }
283
284
285 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
286 // Allocate a new index in table to hold the object once it's been patched.
287 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
288 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
289
290 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
291 __ load_const(reg, addrlit, R0);
292
293 patching_epilog(patch, lir_patch_normal, reg, info);
294 }
295
296
297 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
298 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
299 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
300 }
301
302
303 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
304 // Allocate a new index in table to hold the klass once it's been patched.
305 int index = __ oop_recorder()->allocate_metadata_index(NULL);
306 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
307
308 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
309 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
310 __ load_const(reg, addrlit, R0);
311
312 patching_epilog(patch, lir_patch_normal, reg, info);
313 }
314
315
316 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
317 const bool is_int = result->is_single_cpu();
318 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
319 Register Rdivisor = noreg;
320 Register Rscratch = temp->as_register();
321 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
322 long divisor = -1;
323
324 if (right->is_register()) {
325 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
326 } else {
327 divisor = is_int ? right->as_constant_ptr()->as_jint()
328 : right->as_constant_ptr()->as_jlong();
329 }
330
331 assert(Rdividend != Rscratch, "");
332 assert(Rdivisor != Rscratch, "");
333 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
334
335 if (Rdivisor == noreg) {
336 if (divisor == 1) { // stupid, but can happen
337 if (code == lir_idiv) {
338 __ mr_if_needed(Rresult, Rdividend);
339 } else {
340 __ li(Rresult, 0);
341 }
342
343 } else if (is_power_of_2(divisor)) {
344 // Convert division by a power of two into some shifts and logical operations.
345 int log2 = log2i_exact(divisor);
346
347 // Round towards 0.
348 if (divisor == 2) {
349 if (is_int) {
350 __ srwi(Rscratch, Rdividend, 31);
351 } else {
352 __ srdi(Rscratch, Rdividend, 63);
353 }
354 } else {
355 if (is_int) {
356 __ srawi(Rscratch, Rdividend, 31);
357 } else {
358 __ sradi(Rscratch, Rdividend, 63);
359 }
360 __ clrldi(Rscratch, Rscratch, 64-log2);
361 }
362 __ add(Rscratch, Rdividend, Rscratch);
363
364 if (code == lir_idiv) {
365 if (is_int) {
366 __ srawi(Rresult, Rscratch, log2);
367 } else {
368 __ sradi(Rresult, Rscratch, log2);
369 }
370 } else { // lir_irem
371 __ clrrdi(Rscratch, Rscratch, log2);
372 __ sub(Rresult, Rdividend, Rscratch);
373 }
374
375 } else if (divisor == -1) {
376 if (code == lir_idiv) {
377 __ neg(Rresult, Rdividend);
378 } else {
379 __ li(Rresult, 0);
380 }
381
382 } else {
383 __ load_const_optimized(Rscratch, divisor);
384 if (code == lir_idiv) {
385 if (is_int) {
386 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
387 } else {
388 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
389 }
390 } else {
391 assert(Rscratch != R0, "need both");
392 if (is_int) {
393 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
394 __ mullw(Rscratch, R0, Rscratch);
395 } else {
396 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
397 __ mulld(Rscratch, R0, Rscratch);
398 }
399 __ sub(Rresult, Rdividend, Rscratch);
400 }
401
402 }
403 return;
404 }
405
406 Label regular, done;
407 if (is_int) {
408 __ cmpwi(CCR0, Rdivisor, -1);
409 } else {
410 __ cmpdi(CCR0, Rdivisor, -1);
411 }
412 __ bne(CCR0, regular);
413 if (code == lir_idiv) {
414 __ neg(Rresult, Rdividend);
415 __ b(done);
416 __ bind(regular);
417 if (is_int) {
418 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
419 } else {
420 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
421 }
422 } else { // lir_irem
423 __ li(Rresult, 0);
424 __ b(done);
425 __ bind(regular);
426 if (is_int) {
427 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
428 __ mullw(Rscratch, Rscratch, Rdivisor);
429 } else {
430 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
431 __ mulld(Rscratch, Rscratch, Rdivisor);
432 }
433 __ sub(Rresult, Rdividend, Rscratch);
434 }
435 __ bind(done);
436 }
437
438
439 void LIR_Assembler::emit_op3(LIR_Op3* op) {
440 switch (op->code()) {
441 case lir_idiv:
442 case lir_irem:
443 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
444 op->result_opr(), op->info());
445 break;
446 case lir_fmad:
447 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
448 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
449 break;
450 case lir_fmaf:
451 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
452 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
453 break;
454 default: ShouldNotReachHere(); break;
455 }
456 }
457
458
459 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
460 #ifdef ASSERT
461 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
462 if (op->block() != NULL) _branch_target_blocks.append(op->block());
463 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
464 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
465 #endif
466
467 Label *L = op->label();
468 if (op->cond() == lir_cond_always) {
469 __ b(*L);
470 } else {
471 Label done;
472 bool is_unordered = false;
473 if (op->code() == lir_cond_float_branch) {
474 assert(op->ublock() != NULL, "must have unordered successor");
475 is_unordered = true;
476 } else {
477 assert(op->code() == lir_branch, "just checking");
478 }
479
480 bool positive = false;
481 Assembler::Condition cond = Assembler::equal;
482 switch (op->cond()) {
483 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
484 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
485 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
486 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
487 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
488 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
489 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
490 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
491 default: ShouldNotReachHere();
492 }
493 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
494 int bi = Assembler::bi0(BOOL_RESULT, cond);
495 if (is_unordered) {
496 if (positive) {
497 if (op->ublock() == op->block()) {
498 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
499 }
500 } else {
501 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
502 }
503 }
504 __ bc_far_optimized(bo, bi, *L);
505 __ bind(done);
506 }
507 }
508
509
510 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
511 Bytecodes::Code code = op->bytecode();
512 LIR_Opr src = op->in_opr(),
513 dst = op->result_opr();
514
515 switch(code) {
516 case Bytecodes::_i2l: {
517 __ extsw(dst->as_register_lo(), src->as_register());
518 break;
519 }
520 case Bytecodes::_l2i: {
521 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
522 break;
523 }
524 case Bytecodes::_i2b: {
525 __ extsb(dst->as_register(), src->as_register());
526 break;
527 }
528 case Bytecodes::_i2c: {
529 __ clrldi(dst->as_register(), src->as_register(), 64-16);
530 break;
531 }
532 case Bytecodes::_i2s: {
533 __ extsh(dst->as_register(), src->as_register());
534 break;
535 }
536 case Bytecodes::_i2d:
537 case Bytecodes::_l2d: {
538 bool src_in_memory = !VM_Version::has_mtfprd();
539 FloatRegister rdst = dst->as_double_reg();
540 FloatRegister rsrc;
541 if (src_in_memory) {
542 rsrc = src->as_double_reg(); // via mem
543 } else {
544 // move src to dst register
545 if (code == Bytecodes::_i2d) {
546 __ mtfprwa(rdst, src->as_register());
547 } else {
548 __ mtfprd(rdst, src->as_register_lo());
549 }
550 rsrc = rdst;
551 }
552 __ fcfid(rdst, rsrc);
553 break;
554 }
555 case Bytecodes::_i2f:
556 case Bytecodes::_l2f: {
557 bool src_in_memory = !VM_Version::has_mtfprd();
558 FloatRegister rdst = dst->as_float_reg();
559 FloatRegister rsrc;
560 if (src_in_memory) {
561 rsrc = src->as_double_reg(); // via mem
562 } else {
563 // move src to dst register
564 if (code == Bytecodes::_i2f) {
565 __ mtfprwa(rdst, src->as_register());
566 } else {
567 __ mtfprd(rdst, src->as_register_lo());
568 }
569 rsrc = rdst;
570 }
571 if (VM_Version::has_fcfids()) {
572 __ fcfids(rdst, rsrc);
573 } else {
574 assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
575 __ fcfid(rdst, rsrc);
576 __ frsp(rdst, rdst);
577 }
578 break;
579 }
580 case Bytecodes::_f2d: {
581 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
582 break;
583 }
584 case Bytecodes::_d2f: {
585 __ frsp(dst->as_float_reg(), src->as_double_reg());
586 break;
587 }
588 case Bytecodes::_d2i:
589 case Bytecodes::_f2i: {
590 bool dst_in_memory = !VM_Version::has_mtfprd();
591 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
592 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
593 Label L;
594 // Result must be 0 if value is NaN; test by comparing value to itself.
595 __ fcmpu(CCR0, rsrc, rsrc);
596 if (dst_in_memory) {
597 __ li(R0, 0); // 0 in case of NAN
598 __ std(R0, addr.disp(), addr.base());
599 } else {
600 __ li(dst->as_register(), 0);
601 }
602 __ bso(CCR0, L);
603 __ fctiwz(rsrc, rsrc); // USE_KILL
604 if (dst_in_memory) {
605 __ stfd(rsrc, addr.disp(), addr.base());
606 } else {
607 __ mffprd(dst->as_register(), rsrc);
608 }
609 __ bind(L);
610 break;
611 }
612 case Bytecodes::_d2l:
613 case Bytecodes::_f2l: {
614 bool dst_in_memory = !VM_Version::has_mtfprd();
615 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
616 Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
617 Label L;
618 // Result must be 0 if value is NaN; test by comparing value to itself.
619 __ fcmpu(CCR0, rsrc, rsrc);
620 if (dst_in_memory) {
621 __ li(R0, 0); // 0 in case of NAN
622 __ std(R0, addr.disp(), addr.base());
623 } else {
624 __ li(dst->as_register_lo(), 0);
625 }
626 __ bso(CCR0, L);
627 __ fctidz(rsrc, rsrc); // USE_KILL
628 if (dst_in_memory) {
629 __ stfd(rsrc, addr.disp(), addr.base());
630 } else {
631 __ mffprd(dst->as_register_lo(), rsrc);
632 }
633 __ bind(L);
634 break;
635 }
636
637 default: ShouldNotReachHere();
638 }
639 }
640
641
642 void LIR_Assembler::align_call(LIR_Code) {
643 // do nothing since all instructions are word aligned on ppc
644 }
645
646
647 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
648 int start_offset = __ offset();
649 // Put the entry point as a constant into the constant pool.
650 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
651 if (entry_point_toc_addr == NULL) {
652 bailout("const section overflow");
653 return false;
654 }
655 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
656
657 // Emit the trampoline stub which will be related to the branch-and-link below.
658 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
659 if (!stub) {
660 bailout("no space for trampoline stub");
661 return false;
662 }
663 return true;
664 }
665
666
667 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
668 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
669
670 bool success = emit_trampoline_stub_for_call(op->addr());
671 if (!success) { return; }
672
673 __ relocate(rtype);
674 // Note: At this point we do not have the address of the trampoline
675 // stub, and the entry point might be too far away for bl, so __ pc()
676 // serves as dummy and the bl will be patched later.
677 __ code()->set_insts_mark();
678 __ bl(__ pc());
679 add_call_info(code_offset(), op->info());
680 }
681
682
683 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
684 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
685
686 // Virtual call relocation will point to ic load.
687 address virtual_call_meta_addr = __ pc();
688 // Load a clear inline cache.
689 AddressLiteral empty_ic((address) Universe::non_oop_word());
690 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
691 if (!success) {
692 bailout("const section overflow");
693 return;
694 }
695 // Call to fixup routine. Fixup routine uses ScopeDesc info
696 // to determine who we intended to call.
697 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
698
699 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
700 if (!success) { return; }
701
702 // Note: At this point we do not have the address of the trampoline
703 // stub, and the entry point might be too far away for bl, so __ pc()
704 // serves as dummy and the bl will be patched later.
705 __ bl(__ pc());
706 add_call_info(code_offset(), op->info());
707 }
708
709 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
710 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
711 __ null_check(addr, stub->entry());
712 append_code_stub(stub);
713 }
714
715
716 // Attention: caller must encode oop if needed
717 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide) {
718 int store_offset;
719 if (!Assembler::is_simm16(offset)) {
720 // For offsets larger than a simm16 we setup the offset.
721 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
722 __ load_const_optimized(R0, offset);
723 store_offset = store(from_reg, base, R0, type, wide);
724 } else {
725 store_offset = code_offset();
726 switch (type) {
727 case T_BOOLEAN: // fall through
728 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
729 case T_CHAR :
730 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
731 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
732 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
733 case T_ADDRESS:
734 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
735 case T_ARRAY : // fall through
736 case T_OBJECT:
737 {
738 if (UseCompressedOops && !wide) {
739 // Encoding done in caller
740 __ stw(from_reg->as_register(), offset, base);
741 __ verify_coop(from_reg->as_register(), FILE_AND_LINE);
742 } else {
743 __ std(from_reg->as_register(), offset, base);
744 __ verify_oop(from_reg->as_register(), FILE_AND_LINE);
745 }
746 break;
747 }
748 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
749 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
750 default : ShouldNotReachHere();
751 }
752 }
753 return store_offset;
754 }
755
756
757 // Attention: caller must encode oop if needed
758 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
759 int store_offset = code_offset();
760 switch (type) {
761 case T_BOOLEAN: // fall through
762 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
763 case T_CHAR :
764 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
765 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
766 case T_LONG :
767 #ifdef _LP64
768 __ stdx(from_reg->as_register_lo(), base, disp);
769 #else
770 Unimplemented();
771 #endif
772 break;
773 case T_ADDRESS:
774 __ stdx(from_reg->as_register(), base, disp);
775 break;
776 case T_ARRAY : // fall through
777 case T_OBJECT:
778 {
779 if (UseCompressedOops && !wide) {
780 // Encoding done in caller.
781 __ stwx(from_reg->as_register(), base, disp);
782 __ verify_coop(from_reg->as_register(), FILE_AND_LINE); // kills R0
783 } else {
784 __ stdx(from_reg->as_register(), base, disp);
785 __ verify_oop(from_reg->as_register(), FILE_AND_LINE); // kills R0
786 }
787 break;
788 }
789 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
790 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
791 default : ShouldNotReachHere();
792 }
793 return store_offset;
794 }
795
796
797 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide) {
798 int load_offset;
799 if (!Assembler::is_simm16(offset)) {
800 // For offsets larger than a simm16 we setup the offset.
801 __ load_const_optimized(R0, offset);
802 load_offset = load(base, R0, to_reg, type, wide);
803 } else {
804 load_offset = code_offset();
805 switch(type) {
806 case T_BOOLEAN: // fall through
807 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
808 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
809 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
810 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
811 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
812 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
813 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
814 case T_ADDRESS:
815 __ ld(to_reg->as_register(), offset, base);
816 break;
817 case T_ARRAY : // fall through
818 case T_OBJECT:
819 {
820 if (UseCompressedOops && !wide) {
821 __ lwz(to_reg->as_register(), offset, base);
822 __ decode_heap_oop(to_reg->as_register());
823 } else {
824 __ ld(to_reg->as_register(), offset, base);
825 }
826 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
827 break;
828 }
829 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
830 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
831 default : ShouldNotReachHere();
832 }
833 }
834 return load_offset;
835 }
836
837
838 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
839 int load_offset = code_offset();
840 switch(type) {
841 case T_BOOLEAN: // fall through
842 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
843 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
844 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
845 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
846 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
847 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
848 case T_ARRAY : // fall through
849 case T_OBJECT:
850 {
851 if (UseCompressedOops && !wide) {
852 __ lwzx(to_reg->as_register(), base, disp);
853 __ decode_heap_oop(to_reg->as_register());
854 } else {
855 __ ldx(to_reg->as_register(), base, disp);
856 }
857 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
858 break;
859 }
860 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
861 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
862 case T_LONG :
863 #ifdef _LP64
864 __ ldx(to_reg->as_register_lo(), base, disp);
865 #else
866 Unimplemented();
867 #endif
868 break;
869 default : ShouldNotReachHere();
870 }
871 return load_offset;
872 }
873
874
875 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
876 LIR_Const* c = src->as_constant_ptr();
877 Register src_reg = R0;
878 switch (c->type()) {
879 case T_INT:
880 case T_FLOAT: {
881 int value = c->as_jint_bits();
882 __ load_const_optimized(src_reg, value);
883 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
884 __ stw(src_reg, addr.disp(), addr.base());
885 break;
886 }
887 case T_ADDRESS: {
888 int value = c->as_jint_bits();
889 __ load_const_optimized(src_reg, value);
890 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
891 __ std(src_reg, addr.disp(), addr.base());
892 break;
893 }
894 case T_OBJECT: {
895 jobject2reg(c->as_jobject(), src_reg);
896 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
897 __ std(src_reg, addr.disp(), addr.base());
898 break;
899 }
900 case T_LONG:
901 case T_DOUBLE: {
902 int value = c->as_jlong_bits();
903 __ load_const_optimized(src_reg, value);
904 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
905 __ std(src_reg, addr.disp(), addr.base());
906 break;
907 }
908 default:
909 Unimplemented();
910 }
911 }
912
913
914 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
915 LIR_Const* c = src->as_constant_ptr();
916 LIR_Address* addr = dest->as_address_ptr();
917 Register base = addr->base()->as_pointer_register();
918 LIR_Opr tmp = LIR_OprFact::illegalOpr;
919 int offset = -1;
920 // Null check for large offsets in LIRGenerator::do_StoreField.
921 bool needs_explicit_null_check = !ImplicitNullChecks;
922
923 if (info != NULL && needs_explicit_null_check) {
924 explicit_null_check(base, info);
925 }
926
927 switch (c->type()) {
928 case T_FLOAT: type = T_INT;
929 case T_INT:
930 case T_ADDRESS: {
931 tmp = FrameMap::R0_opr;
932 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
933 break;
934 }
935 case T_DOUBLE: type = T_LONG;
936 case T_LONG: {
937 tmp = FrameMap::R0_long_opr;
938 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
939 break;
940 }
941 case T_OBJECT: {
942 tmp = FrameMap::R0_opr;
943 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
944 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
945 // Don't care about sign extend (will use stw).
946 __ lis(R0, 0); // Will get patched.
947 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
948 __ ori(R0, R0, 0); // Will get patched.
949 } else {
950 jobject2reg(c->as_jobject(), R0);
951 }
952 break;
953 }
954 default:
955 Unimplemented();
956 }
957
958 // Handle either reg+reg or reg+disp address.
959 if (addr->index()->is_valid()) {
960 assert(addr->disp() == 0, "must be zero");
961 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
962 } else {
963 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
964 offset = store(tmp, base, addr->disp(), type, wide);
965 }
966
967 if (info != NULL) {
968 assert(offset != -1, "offset should've been set");
969 if (!needs_explicit_null_check) {
970 add_debug_info_for_null_check(offset, info);
971 }
972 }
973 }
974
975
976 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
977 LIR_Const* c = src->as_constant_ptr();
978 LIR_Opr to_reg = dest;
979
980 switch (c->type()) {
981 case T_INT: {
982 assert(patch_code == lir_patch_none, "no patching handled here");
983 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
984 break;
985 }
986 case T_ADDRESS: {
987 assert(patch_code == lir_patch_none, "no patching handled here");
988 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
989 break;
990 }
991 case T_LONG: {
992 assert(patch_code == lir_patch_none, "no patching handled here");
993 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
994 break;
995 }
996
997 case T_OBJECT: {
998 if (patch_code == lir_patch_none) {
999 jobject2reg(c->as_jobject(), to_reg->as_register());
1000 } else {
1001 jobject2reg_with_patching(to_reg->as_register(), info);
1002 }
1003 break;
1004 }
1005
1006 case T_METADATA:
1007 {
1008 if (patch_code == lir_patch_none) {
1009 metadata2reg(c->as_metadata(), to_reg->as_register());
1010 } else {
1011 klass2reg_with_patching(to_reg->as_register(), info);
1012 }
1013 }
1014 break;
1015
1016 case T_FLOAT:
1017 {
1018 if (to_reg->is_single_fpu()) {
1019 address const_addr = __ float_constant(c->as_jfloat());
1020 if (const_addr == NULL) {
1021 bailout("const section overflow");
1022 break;
1023 }
1024 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1025 __ relocate(rspec);
1026 __ load_const(R0, const_addr);
1027 __ lfsx(to_reg->as_float_reg(), R0);
1028 } else {
1029 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1030 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1031 }
1032 }
1033 break;
1034
1035 case T_DOUBLE:
1036 {
1037 if (to_reg->is_double_fpu()) {
1038 address const_addr = __ double_constant(c->as_jdouble());
1039 if (const_addr == NULL) {
1040 bailout("const section overflow");
1041 break;
1042 }
1043 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1044 __ relocate(rspec);
1045 __ load_const(R0, const_addr);
1046 __ lfdx(to_reg->as_double_reg(), R0);
1047 } else {
1048 assert(to_reg->is_double_cpu(), "Must be a long register.");
1049 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1050 }
1051 }
1052 break;
1053
1054 default:
1055 ShouldNotReachHere();
1056 }
1057 }
1058
1059
1060 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1061 Unimplemented(); return Address();
1062 }
1063
1064
1065 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1066 if (addr->index()->is_illegal()) {
1067 return (RegisterOrConstant)(addr->disp());
1068 } else {
1069 return (RegisterOrConstant)(addr->index()->as_pointer_register());
1070 }
1071 }
1072
1073
1074 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1075 const Register tmp = R0;
1076 switch (type) {
1077 case T_INT:
1078 case T_FLOAT: {
1079 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1080 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1081 __ lwz(tmp, from.disp(), from.base());
1082 __ stw(tmp, to.disp(), to.base());
1083 break;
1084 }
1085 case T_ADDRESS:
1086 case T_OBJECT: {
1087 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1088 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1089 __ ld(tmp, from.disp(), from.base());
1090 __ std(tmp, to.disp(), to.base());
1091 break;
1092 }
1093 case T_LONG:
1094 case T_DOUBLE: {
1095 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1096 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1097 __ ld(tmp, from.disp(), from.base());
1098 __ std(tmp, to.disp(), to.base());
1099 break;
1100 }
1101
1102 default:
1103 ShouldNotReachHere();
1104 }
1105 }
1106
1107
1108 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1109 Unimplemented(); return Address();
1110 }
1111
1112
1113 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1114 Unimplemented(); return Address();
1115 }
1116
1117
1118 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1119 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
1120
1121 assert(type != T_METADATA, "load of metadata ptr not supported");
1122 LIR_Address* addr = src_opr->as_address_ptr();
1123 LIR_Opr to_reg = dest;
1124
1125 Register src = addr->base()->as_pointer_register();
1126 Register disp_reg = noreg;
1127 int disp_value = addr->disp();
1128 bool needs_patching = (patch_code != lir_patch_none);
1129 // null check for large offsets in LIRGenerator::do_LoadField
1130 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1131
1132 if (info != NULL && needs_explicit_null_check) {
1133 explicit_null_check(src, info);
1134 }
1135
1136 if (addr->base()->type() == T_OBJECT) {
1137 __ verify_oop(src, FILE_AND_LINE);
1138 }
1139
1140 PatchingStub* patch = NULL;
1141 if (needs_patching) {
1142 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1143 assert(!to_reg->is_double_cpu() ||
1144 patch_code == lir_patch_none ||
1145 patch_code == lir_patch_normal, "patching doesn't match register");
1146 }
1147
1148 if (addr->index()->is_illegal()) {
1149 if (!Assembler::is_simm16(disp_value)) {
1150 if (needs_patching) {
1151 __ load_const32(R0, 0); // patchable int
1152 } else {
1153 __ load_const_optimized(R0, disp_value);
1154 }
1155 disp_reg = R0;
1156 }
1157 } else {
1158 disp_reg = addr->index()->as_pointer_register();
1159 assert(disp_value == 0, "can't handle 3 operand addresses");
1160 }
1161
1162 // Remember the offset of the load. The patching_epilog must be done
1163 // before the call to add_debug_info, otherwise the PcDescs don't get
1164 // entered in increasing order.
1165 int offset;
1166
1167 if (disp_reg == noreg) {
1168 assert(Assembler::is_simm16(disp_value), "should have set this up");
1169 offset = load(src, disp_value, to_reg, type, wide);
1170 } else {
1171 offset = load(src, disp_reg, to_reg, type, wide);
1172 }
1173
1174 if (patch != NULL) {
1175 patching_epilog(patch, patch_code, src, info);
1176 }
1177 if (info != NULL && !needs_explicit_null_check) {
1178 add_debug_info_for_null_check(offset, info);
1179 }
1180 }
1181
1182
1183 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1184 Address addr;
1185 if (src->is_single_word()) {
1186 addr = frame_map()->address_for_slot(src->single_stack_ix());
1187 } else if (src->is_double_word()) {
1188 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1189 }
1190
1191 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/);
1192 }
1193
1194
1195 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1196 Address addr;
1197 if (dest->is_single_word()) {
1198 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1199 } else if (dest->is_double_word()) {
1200 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1201 }
1202
1203 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/);
1204 }
1205
1206
1207 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1208 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1209 if (from_reg->is_double_fpu()) {
1210 // double to double moves
1211 assert(to_reg->is_double_fpu(), "should match");
1212 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1213 } else {
1214 // float to float moves
1215 assert(to_reg->is_single_fpu(), "should match");
1216 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1217 }
1218 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1219 if (from_reg->is_double_cpu()) {
1220 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1221 } else if (to_reg->is_double_cpu()) {
1222 // int to int moves
1223 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1224 } else {
1225 // int to int moves
1226 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1227 }
1228 } else {
1229 ShouldNotReachHere();
1230 }
1231 if (is_reference_type(to_reg->type())) {
1232 __ verify_oop(to_reg->as_register(), FILE_AND_LINE);
1233 }
1234 }
1235
1236
1237 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1238 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1239 bool wide) {
1240 assert(type != T_METADATA, "store of metadata ptr not supported");
1241 LIR_Address* addr = dest->as_address_ptr();
1242
1243 Register src = addr->base()->as_pointer_register();
1244 Register disp_reg = noreg;
1245 int disp_value = addr->disp();
1246 bool needs_patching = (patch_code != lir_patch_none);
1247 bool compress_oop = (is_reference_type(type)) && UseCompressedOops && !wide &&
1248 CompressedOops::mode() != CompressedOops::UnscaledNarrowOop;
1249 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1250 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1251 // Null check for large offsets in LIRGenerator::do_StoreField.
1252 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1253
1254 if (info != NULL && needs_explicit_null_check) {
1255 explicit_null_check(src, info);
1256 }
1257
1258 if (addr->base()->is_oop_register()) {
1259 __ verify_oop(src, FILE_AND_LINE);
1260 }
1261
1262 PatchingStub* patch = NULL;
1263 if (needs_patching) {
1264 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1265 assert(!from_reg->is_double_cpu() ||
1266 patch_code == lir_patch_none ||
1267 patch_code == lir_patch_normal, "patching doesn't match register");
1268 }
1269
1270 if (addr->index()->is_illegal()) {
1271 if (load_disp) {
1272 disp_reg = use_R29 ? R29_TOC : R0;
1273 if (needs_patching) {
1274 __ load_const32(disp_reg, 0); // patchable int
1275 } else {
1276 __ load_const_optimized(disp_reg, disp_value);
1277 }
1278 }
1279 } else {
1280 disp_reg = addr->index()->as_pointer_register();
1281 assert(disp_value == 0, "can't handle 3 operand addresses");
1282 }
1283
1284 // remember the offset of the store. The patching_epilog must be done
1285 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1286 // entered in increasing order.
1287 int offset;
1288
1289 if (compress_oop) {
1290 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1291 from_reg = FrameMap::as_opr(co);
1292 }
1293
1294 if (disp_reg == noreg) {
1295 assert(Assembler::is_simm16(disp_value), "should have set this up");
1296 offset = store(from_reg, src, disp_value, type, wide);
1297 } else {
1298 offset = store(from_reg, src, disp_reg, type, wide);
1299 }
1300
1301 if (use_R29) {
1302 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1303 }
1304
1305 if (patch != NULL) {
1306 patching_epilog(patch, patch_code, src, info);
1307 }
1308
1309 if (info != NULL && !needs_explicit_null_check) {
1310 add_debug_info_for_null_check(offset, info);
1311 }
1312 }
1313
1314
1315 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
1316 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1317 const Register temp = R12;
1318
1319 // Pop the stack before the safepoint code.
1320 int frame_size = initial_frame_size_in_bytes();
1321 if (Assembler::is_simm(frame_size, 16)) {
1322 __ addi(R1_SP, R1_SP, frame_size);
1323 } else {
1324 __ pop_frame();
1325 }
1326
1327 // Restore return pc relative to callers' sp.
1328 __ ld(return_pc, _abi0(lr), R1_SP);
1329 // Move return pc to LR.
1330 __ mtlr(return_pc);
1331
1332 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1333 __ reserved_stack_check(return_pc);
1334 }
1335
1336 // We need to mark the code position where the load from the safepoint
1337 // polling page was emitted as relocInfo::poll_return_type here.
1338 if (!UseSIGTRAP) {
1339 code_stub->set_safepoint_offset(__ offset());
1340 __ relocate(relocInfo::poll_return_type);
1341 }
1342 __ safepoint_poll(*code_stub->entry(), temp, true /* at_return */, true /* in_nmethod */);
1343
1344 // Return.
1345 __ blr();
1346 }
1347
1348
1349 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1350 const Register poll_addr = tmp->as_register();
1351 __ ld(poll_addr, in_bytes(JavaThread::polling_page_offset()), R16_thread);
1352 if (info != NULL) {
1353 add_debug_info_for_branch(info);
1354 }
1355 int offset = __ offset();
1356 __ relocate(relocInfo::poll_type);
1357 __ load_from_polling_page(poll_addr);
1358
1359 return offset;
1360 }
1361
1362
1363 void LIR_Assembler::emit_static_call_stub() {
1364 address call_pc = __ pc();
1365 address stub = __ start_a_stub(static_call_stub_size());
1366 if (stub == NULL) {
1367 bailout("static call stub overflow");
1368 return;
1369 }
1370
1371 // For java_to_interp stubs we use R11_scratch1 as scratch register
1372 // and in call trampoline stubs we use R12_scratch2. This way we
1373 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1374 const Register reg_scratch = R11_scratch1;
1375
1376 // Create a static stub relocation which relates this stub
1377 // with the call instruction at insts_call_instruction_offset in the
1378 // instructions code-section.
1379 int start = __ offset();
1380 __ relocate(static_stub_Relocation::spec(call_pc));
1381
1382 // Now, create the stub's code:
1383 // - load the TOC
1384 // - load the inline cache oop from the constant pool
1385 // - load the call target from the constant pool
1386 // - call
1387 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1388 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1389 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1390
1391 if (ReoptimizeCallSequences) {
1392 __ b64_patchable((address)-1, relocInfo::none);
1393 } else {
1394 AddressLiteral a((address)-1);
1395 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1396 __ mtctr(reg_scratch);
1397 __ bctr();
1398 }
1399 if (!success) {
1400 bailout("const section overflow");
1401 return;
1402 }
1403
1404 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1405 __ end_a_stub();
1406 }
1407
1408
1409 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1410 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1411 if (opr1->is_single_fpu()) {
1412 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1413 } else if (opr1->is_double_fpu()) {
1414 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1415 } else if (opr1->is_single_cpu()) {
1416 if (opr2->is_constant()) {
1417 switch (opr2->as_constant_ptr()->type()) {
1418 case T_INT:
1419 {
1420 jint con = opr2->as_constant_ptr()->as_jint();
1421 if (unsigned_comp) {
1422 if (Assembler::is_uimm(con, 16)) {
1423 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1424 } else {
1425 __ load_const_optimized(R0, con);
1426 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1427 }
1428 } else {
1429 if (Assembler::is_simm(con, 16)) {
1430 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1431 } else {
1432 __ load_const_optimized(R0, con);
1433 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1434 }
1435 }
1436 }
1437 break;
1438
1439 case T_OBJECT:
1440 // There are only equal/notequal comparisons on objects.
1441 {
1442 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1443 jobject con = opr2->as_constant_ptr()->as_jobject();
1444 if (con == NULL) {
1445 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1446 } else {
1447 jobject2reg(con, R0);
1448 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1449 }
1450 }
1451 break;
1452
1453 case T_METADATA:
1454 // We only need, for now, comparison with NULL for metadata.
1455 {
1456 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1457 Metadata* p = opr2->as_constant_ptr()->as_metadata();
1458 if (p == NULL) {
1459 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1460 } else {
1461 ShouldNotReachHere();
1462 }
1463 }
1464 break;
1465
1466 default:
1467 ShouldNotReachHere();
1468 break;
1469 }
1470 } else {
1471 assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1472 if (is_reference_type(opr1->type())) {
1473 // There are only equal/notequal comparisons on objects.
1474 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1475 __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1476 } else {
1477 if (unsigned_comp) {
1478 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1479 } else {
1480 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1481 }
1482 }
1483 }
1484 } else if (opr1->is_double_cpu()) {
1485 if (opr2->is_constant()) {
1486 jlong con = opr2->as_constant_ptr()->as_jlong();
1487 if (unsigned_comp) {
1488 if (Assembler::is_uimm(con, 16)) {
1489 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1490 } else {
1491 __ load_const_optimized(R0, con);
1492 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1493 }
1494 } else {
1495 if (Assembler::is_simm(con, 16)) {
1496 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1497 } else {
1498 __ load_const_optimized(R0, con);
1499 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1500 }
1501 }
1502 } else if (opr2->is_register()) {
1503 if (unsigned_comp) {
1504 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1505 } else {
1506 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1507 }
1508 } else {
1509 ShouldNotReachHere();
1510 }
1511 } else {
1512 ShouldNotReachHere();
1513 }
1514 }
1515
1516
1517 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1518 const Register Rdst = dst->as_register();
1519 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1520 bool is_unordered_less = (code == lir_ucmp_fd2i);
1521 if (left->is_single_fpu()) {
1522 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1523 } else if (left->is_double_fpu()) {
1524 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1525 } else {
1526 ShouldNotReachHere();
1527 }
1528 __ set_cmpu3(Rdst, is_unordered_less); // is_unordered_less ? -1 : 1
1529 } else if (code == lir_cmp_l2i) {
1530 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1531 __ set_cmp3(Rdst); // set result as follows: <: -1, =: 0, >: 1
1532 } else {
1533 ShouldNotReachHere();
1534 }
1535 }
1536
1537
1538 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1539 if (src->is_constant()) {
1540 lasm->const2reg(src, dst, lir_patch_none, NULL);
1541 } else if (src->is_register()) {
1542 lasm->reg2reg(src, dst);
1543 } else if (src->is_stack()) {
1544 lasm->stack2reg(src, dst, dst->type());
1545 } else {
1546 ShouldNotReachHere();
1547 }
1548 }
1549
1550 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1551 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1552 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
1553
1554 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1555 load_to_reg(this, opr1, result); // Condition doesn't matter.
1556 return;
1557 }
1558
1559 bool positive = false;
1560 Assembler::Condition cond = Assembler::equal;
1561 switch (condition) {
1562 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1563 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1564 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1565 case lir_cond_belowEqual:
1566 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1567 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1568 case lir_cond_aboveEqual:
1569 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1570 default: ShouldNotReachHere();
1571 }
1572
1573 // Try to use isel on >=Power7.
1574 if (VM_Version::has_isel() && result->is_cpu_register()) {
1575 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1576 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1577
1578 // We can use result_reg to load one operand if not already in register.
1579 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1580 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1581
1582 if (first != second) {
1583 if (!o1_is_reg) {
1584 load_to_reg(this, opr1, result);
1585 }
1586
1587 if (!o2_is_reg) {
1588 load_to_reg(this, opr2, result);
1589 }
1590
1591 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1592 return;
1593 }
1594 } // isel
1595
1596 load_to_reg(this, opr1, result);
1597
1598 Label skip;
1599 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1600 int bi = Assembler::bi0(BOOL_RESULT, cond);
1601 __ bc(bo, bi, skip);
1602
1603 load_to_reg(this, opr2, result);
1604 __ bind(skip);
1605 }
1606
1607
1608 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1609 CodeEmitInfo* info, bool pop_fpu_stack) {
1610 assert(info == NULL, "unused on this code path");
1611 assert(left->is_register(), "wrong items state");
1612 assert(dest->is_register(), "wrong items state");
1613
1614 if (right->is_register()) {
1615 if (dest->is_float_kind()) {
1616
1617 FloatRegister lreg, rreg, res;
1618 if (right->is_single_fpu()) {
1619 lreg = left->as_float_reg();
1620 rreg = right->as_float_reg();
1621 res = dest->as_float_reg();
1622 switch (code) {
1623 case lir_add: __ fadds(res, lreg, rreg); break;
1624 case lir_sub: __ fsubs(res, lreg, rreg); break;
1625 case lir_mul: __ fmuls(res, lreg, rreg); break;
1626 case lir_div: __ fdivs(res, lreg, rreg); break;
1627 default: ShouldNotReachHere();
1628 }
1629 } else {
1630 lreg = left->as_double_reg();
1631 rreg = right->as_double_reg();
1632 res = dest->as_double_reg();
1633 switch (code) {
1634 case lir_add: __ fadd(res, lreg, rreg); break;
1635 case lir_sub: __ fsub(res, lreg, rreg); break;
1636 case lir_mul: __ fmul(res, lreg, rreg); break;
1637 case lir_div: __ fdiv(res, lreg, rreg); break;
1638 default: ShouldNotReachHere();
1639 }
1640 }
1641
1642 } else if (dest->is_double_cpu()) {
1643
1644 Register dst_lo = dest->as_register_lo();
1645 Register op1_lo = left->as_pointer_register();
1646 Register op2_lo = right->as_pointer_register();
1647
1648 switch (code) {
1649 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1650 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1651 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1652 default: ShouldNotReachHere();
1653 }
1654 } else {
1655 assert (right->is_single_cpu(), "Just Checking");
1656
1657 Register lreg = left->as_register();
1658 Register res = dest->as_register();
1659 Register rreg = right->as_register();
1660 switch (code) {
1661 case lir_add: __ add (res, lreg, rreg); break;
1662 case lir_sub: __ sub (res, lreg, rreg); break;
1663 case lir_mul: __ mullw(res, lreg, rreg); break;
1664 default: ShouldNotReachHere();
1665 }
1666 }
1667 } else {
1668 assert (right->is_constant(), "must be constant");
1669
1670 if (dest->is_single_cpu()) {
1671 Register lreg = left->as_register();
1672 Register res = dest->as_register();
1673 int simm16 = right->as_constant_ptr()->as_jint();
1674
1675 switch (code) {
1676 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1677 simm16 = -simm16;
1678 case lir_add: if (res == lreg && simm16 == 0) break;
1679 __ addi(res, lreg, simm16); break;
1680 case lir_mul: if (res == lreg && simm16 == 1) break;
1681 __ mulli(res, lreg, simm16); break;
1682 default: ShouldNotReachHere();
1683 }
1684 } else {
1685 Register lreg = left->as_pointer_register();
1686 Register res = dest->as_register_lo();
1687 long con = right->as_constant_ptr()->as_jlong();
1688 assert(Assembler::is_simm16(con), "must be simm16");
1689
1690 switch (code) {
1691 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1692 con = -con;
1693 case lir_add: if (res == lreg && con == 0) break;
1694 __ addi(res, lreg, (int)con); break;
1695 case lir_mul: if (res == lreg && con == 1) break;
1696 __ mulli(res, lreg, (int)con); break;
1697 default: ShouldNotReachHere();
1698 }
1699 }
1700 }
1701 }
1702
1703
1704 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1705 switch (code) {
1706 case lir_sqrt: {
1707 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1708 break;
1709 }
1710 case lir_abs: {
1711 __ fabs(dest->as_double_reg(), value->as_double_reg());
1712 break;
1713 }
1714 default: {
1715 ShouldNotReachHere();
1716 break;
1717 }
1718 }
1719 }
1720
1721
1722 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1723 if (right->is_constant()) { // see do_LogicOp
1724 long uimm;
1725 Register d, l;
1726 if (dest->is_single_cpu()) {
1727 uimm = right->as_constant_ptr()->as_jint();
1728 d = dest->as_register();
1729 l = left->as_register();
1730 } else {
1731 uimm = right->as_constant_ptr()->as_jlong();
1732 d = dest->as_register_lo();
1733 l = left->as_register_lo();
1734 }
1735 long uimms = (unsigned long)uimm >> 16,
1736 uimmss = (unsigned long)uimm >> 32;
1737
1738 switch (code) {
1739 case lir_logic_and:
1740 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2(uimm)) {
1741 __ andi(d, l, uimm); // special cases
1742 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1743 else { __ andi_(d, l, uimm); }
1744 break;
1745
1746 case lir_logic_or:
1747 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1748 else { __ ori(d, l, uimm); }
1749 break;
1750
1751 case lir_logic_xor:
1752 if (uimm == -1) { __ nand(d, l, l); } // special case
1753 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1754 else { __ xori(d, l, uimm); }
1755 break;
1756
1757 default: ShouldNotReachHere();
1758 }
1759 } else {
1760 assert(right->is_register(), "right should be in register");
1761
1762 if (dest->is_single_cpu()) {
1763 switch (code) {
1764 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1765 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1766 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1767 default: ShouldNotReachHere();
1768 }
1769 } else {
1770 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1771 left->as_register_lo();
1772 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1773 right->as_register_lo();
1774
1775 switch (code) {
1776 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1777 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1778 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1779 default: ShouldNotReachHere();
1780 }
1781 }
1782 }
1783 }
1784
1785
1786 int LIR_Assembler::shift_amount(BasicType t) {
1787 int elem_size = type2aelembytes(t);
1788 switch (elem_size) {
1789 case 1 : return 0;
1790 case 2 : return 1;
1791 case 4 : return 2;
1792 case 8 : return 3;
1793 }
1794 ShouldNotReachHere();
1795 return -1;
1796 }
1797
1798
1799 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1800 info->add_register_oop(exceptionOop);
1801
1802 // Reuse the debug info from the safepoint poll for the throw op itself.
1803 address pc_for_athrow = __ pc();
1804 int pc_for_athrow_offset = __ offset();
1805 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1806 //__ relocate(rspec);
1807 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1808 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1809 add_call_info(pc_for_athrow_offset, info); // for exception handler
1810
1811 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1812 : Runtime1::handle_exception_nofpu_id);
1813 //__ load_const_optimized(R0, stub);
1814 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1815 __ mtctr(R0);
1816 __ bctr();
1817 }
1818
1819
1820 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1821 // Note: Not used with EnableDebuggingOnDemand.
1822 assert(exceptionOop->as_register() == R3, "should match");
1823 __ b(_unwind_handler_entry);
1824 }
1825
1826
1827 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1828 Register src = op->src()->as_register();
1829 Register dst = op->dst()->as_register();
1830 Register src_pos = op->src_pos()->as_register();
1831 Register dst_pos = op->dst_pos()->as_register();
1832 Register length = op->length()->as_register();
1833 Register tmp = op->tmp()->as_register();
1834 Register tmp2 = R0;
1835
1836 int flags = op->flags();
1837 ciArrayKlass* default_type = op->expected_type();
1838 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1839 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1840
1841 // Set up the arraycopy stub information.
1842 ArrayCopyStub* stub = op->stub();
1843 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1844
1845 // Always do stub if no type information is available. It's ok if
1846 // the known type isn't loaded since the code sanity checks
1847 // in debug mode and the type isn't required when we know the exact type
1848 // also check that the type is an array type.
1849 if (op->expected_type() == NULL) {
1850 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1851 length->is_nonvolatile(), "must preserve");
1852 address copyfunc_addr = StubRoutines::generic_arraycopy();
1853 assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1854
1855 // 3 parms are int. Convert to long.
1856 __ mr(R3_ARG1, src);
1857 __ extsw(R4_ARG2, src_pos);
1858 __ mr(R5_ARG3, dst);
1859 __ extsw(R6_ARG4, dst_pos);
1860 __ extsw(R7_ARG5, length);
1861
1862 #ifndef PRODUCT
1863 if (PrintC1Statistics) {
1864 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1865 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1866 __ lwz(R11_scratch1, simm16_offs, tmp);
1867 __ addi(R11_scratch1, R11_scratch1, 1);
1868 __ stw(R11_scratch1, simm16_offs, tmp);
1869 }
1870 #endif
1871 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1872
1873 __ nand(tmp, R3_RET, R3_RET);
1874 __ subf(length, tmp, length);
1875 __ add(src_pos, tmp, src_pos);
1876 __ add(dst_pos, tmp, dst_pos);
1877
1878 __ cmpwi(CCR0, R3_RET, 0);
1879 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1880 __ bind(*stub->continuation());
1881 return;
1882 }
1883
1884 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1885 Label cont, slow, copyfunc;
1886
1887 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1888 LIR_OpArrayCopy::dst_null_check |
1889 LIR_OpArrayCopy::src_pos_positive_check |
1890 LIR_OpArrayCopy::dst_pos_positive_check |
1891 LIR_OpArrayCopy::length_positive_check);
1892
1893 // Use only one conditional branch for simple checks.
1894 if (simple_check_flag_set) {
1895 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1896
1897 // Make sure src and dst are non-null.
1898 if (flags & LIR_OpArrayCopy::src_null_check) {
1899 __ cmpdi(combined_check, src, 0);
1900 tmp_check = CCR0;
1901 }
1902
1903 if (flags & LIR_OpArrayCopy::dst_null_check) {
1904 __ cmpdi(tmp_check, dst, 0);
1905 if (tmp_check != combined_check) {
1906 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1907 }
1908 tmp_check = CCR0;
1909 }
1910
1911 // Clear combined_check.eq if not already used.
1912 if (tmp_check == combined_check) {
1913 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1914 tmp_check = CCR0;
1915 }
1916
1917 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1918 // Test src_pos register.
1919 __ cmpwi(tmp_check, src_pos, 0);
1920 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1921 }
1922
1923 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1924 // Test dst_pos register.
1925 __ cmpwi(tmp_check, dst_pos, 0);
1926 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1927 }
1928
1929 if (flags & LIR_OpArrayCopy::length_positive_check) {
1930 // Make sure length isn't negative.
1931 __ cmpwi(tmp_check, length, 0);
1932 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1933 }
1934
1935 __ beq(combined_check, slow);
1936 }
1937
1938 // If the compiler was not able to prove that exact type of the source or the destination
1939 // of the arraycopy is an array type, check at runtime if the source or the destination is
1940 // an instance type.
1941 if (flags & LIR_OpArrayCopy::type_check) {
1942 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1943 __ load_klass(tmp, dst);
1944 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1945 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1946 __ bge(CCR0, slow);
1947 }
1948
1949 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1950 __ load_klass(tmp, src);
1951 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1952 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1953 __ bge(CCR0, slow);
1954 }
1955 }
1956
1957 // Higher 32bits must be null.
1958 __ extsw(length, length);
1959
1960 __ extsw(src_pos, src_pos);
1961 if (flags & LIR_OpArrayCopy::src_range_check) {
1962 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1963 __ add(tmp, length, src_pos);
1964 __ cmpld(CCR0, tmp2, tmp);
1965 __ ble(CCR0, slow);
1966 }
1967
1968 __ extsw(dst_pos, dst_pos);
1969 if (flags & LIR_OpArrayCopy::dst_range_check) {
1970 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1971 __ add(tmp, length, dst_pos);
1972 __ cmpld(CCR0, tmp2, tmp);
1973 __ ble(CCR0, slow);
1974 }
1975
1976 int shift = shift_amount(basic_type);
1977
1978 if (!(flags & LIR_OpArrayCopy::type_check)) {
1979 __ b(cont);
1980 } else {
1981 // We don't know the array types are compatible.
1982 if (basic_type != T_OBJECT) {
1983 // Simple test for basic type arrays.
1984 if (UseCompressedClassPointers) {
1985 // We don't need decode because we just need to compare.
1986 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1987 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1988 __ cmpw(CCR0, tmp, tmp2);
1989 } else {
1990 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1991 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1992 __ cmpd(CCR0, tmp, tmp2);
1993 }
1994 __ beq(CCR0, cont);
1995 } else {
1996 // For object arrays, if src is a sub class of dst then we can
1997 // safely do the copy.
1998 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1999
2000 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2001 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2002
2003 __ load_klass(sub_klass, src);
2004 __ load_klass(super_klass, dst);
2005
2006 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2007 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
2008
2009 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2010 //__ load_const_optimized(tmp, slow_stc, tmp2);
2011 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2012 __ mtctr(tmp);
2013 __ bctrl(); // sets CR0
2014 __ beq(CCR0, cont);
2015
2016 if (copyfunc_addr != NULL) { // Use stub if available.
2017 __ bind(copyfunc);
2018 // Src is not a sub class of dst so we have to do a
2019 // per-element check.
2020 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2021 if ((flags & mask) != mask) {
2022 assert(flags & mask, "one of the two should be known to be an object array");
2023
2024 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2025 __ load_klass(tmp, src);
2026 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2027 __ load_klass(tmp, dst);
2028 }
2029
2030 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2031
2032 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2033 __ load_const_optimized(tmp, objArray_lh);
2034 __ cmpw(CCR0, tmp, tmp2);
2035 __ bne(CCR0, slow);
2036 }
2037
2038 Register src_ptr = R3_ARG1;
2039 Register dst_ptr = R4_ARG2;
2040 Register len = R5_ARG3;
2041 Register chk_off = R6_ARG4;
2042 Register super_k = R7_ARG5;
2043
2044 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2045 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2046 if (shift == 0) {
2047 __ add(src_ptr, src_pos, src_ptr);
2048 __ add(dst_ptr, dst_pos, dst_ptr);
2049 } else {
2050 __ sldi(tmp, src_pos, shift);
2051 __ sldi(tmp2, dst_pos, shift);
2052 __ add(src_ptr, tmp, src_ptr);
2053 __ add(dst_ptr, tmp2, dst_ptr);
2054 }
2055
2056 __ load_klass(tmp, dst);
2057 __ mr(len, length);
2058
2059 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2060 __ ld(super_k, ek_offset, tmp);
2061
2062 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2063 __ lwz(chk_off, sco_offset, super_k);
2064
2065 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2066
2067 #ifndef PRODUCT
2068 if (PrintC1Statistics) {
2069 Label failed;
2070 __ cmpwi(CCR0, R3_RET, 0);
2071 __ bne(CCR0, failed);
2072 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2073 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2074 __ lwz(R11_scratch1, simm16_offs, tmp);
2075 __ addi(R11_scratch1, R11_scratch1, 1);
2076 __ stw(R11_scratch1, simm16_offs, tmp);
2077 __ bind(failed);
2078 }
2079 #endif
2080
2081 __ nand(tmp, R3_RET, R3_RET);
2082 __ cmpwi(CCR0, R3_RET, 0);
2083 __ beq(CCR0, *stub->continuation());
2084
2085 #ifndef PRODUCT
2086 if (PrintC1Statistics) {
2087 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2088 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2089 __ lwz(R11_scratch1, simm16_offs, tmp);
2090 __ addi(R11_scratch1, R11_scratch1, 1);
2091 __ stw(R11_scratch1, simm16_offs, tmp);
2092 }
2093 #endif
2094
2095 __ subf(length, tmp, length);
2096 __ add(src_pos, tmp, src_pos);
2097 __ add(dst_pos, tmp, dst_pos);
2098 }
2099 }
2100 }
2101 __ bind(slow);
2102 __ b(*stub->entry());
2103 __ bind(cont);
2104
2105 #ifdef ASSERT
2106 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2107 // Sanity check the known type with the incoming class. For the
2108 // primitive case the types must match exactly with src.klass and
2109 // dst.klass each exactly matching the default type. For the
2110 // object array case, if no type check is needed then either the
2111 // dst type is exactly the expected type and the src type is a
2112 // subtype which we can't check or src is the same array as dst
2113 // but not necessarily exactly of type default_type.
2114 Label known_ok, halt;
2115 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2116 if (UseCompressedClassPointers) {
2117 // Tmp holds the default type. It currently comes uncompressed after the
2118 // load of a constant, so encode it.
2119 __ encode_klass_not_null(tmp);
2120 // Load the raw value of the dst klass, since we will be comparing
2121 // uncompressed values directly.
2122 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2123 __ cmpw(CCR0, tmp, tmp2);
2124 if (basic_type != T_OBJECT) {
2125 __ bne(CCR0, halt);
2126 // Load the raw value of the src klass.
2127 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2128 __ cmpw(CCR0, tmp, tmp2);
2129 __ beq(CCR0, known_ok);
2130 } else {
2131 __ beq(CCR0, known_ok);
2132 __ cmpw(CCR0, src, dst);
2133 __ beq(CCR0, known_ok);
2134 }
2135 } else {
2136 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2137 __ cmpd(CCR0, tmp, tmp2);
2138 if (basic_type != T_OBJECT) {
2139 __ bne(CCR0, halt);
2140 // Load the raw value of the src klass.
2141 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2142 __ cmpd(CCR0, tmp, tmp2);
2143 __ beq(CCR0, known_ok);
2144 } else {
2145 __ beq(CCR0, known_ok);
2146 __ cmpd(CCR0, src, dst);
2147 __ beq(CCR0, known_ok);
2148 }
2149 }
2150 __ bind(halt);
2151 __ stop("incorrect type information in arraycopy");
2152 __ bind(known_ok);
2153 }
2154 #endif
2155
2156 #ifndef PRODUCT
2157 if (PrintC1Statistics) {
2158 address counter = Runtime1::arraycopy_count_address(basic_type);
2159 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2160 __ lwz(R11_scratch1, simm16_offs, tmp);
2161 __ addi(R11_scratch1, R11_scratch1, 1);
2162 __ stw(R11_scratch1, simm16_offs, tmp);
2163 }
2164 #endif
2165
2166 Register src_ptr = R3_ARG1;
2167 Register dst_ptr = R4_ARG2;
2168 Register len = R5_ARG3;
2169
2170 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2171 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2172 if (shift == 0) {
2173 __ add(src_ptr, src_pos, src_ptr);
2174 __ add(dst_ptr, dst_pos, dst_ptr);
2175 } else {
2176 __ sldi(tmp, src_pos, shift);
2177 __ sldi(tmp2, dst_pos, shift);
2178 __ add(src_ptr, tmp, src_ptr);
2179 __ add(dst_ptr, tmp2, dst_ptr);
2180 }
2181
2182 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2183 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2184 const char *name;
2185 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2186
2187 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2188 __ mr(len, length);
2189 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2190
2191 __ bind(*stub->continuation());
2192 }
2193
2194
2195 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2196 if (dest->is_single_cpu()) {
2197 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2198 #ifdef _LP64
2199 if (left->type() == T_OBJECT) {
2200 switch (code) {
2201 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2202 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2203 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2204 default: ShouldNotReachHere();
2205 }
2206 } else
2207 #endif
2208 switch (code) {
2209 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2210 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2211 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2212 default: ShouldNotReachHere();
2213 }
2214 } else {
2215 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2216 switch (code) {
2217 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2218 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2219 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2220 default: ShouldNotReachHere();
2221 }
2222 }
2223 }
2224
2225
2226 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2227 #ifdef _LP64
2228 if (left->type() == T_OBJECT) {
2229 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2230 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2231 else {
2232 switch (code) {
2233 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2234 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2235 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2236 default: ShouldNotReachHere();
2237 }
2238 }
2239 return;
2240 }
2241 #endif
2242
2243 if (dest->is_single_cpu()) {
2244 count = count & 0x1F; // Java spec
2245 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2246 else {
2247 switch (code) {
2248 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2249 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2250 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2251 default: ShouldNotReachHere();
2252 }
2253 }
2254 } else if (dest->is_double_cpu()) {
2255 count = count & 63; // Java spec
2256 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2257 else {
2258 switch (code) {
2259 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2260 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2261 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2262 default: ShouldNotReachHere();
2263 }
2264 }
2265 } else {
2266 ShouldNotReachHere();
2267 }
2268 }
2269
2270
2271 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2272 if (op->init_check()) {
2273 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2274 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2275 } else {
2276 add_debug_info_for_null_check_here(op->stub()->info());
2277 }
2278 __ lbz(op->tmp1()->as_register(),
2279 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2280 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2281 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2282 }
2283 __ allocate_object(op->obj()->as_register(),
2284 op->tmp1()->as_register(),
2285 op->tmp2()->as_register(),
2286 op->tmp3()->as_register(),
2287 op->header_size(),
2288 op->object_size(),
2289 op->klass()->as_register(),
2290 *op->stub()->entry());
2291
2292 __ bind(*op->stub()->continuation());
2293 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE);
2294 }
2295
2296
2297 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2298 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2299 if (UseSlowPath ||
2300 (!UseFastNewObjectArray && (is_reference_type(op->type()))) ||
2301 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) {
2302 __ b(*op->stub()->entry());
2303 } else {
2304 __ allocate_array(op->obj()->as_register(),
2305 op->len()->as_register(),
2306 op->tmp1()->as_register(),
2307 op->tmp2()->as_register(),
2308 op->tmp3()->as_register(),
2309 arrayOopDesc::header_size(op->type()),
2310 type2aelembytes(op->type()),
2311 op->klass()->as_register(),
2312 *op->stub()->entry());
2313 }
2314 __ bind(*op->stub()->continuation());
2315 }
2316
2317
2318 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2319 ciMethodData *md, ciProfileData *data,
2320 Register recv, Register tmp1, Label* update_done) {
2321 uint i;
2322 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2323 Label next_test;
2324 // See if the receiver is receiver[n].
2325 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2326 __ verify_klass_ptr(tmp1);
2327 __ cmpd(CCR0, recv, tmp1);
2328 __ bne(CCR0, next_test);
2329
2330 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2331 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2332 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2333 __ b(*update_done);
2334
2335 __ bind(next_test);
2336 }
2337
2338 // Didn't find receiver; find next empty slot and fill it in.
2339 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2340 Label next_test;
2341 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2342 __ cmpdi(CCR0, tmp1, 0);
2343 __ bne(CCR0, next_test);
2344 __ li(tmp1, DataLayout::counter_increment);
2345 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2346 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2347 __ b(*update_done);
2348
2349 __ bind(next_test);
2350 }
2351 }
2352
2353
2354 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2355 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2356 md = method->method_data_or_null();
2357 assert(md != NULL, "Sanity");
2358 data = md->bci_to_data(bci);
2359 assert(data != NULL, "need data for checkcast");
2360 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2361 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2362 // The offset is large so bias the mdo by the base of the slot so
2363 // that the ld can use simm16s to reference the slots of the data.
2364 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2365 }
2366 }
2367
2368
2369 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2370 const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2371 Register k_RInfo = op->tmp1()->as_register();
2372 Register klass_RInfo = op->tmp2()->as_register();
2373 Register Rtmp1 = op->tmp3()->as_register();
2374 Register dst = op->result_opr()->as_register();
2375 ciKlass* k = op->klass();
2376 bool should_profile = op->should_profile();
2377 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2378 bool reg_conflict = false;
2379 if (obj == k_RInfo) {
2380 k_RInfo = dst;
2381 reg_conflict = true;
2382 } else if (obj == klass_RInfo) {
2383 klass_RInfo = dst;
2384 reg_conflict = true;
2385 } else if (obj == Rtmp1) {
2386 Rtmp1 = dst;
2387 reg_conflict = true;
2388 }
2389 assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2390
2391 __ cmpdi(CCR0, obj, 0);
2392
2393 ciMethodData* md = NULL;
2394 ciProfileData* data = NULL;
2395 int mdo_offset_bias = 0;
2396 if (should_profile) {
2397 ciMethod* method = op->profiled_method();
2398 assert(method != NULL, "Should have method");
2399 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2400
2401 Register mdo = k_RInfo;
2402 Register data_val = Rtmp1;
2403 Label not_null;
2404 __ bne(CCR0, not_null);
2405 metadata2reg(md->constant_encoding(), mdo);
2406 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2407 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2408 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2409 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2410 __ b(*obj_is_null);
2411 __ bind(not_null);
2412 } else {
2413 __ beq(CCR0, *obj_is_null);
2414 }
2415
2416 // get object class
2417 __ load_klass(klass_RInfo, obj);
2418
2419 if (k->is_loaded()) {
2420 metadata2reg(k->constant_encoding(), k_RInfo);
2421 } else {
2422 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2423 }
2424
2425 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2426 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2427 Label *success_target = should_profile ? &profile_cast_success : success;
2428
2429 if (op->fast_check()) {
2430 assert_different_registers(klass_RInfo, k_RInfo);
2431 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2432 if (should_profile) {
2433 __ bne(CCR0, *failure_target);
2434 // Fall through to success case.
2435 } else {
2436 __ beq(CCR0, *success);
2437 // Fall through to failure case.
2438 }
2439 } else {
2440 bool need_slow_path = true;
2441 if (k->is_loaded()) {
2442 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2443 need_slow_path = false;
2444 }
2445 // Perform the fast part of the checking logic.
2446 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2447 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2448 } else {
2449 // Perform the fast part of the checking logic.
2450 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2451 }
2452 if (!need_slow_path) {
2453 if (!should_profile) { __ b(*success); }
2454 } else {
2455 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2456 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2457 // Stub needs fixed registers (tmp1-3).
2458 Register original_k_RInfo = op->tmp1()->as_register();
2459 Register original_klass_RInfo = op->tmp2()->as_register();
2460 Register original_Rtmp1 = op->tmp3()->as_register();
2461 bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2462 bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2463 if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2464 __ mr_if_needed(original_k_RInfo, k_RInfo);
2465 __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2466 if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2467 //__ load_const_optimized(original_Rtmp1, entry, R0);
2468 __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2469 __ mtctr(original_Rtmp1);
2470 __ bctrl(); // sets CR0
2471 if (keep_obj_alive) {
2472 if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2473 __ mr(obj, dst);
2474 }
2475 if (should_profile) {
2476 __ bne(CCR0, *failure_target);
2477 if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2478 // Fall through to success case.
2479 } else {
2480 __ beq(CCR0, *success);
2481 // Fall through to failure case.
2482 }
2483 }
2484 }
2485
2486 if (should_profile) {
2487 Register mdo = k_RInfo, recv = klass_RInfo;
2488 assert_different_registers(mdo, recv, Rtmp1);
2489 __ bind(profile_cast_success);
2490 metadata2reg(md->constant_encoding(), mdo);
2491 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2492 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2493 __ b(*success);
2494
2495 // Cast failure case.
2496 __ bind(profile_cast_failure);
2497 metadata2reg(md->constant_encoding(), mdo);
2498 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2499 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2500 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2501 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2502 }
2503
2504 __ bind(*failure);
2505 }
2506
2507
2508 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2509 LIR_Code code = op->code();
2510 if (code == lir_store_check) {
2511 Register value = op->object()->as_register();
2512 Register array = op->array()->as_register();
2513 Register k_RInfo = op->tmp1()->as_register();
2514 Register klass_RInfo = op->tmp2()->as_register();
2515 Register Rtmp1 = op->tmp3()->as_register();
2516 bool should_profile = op->should_profile();
2517
2518 __ verify_oop(value, FILE_AND_LINE);
2519 CodeStub* stub = op->stub();
2520 // Check if it needs to be profiled.
2521 ciMethodData* md = NULL;
2522 ciProfileData* data = NULL;
2523 int mdo_offset_bias = 0;
2524 if (should_profile) {
2525 ciMethod* method = op->profiled_method();
2526 assert(method != NULL, "Should have method");
2527 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2528 }
2529 Label profile_cast_success, failure, done;
2530 Label *success_target = should_profile ? &profile_cast_success : &done;
2531
2532 __ cmpdi(CCR0, value, 0);
2533 if (should_profile) {
2534 Label not_null;
2535 __ bne(CCR0, not_null);
2536 Register mdo = k_RInfo;
2537 Register data_val = Rtmp1;
2538 metadata2reg(md->constant_encoding(), mdo);
2539 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2540 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2541 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2542 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2543 __ b(done);
2544 __ bind(not_null);
2545 } else {
2546 __ beq(CCR0, done);
2547 }
2548 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2549 explicit_null_check(array, op->info_for_exception());
2550 } else {
2551 add_debug_info_for_null_check_here(op->info_for_exception());
2552 }
2553 __ load_klass(k_RInfo, array);
2554 __ load_klass(klass_RInfo, value);
2555
2556 // Get instance klass.
2557 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2558 // Perform the fast part of the checking logic.
2559 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2560
2561 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2562 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2563 //__ load_const_optimized(R0, slow_path);
2564 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2565 __ mtctr(R0);
2566 __ bctrl(); // sets CR0
2567 if (!should_profile) {
2568 __ beq(CCR0, done);
2569 __ bind(failure);
2570 } else {
2571 __ bne(CCR0, failure);
2572 // Fall through to the success case.
2573
2574 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2575 assert_different_registers(value, mdo, recv, tmp1);
2576 __ bind(profile_cast_success);
2577 metadata2reg(md->constant_encoding(), mdo);
2578 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2579 __ load_klass(recv, value);
2580 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2581 __ b(done);
2582
2583 // Cast failure case.
2584 __ bind(failure);
2585 metadata2reg(md->constant_encoding(), mdo);
2586 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2587 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2588 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2589 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2590 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2591 }
2592 __ b(*stub->entry());
2593 __ bind(done);
2594
2595 } else if (code == lir_checkcast) {
2596 Label success, failure;
2597 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2598 __ b(*op->stub()->entry());
2599 __ align(32, 12);
2600 __ bind(success);
2601 __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2602 } else if (code == lir_instanceof) {
2603 Register dst = op->result_opr()->as_register();
2604 Label success, failure, done;
2605 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2606 __ li(dst, 0);
2607 __ b(done);
2608 __ align(32, 12);
2609 __ bind(success);
2610 __ li(dst, 1);
2611 __ bind(done);
2612 } else {
2613 ShouldNotReachHere();
2614 }
2615 }
2616
2617
2618 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2619 Register addr = op->addr()->as_pointer_register();
2620 Register cmp_value = noreg, new_value = noreg;
2621 bool is_64bit = false;
2622
2623 if (op->code() == lir_cas_long) {
2624 cmp_value = op->cmp_value()->as_register_lo();
2625 new_value = op->new_value()->as_register_lo();
2626 is_64bit = true;
2627 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2628 cmp_value = op->cmp_value()->as_register();
2629 new_value = op->new_value()->as_register();
2630 if (op->code() == lir_cas_obj) {
2631 if (UseCompressedOops) {
2632 Register t1 = op->tmp1()->as_register();
2633 Register t2 = op->tmp2()->as_register();
2634 cmp_value = __ encode_heap_oop(t1, cmp_value);
2635 new_value = __ encode_heap_oop(t2, new_value);
2636 } else {
2637 is_64bit = true;
2638 }
2639 }
2640 } else {
2641 Unimplemented();
2642 }
2643
2644 if (is_64bit) {
2645 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2646 MacroAssembler::MemBarNone,
2647 MacroAssembler::cmpxchgx_hint_atomic_update(),
2648 noreg, NULL, /*check without ldarx first*/true);
2649 } else {
2650 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2651 MacroAssembler::MemBarNone,
2652 MacroAssembler::cmpxchgx_hint_atomic_update(),
2653 noreg, /*check without ldarx first*/true);
2654 }
2655
2656 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2657 __ isync();
2658 } else {
2659 __ sync();
2660 }
2661 }
2662
2663 void LIR_Assembler::breakpoint() {
2664 __ illtrap();
2665 }
2666
2667
2668 void LIR_Assembler::push(LIR_Opr opr) {
2669 Unimplemented();
2670 }
2671
2672 void LIR_Assembler::pop(LIR_Opr opr) {
2673 Unimplemented();
2674 }
2675
2676
2677 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2678 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2679 Register dst = dst_opr->as_register();
2680 Register reg = mon_addr.base();
2681 int offset = mon_addr.disp();
2682 // Compute pointer to BasicLock.
2683 __ add_const_optimized(dst, reg, offset);
2684 }
2685
2686
2687 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2688 Register obj = op->obj_opr()->as_register();
2689 Register hdr = op->hdr_opr()->as_register();
2690 Register lock = op->lock_opr()->as_register();
2691
2692 // Obj may not be an oop.
2693 if (op->code() == lir_lock) {
2694 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2695 if (!UseHeavyMonitors) {
2696 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2697 // Add debug info for NullPointerException only if one is possible.
2698 if (op->info() != NULL) {
2699 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2700 explicit_null_check(obj, op->info());
2701 } else {
2702 add_debug_info_for_null_check_here(op->info());
2703 }
2704 }
2705 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2706 } else {
2707 // always do slow locking
2708 // note: The slow locking code could be inlined here, however if we use
2709 // slow locking, speed doesn't matter anyway and this solution is
2710 // simpler and requires less duplicated code - additionally, the
2711 // slow locking code is the same in either case which simplifies
2712 // debugging.
2713 __ b(*op->stub()->entry());
2714 }
2715 } else {
2716 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2717 if (!UseHeavyMonitors) {
2718 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2719 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2720 } else {
2721 // always do slow unlocking
2722 // note: The slow unlocking code could be inlined here, however if we use
2723 // slow unlocking, speed doesn't matter anyway and this solution is
2724 // simpler and requires less duplicated code - additionally, the
2725 // slow unlocking code is the same in either case which simplifies
2726 // debugging.
2727 __ b(*op->stub()->entry());
2728 }
2729 }
2730 __ bind(*op->stub()->continuation());
2731 }
2732
2733 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2734 Register obj = op->obj()->as_pointer_register();
2735 Register result = op->result_opr()->as_pointer_register();
2736
2737 CodeEmitInfo* info = op->info();
2738 if (info != NULL) {
2739 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2740 explicit_null_check(obj, info);
2741 } else {
2742 add_debug_info_for_null_check_here(info);
2743 }
2744 }
2745
2746 if (UseCompressedClassPointers) {
2747 __ lwz(result, oopDesc::klass_offset_in_bytes(), obj);
2748 __ decode_klass_not_null(result);
2749 } else {
2750 __ ld(result, oopDesc::klass_offset_in_bytes(), obj);
2751 }
2752 }
2753
2754 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2755 ciMethod* method = op->profiled_method();
2756 int bci = op->profiled_bci();
2757 ciMethod* callee = op->profiled_callee();
2758
2759 // Update counter for all call types.
2760 ciMethodData* md = method->method_data_or_null();
2761 assert(md != NULL, "Sanity");
2762 ciProfileData* data = md->bci_to_data(bci);
2763 assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2764 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2765 Register mdo = op->mdo()->as_register();
2766 #ifdef _LP64
2767 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2768 Register tmp1 = op->tmp1()->as_register_lo();
2769 #else
2770 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2771 Register tmp1 = op->tmp1()->as_register();
2772 #endif
2773 metadata2reg(md->constant_encoding(), mdo);
2774 int mdo_offset_bias = 0;
2775 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2776 data->size_in_bytes())) {
2777 // The offset is large so bias the mdo by the base of the slot so
2778 // that the ld can use simm16s to reference the slots of the data.
2779 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2780 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2781 }
2782
2783 // Perform additional virtual call profiling for invokevirtual and
2784 // invokeinterface bytecodes
2785 if (op->should_profile_receiver_type()) {
2786 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2787 Register recv = op->recv()->as_register();
2788 assert_different_registers(mdo, tmp1, recv);
2789 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2790 ciKlass* known_klass = op->known_holder();
2791 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2792 // We know the type that will be seen at this call site; we can
2793 // statically update the MethodData* rather than needing to do
2794 // dynamic tests on the receiver type.
2795
2796 // NOTE: we should probably put a lock around this search to
2797 // avoid collisions by concurrent compilations.
2798 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2799 uint i;
2800 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2801 ciKlass* receiver = vc_data->receiver(i);
2802 if (known_klass->equals(receiver)) {
2803 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2804 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2805 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2806 return;
2807 }
2808 }
2809
2810 // Receiver type not found in profile data; select an empty slot.
2811
2812 // Note that this is less efficient than it should be because it
2813 // always does a write to the receiver part of the
2814 // VirtualCallData rather than just the first time.
2815 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2816 ciKlass* receiver = vc_data->receiver(i);
2817 if (receiver == NULL) {
2818 metadata2reg(known_klass->constant_encoding(), tmp1);
2819 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2820
2821 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2822 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2823 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2824 return;
2825 }
2826 }
2827 } else {
2828 __ load_klass(recv, recv);
2829 Label update_done;
2830 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2831 // Receiver did not match any saved receiver and there is no empty row for it.
2832 // Increment total counter to indicate polymorphic case.
2833 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2834 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2835 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2836
2837 __ bind(update_done);
2838 }
2839 } else {
2840 // Static call
2841 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2842 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2843 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2844 }
2845 }
2846
2847
2848 void LIR_Assembler::align_backward_branch_target() {
2849 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2850 }
2851
2852
2853 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2854 Unimplemented();
2855 }
2856
2857
2858 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2859 // tmp must be unused
2860 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2861 assert(left->is_register(), "can only handle registers");
2862
2863 if (left->is_single_cpu()) {
2864 __ neg(dest->as_register(), left->as_register());
2865 } else if (left->is_single_fpu()) {
2866 __ fneg(dest->as_float_reg(), left->as_float_reg());
2867 } else if (left->is_double_fpu()) {
2868 __ fneg(dest->as_double_reg(), left->as_double_reg());
2869 } else {
2870 assert (left->is_double_cpu(), "Must be a long");
2871 __ neg(dest->as_register_lo(), left->as_register_lo());
2872 }
2873 }
2874
2875
2876 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2877 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2878 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2879 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2880 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2881 //__ load_const_optimized(R0, dest);
2882 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2883 __ mtctr(R0);
2884 __ bctrl();
2885 assert(info != NULL, "sanity");
2886 add_call_info_here(info);
2887 return;
2888 }
2889
2890 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2891 if (info != NULL) {
2892 add_call_info_here(info);
2893 }
2894 }
2895
2896
2897 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2898 ShouldNotReachHere(); // Not needed on _LP64.
2899 }
2900
2901 void LIR_Assembler::membar() {
2902 __ fence();
2903 }
2904
2905 void LIR_Assembler::membar_acquire() {
2906 __ acquire();
2907 }
2908
2909 void LIR_Assembler::membar_release() {
2910 __ release();
2911 }
2912
2913 void LIR_Assembler::membar_loadload() {
2914 __ membar(Assembler::LoadLoad);
2915 }
2916
2917 void LIR_Assembler::membar_storestore() {
2918 __ membar(Assembler::StoreStore);
2919 }
2920
2921 void LIR_Assembler::membar_loadstore() {
2922 __ membar(Assembler::LoadStore);
2923 }
2924
2925 void LIR_Assembler::membar_storeload() {
2926 __ membar(Assembler::StoreLoad);
2927 }
2928
2929 void LIR_Assembler::on_spin_wait() {
2930 Unimplemented();
2931 }
2932
2933 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2934 LIR_Address* addr = addr_opr->as_address_ptr();
2935 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2936
2937 if (addr->index()->is_illegal()) {
2938 if (patch_code != lir_patch_none) {
2939 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::access_field_id);
2940 __ load_const32(R0, 0); // patchable int
2941 __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), R0);
2942 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
2943 } else {
2944 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2945 }
2946 } else {
2947 assert(patch_code == lir_patch_none, "Patch code not supported");
2948 assert(addr->disp() == 0, "can't have both: index and disp");
2949 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2950 }
2951 }
2952
2953
2954 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2955 ShouldNotReachHere();
2956 }
2957
2958
2959 #ifdef ASSERT
2960 // Emit run-time assertion.
2961 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2962 Unimplemented();
2963 }
2964 #endif
2965
2966
2967 void LIR_Assembler::peephole(LIR_List* lir) {
2968 // Optimize instruction pairs before emitting.
2969 LIR_OpList* inst = lir->instructions_list();
2970 for (int i = 1; i < inst->length(); i++) {
2971 LIR_Op* op = inst->at(i);
2972
2973 // 2 register-register-moves
2974 if (op->code() == lir_move) {
2975 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2976 res2 = ((LIR_Op1*)op)->result_opr();
2977 if (in2->is_register() && res2->is_register()) {
2978 LIR_Op* prev = inst->at(i - 1);
2979 if (prev && prev->code() == lir_move) {
2980 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2981 res1 = ((LIR_Op1*)prev)->result_opr();
2982 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2983 inst->remove_at(i);
2984 }
2985 }
2986 }
2987 }
2988
2989 }
2990 return;
2991 }
2992
2993
2994 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2995 const LIR_Address *addr = src->as_address_ptr();
2996 assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2997 const Register Rptr = addr->base()->as_pointer_register(),
2998 Rtmp = tmp->as_register();
2999 Register Rco = noreg;
3000 if (UseCompressedOops && data->is_oop()) {
3001 Rco = __ encode_heap_oop(Rtmp, data->as_register());
3002 }
3003
3004 Label Lretry;
3005 __ bind(Lretry);
3006
3007 if (data->type() == T_INT) {
3008 const Register Rold = dest->as_register(),
3009 Rsrc = data->as_register();
3010 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3011 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3012 if (code == lir_xadd) {
3013 __ add(Rtmp, Rsrc, Rold);
3014 __ stwcx_(Rtmp, Rptr);
3015 } else {
3016 __ stwcx_(Rsrc, Rptr);
3017 }
3018 } else if (data->is_oop()) {
3019 assert(code == lir_xchg, "xadd for oops");
3020 const Register Rold = dest->as_register();
3021 if (UseCompressedOops) {
3022 assert_different_registers(Rptr, Rold, Rco);
3023 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3024 __ stwcx_(Rco, Rptr);
3025 } else {
3026 const Register Robj = data->as_register();
3027 assert_different_registers(Rptr, Rold, Robj);
3028 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3029 __ stdcx_(Robj, Rptr);
3030 }
3031 } else if (data->type() == T_LONG) {
3032 const Register Rold = dest->as_register_lo(),
3033 Rsrc = data->as_register_lo();
3034 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3035 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3036 if (code == lir_xadd) {
3037 __ add(Rtmp, Rsrc, Rold);
3038 __ stdcx_(Rtmp, Rptr);
3039 } else {
3040 __ stdcx_(Rsrc, Rptr);
3041 }
3042 } else {
3043 ShouldNotReachHere();
3044 }
3045
3046 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3047 __ bne_predict_not_taken(CCR0, Lretry);
3048 } else {
3049 __ bne( CCR0, Lretry);
3050 }
3051
3052 if (UseCompressedOops && data->is_oop()) {
3053 __ decode_heap_oop(dest->as_register());
3054 }
3055 }
3056
3057
3058 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3059 Register obj = op->obj()->as_register();
3060 Register tmp = op->tmp()->as_pointer_register();
3061 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3062 ciKlass* exact_klass = op->exact_klass();
3063 intptr_t current_klass = op->current_klass();
3064 bool not_null = op->not_null();
3065 bool no_conflict = op->no_conflict();
3066
3067 Label Lupdate, Ldo_update, Ldone;
3068
3069 bool do_null = !not_null;
3070 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3071 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3072
3073 assert(do_null || do_update, "why are we here?");
3074 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3075
3076 __ verify_oop(obj, FILE_AND_LINE);
3077
3078 if (do_null) {
3079 if (!TypeEntries::was_null_seen(current_klass)) {
3080 __ cmpdi(CCR0, obj, 0);
3081 __ bne(CCR0, Lupdate);
3082 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3083 __ ori(R0, R0, TypeEntries::null_seen);
3084 if (do_update) {
3085 __ b(Ldo_update);
3086 } else {
3087 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3088 }
3089 } else {
3090 if (do_update) {
3091 __ cmpdi(CCR0, obj, 0);
3092 __ beq(CCR0, Ldone);
3093 }
3094 }
3095 #ifdef ASSERT
3096 } else {
3097 __ cmpdi(CCR0, obj, 0);
3098 __ bne(CCR0, Lupdate);
3099 __ stop("unexpect null obj");
3100 #endif
3101 }
3102
3103 __ bind(Lupdate);
3104 if (do_update) {
3105 Label Lnext;
3106 const Register klass = R29_TOC; // kill and reload
3107 bool klass_reg_used = false;
3108 #ifdef ASSERT
3109 if (exact_klass != NULL) {
3110 Label ok;
3111 klass_reg_used = true;
3112 __ load_klass(klass, obj);
3113 metadata2reg(exact_klass->constant_encoding(), R0);
3114 __ cmpd(CCR0, klass, R0);
3115 __ beq(CCR0, ok);
3116 __ stop("exact klass and actual klass differ");
3117 __ bind(ok);
3118 }
3119 #endif
3120
3121 if (!no_conflict) {
3122 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3123 klass_reg_used = true;
3124 if (exact_klass != NULL) {
3125 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3126 metadata2reg(exact_klass->constant_encoding(), klass);
3127 } else {
3128 __ load_klass(klass, obj);
3129 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3130 }
3131
3132 // Like InterpreterMacroAssembler::profile_obj_type
3133 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3134 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3135 __ cmpd(CCR1, R0, klass);
3136 // Klass seen before, nothing to do (regardless of unknown bit).
3137 //beq(CCR1, do_nothing);
3138
3139 __ andi_(R0, klass, TypeEntries::type_unknown);
3140 // Already unknown. Nothing to do anymore.
3141 //bne(CCR0, do_nothing);
3142 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3143 __ beq(CCR0, Lnext);
3144
3145 if (TypeEntries::is_type_none(current_klass)) {
3146 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3147 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3148 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3149 }
3150
3151 } else {
3152 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3153 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3154
3155 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3156 __ andi_(R0, tmp, TypeEntries::type_unknown);
3157 // Already unknown. Nothing to do anymore.
3158 __ bne(CCR0, Lnext);
3159 }
3160
3161 // Different than before. Cannot keep accurate profile.
3162 __ ori(R0, tmp, TypeEntries::type_unknown);
3163 } else {
3164 // There's a single possible klass at this profile point
3165 assert(exact_klass != NULL, "should be");
3166 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3167
3168 if (TypeEntries::is_type_none(current_klass)) {
3169 klass_reg_used = true;
3170 metadata2reg(exact_klass->constant_encoding(), klass);
3171
3172 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3173 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3174 __ cmpd(CCR1, R0, klass);
3175 // Klass seen before, nothing to do (regardless of unknown bit).
3176 __ beq(CCR1, Lnext);
3177 #ifdef ASSERT
3178 {
3179 Label ok;
3180 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3181 __ beq(CCR0, ok); // First time here.
3182
3183 __ stop("unexpected profiling mismatch");
3184 __ bind(ok);
3185 }
3186 #endif
3187 // First time here. Set profile type.
3188 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3189 } else {
3190 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3191 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3192
3193 // Already unknown. Nothing to do anymore.
3194 __ andi_(R0, tmp, TypeEntries::type_unknown);
3195 __ bne(CCR0, Lnext);
3196
3197 // Different than before. Cannot keep accurate profile.
3198 __ ori(R0, tmp, TypeEntries::type_unknown);
3199 }
3200 }
3201
3202 __ bind(Ldo_update);
3203 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3204
3205 __ bind(Lnext);
3206 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3207 }
3208 __ bind(Ldone);
3209 }
3210
3211
3212 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3213 assert(op->crc()->is_single_cpu(), "crc must be register");
3214 assert(op->val()->is_single_cpu(), "byte value must be register");
3215 assert(op->result_opr()->is_single_cpu(), "result must be register");
3216 Register crc = op->crc()->as_register();
3217 Register val = op->val()->as_register();
3218 Register res = op->result_opr()->as_register();
3219
3220 assert_different_registers(val, crc, res);
3221
3222 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3223 __ kernel_crc32_singleByteReg(crc, val, res, true);
3224 __ mr(res, crc);
3225 }
3226
3227 #undef __