1 /*
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 3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
 4  * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
 5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 7  * This code is free software; you can redistribute it and/or modify it
 8  * under the terms of the GNU General Public License version 2 only, as
 9  * published by the Free Software Foundation.
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12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14  * version 2 for more details (a copy is included in the LICENSE file that
15  * accompanied this code).
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17  * You should have received a copy of the GNU General Public License version
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19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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26 
27 #ifndef CPU_RISCV_C1_DEFS_RISCV_HPP
28 #define CPU_RISCV_C1_DEFS_RISCV_HPP
29 
30 // native word offsets from memory address (little endian)
31 enum {
32   pd_lo_word_offset_in_bytes = 0,
33   pd_hi_word_offset_in_bytes = BytesPerWord
34 };
35 
36 // explicit rounding operations are required to implement the strictFP mode
37 enum {
38   pd_strict_fp_requires_explicit_rounding = false
39 };
40 
41 // registers
42 enum {
43   pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
44   pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of float registers used during code emission
45 
46   // caller saved
47   pd_nof_caller_save_cpu_regs_frame_map = 14, // number of registers killed by calls
48   pd_nof_caller_save_fpu_regs_frame_map = 32, // number of float registers killed by calls
49 
50   pd_first_callee_saved_reg = pd_nof_caller_save_cpu_regs_frame_map,
51   pd_last_callee_saved_reg = 22,
52 
53   pd_last_allocatable_cpu_reg = pd_nof_caller_save_cpu_regs_frame_map - 1,
54 
55   pd_nof_cpu_regs_reg_alloc
56     = pd_nof_caller_save_cpu_regs_frame_map,  // number of registers that are visible to register allocator
57   pd_nof_fpu_regs_reg_alloc = 32,  // number of float registers that are visible to register allocator
58 
59   pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan
60   pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of float registers visible to linear scan
61   pd_nof_xmm_regs_linearscan = 0, // don't have vector registers
62 
63   pd_first_cpu_reg  = 0,
64   pd_last_cpu_reg   = pd_nof_cpu_regs_reg_alloc - 1,
65   pd_first_byte_reg = 0,
66   pd_last_byte_reg  = pd_nof_cpu_regs_reg_alloc - 1,
67 
68   pd_first_fpu_reg  = pd_nof_cpu_regs_frame_map,
69   pd_last_fpu_reg   = pd_first_fpu_reg + 31,
70 
71   pd_first_callee_saved_fpu_reg_1 = 8 + pd_first_fpu_reg,
72   pd_last_callee_saved_fpu_reg_1  = 9 + pd_first_fpu_reg,
73   pd_first_callee_saved_fpu_reg_2 = 18 + pd_first_fpu_reg,
74   pd_last_callee_saved_fpu_reg_2  = 27 + pd_first_fpu_reg
75 };
76 
77 
78 // Encoding of float value in debug info.  This is true on x86 where
79 // floats are extended to doubles when stored in the stack, false for
80 // RISCV64 where floats and doubles are stored in their native form.
81 enum {
82   pd_float_saved_as_double = false
83 };
84 
85 #endif // CPU_RISCV_C1_DEFS_RISCV_HPP