1 /*
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 4  * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
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26 
27 #ifndef CPU_RISCV_DISASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_DISASSEMBLER_RISCV_HPP
29 
30 static int pd_instruction_alignment() {
31   return 1;
32 }
33 
34 static const char* pd_cpu_opts() {
35   return "";
36 }
37 
38 // Returns address of n-th instruction preceding addr,
39 // NULL if no preceding instruction can be found.
40 // On riscv, we assume a constant instruction length.
41 // It might be beneficial to check "is_readable" as we do on ppc and s390.
42 static address find_prev_instr(address addr, int n_instr) {
43   return addr - Assembler::instruction_size * n_instr;
44 }
45 
46 // special-case instruction decoding.
47 // There may be cases where the binutils disassembler doesn't do
48 // the perfect job. In those cases, decode_instruction0 may kick in
49 // and do it right.
50 // If nothing had to be done, just return "here", otherwise return "here + instr_len(here)"
51 static address decode_instruction0(address here, outputStream* st, address virtual_begin = NULL) {
52   return here;
53 }
54 
55 // platform-specific instruction annotations (like value of loaded constants)
56 static void annotate(address pc, outputStream* st) {}
57 
58 #endif // CPU_RISCV_DISASSEMBLER_RISCV_HPP