1 /*
  2  * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved.
  3  * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
  4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  5  *
  6  * This code is free software; you can redistribute it and/or modify it
  7  * under the terms of the GNU General Public License version 2 only, as
  8  * published by the Free Software Foundation.
  9  *
 10  * This code is distributed in the hope that it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13  * version 2 for more details (a copy is included in the LICENSE file that
 14  * accompanied this code).
 15  *
 16  * You should have received a copy of the GNU General Public License version
 17  * 2 along with this work; if not, write to the Free Software Foundation,
 18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 19  *
 20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 21  * or visit www.oracle.com if you need additional information or have any
 22  * questions.
 23  */
 24 
 25 #ifndef CPU_RISCV64_GC_Z_ZBARRIERSETASSEMBLER_RISCV_HPP
 26 #define CPU_RISCV64_GC_Z_ZBARRIERSETASSEMBLER_RISCV_HPP
 27 
 28 #include "code/vmreg.hpp"
 29 #include "oops/accessDecorators.hpp"
 30 #ifdef COMPILER2
 31 #include "opto/optoreg.hpp"
 32 #endif // COMPILER2
 33 
 34 #ifdef COMPILER1
 35 class LIR_Assembler;
 36 class LIR_OprDesc;
 37 typedef LIR_OprDesc* LIR_Opr;
 38 class StubAssembler;
 39 class ZLoadBarrierStubC1;
 40 #endif // COMPILER1
 41 
 42 #ifdef COMPILER2
 43 class Node;
 44 class ZLoadBarrierStubC2;
 45 #endif // COMPILER2
 46 
 47 class ZBarrierSetAssembler : public ZBarrierSetAssemblerBase {
 48 public:
 49   virtual void load_at(MacroAssembler* masm,
 50                        DecoratorSet decorators,
 51                        BasicType type,
 52                        Register dst,
 53                        Address src,
 54                        Register tmp1,
 55                        Register tmp_thread);
 56 
 57 #ifdef ASSERT
 58   virtual void store_at(MacroAssembler* masm,
 59                         DecoratorSet decorators,
 60                         BasicType type,
 61                         Address dst,
 62                         Register val,
 63                         Register tmp1,
 64                         Register tmp2);
 65 #endif // ASSERT
 66 
 67   virtual void arraycopy_prologue(MacroAssembler* masm,
 68                                   DecoratorSet decorators,
 69                                   bool is_oop,
 70                                   Register src,
 71                                   Register dst,
 72                                   Register count,
 73                                   RegSet saved_regs);
 74 
 75   virtual void try_resolve_jobject_in_native(MacroAssembler* masm,
 76                                              Register jni_env,
 77                                              Register robj,
 78                                              Register tmp,
 79                                              Label& slowpath);
 80 
 81 #ifdef COMPILER1
 82   void generate_c1_load_barrier_test(LIR_Assembler* ce,
 83                                      LIR_Opr ref) const;
 84 
 85   void generate_c1_load_barrier_stub(LIR_Assembler* ce,
 86                                      ZLoadBarrierStubC1* stub) const;
 87 
 88   void generate_c1_load_barrier_runtime_stub(StubAssembler* sasm,
 89                                              DecoratorSet decorators) const;
 90 #endif // COMPILER1
 91 
 92 #ifdef COMPILER2
 93   OptoReg::Name refine_register(const Node* node,
 94                                 OptoReg::Name opto_reg);
 95 
 96   void generate_c2_load_barrier_stub(MacroAssembler* masm,
 97                                      ZLoadBarrierStubC2* stub) const;
 98 #endif // COMPILER2
 99 };
100 
101 #endif // CPU_RISCV64_GC_Z_ZBARRIERSETASSEMBLER_RISCV_HPP