1 //
    2 // Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
    4 // Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
    5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    6 //
    7 // This code is free software; you can redistribute it and/or modify it
    8 // under the terms of the GNU General Public License version 2 only, as
    9 // published by the Free Software Foundation.
   10 //
   11 // This code is distributed in the hope that it will be useful, but WITHOUT
   12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   14 // version 2 for more details (a copy is included in the LICENSE file that
   15 // accompanied this code).
   16 //
   17 // You should have received a copy of the GNU General Public License version
   18 // 2 along with this work; if not, write to the Free Software Foundation,
   19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   20 //
   21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   22 // or visit www.oracle.com if you need additional information or have any
   23 // questions.
   24 //
   25 //
   26 
   27 // RISCV64 Architecture Description File
   28 
   29 //----------REGISTER DEFINITION BLOCK------------------------------------------
   30 // This information is used by the matcher and the register allocator to
   31 // describe individual registers and classes of registers within the target
   32 // archtecture.
   33 
   34 register %{
   35 //----------Architecture Description Register Definitions----------------------
   36 // General Registers
   37 // "reg_def"  name ( register save type, C convention save type,
   38 //                   ideal register type, encoding );
   39 // Register Save Types:
   40 //
   41 // NS  = No-Save:       The register allocator assumes that these registers
   42 //                      can be used without saving upon entry to the method, &
   43 //                      that they do not need to be saved at call sites.
   44 //
   45 // SOC = Save-On-Call:  The register allocator assumes that these registers
   46 //                      can be used without saving upon entry to the method,
   47 //                      but that they must be saved at call sites.
   48 //
   49 // SOE = Save-On-Entry: The register allocator assumes that these registers
   50 //                      must be saved before using them upon entry to the
   51 //                      method, but they do not need to be saved at call
   52 //                      sites.
   53 //
   54 // AS  = Always-Save:   The register allocator assumes that these registers
   55 //                      must be saved before using them upon entry to the
   56 //                      method, & that they must be saved at call sites.
   57 //
   58 // Ideal Register Type is used to determine how to save & restore a
   59 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   60 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   61 //
   62 // The encoding number is the actual bit-pattern placed into the opcodes.
   63 
   64 // We must define the 64 bit int registers in two 32 bit halves, the
   65 // real lower register and a virtual upper half register. upper halves
   66 // are used by the register allocator but are not actually supplied as
   67 // operands to memory ops.
   68 //
   69 // follow the C1 compiler in making registers
   70 //
   71 //   x7, x9-x17, x28-x31 volatile (caller save)
   72 //   x0-x4, x8, x27 system (no save, no allocate)
   73 //   x5-x6 non-allocatable (so we can use them as temporary regs)
   74 
   75 //
   76 // as regards Java usage. we don't use any callee save registers
   77 // because this makes it difficult to de-optimise a frame (see comment
   78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
   79 //
   80 
   81 // General Registers
   82 
   83 reg_def R0      ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()         ); // zr
   84 reg_def R0_H    ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()->next() );
   85 reg_def R1      ( SOC, SOC, Op_RegI, 1,  x1->as_VMReg()         ); // lr
   86 reg_def R1_H    ( SOC, SOC, Op_RegI, 1,  x1->as_VMReg()->next() );
   87 reg_def R2      ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()         ); // sp
   88 reg_def R2_H    ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()->next() );
   89 reg_def R3      ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()         ); // gp
   90 reg_def R3_H    ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()->next() );
   91 reg_def R4      ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()         ); // tp
   92 reg_def R4_H    ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()->next() );
   93 reg_def R5      ( NS,  SOC, Op_RegI, 5,  x5->as_VMReg()         ); // t0, non-allocatable
   94 reg_def R5_H    ( NS,  SOC, Op_RegI, 5,  x5->as_VMReg()->next() );
   95 reg_def R6      ( SOC, SOC, Op_RegI, 6,  x6->as_VMReg()         ); // t1, non-allocatable
   96 reg_def R6_H    ( SOC, SOC, Op_RegI, 6,  x6->as_VMReg()->next() );
   97 reg_def R7      ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()         );
   98 reg_def R7_H    ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()->next() );
   99 reg_def R8      ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()         ); // fp
  100 reg_def R8_H    ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()->next() );
  101 reg_def R9      ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()         );
  102 reg_def R9_H    ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()->next() );
  103 reg_def R10     ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()        );
  104 reg_def R10_H   ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
  105 reg_def R11     ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()        );
  106 reg_def R11_H   ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
  107 reg_def R12     ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()        );
  108 reg_def R12_H   ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
  109 reg_def R13     ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()        );
  110 reg_def R13_H   ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
  111 reg_def R14     ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()        );
  112 reg_def R14_H   ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
  113 reg_def R15     ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()        );
  114 reg_def R15_H   ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
  115 reg_def R16     ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()        );
  116 reg_def R16_H   ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
  117 reg_def R17     ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()        );
  118 reg_def R17_H   ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
  119 reg_def R18     ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()        );
  120 reg_def R18_H   ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
  121 reg_def R19     ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()        );
  122 reg_def R19_H   ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
  123 reg_def R20     ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()        ); // caller esp
  124 reg_def R20_H   ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
  125 reg_def R21     ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()        );
  126 reg_def R21_H   ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
  127 reg_def R22     ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()        );
  128 reg_def R22_H   ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
  129 reg_def R23     ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()        ); // java thread
  130 reg_def R23_H   ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()->next());
  131 reg_def R24     ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()        );
  132 reg_def R24_H   ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
  133 reg_def R25     ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()        );
  134 reg_def R25_H   ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
  135 reg_def R26     ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()        );
  136 reg_def R26_H   ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
  137 reg_def R27     ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()        ); // heapbase
  138 reg_def R27_H   ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
  139 reg_def R28     ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()        );
  140 reg_def R28_H   ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
  141 reg_def R29     ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()        );
  142 reg_def R29_H   ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
  143 reg_def R30     ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()        );
  144 reg_def R30_H   ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
  145 reg_def R31     ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()        );
  146 reg_def R31_H   ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
  147 
  148 // ----------------------------
  149 // Float/Double Registers
  150 // ----------------------------
  151 
  152 // Double Registers
  153 
  154 // The rules of ADL require that double registers be defined in pairs.
  155 // Each pair must be two 32-bit values, but not necessarily a pair of
  156 // single float registers. In each pair, ADLC-assigned register numbers
  157 // must be adjacent, with the lower number even. Finally, when the
  158 // CPU stores such a register pair to memory, the word associated with
  159 // the lower ADLC-assigned number must be stored to the lower address.
  160 
  161 // RISCV64 has 32 floating-point registers. Each can store a single
  162 // or double precision floating-point value.
  163 
  164 // for Java use float registers v0-v15 are always save on call whereas
  165 // the platform ABI treats v8-v15 as callee save). float registers
  166 // v16-v31 are SOC as per the platform spec
  167 
  168 reg_def F0    ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()          );
  169 reg_def F0_H  ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()->next()  );
  170 reg_def F1    ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()          );
  171 reg_def F1_H  ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()->next()  );
  172 reg_def F2    ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()          );
  173 reg_def F2_H  ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()->next()  );
  174 reg_def F3    ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()          );
  175 reg_def F3_H  ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()->next()  );
  176 reg_def F4    ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()          );
  177 reg_def F4_H  ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()->next()  );
  178 reg_def F5    ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()          );
  179 reg_def F5_H  ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()->next()  );
  180 reg_def F6    ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()          );
  181 reg_def F6_H  ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()->next()  );
  182 reg_def F7    ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()          );
  183 reg_def F7_H  ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()->next()  );
  184 reg_def F8    ( SOC, SOC, Op_RegF,  8,  f8->as_VMReg()          );
  185 reg_def F8_H  ( SOC, SOC, Op_RegF,  8,  f8->as_VMReg()->next()  );
  186 reg_def F9    ( SOC, SOC, Op_RegF,  9,  f9->as_VMReg()          );
  187 reg_def F9_H  ( SOC, SOC, Op_RegF,  9,  f9->as_VMReg()->next()  );
  188 reg_def F10   ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()         );
  189 reg_def F10_H ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()->next() );
  190 reg_def F11   ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()         );
  191 reg_def F11_H ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()->next() );
  192 reg_def F12   ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()         );
  193 reg_def F12_H ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()->next() );
  194 reg_def F13   ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()         );
  195 reg_def F13_H ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()->next() );
  196 reg_def F14   ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()         );
  197 reg_def F14_H ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()->next() );
  198 reg_def F15   ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()         );
  199 reg_def F15_H ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()->next() );
  200 reg_def F16   ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()         );
  201 reg_def F16_H ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()->next() );
  202 reg_def F17   ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()         );
  203 reg_def F17_H ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()->next() );
  204 reg_def F18   ( SOC, SOC, Op_RegF,  18, f18->as_VMReg()         );
  205 reg_def F18_H ( SOC, SOC, Op_RegF,  18, f18->as_VMReg()->next() );
  206 reg_def F19   ( SOC, SOC, Op_RegF,  19, f19->as_VMReg()         );
  207 reg_def F19_H ( SOC, SOC, Op_RegF,  19, f19->as_VMReg()->next() );
  208 reg_def F20   ( SOC, SOC, Op_RegF,  20, f20->as_VMReg()         );
  209 reg_def F20_H ( SOC, SOC, Op_RegF,  20, f20->as_VMReg()->next() );
  210 reg_def F21   ( SOC, SOC, Op_RegF,  21, f21->as_VMReg()         );
  211 reg_def F21_H ( SOC, SOC, Op_RegF,  21, f21->as_VMReg()->next() );
  212 reg_def F22   ( SOC, SOC, Op_RegF,  22, f22->as_VMReg()         );
  213 reg_def F22_H ( SOC, SOC, Op_RegF,  22, f22->as_VMReg()->next() );
  214 reg_def F23   ( SOC, SOC, Op_RegF,  23, f23->as_VMReg()         );
  215 reg_def F23_H ( SOC, SOC, Op_RegF,  23, f23->as_VMReg()->next() );
  216 reg_def F24   ( SOC, SOC, Op_RegF,  24, f24->as_VMReg()         );
  217 reg_def F24_H ( SOC, SOC, Op_RegF,  24, f24->as_VMReg()->next() );
  218 reg_def F25   ( SOC, SOC, Op_RegF,  25, f25->as_VMReg()         );
  219 reg_def F25_H ( SOC, SOC, Op_RegF,  25, f25->as_VMReg()->next() );
  220 reg_def F26   ( SOC, SOC, Op_RegF,  26, f26->as_VMReg()         );
  221 reg_def F26_H ( SOC, SOC, Op_RegF,  26, f26->as_VMReg()->next() );
  222 reg_def F27   ( SOC, SOC, Op_RegF,  27, f27->as_VMReg()         );
  223 reg_def F27_H ( SOC, SOC, Op_RegF,  27, f27->as_VMReg()->next() );
  224 reg_def F28   ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()         );
  225 reg_def F28_H ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()->next() );
  226 reg_def F29   ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()         );
  227 reg_def F29_H ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()->next() );
  228 reg_def F30   ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()         );
  229 reg_def F30_H ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()->next() );
  230 reg_def F31   ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()         );
  231 reg_def F31_H ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()->next() );
  232 
  233 // ----------------------------
  234 // Vector Registers
  235 // ----------------------------
  236 
  237 // For RVV vector registers, we simply extend vector register size to 4
  238 // 'logical' slots. This is nominally 128 bits but it actually covers
  239 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
  240 // bits. The 'physical' RVV vector register length is detected during
  241 // startup, so the register allocator is able to identify the correct
  242 // number of bytes needed for an RVV spill/unspill.
  243 
  244 reg_def V0    ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()           );
  245 reg_def V0_H  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next()   );
  246 reg_def V0_J  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(2)  );
  247 reg_def V0_K  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(3)  );
  248 
  249 reg_def V1    ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg() 	        );
  250 reg_def V1_H  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next()   );
  251 reg_def V1_J  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(2)  );
  252 reg_def V1_K  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(3)  );
  253 
  254 reg_def V2    ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()           );
  255 reg_def V2_H  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next()   );
  256 reg_def V2_J  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(2)  );
  257 reg_def V2_K  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(3)  );
  258 
  259 reg_def V3    ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()           );
  260 reg_def V3_H  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next()   );
  261 reg_def V3_J  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(2)  );
  262 reg_def V3_K  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(3)  );
  263 
  264 reg_def V4    ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()           );
  265 reg_def V4_H  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next()   );
  266 reg_def V4_J  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(2)  );
  267 reg_def V4_K  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(3)  );
  268 
  269 reg_def V5    ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg() 	        );
  270 reg_def V5_H  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next()   );
  271 reg_def V5_J  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(2)  );
  272 reg_def V5_K  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(3)  );
  273 
  274 reg_def V6    ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()           );
  275 reg_def V6_H  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next()   );
  276 reg_def V6_J  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(2)  );
  277 reg_def V6_K  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(3)  );
  278 
  279 reg_def V7    ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg() 	        );
  280 reg_def V7_H  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next()   );
  281 reg_def V7_J  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(2)  );
  282 reg_def V7_K  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(3)  );
  283 
  284 reg_def V8    ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()           );
  285 reg_def V8_H  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next()   );
  286 reg_def V8_J  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(2)  );
  287 reg_def V8_K  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(3)  );
  288 
  289 reg_def V9    ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()           );
  290 reg_def V9_H  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next()   );
  291 reg_def V9_J  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(2)  );
  292 reg_def V9_K  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(3)  );
  293 
  294 reg_def V10   ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()          );
  295 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next()  );
  296 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
  297 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
  298 
  299 reg_def V11   ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()          );
  300 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next()  );
  301 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
  302 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
  303 
  304 reg_def V12   ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()          );
  305 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next()  );
  306 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
  307 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
  308 
  309 reg_def V13   ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()          );
  310 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next()  );
  311 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
  312 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
  313 
  314 reg_def V14   ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()          );
  315 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next()  );
  316 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
  317 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
  318 
  319 reg_def V15   ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()          );
  320 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next()  );
  321 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
  322 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
  323 
  324 reg_def V16   ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()          );
  325 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next()  );
  326 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
  327 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
  328 
  329 reg_def V17   ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()          );
  330 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next()  );
  331 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
  332 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
  333 
  334 reg_def V18   ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()          );
  335 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next()  );
  336 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
  337 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
  338 
  339 reg_def V19   ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()          );
  340 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next()  );
  341 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
  342 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
  343 
  344 reg_def V20   ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()          );
  345 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next()  );
  346 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
  347 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
  348 
  349 reg_def V21   ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()          );
  350 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next()  );
  351 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
  352 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
  353 
  354 reg_def V22   ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()          );
  355 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next()  );
  356 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
  357 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
  358 
  359 reg_def V23   ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()          );
  360 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next()  );
  361 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
  362 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
  363 
  364 reg_def V24   ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()          );
  365 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next()  );
  366 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
  367 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
  368 
  369 reg_def V25   ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()          );
  370 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next()  );
  371 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
  372 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
  373 
  374 reg_def V26   ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()          );
  375 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next()  );
  376 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
  377 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
  378 
  379 reg_def V27   ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()          );
  380 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next()  );
  381 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
  382 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
  383 
  384 reg_def V28   ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()          );
  385 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next()  );
  386 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
  387 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
  388 
  389 reg_def V29   ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()          );
  390 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next()  );
  391 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
  392 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
  393 
  394 reg_def V30   ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()          );
  395 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next()  );
  396 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
  397 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
  398 
  399 reg_def V31   ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()          );
  400 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next()  );
  401 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
  402 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
  403 
  404 // Specify priority of register selection within phases of register
  405 // allocation.  Highest priority is first.  A useful heuristic is to
  406 // give registers a low priority when they are required by machine
  407 // instructions, like EAX and EDX on I486, and choose no-save registers
  408 // before save-on-call, & save-on-call before save-on-entry.  Registers
  409 // which participate in fixed calling sequences should come last.
  410 // Registers which are used as pairs must fall on an even boundary.
  411 
  412 alloc_class chunk0(
  413     // volatiles
  414     R7,  R7_H,
  415     R28, R28_H,
  416     R29, R29_H,
  417     R30, R30_H,
  418     R31, R31_H,
  419 
  420     // arg registers
  421     R10, R10_H,
  422     R11, R11_H,
  423     R12, R12_H,
  424     R13, R13_H,
  425     R14, R14_H,
  426     R15, R15_H,
  427     R16, R16_H,
  428     R17, R17_H,
  429 
  430     // non-volatiles
  431     R9,  R9_H,
  432     R18, R18_H,
  433     R19, R19_H,
  434     R20, R20_H,
  435     R21, R21_H,
  436     R22, R22_H,
  437     R24, R24_H,
  438     R25, R25_H,
  439     R26, R26_H,
  440 
  441     // non-allocatable registers
  442     R23, R23_H, // java thread
  443     R27, R27_H, // heapbase
  444     R4,  R4_H,  // thread
  445     R8,  R8_H,  // fp
  446     R0,  R0_H,  // zero
  447     R1,  R1_H,  // lr
  448     R2,  R2_H,  // sp
  449     R3,  R3_H,  // gp
  450     R5,  R5_H,  // t0
  451     R6,  R6_H,  // t1
  452 );
  453 
  454 alloc_class chunk1(
  455 
  456     // no save
  457     F0,  F0_H,
  458     F1,  F1_H,
  459     F2,  F2_H,
  460     F3,  F3_H,
  461     F4,  F4_H,
  462     F5,  F5_H,
  463     F6,  F6_H,
  464     F7,  F7_H,
  465     F28, F28_H,
  466     F29, F29_H,
  467     F30, F30_H,
  468     F31, F31_H,
  469 
  470     // arg registers
  471     F10, F10_H,
  472     F11, F11_H,
  473     F12, F12_H,
  474     F13, F13_H,
  475     F14, F14_H,
  476     F15, F15_H,
  477     F16, F16_H,
  478     F17, F17_H,
  479 
  480     // non-volatiles
  481     F8,  F8_H,
  482     F9,  F9_H,
  483     F18, F18_H,
  484     F19, F19_H,
  485     F20, F20_H,
  486     F21, F21_H,
  487     F22, F22_H,
  488     F23, F23_H,
  489     F24, F24_H,
  490     F25, F25_H,
  491     F26, F26_H,
  492     F27, F27_H,
  493 );
  494 
  495 alloc_class chunk2(
  496     V0, V0_H, V0_J, V0_K,
  497     V1, V1_H, V1_J, V1_K,
  498     V2, V2_H, V2_J, V2_K,
  499     V3, V3_H, V3_J, V3_K,
  500     V4, V4_H, V4_J, V4_K,
  501     V5, V5_H, V5_J, V5_K,
  502     V6, V6_H, V6_J, V6_K,
  503     V7, V7_H, V7_J, V7_K,
  504     V8, V8_H, V8_J, V8_K,
  505     V9, V9_H, V9_J, V9_K,
  506     V10, V10_H, V10_J, V10_K,
  507     V11, V11_H, V11_J, V11_K,
  508     V12, V12_H, V12_J, V12_K,
  509     V13, V13_H, V13_J, V13_K,
  510     V14, V14_H, V14_J, V14_K,
  511     V15, V15_H, V15_J, V15_K,
  512     V16, V16_H, V16_J, V16_K,
  513     V17, V17_H, V17_J, V17_K,
  514     V18, V18_H, V18_J, V18_K,
  515     V19, V19_H, V19_J, V19_K,
  516     V20, V20_H, V20_J, V20_K,
  517     V21, V21_H, V21_J, V21_K,
  518     V22, V22_H, V22_J, V22_K,
  519     V23, V23_H, V23_J, V23_K,
  520     V24, V24_H, V24_J, V24_K,
  521     V25, V25_H, V25_J, V25_K,
  522     V26, V26_H, V26_J, V26_K,
  523     V27, V27_H, V27_J, V27_K,
  524     V28, V28_H, V28_J, V28_K,
  525     V29, V29_H, V29_J, V29_K,
  526     V30, V30_H, V30_J, V30_K,
  527     V31, V31_H, V31_J, V31_K,
  528 );
  529 
  530 //----------Architecture Description Register Classes--------------------------
  531 // Several register classes are automatically defined based upon information in
  532 // this architecture description.
  533 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  534 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  535 //
  536 
  537 // Class for all 32 bit general purpose registers
  538 reg_class all_reg32(
  539     R0,
  540     R1,
  541     R2,
  542     R3,
  543     R4,
  544     R7,
  545     R8,
  546     R9,
  547     R10,
  548     R11,
  549     R12,
  550     R13,
  551     R14,
  552     R15,
  553     R16,
  554     R17,
  555     R18,
  556     R19,
  557     R20,
  558     R21,
  559     R22,
  560     R23,
  561     R24,
  562     R25,
  563     R26,
  564     R27,
  565     R28,
  566     R29,
  567     R30,
  568     R31
  569 );
  570 
  571 // Class for any 32 bit integer registers (excluding zr)
  572 reg_class any_reg32 %{
  573   return _ANY_REG32_mask;
  574 %}
  575 
  576 // Singleton class for R10 int register
  577 reg_class int_r10_reg(R10);
  578 
  579 // Singleton class for R12 int register
  580 reg_class int_r12_reg(R12);
  581 
  582 // Singleton class for R13 int register
  583 reg_class int_r13_reg(R13);
  584 
  585 // Singleton class for R14 int register
  586 reg_class int_r14_reg(R14);
  587 
  588 // Class for all long integer registers
  589 reg_class all_reg(
  590     R0,  R0_H,
  591     R1,  R1_H,
  592     R2,  R2_H,
  593     R3,  R3_H,
  594     R4,  R4_H,
  595     R7,  R7_H,
  596     R8,  R8_H,
  597     R9,  R9_H,
  598     R10, R10_H,
  599     R11, R11_H,
  600     R12, R12_H,
  601     R13, R13_H,
  602     R14, R14_H,
  603     R15, R15_H,
  604     R16, R16_H,
  605     R17, R17_H,
  606     R18, R18_H,
  607     R19, R19_H,
  608     R20, R20_H,
  609     R21, R21_H,
  610     R22, R22_H,
  611     R23, R23_H,
  612     R24, R24_H,
  613     R25, R25_H,
  614     R26, R26_H,
  615     R27, R27_H,
  616     R28, R28_H,
  617     R29, R29_H,
  618     R30, R30_H,
  619     R31, R31_H
  620 );
  621 
  622 // Class for all long integer registers (excluding zr)
  623 reg_class any_reg %{
  624   return _ANY_REG_mask;
  625 %}
  626 
  627 // Class for non-allocatable 32 bit registers
  628 reg_class non_allocatable_reg32(
  629     R0,                       // zr
  630     R1,                       // lr
  631     R2,                       // sp
  632     R3,                       // gp
  633     R4,                       // tp
  634     R23                       // java thread
  635 );
  636 
  637 // Class for non-allocatable 64 bit registers
  638 reg_class non_allocatable_reg(
  639     R0,  R0_H,                // zr
  640     R1,  R1_H,                // lr
  641     R2,  R2_H,                // sp
  642     R3,  R3_H,                // gp
  643     R4,  R4_H,                // tp
  644     R23, R23_H                // java thread
  645 );
  646 
  647 reg_class no_special_reg32 %{
  648   return _NO_SPECIAL_REG32_mask;
  649 %}
  650 
  651 reg_class no_special_reg %{
  652   return _NO_SPECIAL_REG_mask;
  653 %}
  654 
  655 reg_class ptr_reg %{
  656   return _PTR_REG_mask;
  657 %}
  658 
  659 reg_class no_special_ptr_reg %{
  660   return _NO_SPECIAL_PTR_REG_mask;
  661 %}
  662 
  663 // Class for 64 bit register r10
  664 reg_class r10_reg(
  665     R10, R10_H
  666 );
  667 
  668 // Class for 64 bit register r11
  669 reg_class r11_reg(
  670     R11, R11_H
  671 );
  672 
  673 // Class for 64 bit register r12
  674 reg_class r12_reg(
  675     R12, R12_H
  676 );
  677 
  678 // Class for 64 bit register r13
  679 reg_class r13_reg(
  680     R13, R13_H
  681 );
  682 
  683 // Class for 64 bit register r14
  684 reg_class r14_reg(
  685     R14, R14_H
  686 );
  687 
  688 // Class for 64 bit register r15
  689 reg_class r15_reg(
  690     R15, R15_H
  691 );
  692 
  693 // Class for 64 bit register r16
  694 reg_class r16_reg(
  695     R16, R16_H
  696 );
  697 
  698 // Class for method register
  699 reg_class method_reg(
  700     R31, R31_H
  701 );
  702 
  703 // Class for heapbase register
  704 reg_class heapbase_reg(
  705     R27, R27_H
  706 );
  707 
  708 // Class for java thread register
  709 reg_class java_thread_reg(
  710     R23, R23_H
  711 );
  712 
  713 reg_class r28_reg(
  714     R28, R28_H
  715 );
  716 
  717 reg_class r29_reg(
  718     R29, R29_H
  719 );
  720 
  721 reg_class r30_reg(
  722     R30, R30_H
  723 );
  724 
  725 // Class for zero registesr
  726 reg_class zr_reg(
  727     R0, R0_H
  728 );
  729 
  730 // Class for thread register
  731 reg_class thread_reg(
  732     R4, R4_H
  733 );
  734 
  735 // Class for frame pointer register
  736 reg_class fp_reg(
  737     R8, R8_H
  738 );
  739 
  740 // Class for link register
  741 reg_class lr_reg(
  742     R1, R1_H
  743 );
  744 
  745 // Class for long sp register
  746 reg_class sp_reg(
  747     R2, R2_H
  748 );
  749 
  750 // Class for all float registers
  751 reg_class float_reg(
  752     F0,
  753     F1,
  754     F2,
  755     F3,
  756     F4,
  757     F5,
  758     F6,
  759     F7,
  760     F8,
  761     F9,
  762     F10,
  763     F11,
  764     F12,
  765     F13,
  766     F14,
  767     F15,
  768     F16,
  769     F17,
  770     F18,
  771     F19,
  772     F20,
  773     F21,
  774     F22,
  775     F23,
  776     F24,
  777     F25,
  778     F26,
  779     F27,
  780     F28,
  781     F29,
  782     F30,
  783     F31
  784 );
  785 
  786 // Double precision float registers have virtual `high halves' that
  787 // are needed by the allocator.
  788 // Class for all double registers
  789 reg_class double_reg(
  790     F0,  F0_H,
  791     F1,  F1_H,
  792     F2,  F2_H,
  793     F3,  F3_H,
  794     F4,  F4_H,
  795     F5,  F5_H,
  796     F6,  F6_H,
  797     F7,  F7_H,
  798     F8,  F8_H,
  799     F9,  F9_H,
  800     F10, F10_H,
  801     F11, F11_H,
  802     F12, F12_H,
  803     F13, F13_H,
  804     F14, F14_H,
  805     F15, F15_H,
  806     F16, F16_H,
  807     F17, F17_H,
  808     F18, F18_H,
  809     F19, F19_H,
  810     F20, F20_H,
  811     F21, F21_H,
  812     F22, F22_H,
  813     F23, F23_H,
  814     F24, F24_H,
  815     F25, F25_H,
  816     F26, F26_H,
  817     F27, F27_H,
  818     F28, F28_H,
  819     F29, F29_H,
  820     F30, F30_H,
  821     F31, F31_H
  822 );
  823 
  824 // Class for all RVV vector registers
  825 reg_class vectora_reg(
  826     V1, V1_H, V1_J, V1_K,
  827     V2, V2_H, V2_J, V2_K,
  828     V3, V3_H, V3_J, V3_K,
  829     V4, V4_H, V4_J, V4_K,
  830     V5, V5_H, V5_J, V5_K,
  831     V6, V6_H, V6_J, V6_K,
  832     V7, V7_H, V7_J, V7_K,
  833     V8, V8_H, V8_J, V8_K,
  834     V9, V9_H, V9_J, V9_K,
  835     V10, V10_H, V10_J, V10_K,
  836     V11, V11_H, V11_J, V11_K,
  837     V12, V12_H, V12_J, V12_K,
  838     V13, V13_H, V13_J, V13_K,
  839     V14, V14_H, V14_J, V14_K,
  840     V15, V15_H, V15_J, V15_K,
  841     V16, V16_H, V16_J, V16_K,
  842     V17, V17_H, V17_J, V17_K,
  843     V18, V18_H, V18_J, V18_K,
  844     V19, V19_H, V19_J, V19_K,
  845     V20, V20_H, V20_J, V20_K,
  846     V21, V21_H, V21_J, V21_K,
  847     V22, V22_H, V22_J, V22_K,
  848     V23, V23_H, V23_J, V23_K,
  849     V24, V24_H, V24_J, V24_K,
  850     V25, V25_H, V25_J, V25_K,
  851     V26, V26_H, V26_J, V26_K,
  852     V27, V27_H, V27_J, V27_K,
  853     V28, V28_H, V28_J, V28_K,
  854     V29, V29_H, V29_J, V29_K,
  855     V30, V30_H, V30_J, V30_K,
  856     V31, V31_H, V31_J, V31_K
  857 );
  858 
  859 // Class for 64 bit register f0
  860 reg_class f0_reg(
  861     F0, F0_H
  862 );
  863 
  864 // Class for 64 bit register f1
  865 reg_class f1_reg(
  866     F1, F1_H
  867 );
  868 
  869 // Class for 64 bit register f2
  870 reg_class f2_reg(
  871     F2, F2_H
  872 );
  873 
  874 // Class for 64 bit register f3
  875 reg_class f3_reg(
  876     F3, F3_H
  877 );
  878 
  879 // Singleton class for condition codes t1
  880 reg_class r6_reg(
  881     R6, R6_H
  882 );
  883 
  884 reg_class int_r6_reg(R6);
  885 
  886 // class for vector register v1
  887 reg_class v1_reg(
  888     V1, V1_H, V1_J, V1_K
  889 );
  890 
  891 // class for vector register v2
  892 reg_class v2_reg(
  893     V2, V2_H, V2_J, V2_K
  894 );
  895 
  896 // class for vector register v3
  897 reg_class v3_reg(
  898     V3, V3_H, V3_J, V3_K
  899 );
  900 
  901 // class for vector register v4
  902 reg_class v4_reg(
  903     V4, V4_H, V4_J, V4_K
  904 );
  905 
  906 // class for vector register v5
  907 reg_class v5_reg(
  908     V5, V5_H, V5_J, V5_K
  909 );
  910 %}
  911 
  912 //----------DEFINITION BLOCK---------------------------------------------------
  913 // Define name --> value mappings to inform the ADLC of an integer valued name
  914 // Current support includes integer values in the range [0, 0x7FFFFFFF]
  915 // Format:
  916 //        int_def  <name>         ( <int_value>, <expression>);
  917 // Generated Code in ad_<arch>.hpp
  918 //        #define  <name>   (<expression>)
  919 //        // value == <int_value>
  920 // Generated code in ad_<arch>.cpp adlc_verification()
  921 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  922 //
  923 
  924 // we follow the ppc-aix port in using a simple cost model which ranks
  925 // register operations as cheap, memory ops as more expensive and
  926 // branches as most expensive. the first two have a low as well as a
  927 // normal cost. huge cost appears to be a way of saying don't do
  928 // something
  929 
  930 definitions %{
  931   // The default cost (of a register move instruction).
  932   int_def DEFAULT_COST         (  100,               100);
  933   int_def ALU_COST             (  100,  1 * DEFAULT_COST);          // unknown, const, arith, shift, slt,
  934                                                                     // multi, auipc, nop, logical, move
  935   int_def LOAD_COST            (  300,  3 * DEFAULT_COST);          // load, fpload
  936   int_def STORE_COST           (  100,  1 * DEFAULT_COST);          // store, fpstore
  937   int_def XFER_COST            (  300,  3 * DEFAULT_COST);          // mfc, mtc, fcvt, fmove, fcmp
  938   int_def BRANCH_COST          (  100,  1 * DEFAULT_COST);          // branch, jmp, call
  939   int_def IMUL_COST            ( 1000, 10 * DEFAULT_COST);          // imul
  940   int_def IDIVSI_COST          ( 3400, 34 * DEFAULT_COST);          // idivdi
  941   int_def IDIVDI_COST          ( 6600, 66 * DEFAULT_COST);          // idivsi
  942   int_def FMUL_SINGLE_COST     (  500,  5 * DEFAULT_COST);          // fadd, fmul, fmadd
  943   int_def FMUL_DOUBLE_COST     (  700,  7 * DEFAULT_COST);          // fadd, fmul, fmadd
  944   int_def FDIV_COST            ( 2000, 20 * DEFAULT_COST);          // fdiv
  945   int_def FSQRT_COST           ( 2500, 25 * DEFAULT_COST);          // fsqrt
  946   int_def VOLATILE_REF_COST    ( 1000, 10 * DEFAULT_COST);
  947 %}
  948 
  949 
  950 
  951 //----------SOURCE BLOCK-------------------------------------------------------
  952 // This is a block of C++ code which provides values, functions, and
  953 // definitions necessary in the rest of the architecture description
  954 
  955 source_hpp %{
  956 
  957 #include "asm/macroAssembler.hpp"
  958 #include "gc/shared/cardTable.hpp"
  959 #include "gc/shared/cardTableBarrierSet.hpp"
  960 #include "gc/shared/collectedHeap.hpp"
  961 #include "opto/addnode.hpp"
  962 #include "opto/convertnode.hpp"
  963 
  964 extern RegMask _ANY_REG32_mask;
  965 extern RegMask _ANY_REG_mask;
  966 extern RegMask _PTR_REG_mask;
  967 extern RegMask _NO_SPECIAL_REG32_mask;
  968 extern RegMask _NO_SPECIAL_REG_mask;
  969 extern RegMask _NO_SPECIAL_PTR_REG_mask;
  970 
  971 class CallStubImpl {
  972 
  973   //--------------------------------------------------------------
  974   //---<  Used for optimization in Compile::shorten_branches  >---
  975   //--------------------------------------------------------------
  976 
  977  public:
  978   // Size of call trampoline stub.
  979   static uint size_call_trampoline() {
  980     return 0; // no call trampolines on this platform
  981   }
  982 
  983   // number of relocations needed by a call trampoline stub
  984   static uint reloc_call_trampoline() {
  985     return 0; // no call trampolines on this platform
  986   }
  987 };
  988 
  989 class HandlerImpl {
  990 
  991  public:
  992 
  993   static int emit_exception_handler(CodeBuffer &cbuf);
  994   static int emit_deopt_handler(CodeBuffer& cbuf);
  995 
  996   static uint size_exception_handler() {
  997     return MacroAssembler::far_branch_size();
  998   }
  999 
 1000   static uint size_deopt_handler() {
 1001     // count auipc + far branch
 1002     return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
 1003   }
 1004 };
 1005 
 1006 class Node::PD {
 1007 public:
 1008   enum NodeFlags {
 1009     _last_flag = Node::_last_flag
 1010   };
 1011 };
 1012 
 1013 bool is_CAS(int opcode, bool maybe_volatile);
 1014 
 1015 // predicate controlling translation of CompareAndSwapX
 1016 bool needs_acquiring_load_reserved(const Node *load);
 1017 
 1018 // predicate controlling addressing modes
 1019 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
 1020 
 1021 // predicate using the temp register for decoding klass
 1022 bool maybe_use_tmp_register_decoding_klass();
 1023 %}
 1024 
 1025 source %{
 1026 
 1027 // Derived RegMask with conditionally allocatable registers
 1028 
 1029 RegMask _ANY_REG32_mask;
 1030 RegMask _ANY_REG_mask;
 1031 RegMask _PTR_REG_mask;
 1032 RegMask _NO_SPECIAL_REG32_mask;
 1033 RegMask _NO_SPECIAL_REG_mask;
 1034 RegMask _NO_SPECIAL_PTR_REG_mask;
 1035 
 1036 void reg_mask_init() {
 1037 
 1038   _ANY_REG32_mask = _ALL_REG32_mask;
 1039   _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
 1040 
 1041   _ANY_REG_mask = _ALL_REG_mask;
 1042   _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
 1043 
 1044   _PTR_REG_mask = _ALL_REG_mask;
 1045   _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
 1046 
 1047   _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
 1048   _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
 1049 
 1050   _NO_SPECIAL_REG_mask = _ALL_REG_mask;
 1051   _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1052 
 1053   _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
 1054   _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1055 
 1056   // x27 is not allocatable when compressed oops is on
 1057   if (UseCompressedOops) {
 1058     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1059     _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1060     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1061   }
 1062 
 1063   // x8 is not allocatable when PreserveFramePointer is on
 1064   if (PreserveFramePointer) {
 1065     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1066     _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
 1067     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
 1068   }
 1069 }
 1070 
 1071 void PhaseOutput::pd_perform_mach_node_analysis() {
 1072 }
 1073 
 1074 int MachNode::pd_alignment_required() const {
 1075   return 1;
 1076 }
 1077 
 1078 int MachNode::compute_padding(int current_offset) const {
 1079   return 0;
 1080 }
 1081 
 1082 // is_CAS(int opcode, bool maybe_volatile)
 1083 //
 1084 // return true if opcode is one of the possible CompareAndSwapX
 1085 // values otherwise false.
 1086 bool is_CAS(int opcode, bool maybe_volatile)
 1087 {
 1088   switch(opcode) {
 1089     // We handle these
 1090     case Op_CompareAndSwapI:
 1091     case Op_CompareAndSwapL:
 1092     case Op_CompareAndSwapP:
 1093     case Op_CompareAndSwapN:
 1094     case Op_ShenandoahCompareAndSwapP:
 1095     case Op_ShenandoahCompareAndSwapN:
 1096     case Op_CompareAndSwapB:
 1097     case Op_CompareAndSwapS:
 1098     case Op_GetAndSetI:
 1099     case Op_GetAndSetL:
 1100     case Op_GetAndSetP:
 1101     case Op_GetAndSetN:
 1102     case Op_GetAndAddI:
 1103     case Op_GetAndAddL:
 1104       return true;
 1105     case Op_CompareAndExchangeI:
 1106     case Op_CompareAndExchangeN:
 1107     case Op_CompareAndExchangeB:
 1108     case Op_CompareAndExchangeS:
 1109     case Op_CompareAndExchangeL:
 1110     case Op_CompareAndExchangeP:
 1111     case Op_WeakCompareAndSwapB:
 1112     case Op_WeakCompareAndSwapS:
 1113     case Op_WeakCompareAndSwapI:
 1114     case Op_WeakCompareAndSwapL:
 1115     case Op_WeakCompareAndSwapP:
 1116     case Op_WeakCompareAndSwapN:
 1117     case Op_ShenandoahWeakCompareAndSwapP:
 1118     case Op_ShenandoahWeakCompareAndSwapN:
 1119     case Op_ShenandoahCompareAndExchangeP:
 1120     case Op_ShenandoahCompareAndExchangeN:
 1121       return maybe_volatile;
 1122     default:
 1123       return false;
 1124   }
 1125 }
 1126 
 1127 // predicate controlling translation of CAS
 1128 //
 1129 // returns true if CAS needs to use an acquiring load otherwise false
 1130 bool needs_acquiring_load_reserved(const Node *n)
 1131 {
 1132   assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
 1133 
 1134   LoadStoreNode* ldst = n->as_LoadStore();
 1135   if (n != NULL && is_CAS(n->Opcode(), false)) {
 1136     assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
 1137   } else {
 1138     return ldst != NULL && ldst->trailing_membar() != NULL;
 1139   }
 1140   // so we can just return true here
 1141   return true;
 1142 }
 1143 
 1144 bool maybe_use_tmp_register_decoding_klass() {
 1145   return !UseCompressedOops &&
 1146          CompressedKlassPointers::base() != NULL &&
 1147          CompressedKlassPointers::shift() != 0;
 1148 }
 1149 #define __ _masm.
 1150 
 1151 // advance declarations for helper functions to convert register
 1152 // indices to register objects
 1153 
 1154 // the ad file has to provide implementations of certain methods
 1155 // expected by the generic code
 1156 //
 1157 // REQUIRED FUNCTIONALITY
 1158 
 1159 //=============================================================================
 1160 
 1161 // !!!!! Special hack to get all types of calls to specify the byte offset
 1162 //       from the start of the call to the point where the return address
 1163 //       will point.
 1164 
 1165 int MachCallStaticJavaNode::ret_addr_offset()
 1166 {
 1167   // call should be a simple jal
 1168   int off = 4;
 1169   return off;
 1170 }
 1171 
 1172 int MachCallDynamicJavaNode::ret_addr_offset()
 1173 {
 1174   return 28; // movptr, jal
 1175 }
 1176 
 1177 int MachCallRuntimeNode::ret_addr_offset() {
 1178   // for generated stubs the call will be
 1179   //   jal(addr)
 1180   // or with far branches
 1181   //   jal(trampoline_stub)
 1182   // for real runtime callouts it will be six instructions
 1183   // see riscv64_enc_java_to_runtime
 1184   //   la(t1, retaddr)
 1185   //   la(t0, RuntimeAddress(addr))
 1186   //   addi(sp, sp, -2 * wordSize)
 1187   //   sd(zr, Address(sp))
 1188   //   sd(t1, Address(sp, wordSize))
 1189   //   jalr(t0)
 1190   CodeBlob *cb = CodeCache::find_blob(_entry_point);
 1191   if (cb != NULL) {
 1192     return 1 * NativeInstruction::instruction_size;
 1193   } else {
 1194     return 12 * NativeInstruction::instruction_size;
 1195   }
 1196 }
 1197 
 1198 int MachCallNativeNode::ret_addr_offset() {
 1199   Unimplemented();
 1200   return -1;
 1201 }
 1202 
 1203 //=============================================================================
 1204 
 1205 #ifndef PRODUCT
 1206 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1207   assert_cond(st != NULL);
 1208   st->print("BREAKPOINT");
 1209 }
 1210 #endif
 1211 
 1212 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1213   C2_MacroAssembler _masm(&cbuf);
 1214   __ ebreak();
 1215 }
 1216 
 1217 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 1218   return MachNode::size(ra_);
 1219 }
 1220 
 1221 //=============================================================================
 1222 
 1223 #ifndef PRODUCT
 1224   void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
 1225     st->print("nop \t# %d bytes pad for loops and calls", _count);
 1226   }
 1227 #endif
 1228 
 1229   void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
 1230     C2_MacroAssembler _masm(&cbuf);
 1231     for (int i = 0; i < _count; i++) {
 1232       __ nop();
 1233     }
 1234   }
 1235 
 1236   uint MachNopNode::size(PhaseRegAlloc*) const {
 1237     return _count * NativeInstruction::instruction_size;
 1238   }
 1239 
 1240 //=============================================================================
 1241 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 1242 
 1243 int ConstantTable::calculate_table_base_offset() const {
 1244   return 0;  // absolute addressing, no offset
 1245 }
 1246 
 1247 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 1248 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 1249   ShouldNotReachHere();
 1250 }
 1251 
 1252 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 1253   // Empty encoding
 1254 }
 1255 
 1256 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 1257   return 0;
 1258 }
 1259 
 1260 #ifndef PRODUCT
 1261 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 1262   assert_cond(st != NULL);
 1263   st->print("-- \t// MachConstantBaseNode (empty encoding)");
 1264 }
 1265 #endif
 1266 
 1267 #ifndef PRODUCT
 1268 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1269   assert_cond(st != NULL && ra_ != NULL);
 1270   Compile* C = ra_->C;
 1271 
 1272   int framesize = C->output()->frame_slots() << LogBytesPerInt;
 1273 
 1274   if (C->output()->need_stack_bang(framesize)) {
 1275     st->print("# stack bang size=%d\n\t", framesize);
 1276   }
 1277 
 1278   st->print("sd  fp, [sp, #%d]", - 2 * wordSize);
 1279   st->print("sd  lr, [sp, #%d]", - wordSize);
 1280   if (PreserveFramePointer) { st->print("\n\tsub  fp, sp, #%d", 2 * wordSize); }
 1281   st->print("sub sp, sp, #%d\n\t", framesize);
 1282 
 1283   if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 1284     st->print("ld  t0, [guard]\n\t");
 1285     st->print("membar LoadLoad\n\t");
 1286     st->print("ld  t1, [xthread, #thread_disarmed_offset]\n\t");
 1287     st->print("beq t0, t1, skip\n\t");
 1288     st->print("jalr #nmethod_entry_barrier_stub\n\t");
 1289     st->print("j skip\n\t");
 1290     st->print("guard: int\n\t");
 1291     st->print("skip:\n\t");
 1292   }
 1293 }
 1294 #endif
 1295 
 1296 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1297   assert_cond(ra_ != NULL);
 1298   Compile* C = ra_->C;
 1299   C2_MacroAssembler _masm(&cbuf);
 1300 
 1301   // n.b. frame size includes space for return pc and fp
 1302   const int framesize = C->output()->frame_size_in_bytes();
 1303 
 1304   // insert a nop at the start of the prolog so we can patch in a
 1305   // branch if we need to invalidate the method later
 1306   __ nop();
 1307 
 1308   assert_cond(C != NULL);
 1309 
 1310   if (C->clinit_barrier_on_entry()) {
 1311     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 1312 
 1313     Label L_skip_barrier;
 1314 
 1315     __ mov_metadata(t1, C->method()->holder()->constant_encoding());
 1316     __ clinit_barrier(t1, t0, &L_skip_barrier);
 1317     __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 1318     __ bind(L_skip_barrier);
 1319   }
 1320 
 1321   int bangsize = C->output()->bang_size_in_bytes();
 1322   if (C->output()->need_stack_bang(bangsize)) {
 1323     __ generate_stack_overflow_check(bangsize);
 1324   }
 1325 
 1326   __ build_frame(framesize);
 1327 
 1328   if (C->stub_function() == NULL) {
 1329     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 1330     bs->nmethod_entry_barrier(&_masm);
 1331   }
 1332 
 1333   if (VerifyStackAtCalls) {
 1334     Unimplemented();
 1335   }
 1336 
 1337   C->output()->set_frame_complete(cbuf.insts_size());
 1338 
 1339   if (C->has_mach_constant_base_node()) {
 1340     // NOTE: We set the table base offset here because users might be
 1341     // emitted before MachConstantBaseNode.
 1342     ConstantTable& constant_table = C->output()->constant_table();
 1343     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 1344   }
 1345 }
 1346 
 1347 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 1348 {
 1349   assert_cond(ra_ != NULL);
 1350   return MachNode::size(ra_); // too many variables; just compute it
 1351                               // the hard way
 1352 }
 1353 
 1354 int MachPrologNode::reloc() const
 1355 {
 1356   return 0;
 1357 }
 1358 
 1359 //=============================================================================
 1360 
 1361 #ifndef PRODUCT
 1362 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1363   assert_cond(st != NULL && ra_ != NULL);
 1364   Compile* C = ra_->C;
 1365   assert_cond(C != NULL);
 1366   int framesize = C->output()->frame_size_in_bytes();
 1367 
 1368   st->print("# pop frame %d\n\t", framesize);
 1369 
 1370   if (framesize == 0) {
 1371     st->print("ld  lr, [sp,#%d]\n\t", (2 * wordSize));
 1372     st->print("ld  fp, [sp,#%d]\n\t", (3 * wordSize));
 1373     st->print("add sp, sp, #%d\n\t", (2 * wordSize));
 1374   } else {
 1375     st->print("add  sp, sp, #%d\n\t", framesize);
 1376     st->print("ld  lr, [sp,#%d]\n\t", - 2 * wordSize);
 1377     st->print("ld  fp, [sp,#%d]\n\t", - wordSize);
 1378   }
 1379 
 1380   if (do_polling() && C->is_method_compilation()) {
 1381     st->print("# test polling word\n\t");
 1382     st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
 1383     st->print("bgtu sp, t0, #slow_path");
 1384   }
 1385 }
 1386 #endif
 1387 
 1388 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1389   assert_cond(ra_ != NULL);
 1390   Compile* C = ra_->C;
 1391   C2_MacroAssembler _masm(&cbuf);
 1392   assert_cond(C != NULL);
 1393   int framesize = C->output()->frame_size_in_bytes();
 1394 
 1395   __ remove_frame(framesize);
 1396 
 1397   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 1398     __ reserved_stack_check();
 1399   }
 1400 
 1401   if (do_polling() && C->is_method_compilation()) {
 1402     Label dummy_label;
 1403     Label* code_stub = &dummy_label;
 1404     if (!C->output()->in_scratch_emit_size()) {
 1405       code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
 1406     }
 1407     __ relocate(relocInfo::poll_return_type);
 1408     __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
 1409   }
 1410 }
 1411 
 1412 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 1413   assert_cond(ra_ != NULL);
 1414   // Variable size. Determine dynamically.
 1415   return MachNode::size(ra_);
 1416 }
 1417 
 1418 int MachEpilogNode::reloc() const {
 1419   // Return number of relocatable values contained in this instruction.
 1420   return 1; // 1 for polling page.
 1421 }
 1422 const Pipeline * MachEpilogNode::pipeline() const {
 1423   return MachNode::pipeline_class();
 1424 }
 1425 
 1426 //=============================================================================
 1427 
 1428 // Figure out which register class each belongs in: rc_int, rc_float or
 1429 // rc_stack.
 1430 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
 1431 
 1432 static enum RC rc_class(OptoReg::Name reg) {
 1433 
 1434   if (reg == OptoReg::Bad) {
 1435     return rc_bad;
 1436   }
 1437 
 1438   // we have 32 int registers * 2 halves
 1439   // (t0 and t1 are omitted)
 1440   int slots_of_int_registers = RegisterImpl::max_slots_per_register * RegisterImpl::number_of_registers;
 1441   if (reg < slots_of_int_registers) {
 1442     return rc_int;
 1443   }
 1444 
 1445   // we have 32 float register * 2 halves
 1446   int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers;
 1447   if (reg < slots_of_int_registers + slots_of_float_registers) {
 1448     return rc_float;
 1449   }
 1450 
 1451   // we have 32 vector register * 4 halves
 1452   int slots_of_vector_registers = VectorRegisterImpl::max_slots_per_register * VectorRegisterImpl::number_of_registers;
 1453   if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
 1454     return rc_vector;
 1455   }
 1456 
 1457   // Between vector regs & stack is the flags regs.
 1458   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
 1459 
 1460   return rc_stack;
 1461 }
 1462 
 1463 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
 1464   assert_cond(ra_ != NULL);
 1465   Compile* C = ra_->C;
 1466 
 1467   // Get registers to move.
 1468   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1469   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1470   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1471   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1472 
 1473   enum RC src_hi_rc = rc_class(src_hi);
 1474   enum RC src_lo_rc = rc_class(src_lo);
 1475   enum RC dst_hi_rc = rc_class(dst_hi);
 1476   enum RC dst_lo_rc = rc_class(dst_lo);
 1477 
 1478   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1479 
 1480   if (src_hi != OptoReg::Bad) {
 1481     assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1482            (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
 1483            "expected aligned-adjacent pairs");
 1484   }
 1485 
 1486   if (src_lo == dst_lo && src_hi == dst_hi) {
 1487     return 0;            // Self copy, no move.
 1488   }
 1489 
 1490   bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1491               (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
 1492   int src_offset = ra_->reg2offset(src_lo);
 1493   int dst_offset = ra_->reg2offset(dst_lo);
 1494 
 1495   if (bottom_type() == NULL) {
 1496     ShouldNotReachHere();
 1497   } else if (bottom_type()->isa_vect() != NULL) {
 1498     uint ireg = ideal_reg();
 1499     if (ireg == Op_VecA && cbuf) {
 1500       C2_MacroAssembler _masm(cbuf);
 1501       int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 1502       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1503         // stack to stack
 1504         __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
 1505                                             vector_reg_size_in_bytes);
 1506       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
 1507         // vpr to stack
 1508         __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
 1509       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
 1510         // stack to vpr
 1511         __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
 1512       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
 1513         // vpr to vpr
 1514         __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
 1515       } else {
 1516         ShouldNotReachHere();
 1517       }
 1518     }
 1519   } else if (cbuf != NULL) {
 1520     C2_MacroAssembler _masm(cbuf);
 1521     switch (src_lo_rc) {
 1522       case rc_int:
 1523         if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
 1524           __ mv(as_Register(Matcher::_regEncode[dst_lo]),
 1525                 as_Register(Matcher::_regEncode[src_lo]));
 1526           if (!is64 && this->ideal_reg() != Op_RegI) // zero extended for narrow oop or klass
 1527             __ clear_upper_bits(as_Register(Matcher::_regEncode[dst_lo]), 32);
 1528         } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
 1529           if (is64) {
 1530             __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1531                        as_Register(Matcher::_regEncode[src_lo]));
 1532           } else {
 1533             __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1534                        as_Register(Matcher::_regEncode[src_lo]));
 1535           }
 1536         } else {                    // gpr --> stack spill
 1537           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1538           __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
 1539         }
 1540         break;
 1541       case rc_float:
 1542         if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
 1543           if (is64) {
 1544             __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
 1545                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1546           } else {
 1547             __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
 1548                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1549           }
 1550         } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
 1551           if (is64) {
 1552             __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1553                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1554           } else {
 1555             __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1556                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1557           }
 1558         } else {                    // fpr --> stack spill
 1559           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1560           __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
 1561                    is64, dst_offset);
 1562         }
 1563         break;
 1564       case rc_stack:
 1565         if (dst_lo_rc == rc_int) {  // stack --> gpr load
 1566           if (this->ideal_reg() == Op_RegI) {
 1567             __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1568           } else { // // zero extended for narrow oop or klass
 1569             __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1570           }
 1571         } else if (dst_lo_rc == rc_float) { // stack --> fpr load
 1572           __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1573                      is64, src_offset);
 1574         } else {                    // stack --> stack copy
 1575           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1576           if (this->ideal_reg() == Op_RegI) {
 1577             __ unspill(t0, is64, src_offset);
 1578           } else { // zero extended for narrow oop or klass
 1579             __ unspillu(t0, is64, src_offset);
 1580           }
 1581           __ spill(t0, is64, dst_offset);
 1582         }
 1583         break;
 1584       default:
 1585         ShouldNotReachHere();
 1586     }
 1587   }
 1588 
 1589   if (st != NULL) {
 1590     st->print("spill ");
 1591     if (src_lo_rc == rc_stack) {
 1592       st->print("[sp, #%d] -> ", src_offset);
 1593     } else {
 1594       st->print("%s -> ", Matcher::regName[src_lo]);
 1595     }
 1596     if (dst_lo_rc == rc_stack) {
 1597       st->print("[sp, #%d]", dst_offset);
 1598     } else {
 1599       st->print("%s", Matcher::regName[dst_lo]);
 1600     }
 1601     if (bottom_type()->isa_vect() != NULL) {
 1602       int vsize = 0;
 1603       if (ideal_reg() == Op_VecA) {
 1604         vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
 1605       } else {
 1606         ShouldNotReachHere();
 1607       }
 1608       st->print("\t# vector spill size = %d", vsize);
 1609     } else {
 1610       st->print("\t# spill size = %d", is64 ? 64 : 32);
 1611     }
 1612   }
 1613 
 1614   return 0;
 1615 }
 1616 
 1617 #ifndef PRODUCT
 1618 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1619   if (ra_ == NULL) {
 1620     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
 1621   } else {
 1622     implementation(NULL, ra_, false, st);
 1623   }
 1624 }
 1625 #endif
 1626 
 1627 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1628   implementation(&cbuf, ra_, false, NULL);
 1629 }
 1630 
 1631 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1632   return MachNode::size(ra_);
 1633 }
 1634 
 1635 //=============================================================================
 1636 
 1637 #ifndef PRODUCT
 1638 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1639   assert_cond(ra_ != NULL && st != NULL);
 1640   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1641   int reg = ra_->get_reg_first(this);
 1642   st->print("add %s, sp, #%d\t# box lock",
 1643             Matcher::regName[reg], offset);
 1644 }
 1645 #endif
 1646 
 1647 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1648   C2_MacroAssembler _masm(&cbuf);
 1649 
 1650   assert_cond(ra_ != NULL);
 1651   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1652   int reg    = ra_->get_encode(this);
 1653 
 1654   if (is_imm_in_range(offset, 12, 0)) {
 1655     __ addi(as_Register(reg), sp, offset);
 1656   } else if (is_imm_in_range(offset, 32, 0)) {
 1657     __ li32(t0, offset);
 1658     __ add(as_Register(reg), sp, t0);
 1659   } else {
 1660     ShouldNotReachHere();
 1661   }
 1662 }
 1663 
 1664 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1665   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
 1666   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1667 
 1668   if (is_imm_in_range(offset, 12, 0)) {
 1669     return NativeInstruction::instruction_size;
 1670   } else {
 1671     return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
 1672   }
 1673 }
 1674 
 1675 //=============================================================================
 1676 
 1677 #ifndef PRODUCT
 1678 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1679 {
 1680   assert_cond(st != NULL);
 1681   st->print_cr("# MachUEPNode");
 1682   if (UseCompressedClassPointers) {
 1683     st->print_cr("\tlw t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1684     if (CompressedKlassPointers::shift() != 0) {
 1685       st->print_cr("\tdecode_klass_not_null t0, t0");
 1686     }
 1687   } else {
 1688    st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1689   }
 1690   st->print_cr("\tbne x10, t0, SharedRuntime::_ic_miss_stub\t # Inline cache check");
 1691 }
 1692 #endif
 1693 
 1694 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1695 {
 1696   // This is the unverified entry point.
 1697   C2_MacroAssembler _masm(&cbuf);
 1698 
 1699   Label skip;
 1700   __ cmp_klass(j_rarg0, t1, t0, skip);
 1701   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 1702   __ bind(skip);
 1703 }
 1704 
 1705 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1706 {
 1707   assert_cond(ra_ != NULL);
 1708   return MachNode::size(ra_);
 1709 }
 1710 
 1711 // REQUIRED EMIT CODE
 1712 
 1713 //=============================================================================
 1714 
 1715 // Emit exception handler code.
 1716 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
 1717 {
 1718   // la_patchable t0, #exception_blob_entry_point
 1719   // jr (offset)t0
 1720   // or
 1721   // j #exception_blob_entry_point
 1722   // Note that the code buffer's insts_mark is always relative to insts.
 1723   // That's why we must use the macroassembler to generate a handler.
 1724   C2_MacroAssembler _masm(&cbuf);
 1725   address base = __ start_a_stub(size_exception_handler());
 1726   if (base == NULL) {
 1727     ciEnv::current()->record_failure("CodeCache is full");
 1728     return 0;  // CodeBuffer::expand failed
 1729   }
 1730   int offset = __ offset();
 1731   __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
 1732   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1733   __ end_a_stub();
 1734   return offset;
 1735 }
 1736 
 1737 // Emit deopt handler code.
 1738 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
 1739 {
 1740   // Note that the code buffer's insts_mark is always relative to insts.
 1741   // That's why we must use the macroassembler to generate a handler.
 1742   C2_MacroAssembler _masm(&cbuf);
 1743   address base = __ start_a_stub(size_deopt_handler());
 1744   if (base == NULL) {
 1745     ciEnv::current()->record_failure("CodeCache is full");
 1746     return 0;  // CodeBuffer::expand failed
 1747   }
 1748   int offset = __ offset();
 1749 
 1750   __ auipc(ra, 0);
 1751   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 1752 
 1753   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 1754   __ end_a_stub();
 1755   return offset;
 1756 
 1757 }
 1758 // REQUIRED MATCHER CODE
 1759 
 1760 //=============================================================================
 1761 
 1762 const bool Matcher::match_rule_supported(int opcode) {
 1763   if (!has_match_rule(opcode)) {
 1764     return false;
 1765   }
 1766 
 1767   switch (opcode) {
 1768     case Op_CacheWB:           // fall through
 1769     case Op_CacheWBPreSync:    // fall through
 1770     case Op_CacheWBPostSync:
 1771       if (!VM_Version::supports_data_cache_line_flush()) {
 1772         return false;
 1773       }
 1774       break;
 1775     case Op_StrCompressedCopy: // fall through
 1776     case Op_StrInflatedCopy:   // fall through
 1777     case Op_HasNegatives:
 1778       return UseVExt;
 1779     case Op_EncodeISOArray:
 1780       return UseVExt && SpecialEncodeISOArray;
 1781   }
 1782 
 1783   return true; // Per default match rules are supported.
 1784 }
 1785 
 1786 // Identify extra cases that we might want to provide match rules for vector nodes and
 1787 // other intrinsics guarded with vector length (vlen) and element type (bt).
 1788 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
 1789   if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
 1790     return false;
 1791   }
 1792 
 1793   return op_vec_supported(opcode);
 1794 }
 1795 
 1796 const RegMask* Matcher::predicate_reg_mask(void) {
 1797   return NULL;
 1798 }
 1799 
 1800 const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
 1801   return NULL;
 1802 }
 1803 
 1804 // Vector calling convention not yet implemented.
 1805 const bool Matcher::supports_vector_calling_convention(void) {
 1806   return false;
 1807 }
 1808 
 1809 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1810   Unimplemented();
 1811   return OptoRegPair(0, 0);
 1812 }
 1813 
 1814 // Is this branch offset short enough that a short branch can be used?
 1815 //
 1816 // NOTE: If the platform does not provide any short branch variants, then
 1817 //       this method should return false for offset 0.
 1818 // |---label(L1)-----|
 1819 // |-----------------|
 1820 // |-----------------|----------eq: float-------------------
 1821 // |-----------------| // far_cmpD_branch   |   cmpD_branch
 1822 // |------- ---------|    feq;              |      feq;
 1823 // |-far_cmpD_branch-|    beqz done;        |      bnez L;
 1824 // |-----------------|    j L;              |
 1825 // |-----------------|    bind(done);       |
 1826 // |-----------------|--------------------------------------
 1827 // |-----------------| // so shortBrSize = br_size - 4;
 1828 // |-----------------| // so offs = offset - shortBrSize + 4;
 1829 // |---label(L2)-----|
 1830 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1831   // The passed offset is relative to address of the branch.
 1832   int shortBrSize = br_size - 4;
 1833   int offs = offset - shortBrSize + 4;
 1834   return (-4096 <= offs && offs < 4096);
 1835 }
 1836 
 1837 // Vector width in bytes.
 1838 const int Matcher::vector_width_in_bytes(BasicType bt) {
 1839   if (UseVExt) {
 1840     // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseVExt.
 1841     // MaxVectorSize == VM_Version::_initial_vector_length
 1842     return MaxVectorSize;
 1843   }
 1844   return 0;
 1845 }
 1846 
 1847 // Limits on vector size (number of elements) loaded into vector.
 1848 const int Matcher::max_vector_size(const BasicType bt) {
 1849   return vector_width_in_bytes(bt) / type2aelembytes(bt);
 1850 }
 1851 const int Matcher::min_vector_size(const BasicType bt) {
 1852   return max_vector_size(bt);
 1853 }
 1854 
 1855 // Vector ideal reg.
 1856 const uint Matcher::vector_ideal_reg(int len) {
 1857   assert(MaxVectorSize >= len, "");
 1858   if (UseVExt) {
 1859     return Op_VecA;
 1860   }
 1861 
 1862   ShouldNotReachHere();
 1863   return 0;
 1864 }
 1865 
 1866 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
 1867   return Matcher::max_vector_size(bt);
 1868 }
 1869 
 1870 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 1871   ShouldNotReachHere(); // generic vector operands not supported
 1872   return NULL;
 1873 }
 1874 
 1875 bool Matcher::is_reg2reg_move(MachNode* m) {
 1876   ShouldNotReachHere(); // generic vector operands not supported
 1877   return false;
 1878 }
 1879 
 1880 bool Matcher::is_generic_vector(MachOper* opnd) {
 1881   ShouldNotReachHere(); // generic vector operands not supported
 1882   return false;
 1883 }
 1884 
 1885 // Return whether or not this register is ever used as an argument.
 1886 // This function is used on startup to build the trampoline stubs in
 1887 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1888 // call in the trampoline, and arguments in those registers not be
 1889 // available to the callee.
 1890 bool Matcher::can_be_java_arg(int reg)
 1891 {
 1892   return
 1893     reg ==  R10_num || reg == R10_H_num ||
 1894     reg ==  R11_num || reg == R11_H_num ||
 1895     reg ==  R12_num || reg == R12_H_num ||
 1896     reg ==  R13_num || reg == R13_H_num ||
 1897     reg ==  R14_num || reg == R14_H_num ||
 1898     reg ==  R15_num || reg == R15_H_num ||
 1899     reg ==  R16_num || reg == R16_H_num ||
 1900     reg ==  R17_num || reg == R17_H_num ||
 1901     reg ==  F10_num || reg == F10_H_num ||
 1902     reg ==  F11_num || reg == F11_H_num ||
 1903     reg ==  F12_num || reg == F12_H_num ||
 1904     reg ==  F13_num || reg == F13_H_num ||
 1905     reg ==  F14_num || reg == F14_H_num ||
 1906     reg ==  F15_num || reg == F15_H_num ||
 1907     reg ==  F16_num || reg == F16_H_num ||
 1908     reg ==  F17_num || reg == F17_H_num;
 1909 }
 1910 
 1911 bool Matcher::is_spillable_arg(int reg)
 1912 {
 1913   return can_be_java_arg(reg);
 1914 }
 1915 
 1916 uint Matcher::int_pressure_limit()
 1917 {
 1918   // A derived pointer is live at CallNode and then is flagged by RA
 1919   // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
 1920   // derived pointers and lastly fail to spill after reaching maximum
 1921   // number of iterations. Lowering the default pressure threshold to
 1922   // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
 1923   // a high register pressure area of the code so that split_DEF can
 1924   // generate DefinitionSpillCopy for the derived pointer.
 1925   uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
 1926   if (!PreserveFramePointer) {
 1927     // When PreserveFramePointer is off, frame pointer is allocatable,
 1928     // but different from other SOC registers, it is excluded from
 1929     // fatproj's mask because its save type is No-Save. Decrease 1 to
 1930     // ensure high pressure at fatproj when PreserveFramePointer is off.
 1931     // See check_pressure_at_fatproj().
 1932     default_int_pressure_threshold--;
 1933   }
 1934   return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
 1935 }
 1936 
 1937 uint Matcher::float_pressure_limit()
 1938 {
 1939   // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
 1940   return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
 1941 }
 1942 
 1943 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 1944   return false;
 1945 }
 1946 
 1947 RegMask Matcher::divI_proj_mask() {
 1948   ShouldNotReachHere();
 1949   return RegMask();
 1950 }
 1951 
 1952 // Register for MODI projection of divmodI.
 1953 RegMask Matcher::modI_proj_mask() {
 1954   ShouldNotReachHere();
 1955   return RegMask();
 1956 }
 1957 
 1958 // Register for DIVL projection of divmodL.
 1959 RegMask Matcher::divL_proj_mask() {
 1960   ShouldNotReachHere();
 1961   return RegMask();
 1962 }
 1963 
 1964 // Register for MODL projection of divmodL.
 1965 RegMask Matcher::modL_proj_mask() {
 1966   ShouldNotReachHere();
 1967   return RegMask();
 1968 }
 1969 
 1970 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 1971   return FP_REG_mask();
 1972 }
 1973 
 1974 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
 1975   assert_cond(addp != NULL);
 1976   for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
 1977     Node* u = addp->fast_out(i);
 1978     if (u != NULL && u->is_Mem()) {
 1979       int opsize = u->as_Mem()->memory_size();
 1980       assert(opsize > 0, "unexpected memory operand size");
 1981       if (u->as_Mem()->memory_size() != (1 << shift)) {
 1982         return false;
 1983       }
 1984     }
 1985   }
 1986   return true;
 1987 }
 1988 
 1989 // Should the Matcher clone input 'm' of node 'n'?
 1990 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 1991   assert_cond(m != NULL);
 1992   if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
 1993     mstack.push(m, Visit);           // m = ShiftCntV
 1994     return true;
 1995   }
 1996   return false;
 1997 }
 1998 
 1999 // Should the Matcher clone shifts on addressing modes, expecting them
 2000 // to be subsumed into complex addressing expressions or compute them
 2001 // into registers?
 2002 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 2003   return clone_base_plus_offset_address(m, mstack, address_visited);
 2004 }
 2005 
 2006 %}
 2007 
 2008 
 2009 
 2010 //----------ENCODING BLOCK-----------------------------------------------------
 2011 // This block specifies the encoding classes used by the compiler to
 2012 // output byte streams.  Encoding classes are parameterized macros
 2013 // used by Machine Instruction Nodes in order to generate the bit
 2014 // encoding of the instruction.  Operands specify their base encoding
 2015 // interface with the interface keyword.  There are currently
 2016 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 2017 // COND_INTER.  REG_INTER causes an operand to generate a function
 2018 // which returns its register number when queried.  CONST_INTER causes
 2019 // an operand to generate a function which returns the value of the
 2020 // constant when queried.  MEMORY_INTER causes an operand to generate
 2021 // four functions which return the Base Register, the Index Register,
 2022 // the Scale Value, and the Offset Value of the operand when queried.
 2023 // COND_INTER causes an operand to generate six functions which return
 2024 // the encoding code (ie - encoding bits for the instruction)
 2025 // associated with each basic boolean condition for a conditional
 2026 // instruction.
 2027 //
 2028 // Instructions specify two basic values for encoding.  Again, a
 2029 // function is available to check if the constant displacement is an
 2030 // oop. They use the ins_encode keyword to specify their encoding
 2031 // classes (which must be a sequence of enc_class names, and their
 2032 // parameters, specified in the encoding block), and they use the
 2033 // opcode keyword to specify, in order, their primary, secondary, and
 2034 // tertiary opcode.  Only the opcode sections which a particular
 2035 // instruction needs for encoding need to be specified.
 2036 encode %{
 2037   // BEGIN Non-volatile memory access
 2038 
 2039   enc_class riscv64_enc_li_imm(iRegIorL dst, immIorL src) %{
 2040     C2_MacroAssembler _masm(&cbuf);
 2041     int64_t con = (int64_t)$src$$constant;
 2042     Register dst_reg = as_Register($dst$$reg);
 2043     __ li(dst_reg, con);
 2044   %}
 2045 
 2046   enc_class riscv64_enc_mov_p(iRegP dst, immP src) %{
 2047     C2_MacroAssembler _masm(&cbuf);
 2048     Register dst_reg = as_Register($dst$$reg);
 2049     address con = (address)$src$$constant;
 2050     if (con == NULL || con == (address)1) {
 2051       ShouldNotReachHere();
 2052     } else {
 2053       relocInfo::relocType rtype = $src->constant_reloc();
 2054       if (rtype == relocInfo::oop_type) {
 2055         __ movoop(dst_reg, (jobject)con, /*immediate*/true);
 2056       } else if (rtype == relocInfo::metadata_type) {
 2057         __ mov_metadata(dst_reg, (Metadata*)con);
 2058       } else {
 2059         assert(rtype == relocInfo::none, "unexpected reloc type");
 2060         __ li(dst_reg, $src$$constant);
 2061       }
 2062     }
 2063   %}
 2064 
 2065   enc_class riscv64_enc_mov_p1(iRegP dst) %{
 2066     C2_MacroAssembler _masm(&cbuf);
 2067     Register dst_reg = as_Register($dst$$reg);
 2068     __ li(dst_reg, 1);
 2069   %}
 2070 
 2071   enc_class riscv64_enc_mov_byte_map_base(iRegP dst) %{
 2072     C2_MacroAssembler _masm(&cbuf);
 2073     __ load_byte_map_base($dst$$Register);
 2074   %}
 2075 
 2076   enc_class riscv64_enc_mov_n(iRegN dst, immN src) %{
 2077     C2_MacroAssembler _masm(&cbuf);
 2078     Register dst_reg = as_Register($dst$$reg);
 2079     address con = (address)$src$$constant;
 2080     if (con == NULL) {
 2081       ShouldNotReachHere();
 2082     } else {
 2083       relocInfo::relocType rtype = $src->constant_reloc();
 2084       assert(rtype == relocInfo::oop_type, "unexpected reloc type");
 2085       __ set_narrow_oop(dst_reg, (jobject)con);
 2086     }
 2087   %}
 2088 
 2089   enc_class riscv64_enc_mov_zero(iRegNorP dst) %{
 2090     C2_MacroAssembler _masm(&cbuf);
 2091     Register dst_reg = as_Register($dst$$reg);
 2092     __ mv(dst_reg, zr);
 2093   %}
 2094 
 2095   enc_class riscv64_enc_mov_nk(iRegN dst, immNKlass src) %{
 2096     C2_MacroAssembler _masm(&cbuf);
 2097     Register dst_reg = as_Register($dst$$reg);
 2098     address con = (address)$src$$constant;
 2099     if (con == NULL) {
 2100       ShouldNotReachHere();
 2101     } else {
 2102       relocInfo::relocType rtype = $src->constant_reloc();
 2103       assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
 2104       __ set_narrow_klass(dst_reg, (Klass *)con);
 2105     }
 2106   %}
 2107 
 2108   enc_class riscv64_enc_cmpxchgw(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2109     C2_MacroAssembler _masm(&cbuf);
 2110     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2111                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2112                /*result as bool*/ true);
 2113   %}
 2114 
 2115   enc_class riscv64_enc_cmpxchgn(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2116     C2_MacroAssembler _masm(&cbuf);
 2117     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2118                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2119                /*result as bool*/ true);
 2120   %}
 2121 
 2122   enc_class riscv64_enc_cmpxchg(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
 2123     C2_MacroAssembler _masm(&cbuf);
 2124     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2125                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2126                /*result as bool*/ true);
 2127   %}
 2128 
 2129   enc_class riscv64_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2130     C2_MacroAssembler _masm(&cbuf);
 2131     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2132                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2133                /*result as bool*/ true);
 2134   %}
 2135 
 2136   enc_class riscv64_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2137     C2_MacroAssembler _masm(&cbuf);
 2138     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2139                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2140                /*result as bool*/ true);
 2141   %}
 2142 
 2143   enc_class riscv64_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
 2144     C2_MacroAssembler _masm(&cbuf);
 2145     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2146                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2147                /*result as bool*/ true);
 2148   %}
 2149 
 2150   // compare and branch instruction encodings
 2151 
 2152   enc_class riscv64_enc_j(label lbl) %{
 2153     C2_MacroAssembler _masm(&cbuf);
 2154     Label* L = $lbl$$label;
 2155     __ j(*L);
 2156   %}
 2157 
 2158   enc_class riscv64_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
 2159     C2_MacroAssembler _masm(&cbuf);
 2160     Label* L = $lbl$$label;
 2161     switch($cmp$$cmpcode) {
 2162       case(BoolTest::ge):
 2163         __ j(*L);
 2164         break;
 2165       case(BoolTest::lt):
 2166         break;
 2167       default:
 2168         Unimplemented();
 2169     }
 2170   %}
 2171 
 2172   // call instruction encodings
 2173 
 2174   enc_class riscv64_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result, iRegI_R6 cr) %{
 2175     Register sub_reg = as_Register($sub$$reg);
 2176     Register super_reg = as_Register($super$$reg);
 2177     Register temp_reg = as_Register($temp$$reg);
 2178     Register result_reg = as_Register($result$$reg);
 2179     Register cr_reg = as_Register($cr$$reg);
 2180 
 2181     Label miss;
 2182     Label done;
 2183     C2_MacroAssembler _masm(&cbuf);
 2184     __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
 2185                                      NULL, &miss);
 2186     if ($primary) {
 2187       __ mv(result_reg, zr);
 2188     } else {
 2189       __ mv(cr_reg, zr);
 2190       __ j(done);
 2191     }
 2192 
 2193     __ bind(miss);
 2194     if (!$primary) {
 2195       __ li(cr_reg, 1);
 2196     }
 2197 
 2198     __ bind(done);
 2199   %}
 2200 
 2201   enc_class riscv64_enc_java_static_call(method meth) %{
 2202     C2_MacroAssembler _masm(&cbuf);
 2203 
 2204     address addr = (address)$meth$$method;
 2205     address call = NULL;
 2206     assert_cond(addr != NULL);
 2207     if (!_method) {
 2208       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
 2209       call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
 2210       if (call == NULL) {
 2211         ciEnv::current()->record_failure("CodeCache is full");
 2212         return;
 2213       }
 2214     } else {
 2215       int method_index = resolved_method_index(cbuf);
 2216       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2217                                                   : static_call_Relocation::spec(method_index);
 2218       call = __ trampoline_call(Address(addr, rspec), &cbuf);
 2219       if (call == NULL) {
 2220         ciEnv::current()->record_failure("CodeCache is full");
 2221         return;
 2222       }
 2223 
 2224       // Emit stub for static call
 2225       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
 2226       if (stub == NULL) {
 2227         ciEnv::current()->record_failure("CodeCache is full");
 2228         return;
 2229       }
 2230     }
 2231   %}
 2232 
 2233   enc_class riscv64_enc_java_dynamic_call(method meth) %{
 2234     C2_MacroAssembler _masm(&cbuf);
 2235     int method_index = resolved_method_index(cbuf);
 2236     address call = __ ic_call((address)$meth$$method, method_index);
 2237     if (call == NULL) {
 2238       ciEnv::current()->record_failure("CodeCache is full");
 2239       return;
 2240     }
 2241   %}
 2242 
 2243   enc_class riscv64_enc_call_epilog() %{
 2244     C2_MacroAssembler _masm(&cbuf);
 2245     if (VerifyStackAtCalls) {
 2246       // Check that stack depth is unchanged: find majik cookie on stack
 2247       __ call_Unimplemented();
 2248     }
 2249   %}
 2250 
 2251   enc_class riscv64_enc_java_to_runtime(method meth) %{
 2252     C2_MacroAssembler _masm(&cbuf);
 2253 
 2254     // some calls to generated routines (arraycopy code) are scheduled
 2255     // by C2 as runtime calls. if so we can call them using a jr (they
 2256     // will be in a reachable segment) otherwise we have to use a jalr
 2257     // which loads the absolute address into a register.
 2258     address entry = (address)$meth$$method;
 2259     CodeBlob *cb = CodeCache::find_blob(entry);
 2260     if (cb != NULL) {
 2261       address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
 2262       if (call == NULL) {
 2263         ciEnv::current()->record_failure("CodeCache is full");
 2264         return;
 2265       }
 2266     } else {
 2267       Label retaddr;
 2268       __ la(t1, retaddr);
 2269       __ la(t0, RuntimeAddress(entry));
 2270       // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
 2271       __ addi(sp, sp, -2 * wordSize);
 2272       __ sd(zr, Address(sp));
 2273       __ sd(t1, Address(sp, wordSize));
 2274       __ jalr(t0);
 2275       __ bind(retaddr);
 2276       __ addi(sp, sp, 2 * wordSize);
 2277     }
 2278   %}
 2279 
 2280   // using the cr register as the bool result: 0 for success; others failed.
 2281   enc_class riscv64_enc_fast_lock(iRegI_R6 cr, iRegP object, iRegP box, iRegP tmp, iRegP tmp2) %{
 2282     C2_MacroAssembler _masm(&cbuf);
 2283     Register flag = as_Register($cr$$reg);
 2284     Register oop = as_Register($object$$reg);
 2285     Register box = as_Register($box$$reg);
 2286     Register disp_hdr = as_Register($tmp$$reg);
 2287     Register tmp = as_Register($tmp2$$reg);
 2288     Label cont;
 2289     Label object_has_monitor;
 2290 
 2291     assert_different_registers(oop, box, tmp, disp_hdr, t0);
 2292 
 2293     // Load markWord from object into displaced_header.
 2294     __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
 2295 
 2296     if (DiagnoseSyncOnValueBasedClasses != 0) {
 2297       __ load_klass(flag, oop);
 2298       __ lwu(flag, Address(flag, Klass::access_flags_offset()));
 2299       __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
 2300       __ bnez(flag, cont, true /* is_far */);
 2301     }
 2302 
 2303     // Check for existing monitor
 2304     __ andi(t0, disp_hdr, markWord::monitor_value);
 2305     __ bnez(t0, object_has_monitor);
 2306 
 2307     // Set tmp to be (markWord of object | UNLOCK_VALUE).
 2308     __ ori(tmp, disp_hdr, markWord::unlocked_value);
 2309 
 2310     // Initialize the box. (Must happen before we update the object mark!)
 2311     __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2312 
 2313     // Compare object markWord with an unlocked value (tmp) and if
 2314     // equal exchange the stack address of our box with object markWord.
 2315     // On failure disp_hdr contains the possibly locked markWord.
 2316     __ cmpxchg(/*memory address*/oop, /*expected value*/tmp, /*new value*/box, Assembler::int64, Assembler::aq,
 2317                Assembler::rl, /*result*/disp_hdr);
 2318     __ mv(flag, zr);
 2319     __ beq(disp_hdr, tmp, cont); // prepare zero flag and goto cont if we won the cas
 2320 
 2321     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2322 
 2323     // If the compare-and-exchange succeeded, then we found an unlocked
 2324     // object, will have now locked it will continue at label cont
 2325     // We did not see an unlocked object so try the fast recursive case.
 2326 
 2327     // Check if the owner is self by comparing the value in the
 2328     // markWord of object (disp_hdr) with the stack pointer.
 2329     __ sub(disp_hdr, disp_hdr, sp);
 2330     __ li(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markWord::lock_mask_in_place));
 2331     // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont,
 2332     // hence we can store 0 as the displaced header in the box, which indicates that it is a
 2333     // recursive lock.
 2334     __ andr(tmp/*==0?*/, disp_hdr, tmp);
 2335     __ sd(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2336     __ mv(flag, tmp); // we can use the value of tmp as the result here
 2337 
 2338     __ j(cont);
 2339 
 2340     // Handle existing monitor.
 2341     __ bind(object_has_monitor);
 2342     // The object's monitor m is unlocked iff m->owner == NULL,
 2343     // otherwise m->owner may contain a thread or a stack address.
 2344     //
 2345     // Try to CAS m->owner from NULL to current thread.
 2346     __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
 2347     __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
 2348              Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
 2349 
 2350     // Store a non-null value into the box to avoid looking like a re-entrant
 2351     // lock. The fast-path monitor unlock code checks for
 2352     // markWord::monitor_value so use markWord::unused_mark which has the
 2353     // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
 2354     __ mv(tmp, (address)markWord::unused_mark().value());
 2355     __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2356 
 2357     __ bind(cont);
 2358   %}
 2359 
 2360   // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
 2361   enc_class riscv64_enc_fast_unlock(iRegI_R6 cr, iRegP object, iRegP box, iRegP tmp, iRegP tmp2) %{
 2362     C2_MacroAssembler _masm(&cbuf);
 2363     Register flag = as_Register($cr$$reg);
 2364     Register oop = as_Register($object$$reg);
 2365     Register box = as_Register($box$$reg);
 2366     Register disp_hdr = as_Register($tmp$$reg);
 2367     Register tmp = as_Register($tmp2$$reg);
 2368     Label cont;
 2369     Label object_has_monitor;
 2370 
 2371     assert_different_registers(oop, box, tmp, disp_hdr, flag);
 2372 
 2373     // Find the lock address and load the displaced header from the stack.
 2374     __ ld(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2375 
 2376     // If the displaced header is 0, we have a recursive unlock.
 2377     __ mv(flag, disp_hdr);
 2378     __ beqz(disp_hdr, cont);
 2379 
 2380     // Handle existing monitor.
 2381     __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
 2382     __ andi(t0, disp_hdr, markWord::monitor_value);
 2383     __ bnez(t0, object_has_monitor);
 2384 
 2385     // Check if it is still a light weight lock, this is true if we
 2386     // see the stack address of the basicLock in the markWord of the
 2387     // object.
 2388 
 2389     __ cmpxchg(/*memory address*/oop, /*expected value*/box, /*new value*/disp_hdr, Assembler::int64, Assembler::relaxed,
 2390                Assembler::rl, /*result*/tmp);
 2391     __ xorr(flag, box, tmp); // box == tmp if cas succeeds
 2392     __ j(cont);
 2393 
 2394     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2395 
 2396     // Handle existing monitor.
 2397     __ bind(object_has_monitor);
 2398     STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
 2399     __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
 2400     __ ld(flag, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
 2401     __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2402     __ xorr(flag, flag, xthread); // Will be 0 if we are the owner.
 2403     __ orr(flag, flag, disp_hdr); // Will be 0 if there are 0 recursions
 2404     __ bnez(flag, cont);
 2405 
 2406     __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
 2407     __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
 2408     __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
 2409     __ bnez(flag, cont);
 2410     // need a release store here
 2411     __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
 2412     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 2413     __ sd(zr, Address(tmp)); // set unowned
 2414 
 2415     __ bind(cont);
 2416   %}
 2417 
 2418   // arithmetic encodings
 2419 
 2420   enc_class riscv64_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
 2421     C2_MacroAssembler _masm(&cbuf);
 2422     Register dst_reg = as_Register($dst$$reg);
 2423     Register src1_reg = as_Register($src1$$reg);
 2424     Register src2_reg = as_Register($src2$$reg);
 2425     __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
 2426   %}
 2427 
 2428   enc_class riscv64_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
 2429     C2_MacroAssembler _masm(&cbuf);
 2430     Register dst_reg = as_Register($dst$$reg);
 2431     Register src1_reg = as_Register($src1$$reg);
 2432     Register src2_reg = as_Register($src2$$reg);
 2433     __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
 2434   %}
 2435 
 2436   enc_class riscv64_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
 2437     C2_MacroAssembler _masm(&cbuf);
 2438     Register dst_reg = as_Register($dst$$reg);
 2439     Register src1_reg = as_Register($src1$$reg);
 2440     Register src2_reg = as_Register($src2$$reg);
 2441     __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
 2442   %}
 2443 
 2444   enc_class riscv64_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
 2445     C2_MacroAssembler _masm(&cbuf);
 2446     Register dst_reg = as_Register($dst$$reg);
 2447     Register src1_reg = as_Register($src1$$reg);
 2448     Register src2_reg = as_Register($src2$$reg);
 2449     __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
 2450   %}
 2451 
 2452   enc_class riscv64_enc_tail_call(iRegP jump_target) %{
 2453     C2_MacroAssembler _masm(&cbuf);
 2454     Register target_reg = as_Register($jump_target$$reg);
 2455     __ jr(target_reg);
 2456   %}
 2457 
 2458   enc_class riscv64_enc_tail_jmp(iRegP jump_target) %{
 2459     C2_MacroAssembler _masm(&cbuf);
 2460     Register target_reg = as_Register($jump_target$$reg);
 2461     // exception oop should be in x10
 2462     // ret addr has been popped into lr
 2463     // callee expects it in x13
 2464     __ mv(x13, lr);
 2465     __ jr(target_reg);
 2466   %}
 2467 
 2468   enc_class riscv64_enc_rethrow() %{
 2469     C2_MacroAssembler _masm(&cbuf);
 2470     __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
 2471   %}
 2472 
 2473   enc_class riscv64_enc_ret() %{
 2474     C2_MacroAssembler _masm(&cbuf);
 2475     __ ret();
 2476   %}
 2477 
 2478 %}
 2479 
 2480 //----------FRAME--------------------------------------------------------------
 2481 // Definition of frame structure and management information.
 2482 //
 2483 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2484 //                             |   (to get allocators register number
 2485 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2486 //  r   CALLER     |        |
 2487 //  o     |        +--------+      pad to even-align allocators stack-slot
 2488 //  w     V        |  pad0  |        numbers; owned by CALLER
 2489 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2490 //  h     ^        |   in   |  5
 2491 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2492 //  |     |        |        |  3
 2493 //  |     |        +--------+
 2494 //  V     |        | old out|      Empty on Intel, window on Sparc
 2495 //        |    old |preserve|      Must be even aligned.
 2496 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2497 //        |        |   in   |  3   area for Intel ret address
 2498 //     Owned by    |preserve|      Empty on Sparc.
 2499 //       SELF      +--------+
 2500 //        |        |  pad2  |  2   pad to align old SP
 2501 //        |        +--------+  1
 2502 //        |        | locks  |  0
 2503 //        |        +--------+----> OptoReg::stack0(), even aligned
 2504 //        |        |  pad1  | 11   pad to align new SP
 2505 //        |        +--------+
 2506 //        |        |        | 10
 2507 //        |        | spills |  9   spills
 2508 //        V        |        |  8   (pad0 slot for callee)
 2509 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2510 //        ^        |  out   |  7
 2511 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2512 //     Owned by    +--------+
 2513 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2514 //        |    new |preserve|      Must be even-aligned.
 2515 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2516 //        |        |        |
 2517 //
 2518 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2519 //         known from SELF's arguments and the Java calling convention.
 2520 //         Region 6-7 is determined per call site.
 2521 // Note 2: If the calling convention leaves holes in the incoming argument
 2522 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2523 //         are owned by the CALLEE.  Holes should not be nessecary in the
 2524 //         incoming area, as the Java calling convention is completely under
 2525 //         the control of the AD file.  Doubles can be sorted and packed to
 2526 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
 2527 //         varargs C calling conventions.
 2528 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2529 //         even aligned with pad0 as needed.
 2530 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2531 //           (the latter is true on Intel but is it false on RISCV64?)
 2532 //         region 6-11 is even aligned; it may be padded out more so that
 2533 //         the region from SP to FP meets the minimum stack alignment.
 2534 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2535 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2536 //         SP meets the minimum alignment.
 2537 
 2538 frame %{
 2539   // These three registers define part of the calling convention
 2540   // between compiled code and the interpreter.
 2541 
 2542   // Inline Cache Register or methodOop for I2C.
 2543   inline_cache_reg(R31);
 2544 
 2545   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
 2546   cisc_spilling_operand_name(indOffset);
 2547 
 2548   // Number of stack slots consumed by locking an object
 2549   // generate Compile::sync_stack_slots
 2550   // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
 2551   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 2552 
 2553   // Compiled code's Frame Pointer
 2554   frame_pointer(R2);
 2555 
 2556   // Interpreter stores its frame pointer in a register which is
 2557   // stored to the stack by I2CAdaptors.
 2558   // I2CAdaptors convert from interpreted java to compiled java.
 2559   interpreter_frame_pointer(R8);
 2560 
 2561   // Stack alignment requirement
 2562   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2563 
 2564   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2565   // for calls to C.  Supports the var-args backing area for register parms.
 2566   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
 2567 
 2568   // The after-PROLOG location of the return address.  Location of
 2569   // return address specifies a type (REG or STACK) and a number
 2570   // representing the register number (i.e. - use a register name) or
 2571   // stack slot.
 2572   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2573   // Otherwise, it is above the locks and verification slot and alignment word
 2574   // TODO this may well be correct but need to check why that - 2 is there
 2575   // ppc port uses 0 but we definitely need to allow for fixed_slots
 2576   // which folds in the space used for monitors
 2577   return_addr(STACK - 2 +
 2578               align_up((Compile::current()->in_preserve_stack_slots() +
 2579                         Compile::current()->fixed_slots()),
 2580                        stack_alignment_in_slots()));
 2581 
 2582   // Location of compiled Java return values.  Same as C for now.
 2583   return_value
 2584   %{
 2585     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2586            "only return normal values");
 2587 
 2588     static const int lo[Op_RegL + 1] = { // enum name
 2589       0,                                 // Op_Node
 2590       0,                                 // Op_Set
 2591       R10_num,                           // Op_RegN
 2592       R10_num,                           // Op_RegI
 2593       R10_num,                           // Op_RegP
 2594       F10_num,                           // Op_RegF
 2595       F10_num,                           // Op_RegD
 2596       R10_num                            // Op_RegL
 2597     };
 2598 
 2599     static const int hi[Op_RegL + 1] = { // enum name
 2600       0,                                 // Op_Node
 2601       0,                                 // Op_Set
 2602       OptoReg::Bad,                      // Op_RegN
 2603       OptoReg::Bad,                      // Op_RegI
 2604       R10_H_num,                         // Op_RegP
 2605       OptoReg::Bad,                      // Op_RegF
 2606       F10_H_num,                         // Op_RegD
 2607       R10_H_num                          // Op_RegL
 2608     };
 2609 
 2610     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2611   %}
 2612 %}
 2613 
 2614 //----------ATTRIBUTES---------------------------------------------------------
 2615 //----------Operand Attributes-------------------------------------------------
 2616 op_attrib op_cost(1);        // Required cost attribute
 2617 
 2618 //----------Instruction Attributes---------------------------------------------
 2619 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
 2620 ins_attrib ins_size(32);        // Required size attribute (in bits)
 2621 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2622                                 // a non-matching short branch variant
 2623                                 // of some long branch?
 2624 ins_attrib ins_alignment(4);    // Required alignment attribute (must
 2625                                 // be a power of 2) specifies the
 2626                                 // alignment that some part of the
 2627                                 // instruction (not necessarily the
 2628                                 // start) requires.  If > 1, a
 2629                                 // compute_padding() function must be
 2630                                 // provided for the instruction
 2631 
 2632 //----------OPERANDS-----------------------------------------------------------
 2633 // Operand definitions must precede instruction definitions for correct parsing
 2634 // in the ADLC because operands constitute user defined types which are used in
 2635 // instruction definitions.
 2636 
 2637 // R6(t1) register, used as output of compare instructions
 2638 operand iRegI_R6() %{
 2639   constraint(ALLOC_IN_RC(int_r6_reg));
 2640   match(RegI);
 2641 
 2642   format %{ "t1" %}
 2643   interface(REG_INTER);
 2644 %}
 2645 
 2646 operand iRegL_R6() %{
 2647   constraint(ALLOC_IN_RC(r6_reg));
 2648   match(RegL);
 2649 
 2650   format %{ "t1" %}
 2651   interface(REG_INTER);
 2652 %}
 2653 
 2654 //----------Simple Operands----------------------------------------------------
 2655 
 2656 // Integer operands 32 bit
 2657 // 32 bit immediate
 2658 operand immI()
 2659 %{
 2660   match(ConI);
 2661 
 2662   op_cost(0);
 2663   format %{ %}
 2664   interface(CONST_INTER);
 2665 %}
 2666 
 2667 // 32 bit zero
 2668 operand immI0()
 2669 %{
 2670   predicate(n->get_int() == 0);
 2671   match(ConI);
 2672 
 2673   op_cost(0);
 2674   format %{ %}
 2675   interface(CONST_INTER);
 2676 %}
 2677 
 2678 // 32 bit unit increment
 2679 operand immI_1()
 2680 %{
 2681   predicate(n->get_int() == 1);
 2682   match(ConI);
 2683 
 2684   op_cost(0);
 2685   format %{ %}
 2686   interface(CONST_INTER);
 2687 %}
 2688 
 2689 // 32 bit unit decrement
 2690 operand immI_M1()
 2691 %{
 2692   predicate(n->get_int() == -1);
 2693   match(ConI);
 2694 
 2695   op_cost(0);
 2696   format %{ %}
 2697   interface(CONST_INTER);
 2698 %}
 2699 
 2700 // Unsigned Integer Immediate:  6-bit int, greater than 32
 2701 operand uimmI6_ge32() %{
 2702   predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
 2703   match(ConI);
 2704   op_cost(0);
 2705   format %{ %}
 2706   interface(CONST_INTER);
 2707 %}
 2708 
 2709 operand immI_le_4()
 2710 %{
 2711   predicate(n->get_int() <= 4);
 2712   match(ConI);
 2713 
 2714   op_cost(0);
 2715   format %{ %}
 2716   interface(CONST_INTER);
 2717 %}
 2718 
 2719 operand immI_31()
 2720 %{
 2721   predicate(n->get_int() == 31);
 2722   match(ConI);
 2723 
 2724   op_cost(0);
 2725   format %{ %}
 2726   interface(CONST_INTER);
 2727 %}
 2728 
 2729 operand immI_63()
 2730 %{
 2731   predicate(n->get_int() == 63);
 2732   match(ConI);
 2733 
 2734   op_cost(0);
 2735   format %{ %}
 2736   interface(CONST_INTER);
 2737 %}
 2738 
 2739 // 32 bit integer valid for add immediate
 2740 operand immIAdd()
 2741 %{
 2742   predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
 2743   match(ConI);
 2744   op_cost(0);
 2745   format %{ %}
 2746   interface(CONST_INTER);
 2747 %}
 2748 
 2749 // 32 bit integer valid for sub immediate
 2750 operand immISub()
 2751 %{
 2752   predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
 2753   match(ConI);
 2754   op_cost(0);
 2755   format %{ %}
 2756   interface(CONST_INTER);
 2757 %}
 2758 
 2759 // 5 bit signed value.
 2760 operand immI5()
 2761 %{
 2762   predicate(n->get_int() <= 15 && n->get_int() >= -16);
 2763   match(ConI);
 2764 
 2765   op_cost(0);
 2766   format %{ %}
 2767   interface(CONST_INTER);
 2768 %}
 2769 
 2770 // 5 bit signed value (simm5)
 2771 operand immL5()
 2772 %{
 2773   predicate(n->get_long() <= 15 && n->get_long() >= -16);
 2774   match(ConL);
 2775 
 2776   op_cost(0);
 2777   format %{ %}
 2778   interface(CONST_INTER);
 2779 %}
 2780 
 2781 // Integer operands 64 bit
 2782 // 64 bit immediate
 2783 operand immL()
 2784 %{
 2785   match(ConL);
 2786 
 2787   op_cost(0);
 2788   format %{ %}
 2789   interface(CONST_INTER);
 2790 %}
 2791 
 2792 // 64 bit zero
 2793 operand immL0()
 2794 %{
 2795   predicate(n->get_long() == 0);
 2796   match(ConL);
 2797 
 2798   op_cost(0);
 2799   format %{ %}
 2800   interface(CONST_INTER);
 2801 %}
 2802 
 2803 // Pointer operands
 2804 // Pointer Immediate
 2805 operand immP()
 2806 %{
 2807   match(ConP);
 2808 
 2809   op_cost(0);
 2810   format %{ %}
 2811   interface(CONST_INTER);
 2812 %}
 2813 
 2814 // NULL Pointer Immediate
 2815 operand immP0()
 2816 %{
 2817   predicate(n->get_ptr() == 0);
 2818   match(ConP);
 2819 
 2820   op_cost(0);
 2821   format %{ %}
 2822   interface(CONST_INTER);
 2823 %}
 2824 
 2825 // Pointer Immediate One
 2826 // this is used in object initialization (initial object header)
 2827 operand immP_1()
 2828 %{
 2829   predicate(n->get_ptr() == 1);
 2830   match(ConP);
 2831 
 2832   op_cost(0);
 2833   format %{ %}
 2834   interface(CONST_INTER);
 2835 %}
 2836 
 2837 // Card Table Byte Map Base
 2838 operand immByteMapBase()
 2839 %{
 2840   // Get base of card map
 2841   predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
 2842             (CardTable::CardValue*)n->get_ptr() ==
 2843              ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
 2844   match(ConP);
 2845 
 2846   op_cost(0);
 2847   format %{ %}
 2848   interface(CONST_INTER);
 2849 %}
 2850 
 2851 // Long Immediate: low 32-bit mask
 2852 operand immL_32bits()
 2853 %{
 2854   predicate(n->get_long() == 0xFFFFFFFFL);
 2855   match(ConL);
 2856   op_cost(0);
 2857   format %{ %}
 2858   interface(CONST_INTER);
 2859 %}
 2860 
 2861 // 64 bit unit decrement
 2862 operand immL_M1()
 2863 %{
 2864   predicate(n->get_long() == -1);
 2865   match(ConL);
 2866 
 2867   op_cost(0);
 2868   format %{ %}
 2869   interface(CONST_INTER);
 2870 %}
 2871 
 2872 
 2873 // 32 bit offset of pc in thread anchor
 2874 
 2875 operand immL_pc_off()
 2876 %{
 2877   predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
 2878                              in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
 2879   match(ConL);
 2880 
 2881   op_cost(0);
 2882   format %{ %}
 2883   interface(CONST_INTER);
 2884 %}
 2885 
 2886 // 64 bit integer valid for add immediate
 2887 operand immLAdd()
 2888 %{
 2889   predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
 2890   match(ConL);
 2891   op_cost(0);
 2892   format %{ %}
 2893   interface(CONST_INTER);
 2894 %}
 2895 
 2896 // 64 bit integer valid for sub immediate
 2897 operand immLSub()
 2898 %{
 2899   predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
 2900   match(ConL);
 2901   op_cost(0);
 2902   format %{ %}
 2903   interface(CONST_INTER);
 2904 %}
 2905 
 2906 // Narrow pointer operands
 2907 // Narrow Pointer Immediate
 2908 operand immN()
 2909 %{
 2910   match(ConN);
 2911 
 2912   op_cost(0);
 2913   format %{ %}
 2914   interface(CONST_INTER);
 2915 %}
 2916 
 2917 // Narrow NULL Pointer Immediate
 2918 operand immN0()
 2919 %{
 2920   predicate(n->get_narrowcon() == 0);
 2921   match(ConN);
 2922 
 2923   op_cost(0);
 2924   format %{ %}
 2925   interface(CONST_INTER);
 2926 %}
 2927 
 2928 operand immNKlass()
 2929 %{
 2930   match(ConNKlass);
 2931 
 2932   op_cost(0);
 2933   format %{ %}
 2934   interface(CONST_INTER);
 2935 %}
 2936 
 2937 // Float and Double operands
 2938 // Double Immediate
 2939 operand immD()
 2940 %{
 2941   match(ConD);
 2942   op_cost(0);
 2943   format %{ %}
 2944   interface(CONST_INTER);
 2945 %}
 2946 
 2947 // Double Immediate: +0.0d
 2948 operand immD0()
 2949 %{
 2950   predicate(jlong_cast(n->getd()) == 0);
 2951   match(ConD);
 2952 
 2953   op_cost(0);
 2954   format %{ %}
 2955   interface(CONST_INTER);
 2956 %}
 2957 
 2958 // Float Immediate
 2959 operand immF()
 2960 %{
 2961   match(ConF);
 2962   op_cost(0);
 2963   format %{ %}
 2964   interface(CONST_INTER);
 2965 %}
 2966 
 2967 // Float Immediate: +0.0f.
 2968 operand immF0()
 2969 %{
 2970   predicate(jint_cast(n->getf()) == 0);
 2971   match(ConF);
 2972 
 2973   op_cost(0);
 2974   format %{ %}
 2975   interface(CONST_INTER);
 2976 %}
 2977 
 2978 operand immIOffset()
 2979 %{
 2980   predicate(is_imm_in_range(n->get_int(), 12, 0));
 2981   match(ConI);
 2982   op_cost(0);
 2983   format %{ %}
 2984   interface(CONST_INTER);
 2985 %}
 2986 
 2987 operand immLOffset()
 2988 %{
 2989   predicate(is_imm_in_range(n->get_long(), 12, 0));
 2990   match(ConL);
 2991   op_cost(0);
 2992   format %{ %}
 2993   interface(CONST_INTER);
 2994 %}
 2995 
 2996 // Integer 32 bit Register Operands
 2997 operand iRegI()
 2998 %{
 2999   constraint(ALLOC_IN_RC(any_reg32));
 3000   match(RegI);
 3001   match(iRegINoSp);
 3002   op_cost(0);
 3003   format %{ %}
 3004   interface(REG_INTER);
 3005 %}
 3006 
 3007 // Integer 32 bit Register not Special
 3008 operand iRegINoSp()
 3009 %{
 3010   constraint(ALLOC_IN_RC(no_special_reg32));
 3011   match(RegI);
 3012   op_cost(0);
 3013   format %{ %}
 3014   interface(REG_INTER);
 3015 %}
 3016 
 3017 // Register R10 only
 3018 operand iRegI_R10()
 3019 %{
 3020   constraint(ALLOC_IN_RC(int_r10_reg));
 3021   match(RegI);
 3022   match(iRegINoSp);
 3023   op_cost(0);
 3024   format %{ %}
 3025   interface(REG_INTER);
 3026 %}
 3027 
 3028 // Register R12 only
 3029 operand iRegI_R12()
 3030 %{
 3031   constraint(ALLOC_IN_RC(int_r12_reg));
 3032   match(RegI);
 3033   match(iRegINoSp);
 3034   op_cost(0);
 3035   format %{ %}
 3036   interface(REG_INTER);
 3037 %}
 3038 
 3039 // Register R13 only
 3040 operand iRegI_R13()
 3041 %{
 3042   constraint(ALLOC_IN_RC(int_r13_reg));
 3043   match(RegI);
 3044   match(iRegINoSp);
 3045   op_cost(0);
 3046   format %{ %}
 3047   interface(REG_INTER);
 3048 %}
 3049 
 3050 // Register R14 only
 3051 operand iRegI_R14()
 3052 %{
 3053   constraint(ALLOC_IN_RC(int_r14_reg));
 3054   match(RegI);
 3055   match(iRegINoSp);
 3056   op_cost(0);
 3057   format %{ %}
 3058   interface(REG_INTER);
 3059 %}
 3060 
 3061 // Integer 64 bit Register Operands
 3062 operand iRegL()
 3063 %{
 3064   constraint(ALLOC_IN_RC(any_reg));
 3065   match(RegL);
 3066   match(iRegLNoSp);
 3067   op_cost(0);
 3068   format %{ %}
 3069   interface(REG_INTER);
 3070 %}
 3071 
 3072 // Integer 64 bit Register not Special
 3073 operand iRegLNoSp()
 3074 %{
 3075   constraint(ALLOC_IN_RC(no_special_reg));
 3076   match(RegL);
 3077   match(iRegL_R10);
 3078   format %{ %}
 3079   interface(REG_INTER);
 3080 %}
 3081 
 3082 // Long 64 bit Register R28 only
 3083 operand iRegL_R28()
 3084 %{
 3085   constraint(ALLOC_IN_RC(r28_reg));
 3086   match(RegL);
 3087   match(iRegLNoSp);
 3088   op_cost(0);
 3089   format %{ %}
 3090   interface(REG_INTER);
 3091 %}
 3092 
 3093 // Long 64 bit Register R29 only
 3094 operand iRegL_R29()
 3095 %{
 3096   constraint(ALLOC_IN_RC(r29_reg));
 3097   match(RegL);
 3098   match(iRegLNoSp);
 3099   op_cost(0);
 3100   format %{ %}
 3101   interface(REG_INTER);
 3102 %}
 3103 
 3104 // Long 64 bit Register R30 only
 3105 operand iRegL_R30()
 3106 %{
 3107   constraint(ALLOC_IN_RC(r30_reg));
 3108   match(RegL);
 3109   match(iRegLNoSp);
 3110   op_cost(0);
 3111   format %{ %}
 3112   interface(REG_INTER);
 3113 %}
 3114 
 3115 // Pointer Register Operands
 3116 // Pointer Register
 3117 operand iRegP()
 3118 %{
 3119   constraint(ALLOC_IN_RC(ptr_reg));
 3120   match(RegP);
 3121   match(iRegPNoSp);
 3122   match(iRegP_R10);
 3123   match(javaThread_RegP);
 3124   op_cost(0);
 3125   format %{ %}
 3126   interface(REG_INTER);
 3127 %}
 3128 
 3129 // Pointer 64 bit Register not Special
 3130 operand iRegPNoSp()
 3131 %{
 3132   constraint(ALLOC_IN_RC(no_special_ptr_reg));
 3133   match(RegP);
 3134   op_cost(0);
 3135   format %{ %}
 3136   interface(REG_INTER);
 3137 %}
 3138 
 3139 operand iRegP_R10()
 3140 %{
 3141   constraint(ALLOC_IN_RC(r10_reg));
 3142   match(RegP);
 3143   // match(iRegP);
 3144   match(iRegPNoSp);
 3145   op_cost(0);
 3146   format %{ %}
 3147   interface(REG_INTER);
 3148 %}
 3149 
 3150 // Pointer 64 bit Register R11 only
 3151 operand iRegP_R11()
 3152 %{
 3153   constraint(ALLOC_IN_RC(r11_reg));
 3154   match(RegP);
 3155   match(iRegPNoSp);
 3156   op_cost(0);
 3157   format %{ %}
 3158   interface(REG_INTER);
 3159 %}
 3160 
 3161 operand iRegP_R12()
 3162 %{
 3163   constraint(ALLOC_IN_RC(r12_reg));
 3164   match(RegP);
 3165   // match(iRegP);
 3166   match(iRegPNoSp);
 3167   op_cost(0);
 3168   format %{ %}
 3169   interface(REG_INTER);
 3170 %}
 3171 
 3172 // Pointer 64 bit Register R13 only
 3173 operand iRegP_R13()
 3174 %{
 3175   constraint(ALLOC_IN_RC(r13_reg));
 3176   match(RegP);
 3177   match(iRegPNoSp);
 3178   op_cost(0);
 3179   format %{ %}
 3180   interface(REG_INTER);
 3181 %}
 3182 
 3183 operand iRegP_R14()
 3184 %{
 3185   constraint(ALLOC_IN_RC(r14_reg));
 3186   match(RegP);
 3187   // match(iRegP);
 3188   match(iRegPNoSp);
 3189   op_cost(0);
 3190   format %{ %}
 3191   interface(REG_INTER);
 3192 %}
 3193 
 3194 operand iRegP_R15()
 3195 %{
 3196   constraint(ALLOC_IN_RC(r15_reg));
 3197   match(RegP);
 3198   // match(iRegP);
 3199   match(iRegPNoSp);
 3200   op_cost(0);
 3201   format %{ %}
 3202   interface(REG_INTER);
 3203 %}
 3204 
 3205 operand iRegP_R16()
 3206 %{
 3207   constraint(ALLOC_IN_RC(r16_reg));
 3208   match(RegP);
 3209   // match(iRegP);
 3210   match(iRegPNoSp);
 3211   op_cost(0);
 3212   format %{ %}
 3213   interface(REG_INTER);
 3214 %}
 3215 
 3216 // Pointer 64 bit Register R28 only
 3217 operand iRegP_R28()
 3218 %{
 3219   constraint(ALLOC_IN_RC(r28_reg));
 3220   match(RegP);
 3221   match(iRegPNoSp);
 3222   op_cost(0);
 3223   format %{ %}
 3224   interface(REG_INTER);
 3225 %}
 3226 
 3227 // Pointer Register Operands
 3228 // Narrow Pointer Register
 3229 operand iRegN()
 3230 %{
 3231   constraint(ALLOC_IN_RC(any_reg32));
 3232   match(RegN);
 3233   match(iRegNNoSp);
 3234   op_cost(0);
 3235   format %{ %}
 3236   interface(REG_INTER);
 3237 %}
 3238 
 3239 // Integer 64 bit Register not Special
 3240 operand iRegNNoSp()
 3241 %{
 3242   constraint(ALLOC_IN_RC(no_special_reg32));
 3243   match(RegN);
 3244   op_cost(0);
 3245   format %{ %}
 3246   interface(REG_INTER);
 3247 %}
 3248 
 3249 // heap base register -- used for encoding immN0
 3250 operand iRegIHeapbase()
 3251 %{
 3252   constraint(ALLOC_IN_RC(heapbase_reg));
 3253   match(RegI);
 3254   op_cost(0);
 3255   format %{ %}
 3256   interface(REG_INTER);
 3257 %}
 3258 
 3259 // Long 64 bit Register R10 only
 3260 operand iRegL_R10()
 3261 %{
 3262   constraint(ALLOC_IN_RC(r10_reg));
 3263   match(RegL);
 3264   match(iRegLNoSp);
 3265   op_cost(0);
 3266   format %{ %}
 3267   interface(REG_INTER);
 3268 %}
 3269 
 3270 // Float Register
 3271 // Float register operands
 3272 operand fRegF()
 3273 %{
 3274   constraint(ALLOC_IN_RC(float_reg));
 3275   match(RegF);
 3276 
 3277   op_cost(0);
 3278   format %{ %}
 3279   interface(REG_INTER);
 3280 %}
 3281 
 3282 // Double Register
 3283 // Double register operands
 3284 operand fRegD()
 3285 %{
 3286   constraint(ALLOC_IN_RC(double_reg));
 3287   match(RegD);
 3288 
 3289   op_cost(0);
 3290   format %{ %}
 3291   interface(REG_INTER);
 3292 %}
 3293 
 3294 // Generic vector class. This will be used for
 3295 // all vector operands.
 3296 operand vReg()
 3297 %{
 3298   constraint(ALLOC_IN_RC(vectora_reg));
 3299   match(VecA);
 3300   op_cost(0);
 3301   format %{ %}
 3302   interface(REG_INTER);
 3303 %}
 3304 
 3305 operand vReg_V1()
 3306 %{
 3307   constraint(ALLOC_IN_RC(v1_reg));
 3308   match(VecA);
 3309   match(vReg);
 3310   op_cost(0);
 3311   format %{ %}
 3312   interface(REG_INTER);
 3313 %}
 3314 
 3315 operand vReg_V2()
 3316 %{
 3317   constraint(ALLOC_IN_RC(v2_reg));
 3318   match(VecA);
 3319   match(vReg);
 3320   op_cost(0);
 3321   format %{ %}
 3322   interface(REG_INTER);
 3323 %}
 3324 
 3325 operand vReg_V3()
 3326 %{
 3327   constraint(ALLOC_IN_RC(v3_reg));
 3328   match(VecA);
 3329   match(vReg);
 3330   op_cost(0);
 3331   format %{ %}
 3332   interface(REG_INTER);
 3333 %}
 3334 
 3335 operand vReg_V4()
 3336 %{
 3337   constraint(ALLOC_IN_RC(v4_reg));
 3338   match(VecA);
 3339   match(vReg);
 3340   op_cost(0);
 3341   format %{ %}
 3342   interface(REG_INTER);
 3343 %}
 3344 
 3345 operand vReg_V5()
 3346 %{
 3347   constraint(ALLOC_IN_RC(v5_reg));
 3348   match(VecA);
 3349   match(vReg);
 3350   op_cost(0);
 3351   format %{ %}
 3352   interface(REG_INTER);
 3353 %}
 3354 
 3355 // Java Thread Register
 3356 operand javaThread_RegP(iRegP reg)
 3357 %{
 3358   constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
 3359   match(reg);
 3360   op_cost(0);
 3361   format %{ %}
 3362   interface(REG_INTER);
 3363 %}
 3364 
 3365 //----------Memory Operands----------------------------------------------------
 3366 // RISCV has only base_plus_offset and literal address mode, so no need to use
 3367 // index and scale. Here set index as 0xffffffff and scale as 0x0.
 3368 operand indirect(iRegP reg)
 3369 %{
 3370   constraint(ALLOC_IN_RC(ptr_reg));
 3371   match(reg);
 3372   op_cost(0);
 3373   format %{ "[$reg]" %}
 3374   interface(MEMORY_INTER) %{
 3375     base($reg);
 3376     index(0xffffffff);
 3377     scale(0x0);
 3378     disp(0x0);
 3379   %}
 3380 %}
 3381 
 3382 operand indOffI(iRegP reg, immIOffset off)
 3383 %{
 3384   constraint(ALLOC_IN_RC(ptr_reg));
 3385   match(AddP reg off);
 3386   op_cost(0);
 3387   format %{ "[$reg, $off]" %}
 3388   interface(MEMORY_INTER) %{
 3389     base($reg);
 3390     index(0xffffffff);
 3391     scale(0x0);
 3392     disp($off);
 3393   %}
 3394 %}
 3395 
 3396 operand indOffL(iRegP reg, immLOffset off)
 3397 %{
 3398   constraint(ALLOC_IN_RC(ptr_reg));
 3399   match(AddP reg off);
 3400   op_cost(0);
 3401   format %{ "[$reg, $off]" %}
 3402   interface(MEMORY_INTER) %{
 3403     base($reg);
 3404     index(0xffffffff);
 3405     scale(0x0);
 3406     disp($off);
 3407   %}
 3408 %}
 3409 
 3410 operand indirectN(iRegN reg)
 3411 %{
 3412   predicate(CompressedOops::shift() == 0);
 3413   constraint(ALLOC_IN_RC(ptr_reg));
 3414   match(DecodeN reg);
 3415   op_cost(0);
 3416   format %{ "[$reg]\t# narrow" %}
 3417   interface(MEMORY_INTER) %{
 3418     base($reg);
 3419     index(0xffffffff);
 3420     scale(0x0);
 3421     disp(0x0);
 3422   %}
 3423 %}
 3424 
 3425 operand indOffIN(iRegN reg, immIOffset off)
 3426 %{
 3427   predicate(CompressedOops::shift() == 0);
 3428   constraint(ALLOC_IN_RC(ptr_reg));
 3429   match(AddP (DecodeN reg) off);
 3430   op_cost(0);
 3431   format %{ "[$reg, $off]\t# narrow" %}
 3432   interface(MEMORY_INTER) %{
 3433     base($reg);
 3434     index(0xffffffff);
 3435     scale(0x0);
 3436     disp($off);
 3437   %}
 3438 %}
 3439 
 3440 operand indOffLN(iRegN reg, immLOffset off)
 3441 %{
 3442   predicate(CompressedOops::shift() == 0);
 3443   constraint(ALLOC_IN_RC(ptr_reg));
 3444   match(AddP (DecodeN reg) off);
 3445   op_cost(0);
 3446   format %{ "[$reg, $off]\t# narrow" %}
 3447   interface(MEMORY_INTER) %{
 3448     base($reg);
 3449     index(0xffffffff);
 3450     scale(0x0);
 3451     disp($off);
 3452   %}
 3453 %}
 3454 
 3455 // Riscv64 opto stubs need to write to the pc slot in the thread anchor
 3456 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
 3457 %{
 3458   constraint(ALLOC_IN_RC(ptr_reg));
 3459   match(AddP reg off);
 3460   op_cost(0);
 3461   format %{ "[$reg, $off]" %}
 3462   interface(MEMORY_INTER) %{
 3463     base($reg);
 3464     index(0xffffffff);
 3465     scale(0x0);
 3466     disp($off);
 3467   %}
 3468 %}
 3469 
 3470 
 3471 //----------Special Memory Operands--------------------------------------------
 3472 // Stack Slot Operand - This operand is used for loading and storing temporary
 3473 //                      values on the stack where a match requires a value to
 3474 //                      flow through memory.
 3475 operand stackSlotI(sRegI reg)
 3476 %{
 3477   constraint(ALLOC_IN_RC(stack_slots));
 3478   // No match rule because this operand is only generated in matching
 3479   // match(RegI);
 3480   format %{ "[$reg]" %}
 3481   interface(MEMORY_INTER) %{
 3482     base(0x02);  // RSP
 3483     index(0xffffffff);  // No Index
 3484     scale(0x0);  // No Scale
 3485     disp($reg);  // Stack Offset
 3486   %}
 3487 %}
 3488 
 3489 operand stackSlotF(sRegF reg)
 3490 %{
 3491   constraint(ALLOC_IN_RC(stack_slots));
 3492   // No match rule because this operand is only generated in matching
 3493   // match(RegF);
 3494   format %{ "[$reg]" %}
 3495   interface(MEMORY_INTER) %{
 3496     base(0x02);  // RSP
 3497     index(0xffffffff);  // No Index
 3498     scale(0x0);  // No Scale
 3499     disp($reg);  // Stack Offset
 3500   %}
 3501 %}
 3502 
 3503 operand stackSlotD(sRegD reg)
 3504 %{
 3505   constraint(ALLOC_IN_RC(stack_slots));
 3506   // No match rule because this operand is only generated in matching
 3507   // match(RegD);
 3508   format %{ "[$reg]" %}
 3509   interface(MEMORY_INTER) %{
 3510     base(0x02);  // RSP
 3511     index(0xffffffff);  // No Index
 3512     scale(0x0);  // No Scale
 3513     disp($reg);  // Stack Offset
 3514   %}
 3515 %}
 3516 
 3517 operand stackSlotL(sRegL reg)
 3518 %{
 3519   constraint(ALLOC_IN_RC(stack_slots));
 3520   // No match rule because this operand is only generated in matching
 3521   // match(RegL);
 3522   format %{ "[$reg]" %}
 3523   interface(MEMORY_INTER) %{
 3524     base(0x02);  // RSP
 3525     index(0xffffffff);  // No Index
 3526     scale(0x0);  // No Scale
 3527     disp($reg);  // Stack Offset
 3528   %}
 3529 %}
 3530 
 3531 // Special operand allowing long args to int ops to be truncated for free
 3532 
 3533 operand iRegL2I(iRegL reg) %{
 3534 
 3535   op_cost(0);
 3536 
 3537   match(ConvL2I reg);
 3538 
 3539   format %{ "l2i($reg)" %}
 3540 
 3541   interface(REG_INTER)
 3542 %}
 3543 
 3544 
 3545 // Comparison Operands
 3546 // NOTE: Label is a predefined operand which should not be redefined in
 3547 //       the AD file. It is generically handled within the ADLC.
 3548 
 3549 //----------Conditional Branch Operands----------------------------------------
 3550 // Comparison Op  - This is the operation of the comparison, and is limited to
 3551 //                  the following set of codes:
 3552 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3553 //
 3554 // Other attributes of the comparison, such as unsignedness, are specified
 3555 // by the comparison instruction that sets a condition code flags register.
 3556 // That result is represented by a flags operand whose subtype is appropriate
 3557 // to the unsignedness (etc.) of the comparison.
 3558 //
 3559 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3560 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3561 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 3562 
 3563 
 3564 // used for signed integral comparisons and fp comparisons
 3565 operand cmpOp()
 3566 %{
 3567   match(Bool);
 3568 
 3569   format %{ "" %}
 3570 
 3571   // the values in interface derives from struct BoolTest::mask
 3572   interface(COND_INTER) %{
 3573     equal(0x0, "eq");
 3574     greater(0x1, "gt");
 3575     overflow(0x2, "overflow");
 3576     less(0x3, "lt");
 3577     not_equal(0x4, "ne");
 3578     less_equal(0x5, "le");
 3579     no_overflow(0x6, "no_overflow");
 3580     greater_equal(0x7, "ge");
 3581   %}
 3582 %}
 3583 
 3584 // used for unsigned integral comparisons
 3585 operand cmpOpU()
 3586 %{
 3587   match(Bool);
 3588 
 3589   format %{ "" %}
 3590   // the values in interface derives from struct BoolTest::mask
 3591   interface(COND_INTER) %{
 3592     equal(0x0, "eq");
 3593     greater(0x1, "gtu");
 3594     overflow(0x2, "overflow");
 3595     less(0x3, "ltu");
 3596     not_equal(0x4, "ne");
 3597     less_equal(0x5, "leu");
 3598     no_overflow(0x6, "no_overflow");
 3599     greater_equal(0x7, "geu");
 3600   %}
 3601 %}
 3602 
 3603 // used for certain integral comparisons which can be
 3604 // converted to bxx instructions
 3605 operand cmpOpEqNe()
 3606 %{
 3607   match(Bool);
 3608   op_cost(0);
 3609   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3610             n->as_Bool()->_test._test == BoolTest::eq);
 3611 
 3612   format %{ "" %}
 3613   interface(COND_INTER) %{
 3614     equal(0x0, "eq");
 3615     greater(0x1, "gt");
 3616     overflow(0x2, "overflow");
 3617     less(0x3, "lt");
 3618     not_equal(0x4, "ne");
 3619     less_equal(0x5, "le");
 3620     no_overflow(0x6, "no_overflow");
 3621     greater_equal(0x7, "ge");
 3622   %}
 3623 %}
 3624 
 3625 operand cmpOpULtGe()
 3626 %{
 3627   match(Bool);
 3628   op_cost(0);
 3629   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 3630             n->as_Bool()->_test._test == BoolTest::ge);
 3631 
 3632   format %{ "" %}
 3633   interface(COND_INTER) %{
 3634     equal(0x0, "eq");
 3635     greater(0x1, "gt");
 3636     overflow(0x2, "overflow");
 3637     less(0x3, "lt");
 3638     not_equal(0x4, "ne");
 3639     less_equal(0x5, "le");
 3640     no_overflow(0x6, "no_overflow");
 3641     greater_equal(0x7, "ge");
 3642   %}
 3643 %}
 3644 
 3645 operand cmpOpUEqNeLeGt()
 3646 %{
 3647   match(Bool);
 3648   op_cost(0);
 3649   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3650             n->as_Bool()->_test._test == BoolTest::eq ||
 3651             n->as_Bool()->_test._test == BoolTest::le ||
 3652             n->as_Bool()->_test._test == BoolTest::gt);
 3653 
 3654   format %{ "" %}
 3655   interface(COND_INTER) %{
 3656     equal(0x0, "eq");
 3657     greater(0x1, "gt");
 3658     overflow(0x2, "overflow");
 3659     less(0x3, "lt");
 3660     not_equal(0x4, "ne");
 3661     less_equal(0x5, "le");
 3662     no_overflow(0x6, "no_overflow");
 3663     greater_equal(0x7, "ge");
 3664   %}
 3665 %}
 3666 
 3667 
 3668 // Special Registers
 3669 
 3670 // Method Register
 3671 operand inline_cache_RegP(iRegP reg)
 3672 %{
 3673   constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
 3674   match(reg);
 3675   match(iRegPNoSp);
 3676   op_cost(0);
 3677   format %{ %}
 3678   interface(REG_INTER);
 3679 %}
 3680 
 3681 //----------OPERAND CLASSES----------------------------------------------------
 3682 // Operand Classes are groups of operands that are used as to simplify
 3683 // instruction definitions by not requiring the AD writer to specify
 3684 // separate instructions for every form of operand when the
 3685 // instruction accepts multiple operand types with the same basic
 3686 // encoding and format. The classic case of this is memory operands.
 3687 
 3688 // memory is used to define read/write location for load/store
 3689 // instruction defs. we can turn a memory op into an Address
 3690 
 3691 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
 3692 
 3693 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
 3694 // operations. it allows the src to be either an iRegI or a (ConvL2I
 3695 // iRegL). in the latter case the l2i normally planted for a ConvL2I
 3696 // can be elided because the 32-bit instruction will just employ the
 3697 // lower 32 bits anyway.
 3698 //
 3699 // n.b. this does not elide all L2I conversions. if the truncated
 3700 // value is consumed by more than one operation then the ConvL2I
 3701 // cannot be bundled into the consuming nodes so an l2i gets planted
 3702 // (actually a mvw $dst $src) and the downstream instructions consume
 3703 // the result of the l2i as an iRegI input. That's a shame since the
 3704 // mvw is actually redundant but its not too costly.
 3705 
 3706 opclass iRegIorL2I(iRegI, iRegL2I);
 3707 opclass iRegIorL(iRegI, iRegL);
 3708 opclass iRegNorP(iRegN, iRegP);
 3709 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
 3710 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
 3711 opclass immIorL(immI, immL);
 3712 
 3713 //----------PIPELINE-----------------------------------------------------------
 3714 // Rules which define the behavior of the target architectures pipeline.
 3715 
 3716 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
 3717 //pipe_desc(ID, EX, MEM, WR);
 3718 #define ID   S0
 3719 #define EX   S1
 3720 #define MEM  S2
 3721 #define WR   S3
 3722 
 3723 // Integer ALU reg operation
 3724 pipeline %{
 3725 
 3726 attributes %{
 3727   // RISC-V instructions are of fixed length
 3728   fixed_size_instructions;           // Fixed size instructions TODO does
 3729   max_instructions_per_bundle = 2;   // Generic RISC-V 1, Sifive Series 7 2
 3730   // RISC-V instructions come in 32-bit word units
 3731   instruction_unit_size = 4;         // An instruction is 4 bytes long
 3732   instruction_fetch_unit_size = 64;  // The processor fetches one line
 3733   instruction_fetch_units = 1;       // of 64 bytes
 3734 
 3735   // List of nop instructions
 3736   nops( MachNop );
 3737 %}
 3738 
 3739 // We don't use an actual pipeline model so don't care about resources
 3740 // or description. we do use pipeline classes to introduce fixed
 3741 // latencies
 3742 
 3743 //----------RESOURCES----------------------------------------------------------
 3744 // Resources are the functional units available to the machine
 3745 
 3746 // Generic RISC-V pipeline
 3747 // 1 decoder
 3748 // 1 instruction decoded per cycle
 3749 // 1 load/store ops per cycle, 1 branch, 1 FPU
 3750 // 1 mul, 1 div
 3751 
 3752 resources ( DECODE,
 3753             ALU,
 3754             MUL,
 3755             DIV,
 3756             BRANCH,
 3757             LDST,
 3758             FPU);
 3759 
 3760 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3761 // Pipeline Description specifies the stages in the machine's pipeline
 3762 
 3763 // Define the pipeline as a generic 6 stage pipeline
 3764 pipe_desc(S0, S1, S2, S3, S4, S5);
 3765 
 3766 //----------PIPELINE CLASSES---------------------------------------------------
 3767 // Pipeline Classes describe the stages in which input and output are
 3768 // referenced by the hardware pipeline.
 3769 
 3770 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
 3771 %{
 3772   single_instruction;
 3773   src1   : S1(read);
 3774   src2   : S2(read);
 3775   dst    : S5(write);
 3776   DECODE : ID;
 3777   FPU    : S5;
 3778 %}
 3779 
 3780 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
 3781 %{
 3782   src1   : S1(read);
 3783   src2   : S2(read);
 3784   dst    : S5(write);
 3785   DECODE : ID;
 3786   FPU    : S5;
 3787 %}
 3788 
 3789 pipe_class fp_uop_s(fRegF dst, fRegF src)
 3790 %{
 3791   single_instruction;
 3792   src    : S1(read);
 3793   dst    : S5(write);
 3794   DECODE : ID;
 3795   FPU    : S5;
 3796 %}
 3797 
 3798 pipe_class fp_uop_d(fRegD dst, fRegD src)
 3799 %{
 3800   single_instruction;
 3801   src    : S1(read);
 3802   dst    : S5(write);
 3803   DECODE : ID;
 3804   FPU    : S5;
 3805 %}
 3806 
 3807 pipe_class fp_d2f(fRegF dst, fRegD src)
 3808 %{
 3809   single_instruction;
 3810   src    : S1(read);
 3811   dst    : S5(write);
 3812   DECODE : ID;
 3813   FPU    : S5;
 3814 %}
 3815 
 3816 pipe_class fp_f2d(fRegD dst, fRegF src)
 3817 %{
 3818   single_instruction;
 3819   src    : S1(read);
 3820   dst    : S5(write);
 3821   DECODE : ID;
 3822   FPU    : S5;
 3823 %}
 3824 
 3825 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
 3826 %{
 3827   single_instruction;
 3828   src    : S1(read);
 3829   dst    : S5(write);
 3830   DECODE : ID;
 3831   FPU    : S5;
 3832 %}
 3833 
 3834 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
 3835 %{
 3836   single_instruction;
 3837   src    : S1(read);
 3838   dst    : S5(write);
 3839   DECODE : ID;
 3840   FPU    : S5;
 3841 %}
 3842 
 3843 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
 3844 %{
 3845   single_instruction;
 3846   src    : S1(read);
 3847   dst    : S5(write);
 3848   DECODE : ID;
 3849   FPU    : S5;
 3850 %}
 3851 
 3852 pipe_class fp_l2f(fRegF dst, iRegL src)
 3853 %{
 3854   single_instruction;
 3855   src    : S1(read);
 3856   dst    : S5(write);
 3857   DECODE : ID;
 3858   FPU    : S5;
 3859 %}
 3860 
 3861 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
 3862 %{
 3863   single_instruction;
 3864   src    : S1(read);
 3865   dst    : S5(write);
 3866   DECODE : ID;
 3867   FPU    : S5;
 3868 %}
 3869 
 3870 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
 3871 %{
 3872   single_instruction;
 3873   src    : S1(read);
 3874   dst    : S5(write);
 3875   DECODE : ID;
 3876   FPU    : S5;
 3877 %}
 3878 
 3879 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
 3880 %{
 3881   single_instruction;
 3882   src    : S1(read);
 3883   dst    : S5(write);
 3884   DECODE : ID;
 3885   FPU    : S5;
 3886 %}
 3887 
 3888 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
 3889 %{
 3890   single_instruction;
 3891   src    : S1(read);
 3892   dst    : S5(write);
 3893   DECODE : ID;
 3894   FPU    : S5;
 3895 %}
 3896 
 3897 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
 3898 %{
 3899   single_instruction;
 3900   src1   : S1(read);
 3901   src2   : S2(read);
 3902   dst    : S5(write);
 3903   DECODE : ID;
 3904   FPU    : S5;
 3905 %}
 3906 
 3907 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
 3908 %{
 3909   single_instruction;
 3910   src1   : S1(read);
 3911   src2   : S2(read);
 3912   dst    : S5(write);
 3913   DECODE : ID;
 3914   FPU    : S5;
 3915 %}
 3916 
 3917 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
 3918 %{
 3919   single_instruction;
 3920   src1   : S1(read);
 3921   src2   : S2(read);
 3922   dst    : S5(write);
 3923   DECODE : ID;
 3924   FPU    : S5;
 3925 %}
 3926 
 3927 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
 3928 %{
 3929   single_instruction;
 3930   src1   : S1(read);
 3931   src2   : S2(read);
 3932   dst    : S5(write);
 3933   DECODE : ID;
 3934   FPU    : S5;
 3935 %}
 3936 
 3937 pipe_class fp_load_constant_s(fRegF dst)
 3938 %{
 3939   single_instruction;
 3940   dst    : S5(write);
 3941   DECODE : ID;
 3942   FPU    : S5;
 3943 %}
 3944 
 3945 pipe_class fp_load_constant_d(fRegD dst)
 3946 %{
 3947   single_instruction;
 3948   dst    : S5(write);
 3949   DECODE : ID;
 3950   FPU    : S5;
 3951 %}
 3952 
 3953 pipe_class fp_load_mem_s(fRegF dst, memory mem)
 3954 %{
 3955   single_instruction;
 3956   mem    : S1(read);
 3957   dst    : S5(write);
 3958   DECODE : ID;
 3959   LDST   : MEM;
 3960 %}
 3961 
 3962 pipe_class fp_load_mem_d(fRegD dst, memory mem)
 3963 %{
 3964   single_instruction;
 3965   mem    : S1(read);
 3966   dst    : S5(write);
 3967   DECODE : ID;
 3968   LDST   : MEM;
 3969 %}
 3970 
 3971 pipe_class fp_store_reg_s(fRegF src, memory mem)
 3972 %{
 3973   single_instruction;
 3974   src    : S1(read);
 3975   mem    : S5(write);
 3976   DECODE : ID;
 3977   LDST   : MEM;
 3978 %}
 3979 
 3980 pipe_class fp_store_reg_d(fRegD src, memory mem)
 3981 %{
 3982   single_instruction;
 3983   src    : S1(read);
 3984   mem    : S5(write);
 3985   DECODE : ID;
 3986   LDST   : MEM;
 3987 %}
 3988 
 3989 //------- Integer ALU operations --------------------------
 3990 
 3991 // Integer ALU reg-reg operation
 3992 // Operands needs in ID, result generated in EX
 3993 // E.g.  ADD   Rd, Rs1, Rs2
 3994 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 3995 %{
 3996   single_instruction;
 3997   dst    : EX(write);
 3998   src1   : ID(read);
 3999   src2   : ID(read);
 4000   DECODE : ID;
 4001   ALU    : EX;
 4002 %}
 4003 
 4004 // Integer ALU reg operation with constant shift
 4005 // E.g. SLLI    Rd, Rs1, #shift
 4006 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
 4007 %{
 4008   single_instruction;
 4009   dst    : EX(write);
 4010   src1   : ID(read);
 4011   DECODE : ID;
 4012   ALU    : EX;
 4013 %}
 4014 
 4015 // Integer ALU reg-reg operation with variable shift
 4016 // both operands must be available in ID
 4017 // E.g. SLL   Rd, Rs1, Rs2
 4018 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
 4019 %{
 4020   single_instruction;
 4021   dst    : EX(write);
 4022   src1   : ID(read);
 4023   src2   : ID(read);
 4024   DECODE : ID;
 4025   ALU    : EX;
 4026 %}
 4027 
 4028 // Integer ALU reg operation
 4029 // E.g. NEG   Rd, Rs2
 4030 pipe_class ialu_reg(iRegI dst, iRegI src)
 4031 %{
 4032   single_instruction;
 4033   dst    : EX(write);
 4034   src    : ID(read);
 4035   DECODE : ID;
 4036   ALU    : EX;
 4037 %}
 4038 
 4039 // Integer ALU reg immediate operation
 4040 // E.g. ADDI   Rd, Rs1, #imm
 4041 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
 4042 %{
 4043   single_instruction;
 4044   dst    : EX(write);
 4045   src1   : ID(read);
 4046   DECODE : ID;
 4047   ALU    : EX;
 4048 %}
 4049 
 4050 // Integer ALU immediate operation (no source operands)
 4051 // E.g. LI    Rd, #imm
 4052 pipe_class ialu_imm(iRegI dst)
 4053 %{
 4054   single_instruction;
 4055   dst    : EX(write);
 4056   DECODE : ID;
 4057   ALU    : EX;
 4058 %}
 4059 
 4060 //------- Multiply pipeline operations --------------------
 4061 
 4062 // Multiply reg-reg
 4063 // E.g. MULW   Rd, Rs1, Rs2
 4064 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4065 %{
 4066   single_instruction;
 4067   dst    : WR(write);
 4068   src1   : ID(read);
 4069   src2   : ID(read);
 4070   DECODE : ID;
 4071   MUL    : WR;
 4072 %}
 4073 
 4074 // E.g. MUL   RD, Rs1, Rs2
 4075 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4076 %{
 4077   single_instruction;
 4078   fixed_latency(3); // Maximum latency for 64 bit mul
 4079   dst    : WR(write);
 4080   src1   : ID(read);
 4081   src2   : ID(read);
 4082   DECODE : ID;
 4083   MUL    : WR;
 4084 %}
 4085 
 4086 //------- Divide pipeline operations --------------------
 4087 
 4088 // E.g. DIVW   Rd, Rs1, Rs2
 4089 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4090 %{
 4091   single_instruction;
 4092   fixed_latency(8); // Maximum latency for 32 bit divide
 4093   dst    : WR(write);
 4094   src1   : ID(read);
 4095   src2   : ID(read);
 4096   DECODE : ID;
 4097   DIV    : WR;
 4098 %}
 4099 
 4100 // E.g. DIV   RD, Rs1, Rs2
 4101 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4102 %{
 4103   single_instruction;
 4104   fixed_latency(16); // Maximum latency for 64 bit divide
 4105   dst    : WR(write);
 4106   src1   : ID(read);
 4107   src2   : ID(read);
 4108   DECODE : ID;
 4109   DIV    : WR;
 4110 %}
 4111 
 4112 //------- Load pipeline operations ------------------------
 4113 
 4114 // Load - reg, mem
 4115 // E.g. LA    Rd, mem
 4116 pipe_class iload_reg_mem(iRegI dst, memory mem)
 4117 %{
 4118   single_instruction;
 4119   dst    : WR(write);
 4120   mem    : ID(read);
 4121   DECODE : ID;
 4122   LDST   : MEM;
 4123 %}
 4124 
 4125 // Load - reg, reg
 4126 // E.g. LD    Rd, Rs
 4127 pipe_class iload_reg_reg(iRegI dst, iRegI src)
 4128 %{
 4129   single_instruction;
 4130   dst    : WR(write);
 4131   src    : ID(read);
 4132   DECODE : ID;
 4133   LDST   : MEM;
 4134 %}
 4135 
 4136 //------- Store pipeline operations -----------------------
 4137 
 4138 // Store - zr, mem
 4139 // E.g. SD    zr, mem
 4140 pipe_class istore_mem(memory mem)
 4141 %{
 4142   single_instruction;
 4143   mem    : ID(read);
 4144   DECODE : ID;
 4145   LDST   : MEM;
 4146 %}
 4147 
 4148 // Store - reg, mem
 4149 // E.g. SD    Rs, mem
 4150 pipe_class istore_reg_mem(iRegI src, memory mem)
 4151 %{
 4152   single_instruction;
 4153   mem    : ID(read);
 4154   src    : EX(read);
 4155   DECODE : ID;
 4156   LDST   : MEM;
 4157 %}
 4158 
 4159 // Store - reg, reg
 4160 // E.g. SD    Rs2, Rs1
 4161 pipe_class istore_reg_reg(iRegI dst, iRegI src)
 4162 %{
 4163   single_instruction;
 4164   dst    : ID(read);
 4165   src    : EX(read);
 4166   DECODE : ID;
 4167   LDST   : MEM;
 4168 %}
 4169 
 4170 //------- Store pipeline operations -----------------------
 4171 
 4172 // Branch
 4173 pipe_class pipe_branch()
 4174 %{
 4175   single_instruction;
 4176   DECODE : ID;
 4177   BRANCH : EX;
 4178 %}
 4179 
 4180 // Branch
 4181 pipe_class pipe_branch_reg(iRegI src)
 4182 %{
 4183   single_instruction;
 4184   src    : ID(read);
 4185   DECODE : ID;
 4186   BRANCH : EX;
 4187 %}
 4188 
 4189 // Compare & Branch
 4190 // E.g. BEQ   Rs1, Rs2, L
 4191 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
 4192 %{
 4193   single_instruction;
 4194   src1   : ID(read);
 4195   src2   : ID(read);
 4196   DECODE : ID;
 4197   BRANCH : EX;
 4198 %}
 4199 
 4200 // E.g. BEQZ Rs, L
 4201 pipe_class pipe_cmpz_branch(iRegI src)
 4202 %{
 4203   single_instruction;
 4204   src    : ID(read);
 4205   DECODE : ID;
 4206   BRANCH : EX;
 4207 %}
 4208 
 4209 //------- Synchronisation operations ----------------------
 4210 // Any operation requiring serialization
 4211 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
 4212 pipe_class pipe_serial()
 4213 %{
 4214   single_instruction;
 4215   force_serialization;
 4216   fixed_latency(16);
 4217   DECODE : ID;
 4218   LDST   : MEM;
 4219 %}
 4220 
 4221 pipe_class pipe_slow()
 4222 %{
 4223   instruction_count(10);
 4224   multiple_bundles;
 4225   force_serialization;
 4226   fixed_latency(16);
 4227   DECODE : ID;
 4228   LDST   : MEM;
 4229 %}
 4230 
 4231 // Empty pipeline class
 4232 pipe_class pipe_class_empty()
 4233 %{
 4234   single_instruction;
 4235   fixed_latency(0);
 4236 %}
 4237 
 4238 // Default pipeline class.
 4239 pipe_class pipe_class_default()
 4240 %{
 4241   single_instruction;
 4242   fixed_latency(2);
 4243 %}
 4244 
 4245 // Pipeline class for compares.
 4246 pipe_class pipe_class_compare()
 4247 %{
 4248   single_instruction;
 4249   fixed_latency(16);
 4250 %}
 4251 
 4252 // Pipeline class for memory operations.
 4253 pipe_class pipe_class_memory()
 4254 %{
 4255   single_instruction;
 4256   fixed_latency(16);
 4257 %}
 4258 
 4259 // Pipeline class for call.
 4260 pipe_class pipe_class_call()
 4261 %{
 4262   single_instruction;
 4263   fixed_latency(100);
 4264 %}
 4265 
 4266 // Define the class for the Nop node.
 4267 define %{
 4268    MachNop = pipe_class_empty;
 4269 %}
 4270 %}
 4271 //----------INSTRUCTIONS-------------------------------------------------------
 4272 //
 4273 // match      -- States which machine-independent subtree may be replaced
 4274 //               by this instruction.
 4275 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4276 //               selection to identify a minimum cost tree of machine
 4277 //               instructions that matches a tree of machine-independent
 4278 //               instructions.
 4279 // format     -- A string providing the disassembly for this instruction.
 4280 //               The value of an instruction's operand may be inserted
 4281 //               by referring to it with a '$' prefix.
 4282 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4283 //               to within an encode class as $primary, $secondary, and $tertiary
 4284 //               rrspectively.  The primary opcode is commonly used to
 4285 //               indicate the type of machine instruction, while secondary
 4286 //               and tertiary are often used for prefix options or addressing
 4287 //               modes.
 4288 // ins_encode -- A list of encode classes with parameters. The encode class
 4289 //               name must have been defined in an 'enc_class' specification
 4290 //               in the encode section of the architecture description.
 4291 
 4292 // ============================================================================
 4293 // Memory (Load/Store) Instructions
 4294 
 4295 // Load Instructions
 4296 
 4297 // Load Byte (8 bit signed)
 4298 instruct loadB(iRegINoSp dst, memory mem)
 4299 %{
 4300   match(Set dst (LoadB mem));
 4301 
 4302   ins_cost(LOAD_COST);
 4303   format %{ "lb  $dst, $mem\t# byte, #@loadB" %}
 4304 
 4305   ins_encode %{
 4306     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4307   %}
 4308 
 4309   ins_pipe(iload_reg_mem);
 4310 %}
 4311 
 4312 // Load Byte (8 bit signed) into long
 4313 instruct loadB2L(iRegLNoSp dst, memory mem)
 4314 %{
 4315   match(Set dst (ConvI2L (LoadB mem)));
 4316 
 4317   ins_cost(LOAD_COST);
 4318   format %{ "lb  $dst, $mem\t# byte, #@loadB2L" %}
 4319 
 4320   ins_encode %{
 4321     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4322   %}
 4323 
 4324   ins_pipe(iload_reg_mem);
 4325 %}
 4326 
 4327 // Load Byte (8 bit unsigned)
 4328 instruct loadUB(iRegINoSp dst, memory mem)
 4329 %{
 4330   match(Set dst (LoadUB mem));
 4331 
 4332   ins_cost(LOAD_COST);
 4333   format %{ "lbu  $dst, $mem\t# byte, #@loadUB" %}
 4334 
 4335   ins_encode %{
 4336     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4337   %}
 4338 
 4339   ins_pipe(iload_reg_mem);
 4340 %}
 4341 
 4342 // Load Byte (8 bit unsigned) into long
 4343 instruct loadUB2L(iRegLNoSp dst, memory mem)
 4344 %{
 4345   match(Set dst (ConvI2L (LoadUB mem)));
 4346 
 4347   ins_cost(LOAD_COST);
 4348   format %{ "lbu  $dst, $mem\t# byte, #@loadUB2L" %}
 4349 
 4350   ins_encode %{
 4351     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4352   %}
 4353 
 4354   ins_pipe(iload_reg_mem);
 4355 %}
 4356 
 4357 // Load Short (16 bit signed)
 4358 instruct loadS(iRegINoSp dst, memory mem)
 4359 %{
 4360   match(Set dst (LoadS mem));
 4361 
 4362   ins_cost(LOAD_COST);
 4363   format %{ "lh  $dst, $mem\t# short, #@loadS" %}
 4364 
 4365   ins_encode %{
 4366     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4367   %}
 4368 
 4369   ins_pipe(iload_reg_mem);
 4370 %}
 4371 
 4372 // Load Short (16 bit signed) into long
 4373 instruct loadS2L(iRegLNoSp dst, memory mem)
 4374 %{
 4375   match(Set dst (ConvI2L (LoadS mem)));
 4376 
 4377   ins_cost(LOAD_COST);
 4378   format %{ "lh  $dst, $mem\t# short, #@loadS2L" %}
 4379 
 4380   ins_encode %{
 4381     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4382   %}
 4383 
 4384   ins_pipe(iload_reg_mem);
 4385 %}
 4386 
 4387 // Load Char (16 bit unsigned)
 4388 instruct loadUS(iRegINoSp dst, memory mem)
 4389 %{
 4390   match(Set dst (LoadUS mem));
 4391 
 4392   ins_cost(LOAD_COST);
 4393   format %{ "lhu  $dst, $mem\t# short, #@loadUS" %}
 4394 
 4395   ins_encode %{
 4396     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4397   %}
 4398 
 4399   ins_pipe(iload_reg_mem);
 4400 %}
 4401 
 4402 // Load Short/Char (16 bit unsigned) into long
 4403 instruct loadUS2L(iRegLNoSp dst, memory mem)
 4404 %{
 4405   match(Set dst (ConvI2L (LoadUS mem)));
 4406 
 4407   ins_cost(LOAD_COST);
 4408   format %{ "lhu  $dst, $mem\t# short, #@loadUS2L" %}
 4409 
 4410   ins_encode %{
 4411     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4412   %}
 4413 
 4414   ins_pipe(iload_reg_mem);
 4415 %}
 4416 
 4417 // Load Integer (32 bit signed)
 4418 instruct loadI(iRegINoSp dst, memory mem)
 4419 %{
 4420   match(Set dst (LoadI mem));
 4421 
 4422   ins_cost(LOAD_COST);
 4423   format %{ "lw  $dst, $mem\t# int, #@loadI" %}
 4424 
 4425   ins_encode %{
 4426     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4427   %}
 4428 
 4429   ins_pipe(iload_reg_mem);
 4430 %}
 4431 
 4432 // Load Integer (32 bit signed) into long
 4433 instruct loadI2L(iRegLNoSp dst, memory mem)
 4434 %{
 4435   match(Set dst (ConvI2L (LoadI mem)));
 4436 
 4437   ins_cost(LOAD_COST);
 4438   format %{ "lw  $dst, $mem\t# int, #@loadI2L" %}
 4439 
 4440   ins_encode %{
 4441     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4442   %}
 4443 
 4444   ins_pipe(iload_reg_mem);
 4445 %}
 4446 
 4447 // Load Integer (32 bit unsigned) into long
 4448 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
 4449 %{
 4450   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4451 
 4452   ins_cost(LOAD_COST);
 4453   format %{ "lwu  $dst, $mem\t# int, #@loadUI2L" %}
 4454 
 4455   ins_encode %{
 4456     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4457   %}
 4458 
 4459   ins_pipe(iload_reg_mem);
 4460 %}
 4461 
 4462 // Load Long (64 bit signed)
 4463 instruct loadL(iRegLNoSp dst, memory mem)
 4464 %{
 4465   match(Set dst (LoadL mem));
 4466 
 4467   ins_cost(LOAD_COST);
 4468   format %{ "ld  $dst, $mem\t# int, #@loadL" %}
 4469 
 4470   ins_encode %{
 4471     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4472   %}
 4473 
 4474   ins_pipe(iload_reg_mem);
 4475 %}
 4476 
 4477 // Load Range
 4478 instruct loadRange(iRegINoSp dst, memory mem)
 4479 %{
 4480   match(Set dst (LoadRange mem));
 4481 
 4482   ins_cost(LOAD_COST);
 4483   format %{ "lwu  $dst, $mem\t# range, #@loadRange" %}
 4484 
 4485   ins_encode %{
 4486     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4487   %}
 4488 
 4489   ins_pipe(iload_reg_mem);
 4490 %}
 4491 
 4492 // Load Pointer
 4493 instruct loadP(iRegPNoSp dst, memory mem)
 4494 %{
 4495   match(Set dst (LoadP mem));
 4496   predicate(n->as_Load()->barrier_data() == 0);
 4497 
 4498   ins_cost(LOAD_COST);
 4499   format %{ "ld  $dst, $mem\t# ptr, #@loadP" %}
 4500 
 4501   ins_encode %{
 4502     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4503   %}
 4504 
 4505   ins_pipe(iload_reg_mem);
 4506 %}
 4507 
 4508 // Load Compressed Pointer
 4509 instruct loadN(iRegNNoSp dst, memory mem)
 4510 %{
 4511   match(Set dst (LoadN mem));
 4512 
 4513   ins_cost(LOAD_COST);
 4514   format %{ "lwu  $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
 4515 
 4516   ins_encode %{
 4517     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4518   %}
 4519 
 4520   ins_pipe(iload_reg_mem);
 4521 %}
 4522 
 4523 // Load Klass Pointer
 4524 instruct loadKlass(iRegPNoSp dst, memory mem)
 4525 %{
 4526   match(Set dst (LoadKlass mem));
 4527 
 4528   ins_cost(LOAD_COST);
 4529   format %{ "ld  $dst, $mem\t# class, #@loadKlass" %}
 4530 
 4531   ins_encode %{
 4532     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4533   %}
 4534 
 4535   ins_pipe(iload_reg_mem);
 4536 %}
 4537 
 4538 // Load Narrow Klass Pointer
 4539 instruct loadNKlass(iRegNNoSp dst, memory mem)
 4540 %{
 4541   match(Set dst (LoadNKlass mem));
 4542 
 4543   ins_cost(LOAD_COST);
 4544   format %{ "lwu  $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
 4545 
 4546   ins_encode %{
 4547     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4548   %}
 4549 
 4550   ins_pipe(iload_reg_mem);
 4551 %}
 4552 
 4553 // Load Float
 4554 instruct loadF(fRegF dst, memory mem)
 4555 %{
 4556   match(Set dst (LoadF mem));
 4557 
 4558   ins_cost(LOAD_COST);
 4559   format %{ "flw  $dst, $mem\t# float, #@loadF" %}
 4560 
 4561   ins_encode %{
 4562     __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4563   %}
 4564 
 4565   ins_pipe(fp_load_mem_s);
 4566 %}
 4567 
 4568 // Load Double
 4569 instruct loadD(fRegD dst, memory mem)
 4570 %{
 4571   match(Set dst (LoadD mem));
 4572 
 4573   ins_cost(LOAD_COST);
 4574   format %{ "fld  $dst, $mem\t# double, #@loadD" %}
 4575 
 4576   ins_encode %{
 4577     __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4578   %}
 4579 
 4580   ins_pipe(fp_load_mem_d);
 4581 %}
 4582 
 4583 // Load Int Constant
 4584 instruct loadConI(iRegINoSp dst, immI src)
 4585 %{
 4586   match(Set dst src);
 4587 
 4588   ins_cost(ALU_COST);
 4589   format %{ "li $dst, $src\t# int, #@loadConI" %}
 4590 
 4591   ins_encode(riscv64_enc_li_imm(dst, src));
 4592 
 4593   ins_pipe(ialu_imm);
 4594 %}
 4595 
 4596 // Load Long Constant
 4597 instruct loadConL(iRegLNoSp dst, immL src)
 4598 %{
 4599   match(Set dst src);
 4600 
 4601   ins_cost(ALU_COST);
 4602   format %{ "li $dst, $src\t# long, #@loadConL" %}
 4603 
 4604   ins_encode(riscv64_enc_li_imm(dst, src));
 4605 
 4606   ins_pipe(ialu_imm);
 4607 %}
 4608 
 4609 // Load Pointer Constant
 4610 instruct loadConP(iRegPNoSp dst, immP con)
 4611 %{
 4612   match(Set dst con);
 4613 
 4614   ins_cost(ALU_COST);
 4615   format %{ "mv  $dst, $con\t# ptr, #@loadConP" %}
 4616 
 4617   ins_encode(riscv64_enc_mov_p(dst, con));
 4618 
 4619   ins_pipe(ialu_imm);
 4620 %}
 4621 
 4622 // Load Null Pointer Constant
 4623 instruct loadConP0(iRegPNoSp dst, immP0 con)
 4624 %{
 4625   match(Set dst con);
 4626 
 4627   ins_cost(ALU_COST);
 4628   format %{ "mv  $dst, $con\t# NULL ptr, #@loadConP0" %}
 4629 
 4630   ins_encode(riscv64_enc_mov_zero(dst));
 4631 
 4632   ins_pipe(ialu_imm);
 4633 %}
 4634 
 4635 // Load Pointer Constant One
 4636 instruct loadConP1(iRegPNoSp dst, immP_1 con)
 4637 %{
 4638   match(Set dst con);
 4639 
 4640   ins_cost(ALU_COST);
 4641   format %{ "mv  $dst, $con\t# load ptr constant one, #@loadConP1" %}
 4642 
 4643   ins_encode(riscv64_enc_mov_p1(dst));
 4644 
 4645   ins_pipe(ialu_imm);
 4646 %}
 4647 
 4648 // Load Byte Map Base Constant
 4649 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
 4650 %{
 4651   match(Set dst con);
 4652   ins_cost(ALU_COST);
 4653   format %{ "mv  $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
 4654 
 4655   ins_encode(riscv64_enc_mov_byte_map_base(dst));
 4656 
 4657   ins_pipe(ialu_imm);
 4658 %}
 4659 
 4660 // Load Narrow Pointer Constant
 4661 instruct loadConN(iRegNNoSp dst, immN con)
 4662 %{
 4663   match(Set dst con);
 4664 
 4665   ins_cost(ALU_COST * 4);
 4666   format %{ "mv  $dst, $con\t# compressed ptr, #@loadConN" %}
 4667 
 4668   ins_encode(riscv64_enc_mov_n(dst, con));
 4669 
 4670   ins_pipe(ialu_imm);
 4671 %}
 4672 
 4673 // Load Narrow Null Pointer Constant
 4674 instruct loadConN0(iRegNNoSp dst, immN0 con)
 4675 %{
 4676   match(Set dst con);
 4677 
 4678   ins_cost(ALU_COST);
 4679   format %{ "mv  $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
 4680 
 4681   ins_encode(riscv64_enc_mov_zero(dst));
 4682 
 4683   ins_pipe(ialu_imm);
 4684 %}
 4685 
 4686 // Load Narrow Klass Constant
 4687 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
 4688 %{
 4689   match(Set dst con);
 4690 
 4691   ins_cost(ALU_COST * 6);
 4692   format %{ "mv  $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
 4693 
 4694   ins_encode(riscv64_enc_mov_nk(dst, con));
 4695 
 4696   ins_pipe(ialu_imm);
 4697 %}
 4698 
 4699 // Load Float Constant
 4700 instruct loadConF(fRegF dst, immF con) %{
 4701   match(Set dst con);
 4702 
 4703   ins_cost(LOAD_COST);
 4704   format %{
 4705     "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
 4706   %}
 4707 
 4708   ins_encode %{
 4709     __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
 4710   %}
 4711 
 4712   ins_pipe(fp_load_constant_s);
 4713 %}
 4714 
 4715 instruct loadConF0(fRegF dst, immF0 con) %{
 4716   match(Set dst con);
 4717 
 4718   ins_cost(XFER_COST);
 4719 
 4720   format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
 4721 
 4722   ins_encode %{
 4723     __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
 4724   %}
 4725 
 4726   ins_pipe(fp_load_constant_s);
 4727 %}
 4728 
 4729 // Load Double Constant
 4730 instruct loadConD(fRegD dst, immD con) %{
 4731   match(Set dst con);
 4732 
 4733   ins_cost(LOAD_COST);
 4734   format %{
 4735     "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
 4736   %}
 4737 
 4738   ins_encode %{
 4739     __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
 4740   %}
 4741 
 4742   ins_pipe(fp_load_constant_d);
 4743 %}
 4744 
 4745 instruct loadConD0(fRegD dst, immD0 con) %{
 4746   match(Set dst con);
 4747 
 4748   ins_cost(XFER_COST);
 4749 
 4750   format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
 4751 
 4752   ins_encode %{
 4753     __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
 4754   %}
 4755 
 4756   ins_pipe(fp_load_constant_d);
 4757 %}
 4758 
 4759 // Store Instructions
 4760 // Store CMS card-mark Immediate
 4761 instruct storeimmCM0(immI0 zero, memory mem)
 4762 %{
 4763   match(Set mem (StoreCM mem zero));
 4764 
 4765   ins_cost(STORE_COST);
 4766   format %{ "storestore (elided)\n\t"
 4767             "sb zr, $mem\t# byte, #@storeimmCM0" %}
 4768 
 4769   ins_encode %{
 4770     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4771   %}
 4772 
 4773   ins_pipe(istore_mem);
 4774 %}
 4775 
 4776 // Store CMS card-mark Immediate with intervening StoreStore
 4777 // needed when using CMS with no conditional card marking
 4778 instruct storeimmCM0_ordered(immI0 zero, memory mem)
 4779 %{
 4780   match(Set mem (StoreCM mem zero));
 4781 
 4782   ins_cost(ALU_COST + STORE_COST);
 4783   format %{ "membar(StoreStore)\n\t"
 4784             "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
 4785 
 4786   ins_encode %{
 4787     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 4788     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4789   %}
 4790 
 4791   ins_pipe(istore_mem);
 4792 %}
 4793 
 4794 // Store Byte
 4795 instruct storeB(iRegIorL2I src, memory mem)
 4796 %{
 4797   match(Set mem (StoreB mem src));
 4798 
 4799   ins_cost(STORE_COST);
 4800   format %{ "sb  $src, $mem\t# byte, #@storeB" %}
 4801 
 4802   ins_encode %{
 4803     __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4804   %}
 4805 
 4806   ins_pipe(istore_reg_mem);
 4807 %}
 4808 
 4809 instruct storeimmB0(immI0 zero, memory mem)
 4810 %{
 4811   match(Set mem (StoreB mem zero));
 4812 
 4813   ins_cost(STORE_COST);
 4814   format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
 4815 
 4816   ins_encode %{
 4817     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4818   %}
 4819 
 4820   ins_pipe(istore_mem);
 4821 %}
 4822 
 4823 // Store Char/Short
 4824 instruct storeC(iRegIorL2I src, memory mem)
 4825 %{
 4826   match(Set mem (StoreC mem src));
 4827 
 4828   ins_cost(STORE_COST);
 4829   format %{ "sh  $src, $mem\t# short, #@storeC" %}
 4830 
 4831   ins_encode %{
 4832     __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4833   %}
 4834 
 4835   ins_pipe(istore_reg_mem);
 4836 %}
 4837 
 4838 instruct storeimmC0(immI0 zero, memory mem)
 4839 %{
 4840   match(Set mem (StoreC mem zero));
 4841 
 4842   ins_cost(STORE_COST);
 4843   format %{ "sh  zr, $mem\t# short, #@storeimmC0" %}
 4844 
 4845   ins_encode %{
 4846     __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
 4847   %}
 4848 
 4849   ins_pipe(istore_mem);
 4850 %}
 4851 
 4852 // Store Integer
 4853 instruct storeI(iRegIorL2I src, memory mem)
 4854 %{
 4855   match(Set mem(StoreI mem src));
 4856 
 4857   ins_cost(STORE_COST);
 4858   format %{ "sw  $src, $mem\t# int, #@storeI" %}
 4859 
 4860   ins_encode %{
 4861     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4862   %}
 4863 
 4864   ins_pipe(istore_reg_mem);
 4865 %}
 4866 
 4867 instruct storeimmI0(immI0 zero, memory mem)
 4868 %{
 4869   match(Set mem(StoreI mem zero));
 4870 
 4871   ins_cost(STORE_COST);
 4872   format %{ "sw  zr, $mem\t# int, #@storeimmI0" %}
 4873 
 4874   ins_encode %{
 4875     __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
 4876   %}
 4877 
 4878   ins_pipe(istore_mem);
 4879 %}
 4880 
 4881 // Store Long (64 bit signed)
 4882 instruct storeL(iRegL src, memory mem)
 4883 %{
 4884   match(Set mem (StoreL mem src));
 4885 
 4886   ins_cost(STORE_COST);
 4887   format %{ "sd  $src, $mem\t# long, #@storeL" %}
 4888 
 4889   ins_encode %{
 4890     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4891   %}
 4892 
 4893   ins_pipe(istore_reg_mem);
 4894 %}
 4895 
 4896 // Store Long (64 bit signed)
 4897 instruct storeimmL0(immL0 zero, memory mem)
 4898 %{
 4899   match(Set mem (StoreL mem zero));
 4900 
 4901   ins_cost(STORE_COST);
 4902   format %{ "sd  zr, $mem\t# long, #@storeimmL0" %}
 4903 
 4904   ins_encode %{
 4905     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 4906   %}
 4907 
 4908   ins_pipe(istore_mem);
 4909 %}
 4910 
 4911 // Store Pointer
 4912 instruct storeP(iRegP src, memory mem)
 4913 %{
 4914   match(Set mem (StoreP mem src));
 4915 
 4916   ins_cost(STORE_COST);
 4917   format %{ "sd  $src, $mem\t# ptr, #@storeP" %}
 4918 
 4919   ins_encode %{
 4920     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4921   %}
 4922 
 4923   ins_pipe(istore_reg_mem);
 4924 %}
 4925 
 4926 // Store Pointer
 4927 instruct storeimmP0(immP0 zero, memory mem)
 4928 %{
 4929   match(Set mem (StoreP mem zero));
 4930 
 4931   ins_cost(STORE_COST);
 4932   format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
 4933 
 4934   ins_encode %{
 4935     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 4936   %}
 4937 
 4938   ins_pipe(istore_mem);
 4939 %}
 4940 
 4941 // Store Compressed Pointer
 4942 instruct storeN(iRegN src, memory mem)
 4943 %{
 4944   match(Set mem (StoreN mem src));
 4945 
 4946   ins_cost(STORE_COST);
 4947   format %{ "sw  $src, $mem\t# compressed ptr, #@storeN" %}
 4948 
 4949   ins_encode %{
 4950     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4951   %}
 4952 
 4953   ins_pipe(istore_reg_mem);
 4954 %}
 4955 
 4956 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
 4957 %{
 4958   match(Set mem (StoreN mem zero));
 4959 
 4960   ins_cost(STORE_COST);
 4961   format %{ "sw  rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
 4962 
 4963   ins_encode %{
 4964     __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4965   %}
 4966 
 4967   ins_pipe(istore_reg_mem);
 4968 %}
 4969 
 4970 // Store Float
 4971 instruct storeF(fRegF src, memory mem)
 4972 %{
 4973   match(Set mem (StoreF mem src));
 4974 
 4975   ins_cost(STORE_COST);
 4976   format %{ "fsw  $src, $mem\t# float, #@storeF" %}
 4977 
 4978   ins_encode %{
 4979     __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4980   %}
 4981 
 4982   ins_pipe(fp_store_reg_s);
 4983 %}
 4984 
 4985 // Store Double
 4986 instruct storeD(fRegD src, memory mem)
 4987 %{
 4988   match(Set mem (StoreD mem src));
 4989 
 4990   ins_cost(STORE_COST);
 4991   format %{ "fsd  $src, $mem\t# double, #@storeD" %}
 4992 
 4993   ins_encode %{
 4994     __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4995   %}
 4996 
 4997   ins_pipe(fp_store_reg_d);
 4998 %}
 4999 
 5000 // Store Compressed Klass Pointer
 5001 instruct storeNKlass(iRegN src, memory mem)
 5002 %{
 5003   match(Set mem (StoreNKlass mem src));
 5004 
 5005   ins_cost(STORE_COST);
 5006   format %{ "sw  $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
 5007 
 5008   ins_encode %{
 5009     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5010   %}
 5011 
 5012   ins_pipe(istore_reg_mem);
 5013 %}
 5014 
 5015 // ============================================================================
 5016 // Atomic operation instructions
 5017 //
 5018 // Intel and SPARC both implement Ideal Node LoadPLocked and
 5019 // Store{PIL}Conditional instructions using a normal load for the
 5020 // LoadPLocked and a CAS for the Store{PIL}Conditional.
 5021 //
 5022 // The ideal code appears only to use LoadPLocked/storePConditional as a
 5023 // pair to lock object allocations from Eden space when not using
 5024 // TLABs.
 5025 //
 5026 // There does not appear to be a Load{IL}Locked Ideal Node and the
 5027 // Ideal code appears to use Store{IL}Conditional as an alias for CAS
 5028 // and to use StoreIConditional only for 32-bit and StoreLConditional
 5029 // only for 64-bit.
 5030 //
 5031 // We implement LoadPLocked and storePConditional instructions using,
 5032 // respectively the RISCV64 hw load-reserve and store-conditional
 5033 // instructions. Whereas we must implement each of
 5034 // Store{IL}Conditional using a CAS which employs a pair of
 5035 // instructions comprising a load-reserve followed by a
 5036 // store-conditional.
 5037 
 5038 
 5039 // Locked-load (load reserved) of the current heap-top
 5040 // used when updating the eden heap top
 5041 // implemented using lr_d on RISCV64
 5042 instruct loadPLocked(iRegPNoSp dst, indirect mem)
 5043 %{
 5044   match(Set dst (LoadPLocked mem));
 5045 
 5046   ins_cost(ALU_COST * 2 + LOAD_COST);
 5047 
 5048   format %{ "lr.d $dst, $mem\t# ptr load reserved, #@loadPLocked" %}
 5049 
 5050   ins_encode %{
 5051     __ la(t0, Address(as_Register($mem$$base), $mem$$disp));
 5052     __ lr_d($dst$$Register, t0, Assembler::aq);
 5053   %}
 5054 
 5055   ins_pipe(pipe_serial);
 5056 %}
 5057 
 5058 // Conditional-store of the updated heap-top.
 5059 // Used during allocation of the shared heap.
 5060 // implemented using sc_d on RISCV64.
 5061 instruct storePConditional(memory heap_top_ptr, iRegP oldval, iRegP newval, iRegI_R6 cr)
 5062 %{
 5063   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
 5064 
 5065   ins_cost(ALU_COST * 2 + STORE_COST);
 5066 
 5067   format %{
 5068     "sc_d t1, $newval $heap_top_ptr,\t# ptr store conditional, #@storePConditional"
 5069   %}
 5070 
 5071   ins_encode %{
 5072     __ la(t0, Address(as_Register($heap_top_ptr$$base), $heap_top_ptr$$disp));
 5073     __ sc_d($cr$$Register, $newval$$Register, t0, Assembler::rl);
 5074   %}
 5075 
 5076   ins_pipe(pipe_serial);
 5077 %}
 5078 
 5079 instruct storeLConditional(indirect mem, iRegLNoSp oldval, iRegLNoSp newval, iRegI_R6 cr)
 5080 %{
 5081   match(Set cr (StoreLConditional mem (Binary oldval newval)));
 5082 
 5083   ins_cost(LOAD_COST + STORE_COST + 2 * BRANCH_COST);
 5084 
 5085   format %{
 5086     "cmpxchg t1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
 5087     "xorr $cr, $cr, $oldval\t# $cr == 0 on successful write, #@storeLConditional"
 5088   %}
 5089 
 5090   ins_encode %{
 5091     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5092                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $cr$$Register);
 5093     __ xorr($cr$$Register,$cr$$Register, $oldval$$Register);
 5094   %}
 5095 
 5096   ins_pipe(pipe_slow);
 5097 %}
 5098 
 5099 // storeIConditional also has acquire semantics, for no better reason
 5100 // than matching storeLConditional.
 5101 instruct storeIConditional(indirect mem, iRegINoSp oldval, iRegINoSp newval, iRegI_R6 cr)
 5102 %{
 5103   match(Set cr (StoreIConditional mem (Binary oldval newval)));
 5104 
 5105   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2);
 5106 
 5107   format %{
 5108     "cmpxchgw t1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
 5109     "xorr $cr, $cr, $oldval\t# $cr == 0 on successful write, #@storeIConditional"
 5110   %}
 5111 
 5112   ins_encode %{
 5113     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5114                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $cr$$Register);
 5115     __ xorr($cr$$Register,$cr$$Register, $oldval$$Register);
 5116   %}
 5117 
 5118   ins_pipe(pipe_slow);
 5119 %}
 5120 
 5121 // standard CompareAndSwapX when we are using barriers
 5122 // these have higher priority than the rules selected by a predicate
 5123 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5124 %{
 5125   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5126 
 5127   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5128 
 5129   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5130 
 5131   format %{
 5132     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5133     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
 5134   %}
 5135 
 5136   ins_encode %{
 5137     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5138                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5139                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5140   %}
 5141 
 5142   ins_pipe(pipe_slow);
 5143 %}
 5144 
 5145 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5146 %{
 5147   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5148 
 5149   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5150 
 5151   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5152 
 5153   format %{
 5154     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5155     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
 5156   %}
 5157 
 5158   ins_encode %{
 5159     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5160                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5161                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5162   %}
 5163 
 5164   ins_pipe(pipe_slow);
 5165 %}
 5166 
 5167 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval)
 5168 %{
 5169   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5170 
 5171   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5172 
 5173   format %{
 5174     "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5175     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
 5176   %}
 5177 
 5178   ins_encode(riscv64_enc_cmpxchgw(res, mem, oldval, newval));
 5179 
 5180   ins_pipe(pipe_slow);
 5181 %}
 5182 
 5183 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval)
 5184 %{
 5185   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5186 
 5187   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5188 
 5189   format %{
 5190     "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5191     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
 5192   %}
 5193 
 5194   ins_encode(riscv64_enc_cmpxchg(res, mem, oldval, newval));
 5195 
 5196   ins_pipe(pipe_slow);
 5197 %}
 5198 
 5199 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5200 %{
 5201   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5202   predicate(n->as_LoadStore()->barrier_data() == 0);
 5203 
 5204   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5205 
 5206   format %{
 5207     "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5208     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
 5209   %}
 5210 
 5211   ins_encode(riscv64_enc_cmpxchg(res, mem, oldval, newval));
 5212 
 5213   ins_pipe(pipe_slow);
 5214 %}
 5215 
 5216 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval)
 5217 %{
 5218   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5219 
 5220   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5221 
 5222   format %{
 5223     "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5224     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
 5225   %}
 5226 
 5227   ins_encode(riscv64_enc_cmpxchgn(res, mem, oldval, newval));
 5228 
 5229   ins_pipe(pipe_slow);
 5230 %}
 5231 
 5232 // alternative CompareAndSwapX when we are eliding barriers
 5233 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5234                             iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5235 %{
 5236   predicate(needs_acquiring_load_reserved(n));
 5237 
 5238   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5239 
 5240   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5241 
 5242   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5243 
 5244   format %{
 5245     "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5246     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
 5247   %}
 5248 
 5249   ins_encode %{
 5250     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5251                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5252                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5253   %}
 5254 
 5255   ins_pipe(pipe_slow);
 5256 %}
 5257 
 5258 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5259                             iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5260 %{
 5261   predicate(needs_acquiring_load_reserved(n));
 5262 
 5263   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5264 
 5265   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5266 
 5267   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5268 
 5269   format %{
 5270     "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5271     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
 5272   %}
 5273 
 5274   ins_encode %{
 5275     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5276                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5277                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5278   %}
 5279 
 5280   ins_pipe(pipe_slow);
 5281 %}
 5282 
 5283 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval)
 5284 %{
 5285   predicate(needs_acquiring_load_reserved(n));
 5286 
 5287   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5288 
 5289   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5290 
 5291   format %{
 5292     "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5293     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
 5294   %}
 5295 
 5296   ins_encode(riscv64_enc_cmpxchgw_acq(res, mem, oldval, newval));
 5297 
 5298   ins_pipe(pipe_slow);
 5299 %}
 5300 
 5301 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval)
 5302 %{
 5303   predicate(needs_acquiring_load_reserved(n));
 5304 
 5305   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5306 
 5307   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5308 
 5309   format %{
 5310     "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5311     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
 5312   %}
 5313 
 5314   ins_encode(riscv64_enc_cmpxchg_acq(res, mem, oldval, newval));
 5315 
 5316   ins_pipe(pipe_slow);
 5317 %}
 5318 
 5319 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5320 %{
 5321   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5322 
 5323   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5324 
 5325   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5326 
 5327   format %{
 5328     "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5329     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
 5330   %}
 5331 
 5332   ins_encode(riscv64_enc_cmpxchg_acq(res, mem, oldval, newval));
 5333 
 5334   ins_pipe(pipe_slow);
 5335 %}
 5336 
 5337 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval)
 5338 %{
 5339   predicate(needs_acquiring_load_reserved(n));
 5340 
 5341   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5342 
 5343   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5344 
 5345   format %{
 5346     "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5347     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
 5348   %}
 5349 
 5350   ins_encode(riscv64_enc_cmpxchgn_acq(res, mem, oldval, newval));
 5351 
 5352   ins_pipe(pipe_slow);
 5353 %}
 5354 
 5355 // Sundry CAS operations.  Note that release is always true,
 5356 // regardless of the memory ordering of the CAS.  This is because we
 5357 // need the volatile case to be sequentially consistent but there is
 5358 // no trailing StoreLoad barrier emitted by C2.  Unfortunately we
 5359 // can't check the type of memory ordering here, so we always emit a
 5360 // sc_d(w) with rl bit set.
 5361 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5362                              iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5363 %{
 5364   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5365 
 5366   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5367 
 5368   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5369 
 5370   format %{
 5371     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
 5372   %}
 5373 
 5374   ins_encode %{
 5375     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5376                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5377                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5378   %}
 5379 
 5380   ins_pipe(pipe_slow);
 5381 %}
 5382 
 5383 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5384                              iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5385 %{
 5386   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5387 
 5388   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5389 
 5390   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5391 
 5392   format %{
 5393     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
 5394   %}
 5395 
 5396   ins_encode %{
 5397     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5398                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5399                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5400   %}
 5401 
 5402   ins_pipe(pipe_slow);
 5403 %}
 5404 
 5405 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5406 %{
 5407   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5408 
 5409   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5410 
 5411   effect(TEMP_DEF res);
 5412 
 5413   format %{
 5414     "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
 5415   %}
 5416 
 5417   ins_encode %{
 5418     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5419                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5420   %}
 5421 
 5422   ins_pipe(pipe_slow);
 5423 %}
 5424 
 5425 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5426 %{
 5427   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5428 
 5429   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5430 
 5431   effect(TEMP_DEF res);
 5432 
 5433   format %{
 5434     "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
 5435   %}
 5436 
 5437   ins_encode %{
 5438     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5439                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5440   %}
 5441 
 5442   ins_pipe(pipe_slow);
 5443 %}
 5444 
 5445 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5446 %{
 5447   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5448 
 5449   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
 5450 
 5451   effect(TEMP_DEF res);
 5452 
 5453   format %{
 5454     "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
 5455   %}
 5456 
 5457   ins_encode %{
 5458     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5459                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5460   %}
 5461 
 5462   ins_pipe(pipe_slow);
 5463 %}
 5464 
 5465 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5466 %{
 5467   predicate(n->as_LoadStore()->barrier_data() == 0);
 5468   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5469 
 5470   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5471 
 5472   effect(TEMP_DEF res);
 5473 
 5474   format %{
 5475     "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
 5476   %}
 5477 
 5478   ins_encode %{
 5479     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5480                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5481   %}
 5482 
 5483   ins_pipe(pipe_slow);
 5484 %}
 5485 
 5486 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5487                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5488 %{
 5489   predicate(needs_acquiring_load_reserved(n));
 5490 
 5491   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5492 
 5493   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5494 
 5495   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5496 
 5497   format %{
 5498     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
 5499   %}
 5500 
 5501   ins_encode %{
 5502     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5503                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5504                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5505   %}
 5506 
 5507   ins_pipe(pipe_slow);
 5508 %}
 5509 
 5510 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5511                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5512 %{
 5513   predicate(needs_acquiring_load_reserved(n));
 5514 
 5515   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5516 
 5517   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5518 
 5519   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5520 
 5521   format %{
 5522     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
 5523   %}
 5524 
 5525   ins_encode %{
 5526     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5527                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5528                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5529   %}
 5530 
 5531   ins_pipe(pipe_slow);
 5532 %}
 5533 
 5534 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5535 %{
 5536   predicate(needs_acquiring_load_reserved(n));
 5537 
 5538   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5539 
 5540   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5541 
 5542   effect(TEMP_DEF res);
 5543 
 5544   format %{
 5545     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
 5546   %}
 5547 
 5548   ins_encode %{
 5549     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5550                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5551   %}
 5552 
 5553   ins_pipe(pipe_slow);
 5554 %}
 5555 
 5556 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5557 %{
 5558   predicate(needs_acquiring_load_reserved(n));
 5559 
 5560   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5561 
 5562   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5563 
 5564   effect(TEMP_DEF res);
 5565 
 5566   format %{
 5567     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
 5568   %}
 5569 
 5570   ins_encode %{
 5571     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5572                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5573   %}
 5574 
 5575   ins_pipe(pipe_slow);
 5576 %}
 5577 
 5578 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5579 %{
 5580   predicate(needs_acquiring_load_reserved(n));
 5581 
 5582   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5583 
 5584   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5585 
 5586   effect(TEMP_DEF res);
 5587 
 5588   format %{
 5589     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
 5590   %}
 5591 
 5592   ins_encode %{
 5593     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5594                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5595   %}
 5596 
 5597   ins_pipe(pipe_slow);
 5598 %}
 5599 
 5600 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5601 %{
 5602   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5603 
 5604   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5605 
 5606   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5607 
 5608   effect(TEMP_DEF res);
 5609 
 5610   format %{
 5611     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
 5612   %}
 5613 
 5614   ins_encode %{
 5615     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5616                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5617   %}
 5618 
 5619   ins_pipe(pipe_slow);
 5620 %}
 5621 
 5622 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5623                              iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5624 %{
 5625   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5626 
 5627   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5628 
 5629   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5630 
 5631   format %{
 5632     "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5633     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapB"
 5634   %}
 5635 
 5636   ins_encode %{
 5637     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5638                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5639                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5640     __ xori($res$$Register, $res$$Register, 1);
 5641   %}
 5642 
 5643   ins_pipe(pipe_slow);
 5644 %}
 5645 
 5646 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5647                              iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5648 %{
 5649   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5650 
 5651   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5652 
 5653   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5654 
 5655   format %{
 5656     "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5657     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapS"
 5658   %}
 5659 
 5660   ins_encode %{
 5661     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5662                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5663                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5664     __ xori($res$$Register, $res$$Register, 1);
 5665   %}
 5666 
 5667   ins_pipe(pipe_slow);
 5668 %}
 5669 
 5670 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5671 %{
 5672   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5673 
 5674   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5675 
 5676   format %{
 5677     "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5678     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapI"
 5679   %}
 5680 
 5681   ins_encode %{
 5682     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5683                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5684     __ xori($res$$Register, $res$$Register, 1);
 5685   %}
 5686 
 5687   ins_pipe(pipe_slow);
 5688 %}
 5689 
 5690 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5691 %{
 5692   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5693 
 5694   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5695 
 5696   format %{
 5697     "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5698     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapL"
 5699   %}
 5700 
 5701   ins_encode %{
 5702     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5703                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5704     __ xori($res$$Register, $res$$Register, 1);
 5705   %}
 5706 
 5707   ins_pipe(pipe_slow);
 5708 %}
 5709 
 5710 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5711 %{
 5712   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5713 
 5714   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5715 
 5716   format %{
 5717     "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5718     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapN"
 5719   %}
 5720 
 5721   ins_encode %{
 5722     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5723                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5724     __ xori($res$$Register, $res$$Register, 1);
 5725   %}
 5726 
 5727   ins_pipe(pipe_slow);
 5728 %}
 5729 
 5730 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5731 %{
 5732   predicate(n->as_LoadStore()->barrier_data() == 0);
 5733   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5734 
 5735   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5736 
 5737   format %{
 5738     "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5739     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapP"
 5740   %}
 5741 
 5742   ins_encode %{
 5743     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5744                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5745     __ xori($res$$Register, $res$$Register, 1);
 5746   %}
 5747 
 5748   ins_pipe(pipe_slow);
 5749 %}
 5750 
 5751 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5752                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5753 %{
 5754   predicate(needs_acquiring_load_reserved(n));
 5755 
 5756   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5757 
 5758   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5759 
 5760   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5761 
 5762   format %{
 5763     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5764     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapBAcq"
 5765   %}
 5766 
 5767   ins_encode %{
 5768     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5769                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5770                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5771     __ xori($res$$Register, $res$$Register, 1);
 5772   %}
 5773 
 5774   ins_pipe(pipe_slow);
 5775 %}
 5776 
 5777 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5778                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegL_R6 cr)
 5779 %{
 5780   predicate(needs_acquiring_load_reserved(n));
 5781 
 5782   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5783 
 5784   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5785 
 5786   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5787 
 5788   format %{
 5789     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5790     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapSAcq"
 5791   %}
 5792 
 5793   ins_encode %{
 5794     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5795                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5796                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5797     __ xori($res$$Register, $res$$Register, 1);
 5798   %}
 5799 
 5800   ins_pipe(pipe_slow);
 5801 %}
 5802 
 5803 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5804 %{
 5805   predicate(needs_acquiring_load_reserved(n));
 5806 
 5807   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5808 
 5809   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5810 
 5811   format %{
 5812     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5813     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapIAcq"
 5814   %}
 5815 
 5816   ins_encode %{
 5817     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5818                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5819     __ xori($res$$Register, $res$$Register, 1);
 5820   %}
 5821 
 5822   ins_pipe(pipe_slow);
 5823 %}
 5824 
 5825 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5826 %{
 5827   predicate(needs_acquiring_load_reserved(n));
 5828 
 5829   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5830 
 5831   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5832 
 5833   format %{
 5834     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5835     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapLAcq"
 5836   %}
 5837 
 5838   ins_encode %{
 5839     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5840                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5841     __ xori($res$$Register, $res$$Register, 1);
 5842   %}
 5843 
 5844   ins_pipe(pipe_slow);
 5845 %}
 5846 
 5847 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5848 %{
 5849   predicate(needs_acquiring_load_reserved(n));
 5850 
 5851   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5852 
 5853   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5854 
 5855   format %{
 5856     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5857     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapNAcq"
 5858   %}
 5859 
 5860   ins_encode %{
 5861     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5862                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5863     __ xori($res$$Register, $res$$Register, 1);
 5864   %}
 5865 
 5866   ins_pipe(pipe_slow);
 5867 %}
 5868 
 5869 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5870 %{
 5871   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5872 
 5873   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5874 
 5875   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5876 
 5877   format %{
 5878     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5879     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
 5880   %}
 5881 
 5882   ins_encode %{
 5883     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5884                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5885     __ xori($res$$Register, $res$$Register, 1);
 5886   %}
 5887 
 5888   ins_pipe(pipe_slow);
 5889 %}
 5890 
 5891 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
 5892 %{
 5893   match(Set prev (GetAndSetI mem newv));
 5894 
 5895   ins_cost(ALU_COST);
 5896 
 5897   format %{ "atomic_xchgw  $prev, $newv, [$mem]\t#@get_and_setI" %}
 5898 
 5899   ins_encode %{
 5900     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5901   %}
 5902 
 5903   ins_pipe(pipe_serial);
 5904 %}
 5905 
 5906 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
 5907 %{
 5908   match(Set prev (GetAndSetL mem newv));
 5909 
 5910   ins_cost(ALU_COST);
 5911 
 5912   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setL" %}
 5913 
 5914   ins_encode %{
 5915     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5916   %}
 5917 
 5918   ins_pipe(pipe_serial);
 5919 %}
 5920 
 5921 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
 5922 %{
 5923   match(Set prev (GetAndSetN mem newv));
 5924 
 5925   ins_cost(ALU_COST);
 5926 
 5927   format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
 5928 
 5929   ins_encode %{
 5930     __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5931   %}
 5932 
 5933   ins_pipe(pipe_serial);
 5934 %}
 5935 
 5936 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
 5937 %{
 5938   predicate(n->as_LoadStore()->barrier_data() == 0);
 5939   match(Set prev (GetAndSetP mem newv));
 5940 
 5941   ins_cost(ALU_COST);
 5942 
 5943   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setP" %}
 5944 
 5945   ins_encode %{
 5946     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5947   %}
 5948 
 5949   ins_pipe(pipe_serial);
 5950 %}
 5951 
 5952 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
 5953 %{
 5954   predicate(needs_acquiring_load_reserved(n));
 5955 
 5956   match(Set prev (GetAndSetI mem newv));
 5957 
 5958   ins_cost(ALU_COST);
 5959 
 5960   format %{ "atomic_xchgw_acq  $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
 5961 
 5962   ins_encode %{
 5963     __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5964   %}
 5965 
 5966   ins_pipe(pipe_serial);
 5967 %}
 5968 
 5969 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
 5970 %{
 5971   predicate(needs_acquiring_load_reserved(n));
 5972 
 5973   match(Set prev (GetAndSetL mem newv));
 5974 
 5975   ins_cost(ALU_COST);
 5976 
 5977   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
 5978 
 5979   ins_encode %{
 5980     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5981   %}
 5982 
 5983   ins_pipe(pipe_serial);
 5984 %}
 5985 
 5986 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
 5987 %{
 5988   predicate(needs_acquiring_load_reserved(n));
 5989 
 5990   match(Set prev (GetAndSetN mem newv));
 5991 
 5992   ins_cost(ALU_COST);
 5993 
 5994   format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
 5995 
 5996   ins_encode %{
 5997     __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 5998   %}
 5999 
 6000   ins_pipe(pipe_serial);
 6001 %}
 6002 
 6003 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
 6004 %{
 6005   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6006 
 6007   match(Set prev (GetAndSetP mem newv));
 6008 
 6009   ins_cost(ALU_COST);
 6010 
 6011   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
 6012 
 6013   ins_encode %{
 6014     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6015   %}
 6016 
 6017   ins_pipe(pipe_serial);
 6018 %}
 6019 
 6020 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
 6021 %{
 6022   match(Set newval (GetAndAddL mem incr));
 6023 
 6024   ins_cost(ALU_COST);
 6025 
 6026   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
 6027 
 6028   ins_encode %{
 6029     __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6030   %}
 6031 
 6032   ins_pipe(pipe_serial);
 6033 %}
 6034 
 6035 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
 6036 %{
 6037   predicate(n->as_LoadStore()->result_not_used());
 6038 
 6039   match(Set dummy (GetAndAddL mem incr));
 6040 
 6041   ins_cost(ALU_COST);
 6042 
 6043   format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
 6044 
 6045   ins_encode %{
 6046     __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
 6047   %}
 6048 
 6049   ins_pipe(pipe_serial);
 6050 %}
 6051 
 6052 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
 6053 %{
 6054   match(Set newval (GetAndAddL mem incr));
 6055 
 6056   ins_cost(ALU_COST);
 6057 
 6058   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
 6059 
 6060   ins_encode %{
 6061     __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6062   %}
 6063 
 6064   ins_pipe(pipe_serial);
 6065 %}
 6066 
 6067 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
 6068 %{
 6069   predicate(n->as_LoadStore()->result_not_used());
 6070 
 6071   match(Set dummy (GetAndAddL mem incr));
 6072 
 6073   ins_cost(ALU_COST);
 6074 
 6075   format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
 6076 
 6077   ins_encode %{
 6078     __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
 6079   %}
 6080 
 6081   ins_pipe(pipe_serial);
 6082 %}
 6083 
 6084 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6085 %{
 6086   match(Set newval (GetAndAddI mem incr));
 6087 
 6088   ins_cost(ALU_COST);
 6089 
 6090   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
 6091 
 6092   ins_encode %{
 6093     __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6094   %}
 6095 
 6096   ins_pipe(pipe_serial);
 6097 %}
 6098 
 6099 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
 6100 %{
 6101   predicate(n->as_LoadStore()->result_not_used());
 6102 
 6103   match(Set dummy (GetAndAddI mem incr));
 6104 
 6105   ins_cost(ALU_COST);
 6106 
 6107   format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
 6108 
 6109   ins_encode %{
 6110     __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
 6111   %}
 6112 
 6113   ins_pipe(pipe_serial);
 6114 %}
 6115 
 6116 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
 6117 %{
 6118   match(Set newval (GetAndAddI mem incr));
 6119 
 6120   ins_cost(ALU_COST);
 6121 
 6122   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
 6123 
 6124   ins_encode %{
 6125     __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6126   %}
 6127 
 6128   ins_pipe(pipe_serial);
 6129 %}
 6130 
 6131 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
 6132 %{
 6133   predicate(n->as_LoadStore()->result_not_used());
 6134 
 6135   match(Set dummy (GetAndAddI mem incr));
 6136 
 6137   ins_cost(ALU_COST);
 6138 
 6139   format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
 6140 
 6141   ins_encode %{
 6142     __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
 6143   %}
 6144 
 6145   ins_pipe(pipe_serial);
 6146 %}
 6147 
 6148 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
 6149 %{
 6150   predicate(needs_acquiring_load_reserved(n));
 6151 
 6152   match(Set newval (GetAndAddL mem incr));
 6153 
 6154   ins_cost(ALU_COST);
 6155 
 6156   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
 6157 
 6158   ins_encode %{
 6159     __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6160   %}
 6161 
 6162   ins_pipe(pipe_serial);
 6163 %}
 6164 
 6165 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
 6166   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6167 
 6168   match(Set dummy (GetAndAddL mem incr));
 6169 
 6170   ins_cost(ALU_COST);
 6171 
 6172   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
 6173 
 6174   ins_encode %{
 6175     __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
 6176   %}
 6177 
 6178   ins_pipe(pipe_serial);
 6179 %}
 6180 
 6181 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
 6182 %{
 6183   predicate(needs_acquiring_load_reserved(n));
 6184 
 6185   match(Set newval (GetAndAddL mem incr));
 6186 
 6187   ins_cost(ALU_COST);
 6188 
 6189   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
 6190 
 6191   ins_encode %{
 6192     __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6193   %}
 6194 
 6195   ins_pipe(pipe_serial);
 6196 %}
 6197 
 6198 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
 6199 %{
 6200   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6201 
 6202   match(Set dummy (GetAndAddL mem incr));
 6203 
 6204   ins_cost(ALU_COST);
 6205 
 6206   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
 6207 
 6208   ins_encode %{
 6209     __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
 6210   %}
 6211 
 6212   ins_pipe(pipe_serial);
 6213 %}
 6214 
 6215 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6216 %{
 6217   predicate(needs_acquiring_load_reserved(n));
 6218 
 6219   match(Set newval (GetAndAddI mem incr));
 6220 
 6221   ins_cost(ALU_COST);
 6222 
 6223   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
 6224 
 6225   ins_encode %{
 6226     __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6227   %}
 6228 
 6229   ins_pipe(pipe_serial);
 6230 %}
 6231 
 6232 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
 6233 %{
 6234   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6235 
 6236   match(Set dummy (GetAndAddI mem incr));
 6237 
 6238   ins_cost(ALU_COST);
 6239 
 6240   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
 6241 
 6242   ins_encode %{
 6243     __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
 6244   %}
 6245 
 6246   ins_pipe(pipe_serial);
 6247 %}
 6248 
 6249 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
 6250 %{
 6251   predicate(needs_acquiring_load_reserved(n));
 6252 
 6253   match(Set newval (GetAndAddI mem incr));
 6254 
 6255   ins_cost(ALU_COST);
 6256 
 6257   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
 6258 
 6259   ins_encode %{
 6260     __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6261   %}
 6262 
 6263   ins_pipe(pipe_serial);
 6264 %}
 6265 
 6266 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
 6267 %{
 6268   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6269 
 6270   match(Set dummy (GetAndAddI mem incr));
 6271 
 6272   ins_cost(ALU_COST);
 6273 
 6274   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
 6275 
 6276   ins_encode %{
 6277     __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
 6278   %}
 6279 
 6280   ins_pipe(pipe_serial);
 6281 %}
 6282 
 6283 // ============================================================================
 6284 // Arithmetic Instructions
 6285 //
 6286 
 6287 // Integer Addition
 6288 
 6289 // TODO
 6290 // these currently employ operations which do not set CR and hence are
 6291 // not flagged as killing CR but we would like to isolate the cases
 6292 // where we want to set flags from those where we don't. need to work
 6293 // out how to do that.
 6294 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6295   match(Set dst (AddI src1 src2));
 6296 
 6297   ins_cost(ALU_COST);
 6298   format %{ "addw  $dst, $src1, $src2\t#@addI_reg_reg" %}
 6299 
 6300   ins_encode %{
 6301     __ addw(as_Register($dst$$reg),
 6302             as_Register($src1$$reg),
 6303             as_Register($src2$$reg));
 6304   %}
 6305 
 6306   ins_pipe(ialu_reg_reg);
 6307 %}
 6308 
 6309 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 6310   match(Set dst (AddI src1 src2));
 6311 
 6312   ins_cost(ALU_COST);
 6313   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm" %}
 6314 
 6315   ins_encode %{
 6316     int32_t con = (int32_t)$src2$$constant;
 6317     __ addiw(as_Register($dst$$reg),
 6318              as_Register($src1$$reg),
 6319              $src2$$constant);
 6320   %}
 6321 
 6322   ins_pipe(ialu_reg_imm);
 6323 %}
 6324 
 6325 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
 6326   match(Set dst (AddI (ConvL2I src1) src2));
 6327 
 6328   ins_cost(ALU_COST);
 6329   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
 6330 
 6331   ins_encode %{
 6332     __ addiw(as_Register($dst$$reg),
 6333              as_Register($src1$$reg),
 6334              $src2$$constant);
 6335   %}
 6336 
 6337   ins_pipe(ialu_reg_imm);
 6338 %}
 6339 
 6340 // Pointer Addition
 6341 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
 6342   match(Set dst (AddP src1 src2));
 6343 
 6344   ins_cost(ALU_COST);
 6345   format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
 6346 
 6347   ins_encode %{
 6348     __ add(as_Register($dst$$reg),
 6349            as_Register($src1$$reg),
 6350            as_Register($src2$$reg));
 6351   %}
 6352 
 6353   ins_pipe(ialu_reg_reg);
 6354 %}
 6355 
 6356 // If we shift more than 32 bits, we need not convert I2L.
 6357 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegIorL2I src, uimmI6_ge32 scale) %{
 6358   match(Set dst (LShiftL (ConvI2L src) scale));
 6359   ins_cost(ALU_COST);
 6360   format %{ "slli  $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
 6361 
 6362   ins_encode %{
 6363     __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
 6364   %}
 6365 
 6366   ins_pipe(ialu_reg_shift);
 6367 %}
 6368 
 6369 // Pointer Immediate Addition
 6370 // n.b. this needs to be more expensive than using an indirect memory
 6371 // operand
 6372 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
 6373   match(Set dst (AddP src1 src2));
 6374   ins_cost(ALU_COST);
 6375   format %{ "addi  $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
 6376 
 6377   ins_encode %{
 6378     // src2 is imm, so actually call the addi
 6379     __ add(as_Register($dst$$reg),
 6380            as_Register($src1$$reg),
 6381            $src2$$constant);
 6382   %}
 6383 
 6384   ins_pipe(ialu_reg_imm);
 6385 %}
 6386 
 6387 // Long Addition
 6388 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6389   match(Set dst (AddL src1 src2));
 6390   ins_cost(ALU_COST);
 6391   format %{ "add  $dst, $src1, $src2\t#@addL_reg_reg" %}
 6392 
 6393   ins_encode %{
 6394     __ add(as_Register($dst$$reg),
 6395            as_Register($src1$$reg),
 6396            as_Register($src2$$reg));
 6397   %}
 6398 
 6399   ins_pipe(ialu_reg_reg);
 6400 %}
 6401 
 6402 // No constant pool entries requiredLong Immediate Addition.
 6403 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 6404   match(Set dst (AddL src1 src2));
 6405   ins_cost(ALU_COST);
 6406   format %{ "addi  $dst, $src1, $src2\t#@addL_reg_imm" %}
 6407 
 6408   ins_encode %{
 6409     // src2 is imm, so actually call the addi
 6410     __ add(as_Register($dst$$reg),
 6411            as_Register($src1$$reg),
 6412            $src2$$constant);
 6413   %}
 6414 
 6415   ins_pipe(ialu_reg_imm);
 6416 %}
 6417 
 6418 // Integer Subtraction
 6419 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6420   match(Set dst (SubI src1 src2));
 6421 
 6422   ins_cost(ALU_COST);
 6423   format %{ "subw  $dst, $src1, $src2\t#@subI_reg_reg" %}
 6424 
 6425   ins_encode %{
 6426     __ subw(as_Register($dst$$reg),
 6427             as_Register($src1$$reg),
 6428             as_Register($src2$$reg));
 6429   %}
 6430 
 6431   ins_pipe(ialu_reg_reg);
 6432 %}
 6433 
 6434 // Immediate Subtraction
 6435 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
 6436   match(Set dst (SubI src1 src2));
 6437 
 6438   ins_cost(ALU_COST);
 6439   format %{ "addiw  $dst, $src1, -$src2\t#@subI_reg_imm" %}
 6440 
 6441   ins_encode %{
 6442     // src2 is imm, so actually call the addiw
 6443     __ subw(as_Register($dst$$reg),
 6444             as_Register($src1$$reg),
 6445             $src2$$constant);
 6446   %}
 6447 
 6448   ins_pipe(ialu_reg_imm);
 6449 %}
 6450 
 6451 // Long Subtraction
 6452 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6453   match(Set dst (SubL src1 src2));
 6454   ins_cost(ALU_COST);
 6455   format %{ "sub  $dst, $src1, $src2\t#@subL_reg_reg" %}
 6456 
 6457   ins_encode %{
 6458     __ sub(as_Register($dst$$reg),
 6459            as_Register($src1$$reg),
 6460            as_Register($src2$$reg));
 6461   %}
 6462 
 6463   ins_pipe(ialu_reg_reg);
 6464 %}
 6465 
 6466 // No constant pool entries requiredLong Immediate Subtraction.
 6467 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
 6468   match(Set dst (SubL src1 src2));
 6469   ins_cost(ALU_COST);
 6470   format %{ "addi  $dst, $src1, -$src2\t#@subL_reg_imm" %}
 6471 
 6472   ins_encode %{
 6473     // src2 is imm, so actually call the addi
 6474     __ sub(as_Register($dst$$reg),
 6475            as_Register($src1$$reg),
 6476            $src2$$constant);
 6477   %}
 6478 
 6479   ins_pipe(ialu_reg_imm);
 6480 %}
 6481 
 6482 // Integer Negation (special case for sub)
 6483 
 6484 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
 6485   match(Set dst (SubI zero src));
 6486   ins_cost(ALU_COST);
 6487   format %{ "subw  $dst, x0, $src\t# int, #@negI_reg" %}
 6488 
 6489   ins_encode %{
 6490     // actually call the subw
 6491     __ negw(as_Register($dst$$reg),
 6492             as_Register($src$$reg));
 6493   %}
 6494 
 6495   ins_pipe(ialu_reg);
 6496 %}
 6497 
 6498 // Long Negation
 6499 
 6500 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
 6501   match(Set dst (SubL zero src));
 6502   ins_cost(ALU_COST);
 6503   format %{ "sub  $dst, x0, $src\t# long, #@negL_reg" %}
 6504 
 6505   ins_encode %{
 6506     // actually call the sub
 6507     __ neg(as_Register($dst$$reg),
 6508            as_Register($src$$reg));
 6509   %}
 6510 
 6511   ins_pipe(ialu_reg);
 6512 %}
 6513 
 6514 // Integer Multiply
 6515 
 6516 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6517   match(Set dst (MulI src1 src2));
 6518   ins_cost(IMUL_COST);
 6519   format %{ "mulw  $dst, $src1, $src2\t#@mulI" %}
 6520 
 6521   //this means 2 word multi, and no sign extend to 64 bits
 6522   ins_encode %{
 6523     // riscv64 mulw will sign-extension to high 32 bits in dst reg
 6524     __ mulw(as_Register($dst$$reg),
 6525             as_Register($src1$$reg),
 6526             as_Register($src2$$reg));
 6527   %}
 6528 
 6529   ins_pipe(imul_reg_reg);
 6530 %}
 6531 
 6532 instruct smulI(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6533   match(Set dst (MulL (ConvI2L src1) (ConvI2L src2)));
 6534   ins_cost(IMUL_COST);
 6535   format %{ "mul  $dst, $src1, $src2\t#@smulI" %}
 6536 
 6537   // Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result.
 6538   ins_encode %{
 6539     __ mul(as_Register($dst$$reg),
 6540             as_Register($src1$$reg),
 6541             as_Register($src2$$reg));
 6542   %}
 6543 
 6544   ins_pipe(imul_reg_reg);
 6545 %}
 6546 
 6547 // Long Multiply
 6548 
 6549 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6550   match(Set dst (MulL src1 src2));
 6551   ins_cost(IMUL_COST);
 6552   format %{ "mul  $dst, $src1, $src2\t#@mulL" %}
 6553 
 6554   ins_encode %{
 6555     __ mul(as_Register($dst$$reg),
 6556            as_Register($src1$$reg),
 6557            as_Register($src2$$reg));
 6558   %}
 6559 
 6560   ins_pipe(lmul_reg_reg);
 6561 %}
 6562 
 6563 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
 6564 %{
 6565   match(Set dst (MulHiL src1 src2));
 6566   ins_cost(IMUL_COST);
 6567   format %{ "mulh  $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
 6568 
 6569   ins_encode %{
 6570     __ mulh(as_Register($dst$$reg),
 6571             as_Register($src1$$reg),
 6572             as_Register($src2$$reg));
 6573   %}
 6574 
 6575   ins_pipe(lmul_reg_reg);
 6576 %}
 6577 
 6578 // Integer Divide
 6579 
 6580 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6581   match(Set dst (DivI src1 src2));
 6582   ins_cost(IDIVSI_COST);
 6583   format %{ "divw  $dst, $src1, $src2\t#@divI"%}
 6584 
 6585   ins_encode(riscv64_enc_divw(dst, src1, src2));
 6586   ins_pipe(idiv_reg_reg);
 6587 %}
 6588 
 6589 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
 6590   match(Set dst (URShiftI (RShiftI src1 div1) div2));
 6591   ins_cost(ALU_COST);
 6592   format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
 6593 
 6594   ins_encode %{
 6595     __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
 6596   %}
 6597   ins_pipe(ialu_reg_shift);
 6598 %}
 6599 
 6600 // Long Divide
 6601 
 6602 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6603   match(Set dst (DivL src1 src2));
 6604   ins_cost(IDIVDI_COST);
 6605   format %{ "div  $dst, $src1, $src2\t#@divL" %}
 6606 
 6607   ins_encode(riscv64_enc_div(dst, src1, src2));
 6608   ins_pipe(ldiv_reg_reg);
 6609 %}
 6610 
 6611 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
 6612   match(Set dst (URShiftL (RShiftL src1 div1) div2));
 6613   ins_cost(ALU_COST);
 6614   format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
 6615 
 6616   ins_encode %{
 6617     __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
 6618   %}
 6619   ins_pipe(ialu_reg_shift);
 6620 %}
 6621 
 6622 // Integer Remainder
 6623 
 6624 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6625   match(Set dst (ModI src1 src2));
 6626   ins_cost(IDIVSI_COST);
 6627   format %{ "remw  $dst, $src1, $src2\t#@modI" %}
 6628 
 6629   ins_encode(riscv64_enc_modw(dst, src1, src2));
 6630   ins_pipe(ialu_reg_reg);
 6631 %}
 6632 
 6633 // Long Remainder
 6634 
 6635 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6636   match(Set dst (ModL src1 src2));
 6637   ins_cost(IDIVDI_COST);
 6638   format %{ "rem  $dst, $src1, $src2\t#@modL" %}
 6639 
 6640   ins_encode(riscv64_enc_mod(dst, src1, src2));
 6641   ins_pipe(ialu_reg_reg);
 6642 %}
 6643 
 6644 // Integer Shifts
 6645 
 6646 // Shift Left Register
 6647 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6648   match(Set dst (LShiftI src1 src2));
 6649   ins_cost(ALU_COST);
 6650   format %{ "sllw  $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
 6651 
 6652   ins_encode %{
 6653     __ sllw(as_Register($dst$$reg),
 6654             as_Register($src1$$reg),
 6655             as_Register($src2$$reg));
 6656   %}
 6657 
 6658   ins_pipe(ialu_reg_reg_vshift);
 6659 %}
 6660 
 6661 // Shift Left Immediate
 6662 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6663   match(Set dst (LShiftI src1 src2));
 6664   ins_cost(ALU_COST);
 6665   format %{ "slliw  $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
 6666 
 6667   ins_encode %{
 6668     // the shift amount is encoded in the lower
 6669     // 5 bits of the I-immediate field for RV32I
 6670     __ slliw(as_Register($dst$$reg),
 6671              as_Register($src1$$reg),
 6672              (unsigned) $src2$$constant & 0x1f);
 6673   %}
 6674 
 6675   ins_pipe(ialu_reg_shift);
 6676 %}
 6677 
 6678 // Shift Right Logical Register
 6679 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6680   match(Set dst (URShiftI src1 src2));
 6681   ins_cost(ALU_COST);
 6682   format %{ "srlw  $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
 6683 
 6684   ins_encode %{
 6685     __ srlw(as_Register($dst$$reg),
 6686             as_Register($src1$$reg),
 6687             as_Register($src2$$reg));
 6688   %}
 6689 
 6690   ins_pipe(ialu_reg_reg_vshift);
 6691 %}
 6692 
 6693 // Shift Right Logical Immediate
 6694 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6695   match(Set dst (URShiftI src1 src2));
 6696   ins_cost(ALU_COST);
 6697   format %{ "srliw  $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
 6698 
 6699   ins_encode %{
 6700     // the shift amount is encoded in the lower
 6701     // 6 bits of the I-immediate field for RV64I
 6702     __ srliw(as_Register($dst$$reg),
 6703              as_Register($src1$$reg),
 6704              (unsigned) $src2$$constant & 0x1f);
 6705   %}
 6706 
 6707   ins_pipe(ialu_reg_shift);
 6708 %}
 6709 
 6710 // Shift Right Arithmetic Register
 6711 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6712   match(Set dst (RShiftI src1 src2));
 6713   ins_cost(ALU_COST);
 6714   format %{ "sraw  $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
 6715 
 6716   ins_encode %{
 6717     // riscv will sign-ext dst high 32 bits
 6718     __ sraw(as_Register($dst$$reg),
 6719             as_Register($src1$$reg),
 6720             as_Register($src2$$reg));
 6721   %}
 6722 
 6723   ins_pipe(ialu_reg_reg_vshift);
 6724 %}
 6725 
 6726 // Shift Right Arithmetic Immediate
 6727 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6728   match(Set dst (RShiftI src1 src2));
 6729   ins_cost(ALU_COST);
 6730   format %{ "sraiw  $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
 6731 
 6732   ins_encode %{
 6733     // riscv will sign-ext dst high 32 bits
 6734     __ sraiw(as_Register($dst$$reg),
 6735              as_Register($src1$$reg),
 6736              (unsigned) $src2$$constant & 0x1f);
 6737   %}
 6738 
 6739   ins_pipe(ialu_reg_shift);
 6740 %}
 6741 
 6742 // Long Shifts
 6743 
 6744 // Shift Left Register
 6745 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6746   match(Set dst (LShiftL src1 src2));
 6747 
 6748   ins_cost(ALU_COST);
 6749   format %{ "sll  $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
 6750 
 6751   ins_encode %{
 6752     __ sll(as_Register($dst$$reg),
 6753            as_Register($src1$$reg),
 6754            as_Register($src2$$reg));
 6755   %}
 6756 
 6757   ins_pipe(ialu_reg_reg_vshift);
 6758 %}
 6759 
 6760 // Shift Left Immediate
 6761 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6762   match(Set dst (LShiftL src1 src2));
 6763 
 6764   ins_cost(ALU_COST);
 6765   format %{ "slli  $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
 6766 
 6767   ins_encode %{
 6768     // the shift amount is encoded in the lower
 6769     // 6 bits of the I-immediate field for RV64I
 6770     __ slli(as_Register($dst$$reg),
 6771             as_Register($src1$$reg),
 6772             (unsigned) $src2$$constant & 0x3f);
 6773   %}
 6774 
 6775   ins_pipe(ialu_reg_shift);
 6776 %}
 6777 
 6778 // Shift Right Logical Register
 6779 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6780   match(Set dst (URShiftL src1 src2));
 6781 
 6782   ins_cost(ALU_COST);
 6783   format %{ "srl  $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
 6784 
 6785   ins_encode %{
 6786     __ srl(as_Register($dst$$reg),
 6787             as_Register($src1$$reg),
 6788             as_Register($src2$$reg));
 6789   %}
 6790 
 6791   ins_pipe(ialu_reg_reg_vshift);
 6792 %}
 6793 
 6794 // Shift Right Logical Immediate
 6795 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6796   match(Set dst (URShiftL src1 src2));
 6797 
 6798   ins_cost(ALU_COST);
 6799   format %{ "srli  $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
 6800 
 6801   ins_encode %{
 6802     // the shift amount is encoded in the lower
 6803     // 6 bits of the I-immediate field for RV64I
 6804     __ srli(as_Register($dst$$reg),
 6805             as_Register($src1$$reg),
 6806             (unsigned) $src2$$constant & 0x3f);
 6807   %}
 6808 
 6809   ins_pipe(ialu_reg_shift);
 6810 %}
 6811 
 6812 // A special-case pattern for card table stores.
 6813 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
 6814   match(Set dst (URShiftL (CastP2X src1) src2));
 6815 
 6816   ins_cost(ALU_COST);
 6817   format %{ "srli  $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
 6818 
 6819   ins_encode %{
 6820     // the shift amount is encoded in the lower
 6821     // 6 bits of the I-immediate field for RV64I
 6822     __ srli(as_Register($dst$$reg),
 6823             as_Register($src1$$reg),
 6824             (unsigned) $src2$$constant & 0x3f);
 6825   %}
 6826 
 6827   ins_pipe(ialu_reg_shift);
 6828 %}
 6829 
 6830 // Shift Right Arithmetic Register
 6831 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6832   match(Set dst (RShiftL src1 src2));
 6833 
 6834   ins_cost(ALU_COST);
 6835   format %{ "sra  $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
 6836 
 6837   ins_encode %{
 6838     __ sra(as_Register($dst$$reg),
 6839            as_Register($src1$$reg),
 6840            as_Register($src2$$reg));
 6841   %}
 6842 
 6843   ins_pipe(ialu_reg_reg_vshift);
 6844 %}
 6845 
 6846 // Shift Right Arithmetic Immediate
 6847 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6848   match(Set dst (RShiftL src1 src2));
 6849 
 6850   ins_cost(ALU_COST);
 6851   format %{ "srai  $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
 6852 
 6853   ins_encode %{
 6854     // the shift amount is encoded in the lower
 6855     // 6 bits of the I-immediate field for RV64I
 6856     __ srai(as_Register($dst$$reg),
 6857             as_Register($src1$$reg),
 6858             (unsigned) $src2$$constant & 0x3f);
 6859   %}
 6860 
 6861   ins_pipe(ialu_reg_shift);
 6862 %}
 6863 
 6864 instruct regI_not_reg(iRegINoSp dst,
 6865                          iRegIorL2I src1, immI_M1 m1) %{
 6866   match(Set dst (XorI src1 m1));
 6867   ins_cost(ALU_COST);
 6868   format %{ "xori  $dst, $src1, -1\t#@regI_not_reg" %}
 6869 
 6870   ins_encode %{
 6871     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 6872   %}
 6873 
 6874   ins_pipe(ialu_reg);
 6875 %}
 6876 
 6877 instruct regL_not_reg(iRegLNoSp dst,
 6878                       iRegL src1, immL_M1 m1) %{
 6879   match(Set dst (XorL src1 m1));
 6880   ins_cost(ALU_COST);
 6881   format %{ "xori  $dst, $src1, -1\t#@regL_not_reg" %}
 6882 
 6883   ins_encode %{
 6884     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 6885   %}
 6886 
 6887   ins_pipe(ialu_reg);
 6888 %}
 6889 
 6890 
 6891 // ============================================================================
 6892 // Floating Point Arithmetic Instructions
 6893 
 6894 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 6895   match(Set dst (AddF src1 src2));
 6896 
 6897   ins_cost(FMUL_SINGLE_COST);
 6898   format %{ "fadd.s  $dst, $src1, $src2\t#@addF_reg_reg" %}
 6899 
 6900   ins_encode %{
 6901     __ fadd_s(as_FloatRegister($dst$$reg),
 6902               as_FloatRegister($src1$$reg),
 6903               as_FloatRegister($src2$$reg));
 6904   %}
 6905 
 6906   ins_pipe(fp_dop_reg_reg_s);
 6907 %}
 6908 
 6909 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 6910   match(Set dst (AddD src1 src2));
 6911 
 6912   ins_cost(FMUL_DOUBLE_COST);
 6913   format %{ "fadd.d  $dst, $src1, $src2\t#@addD_reg_reg" %}
 6914 
 6915   ins_encode %{
 6916     __ fadd_d(as_FloatRegister($dst$$reg),
 6917               as_FloatRegister($src1$$reg),
 6918               as_FloatRegister($src2$$reg));
 6919   %}
 6920 
 6921   ins_pipe(fp_dop_reg_reg_d);
 6922 %}
 6923 
 6924 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 6925   match(Set dst (SubF src1 src2));
 6926 
 6927   ins_cost(FMUL_SINGLE_COST);
 6928   format %{ "fsub.s  $dst, $src1, $src2\t#@subF_reg_reg" %}
 6929 
 6930   ins_encode %{
 6931     __ fsub_s(as_FloatRegister($dst$$reg),
 6932               as_FloatRegister($src1$$reg),
 6933               as_FloatRegister($src2$$reg));
 6934   %}
 6935 
 6936   ins_pipe(fp_dop_reg_reg_s);
 6937 %}
 6938 
 6939 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 6940   match(Set dst (SubD src1 src2));
 6941 
 6942   ins_cost(FMUL_DOUBLE_COST);
 6943   format %{ "fsub.d  $dst, $src1, $src2\t#@subD_reg_reg" %}
 6944 
 6945   ins_encode %{
 6946     __ fsub_d(as_FloatRegister($dst$$reg),
 6947               as_FloatRegister($src1$$reg),
 6948               as_FloatRegister($src2$$reg));
 6949   %}
 6950 
 6951   ins_pipe(fp_dop_reg_reg_d);
 6952 %}
 6953 
 6954 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 6955   match(Set dst (MulF src1 src2));
 6956 
 6957   ins_cost(FMUL_SINGLE_COST);
 6958   format %{ "fmul.s  $dst, $src1, $src2\t#@mulF_reg_reg" %}
 6959 
 6960   ins_encode %{
 6961     __ fmul_s(as_FloatRegister($dst$$reg),
 6962               as_FloatRegister($src1$$reg),
 6963               as_FloatRegister($src2$$reg));
 6964   %}
 6965 
 6966   ins_pipe(fp_dop_reg_reg_s);
 6967 %}
 6968 
 6969 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 6970   match(Set dst (MulD src1 src2));
 6971 
 6972   ins_cost(FMUL_DOUBLE_COST);
 6973   format %{ "fmul.d  $dst, $src1, $src2\t#@mulD_reg_reg" %}
 6974 
 6975   ins_encode %{
 6976     __ fmul_d(as_FloatRegister($dst$$reg),
 6977               as_FloatRegister($src1$$reg),
 6978               as_FloatRegister($src2$$reg));
 6979   %}
 6980 
 6981   ins_pipe(fp_dop_reg_reg_d);
 6982 %}
 6983 
 6984 // src1 * src2 + src3
 6985 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 6986   predicate(UseFMA);
 6987   match(Set dst (FmaF src3 (Binary src1 src2)));
 6988 
 6989   ins_cost(FMUL_SINGLE_COST);
 6990   format %{ "fmadd.s  $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
 6991 
 6992   ins_encode %{
 6993     __ fmadd_s(as_FloatRegister($dst$$reg),
 6994                as_FloatRegister($src1$$reg),
 6995                as_FloatRegister($src2$$reg),
 6996                as_FloatRegister($src3$$reg));
 6997   %}
 6998 
 6999   ins_pipe(pipe_class_default);
 7000 %}
 7001 
 7002 // src1 * src2 + src3
 7003 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7004   predicate(UseFMA);
 7005   match(Set dst (FmaD src3 (Binary src1 src2)));
 7006 
 7007   ins_cost(FMUL_DOUBLE_COST);
 7008   format %{ "fmadd.d  $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
 7009 
 7010   ins_encode %{
 7011     __ fmadd_d(as_FloatRegister($dst$$reg),
 7012                as_FloatRegister($src1$$reg),
 7013                as_FloatRegister($src2$$reg),
 7014                as_FloatRegister($src3$$reg));
 7015   %}
 7016 
 7017   ins_pipe(pipe_class_default);
 7018 %}
 7019 
 7020 // src1 * src2 - src3
 7021 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7022   predicate(UseFMA);
 7023   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
 7024 
 7025   ins_cost(FMUL_SINGLE_COST);
 7026   format %{ "fmsub.s  $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
 7027 
 7028   ins_encode %{
 7029     __ fmsub_s(as_FloatRegister($dst$$reg),
 7030                as_FloatRegister($src1$$reg),
 7031                as_FloatRegister($src2$$reg),
 7032                as_FloatRegister($src3$$reg));
 7033   %}
 7034 
 7035   ins_pipe(pipe_class_default);
 7036 %}
 7037 
 7038 // src1 * src2 - src3
 7039 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7040   predicate(UseFMA);
 7041   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
 7042 
 7043   ins_cost(FMUL_DOUBLE_COST);
 7044   format %{ "fmsub.d  $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
 7045 
 7046   ins_encode %{
 7047     __ fmsub_d(as_FloatRegister($dst$$reg),
 7048                as_FloatRegister($src1$$reg),
 7049                as_FloatRegister($src2$$reg),
 7050                as_FloatRegister($src3$$reg));
 7051   %}
 7052 
 7053   ins_pipe(pipe_class_default);
 7054 %}
 7055 
 7056 // -src1 * src2 + src3
 7057 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7058   predicate(UseFMA);
 7059   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
 7060   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
 7061 
 7062   ins_cost(FMUL_SINGLE_COST);
 7063   format %{ "fnmsub.s  $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
 7064 
 7065   ins_encode %{
 7066     __ fnmsub_s(as_FloatRegister($dst$$reg),
 7067                 as_FloatRegister($src1$$reg),
 7068                 as_FloatRegister($src2$$reg),
 7069                 as_FloatRegister($src3$$reg));
 7070   %}
 7071 
 7072   ins_pipe(pipe_class_default);
 7073 %}
 7074 
 7075 // -src1 * src2 + src3
 7076 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7077   predicate(UseFMA);
 7078   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
 7079   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
 7080 
 7081   ins_cost(FMUL_DOUBLE_COST);
 7082   format %{ "fnmsub.d  $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
 7083 
 7084   ins_encode %{
 7085     __ fnmsub_d(as_FloatRegister($dst$$reg),
 7086                 as_FloatRegister($src1$$reg),
 7087                 as_FloatRegister($src2$$reg),
 7088                 as_FloatRegister($src3$$reg));
 7089   %}
 7090 
 7091   ins_pipe(pipe_class_default);
 7092 %}
 7093 
 7094 // -src1 * src2 - src3
 7095 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7096   predicate(UseFMA);
 7097   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
 7098   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
 7099 
 7100   ins_cost(FMUL_SINGLE_COST);
 7101   format %{ "fnmadd.s  $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
 7102 
 7103   ins_encode %{
 7104     __ fnmadd_s(as_FloatRegister($dst$$reg),
 7105                 as_FloatRegister($src1$$reg),
 7106                 as_FloatRegister($src2$$reg),
 7107                 as_FloatRegister($src3$$reg));
 7108   %}
 7109 
 7110   ins_pipe(pipe_class_default);
 7111 %}
 7112 
 7113 // -src1 * src2 - src3
 7114 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7115   predicate(UseFMA);
 7116   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
 7117   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
 7118 
 7119   ins_cost(FMUL_DOUBLE_COST);
 7120   format %{ "fnmadd.d  $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
 7121 
 7122   ins_encode %{
 7123     __ fnmadd_d(as_FloatRegister($dst$$reg),
 7124                 as_FloatRegister($src1$$reg),
 7125                 as_FloatRegister($src2$$reg),
 7126                 as_FloatRegister($src3$$reg));
 7127   %}
 7128 
 7129   ins_pipe(pipe_class_default);
 7130 %}
 7131 
 7132 // Math.max(FF)F
 7133 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7134   match(Set dst (MaxF src1 src2));
 7135   effect(TEMP_DEF dst);
 7136 
 7137   format %{ "maxF $dst, $src1, $src2" %}
 7138 
 7139   ins_encode %{
 7140     __ minmax_FD(as_FloatRegister($dst$$reg),
 7141                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7142                  false /* is_double */, false /* is_min */);
 7143   %}
 7144 
 7145   ins_pipe(fp_dop_reg_reg_s);
 7146 %}
 7147 
 7148 // Math.min(FF)F
 7149 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7150   match(Set dst (MinF src1 src2));
 7151   effect(TEMP_DEF dst);
 7152 
 7153   format %{ "minF $dst, $src1, $src2" %}
 7154 
 7155   ins_encode %{
 7156     __ minmax_FD(as_FloatRegister($dst$$reg),
 7157                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7158                  false /* is_double */, true /* is_min */);
 7159   %}
 7160 
 7161   ins_pipe(fp_dop_reg_reg_s);
 7162 %}
 7163 
 7164 // Math.max(DD)D
 7165 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7166   match(Set dst (MaxD src1 src2));
 7167   effect(TEMP_DEF dst);
 7168 
 7169   format %{ "maxD $dst, $src1, $src2" %}
 7170 
 7171   ins_encode %{
 7172     __ minmax_FD(as_FloatRegister($dst$$reg),
 7173                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7174                  true /* is_double */, false /* is_min */);
 7175   %}
 7176 
 7177   ins_pipe(fp_dop_reg_reg_d);
 7178 %}
 7179 
 7180 // Math.min(DD)D
 7181 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7182   match(Set dst (MinD src1 src2));
 7183   effect(TEMP_DEF dst);
 7184 
 7185   format %{ "minD $dst, $src1, $src2" %}
 7186 
 7187   ins_encode %{
 7188     __ minmax_FD(as_FloatRegister($dst$$reg),
 7189                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7190                  true /* is_double */, true /* is_min */);
 7191   %}
 7192 
 7193   ins_pipe(fp_dop_reg_reg_d);
 7194 %}
 7195 
 7196 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7197   match(Set dst (DivF src1  src2));
 7198 
 7199   ins_cost(FDIV_COST);
 7200   format %{ "fdiv.s  $dst, $src1, $src2\t#@divF_reg_reg" %}
 7201 
 7202   ins_encode %{
 7203     __ fdiv_s(as_FloatRegister($dst$$reg),
 7204               as_FloatRegister($src1$$reg),
 7205               as_FloatRegister($src2$$reg));
 7206   %}
 7207 
 7208   ins_pipe(fp_div_s);
 7209 %}
 7210 
 7211 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7212   match(Set dst (DivD src1  src2));
 7213 
 7214   ins_cost(FDIV_COST);
 7215   format %{ "fdiv.d  $dst, $src1, $src2\t#@divD_reg_reg" %}
 7216 
 7217   ins_encode %{
 7218     __ fdiv_d(as_FloatRegister($dst$$reg),
 7219               as_FloatRegister($src1$$reg),
 7220               as_FloatRegister($src2$$reg));
 7221   %}
 7222 
 7223   ins_pipe(fp_div_d);
 7224 %}
 7225 
 7226 instruct negF_reg_reg(fRegF dst, fRegF src) %{
 7227   match(Set dst (NegF src));
 7228 
 7229   ins_cost(XFER_COST);
 7230   format %{ "fsgnjn.s  $dst, $src, $src\t#@negF_reg_reg" %}
 7231 
 7232   ins_encode %{
 7233     __ fneg_s(as_FloatRegister($dst$$reg),
 7234               as_FloatRegister($src$$reg));
 7235   %}
 7236 
 7237   ins_pipe(fp_uop_s);
 7238 %}
 7239 
 7240 instruct negD_reg_reg(fRegD dst, fRegD src) %{
 7241   match(Set dst (NegD src));
 7242 
 7243   ins_cost(XFER_COST);
 7244   format %{ "fsgnjn.d  $dst, $src, $src\t#@negD_reg_reg" %}
 7245 
 7246   ins_encode %{
 7247     __ fneg_d(as_FloatRegister($dst$$reg),
 7248               as_FloatRegister($src$$reg));
 7249   %}
 7250 
 7251   ins_pipe(fp_uop_d);
 7252 %}
 7253 
 7254 instruct absF_reg(fRegF dst, fRegF src) %{
 7255   match(Set dst (AbsF src));
 7256 
 7257   ins_cost(XFER_COST);
 7258   format %{ "fsgnjx.s  $dst, $src, $src\t#@absF_reg" %}
 7259   ins_encode %{
 7260     __ fabs_s(as_FloatRegister($dst$$reg),
 7261               as_FloatRegister($src$$reg));
 7262   %}
 7263 
 7264   ins_pipe(fp_uop_s);
 7265 %}
 7266 
 7267 instruct absD_reg(fRegD dst, fRegD src) %{
 7268   match(Set dst (AbsD src));
 7269 
 7270   ins_cost(XFER_COST);
 7271   format %{ "fsgnjx.d  $dst, $src, $src\t#@absD_reg" %}
 7272   ins_encode %{
 7273     __ fabs_d(as_FloatRegister($dst$$reg),
 7274               as_FloatRegister($src$$reg));
 7275   %}
 7276 
 7277   ins_pipe(fp_uop_d);
 7278 %}
 7279 
 7280 instruct sqrtF_reg(fRegF dst, fRegF src) %{
 7281   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7282 
 7283   ins_cost(FSQRT_COST);
 7284   format %{ "fsqrt.s  $dst, $src\t#@sqrtF_reg" %}
 7285   ins_encode %{
 7286     __ fsqrt_s(as_FloatRegister($dst$$reg),
 7287                as_FloatRegister($src$$reg));
 7288   %}
 7289 
 7290   ins_pipe(fp_sqrt_s);
 7291 %}
 7292 
 7293 instruct sqrtD_reg(fRegD dst, fRegD src) %{
 7294   match(Set dst (SqrtD src));
 7295 
 7296   ins_cost(FSQRT_COST);
 7297   format %{ "fsqrt.d  $dst, $src\t#@sqrtD_reg" %}
 7298   ins_encode %{
 7299     __ fsqrt_d(as_FloatRegister($dst$$reg),
 7300                as_FloatRegister($src$$reg));
 7301   %}
 7302 
 7303   ins_pipe(fp_sqrt_d);
 7304 %}
 7305 
 7306 // Arithmetic Instructions End
 7307 
 7308 // ============================================================================
 7309 // Logical Instructions
 7310 
 7311 // Register And
 7312 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7313   match(Set dst (AndI src1 src2));
 7314 
 7315   format %{ "andr  $dst, $src1, $src2\t#@andI_reg_reg" %}
 7316 
 7317   ins_cost(ALU_COST);
 7318   ins_encode %{
 7319     __ andr(as_Register($dst$$reg),
 7320             as_Register($src1$$reg),
 7321             as_Register($src2$$reg));
 7322   %}
 7323 
 7324   ins_pipe(ialu_reg_reg);
 7325 %}
 7326 
 7327 // Immediate And
 7328 instruct andI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 7329   match(Set dst (AndI src1 src2));
 7330 
 7331   format %{ "andi  $dst, $src1, $src2\t#@andI_reg_imm" %}
 7332 
 7333   ins_cost(ALU_COST);
 7334   ins_encode %{
 7335     __ andi(as_Register($dst$$reg),
 7336             as_Register($src1$$reg),
 7337             (int32_t)($src2$$constant));
 7338   %}
 7339 
 7340   ins_pipe(ialu_reg_imm);
 7341 %}
 7342 
 7343 // Register Or
 7344 instruct orI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7345   match(Set dst (OrI src1 src2));
 7346 
 7347   format %{ "orr  $dst, $src1, $src2\t#@orI_reg_reg" %}
 7348 
 7349   ins_cost(ALU_COST);
 7350   ins_encode %{
 7351     __ orr(as_Register($dst$$reg),
 7352            as_Register($src1$$reg),
 7353            as_Register($src2$$reg));
 7354   %}
 7355 
 7356   ins_pipe(ialu_reg_reg);
 7357 %}
 7358 
 7359 // Immediate Or
 7360 instruct orI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 7361   match(Set dst (OrI src1 src2));
 7362 
 7363   format %{ "ori  $dst, $src1, $src2\t#@orI_reg_imm" %}
 7364 
 7365   ins_cost(ALU_COST);
 7366   ins_encode %{
 7367     __ ori(as_Register($dst$$reg),
 7368            as_Register($src1$$reg),
 7369            (int32_t)($src2$$constant));
 7370   %}
 7371 
 7372   ins_pipe(ialu_reg_imm);
 7373 %}
 7374 
 7375 // Register Xor
 7376 instruct xorI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 7377   match(Set dst (XorI src1 src2));
 7378 
 7379   format %{ "xorr  $dst, $src1, $src2\t#@xorI_reg_reg" %}
 7380 
 7381   ins_cost(ALU_COST);
 7382   ins_encode %{
 7383     __ xorr(as_Register($dst$$reg),
 7384             as_Register($src1$$reg),
 7385             as_Register($src2$$reg));
 7386   %}
 7387 
 7388   ins_pipe(ialu_reg_reg);
 7389 %}
 7390 
 7391 // Immediate Xor
 7392 instruct xorI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 7393   match(Set dst (XorI src1 src2));
 7394 
 7395   format %{ "xori  $dst, $src1, $src2\t#@xorI_reg_imm" %}
 7396 
 7397   ins_cost(ALU_COST);
 7398   ins_encode %{
 7399     __ xori(as_Register($dst$$reg),
 7400             as_Register($src1$$reg),
 7401             (int32_t)($src2$$constant));
 7402   %}
 7403 
 7404   ins_pipe(ialu_reg_imm);
 7405 %}
 7406 
 7407 // Register And Long
 7408 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7409   match(Set dst (AndL src1 src2));
 7410 
 7411   format %{ "andr  $dst, $src1, $src2\t#@andL_reg_reg" %}
 7412 
 7413   ins_cost(ALU_COST);
 7414   ins_encode %{
 7415     __ andr(as_Register($dst$$reg),
 7416             as_Register($src1$$reg),
 7417             as_Register($src2$$reg));
 7418   %}
 7419 
 7420   ins_pipe(ialu_reg_reg);
 7421 %}
 7422 
 7423 // Immediate And Long
 7424 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7425   match(Set dst (AndL src1 src2));
 7426 
 7427   format %{ "andi  $dst, $src1, $src2\t#@andL_reg_imm" %}
 7428 
 7429   ins_cost(ALU_COST);
 7430   ins_encode %{
 7431     __ andi(as_Register($dst$$reg),
 7432             as_Register($src1$$reg),
 7433             (int32_t)($src2$$constant));
 7434   %}
 7435 
 7436   ins_pipe(ialu_reg_imm);
 7437 %}
 7438 
 7439 // Register Or Long
 7440 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7441   match(Set dst (OrL src1 src2));
 7442 
 7443   format %{ "orr  $dst, $src1, $src2\t#@orL_reg_reg" %}
 7444 
 7445   ins_cost(ALU_COST);
 7446   ins_encode %{
 7447     __ orr(as_Register($dst$$reg),
 7448            as_Register($src1$$reg),
 7449            as_Register($src2$$reg));
 7450   %}
 7451 
 7452   ins_pipe(ialu_reg_reg);
 7453 %}
 7454 
 7455 // Immediate Or Long
 7456 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7457   match(Set dst (OrL src1 src2));
 7458 
 7459   format %{ "ori  $dst, $src1, $src2\t#@orL_reg_imm" %}
 7460 
 7461   ins_cost(ALU_COST);
 7462   ins_encode %{
 7463     __ ori(as_Register($dst$$reg),
 7464            as_Register($src1$$reg),
 7465            (int32_t)($src2$$constant));
 7466   %}
 7467 
 7468   ins_pipe(ialu_reg_imm);
 7469 %}
 7470 
 7471 // Register Xor Long
 7472 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7473   match(Set dst (XorL src1 src2));
 7474 
 7475   format %{ "xorr  $dst, $src1, $src2\t#@xorL_reg_reg" %}
 7476 
 7477   ins_cost(ALU_COST);
 7478   ins_encode %{
 7479     __ xorr(as_Register($dst$$reg),
 7480             as_Register($src1$$reg),
 7481             as_Register($src2$$reg));
 7482   %}
 7483 
 7484   ins_pipe(ialu_reg_reg);
 7485 %}
 7486 
 7487 // Immediate Xor Long
 7488 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7489   match(Set dst (XorL src1 src2));
 7490 
 7491   ins_cost(ALU_COST);
 7492   format %{ "xori  $dst, $src1, $src2\t#@xorL_reg_imm" %}
 7493 
 7494   ins_encode %{
 7495     __ xori(as_Register($dst$$reg),
 7496             as_Register($src1$$reg),
 7497             (int32_t)($src2$$constant));
 7498   %}
 7499 
 7500   ins_pipe(ialu_reg_imm);
 7501 %}
 7502 
 7503 // ============================================================================
 7504 // BSWAP Instructions
 7505 
 7506 instruct bytes_reverse_int(iRegL_R6 cr, iRegINoSp dst, iRegIorL2I src) %{
 7507   match(Set dst (ReverseBytesI src));
 7508   effect(TEMP cr);
 7509 
 7510   ins_cost(ALU_COST * 17);
 7511   format %{ "grevw  $dst, $src\t#@bytes_reverse_int" %}
 7512 
 7513   ins_encode %{
 7514     __ grevw(as_Register($dst$$reg), as_Register($src$$reg));
 7515   %}
 7516 
 7517   ins_pipe(ialu_reg);
 7518 %}
 7519 
 7520 instruct bytes_reverse_long(iRegL_R6 cr, iRegLNoSp dst, iRegL src) %{
 7521   match(Set dst (ReverseBytesL src));
 7522   effect(TEMP cr);
 7523 
 7524   ins_cost(ALU_COST * 45);
 7525   format %{ "grev  $dst, $src\t#@bytes_reverse_long" %}
 7526 
 7527   ins_encode %{
 7528     __ grev(as_Register($dst$$reg), as_Register($src$$reg));
 7529   %}
 7530 
 7531   ins_pipe(ialu_reg);
 7532 %}
 7533 
 7534 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
 7535   match(Set dst (ReverseBytesUS src));
 7536 
 7537   ins_cost(ALU_COST * 5);
 7538   format %{ "grevhu  $dst, $src\t#@bytes_reverse_unsigned_short" %}
 7539 
 7540   ins_encode %{
 7541     __ grevhu(as_Register($dst$$reg), as_Register($src$$reg));
 7542   %}
 7543 
 7544   ins_pipe(ialu_reg);
 7545 %}
 7546 
 7547 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
 7548   match(Set dst (ReverseBytesS src));
 7549 
 7550   ins_cost(ALU_COST * 5);
 7551   format %{ "grevh  $dst, $src\t#@bytes_reverse_short" %}
 7552 
 7553   ins_encode %{
 7554     __ grevh(as_Register($dst$$reg), as_Register($src$$reg));
 7555   %}
 7556 
 7557   ins_pipe(ialu_reg);
 7558 %}
 7559 
 7560 // ============================================================================
 7561 // MemBar Instruction
 7562 
 7563 instruct load_fence() %{
 7564   match(LoadFence);
 7565   ins_cost(ALU_COST);
 7566 
 7567   format %{ "#@load_fence" %}
 7568 
 7569   ins_encode %{
 7570     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7571   %}
 7572   ins_pipe(pipe_serial);
 7573 %}
 7574 
 7575 instruct membar_acquire() %{
 7576   match(MemBarAcquire);
 7577   ins_cost(ALU_COST);
 7578 
 7579   format %{ "#@membar_acquire\n\t"
 7580             "fence ir iorw" %}
 7581 
 7582   ins_encode %{
 7583     __ block_comment("membar_acquire");
 7584     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7585   %}
 7586 
 7587   ins_pipe(pipe_serial);
 7588 %}
 7589 
 7590 instruct membar_acquire_lock() %{
 7591   match(MemBarAcquireLock);
 7592   ins_cost(0);
 7593 
 7594   format %{ "#@membar_acquire_lock (elided)" %}
 7595 
 7596   ins_encode %{
 7597     __ block_comment("membar_acquire_lock (elided)");
 7598   %}
 7599 
 7600   ins_pipe(pipe_serial);
 7601 %}
 7602 
 7603 instruct store_fence() %{
 7604   match(StoreFence);
 7605   ins_cost(ALU_COST);
 7606 
 7607   format %{ "#@store_fence" %}
 7608 
 7609   ins_encode %{
 7610     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7611   %}
 7612   ins_pipe(pipe_serial);
 7613 %}
 7614 
 7615 instruct membar_release() %{
 7616   match(MemBarRelease);
 7617   ins_cost(ALU_COST);
 7618 
 7619   format %{ "#@membar_release\n\t"
 7620             "fence iorw ow" %}
 7621 
 7622   ins_encode %{
 7623     __ block_comment("membar_release");
 7624     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7625   %}
 7626   ins_pipe(pipe_serial);
 7627 %}
 7628 
 7629 instruct membar_storestore() %{
 7630   match(MemBarStoreStore);
 7631   ins_cost(ALU_COST);
 7632 
 7633   format %{ "MEMBAR-store-store\t#@membar_storestore" %}
 7634 
 7635   ins_encode %{
 7636     __ membar(MacroAssembler::StoreStore);
 7637   %}
 7638   ins_pipe(pipe_serial);
 7639 %}
 7640 
 7641 instruct membar_release_lock() %{
 7642   match(MemBarReleaseLock);
 7643   ins_cost(0);
 7644 
 7645   format %{ "#@membar_release_lock (elided)" %}
 7646 
 7647   ins_encode %{
 7648     __ block_comment("membar_release_lock (elided)");
 7649   %}
 7650 
 7651   ins_pipe(pipe_serial);
 7652 %}
 7653 
 7654 instruct membar_volatile() %{
 7655   match(MemBarVolatile);
 7656   ins_cost(ALU_COST);
 7657 
 7658   format %{ "#@membar_volatile\n\t"
 7659              "fence iorw iorw"%}
 7660 
 7661   ins_encode %{
 7662     __ block_comment("membar_volatile");
 7663     __ membar(MacroAssembler::StoreLoad);
 7664   %}
 7665 
 7666   ins_pipe(pipe_serial);
 7667 %}
 7668 
 7669 // ============================================================================
 7670 // Cast Instructions (Java-level type cast)
 7671 
 7672 instruct castX2P(iRegPNoSp dst, iRegL src) %{
 7673   match(Set dst (CastX2P src));
 7674 
 7675   ins_cost(ALU_COST);
 7676   format %{ "mv  $dst, $src\t# long -> ptr, #@castX2P" %}
 7677 
 7678   ins_encode %{
 7679     if ($dst$$reg != $src$$reg) {
 7680       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7681     }
 7682   %}
 7683 
 7684   ins_pipe(ialu_reg);
 7685 %}
 7686 
 7687 instruct castP2X(iRegLNoSp dst, iRegP src) %{
 7688   match(Set dst (CastP2X src));
 7689 
 7690   ins_cost(ALU_COST);
 7691   format %{ "mv  $dst, $src\t# ptr -> long, #@castP2X" %}
 7692 
 7693   ins_encode %{
 7694     if ($dst$$reg != $src$$reg) {
 7695       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7696     }
 7697   %}
 7698 
 7699   ins_pipe(ialu_reg);
 7700 %}
 7701 
 7702 instruct castPP(iRegPNoSp dst)
 7703 %{
 7704   match(Set dst (CastPP dst));
 7705   ins_cost(0);
 7706 
 7707   size(0);
 7708   format %{ "# castPP of $dst, #@castPP" %}
 7709   ins_encode(/* empty encoding */);
 7710   ins_pipe(pipe_class_empty);
 7711 %}
 7712 
 7713 instruct castLL(iRegL dst)
 7714 %{
 7715   match(Set dst (CastLL dst));
 7716 
 7717   size(0);
 7718   format %{ "# castLL of $dst, #@castLL" %}
 7719   ins_encode(/* empty encoding */);
 7720   ins_cost(0);
 7721   ins_pipe(pipe_class_empty);
 7722 %}
 7723 
 7724 instruct castII(iRegI dst)
 7725 %{
 7726   match(Set dst (CastII dst));
 7727 
 7728   size(0);
 7729   format %{ "# castII of $dst, #@castII" %}
 7730   ins_encode(/* empty encoding */);
 7731   ins_cost(0);
 7732   ins_pipe(pipe_class_empty);
 7733 %}
 7734 
 7735 instruct checkCastPP(iRegPNoSp dst)
 7736 %{
 7737   match(Set dst (CheckCastPP dst));
 7738 
 7739   size(0);
 7740   ins_cost(0);
 7741   format %{ "# checkcastPP of $dst, #@checkCastPP" %}
 7742   ins_encode(/* empty encoding */);
 7743   ins_pipe(pipe_class_empty);
 7744 %}
 7745 
 7746 instruct castFF(fRegF dst)
 7747 %{
 7748   match(Set dst (CastFF dst));
 7749 
 7750   size(0);
 7751   format %{ "# castFF of $dst" %}
 7752   ins_encode(/* empty encoding */);
 7753   ins_cost(0);
 7754   ins_pipe(pipe_class_empty);
 7755 %}
 7756 
 7757 instruct castDD(fRegD dst)
 7758 %{
 7759   match(Set dst (CastDD dst));
 7760 
 7761   size(0);
 7762   format %{ "# castDD of $dst" %}
 7763   ins_encode(/* empty encoding */);
 7764   ins_cost(0);
 7765   ins_pipe(pipe_class_empty);
 7766 %}
 7767 
 7768 instruct castVV(vReg dst)
 7769 %{
 7770   match(Set dst (CastVV dst));
 7771 
 7772   size(0);
 7773   format %{ "# castVV of $dst" %}
 7774   ins_encode(/* empty encoding */);
 7775   ins_cost(0);
 7776   ins_pipe(pipe_class_empty);
 7777 %}
 7778 
 7779 // ============================================================================
 7780 // Convert Instructions
 7781 
 7782 // int to bool
 7783 instruct convI2Bool(iRegINoSp dst, iRegIorL2I src)
 7784 %{
 7785   match(Set dst (Conv2B src));
 7786 
 7787   ins_cost(ALU_COST);
 7788   format %{ "snez  $dst, $src\t#@convI2Bool" %}
 7789 
 7790   ins_encode %{
 7791     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 7792   %}
 7793 
 7794   ins_pipe(ialu_reg);
 7795 %}
 7796 
 7797 // pointer to bool
 7798 instruct convP2Bool(iRegINoSp dst, iRegP src)
 7799 %{
 7800   match(Set dst (Conv2B src));
 7801 
 7802   ins_cost(ALU_COST);
 7803   format %{ "snez  $dst, $src\t#@convP2Bool" %}
 7804 
 7805   ins_encode %{
 7806     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 7807   %}
 7808 
 7809   ins_pipe(ialu_reg);
 7810 %}
 7811 
 7812 // int <-> long
 7813 
 7814 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
 7815 %{
 7816   match(Set dst (ConvI2L src));
 7817 
 7818   ins_cost(ALU_COST);
 7819   format %{ "addw  $dst, $src\t#@convI2L_reg_reg" %}
 7820   ins_encode %{
 7821     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 7822   %}
 7823   ins_pipe(ialu_reg);
 7824 %}
 7825 
 7826 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
 7827   match(Set dst (ConvL2I src));
 7828 
 7829   ins_cost(ALU_COST);
 7830   format %{ "addw  $dst, $src, zr\t#@convL2I_reg" %}
 7831 
 7832   ins_encode %{
 7833     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 7834   %}
 7835 
 7836   ins_pipe(ialu_reg);
 7837 %}
 7838 
 7839 // unsigned int to long (Zero-extend)
 7840 // this pattern occurs in bigmath arithmetic
 7841 instruct convUI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
 7842 %{
 7843   match(Set dst (AndL (ConvI2L src) mask));
 7844 
 7845   ins_cost(ALU_COST * 2);
 7846   format %{ "slli  $dst, $src, 32\t# ui2l\n\t"
 7847             "srli  $dst, $dst, 32\t# ui2l, #@convUI2L_reg_reg" %}
 7848 
 7849   ins_encode %{
 7850     __ zero_ext(as_Register($dst$$reg), as_Register($src$$reg), 32);
 7851   %}
 7852 
 7853   ins_pipe(ialu_reg_shift);
 7854 %}
 7855 
 7856 // float <-> double
 7857 
 7858 instruct convF2D_reg(fRegD dst, fRegF src) %{
 7859   match(Set dst (ConvF2D src));
 7860 
 7861   ins_cost(XFER_COST);
 7862   format %{ "fcvt.d.s  $dst, $src\t#@convF2D_reg" %}
 7863 
 7864   ins_encode %{
 7865     __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 7866   %}
 7867 
 7868   ins_pipe(fp_f2d);
 7869 %}
 7870 
 7871 instruct convD2F_reg(fRegF dst, fRegD src) %{
 7872   match(Set dst (ConvD2F src));
 7873 
 7874   ins_cost(XFER_COST);
 7875   format %{ "fcvt.s.d  $dst, $src\t#@convD2F_reg" %}
 7876 
 7877   ins_encode %{
 7878     __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 7879   %}
 7880 
 7881   ins_pipe(fp_d2f);
 7882 %}
 7883 
 7884 // float <-> int
 7885 
 7886 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 7887   match(Set dst (ConvF2I src));
 7888 
 7889   ins_cost(XFER_COST);
 7890   format %{ "fcvt.w.s  $dst, $src\t#@convF2I_reg_reg" %}
 7891 
 7892   ins_encode %{
 7893     __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
 7894   %}
 7895 
 7896   ins_pipe(fp_f2i);
 7897 %}
 7898 
 7899 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
 7900   match(Set dst (ConvI2F src));
 7901 
 7902   ins_cost(XFER_COST);
 7903   format %{ "fcvt.s.w  $dst, $src\t#@convI2F_reg_reg" %}
 7904 
 7905   ins_encode %{
 7906     __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 7907   %}
 7908 
 7909   ins_pipe(fp_i2f);
 7910 %}
 7911 
 7912 // float <-> long
 7913 
 7914 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
 7915   match(Set dst (ConvF2L src));
 7916 
 7917   ins_cost(XFER_COST);
 7918   format %{ "fcvt.l.s  $dst, $src\t#@convF2L_reg_reg" %}
 7919 
 7920   ins_encode %{
 7921     __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
 7922   %}
 7923 
 7924   ins_pipe(fp_f2l);
 7925 %}
 7926 
 7927 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
 7928   match(Set dst (ConvL2F src));
 7929 
 7930   ins_cost(XFER_COST);
 7931   format %{ "fcvt.s.l  $dst, $src\t#@convL2F_reg_reg" %}
 7932 
 7933   ins_encode %{
 7934     __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 7935   %}
 7936 
 7937   ins_pipe(fp_l2f);
 7938 %}
 7939 
 7940 // double <-> int
 7941 
 7942 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
 7943   match(Set dst (ConvD2I src));
 7944 
 7945   ins_cost(XFER_COST);
 7946   format %{ "fcvt.w.d  $dst, $src\t#@convD2I_reg_reg" %}
 7947 
 7948   ins_encode %{
 7949     __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
 7950   %}
 7951 
 7952   ins_pipe(fp_d2i);
 7953 %}
 7954 
 7955 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
 7956   match(Set dst (ConvI2D src));
 7957 
 7958   ins_cost(XFER_COST);
 7959   format %{ "fcvt.d.w  $dst, $src\t#@convI2D_reg_reg" %}
 7960 
 7961   ins_encode %{
 7962     __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 7963   %}
 7964 
 7965   ins_pipe(fp_i2d);
 7966 %}
 7967 
 7968 // double <-> long
 7969 
 7970 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 7971   match(Set dst (ConvD2L src));
 7972 
 7973   ins_cost(XFER_COST);
 7974   format %{ "fcvt.l.d  $dst, $src\t#@convD2L_reg_reg" %}
 7975 
 7976   ins_encode %{
 7977     __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
 7978   %}
 7979 
 7980   ins_pipe(fp_d2l);
 7981 %}
 7982 
 7983 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
 7984   match(Set dst (ConvL2D src));
 7985 
 7986   ins_cost(XFER_COST);
 7987   format %{ "fcvt.d.l  $dst, $src\t#@convL2D_reg_reg" %}
 7988 
 7989   ins_encode %{
 7990     __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 7991   %}
 7992 
 7993   ins_pipe(fp_l2d);
 7994 %}
 7995 
 7996 // Convert oop into int for vectors alignment masking
 7997 instruct convP2I(iRegINoSp dst, iRegP src) %{
 7998   match(Set dst (ConvL2I (CastP2X src)));
 7999 
 8000   ins_cost(ALU_COST);
 8001   format %{ "mv  $dst,  $src\t# ptr -> int\n\t"
 8002             "slli $dst, $dst, 32\n\t"
 8003             "srli $dst, $dst, 32\t#@convP2I"
 8004   %}
 8005 
 8006   ins_encode %{
 8007     __ mv($dst$$Register, $src$$Register);
 8008     __ clear_upper_bits($dst$$Register, 32);
 8009   %}
 8010 
 8011   ins_pipe(ialu_reg);
 8012 %}
 8013 
 8014 // Convert compressed oop into int for vectors alignment masking
 8015 // in case of 32bit oops (heap < 4Gb).
 8016 instruct convN2I(iRegINoSp dst, iRegN src)
 8017 %{
 8018   predicate(CompressedOops::shift() == 0);
 8019   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 8020 
 8021   ins_cost(ALU_COST);
 8022   format %{ "mv  $dst, $src\t# compressed ptr -> int, #@convN2I" %}
 8023 
 8024   ins_encode %{
 8025     __ mv($dst$$Register, $src$$Register);
 8026   %}
 8027 
 8028   ins_pipe(ialu_reg);
 8029 %}
 8030 
 8031 // Convert oop pointer into compressed form
 8032 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
 8033   match(Set dst (EncodeP src));
 8034   ins_cost(ALU_COST);
 8035   format %{ "encode_heap_oop  $dst, $src\t#@encodeHeapOop" %}
 8036   ins_encode %{
 8037     Register s = $src$$Register;
 8038     Register d = $dst$$Register;
 8039     __ encode_heap_oop(d, s);
 8040   %}
 8041   ins_pipe(ialu_reg);
 8042 %}
 8043 
 8044 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
 8045   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 8046             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 8047   match(Set dst (DecodeN src));
 8048 
 8049   ins_cost(0);
 8050   format %{ "decode_heap_oop  $dst, $src\t#@decodeHeapOop" %}
 8051   ins_encode %{
 8052     Register s = $src$$Register;
 8053     Register d = $dst$$Register;
 8054     __ decode_heap_oop(d, s);
 8055   %}
 8056   ins_pipe(ialu_reg);
 8057 %}
 8058 
 8059 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
 8060   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 8061             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 8062   match(Set dst (DecodeN src));
 8063 
 8064   ins_cost(0);
 8065   format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
 8066   ins_encode %{
 8067     Register s = $src$$Register;
 8068     Register d = $dst$$Register;
 8069     __ decode_heap_oop_not_null(d, s);
 8070   %}
 8071   ins_pipe(ialu_reg);
 8072 %}
 8073 
 8074 // Convert klass pointer into compressed form.
 8075 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
 8076   match(Set dst (EncodePKlass src));
 8077 
 8078   ins_cost(ALU_COST);
 8079   format %{ "encode_klass_not_null  $dst, $src\t#@encodeKlass_not_null" %}
 8080 
 8081   ins_encode %{
 8082     Register src_reg = as_Register($src$$reg);
 8083     Register dst_reg = as_Register($dst$$reg);
 8084     __ encode_klass_not_null(dst_reg, src_reg, t0);
 8085   %}
 8086 
 8087    ins_pipe(ialu_reg);
 8088 %}
 8089 
 8090 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src) %{
 8091   predicate(!maybe_use_tmp_register_decoding_klass());
 8092 
 8093   match(Set dst (DecodeNKlass src));
 8094 
 8095   ins_cost(ALU_COST);
 8096   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
 8097 
 8098   ins_encode %{
 8099     Register src_reg = as_Register($src$$reg);
 8100     Register dst_reg = as_Register($dst$$reg);
 8101     __ decode_klass_not_null(dst_reg, src_reg, UseCompressedOops ? xheapbase : t0);
 8102   %}
 8103 
 8104    ins_pipe(ialu_reg);
 8105 %}
 8106 
 8107 instruct decodeKlass_not_null_with_tmp(iRegPNoSp dst, iRegN src, iRegL_R6 tmp) %{
 8108   predicate(maybe_use_tmp_register_decoding_klass());
 8109 
 8110   match(Set dst (DecodeNKlass src));
 8111 
 8112   effect(TEMP tmp);
 8113 
 8114   ins_cost(ALU_COST);
 8115   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
 8116 
 8117   ins_encode %{
 8118     Register src_reg = as_Register($src$$reg);
 8119     Register dst_reg = as_Register($dst$$reg);
 8120     Register tmp_reg = as_Register($tmp$$reg);
 8121     __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
 8122   %}
 8123 
 8124    ins_pipe(ialu_reg);
 8125 %}
 8126 
 8127 // stack <-> reg and reg <-> reg shuffles with no conversion
 8128 
 8129 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
 8130 
 8131   match(Set dst (MoveF2I src));
 8132 
 8133   effect(DEF dst, USE src);
 8134 
 8135   ins_cost(LOAD_COST);
 8136 
 8137   format %{ "lw  $dst, $src\t#@MoveF2I_stack_reg" %}
 8138 
 8139   ins_encode %{
 8140     __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
 8141   %}
 8142 
 8143   ins_pipe(iload_reg_reg);
 8144 
 8145 %}
 8146 
 8147 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
 8148 
 8149   match(Set dst (MoveI2F src));
 8150 
 8151   effect(DEF dst, USE src);
 8152 
 8153   ins_cost(LOAD_COST);
 8154 
 8155   format %{ "flw  $dst, $src\t#@MoveI2F_stack_reg" %}
 8156 
 8157   ins_encode %{
 8158     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8159   %}
 8160 
 8161   ins_pipe(pipe_class_memory);
 8162 
 8163 %}
 8164 
 8165 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
 8166 
 8167   match(Set dst (MoveD2L src));
 8168 
 8169   effect(DEF dst, USE src);
 8170 
 8171   ins_cost(LOAD_COST);
 8172 
 8173   format %{ "ld  $dst, $src\t#@MoveD2L_stack_reg" %}
 8174 
 8175   ins_encode %{
 8176     __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
 8177   %}
 8178 
 8179   ins_pipe(iload_reg_reg);
 8180 
 8181 %}
 8182 
 8183 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
 8184 
 8185   match(Set dst (MoveL2D src));
 8186 
 8187   effect(DEF dst, USE src);
 8188 
 8189   ins_cost(LOAD_COST);
 8190 
 8191   format %{ "fld  $dst, $src\t#@MoveL2D_stack_reg" %}
 8192 
 8193   ins_encode %{
 8194     __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8195   %}
 8196 
 8197   ins_pipe(pipe_class_memory);
 8198 
 8199 %}
 8200 
 8201 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
 8202 
 8203   match(Set dst (MoveF2I src));
 8204 
 8205   effect(DEF dst, USE src);
 8206 
 8207   ins_cost(STORE_COST);
 8208 
 8209   format %{ "fsw  $src, $dst\t#@MoveF2I_reg_stack" %}
 8210 
 8211   ins_encode %{
 8212     __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8213   %}
 8214 
 8215   ins_pipe(pipe_class_memory);
 8216 
 8217 %}
 8218 
 8219 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 8220 
 8221   match(Set dst (MoveI2F src));
 8222 
 8223   effect(DEF dst, USE src);
 8224 
 8225   ins_cost(STORE_COST);
 8226 
 8227   format %{ "sw  $src, $dst\t#@MoveI2F_reg_stack" %}
 8228 
 8229   ins_encode %{
 8230     __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
 8231   %}
 8232 
 8233   ins_pipe(istore_reg_reg);
 8234 
 8235 %}
 8236 
 8237 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
 8238 
 8239   match(Set dst (MoveD2L src));
 8240 
 8241   effect(DEF dst, USE src);
 8242 
 8243   ins_cost(STORE_COST);
 8244 
 8245   format %{ "fsd  $dst, $src\t#@MoveD2L_reg_stack" %}
 8246 
 8247   ins_encode %{
 8248     __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8249   %}
 8250 
 8251   ins_pipe(pipe_class_memory);
 8252 
 8253 %}
 8254 
 8255 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 8256 
 8257   match(Set dst (MoveL2D src));
 8258 
 8259   effect(DEF dst, USE src);
 8260 
 8261   ins_cost(STORE_COST);
 8262 
 8263   format %{ "sd  $src, $dst\t#@MoveL2D_reg_stack" %}
 8264 
 8265   ins_encode %{
 8266     __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
 8267   %}
 8268 
 8269   ins_pipe(istore_reg_reg);
 8270 
 8271 %}
 8272 
 8273 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8274 
 8275   match(Set dst (MoveF2I src));
 8276 
 8277   effect(DEF dst, USE src);
 8278 
 8279   ins_cost(XFER_COST);
 8280 
 8281   format %{ "fmv.x.w  $dst, $src\t#@MoveL2D_reg_stack" %}
 8282 
 8283   ins_encode %{
 8284     __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8285   %}
 8286 
 8287   ins_pipe(fp_f2i);
 8288 
 8289 %}
 8290 
 8291 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
 8292 
 8293   match(Set dst (MoveI2F src));
 8294 
 8295   effect(DEF dst, USE src);
 8296 
 8297   ins_cost(XFER_COST);
 8298 
 8299   format %{ "fmv.w.x  $dst, $src\t#@MoveI2F_reg_reg" %}
 8300 
 8301   ins_encode %{
 8302     __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8303   %}
 8304 
 8305   ins_pipe(fp_i2f);
 8306 
 8307 %}
 8308 
 8309 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8310 
 8311   match(Set dst (MoveD2L src));
 8312 
 8313   effect(DEF dst, USE src);
 8314 
 8315   ins_cost(XFER_COST);
 8316 
 8317   format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
 8318 
 8319   ins_encode %{
 8320     __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8321   %}
 8322 
 8323   ins_pipe(fp_d2l);
 8324 
 8325 %}
 8326 
 8327 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
 8328 
 8329   match(Set dst (MoveL2D src));
 8330 
 8331   effect(DEF dst, USE src);
 8332 
 8333   ins_cost(XFER_COST);
 8334 
 8335   format %{ "fmv.d.x  $dst, $src\t#@MoveD2L_reg_reg" %}
 8336 
 8337   ins_encode %{
 8338     __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8339   %}
 8340 
 8341   ins_pipe(fp_l2d);
 8342 %}
 8343 
 8344 // ============================================================================
 8345 // Compare Instructions which set the result float comparisons in dest register.
 8346 
 8347 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
 8348 %{
 8349   match(Set dst (CmpF3 op1 op2));
 8350 
 8351   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8352   format %{ "flt.s  $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
 8353             "bgtz   $dst, done\n\t"
 8354             "feq.s  $dst, $op1, $op2\n\t"
 8355             "addi   $dst, $dst, -1\t#@cmpF3_reg_reg"
 8356   %}
 8357 
 8358   ins_encode %{
 8359     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8360     __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
 8361                      as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8362   %}
 8363 
 8364   ins_pipe(pipe_class_default);
 8365 %}
 8366 
 8367 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
 8368 %{
 8369   match(Set dst (CmpD3 op1 op2));
 8370 
 8371   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8372   format %{ "flt.d  $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
 8373             "bgtz   $dst, done\n\t"
 8374             "feq.d  $dst, $op1, $op2\n\t"
 8375             "addi   $dst, $dst, -1\t#@cmpD3_reg_reg"
 8376   %}
 8377 
 8378   ins_encode %{
 8379     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8380     __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8381   %}
 8382 
 8383   ins_pipe(pipe_class_default);
 8384 %}
 8385 
 8386 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
 8387 %{
 8388   match(Set dst (CmpL3 op1 op2));
 8389 
 8390   ins_cost(ALU_COST * 3 + BRANCH_COST);
 8391   format %{ "slt   $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
 8392             "bnez  $dst, done\n\t"
 8393             "slt  $dst, $op1, $op2\n\t"
 8394             "neg   $dst, $dst\t#@cmpL3_reg_reg"
 8395   %}
 8396   ins_encode %{
 8397     __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 8398     __ mv(as_Register($dst$$reg), t0);
 8399   %}
 8400 
 8401   ins_pipe(pipe_class_default);
 8402 %}
 8403 
 8404 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q)
 8405 %{
 8406   match(Set dst (CmpLTMask p q));
 8407 
 8408   ins_cost(2 * ALU_COST);
 8409 
 8410   format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
 8411             "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
 8412   %}
 8413 
 8414   ins_encode %{
 8415     __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
 8416     __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 8417   %}
 8418 
 8419   ins_pipe(ialu_reg_reg);
 8420 %}
 8421 
 8422 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
 8423 %{
 8424   match(Set dst (CmpLTMask op zero));
 8425 
 8426   ins_cost(ALU_COST);
 8427 
 8428   format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
 8429 
 8430   ins_encode %{
 8431     __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
 8432   %}
 8433 
 8434   ins_pipe(ialu_reg_shift);
 8435 %}
 8436 
 8437 
 8438 // ============================================================================
 8439 // Max and Min
 8440 
 8441 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8442 %{
 8443   match(Set dst (MinI src1 src2));
 8444 
 8445   effect(DEF dst, USE src1, USE src2);
 8446 
 8447   ins_cost(BRANCH_COST + ALU_COST * 2);
 8448   format %{
 8449     "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
 8450     "mv $dst, $src2\n\t"
 8451     "j Ldone\n\t"
 8452     "bind Lsrc1\n\t"
 8453     "mv $dst, $src1\n\t"
 8454     "bind\t#@minI_rReg"
 8455   %}
 8456 
 8457   ins_encode %{
 8458     Label Lsrc1, Ldone;
 8459     __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8460     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8461     __ j(Ldone);
 8462     __ bind(Lsrc1);
 8463     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8464     __ bind(Ldone);
 8465   %}
 8466 
 8467   ins_pipe(ialu_reg_reg);
 8468 %}
 8469 
 8470 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8471 %{
 8472   match(Set dst (MaxI src1 src2));
 8473 
 8474   effect(DEF dst, USE src1, USE src2);
 8475 
 8476   ins_cost(BRANCH_COST + ALU_COST * 2);
 8477   format %{
 8478     "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
 8479     "mv $dst, $src2\n\t"
 8480     "j Ldone\n\t"
 8481     "bind Lsrc1\n\t"
 8482     "mv $dst, $src1\n\t"
 8483     "bind\t#@maxI_rReg"
 8484   %}
 8485 
 8486   ins_encode %{
 8487     Label Lsrc1, Ldone;
 8488     __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8489     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8490     __ j(Ldone);
 8491     __ bind(Lsrc1);
 8492     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8493     __ bind(Ldone);
 8494 
 8495   %}
 8496 
 8497   ins_pipe(ialu_reg_reg);
 8498 %}
 8499 
 8500 // ============================================================================
 8501 // Branch Instructions
 8502 // Direct Branch.
 8503 instruct branch(label lbl)
 8504 %{
 8505   match(Goto);
 8506 
 8507   effect(USE lbl);
 8508 
 8509   ins_cost(BRANCH_COST);
 8510   format %{ "j  $lbl\t#@branch" %}
 8511 
 8512   ins_encode(riscv64_enc_j(lbl));
 8513 
 8514   ins_pipe(pipe_branch);
 8515 %}
 8516 
 8517 // ============================================================================
 8518 // Compare and Branch Instructions
 8519 
 8520 // Patterns for short (< 12KiB) variants
 8521 
 8522 // Compare flags and branch near instructions.
 8523 instruct cmpFlag_branch(cmpOpEqNe cmp, iRegI_R6 cr, label lbl) %{
 8524   match(If cmp cr);
 8525   effect(USE lbl);
 8526 
 8527   ins_cost(BRANCH_COST);
 8528   format %{ "b$cmp  $cr, zr, $lbl\t#@cmpFlag_branch" %}
 8529 
 8530   ins_encode %{
 8531     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
 8532   %}
 8533   ins_pipe(pipe_cmpz_branch);
 8534   ins_short_branch(1);
 8535 %}
 8536 
 8537 // Compare signed int and branch near instructions
 8538 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8539 %{
 8540   // Same match rule as `far_cmpI_branch'.
 8541   match(If cmp (CmpI op1 op2));
 8542 
 8543   effect(USE lbl);
 8544 
 8545   ins_cost(BRANCH_COST);
 8546 
 8547   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_branch" %}
 8548 
 8549   ins_encode %{
 8550     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8551   %}
 8552 
 8553   ins_pipe(pipe_cmp_branch);
 8554   ins_short_branch(1);
 8555 %}
 8556 
 8557 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8558 %{
 8559   // Same match rule as `far_cmpI_loop'.
 8560   match(CountedLoopEnd cmp (CmpI op1 op2));
 8561 
 8562   effect(USE lbl);
 8563 
 8564   ins_cost(BRANCH_COST);
 8565 
 8566   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_loop" %}
 8567 
 8568   ins_encode %{
 8569     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8570   %}
 8571 
 8572   ins_pipe(pipe_cmp_branch);
 8573   ins_short_branch(1);
 8574 %}
 8575 
 8576 // Compare unsigned int and branch near instructions
 8577 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8578 %{
 8579   // Same match rule as `far_cmpU_branch'.
 8580   match(If cmp (CmpU op1 op2));
 8581 
 8582   effect(USE lbl);
 8583 
 8584   ins_cost(BRANCH_COST);
 8585 
 8586   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_branch" %}
 8587 
 8588   ins_encode %{
 8589     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8590                   as_Register($op2$$reg), *($lbl$$label));
 8591   %}
 8592 
 8593   ins_pipe(pipe_cmp_branch);
 8594   ins_short_branch(1);
 8595 %}
 8596 
 8597 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8598 %{
 8599   // Same match rule as `far_cmpU_loop'.
 8600   match(CountedLoopEnd cmp (CmpU op1 op2));
 8601 
 8602   effect(USE lbl);
 8603 
 8604   ins_cost(BRANCH_COST);
 8605 
 8606   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_loop" %}
 8607 
 8608   ins_encode %{
 8609     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8610                   as_Register($op2$$reg), *($lbl$$label));
 8611   %}
 8612 
 8613   ins_pipe(pipe_cmp_branch);
 8614   ins_short_branch(1);
 8615 %}
 8616 
 8617 // Compare signed long and branch near instructions
 8618 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8619 %{
 8620   // Same match rule as `far_cmpL_branch'.
 8621   match(If cmp (CmpL op1 op2));
 8622 
 8623   effect(USE lbl);
 8624 
 8625   ins_cost(BRANCH_COST);
 8626 
 8627   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_branch" %}
 8628 
 8629   ins_encode %{
 8630     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8631   %}
 8632 
 8633   ins_pipe(pipe_cmp_branch);
 8634   ins_short_branch(1);
 8635 %}
 8636 
 8637 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8638 %{
 8639   // Same match rule as `far_cmpL_loop'.
 8640   match(CountedLoopEnd cmp (CmpL op1 op2));
 8641 
 8642   effect(USE lbl);
 8643 
 8644   ins_cost(BRANCH_COST);
 8645 
 8646   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_loop" %}
 8647 
 8648   ins_encode %{
 8649     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8650   %}
 8651 
 8652   ins_pipe(pipe_cmp_branch);
 8653   ins_short_branch(1);
 8654 %}
 8655 
 8656 // Compare unsigned long and branch near instructions
 8657 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 8658 %{
 8659   // Same match rule as `far_cmpUL_branch'.
 8660   match(If cmp (CmpUL op1 op2));
 8661 
 8662   effect(USE lbl);
 8663 
 8664   ins_cost(BRANCH_COST);
 8665   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_branch" %}
 8666 
 8667   ins_encode %{
 8668     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8669                   as_Register($op2$$reg), *($lbl$$label));
 8670   %}
 8671 
 8672   ins_pipe(pipe_cmp_branch);
 8673   ins_short_branch(1);
 8674 %}
 8675 
 8676 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 8677 %{
 8678   // Same match rule as `far_cmpUL_loop'.
 8679   match(CountedLoopEnd cmp (CmpUL op1 op2));
 8680 
 8681   effect(USE lbl);
 8682 
 8683   ins_cost(BRANCH_COST);
 8684   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_loop" %}
 8685 
 8686   ins_encode %{
 8687     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8688                   as_Register($op2$$reg), *($lbl$$label));
 8689   %}
 8690 
 8691   ins_pipe(pipe_cmp_branch);
 8692   ins_short_branch(1);
 8693 %}
 8694 
 8695 // Compare pointer and branch near instructions
 8696 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 8697 %{
 8698   // Same match rule as `far_cmpP_branch'.
 8699   match(If cmp (CmpP op1 op2));
 8700 
 8701   effect(USE lbl);
 8702 
 8703   ins_cost(BRANCH_COST);
 8704 
 8705   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_branch" %}
 8706 
 8707   ins_encode %{
 8708     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8709                   as_Register($op2$$reg), *($lbl$$label));
 8710   %}
 8711 
 8712   ins_pipe(pipe_cmp_branch);
 8713   ins_short_branch(1);
 8714 %}
 8715 
 8716 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 8717 %{
 8718   // Same match rule as `far_cmpP_loop'.
 8719   match(CountedLoopEnd cmp (CmpP op1 op2));
 8720 
 8721   effect(USE lbl);
 8722 
 8723   ins_cost(BRANCH_COST);
 8724 
 8725   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_loop" %}
 8726 
 8727   ins_encode %{
 8728     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8729                   as_Register($op2$$reg), *($lbl$$label));
 8730   %}
 8731 
 8732   ins_pipe(pipe_cmp_branch);
 8733   ins_short_branch(1);
 8734 %}
 8735 
 8736 // Compare narrow pointer and branch near instructions
 8737 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 8738 %{
 8739   // Same match rule as `far_cmpN_branch'.
 8740   match(If cmp (CmpN op1 op2));
 8741 
 8742   effect(USE lbl);
 8743 
 8744   ins_cost(BRANCH_COST);
 8745 
 8746   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_branch" %}
 8747 
 8748   ins_encode %{
 8749     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8750                   as_Register($op2$$reg), *($lbl$$label));
 8751   %}
 8752 
 8753   ins_pipe(pipe_cmp_branch);
 8754   ins_short_branch(1);
 8755 %}
 8756 
 8757 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 8758 %{
 8759   // Same match rule as `far_cmpN_loop'.
 8760   match(CountedLoopEnd cmp (CmpN op1 op2));
 8761 
 8762   effect(USE lbl);
 8763 
 8764   ins_cost(BRANCH_COST);
 8765 
 8766   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_loop" %}
 8767 
 8768   ins_encode %{
 8769     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8770                   as_Register($op2$$reg), *($lbl$$label));
 8771   %}
 8772 
 8773   ins_pipe(pipe_cmp_branch);
 8774   ins_short_branch(1);
 8775 %}
 8776 
 8777 // Compare float and branch near instructions
 8778 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 8779 %{
 8780   // Same match rule as `far_cmpF_branch'.
 8781   match(If cmp (CmpF op1 op2));
 8782 
 8783   effect(USE lbl);
 8784 
 8785   ins_cost(XFER_COST + BRANCH_COST);
 8786   format %{ "float_b$cmp $op1, $op2 \t#@cmpF_branch"%}
 8787 
 8788   ins_encode %{
 8789     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 8790   %}
 8791 
 8792   ins_pipe(pipe_class_compare);
 8793   ins_short_branch(1);
 8794 %}
 8795 
 8796 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 8797 %{
 8798   // Same match rule as `far_cmpF_loop'.
 8799   match(CountedLoopEnd cmp (CmpF op1 op2));
 8800   effect(USE lbl);
 8801 
 8802   ins_cost(XFER_COST + BRANCH_COST);
 8803   format %{ "float_b$cmp $op1, $op2\t#@cmpF_loop"%}
 8804 
 8805   ins_encode %{
 8806     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 8807   %}
 8808 
 8809   ins_pipe(pipe_class_compare);
 8810   ins_short_branch(1);
 8811 %}
 8812 
 8813 // Compare double and branch near instructions
 8814 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 8815 %{
 8816   // Same match rule as `far_cmpD_branch'.
 8817   match(If cmp (CmpD op1 op2));
 8818   effect(USE lbl);
 8819 
 8820   ins_cost(XFER_COST + BRANCH_COST);
 8821   format %{ "double_b$cmp $op1, $op2\t#@cmpD_branch"%}
 8822 
 8823   ins_encode %{
 8824     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 8825                         as_FloatRegister($op2$$reg), *($lbl$$label));
 8826   %}
 8827 
 8828   ins_pipe(pipe_class_compare);
 8829   ins_short_branch(1);
 8830 %}
 8831 
 8832 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 8833 %{
 8834   // Same match rule as `far_cmpD_loop'.
 8835   match(CountedLoopEnd cmp (CmpD op1 op2));
 8836   effect(USE lbl);
 8837 
 8838   ins_cost(XFER_COST + BRANCH_COST);
 8839   format %{ "double_b$cmp $op1, $op2\t#@cmpD_loop"%}
 8840 
 8841   ins_encode %{
 8842     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 8843                         as_FloatRegister($op2$$reg), *($lbl$$label));
 8844   %}
 8845 
 8846   ins_pipe(pipe_class_compare);
 8847   ins_short_branch(1);
 8848 %}
 8849 
 8850 // Compare signed int with zero and branch near instructions
 8851 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 8852 %{
 8853   // Same match rule as `far_cmpI_reg_imm0_branch'.
 8854   match(If cmp (CmpI op1 zero));
 8855 
 8856   effect(USE op1, USE lbl);
 8857 
 8858   ins_cost(BRANCH_COST);
 8859   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
 8860 
 8861   ins_encode %{
 8862     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 8863   %}
 8864 
 8865   ins_pipe(pipe_cmpz_branch);
 8866   ins_short_branch(1);
 8867 %}
 8868 
 8869 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 8870 %{
 8871   // Same match rule as `far_cmpI_reg_imm0_loop'.
 8872   match(CountedLoopEnd cmp (CmpI op1 zero));
 8873 
 8874   effect(USE op1, USE lbl);
 8875 
 8876   ins_cost(BRANCH_COST);
 8877 
 8878   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
 8879 
 8880   ins_encode %{
 8881     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 8882   %}
 8883 
 8884   ins_pipe(pipe_cmpz_branch);
 8885   ins_short_branch(1);
 8886 %}
 8887 
 8888 // Compare unsigned int with zero and branch near instructions
 8889 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 8890 %{
 8891   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
 8892   match(If cmp (CmpU op1 zero));
 8893 
 8894   effect(USE op1, USE lbl);
 8895 
 8896   ins_cost(BRANCH_COST);
 8897 
 8898   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
 8899 
 8900   ins_encode %{
 8901     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 8902   %}
 8903 
 8904   ins_pipe(pipe_cmpz_branch);
 8905   ins_short_branch(1);
 8906 %}
 8907 
 8908 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 8909 %{
 8910   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
 8911   match(CountedLoopEnd cmp (CmpU op1 zero));
 8912 
 8913   effect(USE op1, USE lbl);
 8914 
 8915   ins_cost(BRANCH_COST);
 8916 
 8917   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
 8918 
 8919 
 8920   ins_encode %{
 8921     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 8922   %}
 8923 
 8924   ins_pipe(pipe_cmpz_branch);
 8925   ins_short_branch(1);
 8926 %}
 8927 
 8928 // Compare signed long with zero and branch near instructions
 8929 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 8930 %{
 8931   // Same match rule as `far_cmpL_reg_imm0_branch'.
 8932   match(If cmp (CmpL op1 zero));
 8933 
 8934   effect(USE op1, USE lbl);
 8935 
 8936   ins_cost(BRANCH_COST);
 8937 
 8938   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
 8939 
 8940   ins_encode %{
 8941     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 8942   %}
 8943 
 8944   ins_pipe(pipe_cmpz_branch);
 8945   ins_short_branch(1);
 8946 %}
 8947 
 8948 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 8949 %{
 8950   // Same match rule as `far_cmpL_reg_imm0_loop'.
 8951   match(CountedLoopEnd cmp (CmpL op1 zero));
 8952 
 8953   effect(USE op1, USE lbl);
 8954 
 8955   ins_cost(BRANCH_COST);
 8956 
 8957   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
 8958 
 8959   ins_encode %{
 8960     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 8961   %}
 8962 
 8963   ins_pipe(pipe_cmpz_branch);
 8964   ins_short_branch(1);
 8965 %}
 8966 
 8967 // Compare unsigned long with zero and branch near instructions
 8968 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 8969 %{
 8970   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
 8971   match(If cmp (CmpUL op1 zero));
 8972 
 8973   effect(USE op1, USE lbl);
 8974 
 8975   ins_cost(BRANCH_COST);
 8976 
 8977   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
 8978 
 8979   ins_encode %{
 8980     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 8981   %}
 8982 
 8983   ins_pipe(pipe_cmpz_branch);
 8984   ins_short_branch(1);
 8985 %}
 8986 
 8987 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 8988 %{
 8989   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
 8990   match(CountedLoopEnd cmp (CmpUL op1 zero));
 8991 
 8992   effect(USE op1, USE lbl);
 8993 
 8994   ins_cost(BRANCH_COST);
 8995 
 8996   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
 8997 
 8998   ins_encode %{
 8999     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9000   %}
 9001 
 9002   ins_pipe(pipe_cmpz_branch);
 9003   ins_short_branch(1);
 9004 %}
 9005 
 9006 // Compare pointer with zero and branch near instructions
 9007 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9008   // Same match rule as `far_cmpP_reg_imm0_branch'.
 9009   match(If cmp (CmpP op1 zero));
 9010   effect(USE lbl);
 9011 
 9012   ins_cost(BRANCH_COST);
 9013   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
 9014 
 9015   ins_encode %{
 9016     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9017   %}
 9018 
 9019   ins_pipe(pipe_cmpz_branch);
 9020   ins_short_branch(1);
 9021 %}
 9022 
 9023 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9024   // Same match rule as `far_cmpP_reg_imm0_loop'.
 9025   match(CountedLoopEnd cmp (CmpP op1 zero));
 9026   effect(USE lbl);
 9027 
 9028   ins_cost(BRANCH_COST);
 9029   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
 9030 
 9031   ins_encode %{
 9032     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9033   %}
 9034 
 9035   ins_pipe(pipe_cmpz_branch);
 9036   ins_short_branch(1);
 9037 %}
 9038 
 9039 // Compare narrow pointer with zero and branch near instructions
 9040 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9041   // Same match rule as `far_cmpN_reg_imm0_branch'.
 9042   match(If cmp (CmpN op1 zero));
 9043   effect(USE lbl);
 9044 
 9045   ins_cost(BRANCH_COST);
 9046 
 9047   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
 9048 
 9049   ins_encode %{
 9050     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9051   %}
 9052 
 9053   ins_pipe(pipe_cmpz_branch);
 9054   ins_short_branch(1);
 9055 %}
 9056 
 9057 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9058   // Same match rule as `far_cmpN_reg_imm0_loop'.
 9059   match(CountedLoopEnd cmp (CmpN op1 zero));
 9060   effect(USE lbl);
 9061 
 9062   ins_cost(BRANCH_COST);
 9063 
 9064   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
 9065 
 9066   ins_encode %{
 9067     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9068   %}
 9069 
 9070   ins_pipe(pipe_cmpz_branch);
 9071   ins_short_branch(1);
 9072 %}
 9073 
 9074 // Compare narrow pointer with pointer zero and branch near instructions
 9075 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9076   // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
 9077   match(If cmp (CmpP (DecodeN op1) zero));
 9078   effect(USE lbl);
 9079 
 9080   ins_cost(BRANCH_COST);
 9081   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
 9082 
 9083   ins_encode %{
 9084     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9085   %}
 9086 
 9087   ins_pipe(pipe_cmpz_branch);
 9088   ins_short_branch(1);
 9089 %}
 9090 
 9091 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9092   // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
 9093   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9094   effect(USE lbl);
 9095 
 9096   ins_cost(BRANCH_COST);
 9097   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
 9098 
 9099   ins_encode %{
 9100     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9101   %}
 9102 
 9103   ins_pipe(pipe_cmpz_branch);
 9104   ins_short_branch(1);
 9105 %}
 9106 
 9107 // Patterns for far (20KiB) variants
 9108 
 9109 instruct far_cmpFlag_branch(cmpOp cmp, iRegI_R6 cr, label lbl) %{
 9110   match(If cmp cr);
 9111   effect(USE lbl);
 9112 
 9113   ins_cost(BRANCH_COST);
 9114   format %{ "far_b$cmp $cr, zr, L\t#@far_cmpFlag_branch"%}
 9115 
 9116   ins_encode %{
 9117     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
 9118   %}
 9119 
 9120   ins_pipe(pipe_cmpz_branch);
 9121 %}
 9122 
 9123 // Compare signed int and branch far instructions
 9124 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9125   match(If cmp (CmpI op1 op2));
 9126   effect(USE lbl);
 9127 
 9128   ins_cost(BRANCH_COST * 2);
 9129 
 9130   // the format instruction [far_b$cmp] here is be used as two insructions
 9131   // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
 9132   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_branch" %}
 9133 
 9134   ins_encode %{
 9135     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9136   %}
 9137 
 9138   ins_pipe(pipe_cmp_branch);
 9139 %}
 9140 
 9141 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9142   match(CountedLoopEnd cmp (CmpI op1 op2));
 9143   effect(USE lbl);
 9144 
 9145   ins_cost(BRANCH_COST * 2);
 9146   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_loop" %}
 9147 
 9148   ins_encode %{
 9149     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9150   %}
 9151 
 9152   ins_pipe(pipe_cmp_branch);
 9153 %}
 9154 
 9155 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9156   match(If cmp (CmpU op1 op2));
 9157   effect(USE lbl);
 9158 
 9159   ins_cost(BRANCH_COST * 2);
 9160   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
 9161 
 9162   ins_encode %{
 9163     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9164                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9165   %}
 9166 
 9167   ins_pipe(pipe_cmp_branch);
 9168 %}
 9169 
 9170 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9171   match(CountedLoopEnd cmp (CmpU op1 op2));
 9172   effect(USE lbl);
 9173 
 9174   ins_cost(BRANCH_COST * 2);
 9175   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
 9176 
 9177   ins_encode %{
 9178     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9179                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9180   %}
 9181 
 9182   ins_pipe(pipe_cmp_branch);
 9183 %}
 9184 
 9185 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9186   match(If cmp (CmpL op1 op2));
 9187   effect(USE lbl);
 9188 
 9189   ins_cost(BRANCH_COST * 2);
 9190   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_branch" %}
 9191 
 9192   ins_encode %{
 9193     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9194   %}
 9195 
 9196   ins_pipe(pipe_cmp_branch);
 9197 %}
 9198 
 9199 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9200   match(CountedLoopEnd cmp (CmpL op1 op2));
 9201   effect(USE lbl);
 9202 
 9203   ins_cost(BRANCH_COST * 2);
 9204   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_loop" %}
 9205 
 9206   ins_encode %{
 9207     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9208   %}
 9209 
 9210   ins_pipe(pipe_cmp_branch);
 9211 %}
 9212 
 9213 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9214   match(If cmp (CmpUL op1 op2));
 9215   effect(USE lbl);
 9216 
 9217   ins_cost(BRANCH_COST * 2);
 9218   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
 9219 
 9220   ins_encode %{
 9221     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9222                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9223   %}
 9224 
 9225   ins_pipe(pipe_cmp_branch);
 9226 %}
 9227 
 9228 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9229   match(CountedLoopEnd cmp (CmpUL op1 op2));
 9230   effect(USE lbl);
 9231 
 9232   ins_cost(BRANCH_COST * 2);
 9233   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
 9234 
 9235   ins_encode %{
 9236     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9237                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9238   %}
 9239 
 9240   ins_pipe(pipe_cmp_branch);
 9241 %}
 9242 
 9243 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9244 %{
 9245   match(If cmp (CmpP op1 op2));
 9246 
 9247   effect(USE lbl);
 9248 
 9249   ins_cost(BRANCH_COST * 2);
 9250 
 9251   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_branch" %}
 9252 
 9253   ins_encode %{
 9254     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9255                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9256   %}
 9257 
 9258   ins_pipe(pipe_cmp_branch);
 9259 %}
 9260 
 9261 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9262 %{
 9263   match(CountedLoopEnd cmp (CmpP op1 op2));
 9264 
 9265   effect(USE lbl);
 9266 
 9267   ins_cost(BRANCH_COST * 2);
 9268 
 9269   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_loop" %}
 9270 
 9271   ins_encode %{
 9272     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9273                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9274   %}
 9275 
 9276   ins_pipe(pipe_cmp_branch);
 9277 %}
 9278 
 9279 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9280 %{
 9281   match(If cmp (CmpN op1 op2));
 9282 
 9283   effect(USE lbl);
 9284 
 9285   ins_cost(BRANCH_COST * 2);
 9286 
 9287   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_branch" %}
 9288 
 9289   ins_encode %{
 9290     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9291                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9292   %}
 9293 
 9294   ins_pipe(pipe_cmp_branch);
 9295 %}
 9296 
 9297 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9298 %{
 9299   match(CountedLoopEnd cmp (CmpN op1 op2));
 9300 
 9301   effect(USE lbl);
 9302 
 9303   ins_cost(BRANCH_COST * 2);
 9304 
 9305   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_loop" %}
 9306 
 9307   ins_encode %{
 9308     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9309                   as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9310   %}
 9311 
 9312   ins_pipe(pipe_cmp_branch);
 9313 %}
 9314 
 9315 // Float compare and branch instructions
 9316 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9317 %{
 9318   match(If cmp (CmpF op1 op2));
 9319 
 9320   effect(USE lbl);
 9321 
 9322   ins_cost(XFER_COST + BRANCH_COST * 2);
 9323   format %{ "far_float_b$cmp $op1, $op2\t#@far_cmpF_branch"%}
 9324 
 9325   ins_encode %{
 9326     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9327                         *($lbl$$label), /* is_far */ true);
 9328   %}
 9329 
 9330   ins_pipe(pipe_class_compare);
 9331 %}
 9332 
 9333 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9334 %{
 9335   match(CountedLoopEnd cmp (CmpF op1 op2));
 9336   effect(USE lbl);
 9337 
 9338   ins_cost(XFER_COST + BRANCH_COST * 2);
 9339   format %{ "far_float_b$cmp $op1, $op2\t#@far_cmpF_loop"%}
 9340 
 9341   ins_encode %{
 9342     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9343                         *($lbl$$label), /* is_far */ true);
 9344   %}
 9345 
 9346   ins_pipe(pipe_class_compare);
 9347 %}
 9348 
 9349 // Double compare and branch instructions
 9350 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9351 %{
 9352   match(If cmp (CmpD op1 op2));
 9353   effect(USE lbl);
 9354 
 9355   ins_cost(XFER_COST + BRANCH_COST * 2);
 9356   format %{ "far_double_b$cmp $op1, $op2\t#@far_cmpD_branch"%}
 9357 
 9358   ins_encode %{
 9359     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9360                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9361   %}
 9362 
 9363   ins_pipe(pipe_class_compare);
 9364 %}
 9365 
 9366 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9367 %{
 9368   match(CountedLoopEnd cmp (CmpD op1 op2));
 9369   effect(USE lbl);
 9370 
 9371   ins_cost(XFER_COST + BRANCH_COST * 2);
 9372   format %{ "far_double_b$cmp $op1, $op2\t#@far_cmpD_loop"%}
 9373 
 9374   ins_encode %{
 9375     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9376                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9377   %}
 9378 
 9379   ins_pipe(pipe_class_compare);
 9380 %}
 9381 
 9382 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9383 %{
 9384   match(If cmp (CmpI op1 zero));
 9385 
 9386   effect(USE op1, USE lbl);
 9387 
 9388   ins_cost(BRANCH_COST * 2);
 9389 
 9390   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
 9391 
 9392   ins_encode %{
 9393     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9394   %}
 9395 
 9396   ins_pipe(pipe_cmpz_branch);
 9397 %}
 9398 
 9399 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9400 %{
 9401   match(CountedLoopEnd cmp (CmpI op1 zero));
 9402 
 9403   effect(USE op1, USE lbl);
 9404 
 9405   ins_cost(BRANCH_COST * 2);
 9406 
 9407   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
 9408 
 9409   ins_encode %{
 9410     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9411   %}
 9412 
 9413   ins_pipe(pipe_cmpz_branch);
 9414 %}
 9415 
 9416 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9417 %{
 9418   match(If cmp (CmpU op1 zero));
 9419 
 9420   effect(USE op1, USE lbl);
 9421 
 9422   ins_cost(BRANCH_COST * 2);
 9423 
 9424   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
 9425 
 9426   ins_encode %{
 9427     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9428   %}
 9429 
 9430   ins_pipe(pipe_cmpz_branch);
 9431 %}
 9432 
 9433 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9434 %{
 9435   match(CountedLoopEnd cmp (CmpU op1 zero));
 9436 
 9437   effect(USE op1, USE lbl);
 9438 
 9439   ins_cost(BRANCH_COST * 2);
 9440 
 9441   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
 9442 
 9443 
 9444   ins_encode %{
 9445     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9446   %}
 9447 
 9448   ins_pipe(pipe_cmpz_branch);
 9449 %}
 9450 
 9451 // compare lt/ge unsigned instructs has no short instruct with same match
 9452 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9453 %{
 9454   match(If cmp (CmpU op1 zero));
 9455 
 9456   effect(USE op1, USE lbl);
 9457 
 9458   ins_cost(BRANCH_COST);
 9459 
 9460   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
 9461 
 9462   ins_encode(riscv64_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9463 
 9464   ins_pipe(pipe_cmpz_branch);
 9465 %}
 9466 
 9467 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9468 %{
 9469   match(CountedLoopEnd cmp (CmpU op1 zero));
 9470 
 9471   effect(USE op1, USE lbl);
 9472 
 9473   ins_cost(BRANCH_COST);
 9474 
 9475   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
 9476 
 9477   ins_encode(riscv64_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9478 
 9479   ins_pipe(pipe_cmpz_branch);
 9480 %}
 9481 
 9482 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9483 %{
 9484   match(If cmp (CmpL op1 zero));
 9485 
 9486   effect(USE op1, USE lbl);
 9487 
 9488   ins_cost(BRANCH_COST * 2);
 9489 
 9490   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
 9491 
 9492   ins_encode %{
 9493     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9494   %}
 9495 
 9496   ins_pipe(pipe_cmpz_branch);
 9497 %}
 9498 
 9499 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9500 %{
 9501   match(CountedLoopEnd cmp (CmpL op1 zero));
 9502 
 9503   effect(USE op1, USE lbl);
 9504 
 9505   ins_cost(BRANCH_COST * 2);
 9506 
 9507   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
 9508 
 9509   ins_encode %{
 9510     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9511   %}
 9512 
 9513   ins_pipe(pipe_cmpz_branch);
 9514 %}
 9515 
 9516 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9517 %{
 9518   match(If cmp (CmpUL op1 zero));
 9519 
 9520   effect(USE op1, USE lbl);
 9521 
 9522   ins_cost(BRANCH_COST * 2);
 9523 
 9524   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
 9525 
 9526   ins_encode %{
 9527     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9528   %}
 9529 
 9530   ins_pipe(pipe_cmpz_branch);
 9531 %}
 9532 
 9533 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9534 %{
 9535   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9536 
 9537   effect(USE op1, USE lbl);
 9538 
 9539   ins_cost(BRANCH_COST * 2);
 9540 
 9541   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
 9542 
 9543   ins_encode %{
 9544     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9545   %}
 9546 
 9547   ins_pipe(pipe_cmpz_branch);
 9548 %}
 9549 
 9550 // compare lt/ge unsigned instructs has no short instruct with same match
 9551 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9552 %{
 9553   match(If cmp (CmpUL op1 zero));
 9554 
 9555   effect(USE op1, USE lbl);
 9556 
 9557   ins_cost(BRANCH_COST);
 9558 
 9559   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
 9560 
 9561   ins_encode(riscv64_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9562 
 9563   ins_pipe(pipe_cmpz_branch);
 9564 %}
 9565 
 9566 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9567 %{
 9568   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9569 
 9570   effect(USE op1, USE lbl);
 9571 
 9572   ins_cost(BRANCH_COST);
 9573 
 9574   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
 9575 
 9576   ins_encode(riscv64_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9577 
 9578   ins_pipe(pipe_cmpz_branch);
 9579 %}
 9580 
 9581 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9582   match(If cmp (CmpP op1 zero));
 9583   effect(USE lbl);
 9584 
 9585   ins_cost(BRANCH_COST * 2);
 9586   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
 9587 
 9588   ins_encode %{
 9589     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9590   %}
 9591 
 9592   ins_pipe(pipe_cmpz_branch);
 9593 %}
 9594 
 9595 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9596   match(CountedLoopEnd cmp (CmpP op1 zero));
 9597   effect(USE lbl);
 9598 
 9599   ins_cost(BRANCH_COST * 2);
 9600   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
 9601 
 9602   ins_encode %{
 9603     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9604   %}
 9605 
 9606   ins_pipe(pipe_cmpz_branch);
 9607 %}
 9608 
 9609 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9610   match(If cmp (CmpN op1 zero));
 9611   effect(USE lbl);
 9612 
 9613   ins_cost(BRANCH_COST * 2);
 9614 
 9615   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
 9616 
 9617   ins_encode %{
 9618     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9619   %}
 9620 
 9621   ins_pipe(pipe_cmpz_branch);
 9622 %}
 9623 
 9624 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9625   match(CountedLoopEnd cmp (CmpN op1 zero));
 9626   effect(USE lbl);
 9627 
 9628   ins_cost(BRANCH_COST * 2);
 9629 
 9630   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
 9631 
 9632   ins_encode %{
 9633     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9634   %}
 9635 
 9636   ins_pipe(pipe_cmpz_branch);
 9637 %}
 9638 
 9639 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9640   match(If cmp (CmpP (DecodeN op1) zero));
 9641   effect(USE lbl);
 9642 
 9643   ins_cost(BRANCH_COST * 2);
 9644   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
 9645 
 9646   ins_encode %{
 9647     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9648   %}
 9649 
 9650   ins_pipe(pipe_cmpz_branch);
 9651 %}
 9652 
 9653 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9654   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9655   effect(USE lbl);
 9656 
 9657   ins_cost(BRANCH_COST * 2);
 9658   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
 9659 
 9660   ins_encode %{
 9661     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9662   %}
 9663 
 9664   ins_pipe(pipe_cmpz_branch);
 9665 %}
 9666 
 9667 // ============================================================================
 9668 // Conditional Move Instructions
 9669 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
 9670   match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
 9671   ins_cost(ALU_COST + BRANCH_COST);
 9672 
 9673   format %{
 9674              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t"
 9675              "mv $dst, $src\n\t"
 9676              "skip:"
 9677          %}
 9678 
 9679   ins_encode %{
 9680     __ enc_cmove($cop$$cmpcode,
 9681                  as_Register($op1$$reg), as_Register($op2$$reg),
 9682                  as_Register($dst$$reg), as_Register($src$$reg));
 9683   %}
 9684 
 9685   ins_pipe(pipe_slow);
 9686 %}
 9687 
 9688 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
 9689   match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
 9690   ins_cost(ALU_COST + BRANCH_COST);
 9691 
 9692   format %{
 9693              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t"
 9694              "mv $dst, $src\n\t"
 9695              "skip:"
 9696          %}    
 9697 
 9698   ins_encode %{
 9699     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9700                  as_Register($op1$$reg), as_Register($op2$$reg),
 9701                  as_Register($dst$$reg), as_Register($src$$reg));
 9702   %}
 9703 
 9704   ins_pipe(pipe_slow);
 9705 %}
 9706 
 9707 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
 9708   match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
 9709   ins_cost(ALU_COST + BRANCH_COST);
 9710 
 9711   format %{
 9712              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t"
 9713              "mv $dst, $src\n\t"
 9714              "skip:"
 9715          %}
 9716 
 9717   ins_encode %{
 9718     __ enc_cmove($cop$$cmpcode,
 9719                  as_Register($op1$$reg), as_Register($op2$$reg),
 9720                  as_Register($dst$$reg), as_Register($src$$reg));
 9721   %}
 9722 
 9723   ins_pipe(pipe_slow);
 9724 %}
 9725 
 9726 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
 9727   match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
 9728   ins_cost(ALU_COST + BRANCH_COST);
 9729 
 9730   format %{
 9731              "bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t"
 9732              "mv $dst, $src\n\t"
 9733              "skip:"
 9734          %}
 9735 
 9736   ins_encode %{
 9737     __ enc_cmove($cop$$cmpcode,
 9738                  as_Register($op1$$reg), as_Register($op2$$reg),
 9739                  as_Register($dst$$reg), as_Register($src$$reg));
 9740   %}
 9741 
 9742   ins_pipe(pipe_slow);
 9743 %}
 9744 
 9745 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
 9746   match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
 9747   ins_cost(ALU_COST + BRANCH_COST);
 9748 
 9749   format %{
 9750              "bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t"
 9751              "mv $dst, $src\n\t"
 9752              "skip:"
 9753          %}
 9754 
 9755   ins_encode %{
 9756     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9757                  as_Register($op1$$reg), as_Register($op2$$reg),
 9758                  as_Register($dst$$reg), as_Register($src$$reg));
 9759   %}
 9760 
 9761   ins_pipe(pipe_slow);
 9762 %}
 9763 
 9764 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
 9765   match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
 9766   ins_cost(ALU_COST + BRANCH_COST);
 9767   format %{
 9768              "bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t"
 9769              "mv $dst, $src\n\t"
 9770              "skip:"
 9771          %}
 9772 
 9773   ins_encode %{
 9774     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9775                  as_Register($op1$$reg), as_Register($op2$$reg),
 9776                  as_Register($dst$$reg), as_Register($src$$reg));
 9777   %}
 9778 
 9779   ins_pipe(pipe_slow);
 9780 %}
 9781 
 9782 
 9783 // ============================================================================
 9784 // Procedure Call/Return Instructions
 9785 
 9786 // Call Java Static Instruction
 9787 
 9788 instruct CallStaticJavaDirect(method meth)
 9789 %{
 9790   match(CallStaticJava);
 9791 
 9792   effect(USE meth);
 9793 
 9794   ins_cost(BRANCH_COST);
 9795 
 9796   format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
 9797 
 9798   ins_encode( riscv64_enc_java_static_call(meth),
 9799               riscv64_enc_call_epilog );
 9800 
 9801   ins_pipe(pipe_class_call);
 9802 %}
 9803 
 9804 // TO HERE
 9805 
 9806 // Call Java Dynamic Instruction
 9807 instruct CallDynamicJavaDirect(method meth, iRegL_R6 cr)
 9808 %{
 9809   match(CallDynamicJava);
 9810 
 9811   effect(USE meth, KILL cr);
 9812 
 9813   ins_cost(BRANCH_COST + ALU_COST * 6);
 9814 
 9815   format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
 9816 
 9817   ins_encode( riscv64_enc_java_dynamic_call(meth),
 9818                riscv64_enc_call_epilog );
 9819 
 9820   ins_pipe(pipe_class_call);
 9821 %}
 9822 
 9823 // Call Runtime Instruction
 9824 
 9825 instruct CallRuntimeDirect(method meth, iRegL_R6 cr)
 9826 %{
 9827   match(CallRuntime);
 9828 
 9829   effect(USE meth, KILL cr);
 9830 
 9831   ins_cost(BRANCH_COST);
 9832 
 9833   format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
 9834 
 9835   ins_encode( riscv64_enc_java_to_runtime(meth) );
 9836 
 9837   ins_pipe(pipe_class_call);
 9838 %}
 9839 
 9840 // Call Runtime Instruction
 9841 
 9842 instruct CallLeafDirect(method meth, iRegL_R6 cr)
 9843 %{
 9844   match(CallLeaf);
 9845 
 9846   effect(USE meth, KILL cr);
 9847 
 9848   ins_cost(BRANCH_COST);
 9849 
 9850   format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
 9851 
 9852   ins_encode( riscv64_enc_java_to_runtime(meth) );
 9853 
 9854   ins_pipe(pipe_class_call);
 9855 %}
 9856 
 9857 // Call Runtime Instruction
 9858 
 9859 instruct CallLeafNoFPDirect(method meth, iRegL_R6 cr)
 9860 %{
 9861   match(CallLeafNoFP);
 9862 
 9863   effect(USE meth, KILL cr);
 9864 
 9865   ins_cost(BRANCH_COST);
 9866 
 9867   format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
 9868 
 9869   ins_encode( riscv64_enc_java_to_runtime(meth) );
 9870 
 9871   ins_pipe(pipe_class_call);
 9872 %}
 9873 
 9874 // ============================================================================
 9875 // Partial Subtype Check
 9876 //
 9877 // superklass array for an instance of the superklass.  Set a hidden
 9878 // internal cache on a hit (cache is checked with exposed code in
 9879 // gen_subtype_check()).  Return zero for a hit.  The encoding
 9880 // ALSO sets flags.
 9881 
 9882 instruct partialSubtypeCheck(iRegI_R6 cr, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 temp, iRegP_R15 result)
 9883 %{
 9884   match(Set result (PartialSubtypeCheck sub super));
 9885   effect(KILL temp, KILL cr);
 9886 
 9887   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
 9888   format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
 9889 
 9890   ins_encode(riscv64_enc_partial_subtype_check(sub, super, temp, result, cr));
 9891 
 9892   opcode(0x1); // Force zero of result reg on hit
 9893 
 9894   ins_pipe(pipe_class_memory);
 9895 %}
 9896 
 9897 instruct partialSubtypeCheckVsZero(iRegP_R14 sub, iRegP_R10 super, iRegP_R12 temp, iRegP_R15 result,
 9898                                            immP0 zero, iRegI_R6 cr)
 9899 %{
 9900   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
 9901   effect(KILL temp, KILL result);
 9902 
 9903   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
 9904   format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
 9905 
 9906   ins_encode(riscv64_enc_partial_subtype_check(sub, super, temp, result, cr));
 9907 
 9908   opcode(0x0); // Don't zero result reg on hit
 9909 
 9910   ins_pipe(pipe_class_memory);
 9911 %}
 9912 
 9913 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
 9914                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, iRegL_R6 cr)
 9915 %{
 9916   predicate(!UseVExt && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
 9917   match(Set result(StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
 9918   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
 9919 
 9920   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
 9921   ins_encode %{
 9922     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
 9923     __ string_compare($str1$$Register, $str2$$Register,
 9924                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
 9925                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
 9926                       StrIntrinsicNode::UU);
 9927   %}
 9928   ins_pipe(pipe_class_memory);
 9929 %}
 9930 
 9931 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
 9932                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, iRegL_R6 cr)
 9933 %{
 9934   predicate(!UseVExt && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
 9935   match(Set result(StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
 9936   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
 9937 
 9938   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
 9939   ins_encode %{
 9940     __ string_compare($str1$$Register, $str2$$Register,
 9941                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
 9942                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
 9943                       StrIntrinsicNode::LL);
 9944   %}
 9945   ins_pipe(pipe_class_memory);
 9946 %}
 9947 
 9948 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
 9949                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, iRegL_R6 cr)
 9950 %{
 9951   predicate(!UseVExt && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
 9952   match(Set result(StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
 9953   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
 9954 
 9955   format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
 9956   ins_encode %{
 9957     __ string_compare($str1$$Register, $str2$$Register,
 9958                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
 9959                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
 9960                       StrIntrinsicNode::UL);
 9961   %}
 9962   ins_pipe(pipe_class_memory);
 9963 %}
 9964 
 9965 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
 9966                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
 9967                           iRegL_R6 cr)
 9968 %{
 9969   predicate(!UseVExt && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
 9970   match(Set result(StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
 9971   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
 9972 
 9973   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
 9974   ins_encode %{
 9975     __ string_compare($str1$$Register, $str2$$Register,
 9976                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
 9977                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
 9978                       StrIntrinsicNode::LU);
 9979   %}
 9980   ins_pipe(pipe_class_memory);
 9981 %}
 9982 
 9983 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
 9984        iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
 9985        iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, iRegL_R6 tmp)
 9986 %{
 9987   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
 9988   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
 9989   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
 9990          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL tmp);
 9991   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
 9992 
 9993   ins_encode %{
 9994     __ string_indexof($str1$$Register, $str2$$Register,
 9995                       $cnt1$$Register, $cnt2$$Register,
 9996                       $tmp1$$Register, $tmp2$$Register,
 9997                       $tmp3$$Register, $tmp4$$Register,
 9998                       $tmp5$$Register, $tmp6$$Register,
 9999                       $result$$Register, StrIntrinsicNode::UU);
10000   %}
10001   ins_pipe(pipe_class_memory);
10002 %}
10003 
10004 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10005        iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10006        iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, iRegL_R6 tmp)
10007 %{
10008   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10009   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10010   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10011          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL tmp);
10012   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10013 
10014   ins_encode %{
10015     __ string_indexof($str1$$Register, $str2$$Register,
10016                       $cnt1$$Register, $cnt2$$Register,
10017                       $tmp1$$Register, $tmp2$$Register,
10018                       $tmp3$$Register, $tmp4$$Register,
10019                       $tmp5$$Register, $tmp6$$Register,
10020                       $result$$Register, StrIntrinsicNode::LL);
10021   %}
10022   ins_pipe(pipe_class_memory);
10023 %}
10024 
10025 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10026        iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10027        iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, iRegL_R6 tmp)
10028 %{
10029   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10030   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10031   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10032          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL tmp);
10033   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10034 
10035   ins_encode %{
10036     __ string_indexof($str1$$Register, $str2$$Register,
10037                       $cnt1$$Register, $cnt2$$Register,
10038                       $tmp1$$Register, $tmp2$$Register,
10039                       $tmp3$$Register, $tmp4$$Register,
10040                       $tmp5$$Register, $tmp6$$Register,
10041                       $result$$Register, StrIntrinsicNode::UL);
10042   %}
10043   ins_pipe(pipe_class_memory);
10044 %}
10045 
10046 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10047                  immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10048                  iRegINoSp tmp3, iRegINoSp tmp4, iRegL_R6 tmp)
10049 %{
10050   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10051   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10052   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10053          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp);
10054   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10055 
10056   ins_encode %{
10057     int icnt2 = (int)$int_cnt2$$constant;
10058     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10059                                  $cnt1$$Register, zr,
10060                                  $tmp1$$Register, $tmp2$$Register,
10061                                  $tmp3$$Register, $tmp4$$Register,
10062                                  icnt2, $result$$Register, StrIntrinsicNode::UU);
10063   %}
10064   ins_pipe(pipe_class_memory);
10065 %}
10066 
10067 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10068                  immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10069                  iRegINoSp tmp3, iRegINoSp tmp4, iRegL_R6 tmp)
10070 %{
10071   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10072   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10073   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10074          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp);
10075   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10076 
10077   ins_encode %{
10078     int icnt2 = (int)$int_cnt2$$constant;
10079     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10080                                  $cnt1$$Register, zr,
10081                                  $tmp1$$Register, $tmp2$$Register,
10082                                  $tmp3$$Register, $tmp4$$Register,
10083                                  icnt2, $result$$Register, StrIntrinsicNode::LL);
10084   %}
10085   ins_pipe(pipe_class_memory);
10086 %}
10087 
10088 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10089                  immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10090                  iRegINoSp tmp3, iRegINoSp tmp4, iRegL_R6 tmp)
10091 %{
10092   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10093   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10094   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10095          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp);
10096   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10097 
10098   ins_encode %{
10099     int icnt2 = (int)$int_cnt2$$constant;
10100     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10101                                  $cnt1$$Register, zr,
10102                                  $tmp1$$Register, $tmp2$$Register,
10103                                  $tmp3$$Register, $tmp4$$Register,
10104                                  icnt2, $result$$Register, StrIntrinsicNode::UL);
10105   %}
10106   ins_pipe(pipe_class_memory);
10107 %}
10108 
10109 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10110                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10111                               iRegINoSp tmp3, iRegINoSp tmp4, iRegL_R6 tmp)
10112 %{
10113   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10114   predicate(!UseVExt && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10115   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10116          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp);
10117 
10118   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10119 
10120   ins_encode %{
10121     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10122                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10123                            $tmp3$$Register, $tmp4$$Register, false /* isU */) ;
10124   %}
10125   ins_pipe(pipe_class_memory);
10126 %}
10127 
10128 
10129 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10130                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10131                               iRegINoSp tmp3, iRegINoSp tmp4, iRegL_R6 tmp)
10132 %{
10133   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10134   predicate(!UseVExt && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10135   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10136          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp);
10137 
10138   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10139 
10140   ins_encode %{
10141     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10142                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10143                            $tmp3$$Register, $tmp4$$Register, true /* isL */);
10144   %}
10145   ins_pipe(pipe_class_memory);
10146 %}
10147 
10148 // clearing of an array
10149 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy, iRegL_R6 cr)
10150 %{
10151   predicate(!UseVExt);
10152   match(Set dummy (ClearArray cnt base));
10153   effect(USE_KILL cnt, USE_KILL base);
10154 
10155   ins_cost(4 * DEFAULT_COST);
10156   format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10157 
10158   ins_encode %{
10159     address tpc = __ zero_words($base$$Register, $cnt$$Register);
10160     if (tpc == NULL) {
10161       ciEnv::current()->record_failure("CodeCache is full");
10162       return;
10163     }
10164   %}
10165 
10166   ins_pipe(pipe_class_memory);
10167 %}
10168 
10169 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, iRegL_R6 cr)
10170 %{
10171   predicate(!UseVExt && (uint64_t)n->in(2)->get_long()
10172             < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10173   match(Set dummy (ClearArray cnt base));
10174   effect(USE_KILL base, KILL cr);
10175 
10176   ins_cost(4 * DEFAULT_COST);
10177   format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10178 
10179   ins_encode %{
10180     __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10181   %}
10182 
10183   ins_pipe(pipe_class_memory);
10184 %}
10185 
10186 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10187                         iRegI_R10 result, iRegL_R6 cr)
10188 %{
10189   predicate(!UseVExt && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10190   match(Set result (StrEquals (Binary str1 str2) cnt));
10191   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10192 
10193   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10194   ins_encode %{
10195     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10196     __ string_equals($str1$$Register, $str2$$Register,
10197                      $result$$Register, $cnt$$Register, 1);
10198   %}
10199   ins_pipe(pipe_class_memory);
10200 %}
10201 
10202 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10203                         iRegI_R10 result, iRegL_R6 cr)
10204 %{
10205   predicate(!UseVExt && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10206   match(Set result (StrEquals (Binary str1 str2) cnt));
10207   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10208 
10209   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10210   ins_encode %{
10211     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10212     __ string_equals($str1$$Register, $str2$$Register,
10213                      $result$$Register, $cnt$$Register, 2);
10214   %}
10215   ins_pipe(pipe_class_memory);
10216 %}
10217 
10218 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10219                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10220                        iRegP_R16 tmp4, iRegP_R28 tmp, iRegL_R6 cr)
10221 %{
10222   predicate(!UseVExt && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10223   match(Set result (AryEq ary1 ary2));
10224   effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10225 
10226   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp" %}
10227   ins_encode %{
10228     __ arrays_equals($ary1$$Register, $ary2$$Register,
10229                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10230                      $result$$Register, $tmp$$Register, 1);
10231   %}
10232   ins_pipe(pipe_class_memory);
10233 %}
10234 
10235 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10236                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10237                        iRegP_R16 tmp4, iRegP_R28 tmp, iRegL_R6 cr)
10238 %{
10239   predicate(!UseVExt && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10240   match(Set result (AryEq ary1 ary2));
10241   effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10242 
10243   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp" %}
10244   ins_encode %{
10245     __ arrays_equals($ary1$$Register, $ary2$$Register,
10246                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10247                      $result$$Register, $tmp$$Register, 2);
10248   %}
10249   ins_pipe(pipe_class_memory);
10250 %}
10251 
10252 // ============================================================================
10253 // Safepoint Instructions
10254 
10255 instruct safePoint(iRegP poll)
10256 %{
10257   match(SafePoint poll);
10258 
10259   ins_cost(2 * LOAD_COST);
10260   format %{
10261     "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10262   %}
10263   ins_encode %{
10264     __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10265   %}
10266   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10267 %}
10268 
10269 // ============================================================================
10270 // This name is KNOWN by the ADLC and cannot be changed.
10271 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10272 // for this guy.
10273 instruct tlsLoadP(javaThread_RegP dst)
10274 %{
10275   match(Set dst (ThreadLocal));
10276 
10277   ins_cost(0);
10278 
10279   format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10280 
10281   size(0);
10282 
10283   ins_encode( /*empty*/ );
10284 
10285   ins_pipe(pipe_class_empty);
10286 %}
10287 
10288 // inlined locking and unlocking
10289 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10290 instruct cmpFastLock(iRegI_R6 cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
10291 %{
10292   match(Set cr (FastLock object box));
10293   effect(TEMP tmp, TEMP tmp2);
10294 
10295   ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10296   format %{ "fastlock $object,$box\t! kills $tmp,$tmp2, #@cmpFastLock" %}
10297 
10298   ins_encode(riscv64_enc_fast_lock(cr, object, box, tmp, tmp2));
10299 
10300   ins_pipe(pipe_serial);
10301 %}
10302 
10303 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10304 instruct cmpFastUnlock(iRegI_R6 cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
10305 %{
10306   match(Set cr (FastUnlock object box));
10307   effect(TEMP tmp, TEMP tmp2);
10308 
10309   ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10310   format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2, #@cmpFastUnlock" %}
10311 
10312   ins_encode(riscv64_enc_fast_unlock(cr, object, box, tmp, tmp2));
10313 
10314   ins_pipe(pipe_serial);
10315 %}
10316 
10317 // Tail Call; Jump from runtime stub to Java code.
10318 // Also known as an 'interprocedural jump'.
10319 // Target of jump will eventually return to caller.
10320 // TailJump below removes the return address.
10321 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10322 %{
10323   match(TailCall jump_target method_oop);
10324 
10325   ins_cost(BRANCH_COST);
10326 
10327   format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10328 
10329   ins_encode(riscv64_enc_tail_call(jump_target));
10330 
10331   ins_pipe(pipe_class_call);
10332 %}
10333 
10334 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10335 %{
10336   match(TailJump jump_target ex_oop);
10337 
10338   ins_cost(ALU_COST + BRANCH_COST);
10339 
10340   format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10341 
10342   ins_encode(riscv64_enc_tail_jmp(jump_target));
10343 
10344   ins_pipe(pipe_class_call);
10345 %}
10346 
10347 // Create exception oop: created by stack-crawling runtime code.
10348 // Created exception is now available to this handler, and is setup
10349 // just prior to jumping to this handler. No code emitted.
10350 instruct CreateException(iRegP_R10 ex_oop)
10351 %{
10352   match(Set ex_oop (CreateEx));
10353 
10354   ins_cost(0);
10355   format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10356 
10357   size(0);
10358 
10359   ins_encode( /*empty*/ );
10360 
10361   ins_pipe(pipe_class_empty);
10362 %}
10363 
10364 // Rethrow exception: The exception oop will come in the first
10365 // argument position. Then JUMP (not call) to the rethrow stub code.
10366 instruct RethrowException()
10367 %{
10368   match(Rethrow);
10369 
10370   ins_cost(BRANCH_COST);
10371 
10372   format %{ "j rethrow_stub\t#@RethrowException" %}
10373 
10374   ins_encode( riscv64_enc_rethrow() );
10375 
10376   ins_pipe(pipe_class_call);
10377 %}
10378 
10379 // Return Instruction
10380 // epilog node loads ret address into lr as part of frame pop
10381 instruct Ret()
10382 %{
10383   match(Return);
10384 
10385   ins_cost(BRANCH_COST);
10386   format %{ "ret\t// return register, #@Ret" %}
10387 
10388   ins_encode(riscv64_enc_ret());
10389 
10390   ins_pipe(pipe_branch);
10391 %}
10392 
10393 // Die now.
10394 instruct ShouldNotReachHere() %{
10395   match(Halt);
10396 
10397   ins_cost(BRANCH_COST);
10398 
10399   format %{ "#@ShouldNotReachHere" %}
10400 
10401   ins_encode %{
10402     if (is_reachable()) {
10403       __ halt();
10404     }
10405   %}
10406 
10407   ins_pipe(pipe_class_default);
10408 %}
10409 
10410 
10411 //----------PEEPHOLE RULES-----------------------------------------------------
10412 // These must follow all instruction definitions as they use the names
10413 // defined in the instructions definitions.
10414 //
10415 // peepmatch ( root_instr_name [preceding_instruction]* );
10416 //
10417 // peepconstraint %{
10418 // (instruction_number.operand_name relational_op instruction_number.operand_name
10419 //  [, ...] );
10420 // // instruction numbers are zero-based using left to right order in peepmatch
10421 //
10422 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10423 // // provide an instruction_number.operand_name for each operand that appears
10424 // // in the replacement instruction's match rule
10425 //
10426 // ---------VM FLAGS---------------------------------------------------------
10427 //
10428 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10429 //
10430 // Each peephole rule is given an identifying number starting with zero and
10431 // increasing by one in the order seen by the parser.  An individual peephole
10432 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10433 // on the command-line.
10434 //
10435 // ---------CURRENT LIMITATIONS----------------------------------------------
10436 //
10437 // Only match adjacent instructions in same basic block
10438 // Only equality constraints
10439 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10440 // Only one replacement instruction
10441 //
10442 //----------SMARTSPILL RULES---------------------------------------------------
10443 // These must follow all instruction definitions as they use the names
10444 // defined in the instructions definitions.
10445 
10446 // Local Variables:
10447 // mode: c++
10448 // End: