1 //
    2 // Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
    4 // Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved.
    5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    6 //
    7 // This code is free software; you can redistribute it and/or modify it
    8 // under the terms of the GNU General Public License version 2 only, as
    9 // published by the Free Software Foundation.
   10 //
   11 // This code is distributed in the hope that it will be useful, but WITHOUT
   12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   13 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   14 // version 2 for more details (a copy is included in the LICENSE file that
   15 // accompanied this code).
   16 //
   17 // You should have received a copy of the GNU General Public License version
   18 // 2 along with this work; if not, write to the Free Software Foundation,
   19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   20 //
   21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   22 // or visit www.oracle.com if you need additional information or have any
   23 // questions.
   24 //
   25 //
   26 
   27 // RISCV Architecture Description File
   28 
   29 //----------REGISTER DEFINITION BLOCK------------------------------------------
   30 // This information is used by the matcher and the register allocator to
   31 // describe individual registers and classes of registers within the target
   32 // archtecture.
   33 
   34 register %{
   35 //----------Architecture Description Register Definitions----------------------
   36 // General Registers
   37 // "reg_def"  name ( register save type, C convention save type,
   38 //                   ideal register type, encoding );
   39 // Register Save Types:
   40 //
   41 // NS  = No-Save:       The register allocator assumes that these registers
   42 //                      can be used without saving upon entry to the method, &
   43 //                      that they do not need to be saved at call sites.
   44 //
   45 // SOC = Save-On-Call:  The register allocator assumes that these registers
   46 //                      can be used without saving upon entry to the method,
   47 //                      but that they must be saved at call sites.
   48 //
   49 // SOE = Save-On-Entry: The register allocator assumes that these registers
   50 //                      must be saved before using them upon entry to the
   51 //                      method, but they do not need to be saved at call
   52 //                      sites.
   53 //
   54 // AS  = Always-Save:   The register allocator assumes that these registers
   55 //                      must be saved before using them upon entry to the
   56 //                      method, & that they must be saved at call sites.
   57 //
   58 // Ideal Register Type is used to determine how to save & restore a
   59 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   60 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   61 //
   62 // The encoding number is the actual bit-pattern placed into the opcodes.
   63 
   64 // We must define the 64 bit int registers in two 32 bit halves, the
   65 // real lower register and a virtual upper half register. upper halves
   66 // are used by the register allocator but are not actually supplied as
   67 // operands to memory ops.
   68 //
   69 // follow the C1 compiler in making registers
   70 //
   71 //   x7, x9-x17, x27-x31 volatile (caller save)
   72 //   x0-x4, x8, x23 system (no save, no allocate)
   73 //   x5-x6 non-allocatable (so we can use them as temporary regs)
   74 
   75 //
   76 // as regards Java usage. we don't use any callee save registers
   77 // because this makes it difficult to de-optimise a frame (see comment
   78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
   79 //
   80 
   81 // General Registers
   82 
   83 reg_def R0      ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()         ); // zr
   84 reg_def R0_H    ( NS,  NS,  Op_RegI, 0,  x0->as_VMReg()->next() );
   85 reg_def R1      ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()         ); // ra
   86 reg_def R1_H    ( NS,  SOC, Op_RegI, 1,  x1->as_VMReg()->next() );
   87 reg_def R2      ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()         ); // sp
   88 reg_def R2_H    ( NS,  SOE, Op_RegI, 2,  x2->as_VMReg()->next() );
   89 reg_def R3      ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()         ); // gp
   90 reg_def R3_H    ( NS,  NS,  Op_RegI, 3,  x3->as_VMReg()->next() );
   91 reg_def R4      ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()         ); // tp
   92 reg_def R4_H    ( NS,  NS,  Op_RegI, 4,  x4->as_VMReg()->next() );
   93 reg_def R7      ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()         );
   94 reg_def R7_H    ( SOC, SOC, Op_RegI, 7,  x7->as_VMReg()->next() );
   95 reg_def R8      ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()         ); // fp
   96 reg_def R8_H    ( NS,  SOE, Op_RegI, 8,  x8->as_VMReg()->next() );
   97 reg_def R9      ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()         );
   98 reg_def R9_H    ( SOC, SOE, Op_RegI, 9,  x9->as_VMReg()->next() );
   99 reg_def R10     ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()        );
  100 reg_def R10_H   ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
  101 reg_def R11     ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()        );
  102 reg_def R11_H   ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
  103 reg_def R12     ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()        );
  104 reg_def R12_H   ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
  105 reg_def R13     ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()        );
  106 reg_def R13_H   ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
  107 reg_def R14     ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()        );
  108 reg_def R14_H   ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
  109 reg_def R15     ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()        );
  110 reg_def R15_H   ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
  111 reg_def R16     ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()        );
  112 reg_def R16_H   ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
  113 reg_def R17     ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()        );
  114 reg_def R17_H   ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
  115 reg_def R18     ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()        );
  116 reg_def R18_H   ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
  117 reg_def R19     ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()        );
  118 reg_def R19_H   ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
  119 reg_def R20     ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()        ); // caller esp
  120 reg_def R20_H   ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
  121 reg_def R21     ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()        );
  122 reg_def R21_H   ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
  123 reg_def R22     ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()        );
  124 reg_def R22_H   ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
  125 reg_def R23     ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()        ); // java thread
  126 reg_def R23_H   ( NS,  SOE, Op_RegI, 23, x23->as_VMReg()->next());
  127 reg_def R24     ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()        );
  128 reg_def R24_H   ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
  129 reg_def R25     ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()        );
  130 reg_def R25_H   ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
  131 reg_def R26     ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()        );
  132 reg_def R26_H   ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
  133 reg_def R27     ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()        ); // heapbase
  134 reg_def R27_H   ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
  135 reg_def R28     ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()        );
  136 reg_def R28_H   ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
  137 reg_def R29     ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()        );
  138 reg_def R29_H   ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
  139 reg_def R30     ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()        );
  140 reg_def R30_H   ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
  141 reg_def R31     ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()        );
  142 reg_def R31_H   ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
  143 
  144 // ----------------------------
  145 // Float/Double Registers
  146 // ----------------------------
  147 
  148 // Double Registers
  149 
  150 // The rules of ADL require that double registers be defined in pairs.
  151 // Each pair must be two 32-bit values, but not necessarily a pair of
  152 // single float registers. In each pair, ADLC-assigned register numbers
  153 // must be adjacent, with the lower number even. Finally, when the
  154 // CPU stores such a register pair to memory, the word associated with
  155 // the lower ADLC-assigned number must be stored to the lower address.
  156 
  157 // RISCV has 32 floating-point registers. Each can store a single
  158 // or double precision floating-point value.
  159 
  160 // for Java use float registers f0-f31 are always save on call whereas
  161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
  162 // float registers are SOC as per the platform spec
  163 
  164 reg_def F0    ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()          );
  165 reg_def F0_H  ( SOC, SOC, Op_RegF,  0,  f0->as_VMReg()->next()  );
  166 reg_def F1    ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()          );
  167 reg_def F1_H  ( SOC, SOC, Op_RegF,  1,  f1->as_VMReg()->next()  );
  168 reg_def F2    ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()          );
  169 reg_def F2_H  ( SOC, SOC, Op_RegF,  2,  f2->as_VMReg()->next()  );
  170 reg_def F3    ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()          );
  171 reg_def F3_H  ( SOC, SOC, Op_RegF,  3,  f3->as_VMReg()->next()  );
  172 reg_def F4    ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()          );
  173 reg_def F4_H  ( SOC, SOC, Op_RegF,  4,  f4->as_VMReg()->next()  );
  174 reg_def F5    ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()          );
  175 reg_def F5_H  ( SOC, SOC, Op_RegF,  5,  f5->as_VMReg()->next()  );
  176 reg_def F6    ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()          );
  177 reg_def F6_H  ( SOC, SOC, Op_RegF,  6,  f6->as_VMReg()->next()  );
  178 reg_def F7    ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()          );
  179 reg_def F7_H  ( SOC, SOC, Op_RegF,  7,  f7->as_VMReg()->next()  );
  180 reg_def F8    ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()          );
  181 reg_def F8_H  ( SOC, SOE, Op_RegF,  8,  f8->as_VMReg()->next()  );
  182 reg_def F9    ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()          );
  183 reg_def F9_H  ( SOC, SOE, Op_RegF,  9,  f9->as_VMReg()->next()  );
  184 reg_def F10   ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()         );
  185 reg_def F10_H ( SOC, SOC, Op_RegF,  10, f10->as_VMReg()->next() );
  186 reg_def F11   ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()         );
  187 reg_def F11_H ( SOC, SOC, Op_RegF,  11, f11->as_VMReg()->next() );
  188 reg_def F12   ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()         );
  189 reg_def F12_H ( SOC, SOC, Op_RegF,  12, f12->as_VMReg()->next() );
  190 reg_def F13   ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()         );
  191 reg_def F13_H ( SOC, SOC, Op_RegF,  13, f13->as_VMReg()->next() );
  192 reg_def F14   ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()         );
  193 reg_def F14_H ( SOC, SOC, Op_RegF,  14, f14->as_VMReg()->next() );
  194 reg_def F15   ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()         );
  195 reg_def F15_H ( SOC, SOC, Op_RegF,  15, f15->as_VMReg()->next() );
  196 reg_def F16   ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()         );
  197 reg_def F16_H ( SOC, SOC, Op_RegF,  16, f16->as_VMReg()->next() );
  198 reg_def F17   ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()         );
  199 reg_def F17_H ( SOC, SOC, Op_RegF,  17, f17->as_VMReg()->next() );
  200 reg_def F18   ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()         );
  201 reg_def F18_H ( SOC, SOE, Op_RegF,  18, f18->as_VMReg()->next() );
  202 reg_def F19   ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()         );
  203 reg_def F19_H ( SOC, SOE, Op_RegF,  19, f19->as_VMReg()->next() );
  204 reg_def F20   ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()         );
  205 reg_def F20_H ( SOC, SOE, Op_RegF,  20, f20->as_VMReg()->next() );
  206 reg_def F21   ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()         );
  207 reg_def F21_H ( SOC, SOE, Op_RegF,  21, f21->as_VMReg()->next() );
  208 reg_def F22   ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()         );
  209 reg_def F22_H ( SOC, SOE, Op_RegF,  22, f22->as_VMReg()->next() );
  210 reg_def F23   ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()         );
  211 reg_def F23_H ( SOC, SOE, Op_RegF,  23, f23->as_VMReg()->next() );
  212 reg_def F24   ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()         );
  213 reg_def F24_H ( SOC, SOE, Op_RegF,  24, f24->as_VMReg()->next() );
  214 reg_def F25   ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()         );
  215 reg_def F25_H ( SOC, SOE, Op_RegF,  25, f25->as_VMReg()->next() );
  216 reg_def F26   ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()         );
  217 reg_def F26_H ( SOC, SOE, Op_RegF,  26, f26->as_VMReg()->next() );
  218 reg_def F27   ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()         );
  219 reg_def F27_H ( SOC, SOE, Op_RegF,  27, f27->as_VMReg()->next() );
  220 reg_def F28   ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()         );
  221 reg_def F28_H ( SOC, SOC, Op_RegF,  28, f28->as_VMReg()->next() );
  222 reg_def F29   ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()         );
  223 reg_def F29_H ( SOC, SOC, Op_RegF,  29, f29->as_VMReg()->next() );
  224 reg_def F30   ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()         );
  225 reg_def F30_H ( SOC, SOC, Op_RegF,  30, f30->as_VMReg()->next() );
  226 reg_def F31   ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()         );
  227 reg_def F31_H ( SOC, SOC, Op_RegF,  31, f31->as_VMReg()->next() );
  228 
  229 // ----------------------------
  230 // Vector Registers
  231 // ----------------------------
  232 
  233 // For RVV vector registers, we simply extend vector register size to 4
  234 // 'logical' slots. This is nominally 128 bits but it actually covers
  235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
  236 // bits. The 'physical' RVV vector register length is detected during
  237 // startup, so the register allocator is able to identify the correct
  238 // number of bytes needed for an RVV spill/unspill.
  239 
  240 reg_def V0    ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()           );
  241 reg_def V0_H  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next()   );
  242 reg_def V0_J  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(2)  );
  243 reg_def V0_K  ( SOC, SOC, Op_VecA, 0,  v0->as_VMReg()->next(3)  );
  244 
  245 reg_def V1    ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg() 	        );
  246 reg_def V1_H  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next()   );
  247 reg_def V1_J  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(2)  );
  248 reg_def V1_K  ( SOC, SOC, Op_VecA, 1,  v1->as_VMReg()->next(3)  );
  249 
  250 reg_def V2    ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()           );
  251 reg_def V2_H  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next()   );
  252 reg_def V2_J  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(2)  );
  253 reg_def V2_K  ( SOC, SOC, Op_VecA, 2,  v2->as_VMReg()->next(3)  );
  254 
  255 reg_def V3    ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()           );
  256 reg_def V3_H  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next()   );
  257 reg_def V3_J  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(2)  );
  258 reg_def V3_K  ( SOC, SOC, Op_VecA, 3,  v3->as_VMReg()->next(3)  );
  259 
  260 reg_def V4    ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()           );
  261 reg_def V4_H  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next()   );
  262 reg_def V4_J  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(2)  );
  263 reg_def V4_K  ( SOC, SOC, Op_VecA, 4,  v4->as_VMReg()->next(3)  );
  264 
  265 reg_def V5    ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg() 	        );
  266 reg_def V5_H  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next()   );
  267 reg_def V5_J  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(2)  );
  268 reg_def V5_K  ( SOC, SOC, Op_VecA, 5,  v5->as_VMReg()->next(3)  );
  269 
  270 reg_def V6    ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()           );
  271 reg_def V6_H  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next()   );
  272 reg_def V6_J  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(2)  );
  273 reg_def V6_K  ( SOC, SOC, Op_VecA, 6,  v6->as_VMReg()->next(3)  );
  274 
  275 reg_def V7    ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg() 	        );
  276 reg_def V7_H  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next()   );
  277 reg_def V7_J  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(2)  );
  278 reg_def V7_K  ( SOC, SOC, Op_VecA, 7,  v7->as_VMReg()->next(3)  );
  279 
  280 reg_def V8    ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()           );
  281 reg_def V8_H  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next()   );
  282 reg_def V8_J  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(2)  );
  283 reg_def V8_K  ( SOC, SOC, Op_VecA, 8,  v8->as_VMReg()->next(3)  );
  284 
  285 reg_def V9    ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()           );
  286 reg_def V9_H  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next()   );
  287 reg_def V9_J  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(2)  );
  288 reg_def V9_K  ( SOC, SOC, Op_VecA, 9,  v9->as_VMReg()->next(3)  );
  289 
  290 reg_def V10   ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()          );
  291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next()  );
  292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
  293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
  294 
  295 reg_def V11   ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()          );
  296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next()  );
  297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
  298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
  299 
  300 reg_def V12   ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()          );
  301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next()  );
  302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
  303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
  304 
  305 reg_def V13   ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()          );
  306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next()  );
  307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
  308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
  309 
  310 reg_def V14   ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()          );
  311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next()  );
  312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
  313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
  314 
  315 reg_def V15   ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()          );
  316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next()  );
  317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
  318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
  319 
  320 reg_def V16   ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()          );
  321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next()  );
  322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
  323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
  324 
  325 reg_def V17   ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()          );
  326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next()  );
  327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
  328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
  329 
  330 reg_def V18   ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()          );
  331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next()  );
  332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
  333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
  334 
  335 reg_def V19   ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()          );
  336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next()  );
  337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
  338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
  339 
  340 reg_def V20   ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()          );
  341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next()  );
  342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
  343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
  344 
  345 reg_def V21   ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()          );
  346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next()  );
  347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
  348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
  349 
  350 reg_def V22   ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()          );
  351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next()  );
  352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
  353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
  354 
  355 reg_def V23   ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()          );
  356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next()  );
  357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
  358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
  359 
  360 reg_def V24   ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()          );
  361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next()  );
  362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
  363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
  364 
  365 reg_def V25   ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()          );
  366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next()  );
  367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
  368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
  369 
  370 reg_def V26   ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()          );
  371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next()  );
  372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
  373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
  374 
  375 reg_def V27   ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()          );
  376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next()  );
  377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
  378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
  379 
  380 reg_def V28   ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()          );
  381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next()  );
  382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
  383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
  384 
  385 reg_def V29   ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()          );
  386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next()  );
  387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
  388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
  389 
  390 reg_def V30   ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()          );
  391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next()  );
  392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
  393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
  394 
  395 reg_def V31   ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()          );
  396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next()  );
  397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
  398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
  399 
  400 // ----------------------------
  401 // Special Registers
  402 // ----------------------------
  403 
  404 // On riscv, the physical flag register is missing, so we use t1 instead,
  405 // to bridge the RegFlag semantics in share/opto
  406 
  407 reg_def RFLAGS   (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg()        );
  408 
  409 // Specify priority of register selection within phases of register
  410 // allocation.  Highest priority is first.  A useful heuristic is to
  411 // give registers a low priority when they are required by machine
  412 // instructions, like EAX and EDX on I486, and choose no-save registers
  413 // before save-on-call, & save-on-call before save-on-entry.  Registers
  414 // which participate in fixed calling sequences should come last.
  415 // Registers which are used as pairs must fall on an even boundary.
  416 
  417 alloc_class chunk0(
  418     // volatiles
  419     R7,  R7_H,
  420     R28, R28_H,
  421     R29, R29_H,
  422     R30, R30_H,
  423     R31, R31_H,
  424 
  425     // arg registers
  426     R10, R10_H,
  427     R11, R11_H,
  428     R12, R12_H,
  429     R13, R13_H,
  430     R14, R14_H,
  431     R15, R15_H,
  432     R16, R16_H,
  433     R17, R17_H,
  434 
  435     // non-volatiles
  436     R9,  R9_H,
  437     R18, R18_H,
  438     R19, R19_H,
  439     R20, R20_H,
  440     R21, R21_H,
  441     R22, R22_H,
  442     R24, R24_H,
  443     R25, R25_H,
  444     R26, R26_H,
  445 
  446     // non-allocatable registers
  447     R23, R23_H, // java thread
  448     R27, R27_H, // heapbase
  449     R4,  R4_H,  // thread
  450     R8,  R8_H,  // fp
  451     R0,  R0_H,  // zero
  452     R1,  R1_H,  // ra
  453     R2,  R2_H,  // sp
  454     R3,  R3_H,  // gp
  455 );
  456 
  457 alloc_class chunk1(
  458 
  459     // no save
  460     F0,  F0_H,
  461     F1,  F1_H,
  462     F2,  F2_H,
  463     F3,  F3_H,
  464     F4,  F4_H,
  465     F5,  F5_H,
  466     F6,  F6_H,
  467     F7,  F7_H,
  468     F28, F28_H,
  469     F29, F29_H,
  470     F30, F30_H,
  471     F31, F31_H,
  472 
  473     // arg registers
  474     F10, F10_H,
  475     F11, F11_H,
  476     F12, F12_H,
  477     F13, F13_H,
  478     F14, F14_H,
  479     F15, F15_H,
  480     F16, F16_H,
  481     F17, F17_H,
  482 
  483     // non-volatiles
  484     F8,  F8_H,
  485     F9,  F9_H,
  486     F18, F18_H,
  487     F19, F19_H,
  488     F20, F20_H,
  489     F21, F21_H,
  490     F22, F22_H,
  491     F23, F23_H,
  492     F24, F24_H,
  493     F25, F25_H,
  494     F26, F26_H,
  495     F27, F27_H,
  496 );
  497 
  498 alloc_class chunk2(
  499     V0, V0_H, V0_J, V0_K,
  500     V1, V1_H, V1_J, V1_K,
  501     V2, V2_H, V2_J, V2_K,
  502     V3, V3_H, V3_J, V3_K,
  503     V4, V4_H, V4_J, V4_K,
  504     V5, V5_H, V5_J, V5_K,
  505     V6, V6_H, V6_J, V6_K,
  506     V7, V7_H, V7_J, V7_K,
  507     V8, V8_H, V8_J, V8_K,
  508     V9, V9_H, V9_J, V9_K,
  509     V10, V10_H, V10_J, V10_K,
  510     V11, V11_H, V11_J, V11_K,
  511     V12, V12_H, V12_J, V12_K,
  512     V13, V13_H, V13_J, V13_K,
  513     V14, V14_H, V14_J, V14_K,
  514     V15, V15_H, V15_J, V15_K,
  515     V16, V16_H, V16_J, V16_K,
  516     V17, V17_H, V17_J, V17_K,
  517     V18, V18_H, V18_J, V18_K,
  518     V19, V19_H, V19_J, V19_K,
  519     V20, V20_H, V20_J, V20_K,
  520     V21, V21_H, V21_J, V21_K,
  521     V22, V22_H, V22_J, V22_K,
  522     V23, V23_H, V23_J, V23_K,
  523     V24, V24_H, V24_J, V24_K,
  524     V25, V25_H, V25_J, V25_K,
  525     V26, V26_H, V26_J, V26_K,
  526     V27, V27_H, V27_J, V27_K,
  527     V28, V28_H, V28_J, V28_K,
  528     V29, V29_H, V29_J, V29_K,
  529     V30, V30_H, V30_J, V30_K,
  530     V31, V31_H, V31_J, V31_K,
  531 );
  532 
  533 alloc_class chunk3(RFLAGS);
  534 
  535 //----------Architecture Description Register Classes--------------------------
  536 // Several register classes are automatically defined based upon information in
  537 // this architecture description.
  538 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  540 //
  541 
  542 // Class for all 32 bit general purpose registers
  543 reg_class all_reg32(
  544     R0,
  545     R1,
  546     R2,
  547     R3,
  548     R4,
  549     R7,
  550     R8,
  551     R9,
  552     R10,
  553     R11,
  554     R12,
  555     R13,
  556     R14,
  557     R15,
  558     R16,
  559     R17,
  560     R18,
  561     R19,
  562     R20,
  563     R21,
  564     R22,
  565     R23,
  566     R24,
  567     R25,
  568     R26,
  569     R27,
  570     R28,
  571     R29,
  572     R30,
  573     R31
  574 );
  575 
  576 // Class for any 32 bit integer registers (excluding zr)
  577 reg_class any_reg32 %{
  578   return _ANY_REG32_mask;
  579 %}
  580 
  581 // Singleton class for R10 int register
  582 reg_class int_r10_reg(R10);
  583 
  584 // Singleton class for R12 int register
  585 reg_class int_r12_reg(R12);
  586 
  587 // Singleton class for R13 int register
  588 reg_class int_r13_reg(R13);
  589 
  590 // Singleton class for R14 int register
  591 reg_class int_r14_reg(R14);
  592 
  593 // Class for all long integer registers
  594 reg_class all_reg(
  595     R0,  R0_H,
  596     R1,  R1_H,
  597     R2,  R2_H,
  598     R3,  R3_H,
  599     R4,  R4_H,
  600     R7,  R7_H,
  601     R8,  R8_H,
  602     R9,  R9_H,
  603     R10, R10_H,
  604     R11, R11_H,
  605     R12, R12_H,
  606     R13, R13_H,
  607     R14, R14_H,
  608     R15, R15_H,
  609     R16, R16_H,
  610     R17, R17_H,
  611     R18, R18_H,
  612     R19, R19_H,
  613     R20, R20_H,
  614     R21, R21_H,
  615     R22, R22_H,
  616     R23, R23_H,
  617     R24, R24_H,
  618     R25, R25_H,
  619     R26, R26_H,
  620     R27, R27_H,
  621     R28, R28_H,
  622     R29, R29_H,
  623     R30, R30_H,
  624     R31, R31_H
  625 );
  626 
  627 // Class for all long integer registers (excluding zr)
  628 reg_class any_reg %{
  629   return _ANY_REG_mask;
  630 %}
  631 
  632 // Class for non-allocatable 32 bit registers
  633 reg_class non_allocatable_reg32(
  634     R0,                       // zr
  635     R1,                       // ra
  636     R2,                       // sp
  637     R3,                       // gp
  638     R4,                       // tp
  639     R23                       // java thread
  640 );
  641 
  642 // Class for non-allocatable 64 bit registers
  643 reg_class non_allocatable_reg(
  644     R0,  R0_H,                // zr
  645     R1,  R1_H,                // ra
  646     R2,  R2_H,                // sp
  647     R3,  R3_H,                // gp
  648     R4,  R4_H,                // tp
  649     R23, R23_H                // java thread
  650 );
  651 
  652 reg_class no_special_reg32 %{
  653   return _NO_SPECIAL_REG32_mask;
  654 %}
  655 
  656 reg_class no_special_reg %{
  657   return _NO_SPECIAL_REG_mask;
  658 %}
  659 
  660 reg_class ptr_reg %{
  661   return _PTR_REG_mask;
  662 %}
  663 
  664 reg_class no_special_ptr_reg %{
  665   return _NO_SPECIAL_PTR_REG_mask;
  666 %}
  667 
  668 // Class for 64 bit register r10
  669 reg_class r10_reg(
  670     R10, R10_H
  671 );
  672 
  673 // Class for 64 bit register r11
  674 reg_class r11_reg(
  675     R11, R11_H
  676 );
  677 
  678 // Class for 64 bit register r12
  679 reg_class r12_reg(
  680     R12, R12_H
  681 );
  682 
  683 // Class for 64 bit register r13
  684 reg_class r13_reg(
  685     R13, R13_H
  686 );
  687 
  688 // Class for 64 bit register r14
  689 reg_class r14_reg(
  690     R14, R14_H
  691 );
  692 
  693 // Class for 64 bit register r15
  694 reg_class r15_reg(
  695     R15, R15_H
  696 );
  697 
  698 // Class for 64 bit register r16
  699 reg_class r16_reg(
  700     R16, R16_H
  701 );
  702 
  703 // Class for method register
  704 reg_class method_reg(
  705     R31, R31_H
  706 );
  707 
  708 // Class for heapbase register
  709 reg_class heapbase_reg(
  710     R27, R27_H
  711 );
  712 
  713 // Class for java thread register
  714 reg_class java_thread_reg(
  715     R23, R23_H
  716 );
  717 
  718 reg_class r28_reg(
  719     R28, R28_H
  720 );
  721 
  722 reg_class r29_reg(
  723     R29, R29_H
  724 );
  725 
  726 reg_class r30_reg(
  727     R30, R30_H
  728 );
  729 
  730 // Class for zero registesr
  731 reg_class zr_reg(
  732     R0, R0_H
  733 );
  734 
  735 // Class for thread register
  736 reg_class thread_reg(
  737     R4, R4_H
  738 );
  739 
  740 // Class for frame pointer register
  741 reg_class fp_reg(
  742     R8, R8_H
  743 );
  744 
  745 // Class for link register
  746 reg_class ra_reg(
  747     R1, R1_H
  748 );
  749 
  750 // Class for long sp register
  751 reg_class sp_reg(
  752     R2, R2_H
  753 );
  754 
  755 // Class for all float registers
  756 reg_class float_reg(
  757     F0,
  758     F1,
  759     F2,
  760     F3,
  761     F4,
  762     F5,
  763     F6,
  764     F7,
  765     F8,
  766     F9,
  767     F10,
  768     F11,
  769     F12,
  770     F13,
  771     F14,
  772     F15,
  773     F16,
  774     F17,
  775     F18,
  776     F19,
  777     F20,
  778     F21,
  779     F22,
  780     F23,
  781     F24,
  782     F25,
  783     F26,
  784     F27,
  785     F28,
  786     F29,
  787     F30,
  788     F31
  789 );
  790 
  791 // Double precision float registers have virtual `high halves' that
  792 // are needed by the allocator.
  793 // Class for all double registers
  794 reg_class double_reg(
  795     F0,  F0_H,
  796     F1,  F1_H,
  797     F2,  F2_H,
  798     F3,  F3_H,
  799     F4,  F4_H,
  800     F5,  F5_H,
  801     F6,  F6_H,
  802     F7,  F7_H,
  803     F8,  F8_H,
  804     F9,  F9_H,
  805     F10, F10_H,
  806     F11, F11_H,
  807     F12, F12_H,
  808     F13, F13_H,
  809     F14, F14_H,
  810     F15, F15_H,
  811     F16, F16_H,
  812     F17, F17_H,
  813     F18, F18_H,
  814     F19, F19_H,
  815     F20, F20_H,
  816     F21, F21_H,
  817     F22, F22_H,
  818     F23, F23_H,
  819     F24, F24_H,
  820     F25, F25_H,
  821     F26, F26_H,
  822     F27, F27_H,
  823     F28, F28_H,
  824     F29, F29_H,
  825     F30, F30_H,
  826     F31, F31_H
  827 );
  828 
  829 // Class for all RVV vector registers
  830 reg_class vectora_reg(
  831     V1, V1_H, V1_J, V1_K,
  832     V2, V2_H, V2_J, V2_K,
  833     V3, V3_H, V3_J, V3_K,
  834     V4, V4_H, V4_J, V4_K,
  835     V5, V5_H, V5_J, V5_K,
  836     V6, V6_H, V6_J, V6_K,
  837     V7, V7_H, V7_J, V7_K,
  838     V8, V8_H, V8_J, V8_K,
  839     V9, V9_H, V9_J, V9_K,
  840     V10, V10_H, V10_J, V10_K,
  841     V11, V11_H, V11_J, V11_K,
  842     V12, V12_H, V12_J, V12_K,
  843     V13, V13_H, V13_J, V13_K,
  844     V14, V14_H, V14_J, V14_K,
  845     V15, V15_H, V15_J, V15_K,
  846     V16, V16_H, V16_J, V16_K,
  847     V17, V17_H, V17_J, V17_K,
  848     V18, V18_H, V18_J, V18_K,
  849     V19, V19_H, V19_J, V19_K,
  850     V20, V20_H, V20_J, V20_K,
  851     V21, V21_H, V21_J, V21_K,
  852     V22, V22_H, V22_J, V22_K,
  853     V23, V23_H, V23_J, V23_K,
  854     V24, V24_H, V24_J, V24_K,
  855     V25, V25_H, V25_J, V25_K,
  856     V26, V26_H, V26_J, V26_K,
  857     V27, V27_H, V27_J, V27_K,
  858     V28, V28_H, V28_J, V28_K,
  859     V29, V29_H, V29_J, V29_K,
  860     V30, V30_H, V30_J, V30_K,
  861     V31, V31_H, V31_J, V31_K
  862 );
  863 
  864 // Class for 64 bit register f0
  865 reg_class f0_reg(
  866     F0, F0_H
  867 );
  868 
  869 // Class for 64 bit register f1
  870 reg_class f1_reg(
  871     F1, F1_H
  872 );
  873 
  874 // Class for 64 bit register f2
  875 reg_class f2_reg(
  876     F2, F2_H
  877 );
  878 
  879 // Class for 64 bit register f3
  880 reg_class f3_reg(
  881     F3, F3_H
  882 );
  883 
  884 // class for vector register v1
  885 reg_class v1_reg(
  886     V1, V1_H, V1_J, V1_K
  887 );
  888 
  889 // class for vector register v2
  890 reg_class v2_reg(
  891     V2, V2_H, V2_J, V2_K
  892 );
  893 
  894 // class for vector register v3
  895 reg_class v3_reg(
  896     V3, V3_H, V3_J, V3_K
  897 );
  898 
  899 // class for vector register v4
  900 reg_class v4_reg(
  901     V4, V4_H, V4_J, V4_K
  902 );
  903 
  904 // class for vector register v5
  905 reg_class v5_reg(
  906     V5, V5_H, V5_J, V5_K
  907 );
  908 
  909 // class for condition codes
  910 reg_class reg_flags(RFLAGS);
  911 %}
  912 
  913 //----------DEFINITION BLOCK---------------------------------------------------
  914 // Define name --> value mappings to inform the ADLC of an integer valued name
  915 // Current support includes integer values in the range [0, 0x7FFFFFFF]
  916 // Format:
  917 //        int_def  <name>         ( <int_value>, <expression>);
  918 // Generated Code in ad_<arch>.hpp
  919 //        #define  <name>   (<expression>)
  920 //        // value == <int_value>
  921 // Generated code in ad_<arch>.cpp adlc_verification()
  922 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  923 //
  924 
  925 // we follow the ppc-aix port in using a simple cost model which ranks
  926 // register operations as cheap, memory ops as more expensive and
  927 // branches as most expensive. the first two have a low as well as a
  928 // normal cost. huge cost appears to be a way of saying don't do
  929 // something
  930 
  931 definitions %{
  932   // The default cost (of a register move instruction).
  933   int_def DEFAULT_COST         (  100,               100);
  934   int_def ALU_COST             (  100,  1 * DEFAULT_COST);          // unknown, const, arith, shift, slt,
  935                                                                     // multi, auipc, nop, logical, move
  936   int_def LOAD_COST            (  300,  3 * DEFAULT_COST);          // load, fpload
  937   int_def STORE_COST           (  100,  1 * DEFAULT_COST);          // store, fpstore
  938   int_def XFER_COST            (  300,  3 * DEFAULT_COST);          // mfc, mtc, fcvt, fmove, fcmp
  939   int_def BRANCH_COST          (  100,  1 * DEFAULT_COST);          // branch, jmp, call
  940   int_def IMUL_COST            ( 1000, 10 * DEFAULT_COST);          // imul
  941   int_def IDIVSI_COST          ( 3400, 34 * DEFAULT_COST);          // idivdi
  942   int_def IDIVDI_COST          ( 6600, 66 * DEFAULT_COST);          // idivsi
  943   int_def FMUL_SINGLE_COST     (  500,  5 * DEFAULT_COST);          // fadd, fmul, fmadd
  944   int_def FMUL_DOUBLE_COST     (  700,  7 * DEFAULT_COST);          // fadd, fmul, fmadd
  945   int_def FDIV_COST            ( 2000, 20 * DEFAULT_COST);          // fdiv
  946   int_def FSQRT_COST           ( 2500, 25 * DEFAULT_COST);          // fsqrt
  947   int_def VOLATILE_REF_COST    ( 1000, 10 * DEFAULT_COST);
  948 %}
  949 
  950 
  951 
  952 //----------SOURCE BLOCK-------------------------------------------------------
  953 // This is a block of C++ code which provides values, functions, and
  954 // definitions necessary in the rest of the architecture description
  955 
  956 source_hpp %{
  957 
  958 #include "asm/macroAssembler.hpp"
  959 #include "gc/shared/cardTable.hpp"
  960 #include "gc/shared/cardTableBarrierSet.hpp"
  961 #include "gc/shared/collectedHeap.hpp"
  962 #include "opto/addnode.hpp"
  963 #include "opto/convertnode.hpp"
  964 
  965 extern RegMask _ANY_REG32_mask;
  966 extern RegMask _ANY_REG_mask;
  967 extern RegMask _PTR_REG_mask;
  968 extern RegMask _NO_SPECIAL_REG32_mask;
  969 extern RegMask _NO_SPECIAL_REG_mask;
  970 extern RegMask _NO_SPECIAL_PTR_REG_mask;
  971 
  972 class CallStubImpl {
  973 
  974   //--------------------------------------------------------------
  975   //---<  Used for optimization in Compile::shorten_branches  >---
  976   //--------------------------------------------------------------
  977 
  978  public:
  979   // Size of call trampoline stub.
  980   static uint size_call_trampoline() {
  981     return 0; // no call trampolines on this platform
  982   }
  983 
  984   // number of relocations needed by a call trampoline stub
  985   static uint reloc_call_trampoline() {
  986     return 0; // no call trampolines on this platform
  987   }
  988 };
  989 
  990 class HandlerImpl {
  991 
  992  public:
  993 
  994   static int emit_exception_handler(CodeBuffer &cbuf);
  995   static int emit_deopt_handler(CodeBuffer& cbuf);
  996 
  997   static uint size_exception_handler() {
  998     return MacroAssembler::far_branch_size();
  999   }
 1000 
 1001   static uint size_deopt_handler() {
 1002     // count auipc + far branch
 1003     return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
 1004   }
 1005 };
 1006 
 1007 class Node::PD {
 1008 public:
 1009   enum NodeFlags {
 1010     _last_flag = Node::_last_flag
 1011   };
 1012 };
 1013 
 1014 bool is_CAS(int opcode, bool maybe_volatile);
 1015 
 1016 // predicate controlling translation of CompareAndSwapX
 1017 bool needs_acquiring_load_reserved(const Node *load);
 1018 
 1019 // predicate controlling addressing modes
 1020 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
 1021 %}
 1022 
 1023 source %{
 1024 
 1025 // Derived RegMask with conditionally allocatable registers
 1026 
 1027 RegMask _ANY_REG32_mask;
 1028 RegMask _ANY_REG_mask;
 1029 RegMask _PTR_REG_mask;
 1030 RegMask _NO_SPECIAL_REG32_mask;
 1031 RegMask _NO_SPECIAL_REG_mask;
 1032 RegMask _NO_SPECIAL_PTR_REG_mask;
 1033 
 1034 void reg_mask_init() {
 1035 
 1036   _ANY_REG32_mask = _ALL_REG32_mask;
 1037   _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
 1038 
 1039   _ANY_REG_mask = _ALL_REG_mask;
 1040   _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
 1041 
 1042   _PTR_REG_mask = _ALL_REG_mask;
 1043   _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
 1044 
 1045   _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
 1046   _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
 1047 
 1048   _NO_SPECIAL_REG_mask = _ALL_REG_mask;
 1049   _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1050 
 1051   _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
 1052   _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
 1053 
 1054   // x27 is not allocatable when compressed oops is on
 1055   if (UseCompressedOops) {
 1056     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
 1057     _NO_SPECIAL_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1058     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_HEAPBASE_REG_mask);
 1059   }
 1060 
 1061   // x8 is not allocatable when PreserveFramePointer is on
 1062   if (PreserveFramePointer) {
 1063     _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
 1064     _NO_SPECIAL_REG_mask.SUBTRACT(_FP_REG_mask);
 1065     _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_FP_REG_mask);
 1066   }
 1067 }
 1068 
 1069 void PhaseOutput::pd_perform_mach_node_analysis() {
 1070 }
 1071 
 1072 int MachNode::pd_alignment_required() const {
 1073   return 1;
 1074 }
 1075 
 1076 int MachNode::compute_padding(int current_offset) const {
 1077   return 0;
 1078 }
 1079 
 1080 // is_CAS(int opcode, bool maybe_volatile)
 1081 //
 1082 // return true if opcode is one of the possible CompareAndSwapX
 1083 // values otherwise false.
 1084 bool is_CAS(int opcode, bool maybe_volatile)
 1085 {
 1086   switch (opcode) {
 1087     // We handle these
 1088     case Op_CompareAndSwapI:
 1089     case Op_CompareAndSwapL:
 1090     case Op_CompareAndSwapP:
 1091     case Op_CompareAndSwapN:
 1092     case Op_ShenandoahCompareAndSwapP:
 1093     case Op_ShenandoahCompareAndSwapN:
 1094     case Op_CompareAndSwapB:
 1095     case Op_CompareAndSwapS:
 1096     case Op_GetAndSetI:
 1097     case Op_GetAndSetL:
 1098     case Op_GetAndSetP:
 1099     case Op_GetAndSetN:
 1100     case Op_GetAndAddI:
 1101     case Op_GetAndAddL:
 1102       return true;
 1103     case Op_CompareAndExchangeI:
 1104     case Op_CompareAndExchangeN:
 1105     case Op_CompareAndExchangeB:
 1106     case Op_CompareAndExchangeS:
 1107     case Op_CompareAndExchangeL:
 1108     case Op_CompareAndExchangeP:
 1109     case Op_WeakCompareAndSwapB:
 1110     case Op_WeakCompareAndSwapS:
 1111     case Op_WeakCompareAndSwapI:
 1112     case Op_WeakCompareAndSwapL:
 1113     case Op_WeakCompareAndSwapP:
 1114     case Op_WeakCompareAndSwapN:
 1115     case Op_ShenandoahWeakCompareAndSwapP:
 1116     case Op_ShenandoahWeakCompareAndSwapN:
 1117     case Op_ShenandoahCompareAndExchangeP:
 1118     case Op_ShenandoahCompareAndExchangeN:
 1119       return maybe_volatile;
 1120     default:
 1121       return false;
 1122   }
 1123 }
 1124 
 1125 // predicate controlling translation of CAS
 1126 //
 1127 // returns true if CAS needs to use an acquiring load otherwise false
 1128 bool needs_acquiring_load_reserved(const Node *n)
 1129 {
 1130   assert(n != NULL && is_CAS(n->Opcode(), true), "expecting a compare and swap");
 1131 
 1132   LoadStoreNode* ldst = n->as_LoadStore();
 1133   if (n != NULL && is_CAS(n->Opcode(), false)) {
 1134     assert(ldst != NULL && ldst->trailing_membar() != NULL, "expected trailing membar");
 1135   } else {
 1136     return ldst != NULL && ldst->trailing_membar() != NULL;
 1137   }
 1138   // so we can just return true here
 1139   return true;
 1140 }
 1141 #define __ _masm.
 1142 
 1143 // advance declarations for helper functions to convert register
 1144 // indices to register objects
 1145 
 1146 // the ad file has to provide implementations of certain methods
 1147 // expected by the generic code
 1148 //
 1149 // REQUIRED FUNCTIONALITY
 1150 
 1151 //=============================================================================
 1152 
 1153 // !!!!! Special hack to get all types of calls to specify the byte offset
 1154 //       from the start of the call to the point where the return address
 1155 //       will point.
 1156 
 1157 int MachCallStaticJavaNode::ret_addr_offset()
 1158 {
 1159   // jal
 1160   return 1 * NativeInstruction::instruction_size;
 1161 }
 1162 
 1163 int MachCallDynamicJavaNode::ret_addr_offset()
 1164 {
 1165   return 7 * NativeInstruction::instruction_size; // movptr, jal
 1166 }
 1167 
 1168 int MachCallRuntimeNode::ret_addr_offset() {
 1169   // for generated stubs the call will be
 1170   //   jal(addr)
 1171   // or with far branches
 1172   //   jal(trampoline_stub)
 1173   // for real runtime callouts it will be 11 instructions
 1174   // see riscv_enc_java_to_runtime
 1175   //   la(t1, retaddr)                ->  auipc + addi
 1176   //   la(t0, RuntimeAddress(addr))   ->  lui + addi + slli + addi + slli + addi
 1177   //   addi(sp, sp, -2 * wordSize)    ->  addi
 1178   //   sd(t1, Address(sp, wordSize))  ->  sd
 1179   //   jalr(t0)                       ->  jalr
 1180   CodeBlob *cb = CodeCache::find_blob(_entry_point);
 1181   if (cb != NULL) {
 1182     return 1 * NativeInstruction::instruction_size;
 1183   } else {
 1184     return 11 * NativeInstruction::instruction_size;
 1185   }
 1186 }
 1187 
 1188 int MachCallNativeNode::ret_addr_offset() {
 1189   Unimplemented();
 1190   return -1;
 1191 }
 1192 
 1193 //
 1194 // Compute padding required for nodes which need alignment
 1195 //
 1196 
 1197 // With RVC a call instruction may get 2-byte aligned.
 1198 // The address of the call instruction needs to be 4-byte aligned to
 1199 // ensure that it does not span a cache line so that it can be patched.
 1200 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 1201 {
 1202   // to make sure the address of jal 4-byte aligned.
 1203   return align_up(current_offset, alignment_required()) - current_offset;
 1204 }
 1205 
 1206 // With RVC a call instruction may get 2-byte aligned.
 1207 // The address of the call instruction needs to be 4-byte aligned to
 1208 // ensure that it does not span a cache line so that it can be patched.
 1209 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 1210 {
 1211   // skip the movptr in MacroAssembler::ic_call():
 1212   // lui + addi + slli + addi + slli + addi
 1213   // Though movptr() has already 4-byte aligned with or without RVC,
 1214   // We need to prevent from further changes by explicitly calculating the size.
 1215   const int movptr_size = 6 * NativeInstruction::instruction_size;
 1216   current_offset += movptr_size;
 1217   // to make sure the address of jal 4-byte aligned.
 1218   return align_up(current_offset, alignment_required()) - current_offset;
 1219 }
 1220 
 1221 //=============================================================================
 1222 
 1223 #ifndef PRODUCT
 1224 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1225   assert_cond(st != NULL);
 1226   st->print("BREAKPOINT");
 1227 }
 1228 #endif
 1229 
 1230 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1231   C2_MacroAssembler _masm(&cbuf);
 1232   Assembler::CompressibleRegion cr(&_masm);
 1233   __ ebreak();
 1234 }
 1235 
 1236 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 1237   return MachNode::size(ra_);
 1238 }
 1239 
 1240 //=============================================================================
 1241 
 1242 #ifndef PRODUCT
 1243   void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
 1244     st->print("nop \t# %d bytes pad for loops and calls", _count);
 1245   }
 1246 #endif
 1247 
 1248   void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
 1249     C2_MacroAssembler _masm(&cbuf);
 1250     Assembler::CompressibleRegion cr(&_masm); // nops shall be 2-byte under RVC for alignment purposes.
 1251     for (int i = 0; i < _count; i++) {
 1252       __ nop();
 1253     }
 1254   }
 1255 
 1256   uint MachNopNode::size(PhaseRegAlloc*) const {
 1257     return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
 1258   }
 1259 
 1260 //=============================================================================
 1261 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 1262 
 1263 int ConstantTable::calculate_table_base_offset() const {
 1264   return 0;  // absolute addressing, no offset
 1265 }
 1266 
 1267 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 1268 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 1269   ShouldNotReachHere();
 1270 }
 1271 
 1272 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 1273   // Empty encoding
 1274 }
 1275 
 1276 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 1277   return 0;
 1278 }
 1279 
 1280 #ifndef PRODUCT
 1281 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 1282   assert_cond(st != NULL);
 1283   st->print("-- \t// MachConstantBaseNode (empty encoding)");
 1284 }
 1285 #endif
 1286 
 1287 #ifndef PRODUCT
 1288 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1289   assert_cond(st != NULL && ra_ != NULL);
 1290   Compile* C = ra_->C;
 1291 
 1292   int framesize = C->output()->frame_slots() << LogBytesPerInt;
 1293 
 1294   if (C->output()->need_stack_bang(framesize)) {
 1295     st->print("# stack bang size=%d\n\t", framesize);
 1296   }
 1297 
 1298   st->print("sd  fp, [sp, #%d]\n\t", - 2 * wordSize);
 1299   st->print("sd  ra, [sp, #%d]\n\t", - wordSize);
 1300   if (PreserveFramePointer) { st->print("sub  fp, sp, #%d\n\t", 2 * wordSize); }
 1301   st->print("sub sp, sp, #%d\n\t", framesize);
 1302 
 1303   if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
 1304     st->print("ld  t0, [guard]\n\t");
 1305     st->print("membar LoadLoad\n\t");
 1306     st->print("ld  t1, [xthread, #thread_disarmed_offset]\n\t");
 1307     st->print("beq t0, t1, skip\n\t");
 1308     st->print("jalr #nmethod_entry_barrier_stub\n\t");
 1309     st->print("j skip\n\t");
 1310     st->print("guard: int\n\t");
 1311     st->print("skip:\n\t");
 1312   }
 1313 }
 1314 #endif
 1315 
 1316 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1317   assert_cond(ra_ != NULL);
 1318   Compile* C = ra_->C;
 1319   C2_MacroAssembler _masm(&cbuf);
 1320 
 1321   // n.b. frame size includes space for return pc and fp
 1322   const int framesize = C->output()->frame_size_in_bytes();
 1323 
 1324   // insert a nop at the start of the prolog so we can patch in a
 1325   // branch if we need to invalidate the method later
 1326   __ nop();
 1327 
 1328   assert_cond(C != NULL);
 1329 
 1330   if (C->clinit_barrier_on_entry()) {
 1331     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 1332 
 1333     Label L_skip_barrier;
 1334 
 1335     __ mov_metadata(t1, C->method()->holder()->constant_encoding());
 1336     __ clinit_barrier(t1, t0, &L_skip_barrier);
 1337     __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 1338     __ bind(L_skip_barrier);
 1339   }
 1340 
 1341   int bangsize = C->output()->bang_size_in_bytes();
 1342   if (C->output()->need_stack_bang(bangsize)) {
 1343     __ generate_stack_overflow_check(bangsize);
 1344   }
 1345 
 1346   __ build_frame(framesize);
 1347 
 1348   if (C->stub_function() == NULL) {
 1349     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 1350     bs->nmethod_entry_barrier(&_masm);
 1351   }
 1352 
 1353   if (VerifyStackAtCalls) {
 1354     Unimplemented();
 1355   }
 1356 
 1357   C->output()->set_frame_complete(cbuf.insts_size());
 1358 
 1359   if (C->has_mach_constant_base_node()) {
 1360     // NOTE: We set the table base offset here because users might be
 1361     // emitted before MachConstantBaseNode.
 1362     ConstantTable& constant_table = C->output()->constant_table();
 1363     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 1364   }
 1365 }
 1366 
 1367 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 1368 {
 1369   assert_cond(ra_ != NULL);
 1370   return MachNode::size(ra_); // too many variables; just compute it
 1371                               // the hard way
 1372 }
 1373 
 1374 int MachPrologNode::reloc() const
 1375 {
 1376   return 0;
 1377 }
 1378 
 1379 //=============================================================================
 1380 
 1381 #ifndef PRODUCT
 1382 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1383   assert_cond(st != NULL && ra_ != NULL);
 1384   Compile* C = ra_->C;
 1385   assert_cond(C != NULL);
 1386   int framesize = C->output()->frame_size_in_bytes();
 1387 
 1388   st->print("# pop frame %d\n\t", framesize);
 1389 
 1390   if (framesize == 0) {
 1391     st->print("ld  ra, [sp,#%d]\n\t", (2 * wordSize));
 1392     st->print("ld  fp, [sp,#%d]\n\t", (3 * wordSize));
 1393     st->print("add sp, sp, #%d\n\t", (2 * wordSize));
 1394   } else {
 1395     st->print("add  sp, sp, #%d\n\t", framesize);
 1396     st->print("ld  ra, [sp,#%d]\n\t", - 2 * wordSize);
 1397     st->print("ld  fp, [sp,#%d]\n\t", - wordSize);
 1398   }
 1399 
 1400   if (do_polling() && C->is_method_compilation()) {
 1401     st->print("# test polling word\n\t");
 1402     st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
 1403     st->print("bgtu sp, t0, #slow_path");
 1404   }
 1405 }
 1406 #endif
 1407 
 1408 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1409   assert_cond(ra_ != NULL);
 1410   Compile* C = ra_->C;
 1411   C2_MacroAssembler _masm(&cbuf);
 1412   assert_cond(C != NULL);
 1413   int framesize = C->output()->frame_size_in_bytes();
 1414 
 1415   __ remove_frame(framesize);
 1416 
 1417   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 1418     __ reserved_stack_check();
 1419   }
 1420 
 1421   if (do_polling() && C->is_method_compilation()) {
 1422     Label dummy_label;
 1423     Label* code_stub = &dummy_label;
 1424     if (!C->output()->in_scratch_emit_size()) {
 1425       code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
 1426     }
 1427     __ relocate(relocInfo::poll_return_type);
 1428     __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
 1429   }
 1430 }
 1431 
 1432 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 1433   assert_cond(ra_ != NULL);
 1434   // Variable size. Determine dynamically.
 1435   return MachNode::size(ra_);
 1436 }
 1437 
 1438 int MachEpilogNode::reloc() const {
 1439   // Return number of relocatable values contained in this instruction.
 1440   return 1; // 1 for polling page.
 1441 }
 1442 const Pipeline * MachEpilogNode::pipeline() const {
 1443   return MachNode::pipeline_class();
 1444 }
 1445 
 1446 //=============================================================================
 1447 
 1448 // Figure out which register class each belongs in: rc_int, rc_float or
 1449 // rc_stack.
 1450 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
 1451 
 1452 static enum RC rc_class(OptoReg::Name reg) {
 1453 
 1454   if (reg == OptoReg::Bad) {
 1455     return rc_bad;
 1456   }
 1457 
 1458   // we have 30 int registers * 2 halves
 1459   // (t0 and t1 are omitted)
 1460   int slots_of_int_registers = RegisterImpl::max_slots_per_register * (RegisterImpl::number_of_registers - 2);
 1461   if (reg < slots_of_int_registers) {
 1462     return rc_int;
 1463   }
 1464 
 1465   // we have 32 float register * 2 halves
 1466   int slots_of_float_registers = FloatRegisterImpl::max_slots_per_register * FloatRegisterImpl::number_of_registers;
 1467   if (reg < slots_of_int_registers + slots_of_float_registers) {
 1468     return rc_float;
 1469   }
 1470 
 1471   // we have 32 vector register * 4 halves
 1472   int slots_of_vector_registers = VectorRegisterImpl::max_slots_per_register * VectorRegisterImpl::number_of_registers;
 1473   if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
 1474     return rc_vector;
 1475   }
 1476 
 1477   // Between vector regs & stack is the flags regs.
 1478   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
 1479 
 1480   return rc_stack;
 1481 }
 1482 
 1483 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
 1484   assert_cond(ra_ != NULL);
 1485   Compile* C = ra_->C;
 1486 
 1487   // Get registers to move.
 1488   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1489   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1490   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1491   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1492 
 1493   enum RC src_hi_rc = rc_class(src_hi);
 1494   enum RC src_lo_rc = rc_class(src_lo);
 1495   enum RC dst_hi_rc = rc_class(dst_hi);
 1496   enum RC dst_lo_rc = rc_class(dst_lo);
 1497 
 1498   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1499 
 1500   if (src_hi != OptoReg::Bad) {
 1501     assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1502            (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
 1503            "expected aligned-adjacent pairs");
 1504   }
 1505 
 1506   if (src_lo == dst_lo && src_hi == dst_hi) {
 1507     return 0;            // Self copy, no move.
 1508   }
 1509 
 1510   bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
 1511               (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
 1512   int src_offset = ra_->reg2offset(src_lo);
 1513   int dst_offset = ra_->reg2offset(dst_lo);
 1514 
 1515   if (bottom_type()->isa_vect() != NULL) {
 1516     uint ireg = ideal_reg();
 1517     if (ireg == Op_VecA && cbuf) {
 1518       C2_MacroAssembler _masm(cbuf);
 1519       Assembler::CompressibleRegion cr(&_masm);
 1520       int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 1521       if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1522         // stack to stack
 1523         __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
 1524                                             vector_reg_size_in_bytes);
 1525       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
 1526         // vpr to stack
 1527         __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
 1528       } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
 1529         // stack to vpr
 1530         __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
 1531       } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
 1532         // vpr to vpr
 1533         __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
 1534       } else {
 1535         ShouldNotReachHere();
 1536       }
 1537     }
 1538   } else if (cbuf != NULL) {
 1539     C2_MacroAssembler _masm(cbuf);
 1540     Assembler::CompressibleRegion cr(&_masm);
 1541     switch (src_lo_rc) {
 1542       case rc_int:
 1543         if (dst_lo_rc == rc_int) {  // gpr --> gpr copy
 1544           if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
 1545             __ zero_extend(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
 1546           } else {
 1547             __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
 1548           }
 1549         } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
 1550           if (is64) {
 1551             __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1552                        as_Register(Matcher::_regEncode[src_lo]));
 1553           } else {
 1554             __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1555                        as_Register(Matcher::_regEncode[src_lo]));
 1556           }
 1557         } else {                    // gpr --> stack spill
 1558           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1559           __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
 1560         }
 1561         break;
 1562       case rc_float:
 1563         if (dst_lo_rc == rc_int) {  // fpr --> gpr copy
 1564           if (is64) {
 1565             __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
 1566                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1567           } else {
 1568             __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
 1569                        as_FloatRegister(Matcher::_regEncode[src_lo]));
 1570           }
 1571         } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
 1572           if (is64) {
 1573             __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1574                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1575           } else {
 1576             __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1577                      as_FloatRegister(Matcher::_regEncode[src_lo]));
 1578           }
 1579         } else {                    // fpr --> stack spill
 1580           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1581           __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
 1582                    is64, dst_offset);
 1583         }
 1584         break;
 1585       case rc_stack:
 1586         if (dst_lo_rc == rc_int) {  // stack --> gpr load
 1587           if (this->ideal_reg() == Op_RegI) {
 1588             __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1589           } else { // // zero extended for narrow oop or klass
 1590             __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
 1591           }
 1592         } else if (dst_lo_rc == rc_float) { // stack --> fpr load
 1593           __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
 1594                      is64, src_offset);
 1595         } else {                    // stack --> stack copy
 1596           assert(dst_lo_rc == rc_stack, "spill to bad register class");
 1597           if (this->ideal_reg() == Op_RegI) {
 1598             __ unspill(t0, is64, src_offset);
 1599           } else { // zero extended for narrow oop or klass
 1600             __ unspillu(t0, is64, src_offset);
 1601           }
 1602           __ spill(t0, is64, dst_offset);
 1603         }
 1604         break;
 1605       default:
 1606         ShouldNotReachHere();
 1607     }
 1608   }
 1609 
 1610   if (st != NULL) {
 1611     st->print("spill ");
 1612     if (src_lo_rc == rc_stack) {
 1613       st->print("[sp, #%d] -> ", src_offset);
 1614     } else {
 1615       st->print("%s -> ", Matcher::regName[src_lo]);
 1616     }
 1617     if (dst_lo_rc == rc_stack) {
 1618       st->print("[sp, #%d]", dst_offset);
 1619     } else {
 1620       st->print("%s", Matcher::regName[dst_lo]);
 1621     }
 1622     if (bottom_type()->isa_vect() != NULL) {
 1623       int vsize = 0;
 1624       if (ideal_reg() == Op_VecA) {
 1625         vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
 1626       } else {
 1627         ShouldNotReachHere();
 1628       }
 1629       st->print("\t# vector spill size = %d", vsize);
 1630     } else {
 1631       st->print("\t# spill size = %d", is64 ? 64 : 32);
 1632     }
 1633   }
 1634 
 1635   return 0;
 1636 }
 1637 
 1638 #ifndef PRODUCT
 1639 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1640   if (ra_ == NULL) {
 1641     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
 1642   } else {
 1643     implementation(NULL, ra_, false, st);
 1644   }
 1645 }
 1646 #endif
 1647 
 1648 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1649   implementation(&cbuf, ra_, false, NULL);
 1650 }
 1651 
 1652 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1653   return MachNode::size(ra_);
 1654 }
 1655 
 1656 //=============================================================================
 1657 
 1658 #ifndef PRODUCT
 1659 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 1660   assert_cond(ra_ != NULL && st != NULL);
 1661   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1662   int reg = ra_->get_reg_first(this);
 1663   st->print("add %s, sp, #%d\t# box lock",
 1664             Matcher::regName[reg], offset);
 1665 }
 1666 #endif
 1667 
 1668 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1669   C2_MacroAssembler _masm(&cbuf);
 1670 
 1671   assert_cond(ra_ != NULL);
 1672   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1673   int reg    = ra_->get_encode(this);
 1674 
 1675   if (is_imm_in_range(offset, 12, 0)) {
 1676     __ addi(as_Register(reg), sp, offset);
 1677   } else if (is_imm_in_range(offset, 32, 0)) {
 1678     __ li32(t0, offset);
 1679     __ add(as_Register(reg), sp, t0);
 1680   } else {
 1681     ShouldNotReachHere();
 1682   }
 1683 }
 1684 
 1685 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1686   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
 1687   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1688 
 1689   if (is_imm_in_range(offset, 12, 0)) {
 1690     return NativeInstruction::instruction_size;
 1691   } else {
 1692     return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
 1693   }
 1694 }
 1695 
 1696 //=============================================================================
 1697 
 1698 #ifndef PRODUCT
 1699 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1700 {
 1701   assert_cond(st != NULL);
 1702   st->print_cr("# MachUEPNode");
 1703   if (UseCompressedClassPointers) {
 1704     st->print_cr("\tlwu t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1705     if (CompressedKlassPointers::shift() != 0) {
 1706       st->print_cr("\tdecode_klass_not_null t0, t0");
 1707     }
 1708   } else {
 1709     st->print_cr("\tld t0, [j_rarg0, oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1710   }
 1711   st->print_cr("\tbeq t0, t1, ic_hit");
 1712   st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
 1713   st->print_cr("\tic_hit:");
 1714 }
 1715 #endif
 1716 
 1717 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1718 {
 1719   // This is the unverified entry point.
 1720   C2_MacroAssembler _masm(&cbuf);
 1721 
 1722   Label skip;
 1723   __ cmp_klass(j_rarg0, t1, t0, skip);
 1724   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 1725   __ bind(skip);
 1726 }
 1727 
 1728 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1729 {
 1730   assert_cond(ra_ != NULL);
 1731   return MachNode::size(ra_);
 1732 }
 1733 
 1734 // REQUIRED EMIT CODE
 1735 
 1736 //=============================================================================
 1737 
 1738 // Emit exception handler code.
 1739 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf)
 1740 {
 1741   // la_patchable t0, #exception_blob_entry_point
 1742   // jr (offset)t0
 1743   // or
 1744   // j #exception_blob_entry_point
 1745   // Note that the code buffer's insts_mark is always relative to insts.
 1746   // That's why we must use the macroassembler to generate a handler.
 1747   C2_MacroAssembler _masm(&cbuf);
 1748   address base = __ start_a_stub(size_exception_handler());
 1749   if (base == NULL) {
 1750     ciEnv::current()->record_failure("CodeCache is full");
 1751     return 0;  // CodeBuffer::expand failed
 1752   }
 1753   int offset = __ offset();
 1754   __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
 1755   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1756   __ end_a_stub();
 1757   return offset;
 1758 }
 1759 
 1760 // Emit deopt handler code.
 1761 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)
 1762 {
 1763   // Note that the code buffer's insts_mark is always relative to insts.
 1764   // That's why we must use the macroassembler to generate a handler.
 1765   C2_MacroAssembler _masm(&cbuf);
 1766   address base = __ start_a_stub(size_deopt_handler());
 1767   if (base == NULL) {
 1768     ciEnv::current()->record_failure("CodeCache is full");
 1769     return 0;  // CodeBuffer::expand failed
 1770   }
 1771   int offset = __ offset();
 1772 
 1773   __ auipc(ra, 0);
 1774   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 1775 
 1776   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
 1777   __ end_a_stub();
 1778   return offset;
 1779 
 1780 }
 1781 // REQUIRED MATCHER CODE
 1782 
 1783 //=============================================================================
 1784 
 1785 const bool Matcher::match_rule_supported(int opcode) {
 1786   if (!has_match_rule(opcode)) {
 1787     return false;
 1788   }
 1789 
 1790   switch (opcode) {
 1791     case Op_CacheWB:           // fall through
 1792     case Op_CacheWBPreSync:    // fall through
 1793     case Op_CacheWBPostSync:
 1794       if (!VM_Version::supports_data_cache_line_flush()) {
 1795         return false;
 1796       }
 1797       break;
 1798 
 1799     case Op_StrCompressedCopy: // fall through
 1800     case Op_StrInflatedCopy:   // fall through
 1801     case Op_CountPositives:
 1802       return UseRVV;
 1803 
 1804     case Op_EncodeISOArray:
 1805       return UseRVV && SpecialEncodeISOArray;
 1806 
 1807     case Op_PopCountI:
 1808     case Op_PopCountL:
 1809       return UsePopCountInstruction;
 1810 
 1811     case Op_RotateRight:
 1812     case Op_RotateLeft:
 1813     case Op_CountLeadingZerosI:
 1814     case Op_CountLeadingZerosL:
 1815     case Op_CountTrailingZerosI:
 1816     case Op_CountTrailingZerosL:
 1817       return UseRVB;
 1818   }
 1819 
 1820   return true; // Per default match rules are supported.
 1821 }
 1822 
 1823 // Identify extra cases that we might want to provide match rules for vector nodes and
 1824 // other intrinsics guarded with vector length (vlen) and element type (bt).
 1825 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
 1826   if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
 1827     return false;
 1828   }
 1829 
 1830   return op_vec_supported(opcode);
 1831 }
 1832 
 1833 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
 1834   return false;
 1835 }
 1836 
 1837 const RegMask* Matcher::predicate_reg_mask(void) {
 1838   return NULL;
 1839 }
 1840 
 1841 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
 1842   return NULL;
 1843 }
 1844 
 1845 // Vector calling convention not yet implemented.
 1846 const bool Matcher::supports_vector_calling_convention(void) {
 1847   return false;
 1848 }
 1849 
 1850 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1851   Unimplemented();
 1852   return OptoRegPair(0, 0);
 1853 }
 1854 
 1855 // Is this branch offset short enough that a short branch can be used?
 1856 //
 1857 // NOTE: If the platform does not provide any short branch variants, then
 1858 //       this method should return false for offset 0.
 1859 // |---label(L1)-----|
 1860 // |-----------------|
 1861 // |-----------------|----------eq: float-------------------
 1862 // |-----------------| // far_cmpD_branch   |   cmpD_branch
 1863 // |------- ---------|    feq;              |      feq;
 1864 // |-far_cmpD_branch-|    beqz done;        |      bnez L;
 1865 // |-----------------|    j L;              |
 1866 // |-----------------|    bind(done);       |
 1867 // |-----------------|--------------------------------------
 1868 // |-----------------| // so shortBrSize = br_size - 4;
 1869 // |-----------------| // so offs = offset - shortBrSize + 4;
 1870 // |---label(L2)-----|
 1871 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1872   // The passed offset is relative to address of the branch.
 1873   int shortBrSize = br_size - 4;
 1874   int offs = offset - shortBrSize + 4;
 1875   return (-4096 <= offs && offs < 4096);
 1876 }
 1877 
 1878 // Vector width in bytes.
 1879 const int Matcher::vector_width_in_bytes(BasicType bt) {
 1880   if (UseRVV) {
 1881     // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
 1882     // MaxVectorSize == VM_Version::_initial_vector_length
 1883     return MaxVectorSize;
 1884   }
 1885   return 0;
 1886 }
 1887 
 1888 // Limits on vector size (number of elements) loaded into vector.
 1889 const int Matcher::max_vector_size(const BasicType bt) {
 1890   return vector_width_in_bytes(bt) / type2aelembytes(bt);
 1891 }
 1892 const int Matcher::min_vector_size(const BasicType bt) {
 1893   return max_vector_size(bt);
 1894 }
 1895 
 1896 // Vector ideal reg.
 1897 const uint Matcher::vector_ideal_reg(int len) {
 1898   assert(MaxVectorSize >= len, "");
 1899   if (UseRVV) {
 1900     return Op_VecA;
 1901   }
 1902 
 1903   ShouldNotReachHere();
 1904   return 0;
 1905 }
 1906 
 1907 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
 1908   return Matcher::max_vector_size(bt);
 1909 }
 1910 
 1911 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 1912   ShouldNotReachHere(); // generic vector operands not supported
 1913   return NULL;
 1914 }
 1915 
 1916 bool Matcher::is_reg2reg_move(MachNode* m) {
 1917   ShouldNotReachHere(); // generic vector operands not supported
 1918   return false;
 1919 }
 1920 
 1921 bool Matcher::is_generic_vector(MachOper* opnd) {
 1922   ShouldNotReachHere(); // generic vector operands not supported
 1923   return false;
 1924 }
 1925 
 1926 // Return whether or not this register is ever used as an argument.
 1927 // This function is used on startup to build the trampoline stubs in
 1928 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1929 // call in the trampoline, and arguments in those registers not be
 1930 // available to the callee.
 1931 bool Matcher::can_be_java_arg(int reg)
 1932 {
 1933   return
 1934     reg ==  R10_num || reg == R10_H_num ||
 1935     reg ==  R11_num || reg == R11_H_num ||
 1936     reg ==  R12_num || reg == R12_H_num ||
 1937     reg ==  R13_num || reg == R13_H_num ||
 1938     reg ==  R14_num || reg == R14_H_num ||
 1939     reg ==  R15_num || reg == R15_H_num ||
 1940     reg ==  R16_num || reg == R16_H_num ||
 1941     reg ==  R17_num || reg == R17_H_num ||
 1942     reg ==  F10_num || reg == F10_H_num ||
 1943     reg ==  F11_num || reg == F11_H_num ||
 1944     reg ==  F12_num || reg == F12_H_num ||
 1945     reg ==  F13_num || reg == F13_H_num ||
 1946     reg ==  F14_num || reg == F14_H_num ||
 1947     reg ==  F15_num || reg == F15_H_num ||
 1948     reg ==  F16_num || reg == F16_H_num ||
 1949     reg ==  F17_num || reg == F17_H_num;
 1950 }
 1951 
 1952 bool Matcher::is_spillable_arg(int reg)
 1953 {
 1954   return can_be_java_arg(reg);
 1955 }
 1956 
 1957 uint Matcher::int_pressure_limit()
 1958 {
 1959   // A derived pointer is live at CallNode and then is flagged by RA
 1960   // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
 1961   // derived pointers and lastly fail to spill after reaching maximum
 1962   // number of iterations. Lowering the default pressure threshold to
 1963   // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
 1964   // a high register pressure area of the code so that split_DEF can
 1965   // generate DefinitionSpillCopy for the derived pointer.
 1966   uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
 1967   if (!PreserveFramePointer) {
 1968     // When PreserveFramePointer is off, frame pointer is allocatable,
 1969     // but different from other SOC registers, it is excluded from
 1970     // fatproj's mask because its save type is No-Save. Decrease 1 to
 1971     // ensure high pressure at fatproj when PreserveFramePointer is off.
 1972     // See check_pressure_at_fatproj().
 1973     default_int_pressure_threshold--;
 1974   }
 1975   return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
 1976 }
 1977 
 1978 uint Matcher::float_pressure_limit()
 1979 {
 1980   // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
 1981   return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
 1982 }
 1983 
 1984 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 1985   return false;
 1986 }
 1987 
 1988 RegMask Matcher::divI_proj_mask() {
 1989   ShouldNotReachHere();
 1990   return RegMask();
 1991 }
 1992 
 1993 // Register for MODI projection of divmodI.
 1994 RegMask Matcher::modI_proj_mask() {
 1995   ShouldNotReachHere();
 1996   return RegMask();
 1997 }
 1998 
 1999 // Register for DIVL projection of divmodL.
 2000 RegMask Matcher::divL_proj_mask() {
 2001   ShouldNotReachHere();
 2002   return RegMask();
 2003 }
 2004 
 2005 // Register for MODL projection of divmodL.
 2006 RegMask Matcher::modL_proj_mask() {
 2007   ShouldNotReachHere();
 2008   return RegMask();
 2009 }
 2010 
 2011 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 2012   return FP_REG_mask();
 2013 }
 2014 
 2015 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
 2016   assert_cond(addp != NULL);
 2017   for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
 2018     Node* u = addp->fast_out(i);
 2019     if (u != NULL && u->is_Mem()) {
 2020       int opsize = u->as_Mem()->memory_size();
 2021       assert(opsize > 0, "unexpected memory operand size");
 2022       if (u->as_Mem()->memory_size() != (1 << shift)) {
 2023         return false;
 2024       }
 2025     }
 2026   }
 2027   return true;
 2028 }
 2029 
 2030 // Should the Matcher clone input 'm' of node 'n'?
 2031 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 2032   assert_cond(m != NULL);
 2033   if (is_vshift_con_pattern(n, m)) { // ShiftV src (ShiftCntV con)
 2034     mstack.push(m, Visit);           // m = ShiftCntV
 2035     return true;
 2036   }
 2037   return false;
 2038 }
 2039 
 2040 // Should the Matcher clone shifts on addressing modes, expecting them
 2041 // to be subsumed into complex addressing expressions or compute them
 2042 // into registers?
 2043 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 2044   return clone_base_plus_offset_address(m, mstack, address_visited);
 2045 }
 2046 
 2047 %}
 2048 
 2049 
 2050 
 2051 //----------ENCODING BLOCK-----------------------------------------------------
 2052 // This block specifies the encoding classes used by the compiler to
 2053 // output byte streams.  Encoding classes are parameterized macros
 2054 // used by Machine Instruction Nodes in order to generate the bit
 2055 // encoding of the instruction.  Operands specify their base encoding
 2056 // interface with the interface keyword.  There are currently
 2057 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 2058 // COND_INTER.  REG_INTER causes an operand to generate a function
 2059 // which returns its register number when queried.  CONST_INTER causes
 2060 // an operand to generate a function which returns the value of the
 2061 // constant when queried.  MEMORY_INTER causes an operand to generate
 2062 // four functions which return the Base Register, the Index Register,
 2063 // the Scale Value, and the Offset Value of the operand when queried.
 2064 // COND_INTER causes an operand to generate six functions which return
 2065 // the encoding code (ie - encoding bits for the instruction)
 2066 // associated with each basic boolean condition for a conditional
 2067 // instruction.
 2068 //
 2069 // Instructions specify two basic values for encoding.  Again, a
 2070 // function is available to check if the constant displacement is an
 2071 // oop. They use the ins_encode keyword to specify their encoding
 2072 // classes (which must be a sequence of enc_class names, and their
 2073 // parameters, specified in the encoding block), and they use the
 2074 // opcode keyword to specify, in order, their primary, secondary, and
 2075 // tertiary opcode.  Only the opcode sections which a particular
 2076 // instruction needs for encoding need to be specified.
 2077 encode %{
 2078   // BEGIN Non-volatile memory access
 2079 
 2080   enc_class riscv_enc_li_imm(iRegIorL dst, immIorL src) %{
 2081     C2_MacroAssembler _masm(&cbuf);
 2082     Assembler::CompressibleRegion cr(&_masm);
 2083     int64_t con = (int64_t)$src$$constant;
 2084     Register dst_reg = as_Register($dst$$reg);
 2085     __ li(dst_reg, con);
 2086   %}
 2087 
 2088   enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
 2089     C2_MacroAssembler _masm(&cbuf);
 2090     Register dst_reg = as_Register($dst$$reg);
 2091     address con = (address)$src$$constant;
 2092     if (con == NULL || con == (address)1) {
 2093       ShouldNotReachHere();
 2094     } else {
 2095       relocInfo::relocType rtype = $src->constant_reloc();
 2096       if (rtype == relocInfo::oop_type) {
 2097         __ movoop(dst_reg, (jobject)con, /*immediate*/true);
 2098       } else if (rtype == relocInfo::metadata_type) {
 2099         __ mov_metadata(dst_reg, (Metadata*)con);
 2100       } else {
 2101         assert(rtype == relocInfo::none, "unexpected reloc type");
 2102         __ li(dst_reg, $src$$constant);
 2103       }
 2104     }
 2105   %}
 2106 
 2107   enc_class riscv_enc_mov_p1(iRegP dst) %{
 2108     C2_MacroAssembler _masm(&cbuf);
 2109     Assembler::CompressibleRegion cr(&_masm);
 2110     Register dst_reg = as_Register($dst$$reg);
 2111     __ li(dst_reg, 1);
 2112   %}
 2113 
 2114   enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
 2115     C2_MacroAssembler _masm(&cbuf);
 2116     __ load_byte_map_base($dst$$Register);
 2117   %}
 2118 
 2119   enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
 2120     C2_MacroAssembler _masm(&cbuf);
 2121     Register dst_reg = as_Register($dst$$reg);
 2122     address con = (address)$src$$constant;
 2123     if (con == NULL) {
 2124       ShouldNotReachHere();
 2125     } else {
 2126       relocInfo::relocType rtype = $src->constant_reloc();
 2127       assert(rtype == relocInfo::oop_type, "unexpected reloc type");
 2128       __ set_narrow_oop(dst_reg, (jobject)con);
 2129     }
 2130   %}
 2131 
 2132   enc_class riscv_enc_mov_zero(iRegNorP dst) %{
 2133     C2_MacroAssembler _masm(&cbuf);
 2134     Register dst_reg = as_Register($dst$$reg);
 2135     __ mv(dst_reg, zr);
 2136   %}
 2137 
 2138   enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
 2139     C2_MacroAssembler _masm(&cbuf);
 2140     Register dst_reg = as_Register($dst$$reg);
 2141     address con = (address)$src$$constant;
 2142     if (con == NULL) {
 2143       ShouldNotReachHere();
 2144     } else {
 2145       relocInfo::relocType rtype = $src->constant_reloc();
 2146       assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
 2147       __ set_narrow_klass(dst_reg, (Klass *)con);
 2148     }
 2149   %}
 2150 
 2151   enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2152     C2_MacroAssembler _masm(&cbuf);
 2153     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2154                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2155                /*result as bool*/ true);
 2156   %}
 2157 
 2158   enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2159     C2_MacroAssembler _masm(&cbuf);
 2160     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2161                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2162                /*result as bool*/ true);
 2163   %}
 2164 
 2165   enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
 2166     C2_MacroAssembler _masm(&cbuf);
 2167     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2168                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 2169                /*result as bool*/ true);
 2170   %}
 2171 
 2172   enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2173     C2_MacroAssembler _masm(&cbuf);
 2174     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 2175                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2176                /*result as bool*/ true);
 2177   %}
 2178 
 2179   enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegINoSp oldval, iRegINoSp newval) %{
 2180     C2_MacroAssembler _masm(&cbuf);
 2181     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 2182                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2183                /*result as bool*/ true);
 2184   %}
 2185 
 2186   enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
 2187     C2_MacroAssembler _masm(&cbuf);
 2188     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 2189                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 2190                /*result as bool*/ true);
 2191   %}
 2192 
 2193   // compare and branch instruction encodings
 2194 
 2195   enc_class riscv_enc_j(label lbl) %{
 2196     C2_MacroAssembler _masm(&cbuf);
 2197     Label* L = $lbl$$label;
 2198     __ j(*L);
 2199   %}
 2200 
 2201   enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
 2202     C2_MacroAssembler _masm(&cbuf);
 2203     Label* L = $lbl$$label;
 2204     switch ($cmp$$cmpcode) {
 2205       case(BoolTest::ge):
 2206         __ j(*L);
 2207         break;
 2208       case(BoolTest::lt):
 2209         break;
 2210       default:
 2211         Unimplemented();
 2212     }
 2213   %}
 2214 
 2215   // call instruction encodings
 2216 
 2217   enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
 2218     Register sub_reg = as_Register($sub$$reg);
 2219     Register super_reg = as_Register($super$$reg);
 2220     Register temp_reg = as_Register($temp$$reg);
 2221     Register result_reg = as_Register($result$$reg);
 2222     Register cr_reg = t1;
 2223 
 2224     Label miss;
 2225     Label done;
 2226     C2_MacroAssembler _masm(&cbuf);
 2227     __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
 2228                                      NULL, &miss);
 2229     if ($primary) {
 2230       __ mv(result_reg, zr);
 2231     } else {
 2232       __ mv(cr_reg, zr);
 2233       __ j(done);
 2234     }
 2235 
 2236     __ bind(miss);
 2237     if (!$primary) {
 2238       __ li(cr_reg, 1);
 2239     }
 2240 
 2241     __ bind(done);
 2242   %}
 2243 
 2244   enc_class riscv_enc_java_static_call(method meth) %{
 2245     C2_MacroAssembler _masm(&cbuf);
 2246 
 2247     address addr = (address)$meth$$method;
 2248     address call = NULL;
 2249     assert_cond(addr != NULL);
 2250     if (!_method) {
 2251       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
 2252       call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
 2253       if (call == NULL) {
 2254         ciEnv::current()->record_failure("CodeCache is full");
 2255         return;
 2256       }
 2257     } else {
 2258       int method_index = resolved_method_index(cbuf);
 2259       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2260                                                   : static_call_Relocation::spec(method_index);
 2261       call = __ trampoline_call(Address(addr, rspec), &cbuf);
 2262       if (call == NULL) {
 2263         ciEnv::current()->record_failure("CodeCache is full");
 2264         return;
 2265       }
 2266 
 2267       // Emit stub for static call
 2268       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
 2269       if (stub == NULL) {
 2270         ciEnv::current()->record_failure("CodeCache is full");
 2271         return;
 2272       }
 2273     }
 2274   %}
 2275 
 2276   enc_class riscv_enc_java_dynamic_call(method meth) %{
 2277     C2_MacroAssembler _masm(&cbuf);
 2278     int method_index = resolved_method_index(cbuf);
 2279     address call = __ ic_call((address)$meth$$method, method_index);
 2280     if (call == NULL) {
 2281       ciEnv::current()->record_failure("CodeCache is full");
 2282       return;
 2283     }
 2284   %}
 2285 
 2286   enc_class riscv_enc_call_epilog() %{
 2287     C2_MacroAssembler _masm(&cbuf);
 2288     if (VerifyStackAtCalls) {
 2289       // Check that stack depth is unchanged: find majik cookie on stack
 2290       __ call_Unimplemented();
 2291     }
 2292   %}
 2293 
 2294   enc_class riscv_enc_java_to_runtime(method meth) %{
 2295     C2_MacroAssembler _masm(&cbuf);
 2296 
 2297     // some calls to generated routines (arraycopy code) are scheduled
 2298     // by C2 as runtime calls. if so we can call them using a jr (they
 2299     // will be in a reachable segment) otherwise we have to use a jalr
 2300     // which loads the absolute address into a register.
 2301     address entry = (address)$meth$$method;
 2302     CodeBlob *cb = CodeCache::find_blob(entry);
 2303     if (cb != NULL) {
 2304       address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
 2305       if (call == NULL) {
 2306         ciEnv::current()->record_failure("CodeCache is full");
 2307         return;
 2308       }
 2309     } else {
 2310       Label retaddr;
 2311       __ la(t1, retaddr);
 2312       __ la(t0, RuntimeAddress(entry));
 2313       // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
 2314       __ addi(sp, sp, -2 * wordSize);
 2315       __ sd(t1, Address(sp, wordSize));
 2316       __ jalr(t0);
 2317       __ bind(retaddr);
 2318       __ addi(sp, sp, 2 * wordSize);
 2319     }
 2320   %}
 2321 
 2322   // using the cr register as the bool result: 0 for success; others failed.
 2323   enc_class riscv_enc_fast_lock(iRegP object, iRegP box, iRegP tmp1, iRegP tmp2) %{
 2324     C2_MacroAssembler _masm(&cbuf);
 2325     Register flag = t1;
 2326     Register oop = as_Register($object$$reg);
 2327     Register box = as_Register($box$$reg);
 2328     Register disp_hdr = as_Register($tmp1$$reg);
 2329     Register tmp = as_Register($tmp2$$reg);
 2330     Label cont;
 2331     Label object_has_monitor;
 2332 
 2333     assert_different_registers(oop, box, tmp, disp_hdr, t0);
 2334 
 2335     // Load markWord from object into displaced_header.
 2336     __ ld(disp_hdr, Address(oop, oopDesc::mark_offset_in_bytes()));
 2337 
 2338     if (DiagnoseSyncOnValueBasedClasses != 0) {
 2339       __ load_klass(flag, oop);
 2340       __ lwu(flag, Address(flag, Klass::access_flags_offset()));
 2341       __ andi(flag, flag, JVM_ACC_IS_VALUE_BASED_CLASS, tmp /* tmp */);
 2342       __ bnez(flag, cont, true /* is_far */);
 2343     }
 2344 
 2345     // Check for existing monitor
 2346     __ andi(t0, disp_hdr, markWord::monitor_value);
 2347     __ bnez(t0, object_has_monitor);
 2348 
 2349     if (!UseHeavyMonitors) {
 2350       // Set tmp to be (markWord of object | UNLOCK_VALUE).
 2351       __ ori(tmp, disp_hdr, markWord::unlocked_value);
 2352 
 2353       // Initialize the box. (Must happen before we update the object mark!)
 2354       __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2355 
 2356       // Compare object markWord with an unlocked value (tmp) and if
 2357       // equal exchange the stack address of our box with object markWord.
 2358       // On failure disp_hdr contains the possibly locked markWord.
 2359       __ cmpxchg(/*memory address*/oop, /*expected value*/tmp, /*new value*/box, Assembler::int64, Assembler::aq,
 2360                  Assembler::rl, /*result*/disp_hdr);
 2361       __ mv(flag, zr);
 2362       __ beq(disp_hdr, tmp, cont); // prepare zero flag and goto cont if we won the cas
 2363 
 2364       assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2365 
 2366       // If the compare-and-exchange succeeded, then we found an unlocked
 2367       // object, will have now locked it will continue at label cont
 2368       // We did not see an unlocked object so try the fast recursive case.
 2369 
 2370       // Check if the owner is self by comparing the value in the
 2371       // markWord of object (disp_hdr) with the stack pointer.
 2372       __ sub(disp_hdr, disp_hdr, sp);
 2373       __ li(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markWord::lock_mask_in_place));
 2374       // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont,
 2375       // hence we can store 0 as the displaced header in the box, which indicates that it is a
 2376       // recursive lock.
 2377       __ andr(tmp/*==0?*/, disp_hdr, tmp);
 2378       __ sd(tmp/*==0, perhaps*/, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2379       __ mv(flag, tmp); // we can use the value of tmp as the result here
 2380     } else {
 2381       __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow-path
 2382     }
 2383 
 2384     __ j(cont);
 2385 
 2386     // Handle existing monitor.
 2387     __ bind(object_has_monitor);
 2388     // The object's monitor m is unlocked iff m->owner == NULL,
 2389     // otherwise m->owner may contain a thread or a stack address.
 2390     //
 2391     // Try to CAS m->owner from NULL to current thread.
 2392     __ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes() - markWord::monitor_value));
 2393     __ cmpxchg(/*memory address*/tmp, /*expected value*/zr, /*new value*/xthread, Assembler::int64, Assembler::aq,
 2394              Assembler::rl, /*result*/flag); // cas succeeds if flag == zr(expected)
 2395 
 2396     // Store a non-null value into the box to avoid looking like a re-entrant
 2397     // lock. The fast-path monitor unlock code checks for
 2398     // markWord::monitor_value so use markWord::unused_mark which has the
 2399     // relevant bit set, and also matches ObjectSynchronizer::slow_enter.
 2400     __ mv(tmp, (address)markWord::unused_mark().value());
 2401     __ sd(tmp, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2402 
 2403     __ beqz(flag, cont); // CAS success means locking succeeded
 2404 
 2405     __ bne(flag, xthread, cont); // Check for recursive locking
 2406 
 2407     // Recursive lock case
 2408     __ mv(flag, zr);
 2409     __ ld(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
 2410     __ add(tmp, tmp, 1u);
 2411     __ sd(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
 2412 
 2413     __ bind(cont);
 2414   %}
 2415 
 2416   // using cr flag to indicate the fast_unlock result: 0 for success; others failed.
 2417   enc_class riscv_enc_fast_unlock(iRegP object, iRegP box, iRegP tmp1, iRegP tmp2) %{
 2418     C2_MacroAssembler _masm(&cbuf);
 2419     Register flag = t1;
 2420     Register oop = as_Register($object$$reg);
 2421     Register box = as_Register($box$$reg);
 2422     Register disp_hdr = as_Register($tmp1$$reg);
 2423     Register tmp = as_Register($tmp2$$reg);
 2424     Label cont;
 2425     Label object_has_monitor;
 2426 
 2427     assert_different_registers(oop, box, tmp, disp_hdr, flag);
 2428 
 2429     if (!UseHeavyMonitors) {
 2430       // Find the lock address and load the displaced header from the stack.
 2431       __ ld(disp_hdr, Address(box, BasicLock::displaced_header_offset_in_bytes()));
 2432 
 2433       // If the displaced header is 0, we have a recursive unlock.
 2434       __ mv(flag, disp_hdr);
 2435       __ beqz(disp_hdr, cont);
 2436     }
 2437 
 2438     // Handle existing monitor.
 2439     __ ld(tmp, Address(oop, oopDesc::mark_offset_in_bytes()));
 2440     __ andi(t0, disp_hdr, markWord::monitor_value);
 2441     __ bnez(t0, object_has_monitor);
 2442 
 2443     if (!UseHeavyMonitors) {
 2444       // Check if it is still a light weight lock, this is true if we
 2445       // see the stack address of the basicLock in the markWord of the
 2446       // object.
 2447 
 2448       __ cmpxchg(/*memory address*/oop, /*expected value*/box, /*new value*/disp_hdr, Assembler::int64, Assembler::relaxed,
 2449                  Assembler::rl, /*result*/tmp);
 2450       __ xorr(flag, box, tmp); // box == tmp if cas succeeds
 2451     } else {
 2452       __ mv(flag, 1); // Set non-zero flag to indicate 'failure' -> take slow path
 2453     }
 2454     __ j(cont);
 2455 
 2456     assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
 2457 
 2458     // Handle existing monitor.
 2459     __ bind(object_has_monitor);
 2460     STATIC_ASSERT(markWord::monitor_value <= INT_MAX);
 2461     __ add(tmp, tmp, -(int)markWord::monitor_value); // monitor
 2462     __ ld(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2463 
 2464     Label notRecursive;
 2465     __ beqz(disp_hdr, notRecursive); // Will be 0 if not recursive.
 2466 
 2467     // Recursive lock
 2468     __ addi(disp_hdr, disp_hdr, -1);
 2469     __ sd(disp_hdr, Address(tmp, ObjectMonitor::recursions_offset_in_bytes()));
 2470     __ mv(flag, zr);
 2471     __ j(cont);
 2472 
 2473     __ bind(notRecursive);
 2474     __ ld(flag, Address(tmp, ObjectMonitor::EntryList_offset_in_bytes()));
 2475     __ ld(disp_hdr, Address(tmp, ObjectMonitor::cxq_offset_in_bytes()));
 2476     __ orr(flag, flag, disp_hdr); // Will be 0 if both are 0.
 2477     __ bnez(flag, cont);
 2478     // need a release store here
 2479     __ la(tmp, Address(tmp, ObjectMonitor::owner_offset_in_bytes()));
 2480     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 2481     __ sd(zr, Address(tmp)); // set unowned
 2482 
 2483     __ bind(cont);
 2484   %}
 2485 
 2486   // arithmetic encodings
 2487 
 2488   enc_class riscv_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
 2489     C2_MacroAssembler _masm(&cbuf);
 2490     Register dst_reg = as_Register($dst$$reg);
 2491     Register src1_reg = as_Register($src1$$reg);
 2492     Register src2_reg = as_Register($src2$$reg);
 2493     __ corrected_idivl(dst_reg, src1_reg, src2_reg, false);
 2494   %}
 2495 
 2496   enc_class riscv_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
 2497     C2_MacroAssembler _masm(&cbuf);
 2498     Register dst_reg = as_Register($dst$$reg);
 2499     Register src1_reg = as_Register($src1$$reg);
 2500     Register src2_reg = as_Register($src2$$reg);
 2501     __ corrected_idivq(dst_reg, src1_reg, src2_reg, false);
 2502   %}
 2503 
 2504   enc_class riscv_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
 2505     C2_MacroAssembler _masm(&cbuf);
 2506     Register dst_reg = as_Register($dst$$reg);
 2507     Register src1_reg = as_Register($src1$$reg);
 2508     Register src2_reg = as_Register($src2$$reg);
 2509     __ corrected_idivl(dst_reg, src1_reg, src2_reg, true);
 2510   %}
 2511 
 2512   enc_class riscv_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
 2513     C2_MacroAssembler _masm(&cbuf);
 2514     Register dst_reg = as_Register($dst$$reg);
 2515     Register src1_reg = as_Register($src1$$reg);
 2516     Register src2_reg = as_Register($src2$$reg);
 2517     __ corrected_idivq(dst_reg, src1_reg, src2_reg, true);
 2518   %}
 2519 
 2520   enc_class riscv_enc_tail_call(iRegP jump_target) %{
 2521     C2_MacroAssembler _masm(&cbuf);
 2522     Assembler::CompressibleRegion cr(&_masm);
 2523     Register target_reg = as_Register($jump_target$$reg);
 2524     __ jr(target_reg);
 2525   %}
 2526 
 2527   enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
 2528     C2_MacroAssembler _masm(&cbuf);
 2529     Assembler::CompressibleRegion cr(&_masm);
 2530     Register target_reg = as_Register($jump_target$$reg);
 2531     // exception oop should be in x10
 2532     // ret addr has been popped into ra
 2533     // callee expects it in x13
 2534     __ mv(x13, ra);
 2535     __ jr(target_reg);
 2536   %}
 2537 
 2538   enc_class riscv_enc_rethrow() %{
 2539     C2_MacroAssembler _masm(&cbuf);
 2540     __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
 2541   %}
 2542 
 2543   enc_class riscv_enc_ret() %{
 2544     C2_MacroAssembler _masm(&cbuf);
 2545     Assembler::CompressibleRegion cr(&_masm);
 2546     __ ret();
 2547   %}
 2548 
 2549 %}
 2550 
 2551 //----------FRAME--------------------------------------------------------------
 2552 // Definition of frame structure and management information.
 2553 //
 2554 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2555 //                             |   (to get allocators register number
 2556 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2557 //  r   CALLER     |        |
 2558 //  o     |        +--------+      pad to even-align allocators stack-slot
 2559 //  w     V        |  pad0  |        numbers; owned by CALLER
 2560 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2561 //  h     ^        |   in   |  5
 2562 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2563 //  |     |        |        |  3
 2564 //  |     |        +--------+
 2565 //  V     |        | old out|      Empty on Intel, window on Sparc
 2566 //        |    old |preserve|      Must be even aligned.
 2567 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2568 //        |        |   in   |  3   area for Intel ret address
 2569 //     Owned by    |preserve|      Empty on Sparc.
 2570 //       SELF      +--------+
 2571 //        |        |  pad2  |  2   pad to align old SP
 2572 //        |        +--------+  1
 2573 //        |        | locks  |  0
 2574 //        |        +--------+----> OptoReg::stack0(), even aligned
 2575 //        |        |  pad1  | 11   pad to align new SP
 2576 //        |        +--------+
 2577 //        |        |        | 10
 2578 //        |        | spills |  9   spills
 2579 //        V        |        |  8   (pad0 slot for callee)
 2580 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2581 //        ^        |  out   |  7
 2582 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2583 //     Owned by    +--------+
 2584 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2585 //        |    new |preserve|      Must be even-aligned.
 2586 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2587 //        |        |        |
 2588 //
 2589 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2590 //         known from SELF's arguments and the Java calling convention.
 2591 //         Region 6-7 is determined per call site.
 2592 // Note 2: If the calling convention leaves holes in the incoming argument
 2593 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2594 //         are owned by the CALLEE.  Holes should not be nessecary in the
 2595 //         incoming area, as the Java calling convention is completely under
 2596 //         the control of the AD file.  Doubles can be sorted and packed to
 2597 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
 2598 //         varargs C calling conventions.
 2599 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2600 //         even aligned with pad0 as needed.
 2601 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2602 //           (the latter is true on Intel but is it false on RISCV?)
 2603 //         region 6-11 is even aligned; it may be padded out more so that
 2604 //         the region from SP to FP meets the minimum stack alignment.
 2605 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2606 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2607 //         SP meets the minimum alignment.
 2608 
 2609 frame %{
 2610   // These three registers define part of the calling convention
 2611   // between compiled code and the interpreter.
 2612 
 2613   // Inline Cache Register or methodOop for I2C.
 2614   inline_cache_reg(R31);
 2615 
 2616   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
 2617   cisc_spilling_operand_name(indOffset);
 2618 
 2619   // Number of stack slots consumed by locking an object
 2620   // generate Compile::sync_stack_slots
 2621   // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
 2622   sync_stack_slots(1 * VMRegImpl::slots_per_word);
 2623 
 2624   // Compiled code's Frame Pointer
 2625   frame_pointer(R2);
 2626 
 2627   // Interpreter stores its frame pointer in a register which is
 2628   // stored to the stack by I2CAdaptors.
 2629   // I2CAdaptors convert from interpreted java to compiled java.
 2630   interpreter_frame_pointer(R8);
 2631 
 2632   // Stack alignment requirement
 2633   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2634 
 2635   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2636   // for calls to C.  Supports the var-args backing area for register parms.
 2637   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
 2638 
 2639   // The after-PROLOG location of the return address.  Location of
 2640   // return address specifies a type (REG or STACK) and a number
 2641   // representing the register number (i.e. - use a register name) or
 2642   // stack slot.
 2643   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2644   // Otherwise, it is above the locks and verification slot and alignment word
 2645   // TODO this may well be correct but need to check why that - 2 is there
 2646   // ppc port uses 0 but we definitely need to allow for fixed_slots
 2647   // which folds in the space used for monitors
 2648   return_addr(STACK - 2 +
 2649               align_up((Compile::current()->in_preserve_stack_slots() +
 2650                         Compile::current()->fixed_slots()),
 2651                        stack_alignment_in_slots()));
 2652 
 2653   // Location of compiled Java return values.  Same as C for now.
 2654   return_value
 2655   %{
 2656     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2657            "only return normal values");
 2658 
 2659     static const int lo[Op_RegL + 1] = { // enum name
 2660       0,                                 // Op_Node
 2661       0,                                 // Op_Set
 2662       R10_num,                           // Op_RegN
 2663       R10_num,                           // Op_RegI
 2664       R10_num,                           // Op_RegP
 2665       F10_num,                           // Op_RegF
 2666       F10_num,                           // Op_RegD
 2667       R10_num                            // Op_RegL
 2668     };
 2669 
 2670     static const int hi[Op_RegL + 1] = { // enum name
 2671       0,                                 // Op_Node
 2672       0,                                 // Op_Set
 2673       OptoReg::Bad,                      // Op_RegN
 2674       OptoReg::Bad,                      // Op_RegI
 2675       R10_H_num,                         // Op_RegP
 2676       OptoReg::Bad,                      // Op_RegF
 2677       F10_H_num,                         // Op_RegD
 2678       R10_H_num                          // Op_RegL
 2679     };
 2680 
 2681     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2682   %}
 2683 %}
 2684 
 2685 //----------ATTRIBUTES---------------------------------------------------------
 2686 //----------Operand Attributes-------------------------------------------------
 2687 op_attrib op_cost(1);        // Required cost attribute
 2688 
 2689 //----------Instruction Attributes---------------------------------------------
 2690 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
 2691 ins_attrib ins_size(32);        // Required size attribute (in bits)
 2692 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2693                                 // a non-matching short branch variant
 2694                                 // of some long branch?
 2695 ins_attrib ins_alignment(4);    // Required alignment attribute (must
 2696                                 // be a power of 2) specifies the
 2697                                 // alignment that some part of the
 2698                                 // instruction (not necessarily the
 2699                                 // start) requires.  If > 1, a
 2700                                 // compute_padding() function must be
 2701                                 // provided for the instruction
 2702 
 2703 //----------OPERANDS-----------------------------------------------------------
 2704 // Operand definitions must precede instruction definitions for correct parsing
 2705 // in the ADLC because operands constitute user defined types which are used in
 2706 // instruction definitions.
 2707 
 2708 //----------Simple Operands----------------------------------------------------
 2709 
 2710 // Integer operands 32 bit
 2711 // 32 bit immediate
 2712 operand immI()
 2713 %{
 2714   match(ConI);
 2715 
 2716   op_cost(0);
 2717   format %{ %}
 2718   interface(CONST_INTER);
 2719 %}
 2720 
 2721 // 32 bit zero
 2722 operand immI0()
 2723 %{
 2724   predicate(n->get_int() == 0);
 2725   match(ConI);
 2726 
 2727   op_cost(0);
 2728   format %{ %}
 2729   interface(CONST_INTER);
 2730 %}
 2731 
 2732 // 32 bit unit increment
 2733 operand immI_1()
 2734 %{
 2735   predicate(n->get_int() == 1);
 2736   match(ConI);
 2737 
 2738   op_cost(0);
 2739   format %{ %}
 2740   interface(CONST_INTER);
 2741 %}
 2742 
 2743 // 32 bit unit decrement
 2744 operand immI_M1()
 2745 %{
 2746   predicate(n->get_int() == -1);
 2747   match(ConI);
 2748 
 2749   op_cost(0);
 2750   format %{ %}
 2751   interface(CONST_INTER);
 2752 %}
 2753 
 2754 // Unsigned Integer Immediate:  6-bit int, greater than 32
 2755 operand uimmI6_ge32() %{
 2756   predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
 2757   match(ConI);
 2758   op_cost(0);
 2759   format %{ %}
 2760   interface(CONST_INTER);
 2761 %}
 2762 
 2763 operand immI_le_4()
 2764 %{
 2765   predicate(n->get_int() <= 4);
 2766   match(ConI);
 2767 
 2768   op_cost(0);
 2769   format %{ %}
 2770   interface(CONST_INTER);
 2771 %}
 2772 
 2773 operand immI_16()
 2774 %{
 2775   predicate(n->get_int() == 16);
 2776   match(ConI);
 2777   op_cost(0);
 2778   format %{ %}
 2779   interface(CONST_INTER);
 2780 %}
 2781 
 2782 operand immI_24()
 2783 %{
 2784   predicate(n->get_int() == 24);
 2785   match(ConI);
 2786   op_cost(0);
 2787   format %{ %}
 2788   interface(CONST_INTER);
 2789 %}
 2790 
 2791 operand immI_31()
 2792 %{
 2793   predicate(n->get_int() == 31);
 2794   match(ConI);
 2795 
 2796   op_cost(0);
 2797   format %{ %}
 2798   interface(CONST_INTER);
 2799 %}
 2800 
 2801 operand immI_63()
 2802 %{
 2803   predicate(n->get_int() == 63);
 2804   match(ConI);
 2805 
 2806   op_cost(0);
 2807   format %{ %}
 2808   interface(CONST_INTER);
 2809 %}
 2810 
 2811 // 32 bit integer valid for add immediate
 2812 operand immIAdd()
 2813 %{
 2814   predicate(Assembler::operand_valid_for_add_immediate((int64_t)n->get_int()));
 2815   match(ConI);
 2816   op_cost(0);
 2817   format %{ %}
 2818   interface(CONST_INTER);
 2819 %}
 2820 
 2821 // 32 bit integer valid for sub immediate
 2822 operand immISub()
 2823 %{
 2824   predicate(Assembler::operand_valid_for_add_immediate(-(int64_t)n->get_int()));
 2825   match(ConI);
 2826   op_cost(0);
 2827   format %{ %}
 2828   interface(CONST_INTER);
 2829 %}
 2830 
 2831 // 5 bit signed value.
 2832 operand immI5()
 2833 %{
 2834   predicate(n->get_int() <= 15 && n->get_int() >= -16);
 2835   match(ConI);
 2836 
 2837   op_cost(0);
 2838   format %{ %}
 2839   interface(CONST_INTER);
 2840 %}
 2841 
 2842 // 5 bit signed value (simm5)
 2843 operand immL5()
 2844 %{
 2845   predicate(n->get_long() <= 15 && n->get_long() >= -16);
 2846   match(ConL);
 2847 
 2848   op_cost(0);
 2849   format %{ %}
 2850   interface(CONST_INTER);
 2851 %}
 2852 
 2853 // Integer operands 64 bit
 2854 // 64 bit immediate
 2855 operand immL()
 2856 %{
 2857   match(ConL);
 2858 
 2859   op_cost(0);
 2860   format %{ %}
 2861   interface(CONST_INTER);
 2862 %}
 2863 
 2864 // 64 bit zero
 2865 operand immL0()
 2866 %{
 2867   predicate(n->get_long() == 0);
 2868   match(ConL);
 2869 
 2870   op_cost(0);
 2871   format %{ %}
 2872   interface(CONST_INTER);
 2873 %}
 2874 
 2875 // Pointer operands
 2876 // Pointer Immediate
 2877 operand immP()
 2878 %{
 2879   match(ConP);
 2880 
 2881   op_cost(0);
 2882   format %{ %}
 2883   interface(CONST_INTER);
 2884 %}
 2885 
 2886 // NULL Pointer Immediate
 2887 operand immP0()
 2888 %{
 2889   predicate(n->get_ptr() == 0);
 2890   match(ConP);
 2891 
 2892   op_cost(0);
 2893   format %{ %}
 2894   interface(CONST_INTER);
 2895 %}
 2896 
 2897 // Pointer Immediate One
 2898 // this is used in object initialization (initial object header)
 2899 operand immP_1()
 2900 %{
 2901   predicate(n->get_ptr() == 1);
 2902   match(ConP);
 2903 
 2904   op_cost(0);
 2905   format %{ %}
 2906   interface(CONST_INTER);
 2907 %}
 2908 
 2909 // Card Table Byte Map Base
 2910 operand immByteMapBase()
 2911 %{
 2912   // Get base of card map
 2913   predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
 2914             (CardTable::CardValue*)n->get_ptr() ==
 2915              ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
 2916   match(ConP);
 2917 
 2918   op_cost(0);
 2919   format %{ %}
 2920   interface(CONST_INTER);
 2921 %}
 2922 
 2923 // Int Immediate: low 16-bit mask
 2924 operand immI_16bits()
 2925 %{
 2926   predicate(n->get_int() == 0xFFFF);
 2927   match(ConI);
 2928   op_cost(0);
 2929   format %{ %}
 2930   interface(CONST_INTER);
 2931 %}
 2932 
 2933 // Long Immediate: low 32-bit mask
 2934 operand immL_32bits()
 2935 %{
 2936   predicate(n->get_long() == 0xFFFFFFFFL);
 2937   match(ConL);
 2938   op_cost(0);
 2939   format %{ %}
 2940   interface(CONST_INTER);
 2941 %}
 2942 
 2943 // 64 bit unit decrement
 2944 operand immL_M1()
 2945 %{
 2946   predicate(n->get_long() == -1);
 2947   match(ConL);
 2948 
 2949   op_cost(0);
 2950   format %{ %}
 2951   interface(CONST_INTER);
 2952 %}
 2953 
 2954 
 2955 // 32 bit offset of pc in thread anchor
 2956 
 2957 operand immL_pc_off()
 2958 %{
 2959   predicate(n->get_long() == in_bytes(JavaThread::frame_anchor_offset()) +
 2960                              in_bytes(JavaFrameAnchor::last_Java_pc_offset()));
 2961   match(ConL);
 2962 
 2963   op_cost(0);
 2964   format %{ %}
 2965   interface(CONST_INTER);
 2966 %}
 2967 
 2968 // 64 bit integer valid for add immediate
 2969 operand immLAdd()
 2970 %{
 2971   predicate(Assembler::operand_valid_for_add_immediate(n->get_long()));
 2972   match(ConL);
 2973   op_cost(0);
 2974   format %{ %}
 2975   interface(CONST_INTER);
 2976 %}
 2977 
 2978 // 64 bit integer valid for sub immediate
 2979 operand immLSub()
 2980 %{
 2981   predicate(Assembler::operand_valid_for_add_immediate(-(n->get_long())));
 2982   match(ConL);
 2983   op_cost(0);
 2984   format %{ %}
 2985   interface(CONST_INTER);
 2986 %}
 2987 
 2988 // Narrow pointer operands
 2989 // Narrow Pointer Immediate
 2990 operand immN()
 2991 %{
 2992   match(ConN);
 2993 
 2994   op_cost(0);
 2995   format %{ %}
 2996   interface(CONST_INTER);
 2997 %}
 2998 
 2999 // Narrow NULL Pointer Immediate
 3000 operand immN0()
 3001 %{
 3002   predicate(n->get_narrowcon() == 0);
 3003   match(ConN);
 3004 
 3005   op_cost(0);
 3006   format %{ %}
 3007   interface(CONST_INTER);
 3008 %}
 3009 
 3010 operand immNKlass()
 3011 %{
 3012   match(ConNKlass);
 3013 
 3014   op_cost(0);
 3015   format %{ %}
 3016   interface(CONST_INTER);
 3017 %}
 3018 
 3019 // Float and Double operands
 3020 // Double Immediate
 3021 operand immD()
 3022 %{
 3023   match(ConD);
 3024   op_cost(0);
 3025   format %{ %}
 3026   interface(CONST_INTER);
 3027 %}
 3028 
 3029 // Double Immediate: +0.0d
 3030 operand immD0()
 3031 %{
 3032   predicate(jlong_cast(n->getd()) == 0);
 3033   match(ConD);
 3034 
 3035   op_cost(0);
 3036   format %{ %}
 3037   interface(CONST_INTER);
 3038 %}
 3039 
 3040 // Float Immediate
 3041 operand immF()
 3042 %{
 3043   match(ConF);
 3044   op_cost(0);
 3045   format %{ %}
 3046   interface(CONST_INTER);
 3047 %}
 3048 
 3049 // Float Immediate: +0.0f.
 3050 operand immF0()
 3051 %{
 3052   predicate(jint_cast(n->getf()) == 0);
 3053   match(ConF);
 3054 
 3055   op_cost(0);
 3056   format %{ %}
 3057   interface(CONST_INTER);
 3058 %}
 3059 
 3060 operand immIOffset()
 3061 %{
 3062   predicate(is_imm_in_range(n->get_int(), 12, 0));
 3063   match(ConI);
 3064   op_cost(0);
 3065   format %{ %}
 3066   interface(CONST_INTER);
 3067 %}
 3068 
 3069 operand immLOffset()
 3070 %{
 3071   predicate(is_imm_in_range(n->get_long(), 12, 0));
 3072   match(ConL);
 3073   op_cost(0);
 3074   format %{ %}
 3075   interface(CONST_INTER);
 3076 %}
 3077 
 3078 // Scale values
 3079 operand immIScale()
 3080 %{
 3081   predicate(1 <= n->get_int() && (n->get_int() <= 3));
 3082   match(ConI);
 3083 
 3084   op_cost(0);
 3085   format %{ %}
 3086   interface(CONST_INTER);
 3087 %}
 3088 
 3089 // Integer 32 bit Register Operands
 3090 operand iRegI()
 3091 %{
 3092   constraint(ALLOC_IN_RC(any_reg32));
 3093   match(RegI);
 3094   match(iRegINoSp);
 3095   op_cost(0);
 3096   format %{ %}
 3097   interface(REG_INTER);
 3098 %}
 3099 
 3100 // Integer 32 bit Register not Special
 3101 operand iRegINoSp()
 3102 %{
 3103   constraint(ALLOC_IN_RC(no_special_reg32));
 3104   match(RegI);
 3105   op_cost(0);
 3106   format %{ %}
 3107   interface(REG_INTER);
 3108 %}
 3109 
 3110 // Register R10 only
 3111 operand iRegI_R10()
 3112 %{
 3113   constraint(ALLOC_IN_RC(int_r10_reg));
 3114   match(RegI);
 3115   match(iRegINoSp);
 3116   op_cost(0);
 3117   format %{ %}
 3118   interface(REG_INTER);
 3119 %}
 3120 
 3121 // Register R12 only
 3122 operand iRegI_R12()
 3123 %{
 3124   constraint(ALLOC_IN_RC(int_r12_reg));
 3125   match(RegI);
 3126   match(iRegINoSp);
 3127   op_cost(0);
 3128   format %{ %}
 3129   interface(REG_INTER);
 3130 %}
 3131 
 3132 // Register R13 only
 3133 operand iRegI_R13()
 3134 %{
 3135   constraint(ALLOC_IN_RC(int_r13_reg));
 3136   match(RegI);
 3137   match(iRegINoSp);
 3138   op_cost(0);
 3139   format %{ %}
 3140   interface(REG_INTER);
 3141 %}
 3142 
 3143 // Register R14 only
 3144 operand iRegI_R14()
 3145 %{
 3146   constraint(ALLOC_IN_RC(int_r14_reg));
 3147   match(RegI);
 3148   match(iRegINoSp);
 3149   op_cost(0);
 3150   format %{ %}
 3151   interface(REG_INTER);
 3152 %}
 3153 
 3154 // Integer 64 bit Register Operands
 3155 operand iRegL()
 3156 %{
 3157   constraint(ALLOC_IN_RC(any_reg));
 3158   match(RegL);
 3159   match(iRegLNoSp);
 3160   op_cost(0);
 3161   format %{ %}
 3162   interface(REG_INTER);
 3163 %}
 3164 
 3165 // Integer 64 bit Register not Special
 3166 operand iRegLNoSp()
 3167 %{
 3168   constraint(ALLOC_IN_RC(no_special_reg));
 3169   match(RegL);
 3170   match(iRegL_R10);
 3171   format %{ %}
 3172   interface(REG_INTER);
 3173 %}
 3174 
 3175 // Long 64 bit Register R28 only
 3176 operand iRegL_R28()
 3177 %{
 3178   constraint(ALLOC_IN_RC(r28_reg));
 3179   match(RegL);
 3180   match(iRegLNoSp);
 3181   op_cost(0);
 3182   format %{ %}
 3183   interface(REG_INTER);
 3184 %}
 3185 
 3186 // Long 64 bit Register R29 only
 3187 operand iRegL_R29()
 3188 %{
 3189   constraint(ALLOC_IN_RC(r29_reg));
 3190   match(RegL);
 3191   match(iRegLNoSp);
 3192   op_cost(0);
 3193   format %{ %}
 3194   interface(REG_INTER);
 3195 %}
 3196 
 3197 // Long 64 bit Register R30 only
 3198 operand iRegL_R30()
 3199 %{
 3200   constraint(ALLOC_IN_RC(r30_reg));
 3201   match(RegL);
 3202   match(iRegLNoSp);
 3203   op_cost(0);
 3204   format %{ %}
 3205   interface(REG_INTER);
 3206 %}
 3207 
 3208 // Pointer Register Operands
 3209 // Pointer Register
 3210 operand iRegP()
 3211 %{
 3212   constraint(ALLOC_IN_RC(ptr_reg));
 3213   match(RegP);
 3214   match(iRegPNoSp);
 3215   match(iRegP_R10);
 3216   match(javaThread_RegP);
 3217   op_cost(0);
 3218   format %{ %}
 3219   interface(REG_INTER);
 3220 %}
 3221 
 3222 // Pointer 64 bit Register not Special
 3223 operand iRegPNoSp()
 3224 %{
 3225   constraint(ALLOC_IN_RC(no_special_ptr_reg));
 3226   match(RegP);
 3227   op_cost(0);
 3228   format %{ %}
 3229   interface(REG_INTER);
 3230 %}
 3231 
 3232 operand iRegP_R10()
 3233 %{
 3234   constraint(ALLOC_IN_RC(r10_reg));
 3235   match(RegP);
 3236   // match(iRegP);
 3237   match(iRegPNoSp);
 3238   op_cost(0);
 3239   format %{ %}
 3240   interface(REG_INTER);
 3241 %}
 3242 
 3243 // Pointer 64 bit Register R11 only
 3244 operand iRegP_R11()
 3245 %{
 3246   constraint(ALLOC_IN_RC(r11_reg));
 3247   match(RegP);
 3248   match(iRegPNoSp);
 3249   op_cost(0);
 3250   format %{ %}
 3251   interface(REG_INTER);
 3252 %}
 3253 
 3254 operand iRegP_R12()
 3255 %{
 3256   constraint(ALLOC_IN_RC(r12_reg));
 3257   match(RegP);
 3258   // match(iRegP);
 3259   match(iRegPNoSp);
 3260   op_cost(0);
 3261   format %{ %}
 3262   interface(REG_INTER);
 3263 %}
 3264 
 3265 // Pointer 64 bit Register R13 only
 3266 operand iRegP_R13()
 3267 %{
 3268   constraint(ALLOC_IN_RC(r13_reg));
 3269   match(RegP);
 3270   match(iRegPNoSp);
 3271   op_cost(0);
 3272   format %{ %}
 3273   interface(REG_INTER);
 3274 %}
 3275 
 3276 operand iRegP_R14()
 3277 %{
 3278   constraint(ALLOC_IN_RC(r14_reg));
 3279   match(RegP);
 3280   // match(iRegP);
 3281   match(iRegPNoSp);
 3282   op_cost(0);
 3283   format %{ %}
 3284   interface(REG_INTER);
 3285 %}
 3286 
 3287 operand iRegP_R15()
 3288 %{
 3289   constraint(ALLOC_IN_RC(r15_reg));
 3290   match(RegP);
 3291   // match(iRegP);
 3292   match(iRegPNoSp);
 3293   op_cost(0);
 3294   format %{ %}
 3295   interface(REG_INTER);
 3296 %}
 3297 
 3298 operand iRegP_R16()
 3299 %{
 3300   constraint(ALLOC_IN_RC(r16_reg));
 3301   match(RegP);
 3302   // match(iRegP);
 3303   match(iRegPNoSp);
 3304   op_cost(0);
 3305   format %{ %}
 3306   interface(REG_INTER);
 3307 %}
 3308 
 3309 // Pointer 64 bit Register R28 only
 3310 operand iRegP_R28()
 3311 %{
 3312   constraint(ALLOC_IN_RC(r28_reg));
 3313   match(RegP);
 3314   match(iRegPNoSp);
 3315   op_cost(0);
 3316   format %{ %}
 3317   interface(REG_INTER);
 3318 %}
 3319 
 3320 // Pointer Register Operands
 3321 // Narrow Pointer Register
 3322 operand iRegN()
 3323 %{
 3324   constraint(ALLOC_IN_RC(any_reg32));
 3325   match(RegN);
 3326   match(iRegNNoSp);
 3327   op_cost(0);
 3328   format %{ %}
 3329   interface(REG_INTER);
 3330 %}
 3331 
 3332 // Integer 64 bit Register not Special
 3333 operand iRegNNoSp()
 3334 %{
 3335   constraint(ALLOC_IN_RC(no_special_reg32));
 3336   match(RegN);
 3337   op_cost(0);
 3338   format %{ %}
 3339   interface(REG_INTER);
 3340 %}
 3341 
 3342 // heap base register -- used for encoding immN0
 3343 operand iRegIHeapbase()
 3344 %{
 3345   constraint(ALLOC_IN_RC(heapbase_reg));
 3346   match(RegI);
 3347   op_cost(0);
 3348   format %{ %}
 3349   interface(REG_INTER);
 3350 %}
 3351 
 3352 // Long 64 bit Register R10 only
 3353 operand iRegL_R10()
 3354 %{
 3355   constraint(ALLOC_IN_RC(r10_reg));
 3356   match(RegL);
 3357   match(iRegLNoSp);
 3358   op_cost(0);
 3359   format %{ %}
 3360   interface(REG_INTER);
 3361 %}
 3362 
 3363 // Float Register
 3364 // Float register operands
 3365 operand fRegF()
 3366 %{
 3367   constraint(ALLOC_IN_RC(float_reg));
 3368   match(RegF);
 3369 
 3370   op_cost(0);
 3371   format %{ %}
 3372   interface(REG_INTER);
 3373 %}
 3374 
 3375 // Double Register
 3376 // Double register operands
 3377 operand fRegD()
 3378 %{
 3379   constraint(ALLOC_IN_RC(double_reg));
 3380   match(RegD);
 3381 
 3382   op_cost(0);
 3383   format %{ %}
 3384   interface(REG_INTER);
 3385 %}
 3386 
 3387 // Generic vector class. This will be used for
 3388 // all vector operands.
 3389 operand vReg()
 3390 %{
 3391   constraint(ALLOC_IN_RC(vectora_reg));
 3392   match(VecA);
 3393   op_cost(0);
 3394   format %{ %}
 3395   interface(REG_INTER);
 3396 %}
 3397 
 3398 operand vReg_V1()
 3399 %{
 3400   constraint(ALLOC_IN_RC(v1_reg));
 3401   match(VecA);
 3402   match(vReg);
 3403   op_cost(0);
 3404   format %{ %}
 3405   interface(REG_INTER);
 3406 %}
 3407 
 3408 operand vReg_V2()
 3409 %{
 3410   constraint(ALLOC_IN_RC(v2_reg));
 3411   match(VecA);
 3412   match(vReg);
 3413   op_cost(0);
 3414   format %{ %}
 3415   interface(REG_INTER);
 3416 %}
 3417 
 3418 operand vReg_V3()
 3419 %{
 3420   constraint(ALLOC_IN_RC(v3_reg));
 3421   match(VecA);
 3422   match(vReg);
 3423   op_cost(0);
 3424   format %{ %}
 3425   interface(REG_INTER);
 3426 %}
 3427 
 3428 operand vReg_V4()
 3429 %{
 3430   constraint(ALLOC_IN_RC(v4_reg));
 3431   match(VecA);
 3432   match(vReg);
 3433   op_cost(0);
 3434   format %{ %}
 3435   interface(REG_INTER);
 3436 %}
 3437 
 3438 operand vReg_V5()
 3439 %{
 3440   constraint(ALLOC_IN_RC(v5_reg));
 3441   match(VecA);
 3442   match(vReg);
 3443   op_cost(0);
 3444   format %{ %}
 3445   interface(REG_INTER);
 3446 %}
 3447 
 3448 // Java Thread Register
 3449 operand javaThread_RegP(iRegP reg)
 3450 %{
 3451   constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
 3452   match(reg);
 3453   op_cost(0);
 3454   format %{ %}
 3455   interface(REG_INTER);
 3456 %}
 3457 
 3458 //----------Memory Operands----------------------------------------------------
 3459 // RISCV has only base_plus_offset and literal address mode, so no need to use
 3460 // index and scale. Here set index as 0xffffffff and scale as 0x0.
 3461 operand indirect(iRegP reg)
 3462 %{
 3463   constraint(ALLOC_IN_RC(ptr_reg));
 3464   match(reg);
 3465   op_cost(0);
 3466   format %{ "[$reg]" %}
 3467   interface(MEMORY_INTER) %{
 3468     base($reg);
 3469     index(0xffffffff);
 3470     scale(0x0);
 3471     disp(0x0);
 3472   %}
 3473 %}
 3474 
 3475 operand indOffI(iRegP reg, immIOffset off)
 3476 %{
 3477   constraint(ALLOC_IN_RC(ptr_reg));
 3478   match(AddP reg off);
 3479   op_cost(0);
 3480   format %{ "[$reg, $off]" %}
 3481   interface(MEMORY_INTER) %{
 3482     base($reg);
 3483     index(0xffffffff);
 3484     scale(0x0);
 3485     disp($off);
 3486   %}
 3487 %}
 3488 
 3489 operand indOffL(iRegP reg, immLOffset off)
 3490 %{
 3491   constraint(ALLOC_IN_RC(ptr_reg));
 3492   match(AddP reg off);
 3493   op_cost(0);
 3494   format %{ "[$reg, $off]" %}
 3495   interface(MEMORY_INTER) %{
 3496     base($reg);
 3497     index(0xffffffff);
 3498     scale(0x0);
 3499     disp($off);
 3500   %}
 3501 %}
 3502 
 3503 operand indirectN(iRegN reg)
 3504 %{
 3505   predicate(CompressedOops::shift() == 0);
 3506   constraint(ALLOC_IN_RC(ptr_reg));
 3507   match(DecodeN reg);
 3508   op_cost(0);
 3509   format %{ "[$reg]\t# narrow" %}
 3510   interface(MEMORY_INTER) %{
 3511     base($reg);
 3512     index(0xffffffff);
 3513     scale(0x0);
 3514     disp(0x0);
 3515   %}
 3516 %}
 3517 
 3518 operand indOffIN(iRegN reg, immIOffset off)
 3519 %{
 3520   predicate(CompressedOops::shift() == 0);
 3521   constraint(ALLOC_IN_RC(ptr_reg));
 3522   match(AddP (DecodeN reg) off);
 3523   op_cost(0);
 3524   format %{ "[$reg, $off]\t# narrow" %}
 3525   interface(MEMORY_INTER) %{
 3526     base($reg);
 3527     index(0xffffffff);
 3528     scale(0x0);
 3529     disp($off);
 3530   %}
 3531 %}
 3532 
 3533 operand indOffLN(iRegN reg, immLOffset off)
 3534 %{
 3535   predicate(CompressedOops::shift() == 0);
 3536   constraint(ALLOC_IN_RC(ptr_reg));
 3537   match(AddP (DecodeN reg) off);
 3538   op_cost(0);
 3539   format %{ "[$reg, $off]\t# narrow" %}
 3540   interface(MEMORY_INTER) %{
 3541     base($reg);
 3542     index(0xffffffff);
 3543     scale(0x0);
 3544     disp($off);
 3545   %}
 3546 %}
 3547 
 3548 // RISCV opto stubs need to write to the pc slot in the thread anchor
 3549 operand thread_anchor_pc(javaThread_RegP reg, immL_pc_off off)
 3550 %{
 3551   constraint(ALLOC_IN_RC(ptr_reg));
 3552   match(AddP reg off);
 3553   op_cost(0);
 3554   format %{ "[$reg, $off]" %}
 3555   interface(MEMORY_INTER) %{
 3556     base($reg);
 3557     index(0xffffffff);
 3558     scale(0x0);
 3559     disp($off);
 3560   %}
 3561 %}
 3562 
 3563 
 3564 //----------Special Memory Operands--------------------------------------------
 3565 // Stack Slot Operand - This operand is used for loading and storing temporary
 3566 //                      values on the stack where a match requires a value to
 3567 //                      flow through memory.
 3568 operand stackSlotI(sRegI reg)
 3569 %{
 3570   constraint(ALLOC_IN_RC(stack_slots));
 3571   // No match rule because this operand is only generated in matching
 3572   // match(RegI);
 3573   format %{ "[$reg]" %}
 3574   interface(MEMORY_INTER) %{
 3575     base(0x02);  // RSP
 3576     index(0xffffffff);  // No Index
 3577     scale(0x0);  // No Scale
 3578     disp($reg);  // Stack Offset
 3579   %}
 3580 %}
 3581 
 3582 operand stackSlotF(sRegF reg)
 3583 %{
 3584   constraint(ALLOC_IN_RC(stack_slots));
 3585   // No match rule because this operand is only generated in matching
 3586   // match(RegF);
 3587   format %{ "[$reg]" %}
 3588   interface(MEMORY_INTER) %{
 3589     base(0x02);  // RSP
 3590     index(0xffffffff);  // No Index
 3591     scale(0x0);  // No Scale
 3592     disp($reg);  // Stack Offset
 3593   %}
 3594 %}
 3595 
 3596 operand stackSlotD(sRegD reg)
 3597 %{
 3598   constraint(ALLOC_IN_RC(stack_slots));
 3599   // No match rule because this operand is only generated in matching
 3600   // match(RegD);
 3601   format %{ "[$reg]" %}
 3602   interface(MEMORY_INTER) %{
 3603     base(0x02);  // RSP
 3604     index(0xffffffff);  // No Index
 3605     scale(0x0);  // No Scale
 3606     disp($reg);  // Stack Offset
 3607   %}
 3608 %}
 3609 
 3610 operand stackSlotL(sRegL reg)
 3611 %{
 3612   constraint(ALLOC_IN_RC(stack_slots));
 3613   // No match rule because this operand is only generated in matching
 3614   // match(RegL);
 3615   format %{ "[$reg]" %}
 3616   interface(MEMORY_INTER) %{
 3617     base(0x02);  // RSP
 3618     index(0xffffffff);  // No Index
 3619     scale(0x0);  // No Scale
 3620     disp($reg);  // Stack Offset
 3621   %}
 3622 %}
 3623 
 3624 // Special operand allowing long args to int ops to be truncated for free
 3625 
 3626 operand iRegL2I(iRegL reg) %{
 3627 
 3628   op_cost(0);
 3629 
 3630   match(ConvL2I reg);
 3631 
 3632   format %{ "l2i($reg)" %}
 3633 
 3634   interface(REG_INTER)
 3635 %}
 3636 
 3637 
 3638 // Comparison Operands
 3639 // NOTE: Label is a predefined operand which should not be redefined in
 3640 //       the AD file. It is generically handled within the ADLC.
 3641 
 3642 //----------Conditional Branch Operands----------------------------------------
 3643 // Comparison Op  - This is the operation of the comparison, and is limited to
 3644 //                  the following set of codes:
 3645 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3646 //
 3647 // Other attributes of the comparison, such as unsignedness, are specified
 3648 // by the comparison instruction that sets a condition code flags register.
 3649 // That result is represented by a flags operand whose subtype is appropriate
 3650 // to the unsignedness (etc.) of the comparison.
 3651 //
 3652 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3653 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3654 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 3655 
 3656 
 3657 // used for signed integral comparisons and fp comparisons
 3658 operand cmpOp()
 3659 %{
 3660   match(Bool);
 3661 
 3662   format %{ "" %}
 3663 
 3664   // the values in interface derives from struct BoolTest::mask
 3665   interface(COND_INTER) %{
 3666     equal(0x0, "eq");
 3667     greater(0x1, "gt");
 3668     overflow(0x2, "overflow");
 3669     less(0x3, "lt");
 3670     not_equal(0x4, "ne");
 3671     less_equal(0x5, "le");
 3672     no_overflow(0x6, "no_overflow");
 3673     greater_equal(0x7, "ge");
 3674   %}
 3675 %}
 3676 
 3677 // used for unsigned integral comparisons
 3678 operand cmpOpU()
 3679 %{
 3680   match(Bool);
 3681 
 3682   format %{ "" %}
 3683   // the values in interface derives from struct BoolTest::mask
 3684   interface(COND_INTER) %{
 3685     equal(0x0, "eq");
 3686     greater(0x1, "gtu");
 3687     overflow(0x2, "overflow");
 3688     less(0x3, "ltu");
 3689     not_equal(0x4, "ne");
 3690     less_equal(0x5, "leu");
 3691     no_overflow(0x6, "no_overflow");
 3692     greater_equal(0x7, "geu");
 3693   %}
 3694 %}
 3695 
 3696 // used for certain integral comparisons which can be
 3697 // converted to bxx instructions
 3698 operand cmpOpEqNe()
 3699 %{
 3700   match(Bool);
 3701   op_cost(0);
 3702   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3703             n->as_Bool()->_test._test == BoolTest::eq);
 3704 
 3705   format %{ "" %}
 3706   interface(COND_INTER) %{
 3707     equal(0x0, "eq");
 3708     greater(0x1, "gt");
 3709     overflow(0x2, "overflow");
 3710     less(0x3, "lt");
 3711     not_equal(0x4, "ne");
 3712     less_equal(0x5, "le");
 3713     no_overflow(0x6, "no_overflow");
 3714     greater_equal(0x7, "ge");
 3715   %}
 3716 %}
 3717 
 3718 operand cmpOpULtGe()
 3719 %{
 3720   match(Bool);
 3721   op_cost(0);
 3722   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 3723             n->as_Bool()->_test._test == BoolTest::ge);
 3724 
 3725   format %{ "" %}
 3726   interface(COND_INTER) %{
 3727     equal(0x0, "eq");
 3728     greater(0x1, "gt");
 3729     overflow(0x2, "overflow");
 3730     less(0x3, "lt");
 3731     not_equal(0x4, "ne");
 3732     less_equal(0x5, "le");
 3733     no_overflow(0x6, "no_overflow");
 3734     greater_equal(0x7, "ge");
 3735   %}
 3736 %}
 3737 
 3738 operand cmpOpUEqNeLeGt()
 3739 %{
 3740   match(Bool);
 3741   op_cost(0);
 3742   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 3743             n->as_Bool()->_test._test == BoolTest::eq ||
 3744             n->as_Bool()->_test._test == BoolTest::le ||
 3745             n->as_Bool()->_test._test == BoolTest::gt);
 3746 
 3747   format %{ "" %}
 3748   interface(COND_INTER) %{
 3749     equal(0x0, "eq");
 3750     greater(0x1, "gt");
 3751     overflow(0x2, "overflow");
 3752     less(0x3, "lt");
 3753     not_equal(0x4, "ne");
 3754     less_equal(0x5, "le");
 3755     no_overflow(0x6, "no_overflow");
 3756     greater_equal(0x7, "ge");
 3757   %}
 3758 %}
 3759 
 3760 
 3761 // Flags register, used as output of compare logic
 3762 operand rFlagsReg()
 3763 %{
 3764   constraint(ALLOC_IN_RC(reg_flags));
 3765   match(RegFlags);
 3766 
 3767   op_cost(0);
 3768   format %{ "RFLAGS" %}
 3769   interface(REG_INTER);
 3770 %}
 3771 
 3772 // Special Registers
 3773 
 3774 // Method Register
 3775 operand inline_cache_RegP(iRegP reg)
 3776 %{
 3777   constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
 3778   match(reg);
 3779   match(iRegPNoSp);
 3780   op_cost(0);
 3781   format %{ %}
 3782   interface(REG_INTER);
 3783 %}
 3784 
 3785 //----------OPERAND CLASSES----------------------------------------------------
 3786 // Operand Classes are groups of operands that are used as to simplify
 3787 // instruction definitions by not requiring the AD writer to specify
 3788 // separate instructions for every form of operand when the
 3789 // instruction accepts multiple operand types with the same basic
 3790 // encoding and format. The classic case of this is memory operands.
 3791 
 3792 // memory is used to define read/write location for load/store
 3793 // instruction defs. we can turn a memory op into an Address
 3794 
 3795 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
 3796 
 3797 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
 3798 // operations. it allows the src to be either an iRegI or a (ConvL2I
 3799 // iRegL). in the latter case the l2i normally planted for a ConvL2I
 3800 // can be elided because the 32-bit instruction will just employ the
 3801 // lower 32 bits anyway.
 3802 //
 3803 // n.b. this does not elide all L2I conversions. if the truncated
 3804 // value is consumed by more than one operation then the ConvL2I
 3805 // cannot be bundled into the consuming nodes so an l2i gets planted
 3806 // (actually a mvw $dst $src) and the downstream instructions consume
 3807 // the result of the l2i as an iRegI input. That's a shame since the
 3808 // mvw is actually redundant but its not too costly.
 3809 
 3810 opclass iRegIorL2I(iRegI, iRegL2I);
 3811 opclass iRegIorL(iRegI, iRegL);
 3812 opclass iRegNorP(iRegN, iRegP);
 3813 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
 3814 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
 3815 opclass immIorL(immI, immL);
 3816 
 3817 //----------PIPELINE-----------------------------------------------------------
 3818 // Rules which define the behavior of the target architectures pipeline.
 3819 
 3820 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
 3821 //pipe_desc(ID, EX, MEM, WR);
 3822 #define ID   S0
 3823 #define EX   S1
 3824 #define MEM  S2
 3825 #define WR   S3
 3826 
 3827 // Integer ALU reg operation
 3828 pipeline %{
 3829 
 3830 attributes %{
 3831   // RISC-V instructions are of fixed length
 3832   fixed_size_instructions;           // Fixed size instructions TODO does
 3833   max_instructions_per_bundle = 2;   // Generic RISC-V 1, Sifive Series 7 2
 3834   // RISC-V instructions come in 32-bit word units
 3835   instruction_unit_size = 4;         // An instruction is 4 bytes long
 3836   instruction_fetch_unit_size = 64;  // The processor fetches one line
 3837   instruction_fetch_units = 1;       // of 64 bytes
 3838 
 3839   // List of nop instructions
 3840   nops( MachNop );
 3841 %}
 3842 
 3843 // We don't use an actual pipeline model so don't care about resources
 3844 // or description. we do use pipeline classes to introduce fixed
 3845 // latencies
 3846 
 3847 //----------RESOURCES----------------------------------------------------------
 3848 // Resources are the functional units available to the machine
 3849 
 3850 // Generic RISC-V pipeline
 3851 // 1 decoder
 3852 // 1 instruction decoded per cycle
 3853 // 1 load/store ops per cycle, 1 branch, 1 FPU
 3854 // 1 mul, 1 div
 3855 
 3856 resources ( DECODE,
 3857             ALU,
 3858             MUL,
 3859             DIV,
 3860             BRANCH,
 3861             LDST,
 3862             FPU);
 3863 
 3864 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3865 // Pipeline Description specifies the stages in the machine's pipeline
 3866 
 3867 // Define the pipeline as a generic 6 stage pipeline
 3868 pipe_desc(S0, S1, S2, S3, S4, S5);
 3869 
 3870 //----------PIPELINE CLASSES---------------------------------------------------
 3871 // Pipeline Classes describe the stages in which input and output are
 3872 // referenced by the hardware pipeline.
 3873 
 3874 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
 3875 %{
 3876   single_instruction;
 3877   src1   : S1(read);
 3878   src2   : S2(read);
 3879   dst    : S5(write);
 3880   DECODE : ID;
 3881   FPU    : S5;
 3882 %}
 3883 
 3884 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
 3885 %{
 3886   src1   : S1(read);
 3887   src2   : S2(read);
 3888   dst    : S5(write);
 3889   DECODE : ID;
 3890   FPU    : S5;
 3891 %}
 3892 
 3893 pipe_class fp_uop_s(fRegF dst, fRegF src)
 3894 %{
 3895   single_instruction;
 3896   src    : S1(read);
 3897   dst    : S5(write);
 3898   DECODE : ID;
 3899   FPU    : S5;
 3900 %}
 3901 
 3902 pipe_class fp_uop_d(fRegD dst, fRegD src)
 3903 %{
 3904   single_instruction;
 3905   src    : S1(read);
 3906   dst    : S5(write);
 3907   DECODE : ID;
 3908   FPU    : S5;
 3909 %}
 3910 
 3911 pipe_class fp_d2f(fRegF dst, fRegD src)
 3912 %{
 3913   single_instruction;
 3914   src    : S1(read);
 3915   dst    : S5(write);
 3916   DECODE : ID;
 3917   FPU    : S5;
 3918 %}
 3919 
 3920 pipe_class fp_f2d(fRegD dst, fRegF src)
 3921 %{
 3922   single_instruction;
 3923   src    : S1(read);
 3924   dst    : S5(write);
 3925   DECODE : ID;
 3926   FPU    : S5;
 3927 %}
 3928 
 3929 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
 3930 %{
 3931   single_instruction;
 3932   src    : S1(read);
 3933   dst    : S5(write);
 3934   DECODE : ID;
 3935   FPU    : S5;
 3936 %}
 3937 
 3938 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
 3939 %{
 3940   single_instruction;
 3941   src    : S1(read);
 3942   dst    : S5(write);
 3943   DECODE : ID;
 3944   FPU    : S5;
 3945 %}
 3946 
 3947 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
 3948 %{
 3949   single_instruction;
 3950   src    : S1(read);
 3951   dst    : S5(write);
 3952   DECODE : ID;
 3953   FPU    : S5;
 3954 %}
 3955 
 3956 pipe_class fp_l2f(fRegF dst, iRegL src)
 3957 %{
 3958   single_instruction;
 3959   src    : S1(read);
 3960   dst    : S5(write);
 3961   DECODE : ID;
 3962   FPU    : S5;
 3963 %}
 3964 
 3965 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
 3966 %{
 3967   single_instruction;
 3968   src    : S1(read);
 3969   dst    : S5(write);
 3970   DECODE : ID;
 3971   FPU    : S5;
 3972 %}
 3973 
 3974 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
 3975 %{
 3976   single_instruction;
 3977   src    : S1(read);
 3978   dst    : S5(write);
 3979   DECODE : ID;
 3980   FPU    : S5;
 3981 %}
 3982 
 3983 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
 3984 %{
 3985   single_instruction;
 3986   src    : S1(read);
 3987   dst    : S5(write);
 3988   DECODE : ID;
 3989   FPU    : S5;
 3990 %}
 3991 
 3992 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
 3993 %{
 3994   single_instruction;
 3995   src    : S1(read);
 3996   dst    : S5(write);
 3997   DECODE : ID;
 3998   FPU    : S5;
 3999 %}
 4000 
 4001 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
 4002 %{
 4003   single_instruction;
 4004   src1   : S1(read);
 4005   src2   : S2(read);
 4006   dst    : S5(write);
 4007   DECODE : ID;
 4008   FPU    : S5;
 4009 %}
 4010 
 4011 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
 4012 %{
 4013   single_instruction;
 4014   src1   : S1(read);
 4015   src2   : S2(read);
 4016   dst    : S5(write);
 4017   DECODE : ID;
 4018   FPU    : S5;
 4019 %}
 4020 
 4021 pipe_class fp_sqrt_s(fRegF dst, fRegF src1, fRegF src2)
 4022 %{
 4023   single_instruction;
 4024   src1   : S1(read);
 4025   src2   : S2(read);
 4026   dst    : S5(write);
 4027   DECODE : ID;
 4028   FPU    : S5;
 4029 %}
 4030 
 4031 pipe_class fp_sqrt_d(fRegD dst, fRegD src1, fRegD src2)
 4032 %{
 4033   single_instruction;
 4034   src1   : S1(read);
 4035   src2   : S2(read);
 4036   dst    : S5(write);
 4037   DECODE : ID;
 4038   FPU    : S5;
 4039 %}
 4040 
 4041 pipe_class fp_load_constant_s(fRegF dst)
 4042 %{
 4043   single_instruction;
 4044   dst    : S5(write);
 4045   DECODE : ID;
 4046   FPU    : S5;
 4047 %}
 4048 
 4049 pipe_class fp_load_constant_d(fRegD dst)
 4050 %{
 4051   single_instruction;
 4052   dst    : S5(write);
 4053   DECODE : ID;
 4054   FPU    : S5;
 4055 %}
 4056 
 4057 pipe_class fp_load_mem_s(fRegF dst, memory mem)
 4058 %{
 4059   single_instruction;
 4060   mem    : S1(read);
 4061   dst    : S5(write);
 4062   DECODE : ID;
 4063   LDST   : MEM;
 4064 %}
 4065 
 4066 pipe_class fp_load_mem_d(fRegD dst, memory mem)
 4067 %{
 4068   single_instruction;
 4069   mem    : S1(read);
 4070   dst    : S5(write);
 4071   DECODE : ID;
 4072   LDST   : MEM;
 4073 %}
 4074 
 4075 pipe_class fp_store_reg_s(fRegF src, memory mem)
 4076 %{
 4077   single_instruction;
 4078   src    : S1(read);
 4079   mem    : S5(write);
 4080   DECODE : ID;
 4081   LDST   : MEM;
 4082 %}
 4083 
 4084 pipe_class fp_store_reg_d(fRegD src, memory mem)
 4085 %{
 4086   single_instruction;
 4087   src    : S1(read);
 4088   mem    : S5(write);
 4089   DECODE : ID;
 4090   LDST   : MEM;
 4091 %}
 4092 
 4093 //------- Integer ALU operations --------------------------
 4094 
 4095 // Integer ALU reg-reg operation
 4096 // Operands needs in ID, result generated in EX
 4097 // E.g.  ADD   Rd, Rs1, Rs2
 4098 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4099 %{
 4100   single_instruction;
 4101   dst    : EX(write);
 4102   src1   : ID(read);
 4103   src2   : ID(read);
 4104   DECODE : ID;
 4105   ALU    : EX;
 4106 %}
 4107 
 4108 // Integer ALU reg operation with constant shift
 4109 // E.g. SLLI    Rd, Rs1, #shift
 4110 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
 4111 %{
 4112   single_instruction;
 4113   dst    : EX(write);
 4114   src1   : ID(read);
 4115   DECODE : ID;
 4116   ALU    : EX;
 4117 %}
 4118 
 4119 // Integer ALU reg-reg operation with variable shift
 4120 // both operands must be available in ID
 4121 // E.g. SLL   Rd, Rs1, Rs2
 4122 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
 4123 %{
 4124   single_instruction;
 4125   dst    : EX(write);
 4126   src1   : ID(read);
 4127   src2   : ID(read);
 4128   DECODE : ID;
 4129   ALU    : EX;
 4130 %}
 4131 
 4132 // Integer ALU reg operation
 4133 // E.g. NEG   Rd, Rs2
 4134 pipe_class ialu_reg(iRegI dst, iRegI src)
 4135 %{
 4136   single_instruction;
 4137   dst    : EX(write);
 4138   src    : ID(read);
 4139   DECODE : ID;
 4140   ALU    : EX;
 4141 %}
 4142 
 4143 // Integer ALU reg immediate operation
 4144 // E.g. ADDI   Rd, Rs1, #imm
 4145 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
 4146 %{
 4147   single_instruction;
 4148   dst    : EX(write);
 4149   src1   : ID(read);
 4150   DECODE : ID;
 4151   ALU    : EX;
 4152 %}
 4153 
 4154 // Integer ALU immediate operation (no source operands)
 4155 // E.g. LI    Rd, #imm
 4156 pipe_class ialu_imm(iRegI dst)
 4157 %{
 4158   single_instruction;
 4159   dst    : EX(write);
 4160   DECODE : ID;
 4161   ALU    : EX;
 4162 %}
 4163 
 4164 //------- Multiply pipeline operations --------------------
 4165 
 4166 // Multiply reg-reg
 4167 // E.g. MULW   Rd, Rs1, Rs2
 4168 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4169 %{
 4170   single_instruction;
 4171   dst    : WR(write);
 4172   src1   : ID(read);
 4173   src2   : ID(read);
 4174   DECODE : ID;
 4175   MUL    : WR;
 4176 %}
 4177 
 4178 // E.g. MUL   RD, Rs1, Rs2
 4179 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4180 %{
 4181   single_instruction;
 4182   fixed_latency(3); // Maximum latency for 64 bit mul
 4183   dst    : WR(write);
 4184   src1   : ID(read);
 4185   src2   : ID(read);
 4186   DECODE : ID;
 4187   MUL    : WR;
 4188 %}
 4189 
 4190 //------- Divide pipeline operations --------------------
 4191 
 4192 // E.g. DIVW   Rd, Rs1, Rs2
 4193 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4194 %{
 4195   single_instruction;
 4196   fixed_latency(8); // Maximum latency for 32 bit divide
 4197   dst    : WR(write);
 4198   src1   : ID(read);
 4199   src2   : ID(read);
 4200   DECODE : ID;
 4201   DIV    : WR;
 4202 %}
 4203 
 4204 // E.g. DIV   RD, Rs1, Rs2
 4205 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
 4206 %{
 4207   single_instruction;
 4208   fixed_latency(16); // Maximum latency for 64 bit divide
 4209   dst    : WR(write);
 4210   src1   : ID(read);
 4211   src2   : ID(read);
 4212   DECODE : ID;
 4213   DIV    : WR;
 4214 %}
 4215 
 4216 //------- Load pipeline operations ------------------------
 4217 
 4218 // Load - reg, mem
 4219 // E.g. LA    Rd, mem
 4220 pipe_class iload_reg_mem(iRegI dst, memory mem)
 4221 %{
 4222   single_instruction;
 4223   dst    : WR(write);
 4224   mem    : ID(read);
 4225   DECODE : ID;
 4226   LDST   : MEM;
 4227 %}
 4228 
 4229 // Load - reg, reg
 4230 // E.g. LD    Rd, Rs
 4231 pipe_class iload_reg_reg(iRegI dst, iRegI src)
 4232 %{
 4233   single_instruction;
 4234   dst    : WR(write);
 4235   src    : ID(read);
 4236   DECODE : ID;
 4237   LDST   : MEM;
 4238 %}
 4239 
 4240 //------- Store pipeline operations -----------------------
 4241 
 4242 // Store - zr, mem
 4243 // E.g. SD    zr, mem
 4244 pipe_class istore_mem(memory mem)
 4245 %{
 4246   single_instruction;
 4247   mem    : ID(read);
 4248   DECODE : ID;
 4249   LDST   : MEM;
 4250 %}
 4251 
 4252 // Store - reg, mem
 4253 // E.g. SD    Rs, mem
 4254 pipe_class istore_reg_mem(iRegI src, memory mem)
 4255 %{
 4256   single_instruction;
 4257   mem    : ID(read);
 4258   src    : EX(read);
 4259   DECODE : ID;
 4260   LDST   : MEM;
 4261 %}
 4262 
 4263 // Store - reg, reg
 4264 // E.g. SD    Rs2, Rs1
 4265 pipe_class istore_reg_reg(iRegI dst, iRegI src)
 4266 %{
 4267   single_instruction;
 4268   dst    : ID(read);
 4269   src    : EX(read);
 4270   DECODE : ID;
 4271   LDST   : MEM;
 4272 %}
 4273 
 4274 //------- Store pipeline operations -----------------------
 4275 
 4276 // Branch
 4277 pipe_class pipe_branch()
 4278 %{
 4279   single_instruction;
 4280   DECODE : ID;
 4281   BRANCH : EX;
 4282 %}
 4283 
 4284 // Branch
 4285 pipe_class pipe_branch_reg(iRegI src)
 4286 %{
 4287   single_instruction;
 4288   src    : ID(read);
 4289   DECODE : ID;
 4290   BRANCH : EX;
 4291 %}
 4292 
 4293 // Compare & Branch
 4294 // E.g. BEQ   Rs1, Rs2, L
 4295 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
 4296 %{
 4297   single_instruction;
 4298   src1   : ID(read);
 4299   src2   : ID(read);
 4300   DECODE : ID;
 4301   BRANCH : EX;
 4302 %}
 4303 
 4304 // E.g. BEQZ Rs, L
 4305 pipe_class pipe_cmpz_branch(iRegI src)
 4306 %{
 4307   single_instruction;
 4308   src    : ID(read);
 4309   DECODE : ID;
 4310   BRANCH : EX;
 4311 %}
 4312 
 4313 //------- Synchronisation operations ----------------------
 4314 // Any operation requiring serialization
 4315 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
 4316 pipe_class pipe_serial()
 4317 %{
 4318   single_instruction;
 4319   force_serialization;
 4320   fixed_latency(16);
 4321   DECODE : ID;
 4322   LDST   : MEM;
 4323 %}
 4324 
 4325 pipe_class pipe_slow()
 4326 %{
 4327   instruction_count(10);
 4328   multiple_bundles;
 4329   force_serialization;
 4330   fixed_latency(16);
 4331   DECODE : ID;
 4332   LDST   : MEM;
 4333 %}
 4334 
 4335 // Empty pipeline class
 4336 pipe_class pipe_class_empty()
 4337 %{
 4338   single_instruction;
 4339   fixed_latency(0);
 4340 %}
 4341 
 4342 // Default pipeline class.
 4343 pipe_class pipe_class_default()
 4344 %{
 4345   single_instruction;
 4346   fixed_latency(2);
 4347 %}
 4348 
 4349 // Pipeline class for compares.
 4350 pipe_class pipe_class_compare()
 4351 %{
 4352   single_instruction;
 4353   fixed_latency(16);
 4354 %}
 4355 
 4356 // Pipeline class for memory operations.
 4357 pipe_class pipe_class_memory()
 4358 %{
 4359   single_instruction;
 4360   fixed_latency(16);
 4361 %}
 4362 
 4363 // Pipeline class for call.
 4364 pipe_class pipe_class_call()
 4365 %{
 4366   single_instruction;
 4367   fixed_latency(100);
 4368 %}
 4369 
 4370 // Define the class for the Nop node.
 4371 define %{
 4372    MachNop = pipe_class_empty;
 4373 %}
 4374 %}
 4375 //----------INSTRUCTIONS-------------------------------------------------------
 4376 //
 4377 // match      -- States which machine-independent subtree may be replaced
 4378 //               by this instruction.
 4379 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4380 //               selection to identify a minimum cost tree of machine
 4381 //               instructions that matches a tree of machine-independent
 4382 //               instructions.
 4383 // format     -- A string providing the disassembly for this instruction.
 4384 //               The value of an instruction's operand may be inserted
 4385 //               by referring to it with a '$' prefix.
 4386 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4387 //               to within an encode class as $primary, $secondary, and $tertiary
 4388 //               rrspectively.  The primary opcode is commonly used to
 4389 //               indicate the type of machine instruction, while secondary
 4390 //               and tertiary are often used for prefix options or addressing
 4391 //               modes.
 4392 // ins_encode -- A list of encode classes with parameters. The encode class
 4393 //               name must have been defined in an 'enc_class' specification
 4394 //               in the encode section of the architecture description.
 4395 
 4396 // ============================================================================
 4397 // Memory (Load/Store) Instructions
 4398 
 4399 // Load Instructions
 4400 
 4401 // Load Byte (8 bit signed)
 4402 instruct loadB(iRegINoSp dst, memory mem)
 4403 %{
 4404   match(Set dst (LoadB mem));
 4405 
 4406   ins_cost(LOAD_COST);
 4407   format %{ "lb  $dst, $mem\t# byte, #@loadB" %}
 4408 
 4409   ins_encode %{
 4410     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4411   %}
 4412 
 4413   ins_pipe(iload_reg_mem);
 4414 %}
 4415 
 4416 // Load Byte (8 bit signed) into long
 4417 instruct loadB2L(iRegLNoSp dst, memory mem)
 4418 %{
 4419   match(Set dst (ConvI2L (LoadB mem)));
 4420 
 4421   ins_cost(LOAD_COST);
 4422   format %{ "lb  $dst, $mem\t# byte, #@loadB2L" %}
 4423 
 4424   ins_encode %{
 4425     __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4426   %}
 4427 
 4428   ins_pipe(iload_reg_mem);
 4429 %}
 4430 
 4431 // Load Byte (8 bit unsigned)
 4432 instruct loadUB(iRegINoSp dst, memory mem)
 4433 %{
 4434   match(Set dst (LoadUB mem));
 4435 
 4436   ins_cost(LOAD_COST);
 4437   format %{ "lbu  $dst, $mem\t# byte, #@loadUB" %}
 4438 
 4439   ins_encode %{
 4440     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4441   %}
 4442 
 4443   ins_pipe(iload_reg_mem);
 4444 %}
 4445 
 4446 // Load Byte (8 bit unsigned) into long
 4447 instruct loadUB2L(iRegLNoSp dst, memory mem)
 4448 %{
 4449   match(Set dst (ConvI2L (LoadUB mem)));
 4450 
 4451   ins_cost(LOAD_COST);
 4452   format %{ "lbu  $dst, $mem\t# byte, #@loadUB2L" %}
 4453 
 4454   ins_encode %{
 4455     __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4456   %}
 4457 
 4458   ins_pipe(iload_reg_mem);
 4459 %}
 4460 
 4461 // Load Short (16 bit signed)
 4462 instruct loadS(iRegINoSp dst, memory mem)
 4463 %{
 4464   match(Set dst (LoadS mem));
 4465 
 4466   ins_cost(LOAD_COST);
 4467   format %{ "lh  $dst, $mem\t# short, #@loadS" %}
 4468 
 4469   ins_encode %{
 4470     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4471   %}
 4472 
 4473   ins_pipe(iload_reg_mem);
 4474 %}
 4475 
 4476 // Load Short (16 bit signed) into long
 4477 instruct loadS2L(iRegLNoSp dst, memory mem)
 4478 %{
 4479   match(Set dst (ConvI2L (LoadS mem)));
 4480 
 4481   ins_cost(LOAD_COST);
 4482   format %{ "lh  $dst, $mem\t# short, #@loadS2L" %}
 4483 
 4484   ins_encode %{
 4485     __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4486   %}
 4487 
 4488   ins_pipe(iload_reg_mem);
 4489 %}
 4490 
 4491 // Load Char (16 bit unsigned)
 4492 instruct loadUS(iRegINoSp dst, memory mem)
 4493 %{
 4494   match(Set dst (LoadUS mem));
 4495 
 4496   ins_cost(LOAD_COST);
 4497   format %{ "lhu  $dst, $mem\t# short, #@loadUS" %}
 4498 
 4499   ins_encode %{
 4500     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4501   %}
 4502 
 4503   ins_pipe(iload_reg_mem);
 4504 %}
 4505 
 4506 // Load Short/Char (16 bit unsigned) into long
 4507 instruct loadUS2L(iRegLNoSp dst, memory mem)
 4508 %{
 4509   match(Set dst (ConvI2L (LoadUS mem)));
 4510 
 4511   ins_cost(LOAD_COST);
 4512   format %{ "lhu  $dst, $mem\t# short, #@loadUS2L" %}
 4513 
 4514   ins_encode %{
 4515     __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4516   %}
 4517 
 4518   ins_pipe(iload_reg_mem);
 4519 %}
 4520 
 4521 // Load Integer (32 bit signed)
 4522 instruct loadI(iRegINoSp dst, memory mem)
 4523 %{
 4524   match(Set dst (LoadI mem));
 4525 
 4526   ins_cost(LOAD_COST);
 4527   format %{ "lw  $dst, $mem\t# int, #@loadI" %}
 4528 
 4529   ins_encode %{
 4530     Assembler::CompressibleRegion cr(&_masm);
 4531     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4532   %}
 4533 
 4534   ins_pipe(iload_reg_mem);
 4535 %}
 4536 
 4537 // Load Integer (32 bit signed) into long
 4538 instruct loadI2L(iRegLNoSp dst, memory mem)
 4539 %{
 4540   match(Set dst (ConvI2L (LoadI mem)));
 4541 
 4542   ins_cost(LOAD_COST);
 4543   format %{ "lw  $dst, $mem\t# int, #@loadI2L" %}
 4544 
 4545   ins_encode %{
 4546     Assembler::CompressibleRegion cr(&_masm);
 4547     __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4548   %}
 4549 
 4550   ins_pipe(iload_reg_mem);
 4551 %}
 4552 
 4553 // Load Integer (32 bit unsigned) into long
 4554 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
 4555 %{
 4556   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4557 
 4558   ins_cost(LOAD_COST);
 4559   format %{ "lwu  $dst, $mem\t# int, #@loadUI2L" %}
 4560 
 4561   ins_encode %{
 4562     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4563   %}
 4564 
 4565   ins_pipe(iload_reg_mem);
 4566 %}
 4567 
 4568 // Load Long (64 bit signed)
 4569 instruct loadL(iRegLNoSp dst, memory mem)
 4570 %{
 4571   match(Set dst (LoadL mem));
 4572 
 4573   ins_cost(LOAD_COST);
 4574   format %{ "ld  $dst, $mem\t# int, #@loadL" %}
 4575 
 4576   ins_encode %{
 4577     Assembler::CompressibleRegion cr(&_masm);
 4578     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4579   %}
 4580 
 4581   ins_pipe(iload_reg_mem);
 4582 %}
 4583 
 4584 // Load Range
 4585 instruct loadRange(iRegINoSp dst, memory mem)
 4586 %{
 4587   match(Set dst (LoadRange mem));
 4588 
 4589   ins_cost(LOAD_COST);
 4590   format %{ "lwu  $dst, $mem\t# range, #@loadRange" %}
 4591 
 4592   ins_encode %{
 4593     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4594   %}
 4595 
 4596   ins_pipe(iload_reg_mem);
 4597 %}
 4598 
 4599 // Load Pointer
 4600 instruct loadP(iRegPNoSp dst, memory mem)
 4601 %{
 4602   match(Set dst (LoadP mem));
 4603   predicate(n->as_Load()->barrier_data() == 0);
 4604 
 4605   ins_cost(LOAD_COST);
 4606   format %{ "ld  $dst, $mem\t# ptr, #@loadP" %}
 4607 
 4608   ins_encode %{
 4609     Assembler::CompressibleRegion cr(&_masm);
 4610     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4611   %}
 4612 
 4613   ins_pipe(iload_reg_mem);
 4614 %}
 4615 
 4616 // Load Compressed Pointer
 4617 instruct loadN(iRegNNoSp dst, memory mem)
 4618 %{
 4619   match(Set dst (LoadN mem));
 4620 
 4621   ins_cost(LOAD_COST);
 4622   format %{ "lwu  $dst, $mem\t# loadN, compressed ptr, #@loadN" %}
 4623 
 4624   ins_encode %{
 4625     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4626   %}
 4627 
 4628   ins_pipe(iload_reg_mem);
 4629 %}
 4630 
 4631 // Load Klass Pointer
 4632 instruct loadKlass(iRegPNoSp dst, memory mem)
 4633 %{
 4634   match(Set dst (LoadKlass mem));
 4635 
 4636   ins_cost(LOAD_COST);
 4637   format %{ "ld  $dst, $mem\t# class, #@loadKlass" %}
 4638 
 4639   ins_encode %{
 4640     Assembler::CompressibleRegion cr(&_masm);
 4641     __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4642   %}
 4643 
 4644   ins_pipe(iload_reg_mem);
 4645 %}
 4646 
 4647 // Load Narrow Klass Pointer
 4648 instruct loadNKlass(iRegNNoSp dst, memory mem)
 4649 %{
 4650   match(Set dst (LoadNKlass mem));
 4651 
 4652   ins_cost(LOAD_COST);
 4653   format %{ "lwu  $dst, $mem\t# loadNKlass, compressed class ptr, #@loadNKlass" %}
 4654 
 4655   ins_encode %{
 4656     __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4657   %}
 4658 
 4659   ins_pipe(iload_reg_mem);
 4660 %}
 4661 
 4662 // Load Float
 4663 instruct loadF(fRegF dst, memory mem)
 4664 %{
 4665   match(Set dst (LoadF mem));
 4666 
 4667   ins_cost(LOAD_COST);
 4668   format %{ "flw  $dst, $mem\t# float, #@loadF" %}
 4669 
 4670   ins_encode %{
 4671     __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4672   %}
 4673 
 4674   ins_pipe(fp_load_mem_s);
 4675 %}
 4676 
 4677 // Load Double
 4678 instruct loadD(fRegD dst, memory mem)
 4679 %{
 4680   match(Set dst (LoadD mem));
 4681 
 4682   ins_cost(LOAD_COST);
 4683   format %{ "fld  $dst, $mem\t# double, #@loadD" %}
 4684 
 4685   ins_encode %{
 4686     Assembler::CompressibleRegion cr(&_masm);
 4687     __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4688   %}
 4689 
 4690   ins_pipe(fp_load_mem_d);
 4691 %}
 4692 
 4693 // Load Int Constant
 4694 instruct loadConI(iRegINoSp dst, immI src)
 4695 %{
 4696   match(Set dst src);
 4697 
 4698   ins_cost(ALU_COST);
 4699   format %{ "li $dst, $src\t# int, #@loadConI" %}
 4700 
 4701   ins_encode(riscv_enc_li_imm(dst, src));
 4702 
 4703   ins_pipe(ialu_imm);
 4704 %}
 4705 
 4706 // Load Long Constant
 4707 instruct loadConL(iRegLNoSp dst, immL src)
 4708 %{
 4709   match(Set dst src);
 4710 
 4711   ins_cost(ALU_COST);
 4712   format %{ "li $dst, $src\t# long, #@loadConL" %}
 4713 
 4714   ins_encode(riscv_enc_li_imm(dst, src));
 4715 
 4716   ins_pipe(ialu_imm);
 4717 %}
 4718 
 4719 // Load Pointer Constant
 4720 instruct loadConP(iRegPNoSp dst, immP con)
 4721 %{
 4722   match(Set dst con);
 4723 
 4724   ins_cost(ALU_COST);
 4725   format %{ "mv  $dst, $con\t# ptr, #@loadConP" %}
 4726 
 4727   ins_encode(riscv_enc_mov_p(dst, con));
 4728 
 4729   ins_pipe(ialu_imm);
 4730 %}
 4731 
 4732 // Load Null Pointer Constant
 4733 instruct loadConP0(iRegPNoSp dst, immP0 con)
 4734 %{
 4735   match(Set dst con);
 4736 
 4737   ins_cost(ALU_COST);
 4738   format %{ "mv  $dst, $con\t# NULL ptr, #@loadConP0" %}
 4739 
 4740   ins_encode(riscv_enc_mov_zero(dst));
 4741 
 4742   ins_pipe(ialu_imm);
 4743 %}
 4744 
 4745 // Load Pointer Constant One
 4746 instruct loadConP1(iRegPNoSp dst, immP_1 con)
 4747 %{
 4748   match(Set dst con);
 4749 
 4750   ins_cost(ALU_COST);
 4751   format %{ "mv  $dst, $con\t# load ptr constant one, #@loadConP1" %}
 4752 
 4753   ins_encode(riscv_enc_mov_p1(dst));
 4754 
 4755   ins_pipe(ialu_imm);
 4756 %}
 4757 
 4758 // Load Byte Map Base Constant
 4759 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
 4760 %{
 4761   match(Set dst con);
 4762   ins_cost(ALU_COST);
 4763   format %{ "mv  $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
 4764 
 4765   ins_encode(riscv_enc_mov_byte_map_base(dst));
 4766 
 4767   ins_pipe(ialu_imm);
 4768 %}
 4769 
 4770 // Load Narrow Pointer Constant
 4771 instruct loadConN(iRegNNoSp dst, immN con)
 4772 %{
 4773   match(Set dst con);
 4774 
 4775   ins_cost(ALU_COST * 4);
 4776   format %{ "mv  $dst, $con\t# compressed ptr, #@loadConN" %}
 4777 
 4778   ins_encode(riscv_enc_mov_n(dst, con));
 4779 
 4780   ins_pipe(ialu_imm);
 4781 %}
 4782 
 4783 // Load Narrow Null Pointer Constant
 4784 instruct loadConN0(iRegNNoSp dst, immN0 con)
 4785 %{
 4786   match(Set dst con);
 4787 
 4788   ins_cost(ALU_COST);
 4789   format %{ "mv  $dst, $con\t# compressed NULL ptr, #@loadConN0" %}
 4790 
 4791   ins_encode(riscv_enc_mov_zero(dst));
 4792 
 4793   ins_pipe(ialu_imm);
 4794 %}
 4795 
 4796 // Load Narrow Klass Constant
 4797 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
 4798 %{
 4799   match(Set dst con);
 4800 
 4801   ins_cost(ALU_COST * 6);
 4802   format %{ "mv  $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
 4803 
 4804   ins_encode(riscv_enc_mov_nk(dst, con));
 4805 
 4806   ins_pipe(ialu_imm);
 4807 %}
 4808 
 4809 // Load Float Constant
 4810 instruct loadConF(fRegF dst, immF con) %{
 4811   match(Set dst con);
 4812 
 4813   ins_cost(LOAD_COST);
 4814   format %{
 4815     "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
 4816   %}
 4817 
 4818   ins_encode %{
 4819     __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
 4820   %}
 4821 
 4822   ins_pipe(fp_load_constant_s);
 4823 %}
 4824 
 4825 instruct loadConF0(fRegF dst, immF0 con) %{
 4826   match(Set dst con);
 4827 
 4828   ins_cost(XFER_COST);
 4829 
 4830   format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
 4831 
 4832   ins_encode %{
 4833     __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
 4834   %}
 4835 
 4836   ins_pipe(fp_load_constant_s);
 4837 %}
 4838 
 4839 // Load Double Constant
 4840 instruct loadConD(fRegD dst, immD con) %{
 4841   match(Set dst con);
 4842 
 4843   ins_cost(LOAD_COST);
 4844   format %{
 4845     "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
 4846   %}
 4847 
 4848   ins_encode %{
 4849     __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
 4850   %}
 4851 
 4852   ins_pipe(fp_load_constant_d);
 4853 %}
 4854 
 4855 instruct loadConD0(fRegD dst, immD0 con) %{
 4856   match(Set dst con);
 4857 
 4858   ins_cost(XFER_COST);
 4859 
 4860   format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
 4861 
 4862   ins_encode %{
 4863     __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
 4864   %}
 4865 
 4866   ins_pipe(fp_load_constant_d);
 4867 %}
 4868 
 4869 // Store Instructions
 4870 // Store CMS card-mark Immediate
 4871 instruct storeimmCM0(immI0 zero, memory mem)
 4872 %{
 4873   match(Set mem (StoreCM mem zero));
 4874 
 4875   ins_cost(STORE_COST);
 4876   format %{ "storestore (elided)\n\t"
 4877             "sb zr, $mem\t# byte, #@storeimmCM0" %}
 4878 
 4879   ins_encode %{
 4880     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4881   %}
 4882 
 4883   ins_pipe(istore_mem);
 4884 %}
 4885 
 4886 // Store CMS card-mark Immediate with intervening StoreStore
 4887 // needed when using CMS with no conditional card marking
 4888 instruct storeimmCM0_ordered(immI0 zero, memory mem)
 4889 %{
 4890   match(Set mem (StoreCM mem zero));
 4891 
 4892   ins_cost(ALU_COST + STORE_COST);
 4893   format %{ "membar(StoreStore)\n\t"
 4894             "sb zr, $mem\t# byte, #@storeimmCM0_ordered" %}
 4895 
 4896   ins_encode %{
 4897     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 4898     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4899   %}
 4900 
 4901   ins_pipe(istore_mem);
 4902 %}
 4903 
 4904 // Store Byte
 4905 instruct storeB(iRegIorL2I src, memory mem)
 4906 %{
 4907   match(Set mem (StoreB mem src));
 4908 
 4909   ins_cost(STORE_COST);
 4910   format %{ "sb  $src, $mem\t# byte, #@storeB" %}
 4911 
 4912   ins_encode %{
 4913     __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4914   %}
 4915 
 4916   ins_pipe(istore_reg_mem);
 4917 %}
 4918 
 4919 instruct storeimmB0(immI0 zero, memory mem)
 4920 %{
 4921   match(Set mem (StoreB mem zero));
 4922 
 4923   ins_cost(STORE_COST);
 4924   format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
 4925 
 4926   ins_encode %{
 4927     __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
 4928   %}
 4929 
 4930   ins_pipe(istore_mem);
 4931 %}
 4932 
 4933 // Store Char/Short
 4934 instruct storeC(iRegIorL2I src, memory mem)
 4935 %{
 4936   match(Set mem (StoreC mem src));
 4937 
 4938   ins_cost(STORE_COST);
 4939   format %{ "sh  $src, $mem\t# short, #@storeC" %}
 4940 
 4941   ins_encode %{
 4942     __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4943   %}
 4944 
 4945   ins_pipe(istore_reg_mem);
 4946 %}
 4947 
 4948 instruct storeimmC0(immI0 zero, memory mem)
 4949 %{
 4950   match(Set mem (StoreC mem zero));
 4951 
 4952   ins_cost(STORE_COST);
 4953   format %{ "sh  zr, $mem\t# short, #@storeimmC0" %}
 4954 
 4955   ins_encode %{
 4956     __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
 4957   %}
 4958 
 4959   ins_pipe(istore_mem);
 4960 %}
 4961 
 4962 // Store Integer
 4963 instruct storeI(iRegIorL2I src, memory mem)
 4964 %{
 4965   match(Set mem(StoreI mem src));
 4966 
 4967   ins_cost(STORE_COST);
 4968   format %{ "sw  $src, $mem\t# int, #@storeI" %}
 4969 
 4970   ins_encode %{
 4971     Assembler::CompressibleRegion cr(&_masm);
 4972     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 4973   %}
 4974 
 4975   ins_pipe(istore_reg_mem);
 4976 %}
 4977 
 4978 instruct storeimmI0(immI0 zero, memory mem)
 4979 %{
 4980   match(Set mem(StoreI mem zero));
 4981 
 4982   ins_cost(STORE_COST);
 4983   format %{ "sw  zr, $mem\t# int, #@storeimmI0" %}
 4984 
 4985   ins_encode %{
 4986     __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
 4987   %}
 4988 
 4989   ins_pipe(istore_mem);
 4990 %}
 4991 
 4992 // Store Long (64 bit signed)
 4993 instruct storeL(iRegL src, memory mem)
 4994 %{
 4995   match(Set mem (StoreL mem src));
 4996 
 4997   ins_cost(STORE_COST);
 4998   format %{ "sd  $src, $mem\t# long, #@storeL" %}
 4999 
 5000   ins_encode %{
 5001     Assembler::CompressibleRegion cr(&_masm);
 5002     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5003   %}
 5004 
 5005   ins_pipe(istore_reg_mem);
 5006 %}
 5007 
 5008 // Store Long (64 bit signed)
 5009 instruct storeimmL0(immL0 zero, memory mem)
 5010 %{
 5011   match(Set mem (StoreL mem zero));
 5012 
 5013   ins_cost(STORE_COST);
 5014   format %{ "sd  zr, $mem\t# long, #@storeimmL0" %}
 5015 
 5016   ins_encode %{
 5017     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5018   %}
 5019 
 5020   ins_pipe(istore_mem);
 5021 %}
 5022 
 5023 // Store Pointer
 5024 instruct storeP(iRegP src, memory mem)
 5025 %{
 5026   match(Set mem (StoreP mem src));
 5027 
 5028   ins_cost(STORE_COST);
 5029   format %{ "sd  $src, $mem\t# ptr, #@storeP" %}
 5030 
 5031   ins_encode %{
 5032     Assembler::CompressibleRegion cr(&_masm);
 5033     __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5034   %}
 5035 
 5036   ins_pipe(istore_reg_mem);
 5037 %}
 5038 
 5039 // Store Pointer
 5040 instruct storeimmP0(immP0 zero, memory mem)
 5041 %{
 5042   match(Set mem (StoreP mem zero));
 5043 
 5044   ins_cost(STORE_COST);
 5045   format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
 5046 
 5047   ins_encode %{
 5048     __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
 5049   %}
 5050 
 5051   ins_pipe(istore_mem);
 5052 %}
 5053 
 5054 // Store Compressed Pointer
 5055 instruct storeN(iRegN src, memory mem)
 5056 %{
 5057   match(Set mem (StoreN mem src));
 5058 
 5059   ins_cost(STORE_COST);
 5060   format %{ "sw  $src, $mem\t# compressed ptr, #@storeN" %}
 5061 
 5062   ins_encode %{
 5063     Assembler::CompressibleRegion cr(&_masm);
 5064     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5065   %}
 5066 
 5067   ins_pipe(istore_reg_mem);
 5068 %}
 5069 
 5070 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
 5071 %{
 5072   match(Set mem (StoreN mem zero));
 5073 
 5074   ins_cost(STORE_COST);
 5075   format %{ "sw  rheapbase, $mem\t# compressed ptr (rheapbase==0), #@storeImmN0" %}
 5076 
 5077   ins_encode %{
 5078     __ sw(as_Register($heapbase$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5079   %}
 5080 
 5081   ins_pipe(istore_reg_mem);
 5082 %}
 5083 
 5084 // Store Float
 5085 instruct storeF(fRegF src, memory mem)
 5086 %{
 5087   match(Set mem (StoreF mem src));
 5088 
 5089   ins_cost(STORE_COST);
 5090   format %{ "fsw  $src, $mem\t# float, #@storeF" %}
 5091 
 5092   ins_encode %{
 5093     __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5094   %}
 5095 
 5096   ins_pipe(fp_store_reg_s);
 5097 %}
 5098 
 5099 // Store Double
 5100 instruct storeD(fRegD src, memory mem)
 5101 %{
 5102   match(Set mem (StoreD mem src));
 5103 
 5104   ins_cost(STORE_COST);
 5105   format %{ "fsd  $src, $mem\t# double, #@storeD" %}
 5106 
 5107   ins_encode %{
 5108     Assembler::CompressibleRegion cr(&_masm);
 5109     __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5110   %}
 5111 
 5112   ins_pipe(fp_store_reg_d);
 5113 %}
 5114 
 5115 // Store Compressed Klass Pointer
 5116 instruct storeNKlass(iRegN src, memory mem)
 5117 %{
 5118   match(Set mem (StoreNKlass mem src));
 5119 
 5120   ins_cost(STORE_COST);
 5121   format %{ "sw  $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
 5122 
 5123   ins_encode %{
 5124     Assembler::CompressibleRegion cr(&_masm);
 5125     __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
 5126   %}
 5127 
 5128   ins_pipe(istore_reg_mem);
 5129 %}
 5130 
 5131 // ============================================================================
 5132 // Atomic operation instructions
 5133 //
 5134 // Intel and SPARC both implement Ideal Node LoadPLocked and
 5135 // Store{PIL}Conditional instructions using a normal load for the
 5136 // LoadPLocked and a CAS for the Store{PIL}Conditional.
 5137 //
 5138 // The ideal code appears only to use LoadPLocked/storePConditional as a
 5139 // pair to lock object allocations from Eden space when not using
 5140 // TLABs.
 5141 //
 5142 // There does not appear to be a Load{IL}Locked Ideal Node and the
 5143 // Ideal code appears to use Store{IL}Conditional as an alias for CAS
 5144 // and to use StoreIConditional only for 32-bit and StoreLConditional
 5145 // only for 64-bit.
 5146 //
 5147 // We implement LoadPLocked and storePConditional instructions using,
 5148 // respectively the RISCV hw load-reserve and store-conditional
 5149 // instructions. Whereas we must implement each of
 5150 // Store{IL}Conditional using a CAS which employs a pair of
 5151 // instructions comprising a load-reserve followed by a
 5152 // store-conditional.
 5153 
 5154 
 5155 // Locked-load (load reserved) of the current heap-top
 5156 // used when updating the eden heap top
 5157 // implemented using lr_d on RISCV64
 5158 instruct loadPLocked(iRegPNoSp dst, indirect mem)
 5159 %{
 5160   match(Set dst (LoadPLocked mem));
 5161 
 5162   ins_cost(ALU_COST * 2 + LOAD_COST);
 5163 
 5164   format %{ "lr.d $dst, $mem\t# ptr load reserved, #@loadPLocked" %}
 5165 
 5166   ins_encode %{
 5167     __ la(t0, Address(as_Register($mem$$base), $mem$$disp));
 5168     __ lr_d($dst$$Register, t0, Assembler::aq);
 5169   %}
 5170 
 5171   ins_pipe(pipe_serial);
 5172 %}
 5173 
 5174 // Conditional-store of the updated heap-top.
 5175 // Used during allocation of the shared heap.
 5176 // implemented using sc_d on RISCV64.
 5177 instruct storePConditional(memory heap_top_ptr, iRegP oldval, iRegP newval, rFlagsReg cr)
 5178 %{
 5179   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
 5180 
 5181   ins_cost(ALU_COST * 2 + STORE_COST);
 5182 
 5183   format %{
 5184     "sc_d t1, $newval $heap_top_ptr,\t# ptr store conditional, #@storePConditional"
 5185   %}
 5186 
 5187   ins_encode %{
 5188     __ la(t0, Address(as_Register($heap_top_ptr$$base), $heap_top_ptr$$disp));
 5189     __ sc_d($cr$$Register, $newval$$Register, t0, Assembler::rl);
 5190   %}
 5191 
 5192   ins_pipe(pipe_serial);
 5193 %}
 5194 
 5195 instruct storeLConditional(indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr)
 5196 %{
 5197   match(Set cr (StoreLConditional mem (Binary oldval newval)));
 5198 
 5199   ins_cost(LOAD_COST + STORE_COST + 2 * BRANCH_COST);
 5200 
 5201   format %{
 5202     "cmpxchg t1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
 5203     "xorr $cr, $cr, $oldval\t# $cr == 0 on successful write, #@storeLConditional"
 5204   %}
 5205 
 5206   ins_encode %{
 5207     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5208                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $cr$$Register);
 5209     __ xorr($cr$$Register,$cr$$Register, $oldval$$Register);
 5210   %}
 5211 
 5212   ins_pipe(pipe_slow);
 5213 %}
 5214 
 5215 // storeIConditional also has acquire semantics, for no better reason
 5216 // than matching storeLConditional.
 5217 instruct storeIConditional(indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr)
 5218 %{
 5219   match(Set cr (StoreIConditional mem (Binary oldval newval)));
 5220 
 5221   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2);
 5222 
 5223   format %{
 5224     "cmpxchgw t1, $mem, $oldval, $newval, $mem\t# if $mem == $oldval then $mem <-- $newval"
 5225     "xorr $cr, $cr, $oldval\t# $cr == 0 on successful write, #@storeIConditional"
 5226   %}
 5227 
 5228   ins_encode %{
 5229     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5230                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $cr$$Register);
 5231     __ xorr($cr$$Register,$cr$$Register, $oldval$$Register);
 5232   %}
 5233 
 5234   ins_pipe(pipe_slow);
 5235 %}
 5236 
 5237 // standard CompareAndSwapX when we are using barriers
 5238 // these have higher priority than the rules selected by a predicate
 5239 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5240                          iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5241 %{
 5242   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5243 
 5244   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5245 
 5246   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5247 
 5248   format %{
 5249     "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5250     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
 5251   %}
 5252 
 5253   ins_encode %{
 5254     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5255                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5256                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5257   %}
 5258 
 5259   ins_pipe(pipe_slow);
 5260 %}
 5261 
 5262 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5263                          iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5264 %{
 5265   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5266 
 5267   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5268 
 5269   effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
 5270 
 5271   format %{
 5272     "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5273     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
 5274   %}
 5275 
 5276   ins_encode %{
 5277     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5278                             Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
 5279                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5280   %}
 5281 
 5282   ins_pipe(pipe_slow);
 5283 %}
 5284 
 5285 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval)
 5286 %{
 5287   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5288 
 5289   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5290 
 5291   format %{
 5292     "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5293     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
 5294   %}
 5295 
 5296   ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
 5297 
 5298   ins_pipe(pipe_slow);
 5299 %}
 5300 
 5301 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval)
 5302 %{
 5303   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5304 
 5305   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5306 
 5307   format %{
 5308     "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5309     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
 5310   %}
 5311 
 5312   ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
 5313 
 5314   ins_pipe(pipe_slow);
 5315 %}
 5316 
 5317 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5318 %{
 5319   predicate(n->as_LoadStore()->barrier_data() == 0);
 5320 
 5321   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5322 
 5323   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5324 
 5325   format %{
 5326     "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5327     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
 5328   %}
 5329 
 5330   ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
 5331 
 5332   ins_pipe(pipe_slow);
 5333 %}
 5334 
 5335 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval)
 5336 %{
 5337   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5338 
 5339   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5340 
 5341   format %{
 5342     "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5343     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
 5344   %}
 5345 
 5346   ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
 5347 
 5348   ins_pipe(pipe_slow);
 5349 %}
 5350 
 5351 // alternative CompareAndSwapX when we are eliding barriers
 5352 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5353                             iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5354 %{
 5355   predicate(needs_acquiring_load_reserved(n));
 5356 
 5357   match(Set res (CompareAndSwapB mem (Binary oldval newval)));
 5358 
 5359   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
 5360 
 5361   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5362 
 5363   format %{
 5364     "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
 5365     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
 5366   %}
 5367 
 5368   ins_encode %{
 5369     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5370                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5371                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5372   %}
 5373 
 5374   ins_pipe(pipe_slow);
 5375 %}
 5376 
 5377 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5378                             iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5379 %{
 5380   predicate(needs_acquiring_load_reserved(n));
 5381 
 5382   match(Set res (CompareAndSwapS mem (Binary oldval newval)));
 5383 
 5384   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
 5385 
 5386   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5387 
 5388   format %{
 5389     "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
 5390     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
 5391   %}
 5392 
 5393   ins_encode %{
 5394     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5395                             Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
 5396                             true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5397   %}
 5398 
 5399   ins_pipe(pipe_slow);
 5400 %}
 5401 
 5402 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval)
 5403 %{
 5404   predicate(needs_acquiring_load_reserved(n));
 5405 
 5406   match(Set res (CompareAndSwapI mem (Binary oldval newval)));
 5407 
 5408   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5409 
 5410   format %{
 5411     "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
 5412     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
 5413   %}
 5414 
 5415   ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
 5416 
 5417   ins_pipe(pipe_slow);
 5418 %}
 5419 
 5420 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval)
 5421 %{
 5422   predicate(needs_acquiring_load_reserved(n));
 5423 
 5424   match(Set res (CompareAndSwapL mem (Binary oldval newval)));
 5425 
 5426   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5427 
 5428   format %{
 5429     "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
 5430     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
 5431   %}
 5432 
 5433   ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
 5434 
 5435   ins_pipe(pipe_slow);
 5436 %}
 5437 
 5438 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5439 %{
 5440   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5441 
 5442   match(Set res (CompareAndSwapP mem (Binary oldval newval)));
 5443 
 5444   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
 5445 
 5446   format %{
 5447     "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
 5448     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
 5449   %}
 5450 
 5451   ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
 5452 
 5453   ins_pipe(pipe_slow);
 5454 %}
 5455 
 5456 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval)
 5457 %{
 5458   predicate(needs_acquiring_load_reserved(n));
 5459 
 5460   match(Set res (CompareAndSwapN mem (Binary oldval newval)));
 5461 
 5462   ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
 5463 
 5464   format %{
 5465     "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
 5466     "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
 5467   %}
 5468 
 5469   ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
 5470 
 5471   ins_pipe(pipe_slow);
 5472 %}
 5473 
 5474 // Sundry CAS operations.  Note that release is always true,
 5475 // regardless of the memory ordering of the CAS.  This is because we
 5476 // need the volatile case to be sequentially consistent but there is
 5477 // no trailing StoreLoad barrier emitted by C2.  Unfortunately we
 5478 // can't check the type of memory ordering here, so we always emit a
 5479 // sc_d(w) with rl bit set.
 5480 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5481                              iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5482 %{
 5483   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5484 
 5485   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5486 
 5487   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5488 
 5489   format %{
 5490     "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
 5491   %}
 5492 
 5493   ins_encode %{
 5494     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5495                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5496                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5497   %}
 5498 
 5499   ins_pipe(pipe_slow);
 5500 %}
 5501 
 5502 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5503                              iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5504 %{
 5505   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5506 
 5507   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5508 
 5509   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5510 
 5511   format %{
 5512     "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
 5513   %}
 5514 
 5515   ins_encode %{
 5516     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5517                             /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5518                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5519   %}
 5520 
 5521   ins_pipe(pipe_slow);
 5522 %}
 5523 
 5524 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5525 %{
 5526   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5527 
 5528   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5529 
 5530   effect(TEMP_DEF res);
 5531 
 5532   format %{
 5533     "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
 5534   %}
 5535 
 5536   ins_encode %{
 5537     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5538                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5539   %}
 5540 
 5541   ins_pipe(pipe_slow);
 5542 %}
 5543 
 5544 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5545 %{
 5546   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5547 
 5548   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5549 
 5550   effect(TEMP_DEF res);
 5551 
 5552   format %{
 5553     "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
 5554   %}
 5555 
 5556   ins_encode %{
 5557     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5558                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5559   %}
 5560 
 5561   ins_pipe(pipe_slow);
 5562 %}
 5563 
 5564 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5565 %{
 5566   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5567 
 5568   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
 5569 
 5570   effect(TEMP_DEF res);
 5571 
 5572   format %{
 5573     "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
 5574   %}
 5575 
 5576   ins_encode %{
 5577     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5578                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5579   %}
 5580 
 5581   ins_pipe(pipe_slow);
 5582 %}
 5583 
 5584 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5585 %{
 5586   predicate(n->as_LoadStore()->barrier_data() == 0);
 5587   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5588 
 5589   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5590 
 5591   effect(TEMP_DEF res);
 5592 
 5593   format %{
 5594     "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
 5595   %}
 5596 
 5597   ins_encode %{
 5598     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5599                /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5600   %}
 5601 
 5602   ins_pipe(pipe_slow);
 5603 %}
 5604 
 5605 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5606                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5607 %{
 5608   predicate(needs_acquiring_load_reserved(n));
 5609 
 5610   match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
 5611 
 5612   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
 5613 
 5614   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5615 
 5616   format %{
 5617     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
 5618   %}
 5619 
 5620   ins_encode %{
 5621     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5622                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5623                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5624   %}
 5625 
 5626   ins_pipe(pipe_slow);
 5627 %}
 5628 
 5629 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5630                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5631 %{
 5632   predicate(needs_acquiring_load_reserved(n));
 5633 
 5634   match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
 5635 
 5636   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
 5637 
 5638   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5639 
 5640   format %{
 5641     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
 5642   %}
 5643 
 5644   ins_encode %{
 5645     __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5646                             /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5647                             /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5648   %}
 5649 
 5650   ins_pipe(pipe_slow);
 5651 %}
 5652 
 5653 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5654 %{
 5655   predicate(needs_acquiring_load_reserved(n));
 5656 
 5657   match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
 5658 
 5659   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5660 
 5661   effect(TEMP_DEF res);
 5662 
 5663   format %{
 5664     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
 5665   %}
 5666 
 5667   ins_encode %{
 5668     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5669                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5670   %}
 5671 
 5672   ins_pipe(pipe_slow);
 5673 %}
 5674 
 5675 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
 5676 %{
 5677   predicate(needs_acquiring_load_reserved(n));
 5678 
 5679   match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
 5680 
 5681   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5682 
 5683   effect(TEMP_DEF res);
 5684 
 5685   format %{
 5686     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
 5687   %}
 5688 
 5689   ins_encode %{
 5690     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5691                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5692   %}
 5693 
 5694   ins_pipe(pipe_slow);
 5695 %}
 5696 
 5697 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
 5698 %{
 5699   predicate(needs_acquiring_load_reserved(n));
 5700 
 5701   match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
 5702 
 5703   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5704 
 5705   effect(TEMP_DEF res);
 5706 
 5707   format %{
 5708     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
 5709   %}
 5710 
 5711   ins_encode %{
 5712     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5713                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5714   %}
 5715 
 5716   ins_pipe(pipe_slow);
 5717 %}
 5718 
 5719 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
 5720 %{
 5721   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5722 
 5723   match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
 5724 
 5725   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
 5726 
 5727   effect(TEMP_DEF res);
 5728 
 5729   format %{
 5730     "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
 5731   %}
 5732 
 5733   ins_encode %{
 5734     __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5735                /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5736   %}
 5737 
 5738   ins_pipe(pipe_slow);
 5739 %}
 5740 
 5741 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5742                              iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5743 %{
 5744   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5745 
 5746   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5747 
 5748   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5749 
 5750   format %{
 5751     "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5752     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapB"
 5753   %}
 5754 
 5755   ins_encode %{
 5756     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5757                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5758                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5759     __ xori($res$$Register, $res$$Register, 1);
 5760   %}
 5761 
 5762   ins_pipe(pipe_slow);
 5763 %}
 5764 
 5765 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5766                              iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5767 %{
 5768   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5769 
 5770   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5771 
 5772   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5773 
 5774   format %{
 5775     "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5776     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapS"
 5777   %}
 5778 
 5779   ins_encode %{
 5780     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5781                                  /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
 5782                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5783     __ xori($res$$Register, $res$$Register, 1);
 5784   %}
 5785 
 5786   ins_pipe(pipe_slow);
 5787 %}
 5788 
 5789 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5790 %{
 5791   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5792 
 5793   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5794 
 5795   format %{
 5796     "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5797     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapI"
 5798   %}
 5799 
 5800   ins_encode %{
 5801     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5802                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5803     __ xori($res$$Register, $res$$Register, 1);
 5804   %}
 5805 
 5806   ins_pipe(pipe_slow);
 5807 %}
 5808 
 5809 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5810 %{
 5811   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5812 
 5813   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5814 
 5815   format %{
 5816     "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5817     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapL"
 5818   %}
 5819 
 5820   ins_encode %{
 5821     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5822                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5823     __ xori($res$$Register, $res$$Register, 1);
 5824   %}
 5825 
 5826   ins_pipe(pipe_slow);
 5827 %}
 5828 
 5829 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5830 %{
 5831   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5832 
 5833   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5834 
 5835   format %{
 5836     "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5837     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapN"
 5838   %}
 5839 
 5840   ins_encode %{
 5841     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5842                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5843     __ xori($res$$Register, $res$$Register, 1);
 5844   %}
 5845 
 5846   ins_pipe(pipe_slow);
 5847 %}
 5848 
 5849 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5850 %{
 5851   predicate(n->as_LoadStore()->barrier_data() == 0);
 5852   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5853 
 5854   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5855 
 5856   format %{
 5857     "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5858     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapP"
 5859   %}
 5860 
 5861   ins_encode %{
 5862     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5863                     /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
 5864     __ xori($res$$Register, $res$$Register, 1);
 5865   %}
 5866 
 5867   ins_pipe(pipe_slow);
 5868 %}
 5869 
 5870 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5871                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5872 %{
 5873   predicate(needs_acquiring_load_reserved(n));
 5874 
 5875   match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
 5876 
 5877   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
 5878 
 5879   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5880 
 5881   format %{
 5882     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5883     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapBAcq"
 5884   %}
 5885 
 5886   ins_encode %{
 5887     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
 5888                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5889                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5890     __ xori($res$$Register, $res$$Register, 1);
 5891   %}
 5892 
 5893   ins_pipe(pipe_slow);
 5894 %}
 5895 
 5896 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
 5897                                 iRegI tmp1, iRegI tmp2, iRegI tmp3, rFlagsReg cr)
 5898 %{
 5899   predicate(needs_acquiring_load_reserved(n));
 5900 
 5901   match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
 5902 
 5903   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
 5904 
 5905   effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
 5906 
 5907   format %{
 5908     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5909     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapSAcq"
 5910   %}
 5911 
 5912   ins_encode %{
 5913     __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
 5914                                  /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
 5915                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
 5916     __ xori($res$$Register, $res$$Register, 1);
 5917   %}
 5918 
 5919   ins_pipe(pipe_slow);
 5920 %}
 5921 
 5922 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
 5923 %{
 5924   predicate(needs_acquiring_load_reserved(n));
 5925 
 5926   match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
 5927 
 5928   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5929 
 5930   format %{
 5931     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5932     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapIAcq"
 5933   %}
 5934 
 5935   ins_encode %{
 5936     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
 5937                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5938     __ xori($res$$Register, $res$$Register, 1);
 5939   %}
 5940 
 5941   ins_pipe(pipe_slow);
 5942 %}
 5943 
 5944 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
 5945 %{
 5946   predicate(needs_acquiring_load_reserved(n));
 5947 
 5948   match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
 5949 
 5950   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5951 
 5952   format %{
 5953     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5954     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapLAcq"
 5955   %}
 5956 
 5957   ins_encode %{
 5958     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 5959                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5960     __ xori($res$$Register, $res$$Register, 1);
 5961   %}
 5962 
 5963   ins_pipe(pipe_slow);
 5964 %}
 5965 
 5966 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
 5967 %{
 5968   predicate(needs_acquiring_load_reserved(n));
 5969 
 5970   match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
 5971 
 5972   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
 5973 
 5974   format %{
 5975     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5976     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapNAcq"
 5977   %}
 5978 
 5979   ins_encode %{
 5980     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
 5981                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 5982     __ xori($res$$Register, $res$$Register, 1);
 5983   %}
 5984 
 5985   ins_pipe(pipe_slow);
 5986 %}
 5987 
 5988 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
 5989 %{
 5990   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 5991 
 5992   match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
 5993 
 5994   ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
 5995 
 5996   format %{
 5997     "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
 5998     "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
 5999   %}
 6000 
 6001   ins_encode %{
 6002     __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
 6003                     /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
 6004     __ xori($res$$Register, $res$$Register, 1);
 6005   %}
 6006 
 6007   ins_pipe(pipe_slow);
 6008 %}
 6009 
 6010 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
 6011 %{
 6012   match(Set prev (GetAndSetI mem newv));
 6013 
 6014   ins_cost(ALU_COST);
 6015 
 6016   format %{ "atomic_xchgw  $prev, $newv, [$mem]\t#@get_and_setI" %}
 6017 
 6018   ins_encode %{
 6019     __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6020   %}
 6021 
 6022   ins_pipe(pipe_serial);
 6023 %}
 6024 
 6025 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
 6026 %{
 6027   match(Set prev (GetAndSetL mem newv));
 6028 
 6029   ins_cost(ALU_COST);
 6030 
 6031   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setL" %}
 6032 
 6033   ins_encode %{
 6034     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6035   %}
 6036 
 6037   ins_pipe(pipe_serial);
 6038 %}
 6039 
 6040 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
 6041 %{
 6042   match(Set prev (GetAndSetN mem newv));
 6043 
 6044   ins_cost(ALU_COST);
 6045 
 6046   format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
 6047 
 6048   ins_encode %{
 6049     __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6050   %}
 6051 
 6052   ins_pipe(pipe_serial);
 6053 %}
 6054 
 6055 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
 6056 %{
 6057   predicate(n->as_LoadStore()->barrier_data() == 0);
 6058   match(Set prev (GetAndSetP mem newv));
 6059 
 6060   ins_cost(ALU_COST);
 6061 
 6062   format %{ "atomic_xchg  $prev, $newv, [$mem]\t#@get_and_setP" %}
 6063 
 6064   ins_encode %{
 6065     __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6066   %}
 6067 
 6068   ins_pipe(pipe_serial);
 6069 %}
 6070 
 6071 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
 6072 %{
 6073   predicate(needs_acquiring_load_reserved(n));
 6074 
 6075   match(Set prev (GetAndSetI mem newv));
 6076 
 6077   ins_cost(ALU_COST);
 6078 
 6079   format %{ "atomic_xchgw_acq  $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
 6080 
 6081   ins_encode %{
 6082     __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6083   %}
 6084 
 6085   ins_pipe(pipe_serial);
 6086 %}
 6087 
 6088 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
 6089 %{
 6090   predicate(needs_acquiring_load_reserved(n));
 6091 
 6092   match(Set prev (GetAndSetL mem newv));
 6093 
 6094   ins_cost(ALU_COST);
 6095 
 6096   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
 6097 
 6098   ins_encode %{
 6099     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6100   %}
 6101 
 6102   ins_pipe(pipe_serial);
 6103 %}
 6104 
 6105 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
 6106 %{
 6107   predicate(needs_acquiring_load_reserved(n));
 6108 
 6109   match(Set prev (GetAndSetN mem newv));
 6110 
 6111   ins_cost(ALU_COST);
 6112 
 6113   format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
 6114 
 6115   ins_encode %{
 6116     __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6117   %}
 6118 
 6119   ins_pipe(pipe_serial);
 6120 %}
 6121 
 6122 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
 6123 %{
 6124   predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
 6125 
 6126   match(Set prev (GetAndSetP mem newv));
 6127 
 6128   ins_cost(ALU_COST);
 6129 
 6130   format %{ "atomic_xchg_acq  $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
 6131 
 6132   ins_encode %{
 6133     __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
 6134   %}
 6135 
 6136   ins_pipe(pipe_serial);
 6137 %}
 6138 
 6139 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
 6140 %{
 6141   match(Set newval (GetAndAddL mem incr));
 6142 
 6143   ins_cost(ALU_COST);
 6144 
 6145   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
 6146 
 6147   ins_encode %{
 6148     __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6149   %}
 6150 
 6151   ins_pipe(pipe_serial);
 6152 %}
 6153 
 6154 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
 6155 %{
 6156   predicate(n->as_LoadStore()->result_not_used());
 6157 
 6158   match(Set dummy (GetAndAddL mem incr));
 6159 
 6160   ins_cost(ALU_COST);
 6161 
 6162   format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
 6163 
 6164   ins_encode %{
 6165     __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
 6166   %}
 6167 
 6168   ins_pipe(pipe_serial);
 6169 %}
 6170 
 6171 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
 6172 %{
 6173   match(Set newval (GetAndAddL mem incr));
 6174 
 6175   ins_cost(ALU_COST);
 6176 
 6177   format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
 6178 
 6179   ins_encode %{
 6180     __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6181   %}
 6182 
 6183   ins_pipe(pipe_serial);
 6184 %}
 6185 
 6186 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
 6187 %{
 6188   predicate(n->as_LoadStore()->result_not_used());
 6189 
 6190   match(Set dummy (GetAndAddL mem incr));
 6191 
 6192   ins_cost(ALU_COST);
 6193 
 6194   format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
 6195 
 6196   ins_encode %{
 6197     __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
 6198   %}
 6199 
 6200   ins_pipe(pipe_serial);
 6201 %}
 6202 
 6203 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6204 %{
 6205   match(Set newval (GetAndAddI mem incr));
 6206 
 6207   ins_cost(ALU_COST);
 6208 
 6209   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
 6210 
 6211   ins_encode %{
 6212     __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6213   %}
 6214 
 6215   ins_pipe(pipe_serial);
 6216 %}
 6217 
 6218 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
 6219 %{
 6220   predicate(n->as_LoadStore()->result_not_used());
 6221 
 6222   match(Set dummy (GetAndAddI mem incr));
 6223 
 6224   ins_cost(ALU_COST);
 6225 
 6226   format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
 6227 
 6228   ins_encode %{
 6229     __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
 6230   %}
 6231 
 6232   ins_pipe(pipe_serial);
 6233 %}
 6234 
 6235 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
 6236 %{
 6237   match(Set newval (GetAndAddI mem incr));
 6238 
 6239   ins_cost(ALU_COST);
 6240 
 6241   format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
 6242 
 6243   ins_encode %{
 6244     __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6245   %}
 6246 
 6247   ins_pipe(pipe_serial);
 6248 %}
 6249 
 6250 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
 6251 %{
 6252   predicate(n->as_LoadStore()->result_not_used());
 6253 
 6254   match(Set dummy (GetAndAddI mem incr));
 6255 
 6256   ins_cost(ALU_COST);
 6257 
 6258   format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
 6259 
 6260   ins_encode %{
 6261     __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
 6262   %}
 6263 
 6264   ins_pipe(pipe_serial);
 6265 %}
 6266 
 6267 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
 6268 %{
 6269   predicate(needs_acquiring_load_reserved(n));
 6270 
 6271   match(Set newval (GetAndAddL mem incr));
 6272 
 6273   ins_cost(ALU_COST);
 6274 
 6275   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
 6276 
 6277   ins_encode %{
 6278     __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6279   %}
 6280 
 6281   ins_pipe(pipe_serial);
 6282 %}
 6283 
 6284 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
 6285   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6286 
 6287   match(Set dummy (GetAndAddL mem incr));
 6288 
 6289   ins_cost(ALU_COST);
 6290 
 6291   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
 6292 
 6293   ins_encode %{
 6294     __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
 6295   %}
 6296 
 6297   ins_pipe(pipe_serial);
 6298 %}
 6299 
 6300 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
 6301 %{
 6302   predicate(needs_acquiring_load_reserved(n));
 6303 
 6304   match(Set newval (GetAndAddL mem incr));
 6305 
 6306   ins_cost(ALU_COST);
 6307 
 6308   format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
 6309 
 6310   ins_encode %{
 6311     __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6312   %}
 6313 
 6314   ins_pipe(pipe_serial);
 6315 %}
 6316 
 6317 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
 6318 %{
 6319   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6320 
 6321   match(Set dummy (GetAndAddL mem incr));
 6322 
 6323   ins_cost(ALU_COST);
 6324 
 6325   format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
 6326 
 6327   ins_encode %{
 6328     __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
 6329   %}
 6330 
 6331   ins_pipe(pipe_serial);
 6332 %}
 6333 
 6334 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
 6335 %{
 6336   predicate(needs_acquiring_load_reserved(n));
 6337 
 6338   match(Set newval (GetAndAddI mem incr));
 6339 
 6340   ins_cost(ALU_COST);
 6341 
 6342   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
 6343 
 6344   ins_encode %{
 6345     __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
 6346   %}
 6347 
 6348   ins_pipe(pipe_serial);
 6349 %}
 6350 
 6351 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
 6352 %{
 6353   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6354 
 6355   match(Set dummy (GetAndAddI mem incr));
 6356 
 6357   ins_cost(ALU_COST);
 6358 
 6359   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
 6360 
 6361   ins_encode %{
 6362     __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
 6363   %}
 6364 
 6365   ins_pipe(pipe_serial);
 6366 %}
 6367 
 6368 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
 6369 %{
 6370   predicate(needs_acquiring_load_reserved(n));
 6371 
 6372   match(Set newval (GetAndAddI mem incr));
 6373 
 6374   ins_cost(ALU_COST);
 6375 
 6376   format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
 6377 
 6378   ins_encode %{
 6379     __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
 6380   %}
 6381 
 6382   ins_pipe(pipe_serial);
 6383 %}
 6384 
 6385 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
 6386 %{
 6387   predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
 6388 
 6389   match(Set dummy (GetAndAddI mem incr));
 6390 
 6391   ins_cost(ALU_COST);
 6392 
 6393   format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
 6394 
 6395   ins_encode %{
 6396     __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
 6397   %}
 6398 
 6399   ins_pipe(pipe_serial);
 6400 %}
 6401 
 6402 // ============================================================================
 6403 // Arithmetic Instructions
 6404 //
 6405 
 6406 // Integer Addition
 6407 
 6408 // TODO
 6409 // these currently employ operations which do not set CR and hence are
 6410 // not flagged as killing CR but we would like to isolate the cases
 6411 // where we want to set flags from those where we don't. need to work
 6412 // out how to do that.
 6413 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6414   match(Set dst (AddI src1 src2));
 6415 
 6416   ins_cost(ALU_COST);
 6417   format %{ "addw  $dst, $src1, $src2\t#@addI_reg_reg" %}
 6418 
 6419   ins_encode %{
 6420     Assembler::CompressibleRegion cr(&_masm);
 6421     __ addw(as_Register($dst$$reg),
 6422             as_Register($src1$$reg),
 6423             as_Register($src2$$reg));
 6424   %}
 6425 
 6426   ins_pipe(ialu_reg_reg);
 6427 %}
 6428 
 6429 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
 6430   match(Set dst (AddI src1 src2));
 6431 
 6432   ins_cost(ALU_COST);
 6433   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm" %}
 6434 
 6435   ins_encode %{
 6436     Assembler::CompressibleRegion cr(&_masm);
 6437     int32_t con = (int32_t)$src2$$constant;
 6438     __ addiw(as_Register($dst$$reg),
 6439              as_Register($src1$$reg),
 6440              $src2$$constant);
 6441   %}
 6442 
 6443   ins_pipe(ialu_reg_imm);
 6444 %}
 6445 
 6446 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
 6447   match(Set dst (AddI (ConvL2I src1) src2));
 6448 
 6449   ins_cost(ALU_COST);
 6450   format %{ "addiw  $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
 6451 
 6452   ins_encode %{
 6453     Assembler::CompressibleRegion cr(&_masm);
 6454     __ addiw(as_Register($dst$$reg),
 6455              as_Register($src1$$reg),
 6456              $src2$$constant);
 6457   %}
 6458 
 6459   ins_pipe(ialu_reg_imm);
 6460 %}
 6461 
 6462 // Pointer Addition
 6463 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
 6464   match(Set dst (AddP src1 src2));
 6465 
 6466   ins_cost(ALU_COST);
 6467   format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
 6468 
 6469   ins_encode %{
 6470     Assembler::CompressibleRegion cr(&_masm);
 6471     __ add(as_Register($dst$$reg),
 6472            as_Register($src1$$reg),
 6473            as_Register($src2$$reg));
 6474   %}
 6475 
 6476   ins_pipe(ialu_reg_reg);
 6477 %}
 6478 
 6479 // If we shift more than 32 bits, we need not convert I2L.
 6480 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
 6481   match(Set dst (LShiftL (ConvI2L src) scale));
 6482   ins_cost(ALU_COST);
 6483   format %{ "slli  $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
 6484 
 6485   ins_encode %{
 6486     Assembler::CompressibleRegion cr(&_masm);
 6487     __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
 6488   %}
 6489 
 6490   ins_pipe(ialu_reg_shift);
 6491 %}
 6492 
 6493 // Pointer Immediate Addition
 6494 // n.b. this needs to be more expensive than using an indirect memory
 6495 // operand
 6496 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
 6497   match(Set dst (AddP src1 src2));
 6498   ins_cost(ALU_COST);
 6499   format %{ "addi  $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
 6500 
 6501   ins_encode %{
 6502     Assembler::CompressibleRegion cr(&_masm);
 6503     // src2 is imm, so actually call the addi
 6504     __ add(as_Register($dst$$reg),
 6505            as_Register($src1$$reg),
 6506            $src2$$constant);
 6507   %}
 6508 
 6509   ins_pipe(ialu_reg_imm);
 6510 %}
 6511 
 6512 // Long Addition
 6513 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6514   match(Set dst (AddL src1 src2));
 6515   ins_cost(ALU_COST);
 6516   format %{ "add  $dst, $src1, $src2\t#@addL_reg_reg" %}
 6517 
 6518   ins_encode %{
 6519     Assembler::CompressibleRegion cr(&_masm);
 6520     __ add(as_Register($dst$$reg),
 6521            as_Register($src1$$reg),
 6522            as_Register($src2$$reg));
 6523   %}
 6524 
 6525   ins_pipe(ialu_reg_reg);
 6526 %}
 6527 
 6528 // No constant pool entries requiredLong Immediate Addition.
 6529 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 6530   match(Set dst (AddL src1 src2));
 6531   ins_cost(ALU_COST);
 6532   format %{ "addi  $dst, $src1, $src2\t#@addL_reg_imm" %}
 6533 
 6534   ins_encode %{
 6535     Assembler::CompressibleRegion cr(&_masm);
 6536     // src2 is imm, so actually call the addi
 6537     __ add(as_Register($dst$$reg),
 6538            as_Register($src1$$reg),
 6539            $src2$$constant);
 6540   %}
 6541 
 6542   ins_pipe(ialu_reg_imm);
 6543 %}
 6544 
 6545 // Integer Subtraction
 6546 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6547   match(Set dst (SubI src1 src2));
 6548 
 6549   ins_cost(ALU_COST);
 6550   format %{ "subw  $dst, $src1, $src2\t#@subI_reg_reg" %}
 6551 
 6552   ins_encode %{
 6553     Assembler::CompressibleRegion cr(&_masm);
 6554     __ subw(as_Register($dst$$reg),
 6555             as_Register($src1$$reg),
 6556             as_Register($src2$$reg));
 6557   %}
 6558 
 6559   ins_pipe(ialu_reg_reg);
 6560 %}
 6561 
 6562 // Immediate Subtraction
 6563 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
 6564   match(Set dst (SubI src1 src2));
 6565 
 6566   ins_cost(ALU_COST);
 6567   format %{ "addiw  $dst, $src1, -$src2\t#@subI_reg_imm" %}
 6568 
 6569   ins_encode %{
 6570     Assembler::CompressibleRegion cr(&_masm);
 6571     // src2 is imm, so actually call the addiw
 6572     __ subw(as_Register($dst$$reg),
 6573             as_Register($src1$$reg),
 6574             $src2$$constant);
 6575   %}
 6576 
 6577   ins_pipe(ialu_reg_imm);
 6578 %}
 6579 
 6580 // Long Subtraction
 6581 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6582   match(Set dst (SubL src1 src2));
 6583   ins_cost(ALU_COST);
 6584   format %{ "sub  $dst, $src1, $src2\t#@subL_reg_reg" %}
 6585 
 6586   ins_encode %{
 6587     Assembler::CompressibleRegion cr(&_masm);
 6588     __ sub(as_Register($dst$$reg),
 6589            as_Register($src1$$reg),
 6590            as_Register($src2$$reg));
 6591   %}
 6592 
 6593   ins_pipe(ialu_reg_reg);
 6594 %}
 6595 
 6596 // No constant pool entries requiredLong Immediate Subtraction.
 6597 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
 6598   match(Set dst (SubL src1 src2));
 6599   ins_cost(ALU_COST);
 6600   format %{ "addi  $dst, $src1, -$src2\t#@subL_reg_imm" %}
 6601 
 6602   ins_encode %{
 6603     Assembler::CompressibleRegion cr(&_masm);
 6604     // src2 is imm, so actually call the addi
 6605     __ sub(as_Register($dst$$reg),
 6606            as_Register($src1$$reg),
 6607            $src2$$constant);
 6608   %}
 6609 
 6610   ins_pipe(ialu_reg_imm);
 6611 %}
 6612 
 6613 // Integer Negation (special case for sub)
 6614 
 6615 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
 6616   match(Set dst (SubI zero src));
 6617   ins_cost(ALU_COST);
 6618   format %{ "subw  $dst, x0, $src\t# int, #@negI_reg" %}
 6619 
 6620   ins_encode %{
 6621     // actually call the subw
 6622     __ negw(as_Register($dst$$reg),
 6623             as_Register($src$$reg));
 6624   %}
 6625 
 6626   ins_pipe(ialu_reg);
 6627 %}
 6628 
 6629 // Long Negation
 6630 
 6631 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
 6632   match(Set dst (SubL zero src));
 6633   ins_cost(ALU_COST);
 6634   format %{ "sub  $dst, x0, $src\t# long, #@negL_reg" %}
 6635 
 6636   ins_encode %{
 6637     // actually call the sub
 6638     __ neg(as_Register($dst$$reg),
 6639            as_Register($src$$reg));
 6640   %}
 6641 
 6642   ins_pipe(ialu_reg);
 6643 %}
 6644 
 6645 // Integer Multiply
 6646 
 6647 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6648   match(Set dst (MulI src1 src2));
 6649   ins_cost(IMUL_COST);
 6650   format %{ "mulw  $dst, $src1, $src2\t#@mulI" %}
 6651 
 6652   //this means 2 word multi, and no sign extend to 64 bits
 6653   ins_encode %{
 6654     // riscv64 mulw will sign-extension to high 32 bits in dst reg
 6655     __ mulw(as_Register($dst$$reg),
 6656             as_Register($src1$$reg),
 6657             as_Register($src2$$reg));
 6658   %}
 6659 
 6660   ins_pipe(imul_reg_reg);
 6661 %}
 6662 
 6663 // Long Multiply
 6664 
 6665 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6666   match(Set dst (MulL src1 src2));
 6667   ins_cost(IMUL_COST);
 6668   format %{ "mul  $dst, $src1, $src2\t#@mulL" %}
 6669 
 6670   ins_encode %{
 6671     __ mul(as_Register($dst$$reg),
 6672            as_Register($src1$$reg),
 6673            as_Register($src2$$reg));
 6674   %}
 6675 
 6676   ins_pipe(lmul_reg_reg);
 6677 %}
 6678 
 6679 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
 6680 %{
 6681   match(Set dst (MulHiL src1 src2));
 6682   ins_cost(IMUL_COST);
 6683   format %{ "mulh  $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
 6684 
 6685   ins_encode %{
 6686     __ mulh(as_Register($dst$$reg),
 6687             as_Register($src1$$reg),
 6688             as_Register($src2$$reg));
 6689   %}
 6690 
 6691   ins_pipe(lmul_reg_reg);
 6692 %}
 6693 
 6694 // Integer Divide
 6695 
 6696 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6697   match(Set dst (DivI src1 src2));
 6698   ins_cost(IDIVSI_COST);
 6699   format %{ "divw  $dst, $src1, $src2\t#@divI"%}
 6700 
 6701   ins_encode(riscv_enc_divw(dst, src1, src2));
 6702   ins_pipe(idiv_reg_reg);
 6703 %}
 6704 
 6705 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
 6706   match(Set dst (URShiftI (RShiftI src1 div1) div2));
 6707   ins_cost(ALU_COST);
 6708   format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
 6709 
 6710   ins_encode %{
 6711     __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
 6712   %}
 6713   ins_pipe(ialu_reg_shift);
 6714 %}
 6715 
 6716 // Long Divide
 6717 
 6718 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6719   match(Set dst (DivL src1 src2));
 6720   ins_cost(IDIVDI_COST);
 6721   format %{ "div  $dst, $src1, $src2\t#@divL" %}
 6722 
 6723   ins_encode(riscv_enc_div(dst, src1, src2));
 6724   ins_pipe(ldiv_reg_reg);
 6725 %}
 6726 
 6727 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
 6728   match(Set dst (URShiftL (RShiftL src1 div1) div2));
 6729   ins_cost(ALU_COST);
 6730   format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
 6731 
 6732   ins_encode %{
 6733     Assembler::CompressibleRegion cr(&_masm);
 6734     __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
 6735   %}
 6736   ins_pipe(ialu_reg_shift);
 6737 %}
 6738 
 6739 // Integer Remainder
 6740 
 6741 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6742   match(Set dst (ModI src1 src2));
 6743   ins_cost(IDIVSI_COST);
 6744   format %{ "remw  $dst, $src1, $src2\t#@modI" %}
 6745 
 6746   ins_encode(riscv_enc_modw(dst, src1, src2));
 6747   ins_pipe(ialu_reg_reg);
 6748 %}
 6749 
 6750 // Long Remainder
 6751 
 6752 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 6753   match(Set dst (ModL src1 src2));
 6754   ins_cost(IDIVDI_COST);
 6755   format %{ "rem  $dst, $src1, $src2\t#@modL" %}
 6756 
 6757   ins_encode(riscv_enc_mod(dst, src1, src2));
 6758   ins_pipe(ialu_reg_reg);
 6759 %}
 6760 
 6761 // Integer Shifts
 6762 
 6763 // Shift Left Register
 6764 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6765 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6766   match(Set dst (LShiftI src1 src2));
 6767   ins_cost(ALU_COST);
 6768   format %{ "sllw  $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
 6769 
 6770   ins_encode %{
 6771     __ sllw(as_Register($dst$$reg),
 6772             as_Register($src1$$reg),
 6773             as_Register($src2$$reg));
 6774   %}
 6775 
 6776   ins_pipe(ialu_reg_reg_vshift);
 6777 %}
 6778 
 6779 // Shift Left Immediate
 6780 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6781   match(Set dst (LShiftI src1 src2));
 6782   ins_cost(ALU_COST);
 6783   format %{ "slliw  $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
 6784 
 6785   ins_encode %{
 6786     // the shift amount is encoded in the lower
 6787     // 5 bits of the I-immediate field for RV32I
 6788     __ slliw(as_Register($dst$$reg),
 6789              as_Register($src1$$reg),
 6790              (unsigned) $src2$$constant & 0x1f);
 6791   %}
 6792 
 6793   ins_pipe(ialu_reg_shift);
 6794 %}
 6795 
 6796 // Shift Right Logical Register
 6797 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6798 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6799   match(Set dst (URShiftI src1 src2));
 6800   ins_cost(ALU_COST);
 6801   format %{ "srlw  $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
 6802 
 6803   ins_encode %{
 6804     __ srlw(as_Register($dst$$reg),
 6805             as_Register($src1$$reg),
 6806             as_Register($src2$$reg));
 6807   %}
 6808 
 6809   ins_pipe(ialu_reg_reg_vshift);
 6810 %}
 6811 
 6812 // Shift Right Logical Immediate
 6813 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6814   match(Set dst (URShiftI src1 src2));
 6815   ins_cost(ALU_COST);
 6816   format %{ "srliw  $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
 6817 
 6818   ins_encode %{
 6819     // the shift amount is encoded in the lower
 6820     // 6 bits of the I-immediate field for RV64I
 6821     __ srliw(as_Register($dst$$reg),
 6822              as_Register($src1$$reg),
 6823              (unsigned) $src2$$constant & 0x1f);
 6824   %}
 6825 
 6826   ins_pipe(ialu_reg_shift);
 6827 %}
 6828 
 6829 // Shift Right Arithmetic Register
 6830 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
 6831 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
 6832   match(Set dst (RShiftI src1 src2));
 6833   ins_cost(ALU_COST);
 6834   format %{ "sraw  $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
 6835 
 6836   ins_encode %{
 6837     // riscv will sign-ext dst high 32 bits
 6838     __ sraw(as_Register($dst$$reg),
 6839             as_Register($src1$$reg),
 6840             as_Register($src2$$reg));
 6841   %}
 6842 
 6843   ins_pipe(ialu_reg_reg_vshift);
 6844 %}
 6845 
 6846 // Shift Right Arithmetic Immediate
 6847 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
 6848   match(Set dst (RShiftI src1 src2));
 6849   ins_cost(ALU_COST);
 6850   format %{ "sraiw  $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
 6851 
 6852   ins_encode %{
 6853     // riscv will sign-ext dst high 32 bits
 6854     __ sraiw(as_Register($dst$$reg),
 6855              as_Register($src1$$reg),
 6856              (unsigned) $src2$$constant & 0x1f);
 6857   %}
 6858 
 6859   ins_pipe(ialu_reg_shift);
 6860 %}
 6861 
 6862 // Long Shifts
 6863 
 6864 // Shift Left Register
 6865 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6866 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6867   match(Set dst (LShiftL src1 src2));
 6868 
 6869   ins_cost(ALU_COST);
 6870   format %{ "sll  $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
 6871 
 6872   ins_encode %{
 6873     __ sll(as_Register($dst$$reg),
 6874            as_Register($src1$$reg),
 6875            as_Register($src2$$reg));
 6876   %}
 6877 
 6878   ins_pipe(ialu_reg_reg_vshift);
 6879 %}
 6880 
 6881 // Shift Left Immediate
 6882 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6883   match(Set dst (LShiftL src1 src2));
 6884 
 6885   ins_cost(ALU_COST);
 6886   format %{ "slli  $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
 6887 
 6888   ins_encode %{
 6889     Assembler::CompressibleRegion cr(&_masm);
 6890     // the shift amount is encoded in the lower
 6891     // 6 bits of the I-immediate field for RV64I
 6892     __ slli(as_Register($dst$$reg),
 6893             as_Register($src1$$reg),
 6894             (unsigned) $src2$$constant & 0x3f);
 6895   %}
 6896 
 6897   ins_pipe(ialu_reg_shift);
 6898 %}
 6899 
 6900 // Shift Right Logical Register
 6901 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6902 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6903   match(Set dst (URShiftL src1 src2));
 6904 
 6905   ins_cost(ALU_COST);
 6906   format %{ "srl  $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
 6907 
 6908   ins_encode %{
 6909     __ srl(as_Register($dst$$reg),
 6910             as_Register($src1$$reg),
 6911             as_Register($src2$$reg));
 6912   %}
 6913 
 6914   ins_pipe(ialu_reg_reg_vshift);
 6915 %}
 6916 
 6917 // Shift Right Logical Immediate
 6918 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6919   match(Set dst (URShiftL src1 src2));
 6920 
 6921   ins_cost(ALU_COST);
 6922   format %{ "srli  $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
 6923 
 6924   ins_encode %{
 6925     Assembler::CompressibleRegion cr(&_masm);
 6926     // the shift amount is encoded in the lower
 6927     // 6 bits of the I-immediate field for RV64I
 6928     __ srli(as_Register($dst$$reg),
 6929             as_Register($src1$$reg),
 6930             (unsigned) $src2$$constant & 0x3f);
 6931   %}
 6932 
 6933   ins_pipe(ialu_reg_shift);
 6934 %}
 6935 
 6936 // A special-case pattern for card table stores.
 6937 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
 6938   match(Set dst (URShiftL (CastP2X src1) src2));
 6939 
 6940   ins_cost(ALU_COST);
 6941   format %{ "srli  $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
 6942 
 6943   ins_encode %{
 6944     Assembler::CompressibleRegion cr(&_masm);
 6945     // the shift amount is encoded in the lower
 6946     // 6 bits of the I-immediate field for RV64I
 6947     __ srli(as_Register($dst$$reg),
 6948             as_Register($src1$$reg),
 6949             (unsigned) $src2$$constant & 0x3f);
 6950   %}
 6951 
 6952   ins_pipe(ialu_reg_shift);
 6953 %}
 6954 
 6955 // Shift Right Arithmetic Register
 6956 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
 6957 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
 6958   match(Set dst (RShiftL src1 src2));
 6959 
 6960   ins_cost(ALU_COST);
 6961   format %{ "sra  $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
 6962 
 6963   ins_encode %{
 6964     __ sra(as_Register($dst$$reg),
 6965            as_Register($src1$$reg),
 6966            as_Register($src2$$reg));
 6967   %}
 6968 
 6969   ins_pipe(ialu_reg_reg_vshift);
 6970 %}
 6971 
 6972 // Shift Right Arithmetic Immediate
 6973 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
 6974   match(Set dst (RShiftL src1 src2));
 6975 
 6976   ins_cost(ALU_COST);
 6977   format %{ "srai  $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
 6978 
 6979   ins_encode %{
 6980     Assembler::CompressibleRegion cr(&_masm);
 6981     // the shift amount is encoded in the lower
 6982     // 6 bits of the I-immediate field for RV64I
 6983     __ srai(as_Register($dst$$reg),
 6984             as_Register($src1$$reg),
 6985             (unsigned) $src2$$constant & 0x3f);
 6986   %}
 6987 
 6988   ins_pipe(ialu_reg_shift);
 6989 %}
 6990 
 6991 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
 6992   match(Set dst (XorI src1 m1));
 6993   ins_cost(ALU_COST);
 6994   format %{ "xori  $dst, $src1, -1\t#@regI_not_reg" %}
 6995 
 6996   ins_encode %{
 6997     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 6998   %}
 6999 
 7000   ins_pipe(ialu_reg);
 7001 %}
 7002 
 7003 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
 7004   match(Set dst (XorL src1 m1));
 7005   ins_cost(ALU_COST);
 7006   format %{ "xori  $dst, $src1, -1\t#@regL_not_reg" %}
 7007 
 7008   ins_encode %{
 7009     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
 7010   %}
 7011 
 7012   ins_pipe(ialu_reg);
 7013 %}
 7014 
 7015 
 7016 // ============================================================================
 7017 // Floating Point Arithmetic Instructions
 7018 
 7019 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7020   match(Set dst (AddF src1 src2));
 7021 
 7022   ins_cost(FMUL_SINGLE_COST);
 7023   format %{ "fadd.s  $dst, $src1, $src2\t#@addF_reg_reg" %}
 7024 
 7025   ins_encode %{
 7026     __ fadd_s(as_FloatRegister($dst$$reg),
 7027               as_FloatRegister($src1$$reg),
 7028               as_FloatRegister($src2$$reg));
 7029   %}
 7030 
 7031   ins_pipe(fp_dop_reg_reg_s);
 7032 %}
 7033 
 7034 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7035   match(Set dst (AddD src1 src2));
 7036 
 7037   ins_cost(FMUL_DOUBLE_COST);
 7038   format %{ "fadd.d  $dst, $src1, $src2\t#@addD_reg_reg" %}
 7039 
 7040   ins_encode %{
 7041     __ fadd_d(as_FloatRegister($dst$$reg),
 7042               as_FloatRegister($src1$$reg),
 7043               as_FloatRegister($src2$$reg));
 7044   %}
 7045 
 7046   ins_pipe(fp_dop_reg_reg_d);
 7047 %}
 7048 
 7049 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7050   match(Set dst (SubF src1 src2));
 7051 
 7052   ins_cost(FMUL_SINGLE_COST);
 7053   format %{ "fsub.s  $dst, $src1, $src2\t#@subF_reg_reg" %}
 7054 
 7055   ins_encode %{
 7056     __ fsub_s(as_FloatRegister($dst$$reg),
 7057               as_FloatRegister($src1$$reg),
 7058               as_FloatRegister($src2$$reg));
 7059   %}
 7060 
 7061   ins_pipe(fp_dop_reg_reg_s);
 7062 %}
 7063 
 7064 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7065   match(Set dst (SubD src1 src2));
 7066 
 7067   ins_cost(FMUL_DOUBLE_COST);
 7068   format %{ "fsub.d  $dst, $src1, $src2\t#@subD_reg_reg" %}
 7069 
 7070   ins_encode %{
 7071     __ fsub_d(as_FloatRegister($dst$$reg),
 7072               as_FloatRegister($src1$$reg),
 7073               as_FloatRegister($src2$$reg));
 7074   %}
 7075 
 7076   ins_pipe(fp_dop_reg_reg_d);
 7077 %}
 7078 
 7079 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7080   match(Set dst (MulF src1 src2));
 7081 
 7082   ins_cost(FMUL_SINGLE_COST);
 7083   format %{ "fmul.s  $dst, $src1, $src2\t#@mulF_reg_reg" %}
 7084 
 7085   ins_encode %{
 7086     __ fmul_s(as_FloatRegister($dst$$reg),
 7087               as_FloatRegister($src1$$reg),
 7088               as_FloatRegister($src2$$reg));
 7089   %}
 7090 
 7091   ins_pipe(fp_dop_reg_reg_s);
 7092 %}
 7093 
 7094 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7095   match(Set dst (MulD src1 src2));
 7096 
 7097   ins_cost(FMUL_DOUBLE_COST);
 7098   format %{ "fmul.d  $dst, $src1, $src2\t#@mulD_reg_reg" %}
 7099 
 7100   ins_encode %{
 7101     __ fmul_d(as_FloatRegister($dst$$reg),
 7102               as_FloatRegister($src1$$reg),
 7103               as_FloatRegister($src2$$reg));
 7104   %}
 7105 
 7106   ins_pipe(fp_dop_reg_reg_d);
 7107 %}
 7108 
 7109 // src1 * src2 + src3
 7110 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7111   predicate(UseFMA);
 7112   match(Set dst (FmaF src3 (Binary src1 src2)));
 7113 
 7114   ins_cost(FMUL_SINGLE_COST);
 7115   format %{ "fmadd.s  $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
 7116 
 7117   ins_encode %{
 7118     __ fmadd_s(as_FloatRegister($dst$$reg),
 7119                as_FloatRegister($src1$$reg),
 7120                as_FloatRegister($src2$$reg),
 7121                as_FloatRegister($src3$$reg));
 7122   %}
 7123 
 7124   ins_pipe(pipe_class_default);
 7125 %}
 7126 
 7127 // src1 * src2 + src3
 7128 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7129   predicate(UseFMA);
 7130   match(Set dst (FmaD src3 (Binary src1 src2)));
 7131 
 7132   ins_cost(FMUL_DOUBLE_COST);
 7133   format %{ "fmadd.d  $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
 7134 
 7135   ins_encode %{
 7136     __ fmadd_d(as_FloatRegister($dst$$reg),
 7137                as_FloatRegister($src1$$reg),
 7138                as_FloatRegister($src2$$reg),
 7139                as_FloatRegister($src3$$reg));
 7140   %}
 7141 
 7142   ins_pipe(pipe_class_default);
 7143 %}
 7144 
 7145 // src1 * src2 - src3
 7146 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7147   predicate(UseFMA);
 7148   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
 7149 
 7150   ins_cost(FMUL_SINGLE_COST);
 7151   format %{ "fmsub.s  $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
 7152 
 7153   ins_encode %{
 7154     __ fmsub_s(as_FloatRegister($dst$$reg),
 7155                as_FloatRegister($src1$$reg),
 7156                as_FloatRegister($src2$$reg),
 7157                as_FloatRegister($src3$$reg));
 7158   %}
 7159 
 7160   ins_pipe(pipe_class_default);
 7161 %}
 7162 
 7163 // src1 * src2 - src3
 7164 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7165   predicate(UseFMA);
 7166   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
 7167 
 7168   ins_cost(FMUL_DOUBLE_COST);
 7169   format %{ "fmsub.d  $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
 7170 
 7171   ins_encode %{
 7172     __ fmsub_d(as_FloatRegister($dst$$reg),
 7173                as_FloatRegister($src1$$reg),
 7174                as_FloatRegister($src2$$reg),
 7175                as_FloatRegister($src3$$reg));
 7176   %}
 7177 
 7178   ins_pipe(pipe_class_default);
 7179 %}
 7180 
 7181 // -src1 * src2 + src3
 7182 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7183   predicate(UseFMA);
 7184   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
 7185   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
 7186 
 7187   ins_cost(FMUL_SINGLE_COST);
 7188   format %{ "fnmsub.s  $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
 7189 
 7190   ins_encode %{
 7191     __ fnmsub_s(as_FloatRegister($dst$$reg),
 7192                 as_FloatRegister($src1$$reg),
 7193                 as_FloatRegister($src2$$reg),
 7194                 as_FloatRegister($src3$$reg));
 7195   %}
 7196 
 7197   ins_pipe(pipe_class_default);
 7198 %}
 7199 
 7200 // -src1 * src2 + src3
 7201 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7202   predicate(UseFMA);
 7203   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
 7204   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
 7205 
 7206   ins_cost(FMUL_DOUBLE_COST);
 7207   format %{ "fnmsub.d  $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
 7208 
 7209   ins_encode %{
 7210     __ fnmsub_d(as_FloatRegister($dst$$reg),
 7211                 as_FloatRegister($src1$$reg),
 7212                 as_FloatRegister($src2$$reg),
 7213                 as_FloatRegister($src3$$reg));
 7214   %}
 7215 
 7216   ins_pipe(pipe_class_default);
 7217 %}
 7218 
 7219 // -src1 * src2 - src3
 7220 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
 7221   predicate(UseFMA);
 7222   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
 7223   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
 7224 
 7225   ins_cost(FMUL_SINGLE_COST);
 7226   format %{ "fnmadd.s  $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
 7227 
 7228   ins_encode %{
 7229     __ fnmadd_s(as_FloatRegister($dst$$reg),
 7230                 as_FloatRegister($src1$$reg),
 7231                 as_FloatRegister($src2$$reg),
 7232                 as_FloatRegister($src3$$reg));
 7233   %}
 7234 
 7235   ins_pipe(pipe_class_default);
 7236 %}
 7237 
 7238 // -src1 * src2 - src3
 7239 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 7240   predicate(UseFMA);
 7241   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
 7242   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
 7243 
 7244   ins_cost(FMUL_DOUBLE_COST);
 7245   format %{ "fnmadd.d  $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
 7246 
 7247   ins_encode %{
 7248     __ fnmadd_d(as_FloatRegister($dst$$reg),
 7249                 as_FloatRegister($src1$$reg),
 7250                 as_FloatRegister($src2$$reg),
 7251                 as_FloatRegister($src3$$reg));
 7252   %}
 7253 
 7254   ins_pipe(pipe_class_default);
 7255 %}
 7256 
 7257 // Math.max(FF)F
 7258 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7259   match(Set dst (MaxF src1 src2));
 7260   effect(TEMP_DEF dst);
 7261 
 7262   format %{ "maxF $dst, $src1, $src2" %}
 7263 
 7264   ins_encode %{
 7265     __ minmax_FD(as_FloatRegister($dst$$reg),
 7266                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7267                  false /* is_double */, false /* is_min */);
 7268   %}
 7269 
 7270   ins_pipe(fp_dop_reg_reg_s);
 7271 %}
 7272 
 7273 // Math.min(FF)F
 7274 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7275   match(Set dst (MinF src1 src2));
 7276   effect(TEMP_DEF dst);
 7277 
 7278   format %{ "minF $dst, $src1, $src2" %}
 7279 
 7280   ins_encode %{
 7281     __ minmax_FD(as_FloatRegister($dst$$reg),
 7282                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7283                  false /* is_double */, true /* is_min */);
 7284   %}
 7285 
 7286   ins_pipe(fp_dop_reg_reg_s);
 7287 %}
 7288 
 7289 // Math.max(DD)D
 7290 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7291   match(Set dst (MaxD src1 src2));
 7292   effect(TEMP_DEF dst);
 7293 
 7294   format %{ "maxD $dst, $src1, $src2" %}
 7295 
 7296   ins_encode %{
 7297     __ minmax_FD(as_FloatRegister($dst$$reg),
 7298                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7299                  true /* is_double */, false /* is_min */);
 7300   %}
 7301 
 7302   ins_pipe(fp_dop_reg_reg_d);
 7303 %}
 7304 
 7305 // Math.min(DD)D
 7306 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7307   match(Set dst (MinD src1 src2));
 7308   effect(TEMP_DEF dst);
 7309 
 7310   format %{ "minD $dst, $src1, $src2" %}
 7311 
 7312   ins_encode %{
 7313     __ minmax_FD(as_FloatRegister($dst$$reg),
 7314                  as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
 7315                  true /* is_double */, true /* is_min */);
 7316   %}
 7317 
 7318   ins_pipe(fp_dop_reg_reg_d);
 7319 %}
 7320 
 7321 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
 7322   match(Set dst (DivF src1  src2));
 7323 
 7324   ins_cost(FDIV_COST);
 7325   format %{ "fdiv.s  $dst, $src1, $src2\t#@divF_reg_reg" %}
 7326 
 7327   ins_encode %{
 7328     __ fdiv_s(as_FloatRegister($dst$$reg),
 7329               as_FloatRegister($src1$$reg),
 7330               as_FloatRegister($src2$$reg));
 7331   %}
 7332 
 7333   ins_pipe(fp_div_s);
 7334 %}
 7335 
 7336 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
 7337   match(Set dst (DivD src1  src2));
 7338 
 7339   ins_cost(FDIV_COST);
 7340   format %{ "fdiv.d  $dst, $src1, $src2\t#@divD_reg_reg" %}
 7341 
 7342   ins_encode %{
 7343     __ fdiv_d(as_FloatRegister($dst$$reg),
 7344               as_FloatRegister($src1$$reg),
 7345               as_FloatRegister($src2$$reg));
 7346   %}
 7347 
 7348   ins_pipe(fp_div_d);
 7349 %}
 7350 
 7351 instruct negF_reg_reg(fRegF dst, fRegF src) %{
 7352   match(Set dst (NegF src));
 7353 
 7354   ins_cost(XFER_COST);
 7355   format %{ "fsgnjn.s  $dst, $src, $src\t#@negF_reg_reg" %}
 7356 
 7357   ins_encode %{
 7358     __ fneg_s(as_FloatRegister($dst$$reg),
 7359               as_FloatRegister($src$$reg));
 7360   %}
 7361 
 7362   ins_pipe(fp_uop_s);
 7363 %}
 7364 
 7365 instruct negD_reg_reg(fRegD dst, fRegD src) %{
 7366   match(Set dst (NegD src));
 7367 
 7368   ins_cost(XFER_COST);
 7369   format %{ "fsgnjn.d  $dst, $src, $src\t#@negD_reg_reg" %}
 7370 
 7371   ins_encode %{
 7372     __ fneg_d(as_FloatRegister($dst$$reg),
 7373               as_FloatRegister($src$$reg));
 7374   %}
 7375 
 7376   ins_pipe(fp_uop_d);
 7377 %}
 7378 
 7379 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
 7380   match(Set dst (AbsI src));
 7381 
 7382   ins_cost(ALU_COST * 3);
 7383   format %{
 7384     "sraiw  t0, $src, 0x1f\n\t"
 7385     "addw  $dst, $src, t0\n\t"
 7386     "xorr  $dst, $dst, t0\t#@absI_reg"
 7387   %}
 7388 
 7389   ins_encode %{
 7390     __ sraiw(t0, as_Register($src$$reg), 0x1f);
 7391     __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7392     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7393   %}
 7394 
 7395   ins_pipe(ialu_reg_reg);
 7396 %}
 7397 
 7398 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
 7399   match(Set dst (AbsL src));
 7400 
 7401   ins_cost(ALU_COST * 3);
 7402   format %{
 7403     "srai  t0, $src, 0x3f\n\t"
 7404     "add  $dst, $src, t0\n\t"
 7405     "xorr  $dst, $dst, t0\t#@absL_reg"
 7406   %}
 7407 
 7408   ins_encode %{
 7409     __ srai(t0, as_Register($src$$reg), 0x3f);
 7410     __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
 7411     __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
 7412   %}
 7413 
 7414   ins_pipe(ialu_reg_reg);
 7415 %}
 7416 
 7417 instruct absF_reg(fRegF dst, fRegF src) %{
 7418   match(Set dst (AbsF src));
 7419 
 7420   ins_cost(XFER_COST);
 7421   format %{ "fsgnjx.s  $dst, $src, $src\t#@absF_reg" %}
 7422   ins_encode %{
 7423     __ fabs_s(as_FloatRegister($dst$$reg),
 7424               as_FloatRegister($src$$reg));
 7425   %}
 7426 
 7427   ins_pipe(fp_uop_s);
 7428 %}
 7429 
 7430 instruct absD_reg(fRegD dst, fRegD src) %{
 7431   match(Set dst (AbsD src));
 7432 
 7433   ins_cost(XFER_COST);
 7434   format %{ "fsgnjx.d  $dst, $src, $src\t#@absD_reg" %}
 7435   ins_encode %{
 7436     __ fabs_d(as_FloatRegister($dst$$reg),
 7437               as_FloatRegister($src$$reg));
 7438   %}
 7439 
 7440   ins_pipe(fp_uop_d);
 7441 %}
 7442 
 7443 instruct sqrtF_reg(fRegF dst, fRegF src) %{
 7444   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7445 
 7446   ins_cost(FSQRT_COST);
 7447   format %{ "fsqrt.s  $dst, $src\t#@sqrtF_reg" %}
 7448   ins_encode %{
 7449     __ fsqrt_s(as_FloatRegister($dst$$reg),
 7450                as_FloatRegister($src$$reg));
 7451   %}
 7452 
 7453   ins_pipe(fp_sqrt_s);
 7454 %}
 7455 
 7456 instruct sqrtD_reg(fRegD dst, fRegD src) %{
 7457   match(Set dst (SqrtD src));
 7458 
 7459   ins_cost(FSQRT_COST);
 7460   format %{ "fsqrt.d  $dst, $src\t#@sqrtD_reg" %}
 7461   ins_encode %{
 7462     __ fsqrt_d(as_FloatRegister($dst$$reg),
 7463                as_FloatRegister($src$$reg));
 7464   %}
 7465 
 7466   ins_pipe(fp_sqrt_d);
 7467 %}
 7468 
 7469 // Arithmetic Instructions End
 7470 
 7471 // ============================================================================
 7472 // Logical Instructions
 7473 
 7474 // Register And
 7475 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7476   match(Set dst (AndI src1 src2));
 7477 
 7478   format %{ "andr  $dst, $src1, $src2\t#@andI_reg_reg" %}
 7479 
 7480   ins_cost(ALU_COST);
 7481   ins_encode %{
 7482     Assembler::CompressibleRegion cr(&_masm);
 7483     __ andr(as_Register($dst$$reg),
 7484             as_Register($src1$$reg),
 7485             as_Register($src2$$reg));
 7486   %}
 7487 
 7488   ins_pipe(ialu_reg_reg);
 7489 %}
 7490 
 7491 // Immediate And
 7492 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7493   match(Set dst (AndI src1 src2));
 7494 
 7495   format %{ "andi  $dst, $src1, $src2\t#@andI_reg_imm" %}
 7496 
 7497   ins_cost(ALU_COST);
 7498   ins_encode %{
 7499     Assembler::CompressibleRegion cr(&_masm);
 7500     __ andi(as_Register($dst$$reg),
 7501             as_Register($src1$$reg),
 7502             (int32_t)($src2$$constant));
 7503   %}
 7504 
 7505   ins_pipe(ialu_reg_imm);
 7506 %}
 7507 
 7508 // Register Or
 7509 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7510   match(Set dst (OrI src1 src2));
 7511 
 7512   format %{ "orr  $dst, $src1, $src2\t#@orI_reg_reg" %}
 7513 
 7514   ins_cost(ALU_COST);
 7515   ins_encode %{
 7516     Assembler::CompressibleRegion cr(&_masm);
 7517     __ orr(as_Register($dst$$reg),
 7518            as_Register($src1$$reg),
 7519            as_Register($src2$$reg));
 7520   %}
 7521 
 7522   ins_pipe(ialu_reg_reg);
 7523 %}
 7524 
 7525 // Immediate Or
 7526 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7527   match(Set dst (OrI src1 src2));
 7528 
 7529   format %{ "ori  $dst, $src1, $src2\t#@orI_reg_imm" %}
 7530 
 7531   ins_cost(ALU_COST);
 7532   ins_encode %{
 7533     __ ori(as_Register($dst$$reg),
 7534            as_Register($src1$$reg),
 7535            (int32_t)($src2$$constant));
 7536   %}
 7537 
 7538   ins_pipe(ialu_reg_imm);
 7539 %}
 7540 
 7541 // Register Xor
 7542 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
 7543   match(Set dst (XorI src1 src2));
 7544 
 7545   format %{ "xorr  $dst, $src1, $src2\t#@xorI_reg_reg" %}
 7546 
 7547   ins_cost(ALU_COST);
 7548   ins_encode %{
 7549     Assembler::CompressibleRegion cr(&_masm);
 7550     __ xorr(as_Register($dst$$reg),
 7551             as_Register($src1$$reg),
 7552             as_Register($src2$$reg));
 7553   %}
 7554 
 7555   ins_pipe(ialu_reg_reg);
 7556 %}
 7557 
 7558 // Immediate Xor
 7559 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
 7560   match(Set dst (XorI src1 src2));
 7561 
 7562   format %{ "xori  $dst, $src1, $src2\t#@xorI_reg_imm" %}
 7563 
 7564   ins_cost(ALU_COST);
 7565   ins_encode %{
 7566     __ xori(as_Register($dst$$reg),
 7567             as_Register($src1$$reg),
 7568             (int32_t)($src2$$constant));
 7569   %}
 7570 
 7571   ins_pipe(ialu_reg_imm);
 7572 %}
 7573 
 7574 // Register And Long
 7575 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7576   match(Set dst (AndL src1 src2));
 7577 
 7578   format %{ "andr  $dst, $src1, $src2\t#@andL_reg_reg" %}
 7579 
 7580   ins_cost(ALU_COST);
 7581   ins_encode %{
 7582     Assembler::CompressibleRegion cr(&_masm);
 7583     __ andr(as_Register($dst$$reg),
 7584             as_Register($src1$$reg),
 7585             as_Register($src2$$reg));
 7586   %}
 7587 
 7588   ins_pipe(ialu_reg_reg);
 7589 %}
 7590 
 7591 // Immediate And Long
 7592 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7593   match(Set dst (AndL src1 src2));
 7594 
 7595   format %{ "andi  $dst, $src1, $src2\t#@andL_reg_imm" %}
 7596 
 7597   ins_cost(ALU_COST);
 7598   ins_encode %{
 7599     Assembler::CompressibleRegion cr(&_masm);
 7600     __ andi(as_Register($dst$$reg),
 7601             as_Register($src1$$reg),
 7602             (int32_t)($src2$$constant));
 7603   %}
 7604 
 7605   ins_pipe(ialu_reg_imm);
 7606 %}
 7607 
 7608 // Register Or Long
 7609 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7610   match(Set dst (OrL src1 src2));
 7611 
 7612   format %{ "orr  $dst, $src1, $src2\t#@orL_reg_reg" %}
 7613 
 7614   ins_cost(ALU_COST);
 7615   ins_encode %{
 7616     Assembler::CompressibleRegion cr(&_masm);
 7617     __ orr(as_Register($dst$$reg),
 7618            as_Register($src1$$reg),
 7619            as_Register($src2$$reg));
 7620   %}
 7621 
 7622   ins_pipe(ialu_reg_reg);
 7623 %}
 7624 
 7625 // Immediate Or Long
 7626 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7627   match(Set dst (OrL src1 src2));
 7628 
 7629   format %{ "ori  $dst, $src1, $src2\t#@orL_reg_imm" %}
 7630 
 7631   ins_cost(ALU_COST);
 7632   ins_encode %{
 7633     __ ori(as_Register($dst$$reg),
 7634            as_Register($src1$$reg),
 7635            (int32_t)($src2$$constant));
 7636   %}
 7637 
 7638   ins_pipe(ialu_reg_imm);
 7639 %}
 7640 
 7641 // Register Xor Long
 7642 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 7643   match(Set dst (XorL src1 src2));
 7644 
 7645   format %{ "xorr  $dst, $src1, $src2\t#@xorL_reg_reg" %}
 7646 
 7647   ins_cost(ALU_COST);
 7648   ins_encode %{
 7649     Assembler::CompressibleRegion cr(&_masm);
 7650     __ xorr(as_Register($dst$$reg),
 7651             as_Register($src1$$reg),
 7652             as_Register($src2$$reg));
 7653   %}
 7654 
 7655   ins_pipe(ialu_reg_reg);
 7656 %}
 7657 
 7658 // Immediate Xor Long
 7659 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
 7660   match(Set dst (XorL src1 src2));
 7661 
 7662   ins_cost(ALU_COST);
 7663   format %{ "xori  $dst, $src1, $src2\t#@xorL_reg_imm" %}
 7664 
 7665   ins_encode %{
 7666     __ xori(as_Register($dst$$reg),
 7667             as_Register($src1$$reg),
 7668             (int32_t)($src2$$constant));
 7669   %}
 7670 
 7671   ins_pipe(ialu_reg_imm);
 7672 %}
 7673 
 7674 // ============================================================================
 7675 // BSWAP Instructions
 7676 
 7677 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr) %{
 7678   match(Set dst (ReverseBytesI src));
 7679   effect(TEMP cr);
 7680 
 7681   ins_cost(ALU_COST * 13);
 7682   format %{ "revb_w_w  $dst, $src\t#@bytes_reverse_int" %}
 7683 
 7684   ins_encode %{
 7685     __ revb_w_w(as_Register($dst$$reg), as_Register($src$$reg));
 7686   %}
 7687 
 7688   ins_pipe(ialu_reg);
 7689 %}
 7690 
 7691 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src, rFlagsReg cr) %{
 7692   match(Set dst (ReverseBytesL src));
 7693   effect(TEMP cr);
 7694 
 7695   ins_cost(ALU_COST * 29);
 7696   format %{ "revb  $dst, $src\t#@bytes_reverse_long" %}
 7697 
 7698   ins_encode %{
 7699     __ revb(as_Register($dst$$reg), as_Register($src$$reg));
 7700   %}
 7701 
 7702   ins_pipe(ialu_reg);
 7703 %}
 7704 
 7705 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
 7706   match(Set dst (ReverseBytesUS src));
 7707 
 7708   ins_cost(ALU_COST * 5);
 7709   format %{ "revb_h_h_u  $dst, $src\t#@bytes_reverse_unsigned_short" %}
 7710 
 7711   ins_encode %{
 7712     __ revb_h_h_u(as_Register($dst$$reg), as_Register($src$$reg));
 7713   %}
 7714 
 7715   ins_pipe(ialu_reg);
 7716 %}
 7717 
 7718 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
 7719   match(Set dst (ReverseBytesS src));
 7720 
 7721   ins_cost(ALU_COST * 5);
 7722   format %{ "revb_h_h  $dst, $src\t#@bytes_reverse_short" %}
 7723 
 7724   ins_encode %{
 7725     __ revb_h_h(as_Register($dst$$reg), as_Register($src$$reg));
 7726   %}
 7727 
 7728   ins_pipe(ialu_reg);
 7729 %}
 7730 
 7731 // ============================================================================
 7732 // MemBar Instruction
 7733 
 7734 instruct load_fence() %{
 7735   match(LoadFence);
 7736   ins_cost(ALU_COST);
 7737 
 7738   format %{ "#@load_fence" %}
 7739 
 7740   ins_encode %{
 7741     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7742   %}
 7743   ins_pipe(pipe_serial);
 7744 %}
 7745 
 7746 instruct membar_acquire() %{
 7747   match(MemBarAcquire);
 7748   ins_cost(ALU_COST);
 7749 
 7750   format %{ "#@membar_acquire\n\t"
 7751             "fence ir iorw" %}
 7752 
 7753   ins_encode %{
 7754     __ block_comment("membar_acquire");
 7755     __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
 7756   %}
 7757 
 7758   ins_pipe(pipe_serial);
 7759 %}
 7760 
 7761 instruct membar_acquire_lock() %{
 7762   match(MemBarAcquireLock);
 7763   ins_cost(0);
 7764 
 7765   format %{ "#@membar_acquire_lock (elided)" %}
 7766 
 7767   ins_encode %{
 7768     __ block_comment("membar_acquire_lock (elided)");
 7769   %}
 7770 
 7771   ins_pipe(pipe_serial);
 7772 %}
 7773 
 7774 instruct store_fence() %{
 7775   match(StoreFence);
 7776   ins_cost(ALU_COST);
 7777 
 7778   format %{ "#@store_fence" %}
 7779 
 7780   ins_encode %{
 7781     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7782   %}
 7783   ins_pipe(pipe_serial);
 7784 %}
 7785 
 7786 instruct membar_release() %{
 7787   match(MemBarRelease);
 7788   ins_cost(ALU_COST);
 7789 
 7790   format %{ "#@membar_release\n\t"
 7791             "fence iorw ow" %}
 7792 
 7793   ins_encode %{
 7794     __ block_comment("membar_release");
 7795     __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
 7796   %}
 7797   ins_pipe(pipe_serial);
 7798 %}
 7799 
 7800 instruct membar_storestore() %{
 7801   match(MemBarStoreStore);
 7802   match(StoreStoreFence);
 7803   ins_cost(ALU_COST);
 7804 
 7805   format %{ "MEMBAR-store-store\t#@membar_storestore" %}
 7806 
 7807   ins_encode %{
 7808     __ membar(MacroAssembler::StoreStore);
 7809   %}
 7810   ins_pipe(pipe_serial);
 7811 %}
 7812 
 7813 instruct membar_release_lock() %{
 7814   match(MemBarReleaseLock);
 7815   ins_cost(0);
 7816 
 7817   format %{ "#@membar_release_lock (elided)" %}
 7818 
 7819   ins_encode %{
 7820     __ block_comment("membar_release_lock (elided)");
 7821   %}
 7822 
 7823   ins_pipe(pipe_serial);
 7824 %}
 7825 
 7826 instruct membar_volatile() %{
 7827   match(MemBarVolatile);
 7828   ins_cost(ALU_COST);
 7829 
 7830   format %{ "#@membar_volatile\n\t"
 7831              "fence iorw iorw"%}
 7832 
 7833   ins_encode %{
 7834     __ block_comment("membar_volatile");
 7835     __ membar(MacroAssembler::StoreLoad);
 7836   %}
 7837 
 7838   ins_pipe(pipe_serial);
 7839 %}
 7840 
 7841 // ============================================================================
 7842 // Cast Instructions (Java-level type cast)
 7843 
 7844 instruct castX2P(iRegPNoSp dst, iRegL src) %{
 7845   match(Set dst (CastX2P src));
 7846 
 7847   ins_cost(ALU_COST);
 7848   format %{ "mv  $dst, $src\t# long -> ptr, #@castX2P" %}
 7849 
 7850   ins_encode %{
 7851     Assembler::CompressibleRegion cr(&_masm);
 7852     if ($dst$$reg != $src$$reg) {
 7853       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7854     }
 7855   %}
 7856 
 7857   ins_pipe(ialu_reg);
 7858 %}
 7859 
 7860 instruct castP2X(iRegLNoSp dst, iRegP src) %{
 7861   match(Set dst (CastP2X src));
 7862 
 7863   ins_cost(ALU_COST);
 7864   format %{ "mv  $dst, $src\t# ptr -> long, #@castP2X" %}
 7865 
 7866   ins_encode %{
 7867     Assembler::CompressibleRegion cr(&_masm);
 7868     if ($dst$$reg != $src$$reg) {
 7869       __ mv(as_Register($dst$$reg), as_Register($src$$reg));
 7870     }
 7871   %}
 7872 
 7873   ins_pipe(ialu_reg);
 7874 %}
 7875 
 7876 instruct castPP(iRegPNoSp dst)
 7877 %{
 7878   match(Set dst (CastPP dst));
 7879   ins_cost(0);
 7880 
 7881   size(0);
 7882   format %{ "# castPP of $dst, #@castPP" %}
 7883   ins_encode(/* empty encoding */);
 7884   ins_pipe(pipe_class_empty);
 7885 %}
 7886 
 7887 instruct castLL(iRegL dst)
 7888 %{
 7889   match(Set dst (CastLL dst));
 7890 
 7891   size(0);
 7892   format %{ "# castLL of $dst, #@castLL" %}
 7893   ins_encode(/* empty encoding */);
 7894   ins_cost(0);
 7895   ins_pipe(pipe_class_empty);
 7896 %}
 7897 
 7898 instruct castII(iRegI dst)
 7899 %{
 7900   match(Set dst (CastII dst));
 7901 
 7902   size(0);
 7903   format %{ "# castII of $dst, #@castII" %}
 7904   ins_encode(/* empty encoding */);
 7905   ins_cost(0);
 7906   ins_pipe(pipe_class_empty);
 7907 %}
 7908 
 7909 instruct checkCastPP(iRegPNoSp dst)
 7910 %{
 7911   match(Set dst (CheckCastPP dst));
 7912 
 7913   size(0);
 7914   ins_cost(0);
 7915   format %{ "# checkcastPP of $dst, #@checkCastPP" %}
 7916   ins_encode(/* empty encoding */);
 7917   ins_pipe(pipe_class_empty);
 7918 %}
 7919 
 7920 instruct castFF(fRegF dst)
 7921 %{
 7922   match(Set dst (CastFF dst));
 7923 
 7924   size(0);
 7925   format %{ "# castFF of $dst" %}
 7926   ins_encode(/* empty encoding */);
 7927   ins_cost(0);
 7928   ins_pipe(pipe_class_empty);
 7929 %}
 7930 
 7931 instruct castDD(fRegD dst)
 7932 %{
 7933   match(Set dst (CastDD dst));
 7934 
 7935   size(0);
 7936   format %{ "# castDD of $dst" %}
 7937   ins_encode(/* empty encoding */);
 7938   ins_cost(0);
 7939   ins_pipe(pipe_class_empty);
 7940 %}
 7941 
 7942 instruct castVV(vReg dst)
 7943 %{
 7944   match(Set dst (CastVV dst));
 7945 
 7946   size(0);
 7947   format %{ "# castVV of $dst" %}
 7948   ins_encode(/* empty encoding */);
 7949   ins_cost(0);
 7950   ins_pipe(pipe_class_empty);
 7951 %}
 7952 
 7953 // ============================================================================
 7954 // Convert Instructions
 7955 
 7956 // int to bool
 7957 instruct convI2Bool(iRegINoSp dst, iRegI src)
 7958 %{
 7959   match(Set dst (Conv2B src));
 7960 
 7961   ins_cost(ALU_COST);
 7962   format %{ "snez  $dst, $src\t#@convI2Bool" %}
 7963 
 7964   ins_encode %{
 7965     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 7966   %}
 7967 
 7968   ins_pipe(ialu_reg);
 7969 %}
 7970 
 7971 // pointer to bool
 7972 instruct convP2Bool(iRegINoSp dst, iRegP src)
 7973 %{
 7974   match(Set dst (Conv2B src));
 7975 
 7976   ins_cost(ALU_COST);
 7977   format %{ "snez  $dst, $src\t#@convP2Bool" %}
 7978 
 7979   ins_encode %{
 7980     __ snez(as_Register($dst$$reg), as_Register($src$$reg));
 7981   %}
 7982 
 7983   ins_pipe(ialu_reg);
 7984 %}
 7985 
 7986 // int <-> long
 7987 
 7988 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
 7989 %{
 7990   match(Set dst (ConvI2L src));
 7991 
 7992   ins_cost(ALU_COST);
 7993   format %{ "addw  $dst, $src, zr\t#@convI2L_reg_reg" %}
 7994   ins_encode %{
 7995     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 7996   %}
 7997   ins_pipe(ialu_reg);
 7998 %}
 7999 
 8000 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
 8001   match(Set dst (ConvL2I src));
 8002 
 8003   ins_cost(ALU_COST);
 8004   format %{ "addw  $dst, $src, zr\t#@convL2I_reg" %}
 8005 
 8006   ins_encode %{
 8007     __ addw(as_Register($dst$$reg), as_Register($src$$reg), zr);
 8008   %}
 8009 
 8010   ins_pipe(ialu_reg);
 8011 %}
 8012 
 8013 // int to unsigned long (Zero-extend)
 8014 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
 8015 %{
 8016   match(Set dst (AndL (ConvI2L src) mask));
 8017 
 8018   ins_cost(ALU_COST * 2);
 8019   format %{ "zero_extend $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
 8020 
 8021   ins_encode %{
 8022     Assembler::CompressibleRegion cr(&_masm);
 8023     __ zero_extend(as_Register($dst$$reg), as_Register($src$$reg), 32);
 8024   %}
 8025 
 8026   ins_pipe(ialu_reg_shift);
 8027 %}
 8028 
 8029 // float <-> double
 8030 
 8031 instruct convF2D_reg(fRegD dst, fRegF src) %{
 8032   match(Set dst (ConvF2D src));
 8033 
 8034   ins_cost(XFER_COST);
 8035   format %{ "fcvt.d.s  $dst, $src\t#@convF2D_reg" %}
 8036 
 8037   ins_encode %{
 8038     __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 8039   %}
 8040 
 8041   ins_pipe(fp_f2d);
 8042 %}
 8043 
 8044 instruct convD2F_reg(fRegF dst, fRegD src) %{
 8045   match(Set dst (ConvD2F src));
 8046 
 8047   ins_cost(XFER_COST);
 8048   format %{ "fcvt.s.d  $dst, $src\t#@convD2F_reg" %}
 8049 
 8050   ins_encode %{
 8051     __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
 8052   %}
 8053 
 8054   ins_pipe(fp_d2f);
 8055 %}
 8056 
 8057 // float <-> int
 8058 
 8059 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8060   match(Set dst (ConvF2I src));
 8061 
 8062   ins_cost(XFER_COST);
 8063   format %{ "fcvt.w.s  $dst, $src\t#@convF2I_reg_reg" %}
 8064 
 8065   ins_encode %{
 8066     __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
 8067   %}
 8068 
 8069   ins_pipe(fp_f2i);
 8070 %}
 8071 
 8072 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
 8073   match(Set dst (ConvI2F src));
 8074 
 8075   ins_cost(XFER_COST);
 8076   format %{ "fcvt.s.w  $dst, $src\t#@convI2F_reg_reg" %}
 8077 
 8078   ins_encode %{
 8079     __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8080   %}
 8081 
 8082   ins_pipe(fp_i2f);
 8083 %}
 8084 
 8085 // float <-> long
 8086 
 8087 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
 8088   match(Set dst (ConvF2L src));
 8089 
 8090   ins_cost(XFER_COST);
 8091   format %{ "fcvt.l.s  $dst, $src\t#@convF2L_reg_reg" %}
 8092 
 8093   ins_encode %{
 8094     __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
 8095   %}
 8096 
 8097   ins_pipe(fp_f2l);
 8098 %}
 8099 
 8100 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
 8101   match(Set dst (ConvL2F src));
 8102 
 8103   ins_cost(XFER_COST);
 8104   format %{ "fcvt.s.l  $dst, $src\t#@convL2F_reg_reg" %}
 8105 
 8106   ins_encode %{
 8107     __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8108   %}
 8109 
 8110   ins_pipe(fp_l2f);
 8111 %}
 8112 
 8113 // double <-> int
 8114 
 8115 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
 8116   match(Set dst (ConvD2I src));
 8117 
 8118   ins_cost(XFER_COST);
 8119   format %{ "fcvt.w.d  $dst, $src\t#@convD2I_reg_reg" %}
 8120 
 8121   ins_encode %{
 8122     __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
 8123   %}
 8124 
 8125   ins_pipe(fp_d2i);
 8126 %}
 8127 
 8128 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
 8129   match(Set dst (ConvI2D src));
 8130 
 8131   ins_cost(XFER_COST);
 8132   format %{ "fcvt.d.w  $dst, $src\t#@convI2D_reg_reg" %}
 8133 
 8134   ins_encode %{
 8135     __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8136   %}
 8137 
 8138   ins_pipe(fp_i2d);
 8139 %}
 8140 
 8141 // double <-> long
 8142 
 8143 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8144   match(Set dst (ConvD2L src));
 8145 
 8146   ins_cost(XFER_COST);
 8147   format %{ "fcvt.l.d  $dst, $src\t#@convD2L_reg_reg" %}
 8148 
 8149   ins_encode %{
 8150     __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
 8151   %}
 8152 
 8153   ins_pipe(fp_d2l);
 8154 %}
 8155 
 8156 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
 8157   match(Set dst (ConvL2D src));
 8158 
 8159   ins_cost(XFER_COST);
 8160   format %{ "fcvt.d.l  $dst, $src\t#@convL2D_reg_reg" %}
 8161 
 8162   ins_encode %{
 8163     __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8164   %}
 8165 
 8166   ins_pipe(fp_l2d);
 8167 %}
 8168 
 8169 // Convert oop into int for vectors alignment masking
 8170 instruct convP2I(iRegINoSp dst, iRegP src) %{
 8171   match(Set dst (ConvL2I (CastP2X src)));
 8172 
 8173   ins_cost(ALU_COST * 2);
 8174   format %{ "zero_extend $dst, $src, 32\t# ptr -> int, #@convP2I" %}
 8175 
 8176   ins_encode %{
 8177     Assembler::CompressibleRegion cr(&_masm);
 8178     __ zero_extend($dst$$Register, $src$$Register, 32);
 8179   %}
 8180 
 8181   ins_pipe(ialu_reg);
 8182 %}
 8183 
 8184 // Convert compressed oop into int for vectors alignment masking
 8185 // in case of 32bit oops (heap < 4Gb).
 8186 instruct convN2I(iRegINoSp dst, iRegN src)
 8187 %{
 8188   predicate(CompressedOops::shift() == 0);
 8189   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 8190 
 8191   ins_cost(ALU_COST);
 8192   format %{ "mv  $dst, $src\t# compressed ptr -> int, #@convN2I" %}
 8193 
 8194   ins_encode %{
 8195     Assembler::CompressibleRegion cr(&_masm);
 8196     __ mv($dst$$Register, $src$$Register);
 8197   %}
 8198 
 8199   ins_pipe(ialu_reg);
 8200 %}
 8201 
 8202 // Convert oop pointer into compressed form
 8203 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
 8204   match(Set dst (EncodeP src));
 8205   ins_cost(ALU_COST);
 8206   format %{ "encode_heap_oop  $dst, $src\t#@encodeHeapOop" %}
 8207   ins_encode %{
 8208     Register s = $src$$Register;
 8209     Register d = $dst$$Register;
 8210     __ encode_heap_oop(d, s);
 8211   %}
 8212   ins_pipe(ialu_reg);
 8213 %}
 8214 
 8215 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
 8216   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 8217             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 8218   match(Set dst (DecodeN src));
 8219 
 8220   ins_cost(0);
 8221   format %{ "decode_heap_oop  $dst, $src\t#@decodeHeapOop" %}
 8222   ins_encode %{
 8223     Register s = $src$$Register;
 8224     Register d = $dst$$Register;
 8225     __ decode_heap_oop(d, s);
 8226   %}
 8227   ins_pipe(ialu_reg);
 8228 %}
 8229 
 8230 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
 8231   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 8232             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 8233   match(Set dst (DecodeN src));
 8234 
 8235   ins_cost(0);
 8236   format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
 8237   ins_encode %{
 8238     Register s = $src$$Register;
 8239     Register d = $dst$$Register;
 8240     __ decode_heap_oop_not_null(d, s);
 8241   %}
 8242   ins_pipe(ialu_reg);
 8243 %}
 8244 
 8245 // Convert klass pointer into compressed form.
 8246 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
 8247   match(Set dst (EncodePKlass src));
 8248 
 8249   ins_cost(ALU_COST);
 8250   format %{ "encode_klass_not_null  $dst, $src\t#@encodeKlass_not_null" %}
 8251 
 8252   ins_encode %{
 8253     Register src_reg = as_Register($src$$reg);
 8254     Register dst_reg = as_Register($dst$$reg);
 8255     __ encode_klass_not_null(dst_reg, src_reg, t0);
 8256   %}
 8257 
 8258    ins_pipe(ialu_reg);
 8259 %}
 8260 
 8261 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
 8262   match(Set dst (DecodeNKlass src));
 8263 
 8264   effect(TEMP tmp);
 8265 
 8266   ins_cost(ALU_COST);
 8267   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
 8268 
 8269   ins_encode %{
 8270     Register src_reg = as_Register($src$$reg);
 8271     Register dst_reg = as_Register($dst$$reg);
 8272     Register tmp_reg = as_Register($tmp$$reg);
 8273     __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
 8274   %}
 8275 
 8276    ins_pipe(ialu_reg);
 8277 %}
 8278 
 8279 // stack <-> reg and reg <-> reg shuffles with no conversion
 8280 
 8281 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
 8282 
 8283   match(Set dst (MoveF2I src));
 8284 
 8285   effect(DEF dst, USE src);
 8286 
 8287   ins_cost(LOAD_COST);
 8288 
 8289   format %{ "lw  $dst, $src\t#@MoveF2I_stack_reg" %}
 8290 
 8291   ins_encode %{
 8292     Assembler::CompressibleRegion cr(&_masm);
 8293     __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
 8294   %}
 8295 
 8296   ins_pipe(iload_reg_reg);
 8297 
 8298 %}
 8299 
 8300 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
 8301 
 8302   match(Set dst (MoveI2F src));
 8303 
 8304   effect(DEF dst, USE src);
 8305 
 8306   ins_cost(LOAD_COST);
 8307 
 8308   format %{ "flw  $dst, $src\t#@MoveI2F_stack_reg" %}
 8309 
 8310   ins_encode %{
 8311     __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8312   %}
 8313 
 8314   ins_pipe(pipe_class_memory);
 8315 
 8316 %}
 8317 
 8318 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
 8319 
 8320   match(Set dst (MoveD2L src));
 8321 
 8322   effect(DEF dst, USE src);
 8323 
 8324   ins_cost(LOAD_COST);
 8325 
 8326   format %{ "ld  $dst, $src\t#@MoveD2L_stack_reg" %}
 8327 
 8328   ins_encode %{
 8329     Assembler::CompressibleRegion cr(&_masm);
 8330     __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
 8331   %}
 8332 
 8333   ins_pipe(iload_reg_reg);
 8334 
 8335 %}
 8336 
 8337 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
 8338 
 8339   match(Set dst (MoveL2D src));
 8340 
 8341   effect(DEF dst, USE src);
 8342 
 8343   ins_cost(LOAD_COST);
 8344 
 8345   format %{ "fld  $dst, $src\t#@MoveL2D_stack_reg" %}
 8346 
 8347   ins_encode %{
 8348     Assembler::CompressibleRegion cr(&_masm);
 8349     __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
 8350   %}
 8351 
 8352   ins_pipe(pipe_class_memory);
 8353 
 8354 %}
 8355 
 8356 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
 8357 
 8358   match(Set dst (MoveF2I src));
 8359 
 8360   effect(DEF dst, USE src);
 8361 
 8362   ins_cost(STORE_COST);
 8363 
 8364   format %{ "fsw  $src, $dst\t#@MoveF2I_reg_stack" %}
 8365 
 8366   ins_encode %{
 8367     __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8368   %}
 8369 
 8370   ins_pipe(pipe_class_memory);
 8371 
 8372 %}
 8373 
 8374 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 8375 
 8376   match(Set dst (MoveI2F src));
 8377 
 8378   effect(DEF dst, USE src);
 8379 
 8380   ins_cost(STORE_COST);
 8381 
 8382   format %{ "sw  $src, $dst\t#@MoveI2F_reg_stack" %}
 8383 
 8384   ins_encode %{
 8385     Assembler::CompressibleRegion cr(&_masm);
 8386     __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
 8387   %}
 8388 
 8389   ins_pipe(istore_reg_reg);
 8390 
 8391 %}
 8392 
 8393 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
 8394 
 8395   match(Set dst (MoveD2L src));
 8396 
 8397   effect(DEF dst, USE src);
 8398 
 8399   ins_cost(STORE_COST);
 8400 
 8401   format %{ "fsd  $dst, $src\t#@MoveD2L_reg_stack" %}
 8402 
 8403   ins_encode %{
 8404     Assembler::CompressibleRegion cr(&_masm);
 8405     __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
 8406   %}
 8407 
 8408   ins_pipe(pipe_class_memory);
 8409 
 8410 %}
 8411 
 8412 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 8413 
 8414   match(Set dst (MoveL2D src));
 8415 
 8416   effect(DEF dst, USE src);
 8417 
 8418   ins_cost(STORE_COST);
 8419 
 8420   format %{ "sd  $src, $dst\t#@MoveL2D_reg_stack" %}
 8421 
 8422   ins_encode %{
 8423     Assembler::CompressibleRegion cr(&_masm);
 8424     __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
 8425   %}
 8426 
 8427   ins_pipe(istore_reg_reg);
 8428 
 8429 %}
 8430 
 8431 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
 8432 
 8433   match(Set dst (MoveF2I src));
 8434 
 8435   effect(DEF dst, USE src);
 8436 
 8437   ins_cost(XFER_COST);
 8438 
 8439   format %{ "fmv.x.w  $dst, $src\t#@MoveL2D_reg_stack" %}
 8440 
 8441   ins_encode %{
 8442     __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8443   %}
 8444 
 8445   ins_pipe(fp_f2i);
 8446 
 8447 %}
 8448 
 8449 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
 8450 
 8451   match(Set dst (MoveI2F src));
 8452 
 8453   effect(DEF dst, USE src);
 8454 
 8455   ins_cost(XFER_COST);
 8456 
 8457   format %{ "fmv.w.x  $dst, $src\t#@MoveI2F_reg_reg" %}
 8458 
 8459   ins_encode %{
 8460     __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8461   %}
 8462 
 8463   ins_pipe(fp_i2f);
 8464 
 8465 %}
 8466 
 8467 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
 8468 
 8469   match(Set dst (MoveD2L src));
 8470 
 8471   effect(DEF dst, USE src);
 8472 
 8473   ins_cost(XFER_COST);
 8474 
 8475   format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
 8476 
 8477   ins_encode %{
 8478     __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
 8479   %}
 8480 
 8481   ins_pipe(fp_d2l);
 8482 
 8483 %}
 8484 
 8485 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
 8486 
 8487   match(Set dst (MoveL2D src));
 8488 
 8489   effect(DEF dst, USE src);
 8490 
 8491   ins_cost(XFER_COST);
 8492 
 8493   format %{ "fmv.d.x  $dst, $src\t#@MoveD2L_reg_reg" %}
 8494 
 8495   ins_encode %{
 8496     __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
 8497   %}
 8498 
 8499   ins_pipe(fp_l2d);
 8500 %}
 8501 
 8502 // ============================================================================
 8503 // Compare Instructions which set the result float comparisons in dest register.
 8504 
 8505 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
 8506 %{
 8507   match(Set dst (CmpF3 op1 op2));
 8508 
 8509   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8510   format %{ "flt.s  $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
 8511             "bgtz   $dst, done\n\t"
 8512             "feq.s  $dst, $op1, $op2\n\t"
 8513             "addi   $dst, $dst, -1\t#@cmpF3_reg_reg"
 8514   %}
 8515 
 8516   ins_encode %{
 8517     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8518     __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
 8519                      as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8520   %}
 8521 
 8522   ins_pipe(pipe_class_default);
 8523 %}
 8524 
 8525 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
 8526 %{
 8527   match(Set dst (CmpD3 op1 op2));
 8528 
 8529   ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
 8530   format %{ "flt.d  $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
 8531             "bgtz   $dst, done\n\t"
 8532             "feq.d  $dst, $op1, $op2\n\t"
 8533             "addi   $dst, $dst, -1\t#@cmpD3_reg_reg"
 8534   %}
 8535 
 8536   ins_encode %{
 8537     // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
 8538     __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
 8539   %}
 8540 
 8541   ins_pipe(pipe_class_default);
 8542 %}
 8543 
 8544 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
 8545 %{
 8546   match(Set dst (CmpL3 op1 op2));
 8547 
 8548   ins_cost(ALU_COST * 3 + BRANCH_COST);
 8549   format %{ "slt   $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
 8550             "bnez  $dst, done\n\t"
 8551             "slt  $dst, $op1, $op2\n\t"
 8552             "neg   $dst, $dst\t#@cmpL3_reg_reg"
 8553   %}
 8554   ins_encode %{
 8555     __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
 8556     __ mv(as_Register($dst$$reg), t0);
 8557   %}
 8558 
 8559   ins_pipe(pipe_class_default);
 8560 %}
 8561 
 8562 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
 8563 %{
 8564   match(Set dst (CmpLTMask p q));
 8565 
 8566   ins_cost(2 * ALU_COST);
 8567 
 8568   format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
 8569             "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
 8570   %}
 8571 
 8572   ins_encode %{
 8573     __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
 8574     __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
 8575   %}
 8576 
 8577   ins_pipe(ialu_reg_reg);
 8578 %}
 8579 
 8580 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
 8581 %{
 8582   match(Set dst (CmpLTMask op zero));
 8583 
 8584   ins_cost(ALU_COST);
 8585 
 8586   format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
 8587 
 8588   ins_encode %{
 8589     __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
 8590   %}
 8591 
 8592   ins_pipe(ialu_reg_shift);
 8593 %}
 8594 
 8595 
 8596 // ============================================================================
 8597 // Max and Min
 8598 
 8599 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8600 %{
 8601   match(Set dst (MinI src1 src2));
 8602 
 8603   effect(DEF dst, USE src1, USE src2);
 8604 
 8605   ins_cost(BRANCH_COST + ALU_COST * 2);
 8606   format %{
 8607     "ble $src1, $src2, Lsrc1.\t#@minI_rReg\n\t"
 8608     "mv $dst, $src2\n\t"
 8609     "j Ldone\n\t"
 8610     "bind Lsrc1\n\t"
 8611     "mv $dst, $src1\n\t"
 8612     "bind\t#@minI_rReg"
 8613   %}
 8614 
 8615   ins_encode %{
 8616     Label Lsrc1, Ldone;
 8617     __ ble(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8618     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8619     __ j(Ldone);
 8620     __ bind(Lsrc1);
 8621     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8622     __ bind(Ldone);
 8623   %}
 8624 
 8625   ins_pipe(ialu_reg_reg);
 8626 %}
 8627 
 8628 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
 8629 %{
 8630   match(Set dst (MaxI src1 src2));
 8631 
 8632   effect(DEF dst, USE src1, USE src2);
 8633 
 8634   ins_cost(BRANCH_COST + ALU_COST * 2);
 8635   format %{
 8636     "bge $src1, $src2, Lsrc1\t#@maxI_rReg\n\t"
 8637     "mv $dst, $src2\n\t"
 8638     "j Ldone\n\t"
 8639     "bind Lsrc1\n\t"
 8640     "mv $dst, $src1\n\t"
 8641     "bind\t#@maxI_rReg"
 8642   %}
 8643 
 8644   ins_encode %{
 8645     Label Lsrc1, Ldone;
 8646     __ bge(as_Register($src1$$reg), as_Register($src2$$reg), Lsrc1);
 8647     __ mv(as_Register($dst$$reg), as_Register($src2$$reg));
 8648     __ j(Ldone);
 8649     __ bind(Lsrc1);
 8650     __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
 8651     __ bind(Ldone);
 8652 
 8653   %}
 8654 
 8655   ins_pipe(ialu_reg_reg);
 8656 %}
 8657 
 8658 // ============================================================================
 8659 // Branch Instructions
 8660 // Direct Branch.
 8661 instruct branch(label lbl)
 8662 %{
 8663   match(Goto);
 8664 
 8665   effect(USE lbl);
 8666 
 8667   ins_cost(BRANCH_COST);
 8668   format %{ "j  $lbl\t#@branch" %}
 8669 
 8670   ins_encode(riscv_enc_j(lbl));
 8671 
 8672   ins_pipe(pipe_branch);
 8673 %}
 8674 
 8675 // ============================================================================
 8676 // Compare and Branch Instructions
 8677 
 8678 // Patterns for short (< 12KiB) variants
 8679 
 8680 // Compare flags and branch near instructions.
 8681 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
 8682   match(If cmp cr);
 8683   effect(USE lbl);
 8684 
 8685   ins_cost(BRANCH_COST);
 8686   format %{ "b$cmp  $cr, zr, $lbl\t#@cmpFlag_branch" %}
 8687 
 8688   ins_encode %{
 8689     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
 8690   %}
 8691   ins_pipe(pipe_cmpz_branch);
 8692   ins_short_branch(1);
 8693 %}
 8694 
 8695 // Compare signed int and branch near instructions
 8696 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8697 %{
 8698   // Same match rule as `far_cmpI_branch'.
 8699   match(If cmp (CmpI op1 op2));
 8700 
 8701   effect(USE lbl);
 8702 
 8703   ins_cost(BRANCH_COST);
 8704 
 8705   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_branch" %}
 8706 
 8707   ins_encode %{
 8708     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8709   %}
 8710 
 8711   ins_pipe(pipe_cmp_branch);
 8712   ins_short_branch(1);
 8713 %}
 8714 
 8715 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
 8716 %{
 8717   // Same match rule as `far_cmpI_loop'.
 8718   match(CountedLoopEnd cmp (CmpI op1 op2));
 8719 
 8720   effect(USE lbl);
 8721 
 8722   ins_cost(BRANCH_COST);
 8723 
 8724   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpI_loop" %}
 8725 
 8726   ins_encode %{
 8727     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8728   %}
 8729 
 8730   ins_pipe(pipe_cmp_branch);
 8731   ins_short_branch(1);
 8732 %}
 8733 
 8734 // Compare unsigned int and branch near instructions
 8735 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8736 %{
 8737   // Same match rule as `far_cmpU_branch'.
 8738   match(If cmp (CmpU op1 op2));
 8739 
 8740   effect(USE lbl);
 8741 
 8742   ins_cost(BRANCH_COST);
 8743 
 8744   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_branch" %}
 8745 
 8746   ins_encode %{
 8747     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8748                   as_Register($op2$$reg), *($lbl$$label));
 8749   %}
 8750 
 8751   ins_pipe(pipe_cmp_branch);
 8752   ins_short_branch(1);
 8753 %}
 8754 
 8755 instruct cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
 8756 %{
 8757   // Same match rule as `far_cmpU_loop'.
 8758   match(CountedLoopEnd cmp (CmpU op1 op2));
 8759 
 8760   effect(USE lbl);
 8761 
 8762   ins_cost(BRANCH_COST);
 8763 
 8764   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpU_loop" %}
 8765 
 8766   ins_encode %{
 8767     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8768                   as_Register($op2$$reg), *($lbl$$label));
 8769   %}
 8770 
 8771   ins_pipe(pipe_cmp_branch);
 8772   ins_short_branch(1);
 8773 %}
 8774 
 8775 // Compare signed long and branch near instructions
 8776 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8777 %{
 8778   // Same match rule as `far_cmpL_branch'.
 8779   match(If cmp (CmpL op1 op2));
 8780 
 8781   effect(USE lbl);
 8782 
 8783   ins_cost(BRANCH_COST);
 8784 
 8785   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_branch" %}
 8786 
 8787   ins_encode %{
 8788     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8789   %}
 8790 
 8791   ins_pipe(pipe_cmp_branch);
 8792   ins_short_branch(1);
 8793 %}
 8794 
 8795 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
 8796 %{
 8797   // Same match rule as `far_cmpL_loop'.
 8798   match(CountedLoopEnd cmp (CmpL op1 op2));
 8799 
 8800   effect(USE lbl);
 8801 
 8802   ins_cost(BRANCH_COST);
 8803 
 8804   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpL_loop" %}
 8805 
 8806   ins_encode %{
 8807     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
 8808   %}
 8809 
 8810   ins_pipe(pipe_cmp_branch);
 8811   ins_short_branch(1);
 8812 %}
 8813 
 8814 // Compare unsigned long and branch near instructions
 8815 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 8816 %{
 8817   // Same match rule as `far_cmpUL_branch'.
 8818   match(If cmp (CmpUL op1 op2));
 8819 
 8820   effect(USE lbl);
 8821 
 8822   ins_cost(BRANCH_COST);
 8823   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_branch" %}
 8824 
 8825   ins_encode %{
 8826     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8827                   as_Register($op2$$reg), *($lbl$$label));
 8828   %}
 8829 
 8830   ins_pipe(pipe_cmp_branch);
 8831   ins_short_branch(1);
 8832 %}
 8833 
 8834 instruct cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
 8835 %{
 8836   // Same match rule as `far_cmpUL_loop'.
 8837   match(CountedLoopEnd cmp (CmpUL op1 op2));
 8838 
 8839   effect(USE lbl);
 8840 
 8841   ins_cost(BRANCH_COST);
 8842   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpUL_loop" %}
 8843 
 8844   ins_encode %{
 8845     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8846                   as_Register($op2$$reg), *($lbl$$label));
 8847   %}
 8848 
 8849   ins_pipe(pipe_cmp_branch);
 8850   ins_short_branch(1);
 8851 %}
 8852 
 8853 // Compare pointer and branch near instructions
 8854 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 8855 %{
 8856   // Same match rule as `far_cmpP_branch'.
 8857   match(If cmp (CmpP op1 op2));
 8858 
 8859   effect(USE lbl);
 8860 
 8861   ins_cost(BRANCH_COST);
 8862 
 8863   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_branch" %}
 8864 
 8865   ins_encode %{
 8866     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8867                   as_Register($op2$$reg), *($lbl$$label));
 8868   %}
 8869 
 8870   ins_pipe(pipe_cmp_branch);
 8871   ins_short_branch(1);
 8872 %}
 8873 
 8874 instruct cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 8875 %{
 8876   // Same match rule as `far_cmpP_loop'.
 8877   match(CountedLoopEnd cmp (CmpP op1 op2));
 8878 
 8879   effect(USE lbl);
 8880 
 8881   ins_cost(BRANCH_COST);
 8882 
 8883   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpP_loop" %}
 8884 
 8885   ins_encode %{
 8886     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8887                   as_Register($op2$$reg), *($lbl$$label));
 8888   %}
 8889 
 8890   ins_pipe(pipe_cmp_branch);
 8891   ins_short_branch(1);
 8892 %}
 8893 
 8894 // Compare narrow pointer and branch near instructions
 8895 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 8896 %{
 8897   // Same match rule as `far_cmpN_branch'.
 8898   match(If cmp (CmpN op1 op2));
 8899 
 8900   effect(USE lbl);
 8901 
 8902   ins_cost(BRANCH_COST);
 8903 
 8904   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_branch" %}
 8905 
 8906   ins_encode %{
 8907     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8908                   as_Register($op2$$reg), *($lbl$$label));
 8909   %}
 8910 
 8911   ins_pipe(pipe_cmp_branch);
 8912   ins_short_branch(1);
 8913 %}
 8914 
 8915 instruct cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 8916 %{
 8917   // Same match rule as `far_cmpN_loop'.
 8918   match(CountedLoopEnd cmp (CmpN op1 op2));
 8919 
 8920   effect(USE lbl);
 8921 
 8922   ins_cost(BRANCH_COST);
 8923 
 8924   format %{ "b$cmp  $op1, $op2, $lbl\t#@cmpN_loop" %}
 8925 
 8926   ins_encode %{
 8927     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 8928                   as_Register($op2$$reg), *($lbl$$label));
 8929   %}
 8930 
 8931   ins_pipe(pipe_cmp_branch);
 8932   ins_short_branch(1);
 8933 %}
 8934 
 8935 // Compare float and branch near instructions
 8936 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 8937 %{
 8938   // Same match rule as `far_cmpF_branch'.
 8939   match(If cmp (CmpF op1 op2));
 8940 
 8941   effect(USE lbl);
 8942 
 8943   ins_cost(XFER_COST + BRANCH_COST);
 8944   format %{ "float_b$cmp $op1, $op2 \t#@cmpF_branch"%}
 8945 
 8946   ins_encode %{
 8947     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 8948   %}
 8949 
 8950   ins_pipe(pipe_class_compare);
 8951   ins_short_branch(1);
 8952 %}
 8953 
 8954 instruct cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 8955 %{
 8956   // Same match rule as `far_cmpF_loop'.
 8957   match(CountedLoopEnd cmp (CmpF op1 op2));
 8958   effect(USE lbl);
 8959 
 8960   ins_cost(XFER_COST + BRANCH_COST);
 8961   format %{ "float_b$cmp $op1, $op2\t#@cmpF_loop"%}
 8962 
 8963   ins_encode %{
 8964     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
 8965   %}
 8966 
 8967   ins_pipe(pipe_class_compare);
 8968   ins_short_branch(1);
 8969 %}
 8970 
 8971 // Compare double and branch near instructions
 8972 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 8973 %{
 8974   // Same match rule as `far_cmpD_branch'.
 8975   match(If cmp (CmpD op1 op2));
 8976   effect(USE lbl);
 8977 
 8978   ins_cost(XFER_COST + BRANCH_COST);
 8979   format %{ "double_b$cmp $op1, $op2\t#@cmpD_branch"%}
 8980 
 8981   ins_encode %{
 8982     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 8983                         as_FloatRegister($op2$$reg), *($lbl$$label));
 8984   %}
 8985 
 8986   ins_pipe(pipe_class_compare);
 8987   ins_short_branch(1);
 8988 %}
 8989 
 8990 instruct cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 8991 %{
 8992   // Same match rule as `far_cmpD_loop'.
 8993   match(CountedLoopEnd cmp (CmpD op1 op2));
 8994   effect(USE lbl);
 8995 
 8996   ins_cost(XFER_COST + BRANCH_COST);
 8997   format %{ "double_b$cmp $op1, $op2\t#@cmpD_loop"%}
 8998 
 8999   ins_encode %{
 9000     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9001                         as_FloatRegister($op2$$reg), *($lbl$$label));
 9002   %}
 9003 
 9004   ins_pipe(pipe_class_compare);
 9005   ins_short_branch(1);
 9006 %}
 9007 
 9008 // Compare signed int with zero and branch near instructions
 9009 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9010 %{
 9011   // Same match rule as `far_cmpI_reg_imm0_branch'.
 9012   match(If cmp (CmpI op1 zero));
 9013 
 9014   effect(USE op1, USE lbl);
 9015 
 9016   ins_cost(BRANCH_COST);
 9017   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
 9018 
 9019   ins_encode %{
 9020     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9021   %}
 9022 
 9023   ins_pipe(pipe_cmpz_branch);
 9024   ins_short_branch(1);
 9025 %}
 9026 
 9027 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9028 %{
 9029   // Same match rule as `far_cmpI_reg_imm0_loop'.
 9030   match(CountedLoopEnd cmp (CmpI op1 zero));
 9031 
 9032   effect(USE op1, USE lbl);
 9033 
 9034   ins_cost(BRANCH_COST);
 9035 
 9036   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
 9037 
 9038   ins_encode %{
 9039     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9040   %}
 9041 
 9042   ins_pipe(pipe_cmpz_branch);
 9043   ins_short_branch(1);
 9044 %}
 9045 
 9046 // Compare unsigned int with zero and branch near instructions
 9047 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9048 %{
 9049   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
 9050   match(If cmp (CmpU op1 zero));
 9051 
 9052   effect(USE op1, USE lbl);
 9053 
 9054   ins_cost(BRANCH_COST);
 9055 
 9056   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
 9057 
 9058   ins_encode %{
 9059     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9060   %}
 9061 
 9062   ins_pipe(pipe_cmpz_branch);
 9063   ins_short_branch(1);
 9064 %}
 9065 
 9066 instruct cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9067 %{
 9068   // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_loop'.
 9069   match(CountedLoopEnd cmp (CmpU op1 zero));
 9070 
 9071   effect(USE op1, USE lbl);
 9072 
 9073   ins_cost(BRANCH_COST);
 9074 
 9075   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_loop" %}
 9076 
 9077 
 9078   ins_encode %{
 9079     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9080   %}
 9081 
 9082   ins_pipe(pipe_cmpz_branch);
 9083   ins_short_branch(1);
 9084 %}
 9085 
 9086 // Compare signed long with zero and branch near instructions
 9087 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9088 %{
 9089   // Same match rule as `far_cmpL_reg_imm0_branch'.
 9090   match(If cmp (CmpL op1 zero));
 9091 
 9092   effect(USE op1, USE lbl);
 9093 
 9094   ins_cost(BRANCH_COST);
 9095 
 9096   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
 9097 
 9098   ins_encode %{
 9099     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9100   %}
 9101 
 9102   ins_pipe(pipe_cmpz_branch);
 9103   ins_short_branch(1);
 9104 %}
 9105 
 9106 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9107 %{
 9108   // Same match rule as `far_cmpL_reg_imm0_loop'.
 9109   match(CountedLoopEnd cmp (CmpL op1 zero));
 9110 
 9111   effect(USE op1, USE lbl);
 9112 
 9113   ins_cost(BRANCH_COST);
 9114 
 9115   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
 9116 
 9117   ins_encode %{
 9118     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
 9119   %}
 9120 
 9121   ins_pipe(pipe_cmpz_branch);
 9122   ins_short_branch(1);
 9123 %}
 9124 
 9125 // Compare unsigned long with zero and branch near instructions
 9126 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9127 %{
 9128   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
 9129   match(If cmp (CmpUL op1 zero));
 9130 
 9131   effect(USE op1, USE lbl);
 9132 
 9133   ins_cost(BRANCH_COST);
 9134 
 9135   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
 9136 
 9137   ins_encode %{
 9138     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9139   %}
 9140 
 9141   ins_pipe(pipe_cmpz_branch);
 9142   ins_short_branch(1);
 9143 %}
 9144 
 9145 instruct cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9146 %{
 9147   // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_loop'.
 9148   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9149 
 9150   effect(USE op1, USE lbl);
 9151 
 9152   ins_cost(BRANCH_COST);
 9153 
 9154   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_loop" %}
 9155 
 9156   ins_encode %{
 9157     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9158   %}
 9159 
 9160   ins_pipe(pipe_cmpz_branch);
 9161   ins_short_branch(1);
 9162 %}
 9163 
 9164 // Compare pointer with zero and branch near instructions
 9165 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9166   // Same match rule as `far_cmpP_reg_imm0_branch'.
 9167   match(If cmp (CmpP op1 zero));
 9168   effect(USE lbl);
 9169 
 9170   ins_cost(BRANCH_COST);
 9171   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
 9172 
 9173   ins_encode %{
 9174     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9175   %}
 9176 
 9177   ins_pipe(pipe_cmpz_branch);
 9178   ins_short_branch(1);
 9179 %}
 9180 
 9181 instruct cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9182   // Same match rule as `far_cmpP_reg_imm0_loop'.
 9183   match(CountedLoopEnd cmp (CmpP op1 zero));
 9184   effect(USE lbl);
 9185 
 9186   ins_cost(BRANCH_COST);
 9187   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_imm0_loop" %}
 9188 
 9189   ins_encode %{
 9190     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9191   %}
 9192 
 9193   ins_pipe(pipe_cmpz_branch);
 9194   ins_short_branch(1);
 9195 %}
 9196 
 9197 // Compare narrow pointer with zero and branch near instructions
 9198 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9199   // Same match rule as `far_cmpN_reg_imm0_branch'.
 9200   match(If cmp (CmpN op1 zero));
 9201   effect(USE lbl);
 9202 
 9203   ins_cost(BRANCH_COST);
 9204 
 9205   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
 9206 
 9207   ins_encode %{
 9208     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9209   %}
 9210 
 9211   ins_pipe(pipe_cmpz_branch);
 9212   ins_short_branch(1);
 9213 %}
 9214 
 9215 instruct cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9216   // Same match rule as `far_cmpN_reg_imm0_loop'.
 9217   match(CountedLoopEnd cmp (CmpN op1 zero));
 9218   effect(USE lbl);
 9219 
 9220   ins_cost(BRANCH_COST);
 9221 
 9222   format %{ "b$cmp  $op1, zr, $lbl\t#@cmpN_imm0_loop" %}
 9223 
 9224   ins_encode %{
 9225     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9226   %}
 9227 
 9228   ins_pipe(pipe_cmpz_branch);
 9229   ins_short_branch(1);
 9230 %}
 9231 
 9232 // Compare narrow pointer with pointer zero and branch near instructions
 9233 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9234   // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
 9235   match(If cmp (CmpP (DecodeN op1) zero));
 9236   effect(USE lbl);
 9237 
 9238   ins_cost(BRANCH_COST);
 9239   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
 9240 
 9241   ins_encode %{
 9242     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9243   %}
 9244 
 9245   ins_pipe(pipe_cmpz_branch);
 9246   ins_short_branch(1);
 9247 %}
 9248 
 9249 instruct cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9250   // Same match rule as `far_cmpP_narrowOop_imm0_loop'.
 9251   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9252   effect(USE lbl);
 9253 
 9254   ins_cost(BRANCH_COST);
 9255   format %{ "b$cmp   $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_loop" %}
 9256 
 9257   ins_encode %{
 9258     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
 9259   %}
 9260 
 9261   ins_pipe(pipe_cmpz_branch);
 9262   ins_short_branch(1);
 9263 %}
 9264 
 9265 // Patterns for far (20KiB) variants
 9266 
 9267 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
 9268   match(If cmp cr);
 9269   effect(USE lbl);
 9270 
 9271   ins_cost(BRANCH_COST);
 9272   format %{ "far_b$cmp $cr, zr, L\t#@far_cmpFlag_branch"%}
 9273 
 9274   ins_encode %{
 9275     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
 9276   %}
 9277 
 9278   ins_pipe(pipe_cmpz_branch);
 9279 %}
 9280 
 9281 // Compare signed int and branch far instructions
 9282 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9283   match(If cmp (CmpI op1 op2));
 9284   effect(USE lbl);
 9285 
 9286   ins_cost(BRANCH_COST * 2);
 9287 
 9288   // the format instruction [far_b$cmp] here is be used as two insructions
 9289   // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
 9290   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_branch" %}
 9291 
 9292   ins_encode %{
 9293     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9294   %}
 9295 
 9296   ins_pipe(pipe_cmp_branch);
 9297 %}
 9298 
 9299 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
 9300   match(CountedLoopEnd cmp (CmpI op1 op2));
 9301   effect(USE lbl);
 9302 
 9303   ins_cost(BRANCH_COST * 2);
 9304   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpI_loop" %}
 9305 
 9306   ins_encode %{
 9307     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9308   %}
 9309 
 9310   ins_pipe(pipe_cmp_branch);
 9311 %}
 9312 
 9313 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9314   match(If cmp (CmpU op1 op2));
 9315   effect(USE lbl);
 9316 
 9317   ins_cost(BRANCH_COST * 2);
 9318   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
 9319 
 9320   ins_encode %{
 9321     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9322                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9323   %}
 9324 
 9325   ins_pipe(pipe_cmp_branch);
 9326 %}
 9327 
 9328 instruct far_cmpU_loop(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
 9329   match(CountedLoopEnd cmp (CmpU op1 op2));
 9330   effect(USE lbl);
 9331 
 9332   ins_cost(BRANCH_COST * 2);
 9333   format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_loop" %}
 9334 
 9335   ins_encode %{
 9336     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9337                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9338   %}
 9339 
 9340   ins_pipe(pipe_cmp_branch);
 9341 %}
 9342 
 9343 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9344   match(If cmp (CmpL op1 op2));
 9345   effect(USE lbl);
 9346 
 9347   ins_cost(BRANCH_COST * 2);
 9348   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_branch" %}
 9349 
 9350   ins_encode %{
 9351     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9352   %}
 9353 
 9354   ins_pipe(pipe_cmp_branch);
 9355 %}
 9356 
 9357 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
 9358   match(CountedLoopEnd cmp (CmpL op1 op2));
 9359   effect(USE lbl);
 9360 
 9361   ins_cost(BRANCH_COST * 2);
 9362   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpL_loop" %}
 9363 
 9364   ins_encode %{
 9365     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9366   %}
 9367 
 9368   ins_pipe(pipe_cmp_branch);
 9369 %}
 9370 
 9371 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9372   match(If cmp (CmpUL op1 op2));
 9373   effect(USE lbl);
 9374 
 9375   ins_cost(BRANCH_COST * 2);
 9376   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
 9377 
 9378   ins_encode %{
 9379     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9380                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9381   %}
 9382 
 9383   ins_pipe(pipe_cmp_branch);
 9384 %}
 9385 
 9386 instruct far_cmpUL_loop(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
 9387   match(CountedLoopEnd cmp (CmpUL op1 op2));
 9388   effect(USE lbl);
 9389 
 9390   ins_cost(BRANCH_COST * 2);
 9391   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpUL_loop" %}
 9392 
 9393   ins_encode %{
 9394     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9395                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9396   %}
 9397 
 9398   ins_pipe(pipe_cmp_branch);
 9399 %}
 9400 
 9401 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9402 %{
 9403   match(If cmp (CmpP op1 op2));
 9404 
 9405   effect(USE lbl);
 9406 
 9407   ins_cost(BRANCH_COST * 2);
 9408 
 9409   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_branch" %}
 9410 
 9411   ins_encode %{
 9412     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9413                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9414   %}
 9415 
 9416   ins_pipe(pipe_cmp_branch);
 9417 %}
 9418 
 9419 instruct far_cmpP_loop(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
 9420 %{
 9421   match(CountedLoopEnd cmp (CmpP op1 op2));
 9422 
 9423   effect(USE lbl);
 9424 
 9425   ins_cost(BRANCH_COST * 2);
 9426 
 9427   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpP_loop" %}
 9428 
 9429   ins_encode %{
 9430     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9431                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9432   %}
 9433 
 9434   ins_pipe(pipe_cmp_branch);
 9435 %}
 9436 
 9437 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9438 %{
 9439   match(If cmp (CmpN op1 op2));
 9440 
 9441   effect(USE lbl);
 9442 
 9443   ins_cost(BRANCH_COST * 2);
 9444 
 9445   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_branch" %}
 9446 
 9447   ins_encode %{
 9448     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9449                        as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9450   %}
 9451 
 9452   ins_pipe(pipe_cmp_branch);
 9453 %}
 9454 
 9455 instruct far_cmpN_loop(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
 9456 %{
 9457   match(CountedLoopEnd cmp (CmpN op1 op2));
 9458 
 9459   effect(USE lbl);
 9460 
 9461   ins_cost(BRANCH_COST * 2);
 9462 
 9463   format %{ "far_b$cmp  $op1, $op2, $lbl\t#@far_cmpN_loop" %}
 9464 
 9465   ins_encode %{
 9466     __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
 9467                   as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
 9468   %}
 9469 
 9470   ins_pipe(pipe_cmp_branch);
 9471 %}
 9472 
 9473 // Float compare and branch instructions
 9474 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9475 %{
 9476   match(If cmp (CmpF op1 op2));
 9477 
 9478   effect(USE lbl);
 9479 
 9480   ins_cost(XFER_COST + BRANCH_COST * 2);
 9481   format %{ "far_float_b$cmp $op1, $op2\t#@far_cmpF_branch"%}
 9482 
 9483   ins_encode %{
 9484     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9485                         *($lbl$$label), /* is_far */ true);
 9486   %}
 9487 
 9488   ins_pipe(pipe_class_compare);
 9489 %}
 9490 
 9491 instruct far_cmpF_loop(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
 9492 %{
 9493   match(CountedLoopEnd cmp (CmpF op1 op2));
 9494   effect(USE lbl);
 9495 
 9496   ins_cost(XFER_COST + BRANCH_COST * 2);
 9497   format %{ "far_float_b$cmp $op1, $op2\t#@far_cmpF_loop"%}
 9498 
 9499   ins_encode %{
 9500     __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
 9501                         *($lbl$$label), /* is_far */ true);
 9502   %}
 9503 
 9504   ins_pipe(pipe_class_compare);
 9505 %}
 9506 
 9507 // Double compare and branch instructions
 9508 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9509 %{
 9510   match(If cmp (CmpD op1 op2));
 9511   effect(USE lbl);
 9512 
 9513   ins_cost(XFER_COST + BRANCH_COST * 2);
 9514   format %{ "far_double_b$cmp $op1, $op2\t#@far_cmpD_branch"%}
 9515 
 9516   ins_encode %{
 9517     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9518                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9519   %}
 9520 
 9521   ins_pipe(pipe_class_compare);
 9522 %}
 9523 
 9524 instruct far_cmpD_loop(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
 9525 %{
 9526   match(CountedLoopEnd cmp (CmpD op1 op2));
 9527   effect(USE lbl);
 9528 
 9529   ins_cost(XFER_COST + BRANCH_COST * 2);
 9530   format %{ "far_double_b$cmp $op1, $op2\t#@far_cmpD_loop"%}
 9531 
 9532   ins_encode %{
 9533     __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
 9534                         as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
 9535   %}
 9536 
 9537   ins_pipe(pipe_class_compare);
 9538 %}
 9539 
 9540 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9541 %{
 9542   match(If cmp (CmpI op1 zero));
 9543 
 9544   effect(USE op1, USE lbl);
 9545 
 9546   ins_cost(BRANCH_COST * 2);
 9547 
 9548   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
 9549 
 9550   ins_encode %{
 9551     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9552   %}
 9553 
 9554   ins_pipe(pipe_cmpz_branch);
 9555 %}
 9556 
 9557 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
 9558 %{
 9559   match(CountedLoopEnd cmp (CmpI op1 zero));
 9560 
 9561   effect(USE op1, USE lbl);
 9562 
 9563   ins_cost(BRANCH_COST * 2);
 9564 
 9565   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
 9566 
 9567   ins_encode %{
 9568     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9569   %}
 9570 
 9571   ins_pipe(pipe_cmpz_branch);
 9572 %}
 9573 
 9574 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9575 %{
 9576   match(If cmp (CmpU op1 zero));
 9577 
 9578   effect(USE op1, USE lbl);
 9579 
 9580   ins_cost(BRANCH_COST * 2);
 9581 
 9582   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
 9583 
 9584   ins_encode %{
 9585     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9586   %}
 9587 
 9588   ins_pipe(pipe_cmpz_branch);
 9589 %}
 9590 
 9591 instruct far_cmpUEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
 9592 %{
 9593   match(CountedLoopEnd cmp (CmpU op1 zero));
 9594 
 9595   effect(USE op1, USE lbl);
 9596 
 9597   ins_cost(BRANCH_COST * 2);
 9598 
 9599   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_reg_imm0_loop" %}
 9600 
 9601 
 9602   ins_encode %{
 9603     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9604   %}
 9605 
 9606   ins_pipe(pipe_cmpz_branch);
 9607 %}
 9608 
 9609 // compare lt/ge unsigned instructs has no short instruct with same match
 9610 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9611 %{
 9612   match(If cmp (CmpU op1 zero));
 9613 
 9614   effect(USE op1, USE lbl);
 9615 
 9616   ins_cost(BRANCH_COST);
 9617 
 9618   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
 9619 
 9620   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9621 
 9622   ins_pipe(pipe_cmpz_branch);
 9623 %}
 9624 
 9625 instruct far_cmpULtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
 9626 %{
 9627   match(CountedLoopEnd cmp (CmpU op1 zero));
 9628 
 9629   effect(USE op1, USE lbl);
 9630 
 9631   ins_cost(BRANCH_COST);
 9632 
 9633   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_loop" %}
 9634 
 9635   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9636 
 9637   ins_pipe(pipe_cmpz_branch);
 9638 %}
 9639 
 9640 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9641 %{
 9642   match(If cmp (CmpL op1 zero));
 9643 
 9644   effect(USE op1, USE lbl);
 9645 
 9646   ins_cost(BRANCH_COST * 2);
 9647 
 9648   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
 9649 
 9650   ins_encode %{
 9651     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9652   %}
 9653 
 9654   ins_pipe(pipe_cmpz_branch);
 9655 %}
 9656 
 9657 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
 9658 %{
 9659   match(CountedLoopEnd cmp (CmpL op1 zero));
 9660 
 9661   effect(USE op1, USE lbl);
 9662 
 9663   ins_cost(BRANCH_COST * 2);
 9664 
 9665   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
 9666 
 9667   ins_encode %{
 9668     __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
 9669   %}
 9670 
 9671   ins_pipe(pipe_cmpz_branch);
 9672 %}
 9673 
 9674 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9675 %{
 9676   match(If cmp (CmpUL op1 zero));
 9677 
 9678   effect(USE op1, USE lbl);
 9679 
 9680   ins_cost(BRANCH_COST * 2);
 9681 
 9682   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
 9683 
 9684   ins_encode %{
 9685     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9686   %}
 9687 
 9688   ins_pipe(pipe_cmpz_branch);
 9689 %}
 9690 
 9691 instruct far_cmpULEqNeLeGt_reg_imm0_loop(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
 9692 %{
 9693   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9694 
 9695   effect(USE op1, USE lbl);
 9696 
 9697   ins_cost(BRANCH_COST * 2);
 9698 
 9699   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_loop" %}
 9700 
 9701   ins_encode %{
 9702     __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9703   %}
 9704 
 9705   ins_pipe(pipe_cmpz_branch);
 9706 %}
 9707 
 9708 // compare lt/ge unsigned instructs has no short instruct with same match
 9709 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9710 %{
 9711   match(If cmp (CmpUL op1 zero));
 9712 
 9713   effect(USE op1, USE lbl);
 9714 
 9715   ins_cost(BRANCH_COST);
 9716 
 9717   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
 9718 
 9719   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9720 
 9721   ins_pipe(pipe_cmpz_branch);
 9722 %}
 9723 
 9724 instruct far_cmpULLtGe_reg_imm0_loop(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
 9725 %{
 9726   match(CountedLoopEnd cmp (CmpUL op1 zero));
 9727 
 9728   effect(USE op1, USE lbl);
 9729 
 9730   ins_cost(BRANCH_COST);
 9731 
 9732   format %{ "j  $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_loop" %}
 9733 
 9734   ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
 9735 
 9736   ins_pipe(pipe_cmpz_branch);
 9737 %}
 9738 
 9739 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9740   match(If cmp (CmpP op1 zero));
 9741   effect(USE lbl);
 9742 
 9743   ins_cost(BRANCH_COST * 2);
 9744   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
 9745 
 9746   ins_encode %{
 9747     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9748   %}
 9749 
 9750   ins_pipe(pipe_cmpz_branch);
 9751 %}
 9752 
 9753 instruct far_cmpP_imm0_loop(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
 9754   match(CountedLoopEnd cmp (CmpP op1 zero));
 9755   effect(USE lbl);
 9756 
 9757   ins_cost(BRANCH_COST * 2);
 9758   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_imm0_loop" %}
 9759 
 9760   ins_encode %{
 9761     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9762   %}
 9763 
 9764   ins_pipe(pipe_cmpz_branch);
 9765 %}
 9766 
 9767 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9768   match(If cmp (CmpN op1 zero));
 9769   effect(USE lbl);
 9770 
 9771   ins_cost(BRANCH_COST * 2);
 9772 
 9773   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
 9774 
 9775   ins_encode %{
 9776     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9777   %}
 9778 
 9779   ins_pipe(pipe_cmpz_branch);
 9780 %}
 9781 
 9782 instruct far_cmpN_imm0_loop(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
 9783   match(CountedLoopEnd cmp (CmpN op1 zero));
 9784   effect(USE lbl);
 9785 
 9786   ins_cost(BRANCH_COST * 2);
 9787 
 9788   format %{ "far_b$cmp  $op1, zr, $lbl\t#@far_cmpN_imm0_loop" %}
 9789 
 9790   ins_encode %{
 9791     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9792   %}
 9793 
 9794   ins_pipe(pipe_cmpz_branch);
 9795 %}
 9796 
 9797 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9798   match(If cmp (CmpP (DecodeN op1) zero));
 9799   effect(USE lbl);
 9800 
 9801   ins_cost(BRANCH_COST * 2);
 9802   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
 9803 
 9804   ins_encode %{
 9805     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9806   %}
 9807 
 9808   ins_pipe(pipe_cmpz_branch);
 9809 %}
 9810 
 9811 instruct far_cmpP_narrowOop_imm0_loop(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
 9812   match(CountedLoopEnd cmp (CmpP (DecodeN op1) zero));
 9813   effect(USE lbl);
 9814 
 9815   ins_cost(BRANCH_COST * 2);
 9816   format %{ "far_b$cmp   $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_loop" %}
 9817 
 9818   ins_encode %{
 9819     __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
 9820   %}
 9821 
 9822   ins_pipe(pipe_cmpz_branch);
 9823 %}
 9824 
 9825 // ============================================================================
 9826 // Conditional Move Instructions
 9827 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
 9828   match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
 9829   ins_cost(ALU_COST + BRANCH_COST);
 9830 
 9831   format %{
 9832              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpI\n\t"
 9833              "mv $dst, $src\n\t"
 9834              "skip:"
 9835          %}
 9836 
 9837   ins_encode %{
 9838     __ enc_cmove($cop$$cmpcode,
 9839                  as_Register($op1$$reg), as_Register($op2$$reg),
 9840                  as_Register($dst$$reg), as_Register($src$$reg));
 9841   %}
 9842 
 9843   ins_pipe(pipe_slow);
 9844 %}
 9845 
 9846 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
 9847   match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
 9848   ins_cost(ALU_COST + BRANCH_COST);
 9849 
 9850   format %{
 9851              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpU\n\t"
 9852              "mv $dst, $src\n\t"
 9853              "skip:"
 9854          %}
 9855 
 9856   ins_encode %{
 9857     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9858                  as_Register($op1$$reg), as_Register($op2$$reg),
 9859                  as_Register($dst$$reg), as_Register($src$$reg));
 9860   %}
 9861 
 9862   ins_pipe(pipe_slow);
 9863 %}
 9864 
 9865 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
 9866   match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
 9867   ins_cost(ALU_COST + BRANCH_COST);
 9868 
 9869   format %{
 9870              "bneg$cop $op1, $op2, skip\t#@cmovI_cmpL\n\t"
 9871              "mv $dst, $src\n\t"
 9872              "skip:"
 9873          %}
 9874 
 9875   ins_encode %{
 9876     __ enc_cmove($cop$$cmpcode,
 9877                  as_Register($op1$$reg), as_Register($op2$$reg),
 9878                  as_Register($dst$$reg), as_Register($src$$reg));
 9879   %}
 9880 
 9881   ins_pipe(pipe_slow);
 9882 %}
 9883 
 9884 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
 9885   match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
 9886   ins_cost(ALU_COST + BRANCH_COST);
 9887 
 9888   format %{
 9889              "bneg$cop $op1, $op2, skip\t#@cmovL_cmpL\n\t"
 9890              "mv $dst, $src\n\t"
 9891              "skip:"
 9892          %}
 9893 
 9894   ins_encode %{
 9895     __ enc_cmove($cop$$cmpcode,
 9896                  as_Register($op1$$reg), as_Register($op2$$reg),
 9897                  as_Register($dst$$reg), as_Register($src$$reg));
 9898   %}
 9899 
 9900   ins_pipe(pipe_slow);
 9901 %}
 9902 
 9903 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
 9904   match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
 9905   ins_cost(ALU_COST + BRANCH_COST);
 9906 
 9907   format %{
 9908              "bneg$cop $op1, $op2, skip\t#@cmovL_cmpUL\n\t"
 9909              "mv $dst, $src\n\t"
 9910              "skip:"
 9911          %}
 9912 
 9913   ins_encode %{
 9914     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9915                  as_Register($op1$$reg), as_Register($op2$$reg),
 9916                  as_Register($dst$$reg), as_Register($src$$reg));
 9917   %}
 9918 
 9919   ins_pipe(pipe_slow);
 9920 %}
 9921 
 9922 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
 9923   match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
 9924   ins_cost(ALU_COST + BRANCH_COST);
 9925   format %{
 9926              "bneg$cop $op1, $op2\t#@cmovI_cmpUL\n\t"
 9927              "mv $dst, $src\n\t"
 9928              "skip:"
 9929          %}
 9930 
 9931   ins_encode %{
 9932     __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
 9933                  as_Register($op1$$reg), as_Register($op2$$reg),
 9934                  as_Register($dst$$reg), as_Register($src$$reg));
 9935   %}
 9936 
 9937   ins_pipe(pipe_slow);
 9938 %}
 9939 
 9940 
 9941 // ============================================================================
 9942 // Procedure Call/Return Instructions
 9943 
 9944 // Call Java Static Instruction
 9945 // Note: If this code changes, the corresponding ret_addr_offset() and
 9946 //       compute_padding() functions will have to be adjusted.
 9947 instruct CallStaticJavaDirect(method meth)
 9948 %{
 9949   match(CallStaticJava);
 9950 
 9951   effect(USE meth);
 9952 
 9953   ins_cost(BRANCH_COST);
 9954 
 9955   format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
 9956 
 9957   ins_encode(riscv_enc_java_static_call(meth),
 9958              riscv_enc_call_epilog);
 9959 
 9960   ins_pipe(pipe_class_call);
 9961   ins_alignment(4);
 9962 %}
 9963 
 9964 // TO HERE
 9965 
 9966 // Call Java Dynamic Instruction
 9967 // Note: If this code changes, the corresponding ret_addr_offset() and
 9968 //       compute_padding() functions will have to be adjusted.
 9969 instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
 9970 %{
 9971   match(CallDynamicJava);
 9972 
 9973   effect(USE meth, KILL cr);
 9974 
 9975   ins_cost(BRANCH_COST + ALU_COST * 6);
 9976 
 9977   format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
 9978 
 9979   ins_encode(riscv_enc_java_dynamic_call(meth),
 9980              riscv_enc_call_epilog);
 9981 
 9982   ins_pipe(pipe_class_call);
 9983   ins_alignment(4);
 9984 %}
 9985 
 9986 // Call Runtime Instruction
 9987 
 9988 instruct CallRuntimeDirect(method meth, rFlagsReg cr)
 9989 %{
 9990   match(CallRuntime);
 9991 
 9992   effect(USE meth, KILL cr);
 9993 
 9994   ins_cost(BRANCH_COST);
 9995 
 9996   format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
 9997 
 9998   ins_encode(riscv_enc_java_to_runtime(meth));
 9999 
10000   ins_pipe(pipe_class_call);
10001 %}
10002 
10003 // Call Runtime Instruction
10004 
10005 instruct CallLeafDirect(method meth, rFlagsReg cr)
10006 %{
10007   match(CallLeaf);
10008 
10009   effect(USE meth, KILL cr);
10010 
10011   ins_cost(BRANCH_COST);
10012 
10013   format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10014 
10015   ins_encode(riscv_enc_java_to_runtime(meth));
10016 
10017   ins_pipe(pipe_class_call);
10018 %}
10019 
10020 // Call Runtime Instruction
10021 
10022 instruct CallLeafNoFPDirect(method meth, rFlagsReg cr)
10023 %{
10024   match(CallLeafNoFP);
10025 
10026   effect(USE meth, KILL cr);
10027 
10028   ins_cost(BRANCH_COST);
10029 
10030   format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10031 
10032   ins_encode(riscv_enc_java_to_runtime(meth));
10033 
10034   ins_pipe(pipe_class_call);
10035 %}
10036 
10037 // ============================================================================
10038 // Partial Subtype Check
10039 //
10040 // superklass array for an instance of the superklass.  Set a hidden
10041 // internal cache on a hit (cache is checked with exposed code in
10042 // gen_subtype_check()).  Return zero for a hit.  The encoding
10043 // ALSO sets flags.
10044 
10045 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10046 %{
10047   match(Set result (PartialSubtypeCheck sub super));
10048   effect(KILL tmp, KILL cr);
10049 
10050   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10051   format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10052 
10053   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10054 
10055   opcode(0x1); // Force zero of result reg on hit
10056 
10057   ins_pipe(pipe_class_memory);
10058 %}
10059 
10060 instruct partialSubtypeCheckVsZero(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp,
10061                                    immP0 zero, rFlagsReg cr)
10062 %{
10063   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
10064   effect(KILL tmp, KILL result);
10065 
10066   ins_cost(2 * STORE_COST + 3 * LOAD_COST + 4 * ALU_COST + BRANCH_COST * 4);
10067   format %{ "partialSubtypeCheck $result, $sub, $super == 0\t#@partialSubtypeCheckVsZero" %}
10068 
10069   ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10070 
10071   opcode(0x0); // Don't zero result reg on hit
10072 
10073   ins_pipe(pipe_class_memory);
10074 %}
10075 
10076 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10077                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10078 %{
10079   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10080   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10081   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10082 
10083   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10084   ins_encode %{
10085     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10086     __ string_compare($str1$$Register, $str2$$Register,
10087                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10088                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10089                       StrIntrinsicNode::UU);
10090   %}
10091   ins_pipe(pipe_class_memory);
10092 %}
10093 
10094 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10095                          iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10096 %{
10097   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10098   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10099   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10100 
10101   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10102   ins_encode %{
10103     __ string_compare($str1$$Register, $str2$$Register,
10104                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10105                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10106                       StrIntrinsicNode::LL);
10107   %}
10108   ins_pipe(pipe_class_memory);
10109 %}
10110 
10111 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10112                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10113 %{
10114   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10115   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10116   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10117 
10118   format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10119   ins_encode %{
10120     __ string_compare($str1$$Register, $str2$$Register,
10121                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10122                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10123                       StrIntrinsicNode::UL);
10124   %}
10125   ins_pipe(pipe_class_memory);
10126 %}
10127 
10128 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10129                           iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10130                           rFlagsReg cr)
10131 %{
10132   predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10133   match(Set result (StrComp(Binary str1 cnt1)(Binary str2 cnt2)));
10134   effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10135 
10136   format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10137   ins_encode %{
10138     __ string_compare($str1$$Register, $str2$$Register,
10139                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10140                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10141                       StrIntrinsicNode::LU);
10142   %}
10143   ins_pipe(pipe_class_memory);
10144 %}
10145 
10146 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10147                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10148                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10149 %{
10150   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10151   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10152   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10153          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10154 
10155   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10156   ins_encode %{
10157     __ string_indexof($str1$$Register, $str2$$Register,
10158                       $cnt1$$Register, $cnt2$$Register,
10159                       $tmp1$$Register, $tmp2$$Register,
10160                       $tmp3$$Register, $tmp4$$Register,
10161                       $tmp5$$Register, $tmp6$$Register,
10162                       $result$$Register, StrIntrinsicNode::UU);
10163   %}
10164   ins_pipe(pipe_class_memory);
10165 %}
10166 
10167 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10168                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10169                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10170 %{
10171   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10172   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10173   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10174          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10175 
10176   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10177   ins_encode %{
10178     __ string_indexof($str1$$Register, $str2$$Register,
10179                       $cnt1$$Register, $cnt2$$Register,
10180                       $tmp1$$Register, $tmp2$$Register,
10181                       $tmp3$$Register, $tmp4$$Register,
10182                       $tmp5$$Register, $tmp6$$Register,
10183                       $result$$Register, StrIntrinsicNode::LL);
10184   %}
10185   ins_pipe(pipe_class_memory);
10186 %}
10187 
10188 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10189                           iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10190                           iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10191 %{
10192   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10193   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10194   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10195          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10196   format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10197 
10198   ins_encode %{
10199     __ string_indexof($str1$$Register, $str2$$Register,
10200                       $cnt1$$Register, $cnt2$$Register,
10201                       $tmp1$$Register, $tmp2$$Register,
10202                       $tmp3$$Register, $tmp4$$Register,
10203                       $tmp5$$Register, $tmp6$$Register,
10204                       $result$$Register, StrIntrinsicNode::UL);
10205   %}
10206   ins_pipe(pipe_class_memory);
10207 %}
10208 
10209 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10210                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10211                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10212 %{
10213   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10214   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10215   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10216          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10217 
10218   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10219 
10220   ins_encode %{
10221     int icnt2 = (int)$int_cnt2$$constant;
10222     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10223                                  $cnt1$$Register, zr,
10224                                  $tmp1$$Register, $tmp2$$Register,
10225                                  $tmp3$$Register, $tmp4$$Register,
10226                                  icnt2, $result$$Register, StrIntrinsicNode::UU);
10227   %}
10228   ins_pipe(pipe_class_memory);
10229 %}
10230 
10231 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10232                               immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10233                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10234 %{
10235   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10236   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10237   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10238          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10239 
10240   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10241   ins_encode %{
10242     int icnt2 = (int)$int_cnt2$$constant;
10243     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10244                                  $cnt1$$Register, zr,
10245                                  $tmp1$$Register, $tmp2$$Register,
10246                                  $tmp3$$Register, $tmp4$$Register,
10247                                  icnt2, $result$$Register, StrIntrinsicNode::LL);
10248   %}
10249   ins_pipe(pipe_class_memory);
10250 %}
10251 
10252 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10253                               immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10254                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10255 %{
10256   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10257   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10258   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10259          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10260 
10261   format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10262   ins_encode %{
10263     int icnt2 = (int)$int_cnt2$$constant;
10264     __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10265                                  $cnt1$$Register, zr,
10266                                  $tmp1$$Register, $tmp2$$Register,
10267                                  $tmp3$$Register, $tmp4$$Register,
10268                                  icnt2, $result$$Register, StrIntrinsicNode::UL);
10269   %}
10270   ins_pipe(pipe_class_memory);
10271 %}
10272 
10273 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10274                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10275                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10276 %{
10277   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10278   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10279   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10280          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10281 
10282   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10283   ins_encode %{
10284     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10285                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10286                            $tmp3$$Register, $tmp4$$Register, false /* isU */);
10287   %}
10288   ins_pipe(pipe_class_memory);
10289 %}
10290 
10291 
10292 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10293                               iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10294                               iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10295 %{
10296   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10297   predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10298   effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10299          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10300 
10301   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
10302   ins_encode %{
10303     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10304                            $result$$Register, $tmp1$$Register, $tmp2$$Register,
10305                            $tmp3$$Register, $tmp4$$Register, true /* isL */);
10306   %}
10307   ins_pipe(pipe_class_memory);
10308 %}
10309 
10310 // clearing of an array
10311 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy)
10312 %{
10313   predicate(!UseRVV);
10314   match(Set dummy (ClearArray cnt base));
10315   effect(USE_KILL cnt, USE_KILL base);
10316 
10317   ins_cost(4 * DEFAULT_COST);
10318   format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10319 
10320   ins_encode %{
10321     address tpc = __ zero_words($base$$Register, $cnt$$Register);
10322     if (tpc == NULL) {
10323       ciEnv::current()->record_failure("CodeCache is full");
10324       return;
10325     }
10326   %}
10327 
10328   ins_pipe(pipe_class_memory);
10329 %}
10330 
10331 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10332 %{
10333   predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10334             < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10335   match(Set dummy (ClearArray cnt base));
10336   effect(USE_KILL base, KILL cr);
10337 
10338   ins_cost(4 * DEFAULT_COST);
10339   format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10340 
10341   ins_encode %{
10342     __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10343   %}
10344 
10345   ins_pipe(pipe_class_memory);
10346 %}
10347 
10348 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10349                         iRegI_R10 result, rFlagsReg cr)
10350 %{
10351   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10352   match(Set result (StrEquals (Binary str1 str2) cnt));
10353   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10354 
10355   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10356   ins_encode %{
10357     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10358     __ string_equals($str1$$Register, $str2$$Register,
10359                      $result$$Register, $cnt$$Register, 1);
10360   %}
10361   ins_pipe(pipe_class_memory);
10362 %}
10363 
10364 instruct string_equalsU(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10365                         iRegI_R10 result, rFlagsReg cr)
10366 %{
10367   predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10368   match(Set result (StrEquals (Binary str1 str2) cnt));
10369   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10370 
10371   format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsU" %}
10372   ins_encode %{
10373     // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10374     __ string_equals($str1$$Register, $str2$$Register,
10375                      $result$$Register, $cnt$$Register, 2);
10376   %}
10377   ins_pipe(pipe_class_memory);
10378 %}
10379 
10380 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10381                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10382                        iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10383 %{
10384   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10385   match(Set result (AryEq ary1 ary2));
10386   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10387 
10388   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsB // KILL $tmp5" %}
10389   ins_encode %{
10390     __ arrays_equals($ary1$$Register, $ary2$$Register,
10391                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10392                      $result$$Register, $tmp5$$Register, 1);
10393   %}
10394   ins_pipe(pipe_class_memory);
10395 %}
10396 
10397 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10398                        iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3,
10399                        iRegP_R16 tmp4, iRegP_R28 tmp5, rFlagsReg cr)
10400 %{
10401   predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10402   match(Set result (AryEq ary1 ary2));
10403   effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL tmp5, KILL cr);
10404 
10405   format %{ "Array Equals $ary1, ary2 -> $result\t#@array_equalsC // KILL $tmp5" %}
10406   ins_encode %{
10407     __ arrays_equals($ary1$$Register, $ary2$$Register,
10408                      $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10409                      $result$$Register, $tmp5$$Register, 2);
10410   %}
10411   ins_pipe(pipe_class_memory);
10412 %}
10413 
10414 // ============================================================================
10415 // Safepoint Instructions
10416 
10417 instruct safePoint(iRegP poll)
10418 %{
10419   match(SafePoint poll);
10420 
10421   ins_cost(2 * LOAD_COST);
10422   format %{
10423     "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10424   %}
10425   ins_encode %{
10426     __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10427   %}
10428   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10429 %}
10430 
10431 // ============================================================================
10432 // This name is KNOWN by the ADLC and cannot be changed.
10433 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10434 // for this guy.
10435 instruct tlsLoadP(javaThread_RegP dst)
10436 %{
10437   match(Set dst (ThreadLocal));
10438 
10439   ins_cost(0);
10440 
10441   format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10442 
10443   size(0);
10444 
10445   ins_encode( /*empty*/ );
10446 
10447   ins_pipe(pipe_class_empty);
10448 %}
10449 
10450 // inlined locking and unlocking
10451 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10452 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10453 %{
10454   match(Set cr (FastLock object box));
10455   effect(TEMP tmp1, TEMP tmp2);
10456 
10457   ins_cost(LOAD_COST * 2 + STORE_COST * 3 + ALU_COST * 6 + BRANCH_COST * 3);
10458   format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2, #@cmpFastLock" %}
10459 
10460   ins_encode(riscv_enc_fast_lock(object, box, tmp1, tmp2));
10461 
10462   ins_pipe(pipe_serial);
10463 %}
10464 
10465 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10466 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10467 %{
10468   match(Set cr (FastUnlock object box));
10469   effect(TEMP tmp1, TEMP tmp2);
10470 
10471   ins_cost(LOAD_COST * 2 + STORE_COST + ALU_COST * 2 + BRANCH_COST * 4);
10472   format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10473 
10474   ins_encode(riscv_enc_fast_unlock(object, box, tmp1, tmp2));
10475 
10476   ins_pipe(pipe_serial);
10477 %}
10478 
10479 // Tail Call; Jump from runtime stub to Java code.
10480 // Also known as an 'interprocedural jump'.
10481 // Target of jump will eventually return to caller.
10482 // TailJump below removes the return address.
10483 instruct TailCalljmpInd(iRegPNoSp jump_target, inline_cache_RegP method_oop)
10484 %{
10485   match(TailCall jump_target method_oop);
10486 
10487   ins_cost(BRANCH_COST);
10488 
10489   format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10490 
10491   ins_encode(riscv_enc_tail_call(jump_target));
10492 
10493   ins_pipe(pipe_class_call);
10494 %}
10495 
10496 instruct TailjmpInd(iRegPNoSp jump_target, iRegP_R10 ex_oop)
10497 %{
10498   match(TailJump jump_target ex_oop);
10499 
10500   ins_cost(ALU_COST + BRANCH_COST);
10501 
10502   format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10503 
10504   ins_encode(riscv_enc_tail_jmp(jump_target));
10505 
10506   ins_pipe(pipe_class_call);
10507 %}
10508 
10509 // Create exception oop: created by stack-crawling runtime code.
10510 // Created exception is now available to this handler, and is setup
10511 // just prior to jumping to this handler. No code emitted.
10512 instruct CreateException(iRegP_R10 ex_oop)
10513 %{
10514   match(Set ex_oop (CreateEx));
10515 
10516   ins_cost(0);
10517   format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10518 
10519   size(0);
10520 
10521   ins_encode( /*empty*/ );
10522 
10523   ins_pipe(pipe_class_empty);
10524 %}
10525 
10526 // Rethrow exception: The exception oop will come in the first
10527 // argument position. Then JUMP (not call) to the rethrow stub code.
10528 instruct RethrowException()
10529 %{
10530   match(Rethrow);
10531 
10532   ins_cost(BRANCH_COST);
10533 
10534   format %{ "j rethrow_stub\t#@RethrowException" %}
10535 
10536   ins_encode(riscv_enc_rethrow());
10537 
10538   ins_pipe(pipe_class_call);
10539 %}
10540 
10541 // Return Instruction
10542 // epilog node loads ret address into ra as part of frame pop
10543 instruct Ret()
10544 %{
10545   match(Return);
10546 
10547   ins_cost(BRANCH_COST);
10548   format %{ "ret\t// return register, #@Ret" %}
10549 
10550   ins_encode(riscv_enc_ret());
10551 
10552   ins_pipe(pipe_branch);
10553 %}
10554 
10555 // Die now.
10556 instruct ShouldNotReachHere() %{
10557   match(Halt);
10558 
10559   ins_cost(BRANCH_COST);
10560 
10561   format %{ "#@ShouldNotReachHere" %}
10562 
10563   ins_encode %{
10564     Assembler::CompressibleRegion cr(&_masm);
10565     if (is_reachable()) {
10566       __ halt();
10567     }
10568   %}
10569 
10570   ins_pipe(pipe_class_default);
10571 %}
10572 
10573 
10574 //----------PEEPHOLE RULES-----------------------------------------------------
10575 // These must follow all instruction definitions as they use the names
10576 // defined in the instructions definitions.
10577 //
10578 // peepmatch ( root_instr_name [preceding_instruction]* );
10579 //
10580 // peepconstraint %{
10581 // (instruction_number.operand_name relational_op instruction_number.operand_name
10582 //  [, ...] );
10583 // // instruction numbers are zero-based using left to right order in peepmatch
10584 //
10585 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10586 // // provide an instruction_number.operand_name for each operand that appears
10587 // // in the replacement instruction's match rule
10588 //
10589 // ---------VM FLAGS---------------------------------------------------------
10590 //
10591 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10592 //
10593 // Each peephole rule is given an identifying number starting with zero and
10594 // increasing by one in the order seen by the parser.  An individual peephole
10595 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10596 // on the command-line.
10597 //
10598 // ---------CURRENT LIMITATIONS----------------------------------------------
10599 //
10600 // Only match adjacent instructions in same basic block
10601 // Only equality constraints
10602 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10603 // Only one replacement instruction
10604 //
10605 //----------SMARTSPILL RULES---------------------------------------------------
10606 // These must follow all instruction definitions as they use the names
10607 // defined in the instructions definitions.
10608 
10609 // Local Variables:
10610 // mode: c++
10611 // End: