1 /*
 2  * Copyright (c) 2006, 2019, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
 4  * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
 5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 6  *
 7  * This code is free software; you can redistribute it and/or modify it
 8  * under the terms of the GNU General Public License version 2 only, as
 9  * published by the Free Software Foundation.
10  *
11  * This code is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14  * version 2 for more details (a copy is included in the LICENSE file that
15  * accompanied this code).
16  *
17  * You should have received a copy of the GNU General Public License version
18  * 2 along with this work; if not, write to the Free Software Foundation,
19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22  * or visit www.oracle.com if you need additional information or have any
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26 
27 #ifndef CPU_RISCV_VMREG_RISCV_HPP
28 #define CPU_RISCV_VMREG_RISCV_HPP
29 
30 inline bool is_Register() {
31   return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr;
32 }
33 
34 inline bool is_FloatRegister() {
35   return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr;
36 }
37 
38 inline bool is_VectorRegister() {
39   return value() >= ConcreteRegisterImpl::max_fpr && value() < ConcreteRegisterImpl::max_vpr;
40 }
41 
42 inline Register as_Register() {
43   assert( is_Register(), "must be");
44   return ::as_Register(value() / RegisterImpl::max_slots_per_register);
45 }
46 
47 inline FloatRegister as_FloatRegister() {
48   assert( is_FloatRegister() && is_even(value()), "must be" );
49   return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) /
50                             FloatRegisterImpl::max_slots_per_register);
51 }
52 
53 inline VectorRegister as_VectorRegister() {
54   assert( is_VectorRegister() && ((value() & (VectorRegisterImpl::max_slots_per_register - 1)) == 0), "must be" );
55   return ::as_VectorRegister((value() - ConcreteRegisterImpl::max_fpr) /
56                              VectorRegisterImpl::max_slots_per_register);
57 }
58 
59 inline bool is_concrete() {
60   assert(is_reg(), "must be");
61   if (is_VectorRegister()) {
62     int base = value() - ConcreteRegisterImpl::max_fpr;
63     return (base % VectorRegisterImpl::max_slots_per_register) == 0;
64   } else {
65     return is_even(value());
66   }
67 }
68 
69 #endif // CPU_RISCV_VMREG_RISCV_HPP