1 /*
 2  * Copyright (c) 2006, 2020, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
 4  * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
 5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 6  *
 7  * This code is free software; you can redistribute it and/or modify it
 8  * under the terms of the GNU General Public License version 2 only, as
 9  * published by the Free Software Foundation.
10  *
11  * This code is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14  * version 2 for more details (a copy is included in the LICENSE file that
15  * accompanied this code).
16  *
17  * You should have received a copy of the GNU General Public License version
18  * 2 along with this work; if not, write to the Free Software Foundation,
19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20  *
21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22  * or visit www.oracle.com if you need additional information or have any
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25  */
26 
27 #ifndef CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP
28 #define CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP
29 
30 inline VMReg RegisterImpl::as_VMReg() {
31   if( this == noreg ) {
32     return VMRegImpl::Bad();
33   }
34   return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register);
35 }
36 
37 inline VMReg FloatRegisterImpl::as_VMReg() {
38   return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) +
39                              ConcreteRegisterImpl::max_gpr);
40 }
41 
42 inline VMReg VectorRegisterImpl::as_VMReg() {
43   return VMRegImpl::as_VMReg((encoding() * VectorRegisterImpl::max_slots_per_register) +
44                              ConcreteRegisterImpl::max_fpr);
45 }
46 
47 #endif // CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP