1 /* 2 * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016, 2019 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_LIRAssembler.hpp" 30 #include "c1/c1_MacroAssembler.hpp" 31 #include "c1/c1_Runtime1.hpp" 32 #include "c1/c1_ValueStack.hpp" 33 #include "ci/ciArrayKlass.hpp" 34 #include "ci/ciInstance.hpp" 35 #include "gc/shared/collectedHeap.hpp" 36 #include "memory/universe.hpp" 37 #include "nativeInst_s390.hpp" 38 #include "oops/objArrayKlass.hpp" 39 #include "runtime/frame.inline.hpp" 40 #include "runtime/safepointMechanism.inline.hpp" 41 #include "runtime/sharedRuntime.hpp" 42 #include "runtime/stubRoutines.hpp" 43 #include "utilities/powerOfTwo.hpp" 44 #include "vmreg_s390.inline.hpp" 45 46 #define __ _masm-> 47 48 #ifndef PRODUCT 49 #undef __ 50 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)-> 51 #endif 52 53 //------------------------------------------------------------ 54 55 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 56 // Not used on ZARCH_64 57 ShouldNotCallThis(); 58 return false; 59 } 60 61 LIR_Opr LIR_Assembler::receiverOpr() { 62 return FrameMap::Z_R2_oop_opr; 63 } 64 65 LIR_Opr LIR_Assembler::osrBufferPointer() { 66 return FrameMap::Z_R2_opr; 67 } 68 69 int LIR_Assembler::initial_frame_size_in_bytes() const { 70 return in_bytes(frame_map()->framesize_in_bytes()); 71 } 72 73 // Inline cache check: done before the frame is built. 74 // The inline cached class is in Z_inline_cache(Z_R9). 75 // We fetch the class of the receiver and compare it with the cached class. 76 // If they do not match we jump to the slow case. 77 int LIR_Assembler::check_icache() { 78 Register receiver = receiverOpr()->as_register(); 79 int offset = __ offset(); 80 __ inline_cache_check(receiver, Z_inline_cache); 81 return offset; 82 } 83 84 void LIR_Assembler::clinit_barrier(ciMethod* method) { 85 assert(!method->holder()->is_not_initialized(), "initialization should have been started"); 86 87 Label L_skip_barrier; 88 Register klass = Z_R1_scratch; 89 90 metadata2reg(method->holder()->constant_encoding(), klass); 91 __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/); 92 93 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub()); 94 __ z_br(klass); 95 96 __ bind(L_skip_barrier); 97 } 98 99 void LIR_Assembler::osr_entry() { 100 // On-stack-replacement entry sequence (interpreter frame layout described in frame_s390.hpp): 101 // 102 // 1. Create a new compiled activation. 103 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 104 // at the osr_bci; it is not initialized. 105 // 3. Jump to the continuation address in compiled code to resume execution. 106 107 // OSR entry point 108 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 109 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 110 ValueStack* entry_state = osr_entry->end()->state(); 111 int number_of_locks = entry_state->locks_size(); 112 113 // Create a frame for the compiled activation. 114 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 115 116 // OSR buffer is 117 // 118 // locals[nlocals-1..0] 119 // monitors[number_of_locks-1..0] 120 // 121 // Locals is a direct copy of the interpreter frame so in the osr buffer 122 // the first slot in the local array is the last local from the interpreter 123 // and the last slot is local[0] (receiver) from the interpreter 124 // 125 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 126 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 127 // in the interpreter frame (the method lock if a sync method) 128 129 // Initialize monitors in the compiled activation. 130 // I0: pointer to osr buffer 131 // 132 // All other registers are dead at this point and the locals will be 133 // copied into place by code emitted in the IR. 134 135 Register OSR_buf = osrBufferPointer()->as_register(); 136 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 137 int monitor_offset = BytesPerWord * method()->max_locals() + 138 (2 * BytesPerWord) * (number_of_locks - 1); 139 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 140 // the OSR buffer using 2 word entries: first the lock and then 141 // the oop. 142 for (int i = 0; i < number_of_locks; i++) { 143 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 144 // Verify the interpreter's monitor has a non-null object. 145 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__); 146 // Copy the lock field into the compiled activation. 147 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf); 148 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i)); 149 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf); 150 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i)); 151 } 152 } 153 } 154 155 // -------------------------------------------------------------------------------------------- 156 157 address LIR_Assembler::emit_call_c(address a) { 158 __ align_call_far_patchable(__ pc()); 159 address call_addr = __ call_c_opt(a); 160 if (call_addr == NULL) { 161 bailout("const section overflow"); 162 } 163 return call_addr; 164 } 165 166 int LIR_Assembler::emit_exception_handler() { 167 // If the last instruction is a call (typically to do a throw which 168 // is coming at the end after block reordering) the return address 169 // must still point into the code area in order to avoid assertion 170 // failures when searching for the corresponding bci. => Add a nop. 171 // (was bug 5/14/1999 - gri) 172 __ nop(); 173 174 // Generate code for exception handler. 175 address handler_base = __ start_a_stub(exception_handler_size()); 176 if (handler_base == NULL) { 177 // Not enough space left for the handler. 178 bailout("exception handler overflow"); 179 return -1; 180 } 181 182 int offset = code_offset(); 183 184 address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id); 185 address call_addr = emit_call_c(a); 186 CHECK_BAILOUT_(-1); 187 __ should_not_reach_here(); 188 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 189 __ end_a_stub(); 190 191 return offset; 192 } 193 194 // Emit the code to remove the frame from the stack in the exception 195 // unwind path. 196 int LIR_Assembler::emit_unwind_handler() { 197 #ifndef PRODUCT 198 if (CommentedAssembly) { 199 _masm->block_comment("Unwind handler"); 200 } 201 #endif 202 203 int offset = code_offset(); 204 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved. 205 Register Rtmp1 = Z_R11; 206 Register Rtmp2 = Z_R12; 207 208 // Fetch the exception from TLS and clear out exception related thread state. 209 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset()); 210 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset()); 211 __ z_lg(Z_EXC_OOP, exc_oop_addr); 212 __ clear_mem(exc_oop_addr, sizeof(oop)); 213 __ clear_mem(exc_pc_addr, sizeof(intptr_t)); 214 215 __ bind(_unwind_handler_entry); 216 __ verify_not_null_oop(Z_EXC_OOP); 217 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 218 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception. 219 } 220 221 // Preform needed unlocking. 222 MonitorExitStub* stub = NULL; 223 if (method()->is_synchronized()) { 224 // Runtime1::monitorexit_id expects lock address in Z_R1_scratch. 225 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch); 226 monitor_address(0, lock); 227 stub = new MonitorExitStub(lock, true, 0); 228 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry()); 229 __ bind(*stub->continuation()); 230 } 231 232 if (compilation()->env()->dtrace_method_probes()) { 233 ShouldNotReachHere(); // Not supported. 234 #if 0 235 __ mov(rdi, r15_thread); 236 __ mov_metadata(rsi, method()->constant_encoding()); 237 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 238 #endif 239 } 240 241 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 242 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception. 243 } 244 245 // Remove the activation and dispatch to the unwind handler. 246 __ pop_frame(); 247 __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP); 248 249 // Z_EXC_OOP: exception oop 250 // Z_EXC_PC: exception pc 251 252 // Dispatch to the unwind logic. 253 __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id)); 254 __ z_br(Z_R5); 255 256 // Emit the slow path assembly. 257 if (stub != NULL) { 258 stub->emit_code(this); 259 } 260 261 return offset; 262 } 263 264 int LIR_Assembler::emit_deopt_handler() { 265 // If the last instruction is a call (typically to do a throw which 266 // is coming at the end after block reordering) the return address 267 // must still point into the code area in order to avoid assertion 268 // failures when searching for the corresponding bci. => Add a nop. 269 // (was bug 5/14/1999 - gri) 270 __ nop(); 271 272 // Generate code for exception handler. 273 address handler_base = __ start_a_stub(deopt_handler_size()); 274 if (handler_base == NULL) { 275 // Not enough space left for the handler. 276 bailout("deopt handler overflow"); 277 return -1; 278 } int offset = code_offset(); 279 // Size must be constant (see HandlerImpl::emit_deopt_handler). 280 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack()); 281 __ call(Z_R1_scratch); 282 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 283 __ end_a_stub(); 284 285 return offset; 286 } 287 288 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 289 if (o == NULL) { 290 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove. 291 } else { 292 AddressLiteral a = __ allocate_oop_address(o); 293 bool success = __ load_oop_from_toc(reg, a, reg); 294 if (!success) { 295 bailout("const section overflow"); 296 } 297 } 298 } 299 300 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 301 // Allocate a new index in table to hold the object once it's been patched. 302 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 303 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 304 305 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index)); 306 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 307 // The NULL will be dynamically patched later so the sequence to 308 // load the address literal must not be optimized. 309 __ load_const(reg, addrlit); 310 311 patching_epilog(patch, lir_patch_normal, reg, info); 312 } 313 314 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) { 315 bool success = __ set_metadata_constant(md, reg); 316 if (!success) { 317 bailout("const section overflow"); 318 return; 319 } 320 } 321 322 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 323 // Allocate a new index in table to hold the klass once it's been patched. 324 int index = __ oop_recorder()->allocate_metadata_index(NULL); 325 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 326 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index)); 327 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 328 // The NULL will be dynamically patched later so the sequence to 329 // load the address literal must not be optimized. 330 __ load_const(reg, addrlit); 331 332 patching_epilog(patch, lir_patch_normal, reg, info); 333 } 334 335 void LIR_Assembler::emit_op3(LIR_Op3* op) { 336 switch (op->code()) { 337 case lir_idiv: 338 case lir_irem: 339 arithmetic_idiv(op->code(), 340 op->in_opr1(), 341 op->in_opr2(), 342 op->in_opr3(), 343 op->result_opr(), 344 op->info()); 345 break; 346 case lir_fmad: { 347 const FloatRegister opr1 = op->in_opr1()->as_double_reg(), 348 opr2 = op->in_opr2()->as_double_reg(), 349 opr3 = op->in_opr3()->as_double_reg(), 350 res = op->result_opr()->as_double_reg(); 351 __ z_madbr(opr3, opr1, opr2); 352 if (res != opr3) { __ z_ldr(res, opr3); } 353 } break; 354 case lir_fmaf: { 355 const FloatRegister opr1 = op->in_opr1()->as_float_reg(), 356 opr2 = op->in_opr2()->as_float_reg(), 357 opr3 = op->in_opr3()->as_float_reg(), 358 res = op->result_opr()->as_float_reg(); 359 __ z_maebr(opr3, opr1, opr2); 360 if (res != opr3) { __ z_ler(res, opr3); } 361 } break; 362 default: ShouldNotReachHere(); break; 363 } 364 } 365 366 367 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 368 #ifdef ASSERT 369 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 370 if (op->block() != NULL) { _branch_target_blocks.append(op->block()); } 371 if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); } 372 #endif 373 374 if (op->cond() == lir_cond_always) { 375 if (op->info() != NULL) { add_debug_info_for_branch(op->info()); } 376 __ branch_optimized(Assembler::bcondAlways, *(op->label())); 377 } else { 378 Assembler::branch_condition acond = Assembler::bcondZero; 379 if (op->code() == lir_cond_float_branch) { 380 assert(op->ublock() != NULL, "must have unordered successor"); 381 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label())); 382 } 383 switch (op->cond()) { 384 case lir_cond_equal: acond = Assembler::bcondEqual; break; 385 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break; 386 case lir_cond_less: acond = Assembler::bcondLow; break; 387 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break; 388 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break; 389 case lir_cond_greater: acond = Assembler::bcondHigh; break; 390 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break; 391 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break; 392 default: ShouldNotReachHere(); 393 } 394 __ branch_optimized(acond,*(op->label())); 395 } 396 } 397 398 399 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 400 LIR_Opr src = op->in_opr(); 401 LIR_Opr dest = op->result_opr(); 402 403 switch (op->bytecode()) { 404 case Bytecodes::_i2l: 405 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT); 406 break; 407 408 case Bytecodes::_l2i: 409 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG); 410 break; 411 412 case Bytecodes::_i2b: 413 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT); 414 break; 415 416 case Bytecodes::_i2c: 417 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT); 418 break; 419 420 case Bytecodes::_i2s: 421 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT); 422 break; 423 424 case Bytecodes::_f2d: 425 assert(dest->is_double_fpu(), "check"); 426 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT); 427 break; 428 429 case Bytecodes::_d2f: 430 assert(dest->is_single_fpu(), "check"); 431 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE); 432 break; 433 434 case Bytecodes::_i2f: 435 __ z_cefbr(dest->as_float_reg(), src->as_register()); 436 break; 437 438 case Bytecodes::_i2d: 439 __ z_cdfbr(dest->as_double_reg(), src->as_register()); 440 break; 441 442 case Bytecodes::_l2f: 443 __ z_cegbr(dest->as_float_reg(), src->as_register_lo()); 444 break; 445 case Bytecodes::_l2d: 446 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo()); 447 break; 448 449 case Bytecodes::_f2i: 450 case Bytecodes::_f2l: { 451 Label done; 452 FloatRegister Rsrc = src->as_float_reg(); 453 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo()); 454 __ clear_reg(Rdst, true, false); 455 __ z_cebr(Rsrc, Rsrc); 456 __ z_brno(done); // NaN -> 0 457 if (op->bytecode() == Bytecodes::_f2i) { 458 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero); 459 } else { // op->bytecode() == Bytecodes::_f2l 460 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero); 461 } 462 __ bind(done); 463 } 464 break; 465 466 case Bytecodes::_d2i: 467 case Bytecodes::_d2l: { 468 Label done; 469 FloatRegister Rsrc = src->as_double_reg(); 470 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo()); 471 __ clear_reg(Rdst, true, false); // Don't set CC. 472 __ z_cdbr(Rsrc, Rsrc); 473 __ z_brno(done); // NaN -> 0 474 if (op->bytecode() == Bytecodes::_d2i) { 475 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero); 476 } else { // Bytecodes::_d2l 477 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero); 478 } 479 __ bind(done); 480 } 481 break; 482 483 default: ShouldNotReachHere(); 484 } 485 } 486 487 void LIR_Assembler::align_call(LIR_Code code) { 488 // End of call instruction must be 4 byte aligned. 489 int offset = __ offset(); 490 switch (code) { 491 case lir_icvirtual_call: 492 offset += MacroAssembler::load_const_from_toc_size(); 493 // no break 494 case lir_static_call: 495 case lir_optvirtual_call: 496 case lir_dynamic_call: 497 offset += NativeCall::call_far_pcrelative_displacement_offset; 498 break; 499 default: ShouldNotReachHere(); 500 } 501 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) { 502 __ nop(); 503 } 504 } 505 506 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 507 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0, 508 "must be aligned (offset=%d)", __ offset()); 509 assert(rtype == relocInfo::none || 510 rtype == relocInfo::opt_virtual_call_type || 511 rtype == relocInfo::static_call_type, "unexpected rtype"); 512 // Prepend each BRASL with a nop. 513 __ relocate(rtype); 514 __ z_nop(); 515 __ z_brasl(Z_R14, op->addr()); 516 add_call_info(code_offset(), op->info()); 517 } 518 519 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 520 address virtual_call_oop_addr = NULL; 521 AddressLiteral empty_ic((address) Universe::non_oop_word()); 522 virtual_call_oop_addr = __ pc(); 523 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic); 524 if (!success) { 525 bailout("const section overflow"); 526 return; 527 } 528 529 // CALL to fixup routine. Fixup routine uses ScopeDesc info 530 // to determine who we intended to call. 531 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 532 call(op, relocInfo::none); 533 } 534 535 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 536 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg); 537 } 538 539 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 540 assert(src->is_constant(), "should not call otherwise"); 541 assert(dest->is_stack(), "should not call otherwise"); 542 LIR_Const* c = src->as_constant_ptr(); 543 544 unsigned int lmem = 0; 545 unsigned int lcon = 0; 546 int64_t cbits = 0; 547 Address dest_addr; 548 switch (c->type()) { 549 case T_INT: // fall through 550 case T_FLOAT: 551 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 552 lmem = 4; lcon = 4; cbits = c->as_jint_bits(); 553 break; 554 555 case T_ADDRESS: 556 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 557 lmem = 8; lcon = 4; cbits = c->as_jint_bits(); 558 break; 559 560 case T_OBJECT: 561 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 562 if (c->as_jobject() == NULL) { 563 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8); 564 } else { 565 jobject2reg(c->as_jobject(), Z_R1_scratch); 566 __ reg2mem_opt(Z_R1_scratch, dest_addr, true); 567 } 568 return; 569 570 case T_LONG: // fall through 571 case T_DOUBLE: 572 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 573 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits()); 574 break; 575 576 default: 577 ShouldNotReachHere(); 578 } 579 580 __ store_const(dest_addr, cbits, lmem, lcon); 581 } 582 583 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 584 assert(src->is_constant(), "should not call otherwise"); 585 assert(dest->is_address(), "should not call otherwise"); 586 587 LIR_Const* c = src->as_constant_ptr(); 588 Address addr = as_Address(dest->as_address_ptr()); 589 590 int store_offset = -1; 591 592 if (dest->as_address_ptr()->index()->is_valid()) { 593 switch (type) { 594 case T_INT: // fall through 595 case T_FLOAT: 596 __ load_const_optimized(Z_R0_scratch, c->as_jint_bits()); 597 store_offset = __ offset(); 598 if (Immediate::is_uimm12(addr.disp())) { 599 __ z_st(Z_R0_scratch, addr); 600 } else { 601 __ z_sty(Z_R0_scratch, addr); 602 } 603 break; 604 605 case T_ADDRESS: 606 __ load_const_optimized(Z_R1_scratch, c->as_jint_bits()); 607 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true); 608 break; 609 610 case T_OBJECT: // fall through 611 case T_ARRAY: 612 if (c->as_jobject() == NULL) { 613 if (UseCompressedOops && !wide) { 614 __ clear_reg(Z_R1_scratch, false); 615 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false); 616 } else { 617 __ clear_reg(Z_R1_scratch, true); 618 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true); 619 } 620 } else { 621 jobject2reg(c->as_jobject(), Z_R1_scratch); 622 if (UseCompressedOops && !wide) { 623 __ encode_heap_oop(Z_R1_scratch); 624 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false); 625 } else { 626 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true); 627 } 628 } 629 assert(store_offset >= 0, "check"); 630 break; 631 632 case T_LONG: // fall through 633 case T_DOUBLE: 634 __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits())); 635 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true); 636 break; 637 638 case T_BOOLEAN: // fall through 639 case T_BYTE: 640 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint())); 641 store_offset = __ offset(); 642 if (Immediate::is_uimm12(addr.disp())) { 643 __ z_stc(Z_R0_scratch, addr); 644 } else { 645 __ z_stcy(Z_R0_scratch, addr); 646 } 647 break; 648 649 case T_CHAR: // fall through 650 case T_SHORT: 651 __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint())); 652 store_offset = __ offset(); 653 if (Immediate::is_uimm12(addr.disp())) { 654 __ z_sth(Z_R0_scratch, addr); 655 } else { 656 __ z_sthy(Z_R0_scratch, addr); 657 } 658 break; 659 660 default: 661 ShouldNotReachHere(); 662 } 663 664 } else { // no index 665 666 unsigned int lmem = 0; 667 unsigned int lcon = 0; 668 int64_t cbits = 0; 669 670 switch (type) { 671 case T_INT: // fall through 672 case T_FLOAT: 673 lmem = 4; lcon = 4; cbits = c->as_jint_bits(); 674 break; 675 676 case T_ADDRESS: 677 lmem = 8; lcon = 4; cbits = c->as_jint_bits(); 678 break; 679 680 case T_OBJECT: // fall through 681 case T_ARRAY: 682 if (c->as_jobject() == NULL) { 683 if (UseCompressedOops && !wide) { 684 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4); 685 } else { 686 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8); 687 } 688 } else { 689 jobject2reg(c->as_jobject(), Z_R1_scratch); 690 if (UseCompressedOops && !wide) { 691 __ encode_heap_oop(Z_R1_scratch); 692 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false); 693 } else { 694 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true); 695 } 696 } 697 assert(store_offset >= 0, "check"); 698 break; 699 700 case T_LONG: // fall through 701 case T_DOUBLE: 702 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits()); 703 break; 704 705 case T_BOOLEAN: // fall through 706 case T_BYTE: 707 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint()); 708 break; 709 710 case T_CHAR: // fall through 711 case T_SHORT: 712 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint()); 713 break; 714 715 default: 716 ShouldNotReachHere(); 717 } 718 719 if (store_offset == -1) { 720 store_offset = __ store_const(addr, cbits, lmem, lcon); 721 assert(store_offset >= 0, "check"); 722 } 723 } 724 725 if (info != NULL) { 726 add_debug_info_for_null_check(store_offset, info); 727 } 728 } 729 730 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 731 assert(src->is_constant(), "should not call otherwise"); 732 assert(dest->is_register(), "should not call otherwise"); 733 LIR_Const* c = src->as_constant_ptr(); 734 735 switch (c->type()) { 736 case T_INT: { 737 assert(patch_code == lir_patch_none, "no patching handled here"); 738 __ load_const_optimized(dest->as_register(), c->as_jint()); 739 break; 740 } 741 742 case T_ADDRESS: { 743 assert(patch_code == lir_patch_none, "no patching handled here"); 744 __ load_const_optimized(dest->as_register(), c->as_jint()); 745 break; 746 } 747 748 case T_LONG: { 749 assert(patch_code == lir_patch_none, "no patching handled here"); 750 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong()); 751 break; 752 } 753 754 case T_OBJECT: { 755 if (patch_code != lir_patch_none) { 756 jobject2reg_with_patching(dest->as_register(), info); 757 } else { 758 jobject2reg(c->as_jobject(), dest->as_register()); 759 } 760 break; 761 } 762 763 case T_METADATA: { 764 if (patch_code != lir_patch_none) { 765 klass2reg_with_patching(dest->as_register(), info); 766 } else { 767 metadata2reg(c->as_metadata(), dest->as_register()); 768 } 769 break; 770 } 771 772 case T_FLOAT: { 773 Register toc_reg = Z_R1_scratch; 774 __ load_toc(toc_reg); 775 address const_addr = __ float_constant(c->as_jfloat()); 776 if (const_addr == NULL) { 777 bailout("const section overflow"); 778 break; 779 } 780 int displ = const_addr - _masm->code()->consts()->start(); 781 if (dest->is_single_fpu()) { 782 __ z_ley(dest->as_float_reg(), displ, toc_reg); 783 } else { 784 assert(dest->is_single_cpu(), "Must be a cpu register."); 785 __ z_ly(dest->as_register(), displ, toc_reg); 786 } 787 } 788 break; 789 790 case T_DOUBLE: { 791 Register toc_reg = Z_R1_scratch; 792 __ load_toc(toc_reg); 793 address const_addr = __ double_constant(c->as_jdouble()); 794 if (const_addr == NULL) { 795 bailout("const section overflow"); 796 break; 797 } 798 int displ = const_addr - _masm->code()->consts()->start(); 799 if (dest->is_double_fpu()) { 800 __ z_ldy(dest->as_double_reg(), displ, toc_reg); 801 } else { 802 assert(dest->is_double_cpu(), "Must be a long register."); 803 __ z_lg(dest->as_register_lo(), displ, toc_reg); 804 } 805 } 806 break; 807 808 default: 809 ShouldNotReachHere(); 810 } 811 } 812 813 Address LIR_Assembler::as_Address(LIR_Address* addr) { 814 if (addr->base()->is_illegal()) { 815 Unimplemented(); 816 } 817 818 Register base = addr->base()->as_pointer_register(); 819 820 if (addr->index()->is_illegal()) { 821 return Address(base, addr->disp()); 822 } else if (addr->index()->is_cpu_register()) { 823 Register index = addr->index()->as_pointer_register(); 824 return Address(base, index, addr->disp()); 825 } else if (addr->index()->is_constant()) { 826 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp(); 827 return Address(base, addr_offset); 828 } else { 829 ShouldNotReachHere(); 830 return Address(); 831 } 832 } 833 834 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 835 switch (type) { 836 case T_INT: 837 case T_FLOAT: { 838 Register tmp = Z_R1_scratch; 839 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 840 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 841 __ mem2reg_opt(tmp, from, false); 842 __ reg2mem_opt(tmp, to, false); 843 break; 844 } 845 case T_ADDRESS: 846 case T_OBJECT: { 847 Register tmp = Z_R1_scratch; 848 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 849 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 850 __ mem2reg_opt(tmp, from, true); 851 __ reg2mem_opt(tmp, to, true); 852 break; 853 } 854 case T_LONG: 855 case T_DOUBLE: { 856 Register tmp = Z_R1_scratch; 857 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 858 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 859 __ mem2reg_opt(tmp, from, true); 860 __ reg2mem_opt(tmp, to, true); 861 break; 862 } 863 864 default: 865 ShouldNotReachHere(); 866 } 867 } 868 869 // 4-byte accesses only! Don't use it to access 8 bytes! 870 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 871 ShouldNotCallThis(); 872 return 0; // unused 873 } 874 875 // 4-byte accesses only! Don't use it to access 8 bytes! 876 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 877 ShouldNotCallThis(); 878 return 0; // unused 879 } 880 881 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, 882 CodeEmitInfo* info, bool wide) { 883 884 assert(type != T_METADATA, "load of metadata ptr not supported"); 885 LIR_Address* addr = src_opr->as_address_ptr(); 886 LIR_Opr to_reg = dest; 887 888 Register src = addr->base()->as_pointer_register(); 889 Register disp_reg = Z_R0; 890 int disp_value = addr->disp(); 891 bool needs_patching = (patch_code != lir_patch_none); 892 893 if (addr->base()->type() == T_OBJECT) { 894 __ verify_oop(src, FILE_AND_LINE); 895 } 896 897 PatchingStub* patch = NULL; 898 if (needs_patching) { 899 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 900 assert(!to_reg->is_double_cpu() || 901 patch_code == lir_patch_none || 902 patch_code == lir_patch_normal, "patching doesn't match register"); 903 } 904 905 if (addr->index()->is_illegal()) { 906 if (!Immediate::is_simm20(disp_value)) { 907 if (needs_patching) { 908 __ load_const(Z_R1_scratch, (intptr_t)0); 909 } else { 910 __ load_const_optimized(Z_R1_scratch, disp_value); 911 } 912 disp_reg = Z_R1_scratch; 913 disp_value = 0; 914 } 915 } else { 916 if (!Immediate::is_simm20(disp_value)) { 917 __ load_const_optimized(Z_R1_scratch, disp_value); 918 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register()); 919 disp_reg = Z_R1_scratch; 920 disp_value = 0; 921 } 922 disp_reg = addr->index()->as_pointer_register(); 923 } 924 925 // Remember the offset of the load. The patching_epilog must be done 926 // before the call to add_debug_info, otherwise the PcDescs don't get 927 // entered in increasing order. 928 int offset = code_offset(); 929 930 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up"); 931 932 bool short_disp = Immediate::is_uimm12(disp_value); 933 934 switch (type) { 935 case T_BOOLEAN: // fall through 936 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break; 937 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break; 938 case T_SHORT : 939 if (short_disp) { 940 __ z_lh(dest->as_register(), disp_value, disp_reg, src); 941 } else { 942 __ z_lhy(dest->as_register(), disp_value, disp_reg, src); 943 } 944 break; 945 case T_INT : 946 if (short_disp) { 947 __ z_l(dest->as_register(), disp_value, disp_reg, src); 948 } else { 949 __ z_ly(dest->as_register(), disp_value, disp_reg, src); 950 } 951 break; 952 case T_ADDRESS: 953 __ z_lg(dest->as_register(), disp_value, disp_reg, src); 954 break; 955 case T_ARRAY : // fall through 956 case T_OBJECT: 957 { 958 if (UseCompressedOops && !wide) { 959 __ z_llgf(dest->as_register(), disp_value, disp_reg, src); 960 __ oop_decoder(dest->as_register(), dest->as_register(), true); 961 } else { 962 __ z_lg(dest->as_register(), disp_value, disp_reg, src); 963 } 964 __ verify_oop(dest->as_register(), FILE_AND_LINE); 965 break; 966 } 967 case T_FLOAT: 968 if (short_disp) { 969 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src); 970 } else { 971 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src); 972 } 973 break; 974 case T_DOUBLE: 975 if (short_disp) { 976 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src); 977 } else { 978 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src); 979 } 980 break; 981 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break; 982 default : ShouldNotReachHere(); 983 } 984 985 if (patch != NULL) { 986 patching_epilog(patch, patch_code, src, info); 987 } 988 if (info != NULL) add_debug_info_for_null_check(offset, info); 989 } 990 991 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 992 assert(src->is_stack(), "should not call otherwise"); 993 assert(dest->is_register(), "should not call otherwise"); 994 995 if (dest->is_single_cpu()) { 996 if (is_reference_type(type)) { 997 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true); 998 __ verify_oop(dest->as_register(), FILE_AND_LINE); 999 } else if (type == T_METADATA || type == T_ADDRESS) { 1000 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true); 1001 } else { 1002 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false); 1003 } 1004 } else if (dest->is_double_cpu()) { 1005 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix()); 1006 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true); 1007 } else if (dest->is_single_fpu()) { 1008 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1009 __ mem2freg_opt(dest->as_float_reg(), src_addr, false); 1010 } else if (dest->is_double_fpu()) { 1011 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1012 __ mem2freg_opt(dest->as_double_reg(), src_addr, true); 1013 } else { 1014 ShouldNotReachHere(); 1015 } 1016 } 1017 1018 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1019 assert(src->is_register(), "should not call otherwise"); 1020 assert(dest->is_stack(), "should not call otherwise"); 1021 1022 if (src->is_single_cpu()) { 1023 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 1024 if (is_reference_type(type)) { 1025 __ verify_oop(src->as_register(), FILE_AND_LINE); 1026 __ reg2mem_opt(src->as_register(), dst, true); 1027 } else if (type == T_METADATA || type == T_ADDRESS) { 1028 __ reg2mem_opt(src->as_register(), dst, true); 1029 } else { 1030 __ reg2mem_opt(src->as_register(), dst, false); 1031 } 1032 } else if (src->is_double_cpu()) { 1033 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix()); 1034 __ reg2mem_opt(src->as_register_lo(), dstLO, true); 1035 } else if (src->is_single_fpu()) { 1036 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1037 __ freg2mem_opt(src->as_float_reg(), dst_addr, false); 1038 } else if (src->is_double_fpu()) { 1039 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1040 __ freg2mem_opt(src->as_double_reg(), dst_addr, true); 1041 } else { 1042 ShouldNotReachHere(); 1043 } 1044 } 1045 1046 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1047 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1048 if (from_reg->is_double_fpu()) { 1049 // double to double moves 1050 assert(to_reg->is_double_fpu(), "should match"); 1051 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg()); 1052 } else { 1053 // float to float moves 1054 assert(to_reg->is_single_fpu(), "should match"); 1055 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg()); 1056 } 1057 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1058 if (from_reg->is_double_cpu()) { 1059 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register()); 1060 } else if (to_reg->is_double_cpu()) { 1061 // int to int moves 1062 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register()); 1063 } else { 1064 // int to int moves 1065 __ z_lgr(to_reg->as_register(), from_reg->as_register()); 1066 } 1067 } else { 1068 ShouldNotReachHere(); 1069 } 1070 if (is_reference_type(to_reg->type())) { 1071 __ verify_oop(to_reg->as_register(), FILE_AND_LINE); 1072 } 1073 } 1074 1075 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type, 1076 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1077 bool wide) { 1078 assert(type != T_METADATA, "store of metadata ptr not supported"); 1079 LIR_Address* addr = dest_opr->as_address_ptr(); 1080 1081 Register dest = addr->base()->as_pointer_register(); 1082 Register disp_reg = Z_R0; 1083 int disp_value = addr->disp(); 1084 bool needs_patching = (patch_code != lir_patch_none); 1085 1086 if (addr->base()->is_oop_register()) { 1087 __ verify_oop(dest, FILE_AND_LINE); 1088 } 1089 1090 PatchingStub* patch = NULL; 1091 if (needs_patching) { 1092 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1093 assert(!from->is_double_cpu() || 1094 patch_code == lir_patch_none || 1095 patch_code == lir_patch_normal, "patching doesn't match register"); 1096 } 1097 1098 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption"); 1099 if (addr->index()->is_illegal()) { 1100 if (!Immediate::is_simm20(disp_value)) { 1101 if (needs_patching) { 1102 __ load_const(Z_R1_scratch, (intptr_t)0); 1103 } else { 1104 __ load_const_optimized(Z_R1_scratch, disp_value); 1105 } 1106 disp_reg = Z_R1_scratch; 1107 disp_value = 0; 1108 } 1109 } else { 1110 if (!Immediate::is_simm20(disp_value)) { 1111 __ load_const_optimized(Z_R1_scratch, disp_value); 1112 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register()); 1113 disp_reg = Z_R1_scratch; 1114 disp_value = 0; 1115 } 1116 disp_reg = addr->index()->as_pointer_register(); 1117 } 1118 1119 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up"); 1120 1121 if (is_reference_type(type)) { 1122 __ verify_oop(from->as_register(), FILE_AND_LINE); 1123 } 1124 1125 bool short_disp = Immediate::is_uimm12(disp_value); 1126 1127 // Remember the offset of the store. The patching_epilog must be done 1128 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1129 // entered in increasing order. 1130 int offset = code_offset(); 1131 switch (type) { 1132 case T_BOOLEAN: // fall through 1133 case T_BYTE : 1134 if (short_disp) { 1135 __ z_stc(from->as_register(), disp_value, disp_reg, dest); 1136 } else { 1137 __ z_stcy(from->as_register(), disp_value, disp_reg, dest); 1138 } 1139 break; 1140 case T_CHAR : // fall through 1141 case T_SHORT : 1142 if (short_disp) { 1143 __ z_sth(from->as_register(), disp_value, disp_reg, dest); 1144 } else { 1145 __ z_sthy(from->as_register(), disp_value, disp_reg, dest); 1146 } 1147 break; 1148 case T_INT : 1149 if (short_disp) { 1150 __ z_st(from->as_register(), disp_value, disp_reg, dest); 1151 } else { 1152 __ z_sty(from->as_register(), disp_value, disp_reg, dest); 1153 } 1154 break; 1155 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break; 1156 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break; 1157 break; 1158 case T_ARRAY : // fall through 1159 case T_OBJECT: 1160 { 1161 if (UseCompressedOops && !wide) { 1162 Register compressed_src = Z_R14; 1163 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true); 1164 offset = code_offset(); 1165 if (short_disp) { 1166 __ z_st(compressed_src, disp_value, disp_reg, dest); 1167 } else { 1168 __ z_sty(compressed_src, disp_value, disp_reg, dest); 1169 } 1170 } else { 1171 __ z_stg(from->as_register(), disp_value, disp_reg, dest); 1172 } 1173 break; 1174 } 1175 case T_FLOAT : 1176 if (short_disp) { 1177 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest); 1178 } else { 1179 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest); 1180 } 1181 break; 1182 case T_DOUBLE: 1183 if (short_disp) { 1184 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest); 1185 } else { 1186 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest); 1187 } 1188 break; 1189 default: ShouldNotReachHere(); 1190 } 1191 1192 if (patch != NULL) { 1193 patching_epilog(patch, patch_code, dest, info); 1194 } 1195 1196 if (info != NULL) add_debug_info_for_null_check(offset, info); 1197 } 1198 1199 1200 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) { 1201 assert(result->is_illegal() || 1202 (result->is_single_cpu() && result->as_register() == Z_R2) || 1203 (result->is_double_cpu() && result->as_register_lo() == Z_R2) || 1204 (result->is_single_fpu() && result->as_float_reg() == Z_F0) || 1205 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention"); 1206 1207 __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset())); 1208 1209 // Pop the frame before the safepoint code. 1210 __ pop_frame_restore_retPC(initial_frame_size_in_bytes()); 1211 1212 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1213 __ reserved_stack_check(Z_R14); 1214 } 1215 1216 // We need to mark the code position where the load from the safepoint 1217 // polling page was emitted as relocInfo::poll_return_type here. 1218 __ relocate(relocInfo::poll_return_type); 1219 __ load_from_polling_page(Z_R1_scratch); 1220 1221 __ z_br(Z_R14); // Return to caller. 1222 } 1223 1224 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1225 const Register poll_addr = tmp->as_register_lo(); 1226 __ z_lg(poll_addr, Address(Z_thread, JavaThread::polling_page_offset())); 1227 guarantee(info != NULL, "Shouldn't be NULL"); 1228 add_debug_info_for_branch(info); 1229 int offset = __ offset(); 1230 __ relocate(relocInfo::poll_type); 1231 __ load_from_polling_page(poll_addr); 1232 return offset; 1233 } 1234 1235 void LIR_Assembler::emit_static_call_stub() { 1236 1237 // Stub is fixed up when the corresponding call is converted from calling 1238 // compiled code to calling interpreted code. 1239 1240 address call_pc = __ pc(); 1241 address stub = __ start_a_stub(call_stub_size()); 1242 if (stub == NULL) { 1243 bailout("static call stub overflow"); 1244 return; 1245 } 1246 1247 int start = __ offset(); 1248 1249 __ relocate(static_stub_Relocation::spec(call_pc)); 1250 1251 // See also Matcher::interpreter_method_reg(). 1252 AddressLiteral meta = __ allocate_metadata_address(NULL); 1253 bool success = __ load_const_from_toc(Z_method, meta); 1254 1255 __ set_inst_mark(); 1256 AddressLiteral a((address)-1); 1257 success = success && __ load_const_from_toc(Z_R1, a); 1258 if (!success) { 1259 bailout("const section overflow"); 1260 return; 1261 } 1262 1263 __ z_br(Z_R1); 1264 assert(__ offset() - start <= call_stub_size(), "stub too big"); 1265 __ end_a_stub(); // Update current stubs pointer and restore insts_end. 1266 } 1267 1268 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1269 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual; 1270 if (opr1->is_single_cpu()) { 1271 Register reg1 = opr1->as_register(); 1272 if (opr2->is_single_cpu()) { 1273 // cpu register - cpu register 1274 if (is_reference_type(opr1->type())) { 1275 __ z_clgr(reg1, opr2->as_register()); 1276 } else { 1277 assert(!is_reference_type(opr2->type()), "cmp int, oop?"); 1278 if (unsigned_comp) { 1279 __ z_clr(reg1, opr2->as_register()); 1280 } else { 1281 __ z_cr(reg1, opr2->as_register()); 1282 } 1283 } 1284 } else if (opr2->is_stack()) { 1285 // cpu register - stack 1286 if (is_reference_type(opr1->type())) { 1287 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 1288 } else { 1289 if (unsigned_comp) { 1290 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 1291 } else { 1292 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 1293 } 1294 } 1295 } else if (opr2->is_constant()) { 1296 // cpu register - constant 1297 LIR_Const* c = opr2->as_constant_ptr(); 1298 if (c->type() == T_INT) { 1299 if (unsigned_comp) { 1300 __ z_clfi(reg1, c->as_jint()); 1301 } else { 1302 __ z_cfi(reg1, c->as_jint()); 1303 } 1304 } else if (c->type() == T_METADATA) { 1305 // We only need, for now, comparison with NULL for metadata. 1306 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops"); 1307 Metadata* m = c->as_metadata(); 1308 if (m == NULL) { 1309 __ z_cghi(reg1, 0); 1310 } else { 1311 ShouldNotReachHere(); 1312 } 1313 } else if (is_reference_type(c->type())) { 1314 // In 64bit oops are single register. 1315 jobject o = c->as_jobject(); 1316 if (o == NULL) { 1317 __ z_ltgr(reg1, reg1); 1318 } else { 1319 jobject2reg(o, Z_R1_scratch); 1320 __ z_cgr(reg1, Z_R1_scratch); 1321 } 1322 } else { 1323 fatal("unexpected type: %s", basictype_to_str(c->type())); 1324 } 1325 // cpu register - address 1326 } else if (opr2->is_address()) { 1327 if (op->info() != NULL) { 1328 add_debug_info_for_null_check_here(op->info()); 1329 } 1330 if (unsigned_comp) { 1331 __ z_cly(reg1, as_Address(opr2->as_address_ptr())); 1332 } else { 1333 __ z_cy(reg1, as_Address(opr2->as_address_ptr())); 1334 } 1335 } else { 1336 ShouldNotReachHere(); 1337 } 1338 1339 } else if (opr1->is_double_cpu()) { 1340 assert(!unsigned_comp, "unexpected"); 1341 Register xlo = opr1->as_register_lo(); 1342 Register xhi = opr1->as_register_hi(); 1343 if (opr2->is_double_cpu()) { 1344 __ z_cgr(xlo, opr2->as_register_lo()); 1345 } else if (opr2->is_constant()) { 1346 // cpu register - constant 0 1347 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 1348 __ z_ltgr(xlo, xlo); 1349 } else { 1350 ShouldNotReachHere(); 1351 } 1352 1353 } else if (opr1->is_single_fpu()) { 1354 if (opr2->is_single_fpu()) { 1355 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg()); 1356 } else { 1357 // stack slot 1358 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix()); 1359 if (Immediate::is_uimm12(addr.disp())) { 1360 __ z_ceb(opr1->as_float_reg(), addr); 1361 } else { 1362 __ z_ley(Z_fscratch_1, addr); 1363 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1); 1364 } 1365 } 1366 } else if (opr1->is_double_fpu()) { 1367 if (opr2->is_double_fpu()) { 1368 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg()); 1369 } else { 1370 // stack slot 1371 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix()); 1372 if (Immediate::is_uimm12(addr.disp())) { 1373 __ z_cdb(opr1->as_double_reg(), addr); 1374 } else { 1375 __ z_ldy(Z_fscratch_1, addr); 1376 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1); 1377 } 1378 } 1379 } else { 1380 ShouldNotReachHere(); 1381 } 1382 } 1383 1384 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 1385 Label done; 1386 Register dreg = dst->as_register(); 1387 1388 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1389 assert((left->is_single_fpu() && right->is_single_fpu()) || 1390 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types"); 1391 bool is_single = left->is_single_fpu(); 1392 bool is_unordered_less = (code == lir_ucmp_fd2i); 1393 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg(); 1394 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg(); 1395 if (is_single) { 1396 __ z_cebr(lreg, rreg); 1397 } else { 1398 __ z_cdbr(lreg, rreg); 1399 } 1400 if (VM_Version::has_LoadStoreConditional()) { 1401 Register one = Z_R0_scratch; 1402 Register minus_one = Z_R1_scratch; 1403 __ z_lghi(minus_one, -1); 1404 __ z_lghi(one, 1); 1405 __ z_lghi(dreg, 0); 1406 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered); 1407 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow); 1408 } else { 1409 __ clear_reg(dreg, true, false); 1410 __ z_bre(done); // if (left == right) dst = 0 1411 1412 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1 1413 __ z_lhi(dreg, 1); 1414 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done); 1415 1416 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1 1417 __ z_lhi(dreg, -1); 1418 } 1419 } else { 1420 assert(code == lir_cmp_l2i, "check"); 1421 if (VM_Version::has_LoadStoreConditional()) { 1422 Register one = Z_R0_scratch; 1423 Register minus_one = Z_R1_scratch; 1424 __ z_cgr(left->as_register_lo(), right->as_register_lo()); 1425 __ z_lghi(minus_one, -1); 1426 __ z_lghi(one, 1); 1427 __ z_lghi(dreg, 0); 1428 __ z_locgr(dreg, one, Assembler::bcondHigh); 1429 __ z_locgr(dreg, minus_one, Assembler::bcondLow); 1430 } else { 1431 __ z_cgr(left->as_register_lo(), right->as_register_lo()); 1432 __ z_lghi(dreg, 0); // eq value 1433 __ z_bre(done); 1434 __ z_lghi(dreg, 1); // gt value 1435 __ z_brh(done); 1436 __ z_lghi(dreg, -1); // lt value 1437 } 1438 } 1439 __ bind(done); 1440 } 1441 1442 // result = condition ? opr1 : opr2 1443 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type, 1444 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) { 1445 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390"); 1446 1447 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual; 1448 switch (condition) { 1449 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break; 1450 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break; 1451 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break; 1452 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break; 1453 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break; 1454 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break; 1455 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break; 1456 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break; 1457 default: ShouldNotReachHere(); 1458 } 1459 1460 if (opr1->is_cpu_register()) { 1461 reg2reg(opr1, result); 1462 } else if (opr1->is_stack()) { 1463 stack2reg(opr1, result, result->type()); 1464 } else if (opr1->is_constant()) { 1465 const2reg(opr1, result, lir_patch_none, NULL); 1466 } else { 1467 ShouldNotReachHere(); 1468 } 1469 1470 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) { 1471 // Optimized version that does not require a branch. 1472 if (opr2->is_single_cpu()) { 1473 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1474 __ z_locgr(result->as_register(), opr2->as_register(), ncond); 1475 } else if (opr2->is_double_cpu()) { 1476 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1477 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1478 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond); 1479 } else if (opr2->is_single_stack()) { 1480 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond); 1481 } else if (opr2->is_double_stack()) { 1482 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond); 1483 } else { 1484 ShouldNotReachHere(); 1485 } 1486 } else { 1487 Label skip; 1488 __ z_brc(acond, skip); 1489 if (opr2->is_cpu_register()) { 1490 reg2reg(opr2, result); 1491 } else if (opr2->is_stack()) { 1492 stack2reg(opr2, result, result->type()); 1493 } else if (opr2->is_constant()) { 1494 const2reg(opr2, result, lir_patch_none, NULL); 1495 } else { 1496 ShouldNotReachHere(); 1497 } 1498 __ bind(skip); 1499 } 1500 } 1501 1502 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, 1503 CodeEmitInfo* info, bool pop_fpu_stack) { 1504 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1505 1506 if (left->is_single_cpu()) { 1507 assert(left == dest, "left and dest must be equal"); 1508 Register lreg = left->as_register(); 1509 1510 if (right->is_single_cpu()) { 1511 // cpu register - cpu register 1512 Register rreg = right->as_register(); 1513 switch (code) { 1514 case lir_add: __ z_ar (lreg, rreg); break; 1515 case lir_sub: __ z_sr (lreg, rreg); break; 1516 case lir_mul: __ z_msr(lreg, rreg); break; 1517 default: ShouldNotReachHere(); 1518 } 1519 1520 } else if (right->is_stack()) { 1521 // cpu register - stack 1522 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1523 switch (code) { 1524 case lir_add: __ z_ay(lreg, raddr); break; 1525 case lir_sub: __ z_sy(lreg, raddr); break; 1526 default: ShouldNotReachHere(); 1527 } 1528 1529 } else if (right->is_constant()) { 1530 // cpu register - constant 1531 jint c = right->as_constant_ptr()->as_jint(); 1532 switch (code) { 1533 case lir_add: __ z_agfi(lreg, c); break; 1534 case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint 1535 case lir_mul: __ z_msfi(lreg, c); break; 1536 default: ShouldNotReachHere(); 1537 } 1538 1539 } else { 1540 ShouldNotReachHere(); 1541 } 1542 1543 } else if (left->is_double_cpu()) { 1544 assert(left == dest, "left and dest must be equal"); 1545 Register lreg_lo = left->as_register_lo(); 1546 Register lreg_hi = left->as_register_hi(); 1547 1548 if (right->is_double_cpu()) { 1549 // cpu register - cpu register 1550 Register rreg_lo = right->as_register_lo(); 1551 Register rreg_hi = right->as_register_hi(); 1552 assert_different_registers(lreg_lo, rreg_lo); 1553 switch (code) { 1554 case lir_add: 1555 __ z_agr(lreg_lo, rreg_lo); 1556 break; 1557 case lir_sub: 1558 __ z_sgr(lreg_lo, rreg_lo); 1559 break; 1560 case lir_mul: 1561 __ z_msgr(lreg_lo, rreg_lo); 1562 break; 1563 default: 1564 ShouldNotReachHere(); 1565 } 1566 1567 } else if (right->is_constant()) { 1568 // cpu register - constant 1569 jlong c = right->as_constant_ptr()->as_jlong_bits(); 1570 switch (code) { 1571 case lir_add: __ z_agfi(lreg_lo, c); break; 1572 case lir_sub: 1573 if (c != min_jint) { 1574 __ z_agfi(lreg_lo, -c); 1575 } else { 1576 // -min_jint cannot be represented as simm32 in z_agfi 1577 // min_jint sign extended: 0xffffffff80000000 1578 // -min_jint as 64 bit integer: 0x0000000080000000 1579 // 0x80000000 can be represented as uimm32 in z_algfi 1580 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000 1581 __ z_algfi(lreg_lo, UCONST64(0x80000000)); 1582 } 1583 break; 1584 case lir_mul: __ z_msgfi(lreg_lo, c); break; 1585 default: 1586 ShouldNotReachHere(); 1587 } 1588 1589 } else { 1590 ShouldNotReachHere(); 1591 } 1592 1593 } else if (left->is_single_fpu()) { 1594 assert(left == dest, "left and dest must be equal"); 1595 FloatRegister lreg = left->as_float_reg(); 1596 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg; 1597 Address raddr; 1598 1599 if (rreg == fnoreg) { 1600 assert(right->is_single_stack(), "constants should be loaded into register"); 1601 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1602 if (!Immediate::is_uimm12(raddr.disp())) { 1603 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false); 1604 } 1605 } 1606 1607 if (rreg != fnoreg) { 1608 switch (code) { 1609 case lir_add: __ z_aebr(lreg, rreg); break; 1610 case lir_sub: __ z_sebr(lreg, rreg); break; 1611 case lir_mul: __ z_meebr(lreg, rreg); break; 1612 case lir_div: __ z_debr(lreg, rreg); break; 1613 default: ShouldNotReachHere(); 1614 } 1615 } else { 1616 switch (code) { 1617 case lir_add: __ z_aeb(lreg, raddr); break; 1618 case lir_sub: __ z_seb(lreg, raddr); break; 1619 case lir_mul: __ z_meeb(lreg, raddr); break; 1620 case lir_div: __ z_deb(lreg, raddr); break; 1621 default: ShouldNotReachHere(); 1622 } 1623 } 1624 } else if (left->is_double_fpu()) { 1625 assert(left == dest, "left and dest must be equal"); 1626 FloatRegister lreg = left->as_double_reg(); 1627 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg; 1628 Address raddr; 1629 1630 if (rreg == fnoreg) { 1631 assert(right->is_double_stack(), "constants should be loaded into register"); 1632 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 1633 if (!Immediate::is_uimm12(raddr.disp())) { 1634 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true); 1635 } 1636 } 1637 1638 if (rreg != fnoreg) { 1639 switch (code) { 1640 case lir_add: __ z_adbr(lreg, rreg); break; 1641 case lir_sub: __ z_sdbr(lreg, rreg); break; 1642 case lir_mul: __ z_mdbr(lreg, rreg); break; 1643 case lir_div: __ z_ddbr(lreg, rreg); break; 1644 default: ShouldNotReachHere(); 1645 } 1646 } else { 1647 switch (code) { 1648 case lir_add: __ z_adb(lreg, raddr); break; 1649 case lir_sub: __ z_sdb(lreg, raddr); break; 1650 case lir_mul: __ z_mdb(lreg, raddr); break; 1651 case lir_div: __ z_ddb(lreg, raddr); break; 1652 default: ShouldNotReachHere(); 1653 } 1654 } 1655 } else if (left->is_address()) { 1656 assert(left == dest, "left and dest must be equal"); 1657 assert(code == lir_add, "unsupported operation"); 1658 assert(right->is_constant(), "unsupported operand"); 1659 jint c = right->as_constant_ptr()->as_jint(); 1660 LIR_Address* lir_addr = left->as_address_ptr(); 1661 Address addr = as_Address(lir_addr); 1662 switch (lir_addr->type()) { 1663 case T_INT: 1664 __ add2mem_32(addr, c, Z_R1_scratch); 1665 break; 1666 case T_LONG: 1667 __ add2mem_64(addr, c, Z_R1_scratch); 1668 break; 1669 default: 1670 ShouldNotReachHere(); 1671 } 1672 } else { 1673 ShouldNotReachHere(); 1674 } 1675 } 1676 1677 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1678 switch (code) { 1679 case lir_sqrt: { 1680 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1681 FloatRegister src_reg = value->as_double_reg(); 1682 FloatRegister dst_reg = dest->as_double_reg(); 1683 __ z_sqdbr(dst_reg, src_reg); 1684 break; 1685 } 1686 case lir_abs: { 1687 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 1688 FloatRegister src_reg = value->as_double_reg(); 1689 FloatRegister dst_reg = dest->as_double_reg(); 1690 __ z_lpdbr(dst_reg, src_reg); 1691 break; 1692 } 1693 default: { 1694 ShouldNotReachHere(); 1695 break; 1696 } 1697 } 1698 } 1699 1700 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 1701 if (left->is_single_cpu()) { 1702 Register reg = left->as_register(); 1703 if (right->is_constant()) { 1704 int val = right->as_constant_ptr()->as_jint(); 1705 switch (code) { 1706 case lir_logic_and: __ z_nilf(reg, val); break; 1707 case lir_logic_or: __ z_oilf(reg, val); break; 1708 case lir_logic_xor: __ z_xilf(reg, val); break; 1709 default: ShouldNotReachHere(); 1710 } 1711 } else if (right->is_stack()) { 1712 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1713 switch (code) { 1714 case lir_logic_and: __ z_ny(reg, raddr); break; 1715 case lir_logic_or: __ z_oy(reg, raddr); break; 1716 case lir_logic_xor: __ z_xy(reg, raddr); break; 1717 default: ShouldNotReachHere(); 1718 } 1719 } else { 1720 Register rright = right->as_register(); 1721 switch (code) { 1722 case lir_logic_and: __ z_nr(reg, rright); break; 1723 case lir_logic_or : __ z_or(reg, rright); break; 1724 case lir_logic_xor: __ z_xr(reg, rright); break; 1725 default: ShouldNotReachHere(); 1726 } 1727 } 1728 move_regs(reg, dst->as_register()); 1729 } else { 1730 Register l_lo = left->as_register_lo(); 1731 if (right->is_constant()) { 1732 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong()); 1733 switch (code) { 1734 case lir_logic_and: 1735 __ z_ngr(l_lo, Z_R1_scratch); 1736 break; 1737 case lir_logic_or: 1738 __ z_ogr(l_lo, Z_R1_scratch); 1739 break; 1740 case lir_logic_xor: 1741 __ z_xgr(l_lo, Z_R1_scratch); 1742 break; 1743 default: ShouldNotReachHere(); 1744 } 1745 } else { 1746 Register r_lo; 1747 if (is_reference_type(right->type())) { 1748 r_lo = right->as_register(); 1749 } else { 1750 r_lo = right->as_register_lo(); 1751 } 1752 switch (code) { 1753 case lir_logic_and: 1754 __ z_ngr(l_lo, r_lo); 1755 break; 1756 case lir_logic_or: 1757 __ z_ogr(l_lo, r_lo); 1758 break; 1759 case lir_logic_xor: 1760 __ z_xgr(l_lo, r_lo); 1761 break; 1762 default: ShouldNotReachHere(); 1763 } 1764 } 1765 1766 Register dst_lo = dst->as_register_lo(); 1767 1768 move_regs(l_lo, dst_lo); 1769 } 1770 } 1771 1772 // See operand selection in LIRGenerator::do_ArithmeticOp_Int(). 1773 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 1774 if (left->is_double_cpu()) { 1775 // 64 bit integer case 1776 assert(left->is_double_cpu(), "left must be register"); 1777 assert(right->is_double_cpu() || is_power_of_2(right->as_jlong()), 1778 "right must be register or power of 2 constant"); 1779 assert(result->is_double_cpu(), "result must be register"); 1780 1781 Register lreg = left->as_register_lo(); 1782 Register dreg = result->as_register_lo(); 1783 1784 if (right->is_constant()) { 1785 // Convert division by a power of two into some shifts and logical operations. 1786 Register treg1 = Z_R0_scratch; 1787 Register treg2 = Z_R1_scratch; 1788 jlong divisor = right->as_jlong(); 1789 jlong log_divisor = log2i_exact(right->as_jlong()); 1790 1791 if (divisor == min_jlong) { 1792 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1. 1793 if (dreg == lreg) { 1794 NearLabel done; 1795 __ load_const_optimized(treg2, min_jlong); 1796 __ z_cgr(lreg, treg2); 1797 __ z_lghi(dreg, 0); // Preserves condition code. 1798 __ z_brne(done); 1799 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1 1800 __ bind(done); 1801 } else { 1802 assert_different_registers(dreg, lreg); 1803 NearLabel done; 1804 __ z_lghi(dreg, 0); 1805 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done); 1806 __ z_lghi(dreg, 1); 1807 __ bind(done); 1808 } 1809 return; 1810 } 1811 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG); 1812 if (divisor == 2) { 1813 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0 1814 } else { 1815 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0 1816 __ and_imm(treg2, divisor - 1, treg1, true); 1817 } 1818 if (code == lir_idiv) { 1819 __ z_agr(dreg, treg2); 1820 __ z_srag(dreg, dreg, log_divisor); 1821 } else { 1822 assert(code == lir_irem, "check"); 1823 __ z_agr(treg2, dreg); 1824 __ and_imm(treg2, ~(divisor - 1), treg1, true); 1825 __ z_sgr(dreg, treg2); 1826 } 1827 return; 1828 } 1829 1830 // Divisor is not a power of 2 constant. 1831 Register rreg = right->as_register_lo(); 1832 Register treg = temp->as_register_lo(); 1833 assert(right->is_double_cpu(), "right must be register"); 1834 assert(lreg == Z_R11, "see ldivInOpr()"); 1835 assert(rreg != lreg, "right register must not be same as left register"); 1836 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) || 1837 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()"); 1838 1839 Register R1 = lreg->predecessor(); 1840 Register R2 = rreg; 1841 assert(code != lir_idiv || lreg==dreg, "see code below"); 1842 if (code == lir_idiv) { 1843 __ z_lcgr(lreg, lreg); 1844 } else { 1845 __ clear_reg(dreg, true, false); 1846 } 1847 NearLabel done; 1848 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done); 1849 if (code == lir_idiv) { 1850 __ z_lcgr(lreg, lreg); // Revert lcgr above. 1851 } 1852 if (ImplicitDiv0Checks) { 1853 // No debug info because the idiv won't trap. 1854 // Add_debug_info_for_div0 would instantiate another DivByZeroStub, 1855 // which is unnecessary, too. 1856 add_debug_info_for_div0(__ offset(), info); 1857 } 1858 __ z_dsgr(R1, R2); 1859 __ bind(done); 1860 return; 1861 } 1862 1863 // 32 bit integer case 1864 1865 assert(left->is_single_cpu(), "left must be register"); 1866 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant"); 1867 assert(result->is_single_cpu(), "result must be register"); 1868 1869 Register lreg = left->as_register(); 1870 Register dreg = result->as_register(); 1871 1872 if (right->is_constant()) { 1873 // Convert division by a power of two into some shifts and logical operations. 1874 Register treg1 = Z_R0_scratch; 1875 Register treg2 = Z_R1_scratch; 1876 jlong divisor = right->as_jint(); 1877 jlong log_divisor = log2i_exact(right->as_jint()); 1878 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend 1879 if (divisor == 2) { 1880 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0 1881 } else { 1882 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0 1883 __ and_imm(treg2, divisor - 1, treg1, true); 1884 } 1885 if (code == lir_idiv) { 1886 __ z_agr(dreg, treg2); 1887 __ z_srag(dreg, dreg, log_divisor); 1888 } else { 1889 assert(code == lir_irem, "check"); 1890 __ z_agr(treg2, dreg); 1891 __ and_imm(treg2, ~(divisor - 1), treg1, true); 1892 __ z_sgr(dreg, treg2); 1893 } 1894 return; 1895 } 1896 1897 // Divisor is not a power of 2 constant. 1898 Register rreg = right->as_register(); 1899 Register treg = temp->as_register(); 1900 assert(right->is_single_cpu(), "right must be register"); 1901 assert(lreg == Z_R11, "left register must be rax,"); 1902 assert(rreg != lreg, "right register must not be same as left register"); 1903 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) 1904 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()"); 1905 1906 Register R1 = lreg->predecessor(); 1907 Register R2 = rreg; 1908 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend 1909 if (ImplicitDiv0Checks) { 1910 // No debug info because the idiv won't trap. 1911 // Add_debug_info_for_div0 would instantiate another DivByZeroStub, 1912 // which is unnecessary, too. 1913 add_debug_info_for_div0(__ offset(), info); 1914 } 1915 __ z_dsgfr(R1, R2); 1916 } 1917 1918 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1919 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match"); 1920 assert(exceptionPC->as_register() == Z_EXC_PC, "should match"); 1921 1922 // Exception object is not added to oop map by LinearScan 1923 // (LinearScan assumes that no oops are in fixed registers). 1924 info->add_register_oop(exceptionOop); 1925 1926 // Reuse the debug info from the safepoint poll for the throw op itself. 1927 __ get_PC(Z_EXC_PC); 1928 add_call_info(__ offset(), info); // for exception handler 1929 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id 1930 : Runtime1::handle_exception_nofpu_id); 1931 emit_call_c(stub); 1932 } 1933 1934 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1935 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match"); 1936 1937 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry); 1938 } 1939 1940 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1941 ciArrayKlass* default_type = op->expected_type(); 1942 Register src = op->src()->as_register(); 1943 Register dst = op->dst()->as_register(); 1944 Register src_pos = op->src_pos()->as_register(); 1945 Register dst_pos = op->dst_pos()->as_register(); 1946 Register length = op->length()->as_register(); 1947 Register tmp = op->tmp()->as_register(); 1948 1949 CodeStub* stub = op->stub(); 1950 int flags = op->flags(); 1951 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1952 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1953 1954 // If we don't know anything, just go through the generic arraycopy. 1955 if (default_type == NULL) { 1956 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1957 1958 if (copyfunc_addr == NULL) { 1959 // Take a slow path for generic arraycopy. 1960 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 1961 __ bind(*stub->continuation()); 1962 return; 1963 } 1964 1965 // Save outgoing arguments in callee saved registers (C convention) in case 1966 // a call to System.arraycopy is needed. 1967 Register callee_saved_src = Z_R10; 1968 Register callee_saved_src_pos = Z_R11; 1969 Register callee_saved_dst = Z_R12; 1970 Register callee_saved_dst_pos = Z_R13; 1971 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved. 1972 1973 __ lgr_if_needed(callee_saved_src, src); 1974 __ lgr_if_needed(callee_saved_src_pos, src_pos); 1975 __ lgr_if_needed(callee_saved_dst, dst); 1976 __ lgr_if_needed(callee_saved_dst_pos, dst_pos); 1977 __ lgr_if_needed(callee_saved_length, length); 1978 1979 // C function requires 64 bit values. 1980 __ z_lgfr(src_pos, src_pos); 1981 __ z_lgfr(dst_pos, dst_pos); 1982 __ z_lgfr(length, length); 1983 1984 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint. 1985 1986 // The arguments are in the corresponding registers. 1987 assert(Z_ARG1 == src, "assumption"); 1988 assert(Z_ARG2 == src_pos, "assumption"); 1989 assert(Z_ARG3 == dst, "assumption"); 1990 assert(Z_ARG4 == dst_pos, "assumption"); 1991 assert(Z_ARG5 == length, "assumption"); 1992 #ifndef PRODUCT 1993 if (PrintC1Statistics) { 1994 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt); 1995 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 1996 } 1997 #endif 1998 emit_call_c(copyfunc_addr); 1999 CHECK_BAILOUT(); 2000 2001 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation()); 2002 2003 __ z_lgr(tmp, Z_RET); 2004 __ z_xilf(tmp, -1); 2005 2006 // Restore values from callee saved registers so they are where the stub 2007 // expects them. 2008 __ lgr_if_needed(src, callee_saved_src); 2009 __ lgr_if_needed(src_pos, callee_saved_src_pos); 2010 __ lgr_if_needed(dst, callee_saved_dst); 2011 __ lgr_if_needed(dst_pos, callee_saved_dst_pos); 2012 __ lgr_if_needed(length, callee_saved_length); 2013 2014 __ z_sr(length, tmp); 2015 __ z_ar(src_pos, tmp); 2016 __ z_ar(dst_pos, tmp); 2017 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 2018 2019 __ bind(*stub->continuation()); 2020 return; 2021 } 2022 2023 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 2024 2025 int elem_size = type2aelembytes(basic_type); 2026 int shift_amount; 2027 2028 switch (elem_size) { 2029 case 1 : 2030 shift_amount = 0; 2031 break; 2032 case 2 : 2033 shift_amount = 1; 2034 break; 2035 case 4 : 2036 shift_amount = 2; 2037 break; 2038 case 8 : 2039 shift_amount = 3; 2040 break; 2041 default: 2042 shift_amount = -1; 2043 ShouldNotReachHere(); 2044 } 2045 2046 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 2047 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 2048 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 2049 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 2050 2051 // Length and pos's are all sign extended at this point on 64bit. 2052 2053 // test for NULL 2054 if (flags & LIR_OpArrayCopy::src_null_check) { 2055 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry()); 2056 } 2057 if (flags & LIR_OpArrayCopy::dst_null_check) { 2058 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry()); 2059 } 2060 2061 // Check if negative. 2062 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2063 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry()); 2064 } 2065 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2066 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry()); 2067 } 2068 2069 // If the compiler was not able to prove that exact type of the source or the destination 2070 // of the arraycopy is an array type, check at runtime if the source or the destination is 2071 // an instance type. 2072 if (flags & LIR_OpArrayCopy::type_check) { 2073 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions"); 2074 2075 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2076 __ load_klass(tmp, dst); 2077 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2078 __ branch_optimized(Assembler::bcondNotLow, *stub->entry()); 2079 } 2080 2081 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2082 __ load_klass(tmp, src); 2083 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2084 __ branch_optimized(Assembler::bcondNotLow, *stub->entry()); 2085 } 2086 } 2087 2088 if (flags & LIR_OpArrayCopy::src_range_check) { 2089 __ z_la(tmp, Address(src_pos, length)); 2090 __ z_cl(tmp, src_length_addr); 2091 __ branch_optimized(Assembler::bcondHigh, *stub->entry()); 2092 } 2093 if (flags & LIR_OpArrayCopy::dst_range_check) { 2094 __ z_la(tmp, Address(dst_pos, length)); 2095 __ z_cl(tmp, dst_length_addr); 2096 __ branch_optimized(Assembler::bcondHigh, *stub->entry()); 2097 } 2098 2099 if (flags & LIR_OpArrayCopy::length_positive_check) { 2100 __ z_ltr(length, length); 2101 __ branch_optimized(Assembler::bcondNegative, *stub->entry()); 2102 } 2103 2104 // Stubs require 64 bit values. 2105 __ z_lgfr(src_pos, src_pos); // int -> long 2106 __ z_lgfr(dst_pos, dst_pos); // int -> long 2107 __ z_lgfr(length, length); // int -> long 2108 2109 if (flags & LIR_OpArrayCopy::type_check) { 2110 // We don't know the array types are compatible. 2111 if (basic_type != T_OBJECT) { 2112 // Simple test for basic type arrays. 2113 if (UseCompressedClassPointers) { 2114 __ z_l(tmp, src_klass_addr); 2115 __ z_c(tmp, dst_klass_addr); 2116 } else { 2117 __ z_lg(tmp, src_klass_addr); 2118 __ z_cg(tmp, dst_klass_addr); 2119 } 2120 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry()); 2121 } else { 2122 // For object arrays, if src is a sub class of dst then we can 2123 // safely do the copy. 2124 NearLabel cont, slow; 2125 Register src_klass = Z_R1_scratch; 2126 Register dst_klass = Z_R10; 2127 2128 __ load_klass(src_klass, src); 2129 __ load_klass(dst_klass, dst); 2130 2131 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL); 2132 2133 store_parameter(src_klass, 0); // sub 2134 store_parameter(dst_klass, 1); // super 2135 emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id)); 2136 CHECK_BAILOUT2(cont, slow); 2137 // Sets condition code 0 for match (2 otherwise). 2138 __ branch_optimized(Assembler::bcondEqual, cont); 2139 2140 __ bind(slow); 2141 2142 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2143 if (copyfunc_addr != NULL) { // use stub if available 2144 // Src is not a sub class of dst so we have to do a 2145 // per-element check. 2146 2147 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2148 if ((flags & mask) != mask) { 2149 // Check that at least both of them object arrays. 2150 assert(flags & mask, "one of the two should be known to be an object array"); 2151 2152 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2153 __ load_klass(tmp, src); 2154 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2155 __ load_klass(tmp, dst); 2156 } 2157 Address klass_lh_addr(tmp, Klass::layout_helper_offset()); 2158 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2159 __ load_const_optimized(Z_R1_scratch, objArray_lh); 2160 __ z_c(Z_R1_scratch, klass_lh_addr); 2161 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry()); 2162 } 2163 2164 // Save outgoing arguments in callee saved registers (C convention) in case 2165 // a call to System.arraycopy is needed. 2166 Register callee_saved_src = Z_R10; 2167 Register callee_saved_src_pos = Z_R11; 2168 Register callee_saved_dst = Z_R12; 2169 Register callee_saved_dst_pos = Z_R13; 2170 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved. 2171 2172 __ lgr_if_needed(callee_saved_src, src); 2173 __ lgr_if_needed(callee_saved_src_pos, src_pos); 2174 __ lgr_if_needed(callee_saved_dst, dst); 2175 __ lgr_if_needed(callee_saved_dst_pos, dst_pos); 2176 __ lgr_if_needed(callee_saved_length, length); 2177 2178 __ z_llgfr(length, length); // Higher 32bits must be null. 2179 2180 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset 2181 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset 2182 2183 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type))); 2184 assert_different_registers(Z_ARG1, dst, dst_pos, length); 2185 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type))); 2186 assert_different_registers(Z_ARG2, dst, length); 2187 2188 __ z_lgr(Z_ARG3, length); 2189 assert_different_registers(Z_ARG3, dst); 2190 2191 __ load_klass(Z_ARG5, dst); 2192 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset())); 2193 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset())); 2194 emit_call_c(copyfunc_addr); 2195 CHECK_BAILOUT2(cont, slow); 2196 2197 #ifndef PRODUCT 2198 if (PrintC1Statistics) { 2199 NearLabel failed; 2200 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed); 2201 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt); 2202 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 2203 __ bind(failed); 2204 } 2205 #endif 2206 2207 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation()); 2208 2209 #ifndef PRODUCT 2210 if (PrintC1Statistics) { 2211 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt); 2212 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 2213 } 2214 #endif 2215 2216 __ z_lgr(tmp, Z_RET); 2217 __ z_xilf(tmp, -1); 2218 2219 // Restore previously spilled arguments 2220 __ lgr_if_needed(src, callee_saved_src); 2221 __ lgr_if_needed(src_pos, callee_saved_src_pos); 2222 __ lgr_if_needed(dst, callee_saved_dst); 2223 __ lgr_if_needed(dst_pos, callee_saved_dst_pos); 2224 __ lgr_if_needed(length, callee_saved_length); 2225 2226 __ z_sr(length, tmp); 2227 __ z_ar(src_pos, tmp); 2228 __ z_ar(dst_pos, tmp); 2229 } 2230 2231 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 2232 2233 __ bind(cont); 2234 } 2235 } 2236 2237 #ifdef ASSERT 2238 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2239 // Sanity check the known type with the incoming class. For the 2240 // primitive case the types must match exactly with src.klass and 2241 // dst.klass each exactly matching the default type. For the 2242 // object array case, if no type check is needed then either the 2243 // dst type is exactly the expected type and the src type is a 2244 // subtype which we can't check or src is the same array as dst 2245 // but not necessarily exactly of type default_type. 2246 NearLabel known_ok, halt; 2247 metadata2reg(default_type->constant_encoding(), tmp); 2248 if (UseCompressedClassPointers) { 2249 __ encode_klass_not_null(tmp); 2250 } 2251 2252 if (basic_type != T_OBJECT) { 2253 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); } 2254 else { __ z_cg(tmp, dst_klass_addr); } 2255 __ branch_optimized(Assembler::bcondNotEqual, halt); 2256 if (UseCompressedClassPointers) { __ z_c (tmp, src_klass_addr); } 2257 else { __ z_cg(tmp, src_klass_addr); } 2258 __ branch_optimized(Assembler::bcondEqual, known_ok); 2259 } else { 2260 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); } 2261 else { __ z_cg(tmp, dst_klass_addr); } 2262 __ branch_optimized(Assembler::bcondEqual, known_ok); 2263 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok); 2264 } 2265 __ bind(halt); 2266 __ stop("incorrect type information in arraycopy"); 2267 __ bind(known_ok); 2268 } 2269 #endif 2270 2271 #ifndef PRODUCT 2272 if (PrintC1Statistics) { 2273 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type)); 2274 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 2275 } 2276 #endif 2277 2278 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset 2279 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset 2280 2281 assert_different_registers(Z_ARG1, dst, dst_pos, length); 2282 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type))); 2283 assert_different_registers(Z_ARG2, length); 2284 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type))); 2285 __ lgr_if_needed(Z_ARG3, length); 2286 2287 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2288 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2289 const char *name; 2290 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2291 __ call_VM_leaf(entry); 2292 2293 __ bind(*stub->continuation()); 2294 } 2295 2296 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2297 if (dest->is_single_cpu()) { 2298 if (left->type() == T_OBJECT) { 2299 switch (code) { 2300 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break; 2301 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break; 2302 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break; 2303 default: ShouldNotReachHere(); 2304 } 2305 } else { 2306 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts"); 2307 Register masked_count = Z_R1_scratch; 2308 __ z_lr(masked_count, count->as_register()); 2309 __ z_nill(masked_count, 31); 2310 switch (code) { 2311 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break; 2312 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break; 2313 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break; 2314 default: ShouldNotReachHere(); 2315 } 2316 } 2317 } else { 2318 switch (code) { 2319 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break; 2320 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break; 2321 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break; 2322 default: ShouldNotReachHere(); 2323 } 2324 } 2325 } 2326 2327 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2328 if (left->type() == T_OBJECT) { 2329 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t). 2330 Register l = left->as_register(); 2331 Register d = dest->as_register_lo(); 2332 switch (code) { 2333 case lir_shl: __ z_sllg (d, l, count); break; 2334 case lir_shr: __ z_srag (d, l, count); break; 2335 case lir_ushr: __ z_srlg (d, l, count); break; 2336 default: ShouldNotReachHere(); 2337 } 2338 return; 2339 } 2340 if (dest->is_single_cpu()) { 2341 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts"); 2342 count = count & 0x1F; // Java spec 2343 switch (code) { 2344 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break; 2345 case lir_shr: __ z_sra (dest->as_register(), count); break; 2346 case lir_ushr: __ z_srl (dest->as_register(), count); break; 2347 default: ShouldNotReachHere(); 2348 } 2349 } else if (dest->is_double_cpu()) { 2350 count = count & 63; // Java spec 2351 Register l = left->as_pointer_register(); 2352 Register d = dest->as_pointer_register(); 2353 switch (code) { 2354 case lir_shl: __ z_sllg (d, l, count); break; 2355 case lir_shr: __ z_srag (d, l, count); break; 2356 case lir_ushr: __ z_srlg (d, l, count); break; 2357 default: ShouldNotReachHere(); 2358 } 2359 } else { 2360 ShouldNotReachHere(); 2361 } 2362 } 2363 2364 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2365 if (op->init_check()) { 2366 // Make sure klass is initialized & doesn't have finalizer. 2367 const int state_offset = in_bytes(InstanceKlass::init_state_offset()); 2368 Register iklass = op->klass()->as_register(); 2369 add_debug_info_for_null_check_here(op->stub()->info()); 2370 if (Immediate::is_uimm12(state_offset)) { 2371 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized); 2372 } else { 2373 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized); 2374 } 2375 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far. 2376 } 2377 __ allocate_object(op->obj()->as_register(), 2378 op->tmp1()->as_register(), 2379 op->tmp2()->as_register(), 2380 op->header_size(), 2381 op->object_size(), 2382 op->klass()->as_register(), 2383 *op->stub()->entry()); 2384 __ bind(*op->stub()->continuation()); 2385 __ verify_oop(op->obj()->as_register(), FILE_AND_LINE); 2386 } 2387 2388 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2389 Register len = op->len()->as_register(); 2390 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend 2391 2392 if (UseSlowPath || 2393 (!UseFastNewObjectArray && (is_reference_type(op->type()))) || 2394 (!UseFastNewTypeArray && (!is_reference_type(op->type())))) { 2395 __ z_brul(*op->stub()->entry()); 2396 } else { 2397 __ allocate_array(op->obj()->as_register(), 2398 op->len()->as_register(), 2399 op->tmp1()->as_register(), 2400 op->tmp2()->as_register(), 2401 arrayOopDesc::header_size(op->type()), 2402 type2aelembytes(op->type()), 2403 op->klass()->as_register(), 2404 *op->stub()->entry()); 2405 } 2406 __ bind(*op->stub()->continuation()); 2407 } 2408 2409 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, 2410 Register recv, Register tmp1, Label* update_done) { 2411 uint i; 2412 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2413 Label next_test; 2414 // See if the receiver is receiver[n]. 2415 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 2416 __ z_cg(recv, receiver_addr); 2417 __ z_brne(next_test); 2418 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 2419 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1); 2420 __ branch_optimized(Assembler::bcondAlways, *update_done); 2421 __ bind(next_test); 2422 } 2423 2424 // Didn't find receiver; find next empty slot and fill it in. 2425 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2426 Label next_test; 2427 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 2428 __ z_ltg(Z_R0_scratch, recv_addr); 2429 __ z_brne(next_test); 2430 __ z_stg(recv, recv_addr); 2431 __ load_const_optimized(tmp1, DataLayout::counter_increment); 2432 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo); 2433 __ branch_optimized(Assembler::bcondAlways, *update_done); 2434 __ bind(next_test); 2435 } 2436 } 2437 2438 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2439 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2440 Unimplemented(); 2441 } 2442 2443 void LIR_Assembler::store_parameter(Register r, int param_num) { 2444 assert(param_num >= 0, "invalid num"); 2445 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame; 2446 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2447 __ z_stg(r, offset_in_bytes, Z_SP); 2448 } 2449 2450 void LIR_Assembler::store_parameter(jint c, int param_num) { 2451 assert(param_num >= 0, "invalid num"); 2452 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame; 2453 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2454 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true); 2455 } 2456 2457 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2458 // We always need a stub for the failure case. 2459 CodeStub* stub = op->stub(); 2460 Register obj = op->object()->as_register(); 2461 Register k_RInfo = op->tmp1()->as_register(); 2462 Register klass_RInfo = op->tmp2()->as_register(); 2463 Register dst = op->result_opr()->as_register(); 2464 Register Rtmp1 = Z_R1_scratch; 2465 ciKlass* k = op->klass(); 2466 2467 assert(!op->tmp3()->is_valid(), "tmp3's not needed"); 2468 2469 // Check if it needs to be profiled. 2470 ciMethodData* md = NULL; 2471 ciProfileData* data = NULL; 2472 2473 if (op->should_profile()) { 2474 ciMethod* method = op->profiled_method(); 2475 assert(method != NULL, "Should have method"); 2476 int bci = op->profiled_bci(); 2477 md = method->method_data_or_null(); 2478 assert(md != NULL, "Sanity"); 2479 data = md->bci_to_data(bci); 2480 assert(data != NULL, "need data for type check"); 2481 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2482 } 2483 2484 // Temp operands do not overlap with inputs, if this is their last 2485 // use (end of range is exclusive), so a register conflict is possible. 2486 if (obj == k_RInfo) { 2487 k_RInfo = dst; 2488 } else if (obj == klass_RInfo) { 2489 klass_RInfo = dst; 2490 } 2491 assert_different_registers(obj, k_RInfo, klass_RInfo); 2492 2493 if (op->should_profile()) { 2494 NearLabel not_null; 2495 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null); 2496 // Object is null; update MDO and exit. 2497 Register mdo = klass_RInfo; 2498 metadata2reg(md->constant_encoding(), mdo); 2499 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 2500 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 2501 __ or2mem_8(data_addr, header_bits); 2502 __ branch_optimized(Assembler::bcondAlways, *obj_is_null); 2503 __ bind(not_null); 2504 } else { 2505 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null); 2506 } 2507 2508 NearLabel profile_cast_failure, profile_cast_success; 2509 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 2510 Label *success_target = op->should_profile() ? &profile_cast_success : success; 2511 2512 // Patching may screw with our temporaries, 2513 // so let's do it before loading the class. 2514 if (k->is_loaded()) { 2515 metadata2reg(k->constant_encoding(), k_RInfo); 2516 } else { 2517 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2518 } 2519 assert(obj != k_RInfo, "must be different"); 2520 2521 __ verify_oop(obj, FILE_AND_LINE); 2522 2523 // Get object class. 2524 // Not a safepoint as obj null check happens earlier. 2525 if (op->fast_check()) { 2526 if (UseCompressedClassPointers) { 2527 __ load_klass(klass_RInfo, obj); 2528 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target); 2529 } else { 2530 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 2531 __ branch_optimized(Assembler::bcondNotEqual, *failure_target); 2532 } 2533 // Successful cast, fall through to profile or jump. 2534 } else { 2535 bool need_slow_path = !k->is_loaded() || 2536 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset())); 2537 intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L; 2538 __ load_klass(klass_RInfo, obj); 2539 // Perform the fast part of the checking logic. 2540 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, 2541 (need_slow_path ? success_target : NULL), 2542 failure_target, NULL, 2543 RegisterOrConstant(super_check_offset)); 2544 if (need_slow_path) { 2545 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2546 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id); 2547 store_parameter(klass_RInfo, 0); // sub 2548 store_parameter(k_RInfo, 1); // super 2549 emit_call_c(a); // Sets condition code 0 for match (2 otherwise). 2550 CHECK_BAILOUT2(profile_cast_failure, profile_cast_success); 2551 __ branch_optimized(Assembler::bcondNotEqual, *failure_target); 2552 // Fall through to success case. 2553 } 2554 } 2555 2556 if (op->should_profile()) { 2557 Register mdo = klass_RInfo, recv = k_RInfo; 2558 assert_different_registers(obj, mdo, recv); 2559 __ bind(profile_cast_success); 2560 metadata2reg(md->constant_encoding(), mdo); 2561 __ load_klass(recv, obj); 2562 type_profile_helper(mdo, md, data, recv, Rtmp1, success); 2563 __ branch_optimized(Assembler::bcondAlways, *success); 2564 2565 __ bind(profile_cast_failure); 2566 metadata2reg(md->constant_encoding(), mdo); 2567 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1); 2568 __ branch_optimized(Assembler::bcondAlways, *failure); 2569 } else { 2570 __ branch_optimized(Assembler::bcondAlways, *success); 2571 } 2572 } 2573 2574 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2575 LIR_Code code = op->code(); 2576 if (code == lir_store_check) { 2577 Register value = op->object()->as_register(); 2578 Register array = op->array()->as_register(); 2579 Register k_RInfo = op->tmp1()->as_register(); 2580 Register klass_RInfo = op->tmp2()->as_register(); 2581 Register Rtmp1 = Z_R1_scratch; 2582 2583 CodeStub* stub = op->stub(); 2584 2585 // Check if it needs to be profiled. 2586 ciMethodData* md = NULL; 2587 ciProfileData* data = NULL; 2588 2589 assert_different_registers(value, k_RInfo, klass_RInfo); 2590 2591 if (op->should_profile()) { 2592 ciMethod* method = op->profiled_method(); 2593 assert(method != NULL, "Should have method"); 2594 int bci = op->profiled_bci(); 2595 md = method->method_data_or_null(); 2596 assert(md != NULL, "Sanity"); 2597 data = md->bci_to_data(bci); 2598 assert(data != NULL, "need data for type check"); 2599 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2600 } 2601 NearLabel profile_cast_success, profile_cast_failure, done; 2602 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 2603 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 2604 2605 if (op->should_profile()) { 2606 NearLabel not_null; 2607 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null); 2608 // Object is null; update MDO and exit. 2609 Register mdo = klass_RInfo; 2610 metadata2reg(md->constant_encoding(), mdo); 2611 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 2612 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 2613 __ or2mem_8(data_addr, header_bits); 2614 __ branch_optimized(Assembler::bcondAlways, done); 2615 __ bind(not_null); 2616 } else { 2617 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done); 2618 } 2619 2620 add_debug_info_for_null_check_here(op->info_for_exception()); 2621 __ load_klass(k_RInfo, array); 2622 __ load_klass(klass_RInfo, value); 2623 2624 // Get instance klass (it's already uncompressed). 2625 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 2626 // Perform the fast part of the checking logic. 2627 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 2628 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2629 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id); 2630 store_parameter(klass_RInfo, 0); // sub 2631 store_parameter(k_RInfo, 1); // super 2632 emit_call_c(a); // Sets condition code 0 for match (2 otherwise). 2633 CHECK_BAILOUT3(profile_cast_success, profile_cast_failure, done); 2634 __ branch_optimized(Assembler::bcondNotEqual, *failure_target); 2635 // Fall through to success case. 2636 2637 if (op->should_profile()) { 2638 Register mdo = klass_RInfo, recv = k_RInfo; 2639 assert_different_registers(value, mdo, recv); 2640 __ bind(profile_cast_success); 2641 metadata2reg(md->constant_encoding(), mdo); 2642 __ load_klass(recv, value); 2643 type_profile_helper(mdo, md, data, recv, Rtmp1, &done); 2644 __ branch_optimized(Assembler::bcondAlways, done); 2645 2646 __ bind(profile_cast_failure); 2647 metadata2reg(md->constant_encoding(), mdo); 2648 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1); 2649 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 2650 } 2651 2652 __ bind(done); 2653 } else { 2654 if (code == lir_checkcast) { 2655 Register obj = op->object()->as_register(); 2656 Register dst = op->result_opr()->as_register(); 2657 NearLabel success; 2658 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 2659 __ bind(success); 2660 __ lgr_if_needed(dst, obj); 2661 } else { 2662 if (code == lir_instanceof) { 2663 Register obj = op->object()->as_register(); 2664 Register dst = op->result_opr()->as_register(); 2665 NearLabel success, failure, done; 2666 emit_typecheck_helper(op, &success, &failure, &failure); 2667 __ bind(failure); 2668 __ clear_reg(dst); 2669 __ branch_optimized(Assembler::bcondAlways, done); 2670 __ bind(success); 2671 __ load_const_optimized(dst, 1); 2672 __ bind(done); 2673 } else { 2674 ShouldNotReachHere(); 2675 } 2676 } 2677 } 2678 } 2679 2680 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2681 Register addr = op->addr()->as_pointer_register(); 2682 Register t1_cmp = Z_R1_scratch; 2683 if (op->code() == lir_cas_long) { 2684 assert(VM_Version::supports_cx8(), "wrong machine"); 2685 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2686 Register new_value_lo = op->new_value()->as_register_lo(); 2687 __ z_lgr(t1_cmp, cmp_value_lo); 2688 // Perform the compare and swap operation. 2689 __ z_csg(t1_cmp, new_value_lo, 0, addr); 2690 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2691 Register cmp_value = op->cmp_value()->as_register(); 2692 Register new_value = op->new_value()->as_register(); 2693 if (op->code() == lir_cas_obj) { 2694 if (UseCompressedOops) { 2695 t1_cmp = op->tmp1()->as_register(); 2696 Register t2_new = op->tmp2()->as_register(); 2697 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new); 2698 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/); 2699 __ oop_encoder(t2_new, new_value, true /*maybe null*/); 2700 __ z_cs(t1_cmp, t2_new, 0, addr); 2701 } else { 2702 __ z_lgr(t1_cmp, cmp_value); 2703 __ z_csg(t1_cmp, new_value, 0, addr); 2704 } 2705 } else { 2706 __ z_lr(t1_cmp, cmp_value); 2707 __ z_cs(t1_cmp, new_value, 0, addr); 2708 } 2709 } else { 2710 ShouldNotReachHere(); // new lir_cas_?? 2711 } 2712 } 2713 2714 void LIR_Assembler::breakpoint() { 2715 Unimplemented(); 2716 // __ breakpoint_trap(); 2717 } 2718 2719 void LIR_Assembler::push(LIR_Opr opr) { 2720 ShouldNotCallThis(); // unused 2721 } 2722 2723 void LIR_Assembler::pop(LIR_Opr opr) { 2724 ShouldNotCallThis(); // unused 2725 } 2726 2727 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2728 Address addr = frame_map()->address_for_monitor_lock(monitor_no); 2729 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base()); 2730 } 2731 2732 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2733 Register obj = op->obj_opr()->as_register(); // May not be an oop. 2734 Register hdr = op->hdr_opr()->as_register(); 2735 Register lock = op->lock_opr()->as_register(); 2736 if (UseHeavyMonitors) { 2737 __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry()); 2738 } else if (op->code() == lir_lock) { 2739 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2740 // Add debug info for NullPointerException only if one is possible. 2741 if (op->info() != NULL) { 2742 add_debug_info_for_null_check_here(op->info()); 2743 } 2744 __ lock_object(hdr, obj, lock, *op->stub()->entry()); 2745 // done 2746 } else if (op->code() == lir_unlock) { 2747 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2748 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2749 } else { 2750 ShouldNotReachHere(); 2751 } 2752 __ bind(*op->stub()->continuation()); 2753 } 2754 2755 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { 2756 Register obj = op->obj()->as_pointer_register(); 2757 Register result = op->result_opr()->as_pointer_register(); 2758 2759 CodeEmitInfo* info = op->info(); 2760 if (info != NULL) { 2761 add_debug_info_for_null_check_here(info); 2762 } 2763 2764 if (UseCompressedClassPointers) { 2765 __ z_llgf(result, Address(obj, oopDesc::klass_offset_in_bytes())); 2766 __ decode_klass_not_null(result); 2767 } else { 2768 __ z_lg(result, Address(obj, oopDesc::klass_offset_in_bytes())); 2769 } 2770 } 2771 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2772 ciMethod* method = op->profiled_method(); 2773 int bci = op->profiled_bci(); 2774 ciMethod* callee = op->profiled_callee(); 2775 2776 // Update counter for all call types. 2777 ciMethodData* md = method->method_data_or_null(); 2778 assert(md != NULL, "Sanity"); 2779 ciProfileData* data = md->bci_to_data(bci); 2780 assert(data != NULL && data->is_CounterData(), "need CounterData for calls"); 2781 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2782 Register mdo = op->mdo()->as_register(); 2783 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2784 Register tmp1 = op->tmp1()->as_register_lo(); 2785 metadata2reg(md->constant_encoding(), mdo); 2786 2787 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 2788 // Perform additional virtual call profiling for invokevirtual and 2789 // invokeinterface bytecodes 2790 if (op->should_profile_receiver_type()) { 2791 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2792 Register recv = op->recv()->as_register(); 2793 assert_different_registers(mdo, tmp1, recv); 2794 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2795 ciKlass* known_klass = op->known_holder(); 2796 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2797 // We know the type that will be seen at this call site; we can 2798 // statically update the MethodData* rather than needing to do 2799 // dynamic tests on the receiver type. 2800 2801 // NOTE: we should probably put a lock around this search to 2802 // avoid collisions by concurrent compilations. 2803 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2804 uint i; 2805 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2806 ciKlass* receiver = vc_data->receiver(i); 2807 if (known_klass->equals(receiver)) { 2808 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2809 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1); 2810 return; 2811 } 2812 } 2813 2814 // Receiver type not found in profile data. Select an empty slot. 2815 2816 // Note that this is less efficient than it should be because it 2817 // always does a write to the receiver part of the 2818 // VirtualCallData rather than just the first time. 2819 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2820 ciKlass* receiver = vc_data->receiver(i); 2821 if (receiver == NULL) { 2822 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 2823 metadata2reg(known_klass->constant_encoding(), tmp1); 2824 __ z_stg(tmp1, recv_addr); 2825 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2826 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1); 2827 return; 2828 } 2829 } 2830 } else { 2831 __ load_klass(recv, recv); 2832 NearLabel update_done; 2833 type_profile_helper(mdo, md, data, recv, tmp1, &update_done); 2834 // Receiver did not match any saved receiver and there is no empty row for it. 2835 // Increment total counter to indicate polymorphic case. 2836 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1); 2837 __ bind(update_done); 2838 } 2839 } else { 2840 // static call 2841 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1); 2842 } 2843 } 2844 2845 void LIR_Assembler::align_backward_branch_target() { 2846 __ align(OptoLoopAlignment); 2847 } 2848 2849 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2850 ShouldNotCallThis(); // There are no delay slots on ZARCH_64. 2851 } 2852 2853 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { 2854 // tmp must be unused 2855 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2856 assert(left->is_register(), "can only handle registers"); 2857 2858 if (left->is_single_cpu()) { 2859 __ z_lcr(dest->as_register(), left->as_register()); 2860 } else if (left->is_single_fpu()) { 2861 __ z_lcebr(dest->as_float_reg(), left->as_float_reg()); 2862 } else if (left->is_double_fpu()) { 2863 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg()); 2864 } else { 2865 assert(left->is_double_cpu(), "Must be a long"); 2866 __ z_lcgr(dest->as_register_lo(), left->as_register_lo()); 2867 } 2868 } 2869 2870 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 2871 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2872 assert(!tmp->is_valid(), "don't need temporary"); 2873 emit_call_c(dest); 2874 CHECK_BAILOUT(); 2875 if (info != NULL) { 2876 add_call_info_here(info); 2877 } 2878 } 2879 2880 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2881 ShouldNotCallThis(); // not needed on ZARCH_64 2882 } 2883 2884 void LIR_Assembler::membar() { 2885 __ z_fence(); 2886 } 2887 2888 void LIR_Assembler::membar_acquire() { 2889 __ z_acquire(); 2890 } 2891 2892 void LIR_Assembler::membar_release() { 2893 __ z_release(); 2894 } 2895 2896 void LIR_Assembler::membar_loadload() { 2897 __ z_acquire(); 2898 } 2899 2900 void LIR_Assembler::membar_storestore() { 2901 __ z_release(); 2902 } 2903 2904 void LIR_Assembler::membar_loadstore() { 2905 __ z_acquire(); 2906 } 2907 2908 void LIR_Assembler::membar_storeload() { 2909 __ z_fence(); 2910 } 2911 2912 void LIR_Assembler::on_spin_wait() { 2913 Unimplemented(); 2914 } 2915 2916 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 2917 assert(patch_code == lir_patch_none, "Patch code not supported"); 2918 LIR_Address* addr = addr_opr->as_address_ptr(); 2919 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported"); 2920 __ load_address(dest->as_pointer_register(), as_Address(addr)); 2921 } 2922 2923 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2924 ShouldNotCallThis(); // unused 2925 } 2926 2927 #ifdef ASSERT 2928 // Emit run-time assertion. 2929 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2930 Unimplemented(); 2931 } 2932 #endif 2933 2934 void LIR_Assembler::peephole(LIR_List*) { 2935 // Do nothing for now. 2936 } 2937 2938 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 2939 assert(code == lir_xadd, "lir_xchg not supported"); 2940 Address src_addr = as_Address(src->as_address_ptr()); 2941 Register base = src_addr.base(); 2942 intptr_t disp = src_addr.disp(); 2943 if (src_addr.index()->is_valid()) { 2944 // LAA and LAAG do not support index register. 2945 __ load_address(Z_R1_scratch, src_addr); 2946 base = Z_R1_scratch; 2947 disp = 0; 2948 } 2949 if (data->type() == T_INT) { 2950 __ z_laa(dest->as_register(), data->as_register(), disp, base); 2951 } else if (data->type() == T_LONG) { 2952 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 2953 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base); 2954 } else { 2955 ShouldNotReachHere(); 2956 } 2957 } 2958 2959 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2960 Register obj = op->obj()->as_register(); 2961 Register tmp1 = op->tmp()->as_pointer_register(); 2962 Register tmp2 = Z_R1_scratch; 2963 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2964 ciKlass* exact_klass = op->exact_klass(); 2965 intptr_t current_klass = op->current_klass(); 2966 bool not_null = op->not_null(); 2967 bool no_conflict = op->no_conflict(); 2968 2969 Label update, next, none, null_seen, init_klass; 2970 2971 bool do_null = !not_null; 2972 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2973 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2974 2975 assert(do_null || do_update, "why are we here?"); 2976 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2977 2978 __ verify_oop(obj, FILE_AND_LINE); 2979 2980 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) { 2981 __ z_ltgr(tmp1, obj); 2982 } 2983 if (do_null) { 2984 __ z_brnz(update); 2985 if (!TypeEntries::was_null_seen(current_klass)) { 2986 __ z_lg(tmp1, mdo_addr); 2987 __ z_oill(tmp1, TypeEntries::null_seen); 2988 __ z_stg(tmp1, mdo_addr); 2989 } 2990 if (do_update) { 2991 __ z_bru(next); 2992 } 2993 } else { 2994 __ asm_assert_ne("unexpect null obj", __LINE__); 2995 } 2996 2997 __ bind(update); 2998 2999 if (do_update) { 3000 #ifdef ASSERT 3001 if (exact_klass != NULL) { 3002 __ load_klass(tmp1, tmp1); 3003 metadata2reg(exact_klass->constant_encoding(), tmp2); 3004 __ z_cgr(tmp1, tmp2); 3005 __ asm_assert_eq("exact klass and actual klass differ", __LINE__); 3006 } 3007 #endif 3008 3009 Label do_update; 3010 __ z_lg(tmp2, mdo_addr); 3011 3012 if (!no_conflict) { 3013 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 3014 if (exact_klass != NULL) { 3015 metadata2reg(exact_klass->constant_encoding(), tmp1); 3016 } else { 3017 __ load_klass(tmp1, tmp1); 3018 } 3019 3020 // Klass seen before: nothing to do (regardless of unknown bit). 3021 __ z_lgr(Z_R0_scratch, tmp2); 3022 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction"); 3023 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF); 3024 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next); 3025 3026 // Already unknown: Nothing to do anymore. 3027 __ z_tmll(tmp2, TypeEntries::type_unknown); 3028 __ z_brc(Assembler::bcondAllOne, next); 3029 3030 if (TypeEntries::is_type_none(current_klass)) { 3031 __ z_lgr(Z_R0_scratch, tmp2); 3032 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction"); 3033 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF); 3034 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass); 3035 } 3036 } else { 3037 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3038 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 3039 3040 // Already unknown: Nothing to do anymore. 3041 __ z_tmll(tmp2, TypeEntries::type_unknown); 3042 __ z_brc(Assembler::bcondAllOne, next); 3043 } 3044 3045 // Different than before. Cannot keep accurate profile. 3046 __ z_oill(tmp2, TypeEntries::type_unknown); 3047 __ z_bru(do_update); 3048 } else { 3049 // There's a single possible klass at this profile point. 3050 assert(exact_klass != NULL, "should be"); 3051 if (TypeEntries::is_type_none(current_klass)) { 3052 metadata2reg(exact_klass->constant_encoding(), tmp1); 3053 __ z_lgr(Z_R0_scratch, tmp2); 3054 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction"); 3055 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF); 3056 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next); 3057 #ifdef ASSERT 3058 { 3059 Label ok; 3060 __ z_lgr(Z_R0_scratch, tmp2); 3061 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction"); 3062 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF); 3063 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok); 3064 __ stop("unexpected profiling mismatch"); 3065 __ bind(ok); 3066 } 3067 #endif 3068 3069 } else { 3070 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3071 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3072 3073 // Already unknown: Nothing to do anymore. 3074 __ z_tmll(tmp2, TypeEntries::type_unknown); 3075 __ z_brc(Assembler::bcondAllOne, next); 3076 __ z_oill(tmp2, TypeEntries::type_unknown); 3077 __ z_bru(do_update); 3078 } 3079 } 3080 3081 __ bind(init_klass); 3082 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3083 __ z_ogr(tmp2, tmp1); 3084 3085 __ bind(do_update); 3086 __ z_stg(tmp2, mdo_addr); 3087 3088 __ bind(next); 3089 } 3090 } 3091 3092 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3093 assert(op->crc()->is_single_cpu(), "crc must be register"); 3094 assert(op->val()->is_single_cpu(), "byte value must be register"); 3095 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3096 Register crc = op->crc()->as_register(); 3097 Register val = op->val()->as_register(); 3098 Register res = op->result_opr()->as_register(); 3099 3100 assert_different_registers(val, crc, res); 3101 3102 __ load_const_optimized(res, StubRoutines::crc_table_addr()); 3103 __ kernel_crc32_singleByteReg(crc, val, res, true); 3104 __ z_lgfr(res, crc); 3105 } 3106 3107 #undef __