1 /*
 2  * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
 4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 5  *
 6  * This code is free software; you can redistribute it and/or modify it
 7  * under the terms of the GNU General Public License version 2 only, as
 8  * published by the Free Software Foundation.
 9  *
10  * This code is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * version 2 for more details (a copy is included in the LICENSE file that
14  * accompanied this code).
15  *
16  * You should have received a copy of the GNU General Public License version
17  * 2 along with this work; if not, write to the Free Software Foundation,
18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19  *
20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21  * or visit www.oracle.com if you need additional information or have any
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24  */
25 
26 #ifndef OS_CPU_LINUX_RISCV_ORDERACCESS_LINUX_RISCV_HPP
27 #define OS_CPU_LINUX_RISCV_ORDERACCESS_LINUX_RISCV_HPP
28 
29 // Included in orderAccess.hpp header file.
30 
31 #include "runtime/vm_version.hpp"
32 
33 // Implementation of class OrderAccess.
34 
35 inline void OrderAccess::loadload()   { acquire(); }
36 inline void OrderAccess::storestore() { release(); }
37 inline void OrderAccess::loadstore()  { acquire(); }
38 inline void OrderAccess::storeload()  { fence(); }
39 
40 #define FULL_MEM_BARRIER  __sync_synchronize()
41 #define READ_MEM_BARRIER  __atomic_thread_fence(__ATOMIC_ACQUIRE);
42 #define WRITE_MEM_BARRIER __atomic_thread_fence(__ATOMIC_RELEASE);
43 
44 inline void OrderAccess::acquire() {
45   READ_MEM_BARRIER;
46 }
47 
48 inline void OrderAccess::release() {
49   WRITE_MEM_BARRIER;
50 }
51 
52 inline void OrderAccess::fence() {
53   FULL_MEM_BARRIER;
54 }
55 
56 inline void OrderAccess::cross_modify_fence_impl() {
57   asm volatile("fence.i" : : : "memory");
58   if (UseConservativeFence) {
59     asm volatile("fence ir, ir" : : : "memory");
60   }
61 }
62 
63 #endif // OS_CPU_LINUX_RISCV_ORDERACCESS_LINUX_RISCV_HPP