1 /*
 2  * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
 3  * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
 4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 5  *
 6  * This code is free software; you can redistribute it and/or modify it
 7  * under the terms of the GNU General Public License version 2 only, as
 8  * published by the Free Software Foundation.
 9  *
10  * This code is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13  * version 2 for more details (a copy is included in the LICENSE file that
14  * accompanied this code).
15  *
16  * You should have received a copy of the GNU General Public License version
17  * 2 along with this work; if not, write to the Free Software Foundation,
18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19  *
20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21  * or visit www.oracle.com if you need additional information or have any
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24  */
25 
26 #ifndef OS_CPU_LINUX_RISCV_VM_OS_LINUX_RISCV_HPP
27 #define OS_CPU_LINUX_RISCV_VM_OS_LINUX_RISCV_HPP
28 
29   static void setup_fpu();
30 
31   // Used to register dynamic code cache area with the OS
32   // Note: Currently only used in 64 bit Windows implementations
33   static bool register_code_area(char *low, char *high) { return true; }
34 
35   // Atomically copy 64 bits of data
36   static void atomic_copy64(const volatile void *src, volatile void *dst) {
37     *(jlong *) dst = *(const jlong *) src;
38   }
39 
40   // SYSCALL_RISCV_FLUSH_ICACHE is used to flush instruction cache. The "fence.i" instruction
41   // only work on the current hart, so kernel provides the icache flush syscall to flush icache
42   // on each hart. You can pass a flag to determine a global or local icache flush.
43   static void icache_flush(long int start, long int end)
44   {
45     const int SYSCALL_RISCV_FLUSH_ICACHE = 259;
46     register long int __a7 asm ("a7") = SYSCALL_RISCV_FLUSH_ICACHE;
47     register long int __a0 asm ("a0") = start;
48     register long int __a1 asm ("a1") = end;
49     // the flush can be applied to either all threads or only the current.
50     // 0 means a global icache flush, and the icache flush will be applied
51     // to other harts concurrently executing.
52     register long int __a2 asm ("a2") = 0;
53     __asm__ volatile ("ecall\n\t"
54                       : "+r" (__a0)
55                       : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a7)
56                       : "memory");
57   }
58 
59 #endif // OS_CPU_LINUX_RISCV_VM_OS_LINUX_RISCV_HPP