1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CodeStubs.hpp"
  27 #include "c1/c1_InstructionPrinter.hpp"
  28 #include "c1/c1_LIR.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_ValueStack.hpp"
  31 #include "ci/ciInstance.hpp"
  32 #include "runtime/safepointMechanism.inline.hpp"
  33 #include "runtime/sharedRuntime.hpp"
  34 #include "runtime/vm_version.hpp"
  35 
  36 Register LIR_OprDesc::as_register() const {
  37   return FrameMap::cpu_rnr2reg(cpu_regnr());
  38 }
  39 
  40 Register LIR_OprDesc::as_register_lo() const {
  41   return FrameMap::cpu_rnr2reg(cpu_regnrLo());
  42 }
  43 
  44 Register LIR_OprDesc::as_register_hi() const {
  45   return FrameMap::cpu_rnr2reg(cpu_regnrHi());
  46 }
  47 
  48 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  49 
  50 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
  51   ValueTag tag = type->tag();
  52   switch (tag) {
  53   case metaDataTag : {
  54     ClassConstant* c = type->as_ClassConstant();
  55     if (c != NULL && !c->value()->is_loaded()) {
  56       return LIR_OprFact::metadataConst(NULL);
  57     } else if (c != NULL) {
  58       return LIR_OprFact::metadataConst(c->value()->constant_encoding());
  59     } else {
  60       MethodConstant* m = type->as_MethodConstant();
  61       assert (m != NULL, "not a class or a method?");
  62       return LIR_OprFact::metadataConst(m->value()->constant_encoding());
  63     }
  64   }
  65   case objectTag : {
  66       return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
  67     }
  68   case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
  69   case intTag    : return LIR_OprFact::intConst(type->as_IntConstant()->value());
  70   case floatTag  : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
  71   case longTag   : return LIR_OprFact::longConst(type->as_LongConstant()->value());
  72   case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
  73   default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
  74   }
  75 }
  76 
  77 
  78 //---------------------------------------------------
  79 
  80 
  81 LIR_Address::Scale LIR_Address::scale(BasicType type) {
  82   int elem_size = type2aelembytes(type);
  83   switch (elem_size) {
  84   case 1: return LIR_Address::times_1;
  85   case 2: return LIR_Address::times_2;
  86   case 4: return LIR_Address::times_4;
  87   case 8: return LIR_Address::times_8;
  88   }
  89   ShouldNotReachHere();
  90   return LIR_Address::times_1;
  91 }
  92 
  93 //---------------------------------------------------
  94 
  95 char LIR_OprDesc::type_char(BasicType t) {
  96   switch (t) {
  97     case T_ARRAY:
  98       t = T_OBJECT;
  99     case T_BOOLEAN:
 100     case T_CHAR:
 101     case T_FLOAT:
 102     case T_DOUBLE:
 103     case T_BYTE:
 104     case T_SHORT:
 105     case T_INT:
 106     case T_LONG:
 107     case T_OBJECT:
 108     case T_ADDRESS:
 109     case T_VOID:
 110       return ::type2char(t);
 111     case T_METADATA:
 112       return 'M';
 113     case T_ILLEGAL:
 114       return '?';
 115 
 116     default:
 117       ShouldNotReachHere();
 118       return '?';
 119   }
 120 }
 121 
 122 #ifndef PRODUCT
 123 void LIR_OprDesc::validate_type() const {
 124 
 125 #ifdef ASSERT
 126   if (!is_pointer() && !is_illegal()) {
 127     OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
 128     switch (as_BasicType(type_field())) {
 129     case T_LONG:
 130       assert((kindfield == cpu_register || kindfield == stack_value) &&
 131              size_field() == double_size, "must match");
 132       break;
 133     case T_FLOAT:
 134       // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
 135       assert((kindfield == fpu_register || kindfield == stack_value
 136              ARM_ONLY(|| kindfield == cpu_register)
 137              PPC32_ONLY(|| kindfield == cpu_register) ) &&
 138              size_field() == single_size, "must match");
 139       break;
 140     case T_DOUBLE:
 141       // FP return values can be also in CPU registers on ARM and PPC32 (softfp ABI)
 142       assert((kindfield == fpu_register || kindfield == stack_value
 143              ARM_ONLY(|| kindfield == cpu_register)
 144              PPC32_ONLY(|| kindfield == cpu_register) ) &&
 145              size_field() == double_size, "must match");
 146       break;
 147     case T_BOOLEAN:
 148     case T_CHAR:
 149     case T_BYTE:
 150     case T_SHORT:
 151     case T_INT:
 152     case T_ADDRESS:
 153     case T_OBJECT:
 154     case T_METADATA:
 155     case T_ARRAY:
 156       assert((kindfield == cpu_register || kindfield == stack_value) &&
 157              size_field() == single_size, "must match");
 158       break;
 159 
 160     case T_ILLEGAL:
 161       // XXX TKR also means unknown right now
 162       // assert(is_illegal(), "must match");
 163       break;
 164 
 165     default:
 166       ShouldNotReachHere();
 167     }
 168   }
 169 #endif
 170 
 171 }
 172 #endif // PRODUCT
 173 
 174 
 175 bool LIR_OprDesc::is_oop() const {
 176   if (is_pointer()) {
 177     return pointer()->is_oop_pointer();
 178   } else {
 179     OprType t= type_field();
 180     assert(t != unknown_type, "not set");
 181     return t == object_type;
 182   }
 183 }
 184 
 185 #ifdef RISCV
 186 bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
 187 
 188   if (!(is_register() && opr->is_register())) {
 189     return false;
 190   }
 191 
 192   if (is_single_cpu()) {
 193     Register dst = as_register();
 194     if (opr->is_single_cpu()) {
 195       return dst == opr->as_register();
 196     } else if (opr->is_double_cpu()) {
 197       return dst == opr->as_register_lo();
 198     }
 199   } else if (is_double_cpu()) {
 200     Register dst_lo = as_register_lo();
 201     if (opr->is_single_cpu()) {
 202       return dst_lo == opr->as_register();
 203     } else if (opr->is_double_cpu()) {
 204       return dst_lo == opr->as_register_lo();
 205     }
 206   } else if (is_single_fpu()) {
 207     if (opr->is_single_fpu()) {
 208       return as_float_reg() == opr->as_float_reg();
 209     } else if (opr->is_double_fpu()) {
 210       return as_float_reg() == opr->as_double_reg();
 211     }
 212   } else if (is_double_fpu()) {
 213     if (opr->is_single_fpu()) {
 214       return as_double_reg() == opr->as_float_reg();
 215     }else if (opr->is_double_fpu()) {
 216       return as_double_reg() == opr->as_double_reg();
 217     }
 218   }
 219   return false;
 220 }
 221 #endif // RISCV
 222 
 223 void LIR_Op2::verify() const {
 224 #ifdef ASSERT
 225   switch (code()) {
 226 #ifndef RISCV
 227     case lir_cmove:
 228 #endif
 229     case lir_xchg:
 230       break;
 231 
 232     default:
 233       assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
 234              "can't produce oops from arith");
 235   }
 236 
 237   if (TwoOperandLIRForm) {
 238 
 239 #ifdef ASSERT
 240     bool threeOperandForm = false;
 241 #ifdef S390
 242     // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
 243     threeOperandForm =
 244       code() == lir_shl ||
 245       ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
 246 #endif
 247 #endif
 248 
 249     switch (code()) {
 250     case lir_add:
 251     case lir_sub:
 252     case lir_mul:
 253     case lir_div:
 254     case lir_rem:
 255     case lir_logic_and:
 256     case lir_logic_or:
 257     case lir_logic_xor:
 258     case lir_shl:
 259     case lir_shr:
 260       assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
 261       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 262       break;
 263 
 264     // special handling for lir_ushr because of write barriers
 265     case lir_ushr:
 266       assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
 267       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 268       break;
 269 
 270     default:
 271       break;
 272     }
 273   }
 274 #endif
 275 }
 276 
 277 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond,
 278 #ifdef RISCV
 279                            LIR_Opr left,
 280                            LIR_Opr right,
 281 #endif
 282                            BlockBegin* block)
 283 #ifdef RISCV
 284   : LIR_Op2(lir_branch, cond, left, right, (CodeEmitInfo*)NULL)
 285 #else
 286   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 287   , _cond(cond)
 288 #endif
 289   , _label(block->label())
 290   , _block(block)
 291   , _ublock(NULL)
 292   , _stub(NULL) {
 293 }
 294 
 295 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond,
 296 #ifdef RISCV
 297                            LIR_Opr left,
 298                            LIR_Opr right,
 299 #endif
 300                            CodeStub* stub)
 301 #ifdef RISCV
 302   : LIR_Op2(lir_branch, cond, left, right, (CodeEmitInfo*)NULL)
 303 #else
 304   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 305   , _cond(cond)
 306 #endif
 307   , _label(stub->entry())
 308   , _block(NULL)
 309   , _ublock(NULL)
 310   , _stub(stub) {
 311 }
 312 
 313 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond,
 314 #ifdef RISCV
 315                            LIR_Opr left,
 316                            LIR_Opr right,
 317 #endif
 318                            BlockBegin* block,
 319                            BlockBegin* ublock)
 320 #ifdef RISCV
 321   : LIR_Op2(lir_branch, cond, left, right, (CodeEmitInfo*)NULL)
 322 #else
 323   : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 324   , _cond(cond)
 325 #endif
 326   , _label(block->label())
 327   , _block(block)
 328   , _ublock(ublock)
 329   , _stub(NULL)
 330 {
 331 }
 332 
 333 void LIR_OpBranch::change_block(BlockBegin* b) {
 334   assert(_block != NULL, "must have old block");
 335   assert(_block->label() == label(), "must be equal");
 336 
 337   _block = b;
 338   _label = b->label();
 339 }
 340 
 341 void LIR_OpBranch::change_ublock(BlockBegin* b) {
 342   assert(_ublock != NULL, "must have old block");
 343   _ublock = b;
 344 }
 345 
 346 void LIR_OpBranch::negate_cond() {
 347   switch (cond()) {
 348     case lir_cond_equal:        set_cond(lir_cond_notEqual);     break;
 349     case lir_cond_notEqual:     set_cond(lir_cond_equal);        break;
 350     case lir_cond_less:         set_cond(lir_cond_greaterEqual); break;
 351     case lir_cond_lessEqual:    set_cond(lir_cond_greater);      break;
 352     case lir_cond_greaterEqual: set_cond(lir_cond_less);         break;
 353     case lir_cond_greater:      set_cond(lir_cond_lessEqual);    break;
 354     default: ShouldNotReachHere();
 355   }
 356 }
 357 
 358 
 359 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
 360                                  LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
 361                                  bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
 362                                  CodeStub* stub)
 363 
 364   : LIR_Op(code, result, NULL)
 365   , _object(object)
 366   , _array(LIR_OprFact::illegalOpr)
 367   , _klass(klass)
 368   , _tmp1(tmp1)
 369   , _tmp2(tmp2)
 370   , _tmp3(tmp3)
 371   , _fast_check(fast_check)
 372   , _info_for_patch(info_for_patch)
 373   , _info_for_exception(info_for_exception)
 374   , _stub(stub)
 375   , _profiled_method(NULL)
 376   , _profiled_bci(-1)
 377   , _should_profile(false)
 378 {
 379   if (code == lir_checkcast) {
 380     assert(info_for_exception != NULL, "checkcast throws exceptions");
 381   } else if (code == lir_instanceof) {
 382     assert(info_for_exception == NULL, "instanceof throws no exceptions");
 383   } else {
 384     ShouldNotReachHere();
 385   }
 386 }
 387 
 388 
 389 
 390 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
 391   : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
 392   , _object(object)
 393   , _array(array)
 394   , _klass(NULL)
 395   , _tmp1(tmp1)
 396   , _tmp2(tmp2)
 397   , _tmp3(tmp3)
 398   , _fast_check(false)
 399   , _info_for_patch(NULL)
 400   , _info_for_exception(info_for_exception)
 401   , _stub(NULL)
 402   , _profiled_method(NULL)
 403   , _profiled_bci(-1)
 404   , _should_profile(false)
 405 {
 406   if (code == lir_store_check) {
 407     _stub = new ArrayStoreExceptionStub(object, info_for_exception);
 408     assert(info_for_exception != NULL, "store_check throws exceptions");
 409   } else {
 410     ShouldNotReachHere();
 411   }
 412 }
 413 
 414 
 415 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
 416                                  LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
 417   : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
 418   , _src(src)
 419   , _src_pos(src_pos)
 420   , _dst(dst)
 421   , _dst_pos(dst_pos)
 422   , _length(length)
 423   , _tmp(tmp)
 424   , _expected_type(expected_type)
 425   , _flags(flags) {
 426   _stub = new ArrayCopyStub(this);
 427 }
 428 
 429 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
 430   : LIR_Op(lir_updatecrc32, res, NULL)
 431   , _crc(crc)
 432   , _val(val) {
 433 }
 434 
 435 //-------------------verify--------------------------
 436 
 437 void LIR_Op1::verify() const {
 438   switch(code()) {
 439   case lir_move:
 440     assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
 441     break;
 442   case lir_null_check:
 443     assert(in_opr()->is_register(), "must be");
 444     break;
 445   case lir_return:
 446     assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
 447     break;
 448   default:
 449     break;
 450   }
 451 }
 452 
 453 void LIR_OpRTCall::verify() const {
 454   assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
 455 }
 456 
 457 //-------------------visits--------------------------
 458 
 459 // complete rework of LIR instruction visitor.
 460 // The virtual call for each instruction type is replaced by a big
 461 // switch that adds the operands for each instruction
 462 
 463 void LIR_OpVisitState::visit(LIR_Op* op) {
 464   // copy information from the LIR_Op
 465   reset();
 466   set_op(op);
 467 
 468   switch (op->code()) {
 469 
 470 // LIR_Op0
 471     case lir_fpop_raw:                 // result and info always invalid
 472     case lir_breakpoint:               // result and info always invalid
 473     case lir_membar:                   // result and info always invalid
 474     case lir_membar_acquire:           // result and info always invalid
 475     case lir_membar_release:           // result and info always invalid
 476     case lir_membar_loadload:          // result and info always invalid
 477     case lir_membar_storestore:        // result and info always invalid
 478     case lir_membar_loadstore:         // result and info always invalid
 479     case lir_membar_storeload:         // result and info always invalid
 480     case lir_on_spin_wait:
 481     {
 482       assert(op->as_Op0() != NULL, "must be");
 483       assert(op->_info == NULL, "info not used by this instruction");
 484       assert(op->_result->is_illegal(), "not used");
 485       break;
 486     }
 487 
 488     case lir_nop:                      // may have info, result always invalid
 489     case lir_std_entry:                // may have result, info always invalid
 490     case lir_osr_entry:                // may have result, info always invalid
 491     case lir_get_thread:               // may have result, info always invalid
 492     {
 493       assert(op->as_Op0() != NULL, "must be");
 494       if (op->_info != NULL)           do_info(op->_info);
 495       if (op->_result->is_valid())     do_output(op->_result);
 496       break;
 497     }
 498 
 499 
 500 // LIR_OpLabel
 501     case lir_label:                    // result and info always invalid
 502     {
 503       assert(op->as_OpLabel() != NULL, "must be");
 504       assert(op->_info == NULL, "info not used by this instruction");
 505       assert(op->_result->is_illegal(), "not used");
 506       break;
 507     }
 508 
 509 
 510 // LIR_Op1
 511     case lir_fxch:           // input always valid, result and info always invalid
 512     case lir_fld:            // input always valid, result and info always invalid
 513     case lir_push:           // input always valid, result and info always invalid
 514     case lir_pop:            // input always valid, result and info always invalid
 515     case lir_leal:           // input and result always valid, info always invalid
 516     case lir_monaddr:        // input and result always valid, info always invalid
 517     case lir_null_check:     // input and info always valid, result always invalid
 518     case lir_move:           // input and result always valid, may have info
 519     {
 520       assert(op->as_Op1() != NULL, "must be");
 521       LIR_Op1* op1 = (LIR_Op1*)op;
 522 
 523       if (op1->_info)                  do_info(op1->_info);
 524       if (op1->_opr->is_valid())       do_input(op1->_opr);
 525       if (op1->_result->is_valid())    do_output(op1->_result);
 526 
 527       break;
 528     }
 529 
 530     case lir_return:
 531     {
 532       assert(op->as_OpReturn() != NULL, "must be");
 533       LIR_OpReturn* op_ret = (LIR_OpReturn*)op;
 534 
 535       if (op_ret->_info)               do_info(op_ret->_info);
 536       if (op_ret->_opr->is_valid())    do_input(op_ret->_opr);
 537       if (op_ret->_result->is_valid()) do_output(op_ret->_result);
 538       if (op_ret->stub() != NULL)      do_stub(op_ret->stub());
 539 
 540       break;
 541     }
 542 
 543     case lir_safepoint:
 544     {
 545       assert(op->as_Op1() != NULL, "must be");
 546       LIR_Op1* op1 = (LIR_Op1*)op;
 547 
 548       assert(op1->_info != NULL, "");  do_info(op1->_info);
 549       if (op1->_opr->is_valid())       do_temp(op1->_opr); // safepoints on SPARC need temporary register
 550       assert(op1->_result->is_illegal(), "safepoint does not produce value");
 551 
 552       break;
 553     }
 554 
 555 // LIR_OpConvert;
 556     case lir_convert:        // input and result always valid, info always invalid
 557     {
 558       assert(op->as_OpConvert() != NULL, "must be");
 559       LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
 560 
 561       assert(opConvert->_info == NULL, "must be");
 562       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 563       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 564 #ifdef PPC32
 565       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 566       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 567 #endif
 568       do_stub(opConvert->_stub);
 569 
 570       break;
 571     }
 572 
 573 // LIR_OpBranch;
 574     case lir_branch:                   // may have info, input and result register always invalid
 575     case lir_cond_float_branch:        // may have info, input and result register always invalid
 576     {
 577       assert(op->as_OpBranch() != NULL, "must be");
 578       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 579 
 580 #ifdef RISCV
 581       // lir_branch and lir_cond_float_branch should be LIR_Op2 if arch has no flag register
 582       if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
 583       if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
 584       if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
 585       if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
 586       if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
 587       if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
 588       if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
 589 #endif
 590 
 591       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 592       assert(opBranch->_result->is_illegal(), "not used");
 593       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 594 
 595       break;
 596     }
 597 
 598 
 599 // LIR_OpAllocObj
 600     case lir_alloc_object:
 601     {
 602       assert(op->as_OpAllocObj() != NULL, "must be");
 603       LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
 604 
 605       if (opAllocObj->_info)                     do_info(opAllocObj->_info);
 606       if (opAllocObj->_opr->is_valid()) {        do_input(opAllocObj->_opr);
 607                                                  do_temp(opAllocObj->_opr);
 608                                         }
 609       if (opAllocObj->_tmp1->is_valid())         do_temp(opAllocObj->_tmp1);
 610       if (opAllocObj->_tmp2->is_valid())         do_temp(opAllocObj->_tmp2);
 611       if (opAllocObj->_tmp3->is_valid())         do_temp(opAllocObj->_tmp3);
 612       if (opAllocObj->_tmp4->is_valid())         do_temp(opAllocObj->_tmp4);
 613       if (opAllocObj->_result->is_valid())       do_output(opAllocObj->_result);
 614                                                  do_stub(opAllocObj->_stub);
 615       break;
 616     }
 617 
 618 
 619 // LIR_OpRoundFP;
 620     case lir_roundfp: {
 621       assert(op->as_OpRoundFP() != NULL, "must be");
 622       LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
 623 
 624       assert(op->_info == NULL, "info not used by this instruction");
 625       assert(opRoundFP->_tmp->is_illegal(), "not used");
 626       do_input(opRoundFP->_opr);
 627       do_output(opRoundFP->_result);
 628 
 629       break;
 630     }
 631 
 632 
 633 // LIR_Op2
 634 #ifndef RISCV
 635     case lir_cmp:
 636 #endif
 637     case lir_cmp_l2i:
 638     case lir_ucmp_fd2i:
 639     case lir_cmp_fd2i:
 640     case lir_add:
 641     case lir_sub:
 642     case lir_rem:
 643     case lir_sqrt:
 644     case lir_abs:
 645     case lir_neg:
 646     case lir_logic_and:
 647     case lir_logic_or:
 648     case lir_logic_xor:
 649     case lir_shl:
 650     case lir_shr:
 651     case lir_ushr:
 652     case lir_xadd:
 653     case lir_xchg:
 654     case lir_assert:
 655     {
 656       assert(op->as_Op2() != NULL, "must be");
 657       LIR_Op2* op2 = (LIR_Op2*)op;
 658       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 659              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 660 
 661       if (op2->_info)                     do_info(op2->_info);
 662       if (op2->_opr1->is_valid())         do_input(op2->_opr1);
 663       if (op2->_opr2->is_valid())         do_input(op2->_opr2);
 664       if (op2->_tmp1->is_valid())         do_temp(op2->_tmp1);
 665       if (op2->_result->is_valid())       do_output(op2->_result);
 666       if (op->code() == lir_xchg || op->code() == lir_xadd) {
 667         // on ARM and PPC, return value is loaded first so could
 668         // destroy inputs. On other platforms that implement those
 669         // (x86, sparc), the extra constrainsts are harmless.
 670         if (op2->_opr1->is_valid())       do_temp(op2->_opr1);
 671         if (op2->_opr2->is_valid())       do_temp(op2->_opr2);
 672       }
 673 
 674       break;
 675     }
 676 
 677     // special handling for cmove: right input operand must not be equal
 678     // to the result operand, otherwise the backend fails
 679     case lir_cmove:
 680     {
 681 #ifdef RISCV
 682       // lir_cmove should be LIR_Op4 on riscv64
 683       assert(op->as_Op4() != NULL, "must be");
 684       LIR_Op4* op4 = (LIR_Op4*)op;
 685 
 686       assert(op4->_info == NULL, "must be");
 687       assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_opr3->is_valid() &&
 688              op4->_opr4->is_valid() && op4->_result->is_valid(), "used");
 689 
 690       do_input(op4->_opr1);
 691       do_input(op4->_opr2);
 692       do_input(op4->_opr3);
 693       do_input(op4->_opr4);
 694       if (op4->_tmp1->is_valid())  do_temp(op4->_tmp1);
 695       if (op4->_tmp2->is_valid())  do_temp(op4->_tmp2);
 696       if (op4->_tmp3->is_valid())  do_temp(op4->_tmp3);
 697       if (op4->_tmp4->is_valid())  do_temp(op4->_tmp4);
 698       if (op4->_tmp5->is_valid())  do_temp(op4->_tmp5);
 699       do_output(op4->_result);
 700 #else
 701       assert(op->as_Op2() != NULL, "must be");
 702       LIR_Op2* op2 = (LIR_Op2*)op;
 703 
 704       assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
 705              op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 706       assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
 707 
 708       do_input(op2->_opr1);
 709       do_input(op2->_opr2);
 710       do_temp(op2->_opr2);
 711       do_output(op2->_result);
 712 #endif // RISCV
 713 
 714       break;
 715     }
 716 
 717     // vspecial handling for strict operations: register input operands
 718     // as temp to guarantee that they do not overlap with other
 719     // registers
 720     case lir_mul:
 721     case lir_div:
 722     {
 723       assert(op->as_Op2() != NULL, "must be");
 724       LIR_Op2* op2 = (LIR_Op2*)op;
 725 
 726       assert(op2->_info == NULL, "not used");
 727       assert(op2->_opr1->is_valid(), "used");
 728       assert(op2->_opr2->is_valid(), "used");
 729       assert(op2->_result->is_valid(), "used");
 730       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 731              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 732 
 733       do_input(op2->_opr1); do_temp(op2->_opr1);
 734       do_input(op2->_opr2); do_temp(op2->_opr2);
 735       if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
 736       do_output(op2->_result);
 737 
 738       break;
 739     }
 740 
 741     case lir_throw: {
 742       assert(op->as_Op2() != NULL, "must be");
 743       LIR_Op2* op2 = (LIR_Op2*)op;
 744 
 745       if (op2->_info)                     do_info(op2->_info);
 746       if (op2->_opr1->is_valid())         do_temp(op2->_opr1);
 747       if (op2->_opr2->is_valid())         do_input(op2->_opr2); // exception object is input parameter
 748       assert(op2->_result->is_illegal(), "no result");
 749       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 750              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 751 
 752       break;
 753     }
 754 
 755     case lir_unwind: {
 756       assert(op->as_Op1() != NULL, "must be");
 757       LIR_Op1* op1 = (LIR_Op1*)op;
 758 
 759       assert(op1->_info == NULL, "no info");
 760       assert(op1->_opr->is_valid(), "exception oop");         do_input(op1->_opr);
 761       assert(op1->_result->is_illegal(), "no result");
 762 
 763       break;
 764     }
 765 
 766 // LIR_Op3
 767     case lir_idiv:
 768     case lir_irem: {
 769       assert(op->as_Op3() != NULL, "must be");
 770       LIR_Op3* op3= (LIR_Op3*)op;
 771 
 772       if (op3->_info)                     do_info(op3->_info);
 773       if (op3->_opr1->is_valid())         do_input(op3->_opr1);
 774 
 775       // second operand is input and temp, so ensure that second operand
 776       // and third operand get not the same register
 777       if (op3->_opr2->is_valid())         do_input(op3->_opr2);
 778       if (op3->_opr2->is_valid())         do_temp(op3->_opr2);
 779       if (op3->_opr3->is_valid())         do_temp(op3->_opr3);
 780 
 781       if (op3->_result->is_valid())       do_output(op3->_result);
 782 
 783       break;
 784     }
 785 
 786     case lir_fmad:
 787     case lir_fmaf: {
 788       assert(op->as_Op3() != NULL, "must be");
 789       LIR_Op3* op3= (LIR_Op3*)op;
 790       assert(op3->_info == NULL, "no info");
 791       do_input(op3->_opr1);
 792       do_input(op3->_opr2);
 793       do_input(op3->_opr3);
 794       do_output(op3->_result);
 795       break;
 796     }
 797 
 798 // LIR_OpJavaCall
 799     case lir_static_call:
 800     case lir_optvirtual_call:
 801     case lir_icvirtual_call:
 802     case lir_dynamic_call: {
 803       LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
 804       assert(opJavaCall != NULL, "must be");
 805 
 806       if (opJavaCall->_receiver->is_valid())     do_input(opJavaCall->_receiver);
 807 
 808       // only visit register parameters
 809       int n = opJavaCall->_arguments->length();
 810       for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
 811         if (!opJavaCall->_arguments->at(i)->is_pointer()) {
 812           do_input(*opJavaCall->_arguments->adr_at(i));
 813         }
 814       }
 815 
 816       if (opJavaCall->_info)                     do_info(opJavaCall->_info);
 817       if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
 818           opJavaCall->is_method_handle_invoke()) {
 819         opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
 820         do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
 821       }
 822       do_call();
 823       if (opJavaCall->_result->is_valid())       do_output(opJavaCall->_result);
 824 
 825       break;
 826     }
 827 
 828 
 829 // LIR_OpRTCall
 830     case lir_rtcall: {
 831       assert(op->as_OpRTCall() != NULL, "must be");
 832       LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
 833 
 834       // only visit register parameters
 835       int n = opRTCall->_arguments->length();
 836       for (int i = 0; i < n; i++) {
 837         if (!opRTCall->_arguments->at(i)->is_pointer()) {
 838           do_input(*opRTCall->_arguments->adr_at(i));
 839         }
 840       }
 841       if (opRTCall->_info)                     do_info(opRTCall->_info);
 842       if (opRTCall->_tmp->is_valid())          do_temp(opRTCall->_tmp);
 843       do_call();
 844       if (opRTCall->_result->is_valid())       do_output(opRTCall->_result);
 845 
 846       break;
 847     }
 848 
 849 
 850 // LIR_OpArrayCopy
 851     case lir_arraycopy: {
 852       assert(op->as_OpArrayCopy() != NULL, "must be");
 853       LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
 854 
 855       assert(opArrayCopy->_result->is_illegal(), "unused");
 856       assert(opArrayCopy->_src->is_valid(), "used");          do_input(opArrayCopy->_src);     do_temp(opArrayCopy->_src);
 857       assert(opArrayCopy->_src_pos->is_valid(), "used");      do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
 858       assert(opArrayCopy->_dst->is_valid(), "used");          do_input(opArrayCopy->_dst);     do_temp(opArrayCopy->_dst);
 859       assert(opArrayCopy->_dst_pos->is_valid(), "used");      do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
 860       assert(opArrayCopy->_length->is_valid(), "used");       do_input(opArrayCopy->_length);  do_temp(opArrayCopy->_length);
 861       assert(opArrayCopy->_tmp->is_valid(), "used");          do_temp(opArrayCopy->_tmp);
 862       if (opArrayCopy->_info)                     do_info(opArrayCopy->_info);
 863 
 864       // the implementation of arraycopy always has a call into the runtime
 865       do_call();
 866 
 867       break;
 868     }
 869 
 870 
 871 // LIR_OpUpdateCRC32
 872     case lir_updatecrc32: {
 873       assert(op->as_OpUpdateCRC32() != NULL, "must be");
 874       LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
 875 
 876       assert(opUp->_crc->is_valid(), "used");          do_input(opUp->_crc);     do_temp(opUp->_crc);
 877       assert(opUp->_val->is_valid(), "used");          do_input(opUp->_val);     do_temp(opUp->_val);
 878       assert(opUp->_result->is_valid(), "used");       do_output(opUp->_result);
 879       assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
 880 
 881       break;
 882     }
 883 
 884 
 885 // LIR_OpLock
 886     case lir_lock:
 887     case lir_unlock: {
 888       assert(op->as_OpLock() != NULL, "must be");
 889       LIR_OpLock* opLock = (LIR_OpLock*)op;
 890 
 891       if (opLock->_info)                          do_info(opLock->_info);
 892 
 893       // TODO: check if these operands really have to be temp
 894       // (or if input is sufficient). This may have influence on the oop map!
 895       assert(opLock->_lock->is_valid(), "used");  do_temp(opLock->_lock);
 896       assert(opLock->_hdr->is_valid(),  "used");  do_temp(opLock->_hdr);
 897       assert(opLock->_obj->is_valid(),  "used");  do_temp(opLock->_obj);
 898 
 899       if (opLock->_scratch->is_valid())           do_temp(opLock->_scratch);
 900       assert(opLock->_result->is_illegal(), "unused");
 901 
 902       do_stub(opLock->_stub);
 903 
 904       break;
 905     }
 906 
 907 
 908 // LIR_OpDelay
 909     case lir_delay_slot: {
 910       assert(op->as_OpDelay() != NULL, "must be");
 911       LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
 912 
 913       visit(opDelay->delay_op());
 914       break;
 915     }
 916 
 917 // LIR_OpTypeCheck
 918     case lir_instanceof:
 919     case lir_checkcast:
 920     case lir_store_check: {
 921       assert(op->as_OpTypeCheck() != NULL, "must be");
 922       LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
 923 
 924       if (opTypeCheck->_info_for_exception)       do_info(opTypeCheck->_info_for_exception);
 925       if (opTypeCheck->_info_for_patch)           do_info(opTypeCheck->_info_for_patch);
 926       if (opTypeCheck->_object->is_valid())       do_input(opTypeCheck->_object);
 927       if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
 928         do_temp(opTypeCheck->_object);
 929       }
 930       if (opTypeCheck->_array->is_valid())        do_input(opTypeCheck->_array);
 931       if (opTypeCheck->_tmp1->is_valid())         do_temp(opTypeCheck->_tmp1);
 932       if (opTypeCheck->_tmp2->is_valid())         do_temp(opTypeCheck->_tmp2);
 933       if (opTypeCheck->_tmp3->is_valid())         do_temp(opTypeCheck->_tmp3);
 934       if (opTypeCheck->_result->is_valid())       do_output(opTypeCheck->_result);
 935                                                   do_stub(opTypeCheck->_stub);
 936       break;
 937     }
 938 
 939 // LIR_OpCompareAndSwap
 940     case lir_cas_long:
 941     case lir_cas_obj:
 942     case lir_cas_int: {
 943       assert(op->as_OpCompareAndSwap() != NULL, "must be");
 944       LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
 945 
 946       assert(opCompareAndSwap->_addr->is_valid(),      "used");
 947       assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
 948       assert(opCompareAndSwap->_new_value->is_valid(), "used");
 949       if (opCompareAndSwap->_info)                    do_info(opCompareAndSwap->_info);
 950                                                       do_input(opCompareAndSwap->_addr);
 951                                                       do_temp(opCompareAndSwap->_addr);
 952                                                       do_input(opCompareAndSwap->_cmp_value);
 953                                                       do_temp(opCompareAndSwap->_cmp_value);
 954                                                       do_input(opCompareAndSwap->_new_value);
 955                                                       do_temp(opCompareAndSwap->_new_value);
 956       if (opCompareAndSwap->_tmp1->is_valid())        do_temp(opCompareAndSwap->_tmp1);
 957       if (opCompareAndSwap->_tmp2->is_valid())        do_temp(opCompareAndSwap->_tmp2);
 958       if (opCompareAndSwap->_result->is_valid())      do_output(opCompareAndSwap->_result);
 959 
 960       break;
 961     }
 962 
 963 
 964 // LIR_OpAllocArray;
 965     case lir_alloc_array: {
 966       assert(op->as_OpAllocArray() != NULL, "must be");
 967       LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
 968 
 969       if (opAllocArray->_info)                        do_info(opAllocArray->_info);
 970       if (opAllocArray->_klass->is_valid())           do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
 971       if (opAllocArray->_len->is_valid())             do_input(opAllocArray->_len);   do_temp(opAllocArray->_len);
 972       if (opAllocArray->_tmp1->is_valid())            do_temp(opAllocArray->_tmp1);
 973       if (opAllocArray->_tmp2->is_valid())            do_temp(opAllocArray->_tmp2);
 974       if (opAllocArray->_tmp3->is_valid())            do_temp(opAllocArray->_tmp3);
 975       if (opAllocArray->_tmp4->is_valid())            do_temp(opAllocArray->_tmp4);
 976       if (opAllocArray->_result->is_valid())          do_output(opAllocArray->_result);
 977                                                       do_stub(opAllocArray->_stub);
 978       break;
 979     }
 980 
 981 // LIR_OpProfileCall:
 982     case lir_profile_call: {
 983       assert(op->as_OpProfileCall() != NULL, "must be");
 984       LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
 985 
 986       if (opProfileCall->_recv->is_valid())              do_temp(opProfileCall->_recv);
 987       assert(opProfileCall->_mdo->is_valid(), "used");   do_temp(opProfileCall->_mdo);
 988       assert(opProfileCall->_tmp1->is_valid(), "used");  do_temp(opProfileCall->_tmp1);
 989       break;
 990     }
 991 
 992 // LIR_OpProfileType:
 993     case lir_profile_type: {
 994       assert(op->as_OpProfileType() != NULL, "must be");
 995       LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
 996 
 997       do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
 998       do_input(opProfileType->_obj);
 999       do_temp(opProfileType->_tmp);
1000       break;
1001     }
1002   default:
1003     op->visit(this);
1004   }
1005 }
1006 
1007 void LIR_Op::visit(LIR_OpVisitState* state) {
1008   ShouldNotReachHere();
1009 }
1010 
1011 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1012   if (stub != NULL) {
1013     stub->visit(this);
1014   }
1015 }
1016 
1017 XHandlers* LIR_OpVisitState::all_xhandler() {
1018   XHandlers* result = NULL;
1019 
1020   int i;
1021   for (i = 0; i < info_count(); i++) {
1022     if (info_at(i)->exception_handlers() != NULL) {
1023       result = info_at(i)->exception_handlers();
1024       break;
1025     }
1026   }
1027 
1028 #ifdef ASSERT
1029   for (i = 0; i < info_count(); i++) {
1030     assert(info_at(i)->exception_handlers() == NULL ||
1031            info_at(i)->exception_handlers() == result,
1032            "only one xhandler list allowed per LIR-operation");
1033   }
1034 #endif
1035 
1036   if (result != NULL) {
1037     return result;
1038   } else {
1039     return new XHandlers();
1040   }
1041 
1042   return result;
1043 }
1044 
1045 
1046 #ifdef ASSERT
1047 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1048   visit(op);
1049 
1050   return opr_count(inputMode) == 0 &&
1051          opr_count(outputMode) == 0 &&
1052          opr_count(tempMode) == 0 &&
1053          info_count() == 0 &&
1054          !has_call() &&
1055          !has_slow_case();
1056 }
1057 #endif
1058 
1059 // LIR_OpReturn
1060 LIR_OpReturn::LIR_OpReturn(LIR_Opr opr) :
1061     LIR_Op1(lir_return, opr, (CodeEmitInfo*)NULL /* info */),
1062     _stub(NULL) {
1063   if (VM_Version::supports_stack_watermark_barrier()) {
1064     _stub = new C1SafepointPollStub();
1065   }
1066 }
1067 
1068 //---------------------------------------------------
1069 
1070 
1071 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1072   masm->emit_call(this);
1073 }
1074 
1075 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1076   masm->emit_rtcall(this);
1077 }
1078 
1079 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1080   masm->emit_opLabel(this);
1081 }
1082 
1083 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1084   masm->emit_arraycopy(this);
1085   masm->append_code_stub(stub());
1086 }
1087 
1088 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1089   masm->emit_updatecrc32(this);
1090 }
1091 
1092 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1093   masm->emit_op0(this);
1094 }
1095 
1096 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1097   masm->emit_op1(this);
1098 }
1099 
1100 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1101   masm->emit_alloc_obj(this);
1102   masm->append_code_stub(stub());
1103 }
1104 
1105 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1106   masm->emit_opBranch(this);
1107   if (stub()) {
1108     masm->append_code_stub(stub());
1109   }
1110 }
1111 
1112 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1113   masm->emit_opConvert(this);
1114   if (stub() != NULL) {
1115     masm->append_code_stub(stub());
1116   }
1117 }
1118 
1119 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1120   masm->emit_op2(this);
1121 }
1122 
1123 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1124   masm->emit_alloc_array(this);
1125   masm->append_code_stub(stub());
1126 }
1127 
1128 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1129   masm->emit_opTypeCheck(this);
1130   if (stub()) {
1131     masm->append_code_stub(stub());
1132   }
1133 }
1134 
1135 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1136   masm->emit_compare_and_swap(this);
1137 }
1138 
1139 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1140   masm->emit_op3(this);
1141 }
1142 
1143 #ifdef RISCV
1144 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1145   masm->emit_op4(this);
1146 }
1147 #endif
1148 
1149 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1150   masm->emit_lock(this);
1151   if (stub()) {
1152     masm->append_code_stub(stub());
1153   }
1154 }
1155 
1156 #ifdef ASSERT
1157 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1158   masm->emit_assert(this);
1159 }
1160 #endif
1161 
1162 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1163   masm->emit_delay(this);
1164 }
1165 
1166 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1167   masm->emit_profile_call(this);
1168 }
1169 
1170 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1171   masm->emit_profile_type(this);
1172 }
1173 
1174 // LIR_List
1175 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1176   : _operations(8)
1177   , _compilation(compilation)
1178 #ifndef PRODUCT
1179   , _block(block)
1180 #endif
1181 #ifdef ASSERT
1182   , _file(NULL)
1183   , _line(0)
1184 #endif
1185 { }
1186 
1187 
1188 #ifdef ASSERT
1189 void LIR_List::set_file_and_line(const char * file, int line) {
1190   const char * f = strrchr(file, '/');
1191   if (f == NULL) f = strrchr(file, '\\');
1192   if (f == NULL) {
1193     f = file;
1194   } else {
1195     f++;
1196   }
1197   _file = f;
1198   _line = line;
1199 }
1200 #endif
1201 
1202 
1203 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1204   assert(this == buffer->lir_list(), "wrong lir list");
1205   const int n = _operations.length();
1206 
1207   if (buffer->number_of_ops() > 0) {
1208     // increase size of instructions list
1209     _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1210     // insert ops from buffer into instructions list
1211     int op_index = buffer->number_of_ops() - 1;
1212     int ip_index = buffer->number_of_insertion_points() - 1;
1213     int from_index = n - 1;
1214     int to_index = _operations.length() - 1;
1215     for (; ip_index >= 0; ip_index --) {
1216       int index = buffer->index_at(ip_index);
1217       // make room after insertion point
1218       while (index < from_index) {
1219         _operations.at_put(to_index --, _operations.at(from_index --));
1220       }
1221       // insert ops from buffer
1222       for (int i = buffer->count_at(ip_index); i > 0; i --) {
1223         _operations.at_put(to_index --, buffer->op_at(op_index --));
1224       }
1225     }
1226   }
1227 
1228   buffer->finish();
1229 }
1230 
1231 
1232 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1233   assert(reg->type() == T_OBJECT, "bad reg");
1234   append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o),  reg, T_OBJECT, lir_patch_normal, info));
1235 }
1236 
1237 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1238   assert(reg->type() == T_METADATA, "bad reg");
1239   append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1240 }
1241 
1242 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1243   append(new LIR_Op1(
1244             lir_move,
1245             LIR_OprFact::address(addr),
1246             src,
1247             addr->type(),
1248             patch_code,
1249             info));
1250 }
1251 
1252 
1253 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1254   append(new LIR_Op1(
1255             lir_move,
1256             LIR_OprFact::address(address),
1257             dst,
1258             address->type(),
1259             patch_code,
1260             info, lir_move_volatile));
1261 }
1262 
1263 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1264   append(new LIR_Op1(
1265             lir_move,
1266             LIR_OprFact::address(new LIR_Address(base, offset, type)),
1267             dst,
1268             type,
1269             patch_code,
1270             info, lir_move_volatile));
1271 }
1272 
1273 
1274 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1275   append(new LIR_Op1(
1276             lir_move,
1277             LIR_OprFact::intConst(v),
1278             LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1279             type,
1280             patch_code,
1281             info));
1282 }
1283 
1284 
1285 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1286   append(new LIR_Op1(
1287             lir_move,
1288             LIR_OprFact::oopConst(o),
1289             LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1290             type,
1291             patch_code,
1292             info));
1293 }
1294 
1295 
1296 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1297   append(new LIR_Op1(
1298             lir_move,
1299             src,
1300             LIR_OprFact::address(addr),
1301             addr->type(),
1302             patch_code,
1303             info));
1304 }
1305 
1306 
1307 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1308   append(new LIR_Op1(
1309             lir_move,
1310             src,
1311             LIR_OprFact::address(addr),
1312             addr->type(),
1313             patch_code,
1314             info,
1315             lir_move_volatile));
1316 }
1317 
1318 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1319   append(new LIR_Op1(
1320             lir_move,
1321             src,
1322             LIR_OprFact::address(new LIR_Address(base, offset, type)),
1323             type,
1324             patch_code,
1325             info, lir_move_volatile));
1326 }
1327 
1328 
1329 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1330   append(new LIR_Op3(
1331                     lir_idiv,
1332                     left,
1333                     right,
1334                     tmp,
1335                     res,
1336                     info));
1337 }
1338 
1339 
1340 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1341   append(new LIR_Op3(
1342                     lir_idiv,
1343                     left,
1344                     LIR_OprFact::intConst(right),
1345                     tmp,
1346                     res,
1347                     info));
1348 }
1349 
1350 
1351 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1352   append(new LIR_Op3(
1353                     lir_irem,
1354                     left,
1355                     right,
1356                     tmp,
1357                     res,
1358                     info));
1359 }
1360 
1361 
1362 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1363   append(new LIR_Op3(
1364                     lir_irem,
1365                     left,
1366                     LIR_OprFact::intConst(right),
1367                     tmp,
1368                     res,
1369                     info));
1370 }
1371 
1372 
1373 #ifndef RISCV
1374 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1375   append(new LIR_Op2(
1376                     lir_cmp,
1377                     condition,
1378                     LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1379                     LIR_OprFact::intConst(c),
1380                     info));
1381 }
1382 
1383 
1384 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1385   append(new LIR_Op2(
1386                     lir_cmp,
1387                     condition,
1388                     reg,
1389                     LIR_OprFact::address(addr),
1390                     info));
1391 }
1392 #endif
1393 
1394 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1395                                int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1396   append(new LIR_OpAllocObj(
1397                            klass,
1398                            dst,
1399                            t1,
1400                            t2,
1401                            t3,
1402                            t4,
1403                            header_size,
1404                            object_size,
1405                            init_check,
1406                            stub));
1407 }
1408 
1409 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1410   append(new LIR_OpAllocArray(
1411                            klass,
1412                            len,
1413                            dst,
1414                            t1,
1415                            t2,
1416                            t3,
1417                            t4,
1418                            type,
1419                            stub));
1420 }
1421 
1422 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1423  append(new LIR_Op2(
1424                     lir_shl,
1425                     value,
1426                     count,
1427                     dst,
1428                     tmp));
1429 }
1430 
1431 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1432  append(new LIR_Op2(
1433                     lir_shr,
1434                     value,
1435                     count,
1436                     dst,
1437                     tmp));
1438 }
1439 
1440 
1441 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1442  append(new LIR_Op2(
1443                     lir_ushr,
1444                     value,
1445                     count,
1446                     dst,
1447                     tmp));
1448 }
1449 
1450 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1451   append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1452                      left,
1453                      right,
1454                      dst));
1455 }
1456 
1457 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1458   append(new LIR_OpLock(
1459                     lir_lock,
1460                     hdr,
1461                     obj,
1462                     lock,
1463                     scratch,
1464                     stub,
1465                     info));
1466 }
1467 
1468 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1469   append(new LIR_OpLock(
1470                     lir_unlock,
1471                     hdr,
1472                     obj,
1473                     lock,
1474                     scratch,
1475                     stub,
1476                     NULL));
1477 }
1478 
1479 
1480 void check_LIR() {
1481   // cannot do the proper checking as PRODUCT and other modes return different results
1482   // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1483 }
1484 
1485 
1486 
1487 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1488                           LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1489                           CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1490                           ciMethod* profiled_method, int profiled_bci) {
1491   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1492                                            tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1493   if (profiled_method != NULL) {
1494     c->set_profiled_method(profiled_method);
1495     c->set_profiled_bci(profiled_bci);
1496     c->set_should_profile(true);
1497   }
1498   append(c);
1499 }
1500 
1501 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1502   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1503   if (profiled_method != NULL) {
1504     c->set_profiled_method(profiled_method);
1505     c->set_profiled_bci(profiled_bci);
1506     c->set_should_profile(true);
1507   }
1508   append(c);
1509 }
1510 
1511 
1512 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1513                            CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1514   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1515   if (profiled_method != NULL) {
1516     c->set_profiled_method(profiled_method);
1517     c->set_profiled_bci(profiled_bci);
1518     c->set_should_profile(true);
1519   }
1520   append(c);
1521 }
1522 
1523 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1524   if (deoptimize_on_null) {
1525     // Emit an explicit null check and deoptimize if opr is null
1526     CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none);
1527     cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1528     branch(lir_cond_equal,
1529 #ifdef RISCV
1530            opr,
1531            LIR_OprFact::oopConst(NULL),
1532 #endif
1533            deopt);
1534   } else {
1535     // Emit an implicit null check
1536     append(new LIR_Op1(lir_null_check, opr, info));
1537   }
1538 }
1539 
1540 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1541                         LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1542   append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1543 }
1544 
1545 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1546                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1547   append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1548 }
1549 
1550 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1551                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1552   append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1553 }
1554 
1555 
1556 #ifdef PRODUCT
1557 
1558 void print_LIR(BlockList* blocks) {
1559 }
1560 
1561 #else
1562 // LIR_OprDesc
1563 void LIR_OprDesc::print() const {
1564   print(tty);
1565 }
1566 
1567 void LIR_OprDesc::print(outputStream* out) const {
1568   if (is_illegal()) {
1569     return;
1570   }
1571 
1572   out->print("[");
1573   if (is_pointer()) {
1574     pointer()->print_value_on(out);
1575   } else if (is_single_stack()) {
1576     out->print("stack:%d", single_stack_ix());
1577   } else if (is_double_stack()) {
1578     out->print("dbl_stack:%d",double_stack_ix());
1579   } else if (is_virtual()) {
1580     out->print("R%d", vreg_number());
1581   } else if (is_single_cpu()) {
1582     out->print("%s", as_register()->name());
1583   } else if (is_double_cpu()) {
1584     out->print("%s", as_register_hi()->name());
1585     out->print("%s", as_register_lo()->name());
1586 #if defined(X86)
1587   } else if (is_single_xmm()) {
1588     out->print("%s", as_xmm_float_reg()->name());
1589   } else if (is_double_xmm()) {
1590     out->print("%s", as_xmm_double_reg()->name());
1591   } else if (is_single_fpu()) {
1592     out->print("fpu%d", fpu_regnr());
1593   } else if (is_double_fpu()) {
1594     out->print("fpu%d", fpu_regnrLo());
1595 #elif defined(AARCH64)
1596   } else if (is_single_fpu()) {
1597     out->print("fpu%d", fpu_regnr());
1598   } else if (is_double_fpu()) {
1599     out->print("fpu%d", fpu_regnrLo());
1600 #elif defined(ARM)
1601   } else if (is_single_fpu()) {
1602     out->print("s%d", fpu_regnr());
1603   } else if (is_double_fpu()) {
1604     out->print("d%d", fpu_regnrLo() >> 1);
1605 #else
1606   } else if (is_single_fpu()) {
1607     out->print("%s", as_float_reg()->name());
1608   } else if (is_double_fpu()) {
1609     out->print("%s", as_double_reg()->name());
1610 #endif
1611 
1612   } else if (is_illegal()) {
1613     out->print("-");
1614   } else {
1615     out->print("Unknown Operand");
1616   }
1617   if (!is_illegal()) {
1618     out->print("|%c", type_char());
1619   }
1620   if (is_register() && is_last_use()) {
1621     out->print("(last_use)");
1622   }
1623   out->print("]");
1624 }
1625 
1626 
1627 // LIR_Address
1628 void LIR_Const::print_value_on(outputStream* out) const {
1629   switch (type()) {
1630     case T_ADDRESS:out->print("address:%d",as_jint());          break;
1631     case T_INT:    out->print("int:%d",   as_jint());           break;
1632     case T_LONG:   out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1633     case T_FLOAT:  out->print("flt:%f",   as_jfloat());         break;
1634     case T_DOUBLE: out->print("dbl:%f",   as_jdouble());        break;
1635     case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject()));        break;
1636     case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1637     default:       out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1638   }
1639 }
1640 
1641 // LIR_Address
1642 void LIR_Address::print_value_on(outputStream* out) const {
1643   out->print("Base:"); _base->print(out);
1644   if (!_index->is_illegal()) {
1645     out->print(" Index:"); _index->print(out);
1646     switch (scale()) {
1647     case times_1: break;
1648     case times_2: out->print(" * 2"); break;
1649     case times_4: out->print(" * 4"); break;
1650     case times_8: out->print(" * 8"); break;
1651     }
1652   }
1653   out->print(" Disp: " INTX_FORMAT, _disp);
1654 }
1655 
1656 // debug output of block header without InstructionPrinter
1657 //       (because phi functions are not necessary for LIR)
1658 static void print_block(BlockBegin* x) {
1659   // print block id
1660   BlockEnd* end = x->end();
1661   tty->print("B%d ", x->block_id());
1662 
1663   // print flags
1664   if (x->is_set(BlockBegin::std_entry_flag))               tty->print("std ");
1665   if (x->is_set(BlockBegin::osr_entry_flag))               tty->print("osr ");
1666   if (x->is_set(BlockBegin::exception_entry_flag))         tty->print("ex ");
1667   if (x->is_set(BlockBegin::subroutine_entry_flag))        tty->print("jsr ");
1668   if (x->is_set(BlockBegin::backward_branch_target_flag))  tty->print("bb ");
1669   if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1670   if (x->is_set(BlockBegin::linear_scan_loop_end_flag))    tty->print("le ");
1671 
1672   // print block bci range
1673   tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1674 
1675   // print predecessors and successors
1676   if (x->number_of_preds() > 0) {
1677     tty->print("preds: ");
1678     for (int i = 0; i < x->number_of_preds(); i ++) {
1679       tty->print("B%d ", x->pred_at(i)->block_id());
1680     }
1681   }
1682 
1683   if (x->number_of_sux() > 0) {
1684     tty->print("sux: ");
1685     for (int i = 0; i < x->number_of_sux(); i ++) {
1686       tty->print("B%d ", x->sux_at(i)->block_id());
1687     }
1688   }
1689 
1690   // print exception handlers
1691   if (x->number_of_exception_handlers() > 0) {
1692     tty->print("xhandler: ");
1693     for (int i = 0; i < x->number_of_exception_handlers();  i++) {
1694       tty->print("B%d ", x->exception_handler_at(i)->block_id());
1695     }
1696   }
1697 
1698   tty->cr();
1699 }
1700 
1701 void print_LIR(BlockList* blocks) {
1702   tty->print_cr("LIR:");
1703   int i;
1704   for (i = 0; i < blocks->length(); i++) {
1705     BlockBegin* bb = blocks->at(i);
1706     print_block(bb);
1707     tty->print("__id_Instruction___________________________________________"); tty->cr();
1708     bb->lir()->print_instructions();
1709   }
1710 }
1711 
1712 void LIR_List::print_instructions() {
1713   for (int i = 0; i < _operations.length(); i++) {
1714     _operations.at(i)->print(); tty->cr();
1715   }
1716   tty->cr();
1717 }
1718 
1719 // LIR_Ops printing routines
1720 // LIR_Op
1721 void LIR_Op::print_on(outputStream* out) const {
1722   if (id() != -1 || PrintCFGToFile) {
1723     out->print("%4d ", id());
1724   } else {
1725     out->print("     ");
1726   }
1727   out->print("%s ", name());
1728   print_instr(out);
1729   if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1730 #ifdef ASSERT
1731   if (Verbose && _file != NULL) {
1732     out->print(" (%s:%d)", _file, _line);
1733   }
1734 #endif
1735 }
1736 
1737 const char * LIR_Op::name() const {
1738   const char* s = NULL;
1739   switch(code()) {
1740      // LIR_Op0
1741      case lir_membar:                s = "membar";        break;
1742      case lir_membar_acquire:        s = "membar_acquire"; break;
1743      case lir_membar_release:        s = "membar_release"; break;
1744      case lir_membar_loadload:       s = "membar_loadload";   break;
1745      case lir_membar_storestore:     s = "membar_storestore"; break;
1746      case lir_membar_loadstore:      s = "membar_loadstore";  break;
1747      case lir_membar_storeload:      s = "membar_storeload";  break;
1748      case lir_label:                 s = "label";         break;
1749      case lir_nop:                   s = "nop";           break;
1750      case lir_on_spin_wait:          s = "on_spin_wait";  break;
1751      case lir_std_entry:             s = "std_entry";     break;
1752      case lir_osr_entry:             s = "osr_entry";     break;
1753      case lir_fpop_raw:              s = "fpop_raw";      break;
1754      case lir_breakpoint:            s = "breakpoint";    break;
1755      case lir_get_thread:            s = "get_thread";    break;
1756      // LIR_Op1
1757      case lir_fxch:                  s = "fxch";          break;
1758      case lir_fld:                   s = "fld";           break;
1759      case lir_push:                  s = "push";          break;
1760      case lir_pop:                   s = "pop";           break;
1761      case lir_null_check:            s = "null_check";    break;
1762      case lir_return:                s = "return";        break;
1763      case lir_safepoint:             s = "safepoint";     break;
1764      case lir_leal:                  s = "leal";          break;
1765      case lir_branch:                s = "branch";        break;
1766      case lir_cond_float_branch:     s = "flt_cond_br";   break;
1767      case lir_move:                  s = "move";          break;
1768      case lir_roundfp:               s = "roundfp";       break;
1769      case lir_rtcall:                s = "rtcall";        break;
1770      case lir_throw:                 s = "throw";         break;
1771      case lir_unwind:                s = "unwind";        break;
1772      case lir_convert:               s = "convert";       break;
1773      case lir_alloc_object:          s = "alloc_obj";     break;
1774      case lir_monaddr:               s = "mon_addr";      break;
1775      // LIR_Op2
1776 #ifndef RISCV
1777      case lir_cmp:                   s = "cmp";           break;
1778 #endif
1779      case lir_cmp_l2i:               s = "cmp_l2i";       break;
1780      case lir_ucmp_fd2i:             s = "ucomp_fd2i";    break;
1781      case lir_cmp_fd2i:              s = "comp_fd2i";     break;
1782      // lir_cmove is LIR_Op4 on riscv64
1783      case lir_cmove:                 s = "cmove";         break;
1784      case lir_add:                   s = "add";           break;
1785      case lir_sub:                   s = "sub";           break;
1786      case lir_mul:                   s = "mul";           break;
1787      case lir_div:                   s = "div";           break;
1788      case lir_rem:                   s = "rem";           break;
1789      case lir_abs:                   s = "abs";           break;
1790      case lir_neg:                   s = "neg";           break;
1791      case lir_sqrt:                  s = "sqrt";          break;
1792      case lir_logic_and:             s = "logic_and";     break;
1793      case lir_logic_or:              s = "logic_or";      break;
1794      case lir_logic_xor:             s = "logic_xor";     break;
1795      case lir_shl:                   s = "shift_left";    break;
1796      case lir_shr:                   s = "shift_right";   break;
1797      case lir_ushr:                  s = "ushift_right";  break;
1798      case lir_alloc_array:           s = "alloc_array";   break;
1799      case lir_xadd:                  s = "xadd";          break;
1800      case lir_xchg:                  s = "xchg";          break;
1801      // LIR_Op3
1802      case lir_idiv:                  s = "idiv";          break;
1803      case lir_irem:                  s = "irem";          break;
1804      case lir_fmad:                  s = "fmad";          break;
1805      case lir_fmaf:                  s = "fmaf";          break;
1806      // LIR_OpJavaCall
1807      case lir_static_call:           s = "static";        break;
1808      case lir_optvirtual_call:       s = "optvirtual";    break;
1809      case lir_icvirtual_call:        s = "icvirtual";     break;
1810      case lir_dynamic_call:          s = "dynamic";       break;
1811      // LIR_OpArrayCopy
1812      case lir_arraycopy:             s = "arraycopy";     break;
1813      // LIR_OpUpdateCRC32
1814      case lir_updatecrc32:           s = "updatecrc32";   break;
1815      // LIR_OpLock
1816      case lir_lock:                  s = "lock";          break;
1817      case lir_unlock:                s = "unlock";        break;
1818      // LIR_OpDelay
1819      case lir_delay_slot:            s = "delay";         break;
1820      // LIR_OpTypeCheck
1821      case lir_instanceof:            s = "instanceof";    break;
1822      case lir_checkcast:             s = "checkcast";     break;
1823      case lir_store_check:           s = "store_check";   break;
1824      // LIR_OpCompareAndSwap
1825      case lir_cas_long:              s = "cas_long";      break;
1826      case lir_cas_obj:               s = "cas_obj";      break;
1827      case lir_cas_int:               s = "cas_int";      break;
1828      // LIR_OpProfileCall
1829      case lir_profile_call:          s = "profile_call";  break;
1830      // LIR_OpProfileType
1831      case lir_profile_type:          s = "profile_type";  break;
1832      // LIR_OpAssert
1833 #ifdef ASSERT
1834      case lir_assert:                s = "assert";        break;
1835 #endif
1836      case lir_none:                  ShouldNotReachHere();break;
1837     default:                         s = "illegal_op";    break;
1838   }
1839   return s;
1840 }
1841 
1842 // LIR_OpJavaCall
1843 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1844   out->print("call: ");
1845   out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1846   if (receiver()->is_valid()) {
1847     out->print(" [recv: ");   receiver()->print(out);   out->print("]");
1848   }
1849   if (result_opr()->is_valid()) {
1850     out->print(" [result: "); result_opr()->print(out); out->print("]");
1851   }
1852 }
1853 
1854 // LIR_OpLabel
1855 void LIR_OpLabel::print_instr(outputStream* out) const {
1856   out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1857 }
1858 
1859 // LIR_OpArrayCopy
1860 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1861   src()->print(out);     out->print(" ");
1862   src_pos()->print(out); out->print(" ");
1863   dst()->print(out);     out->print(" ");
1864   dst_pos()->print(out); out->print(" ");
1865   length()->print(out);  out->print(" ");
1866   tmp()->print(out);     out->print(" ");
1867 }
1868 
1869 // LIR_OpUpdateCRC32
1870 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1871   crc()->print(out);     out->print(" ");
1872   val()->print(out);     out->print(" ");
1873   result_opr()->print(out); out->print(" ");
1874 }
1875 
1876 // LIR_OpCompareAndSwap
1877 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1878   addr()->print(out);      out->print(" ");
1879   cmp_value()->print(out); out->print(" ");
1880   new_value()->print(out); out->print(" ");
1881   tmp1()->print(out);      out->print(" ");
1882   tmp2()->print(out);      out->print(" ");
1883 
1884 }
1885 
1886 // LIR_Op0
1887 void LIR_Op0::print_instr(outputStream* out) const {
1888   result_opr()->print(out);
1889 }
1890 
1891 // LIR_Op1
1892 const char * LIR_Op1::name() const {
1893   if (code() == lir_move) {
1894     switch (move_kind()) {
1895     case lir_move_normal:
1896       return "move";
1897     case lir_move_volatile:
1898       return "volatile_move";
1899     case lir_move_wide:
1900       return "wide_move";
1901     default:
1902       ShouldNotReachHere();
1903     return "illegal_op";
1904     }
1905   } else {
1906     return LIR_Op::name();
1907   }
1908 }
1909 
1910 
1911 void LIR_Op1::print_instr(outputStream* out) const {
1912   _opr->print(out);         out->print(" ");
1913   result_opr()->print(out); out->print(" ");
1914   print_patch_code(out, patch_code());
1915 }
1916 
1917 
1918 // LIR_Op1
1919 void LIR_OpRTCall::print_instr(outputStream* out) const {
1920   intx a = (intx)addr();
1921   out->print("%s", Runtime1::name_for_address(addr()));
1922   out->print(" ");
1923   tmp()->print(out);
1924 }
1925 
1926 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1927   switch(code) {
1928     case lir_patch_none:                                 break;
1929     case lir_patch_low:    out->print("[patch_low]");    break;
1930     case lir_patch_high:   out->print("[patch_high]");   break;
1931     case lir_patch_normal: out->print("[patch_normal]"); break;
1932     default: ShouldNotReachHere();
1933   }
1934 }
1935 
1936 // LIR_OpBranch
1937 void LIR_OpBranch::print_instr(outputStream* out) const {
1938   print_condition(out, cond());             out->print(" ");
1939 #ifdef RISCV
1940   in_opr1()->print(out); out->print(" ");
1941   in_opr2()->print(out); out->print(" ");
1942 #endif
1943   if (block() != NULL) {
1944     out->print("[B%d] ", block()->block_id());
1945   } else if (stub() != NULL) {
1946     out->print("[");
1947     stub()->print_name(out);
1948     out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1949     if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1950   } else {
1951     out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1952   }
1953   if (ublock() != NULL) {
1954     out->print("unordered: [B%d] ", ublock()->block_id());
1955   }
1956 }
1957 
1958 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1959   switch(cond) {
1960     case lir_cond_equal:           out->print("[EQ]");      break;
1961     case lir_cond_notEqual:        out->print("[NE]");      break;
1962     case lir_cond_less:            out->print("[LT]");      break;
1963     case lir_cond_lessEqual:       out->print("[LE]");      break;
1964     case lir_cond_greaterEqual:    out->print("[GE]");      break;
1965     case lir_cond_greater:         out->print("[GT]");      break;
1966     case lir_cond_belowEqual:      out->print("[BE]");      break;
1967     case lir_cond_aboveEqual:      out->print("[AE]");      break;
1968     case lir_cond_always:          out->print("[AL]");      break;
1969     default:                       out->print("[%d]",cond); break;
1970   }
1971 }
1972 
1973 // LIR_OpConvert
1974 void LIR_OpConvert::print_instr(outputStream* out) const {
1975   print_bytecode(out, bytecode());
1976   in_opr()->print(out);                  out->print(" ");
1977   result_opr()->print(out);              out->print(" ");
1978 #ifdef PPC32
1979   if(tmp1()->is_valid()) {
1980     tmp1()->print(out); out->print(" ");
1981     tmp2()->print(out); out->print(" ");
1982   }
1983 #endif
1984 }
1985 
1986 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1987   switch(code) {
1988     case Bytecodes::_d2f: out->print("[d2f] "); break;
1989     case Bytecodes::_d2i: out->print("[d2i] "); break;
1990     case Bytecodes::_d2l: out->print("[d2l] "); break;
1991     case Bytecodes::_f2d: out->print("[f2d] "); break;
1992     case Bytecodes::_f2i: out->print("[f2i] "); break;
1993     case Bytecodes::_f2l: out->print("[f2l] "); break;
1994     case Bytecodes::_i2b: out->print("[i2b] "); break;
1995     case Bytecodes::_i2c: out->print("[i2c] "); break;
1996     case Bytecodes::_i2d: out->print("[i2d] "); break;
1997     case Bytecodes::_i2f: out->print("[i2f] "); break;
1998     case Bytecodes::_i2l: out->print("[i2l] "); break;
1999     case Bytecodes::_i2s: out->print("[i2s] "); break;
2000     case Bytecodes::_l2i: out->print("[l2i] "); break;
2001     case Bytecodes::_l2f: out->print("[l2f] "); break;
2002     case Bytecodes::_l2d: out->print("[l2d] "); break;
2003     default:
2004       out->print("[?%d]",code);
2005     break;
2006   }
2007 }
2008 
2009 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2010   klass()->print(out);                      out->print(" ");
2011   obj()->print(out);                        out->print(" ");
2012   tmp1()->print(out);                       out->print(" ");
2013   tmp2()->print(out);                       out->print(" ");
2014   tmp3()->print(out);                       out->print(" ");
2015   tmp4()->print(out);                       out->print(" ");
2016   out->print("[hdr:%d]", header_size()); out->print(" ");
2017   out->print("[obj:%d]", object_size()); out->print(" ");
2018   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2019 }
2020 
2021 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2022   _opr->print(out);         out->print(" ");
2023   tmp()->print(out);        out->print(" ");
2024   result_opr()->print(out); out->print(" ");
2025 }
2026 
2027 // LIR_Op2
2028 void LIR_Op2::print_instr(outputStream* out) const {
2029 #ifdef RISCV
2030   if (code() == lir_branch || code() == lir_cond_float_branch) {
2031 #else
2032   if (code() == lir_cmove || code() == lir_cmp) {
2033 #endif
2034     print_condition(out, condition());         out->print(" ");
2035   }
2036   in_opr1()->print(out);    out->print(" ");
2037   in_opr2()->print(out);    out->print(" ");
2038   if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out);    out->print(" "); }
2039   if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out);    out->print(" "); }
2040   if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out);    out->print(" "); }
2041   if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out);    out->print(" "); }
2042   if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out);    out->print(" "); }
2043   result_opr()->print(out);
2044 }
2045 
2046 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2047   klass()->print(out);                   out->print(" ");
2048   len()->print(out);                     out->print(" ");
2049   obj()->print(out);                     out->print(" ");
2050   tmp1()->print(out);                    out->print(" ");
2051   tmp2()->print(out);                    out->print(" ");
2052   tmp3()->print(out);                    out->print(" ");
2053   tmp4()->print(out);                    out->print(" ");
2054   out->print("[type:0x%x]", type());     out->print(" ");
2055   out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2056 }
2057 
2058 
2059 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2060   object()->print(out);                  out->print(" ");
2061   if (code() == lir_store_check) {
2062     array()->print(out);                 out->print(" ");
2063   }
2064   if (code() != lir_store_check) {
2065     klass()->print_name_on(out);         out->print(" ");
2066     if (fast_check())                 out->print("fast_check ");
2067   }
2068   tmp1()->print(out);                    out->print(" ");
2069   tmp2()->print(out);                    out->print(" ");
2070   tmp3()->print(out);                    out->print(" ");
2071   result_opr()->print(out);              out->print(" ");
2072   if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2073 }
2074 
2075 
2076 // LIR_Op3
2077 void LIR_Op3::print_instr(outputStream* out) const {
2078   in_opr1()->print(out);    out->print(" ");
2079   in_opr2()->print(out);    out->print(" ");
2080   in_opr3()->print(out);    out->print(" ");
2081   result_opr()->print(out);
2082 }
2083 
2084 #ifdef RISCV
2085 // LIR_Op4
2086 void LIR_Op4::print_instr(outputStream* out) const {
2087   print_condition(out, cond()); out->print(" ");
2088   in_opr1()->print(out);        out->print(" ");
2089   in_opr2()->print(out);        out->print(" ");
2090   in_opr3()->print(out);        out->print(" ");
2091   in_opr4()->print(out);        out->print(" ");
2092   result_opr()->print(out);
2093 }
2094 #endif // RISCV
2095 
2096 void LIR_OpLock::print_instr(outputStream* out) const {
2097   hdr_opr()->print(out);   out->print(" ");
2098   obj_opr()->print(out);   out->print(" ");
2099   lock_opr()->print(out);  out->print(" ");
2100   if (_scratch->is_valid()) {
2101     _scratch->print(out);  out->print(" ");
2102   }
2103   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2104 }
2105 
2106 #ifdef ASSERT
2107 void LIR_OpAssert::print_instr(outputStream* out) const {
2108   print_condition(out, condition()); out->print(" ");
2109   in_opr1()->print(out);             out->print(" ");
2110   in_opr2()->print(out);             out->print(", \"");
2111   out->print("%s", msg());          out->print("\"");
2112 }
2113 #endif
2114 
2115 
2116 void LIR_OpDelay::print_instr(outputStream* out) const {
2117   _op->print_on(out);
2118 }
2119 
2120 
2121 // LIR_OpProfileCall
2122 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2123   profiled_method()->name()->print_symbol_on(out);
2124   out->print(".");
2125   profiled_method()->holder()->name()->print_symbol_on(out);
2126   out->print(" @ %d ", profiled_bci());
2127   mdo()->print(out);           out->print(" ");
2128   recv()->print(out);          out->print(" ");
2129   tmp1()->print(out);          out->print(" ");
2130 }
2131 
2132 // LIR_OpProfileType
2133 void LIR_OpProfileType::print_instr(outputStream* out) const {
2134   out->print("exact = ");
2135   if  (exact_klass() == NULL) {
2136     out->print("unknown");
2137   } else {
2138     exact_klass()->print_name_on(out);
2139   }
2140   out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2141   out->print(" ");
2142   mdp()->print(out);          out->print(" ");
2143   obj()->print(out);          out->print(" ");
2144   tmp()->print(out);          out->print(" ");
2145 }
2146 
2147 #endif // PRODUCT
2148 
2149 // Implementation of LIR_InsertionBuffer
2150 
2151 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2152   assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2153 
2154   int i = number_of_insertion_points() - 1;
2155   if (i < 0 || index_at(i) < index) {
2156     append_new(index, 1);
2157   } else {
2158     assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2159     assert(count_at(i) > 0, "check");
2160     set_count_at(i, count_at(i) + 1);
2161   }
2162   _ops.push(op);
2163 
2164   DEBUG_ONLY(verify());
2165 }
2166 
2167 #ifdef ASSERT
2168 void LIR_InsertionBuffer::verify() {
2169   int sum = 0;
2170   int prev_idx = -1;
2171 
2172   for (int i = 0; i < number_of_insertion_points(); i++) {
2173     assert(prev_idx < index_at(i), "index must be ordered ascending");
2174     sum += count_at(i);
2175   }
2176   assert(sum == number_of_ops(), "wrong total sum");
2177 }
2178 #endif