< prev index next >

src/hotspot/share/c1/c1_LIR.cpp

Print this page

 165     default:
 166       ShouldNotReachHere();
 167     }
 168   }
 169 #endif
 170 
 171 }
 172 #endif // PRODUCT
 173 
 174 
 175 bool LIR_OprDesc::is_oop() const {
 176   if (is_pointer()) {
 177     return pointer()->is_oop_pointer();
 178   } else {
 179     OprType t= type_field();
 180     assert(t != unknown_type, "not set");
 181     return t == object_type;
 182   }
 183 }
 184 


 185 


































 186 
 187 void LIR_Op2::verify() const {
 188 #ifdef ASSERT
 189   switch (code()) {

 190     case lir_cmove:

 191     case lir_xchg:
 192       break;
 193 
 194     default:
 195       assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
 196              "can't produce oops from arith");
 197   }
 198 
 199   if (TwoOperandLIRForm) {
 200 
 201 #ifdef ASSERT
 202     bool threeOperandForm = false;
 203 #ifdef S390
 204     // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
 205     threeOperandForm =
 206       code() == lir_shl ||
 207       ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
 208 #endif
 209 #endif
 210 

 219     case lir_logic_xor:
 220     case lir_shl:
 221     case lir_shr:
 222       assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
 223       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 224       break;
 225 
 226     // special handling for lir_ushr because of write barriers
 227     case lir_ushr:
 228       assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
 229       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 230       break;
 231 
 232     default:
 233       break;
 234     }
 235   }
 236 #endif
 237 }
 238 
 239 
 240 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block)







 241   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 242   , _cond(cond)

 243   , _label(block->label())
 244   , _block(block)
 245   , _ublock(NULL)
 246   , _stub(NULL) {
 247 }
 248 
 249 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, CodeStub* stub) :
 250   LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)








 251   , _cond(cond)

 252   , _label(stub->entry())
 253   , _block(NULL)
 254   , _ublock(NULL)
 255   , _stub(stub) {
 256 }
 257 
 258 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock)









 259   : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 260   , _cond(cond)

 261   , _label(block->label())
 262   , _block(block)
 263   , _ublock(ublock)
 264   , _stub(NULL)
 265 {
 266 }
 267 
 268 void LIR_OpBranch::change_block(BlockBegin* b) {
 269   assert(_block != NULL, "must have old block");
 270   assert(_block->label() == label(), "must be equal");
 271 
 272   _block = b;
 273   _label = b->label();
 274 }
 275 
 276 void LIR_OpBranch::change_ublock(BlockBegin* b) {
 277   assert(_ublock != NULL, "must have old block");
 278   _ublock = b;
 279 }
 280 
 281 void LIR_OpBranch::negate_cond() {
 282   switch (_cond) {
 283     case lir_cond_equal:        _cond = lir_cond_notEqual;     break;
 284     case lir_cond_notEqual:     _cond = lir_cond_equal;        break;
 285     case lir_cond_less:         _cond = lir_cond_greaterEqual; break;
 286     case lir_cond_lessEqual:    _cond = lir_cond_greater;      break;
 287     case lir_cond_greaterEqual: _cond = lir_cond_less;         break;
 288     case lir_cond_greater:      _cond = lir_cond_lessEqual;    break;
 289     default: ShouldNotReachHere();
 290   }
 291 }
 292 
 293 
 294 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
 295                                  LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
 296                                  bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
 297                                  CodeStub* stub)
 298 
 299   : LIR_Op(code, result, NULL)
 300   , _object(object)
 301   , _array(LIR_OprFact::illegalOpr)
 302   , _klass(klass)
 303   , _tmp1(tmp1)
 304   , _tmp2(tmp2)
 305   , _tmp3(tmp3)
 306   , _fast_check(fast_check)
 307   , _info_for_patch(info_for_patch)
 308   , _info_for_exception(info_for_exception)

 495 
 496       assert(opConvert->_info == NULL, "must be");
 497       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 498       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 499 #ifdef PPC32
 500       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 501       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 502 #endif
 503       do_stub(opConvert->_stub);
 504 
 505       break;
 506     }
 507 
 508 // LIR_OpBranch;
 509     case lir_branch:                   // may have info, input and result register always invalid
 510     case lir_cond_float_branch:        // may have info, input and result register always invalid
 511     {
 512       assert(op->as_OpBranch() != NULL, "must be");
 513       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 514 











 515       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 516       assert(opBranch->_result->is_illegal(), "not used");
 517       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 518 
 519       break;
 520     }
 521 
 522 
 523 // LIR_OpAllocObj
 524     case lir_alloc_object:
 525     {
 526       assert(op->as_OpAllocObj() != NULL, "must be");
 527       LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
 528 
 529       if (opAllocObj->_info)                     do_info(opAllocObj->_info);
 530       if (opAllocObj->_opr->is_valid()) {        do_input(opAllocObj->_opr);
 531                                                  do_temp(opAllocObj->_opr);
 532                                         }
 533       if (opAllocObj->_tmp1->is_valid())         do_temp(opAllocObj->_tmp1);
 534       if (opAllocObj->_tmp2->is_valid())         do_temp(opAllocObj->_tmp2);

 538                                                  do_stub(opAllocObj->_stub);
 539       break;
 540     }
 541 
 542 
 543 // LIR_OpRoundFP;
 544     case lir_roundfp: {
 545       assert(op->as_OpRoundFP() != NULL, "must be");
 546       LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
 547 
 548       assert(op->_info == NULL, "info not used by this instruction");
 549       assert(opRoundFP->_tmp->is_illegal(), "not used");
 550       do_input(opRoundFP->_opr);
 551       do_output(opRoundFP->_result);
 552 
 553       break;
 554     }
 555 
 556 
 557 // LIR_Op2

 558     case lir_cmp:

 559     case lir_cmp_l2i:
 560     case lir_ucmp_fd2i:
 561     case lir_cmp_fd2i:
 562     case lir_add:
 563     case lir_sub:
 564     case lir_rem:
 565     case lir_sqrt:
 566     case lir_abs:
 567     case lir_neg:
 568     case lir_logic_and:
 569     case lir_logic_or:
 570     case lir_logic_xor:
 571     case lir_shl:
 572     case lir_shr:
 573     case lir_ushr:
 574     case lir_xadd:
 575     case lir_xchg:
 576     case lir_assert:
 577     {
 578       assert(op->as_Op2() != NULL, "must be");

 583       if (op2->_info)                     do_info(op2->_info);
 584       if (op2->_opr1->is_valid())         do_input(op2->_opr1);
 585       if (op2->_opr2->is_valid())         do_input(op2->_opr2);
 586       if (op2->_tmp1->is_valid())         do_temp(op2->_tmp1);
 587       if (op2->_result->is_valid())       do_output(op2->_result);
 588       if (op->code() == lir_xchg || op->code() == lir_xadd) {
 589         // on ARM and PPC, return value is loaded first so could
 590         // destroy inputs. On other platforms that implement those
 591         // (x86, sparc), the extra constrainsts are harmless.
 592         if (op2->_opr1->is_valid())       do_temp(op2->_opr1);
 593         if (op2->_opr2->is_valid())       do_temp(op2->_opr2);
 594       }
 595 
 596       break;
 597     }
 598 
 599     // special handling for cmove: right input operand must not be equal
 600     // to the result operand, otherwise the backend fails
 601     case lir_cmove:
 602     {




















 603       assert(op->as_Op2() != NULL, "must be");
 604       LIR_Op2* op2 = (LIR_Op2*)op;
 605 
 606       assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
 607              op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 608       assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
 609 
 610       do_input(op2->_opr1);
 611       do_input(op2->_opr2);
 612       do_temp(op2->_opr2);
 613       do_output(op2->_result);

 614 
 615       break;
 616     }
 617 
 618     // vspecial handling for strict operations: register input operands
 619     // as temp to guarantee that they do not overlap with other
 620     // registers
 621     case lir_mul:
 622     case lir_div:
 623     {
 624       assert(op->as_Op2() != NULL, "must be");
 625       LIR_Op2* op2 = (LIR_Op2*)op;
 626 
 627       assert(op2->_info == NULL, "not used");
 628       assert(op2->_opr1->is_valid(), "used");
 629       assert(op2->_opr2->is_valid(), "used");
 630       assert(op2->_result->is_valid(), "used");
 631       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 632              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 633 

1024 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1025   masm->emit_alloc_array(this);
1026   masm->append_code_stub(stub());
1027 }
1028 
1029 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1030   masm->emit_opTypeCheck(this);
1031   if (stub()) {
1032     masm->append_code_stub(stub());
1033   }
1034 }
1035 
1036 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1037   masm->emit_compare_and_swap(this);
1038 }
1039 
1040 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1041   masm->emit_op3(this);
1042 }
1043 






1044 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1045   masm->emit_lock(this);
1046   if (stub()) {
1047     masm->append_code_stub(stub());
1048   }
1049 }
1050 
1051 #ifdef ASSERT
1052 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1053   masm->emit_assert(this);
1054 }
1055 #endif
1056 
1057 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1058   masm->emit_delay(this);
1059 }
1060 
1061 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1062   masm->emit_profile_call(this);
1063 }

1248                     lir_irem,
1249                     left,
1250                     right,
1251                     tmp,
1252                     res,
1253                     info));
1254 }
1255 
1256 
1257 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1258   append(new LIR_Op3(
1259                     lir_irem,
1260                     left,
1261                     LIR_OprFact::intConst(right),
1262                     tmp,
1263                     res,
1264                     info));
1265 }
1266 
1267 

1268 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1269   append(new LIR_Op2(
1270                     lir_cmp,
1271                     condition,
1272                     LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1273                     LIR_OprFact::intConst(c),
1274                     info));
1275 }
1276 
1277 
1278 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1279   append(new LIR_Op2(
1280                     lir_cmp,
1281                     condition,
1282                     reg,
1283                     LIR_OprFact::address(addr),
1284                     info));
1285 }

1286 
1287 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1288                                int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1289   append(new LIR_OpAllocObj(
1290                            klass,
1291                            dst,
1292                            t1,
1293                            t2,
1294                            t3,
1295                            t4,
1296                            header_size,
1297                            object_size,
1298                            init_check,
1299                            stub));
1300 }
1301 
1302 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1303   append(new LIR_OpAllocArray(
1304                            klass,
1305                            len,

1401   append(c);
1402 }
1403 
1404 
1405 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1406                            CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1407   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1408   if (profiled_method != NULL) {
1409     c->set_profiled_method(profiled_method);
1410     c->set_profiled_bci(profiled_bci);
1411     c->set_should_profile(true);
1412   }
1413   append(c);
1414 }
1415 
1416 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1417   if (deoptimize_on_null) {
1418     // Emit an explicit null check and deoptimize if opr is null
1419     CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none);
1420     cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1421     branch(lir_cond_equal, deopt);





1422   } else {
1423     // Emit an implicit null check
1424     append(new LIR_Op1(lir_null_check, opr, info));
1425   }
1426 }
1427 
1428 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1429                         LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1430   append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1431 }
1432 
1433 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1434                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1435   append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1436 }
1437 
1438 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1439                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1440   append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1441 }

1644      // LIR_Op1
1645      case lir_fxch:                  s = "fxch";          break;
1646      case lir_fld:                   s = "fld";           break;
1647      case lir_push:                  s = "push";          break;
1648      case lir_pop:                   s = "pop";           break;
1649      case lir_null_check:            s = "null_check";    break;
1650      case lir_return:                s = "return";        break;
1651      case lir_safepoint:             s = "safepoint";     break;
1652      case lir_leal:                  s = "leal";          break;
1653      case lir_branch:                s = "branch";        break;
1654      case lir_cond_float_branch:     s = "flt_cond_br";   break;
1655      case lir_move:                  s = "move";          break;
1656      case lir_roundfp:               s = "roundfp";       break;
1657      case lir_rtcall:                s = "rtcall";        break;
1658      case lir_throw:                 s = "throw";         break;
1659      case lir_unwind:                s = "unwind";        break;
1660      case lir_convert:               s = "convert";       break;
1661      case lir_alloc_object:          s = "alloc_obj";     break;
1662      case lir_monaddr:               s = "mon_addr";      break;
1663      // LIR_Op2

1664      case lir_cmp:                   s = "cmp";           break;

1665      case lir_cmp_l2i:               s = "cmp_l2i";       break;
1666      case lir_ucmp_fd2i:             s = "ucomp_fd2i";    break;
1667      case lir_cmp_fd2i:              s = "comp_fd2i";     break;

1668      case lir_cmove:                 s = "cmove";         break;
1669      case lir_add:                   s = "add";           break;
1670      case lir_sub:                   s = "sub";           break;
1671      case lir_mul:                   s = "mul";           break;
1672      case lir_div:                   s = "div";           break;
1673      case lir_rem:                   s = "rem";           break;
1674      case lir_abs:                   s = "abs";           break;
1675      case lir_neg:                   s = "neg";           break;
1676      case lir_sqrt:                  s = "sqrt";          break;
1677      case lir_logic_and:             s = "logic_and";     break;
1678      case lir_logic_or:              s = "logic_or";      break;
1679      case lir_logic_xor:             s = "logic_xor";     break;
1680      case lir_shl:                   s = "shift_left";    break;
1681      case lir_shr:                   s = "shift_right";   break;
1682      case lir_ushr:                  s = "ushift_right";  break;
1683      case lir_alloc_array:           s = "alloc_array";   break;
1684      case lir_xadd:                  s = "xadd";          break;
1685      case lir_xchg:                  s = "xchg";          break;
1686      // LIR_Op3
1687      case lir_idiv:                  s = "idiv";          break;

1804 void LIR_OpRTCall::print_instr(outputStream* out) const {
1805   intx a = (intx)addr();
1806   out->print("%s", Runtime1::name_for_address(addr()));
1807   out->print(" ");
1808   tmp()->print(out);
1809 }
1810 
1811 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1812   switch(code) {
1813     case lir_patch_none:                                 break;
1814     case lir_patch_low:    out->print("[patch_low]");    break;
1815     case lir_patch_high:   out->print("[patch_high]");   break;
1816     case lir_patch_normal: out->print("[patch_normal]"); break;
1817     default: ShouldNotReachHere();
1818   }
1819 }
1820 
1821 // LIR_OpBranch
1822 void LIR_OpBranch::print_instr(outputStream* out) const {
1823   print_condition(out, cond());             out->print(" ");




1824   if (block() != NULL) {
1825     out->print("[B%d] ", block()->block_id());
1826   } else if (stub() != NULL) {
1827     out->print("[");
1828     stub()->print_name(out);
1829     out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1830     if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1831   } else {
1832     out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1833   }
1834   if (ublock() != NULL) {
1835     out->print("unordered: [B%d] ", ublock()->block_id());
1836   }
1837 }
1838 
1839 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1840   switch(cond) {
1841     case lir_cond_equal:           out->print("[EQ]");      break;
1842     case lir_cond_notEqual:        out->print("[NE]");      break;
1843     case lir_cond_less:            out->print("[LT]");      break;

1890 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1891   klass()->print(out);                      out->print(" ");
1892   obj()->print(out);                        out->print(" ");
1893   tmp1()->print(out);                       out->print(" ");
1894   tmp2()->print(out);                       out->print(" ");
1895   tmp3()->print(out);                       out->print(" ");
1896   tmp4()->print(out);                       out->print(" ");
1897   out->print("[hdr:%d]", header_size()); out->print(" ");
1898   out->print("[obj:%d]", object_size()); out->print(" ");
1899   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1900 }
1901 
1902 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1903   _opr->print(out);         out->print(" ");
1904   tmp()->print(out);        out->print(" ");
1905   result_opr()->print(out); out->print(" ");
1906 }
1907 
1908 // LIR_Op2
1909 void LIR_Op2::print_instr(outputStream* out) const {



1910   if (code() == lir_cmove || code() == lir_cmp) {

1911     print_condition(out, condition());         out->print(" ");
1912   }
1913   in_opr1()->print(out);    out->print(" ");
1914   in_opr2()->print(out);    out->print(" ");
1915   if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out);    out->print(" "); }
1916   if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out);    out->print(" "); }
1917   if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out);    out->print(" "); }
1918   if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out);    out->print(" "); }
1919   if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out);    out->print(" "); }
1920   result_opr()->print(out);
1921 }
1922 
1923 void LIR_OpAllocArray::print_instr(outputStream* out) const {
1924   klass()->print(out);                   out->print(" ");
1925   len()->print(out);                     out->print(" ");
1926   obj()->print(out);                     out->print(" ");
1927   tmp1()->print(out);                    out->print(" ");
1928   tmp2()->print(out);                    out->print(" ");
1929   tmp3()->print(out);                    out->print(" ");
1930   tmp4()->print(out);                    out->print(" ");

1941   if (code() != lir_store_check) {
1942     klass()->print_name_on(out);         out->print(" ");
1943     if (fast_check())                 out->print("fast_check ");
1944   }
1945   tmp1()->print(out);                    out->print(" ");
1946   tmp2()->print(out);                    out->print(" ");
1947   tmp3()->print(out);                    out->print(" ");
1948   result_opr()->print(out);              out->print(" ");
1949   if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
1950 }
1951 
1952 
1953 // LIR_Op3
1954 void LIR_Op3::print_instr(outputStream* out) const {
1955   in_opr1()->print(out);    out->print(" ");
1956   in_opr2()->print(out);    out->print(" ");
1957   in_opr3()->print(out);    out->print(" ");
1958   result_opr()->print(out);
1959 }
1960 











1961 
1962 void LIR_OpLock::print_instr(outputStream* out) const {
1963   hdr_opr()->print(out);   out->print(" ");
1964   obj_opr()->print(out);   out->print(" ");
1965   lock_opr()->print(out);  out->print(" ");
1966   if (_scratch->is_valid()) {
1967     _scratch->print(out);  out->print(" ");
1968   }
1969   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1970 }
1971 
1972 #ifdef ASSERT
1973 void LIR_OpAssert::print_instr(outputStream* out) const {
1974   print_condition(out, condition()); out->print(" ");
1975   in_opr1()->print(out);             out->print(" ");
1976   in_opr2()->print(out);             out->print(", \"");
1977   out->print("%s", msg());          out->print("\"");
1978 }
1979 #endif
1980 

 165     default:
 166       ShouldNotReachHere();
 167     }
 168   }
 169 #endif
 170 
 171 }
 172 #endif // PRODUCT
 173 
 174 
 175 bool LIR_OprDesc::is_oop() const {
 176   if (is_pointer()) {
 177     return pointer()->is_oop_pointer();
 178   } else {
 179     OprType t= type_field();
 180     assert(t != unknown_type, "not set");
 181     return t == object_type;
 182   }
 183 }
 184 
 185 #ifdef RISCV
 186 bool LIR_OprDesc::has_common_register(LIR_Opr opr) const {
 187 
 188   if (!(is_register() && opr->is_register())) {
 189     return false;
 190   }
 191 
 192   if (is_single_cpu()) {
 193     Register dst = as_register();
 194     if (opr->is_single_cpu()) {
 195       return dst == opr->as_register();
 196     } else if (opr->is_double_cpu()) {
 197       return dst == opr->as_register_lo();
 198     }
 199   } else if (is_double_cpu()) {
 200     Register dst_lo = as_register_lo();
 201     if (opr->is_single_cpu()) {
 202       return dst_lo == opr->as_register();
 203     } else if (opr->is_double_cpu()) {
 204       return dst_lo == opr->as_register_lo();
 205     }
 206   } else if (is_single_fpu()) {
 207     if (opr->is_single_fpu()) {
 208       return as_float_reg() == opr->as_float_reg();
 209     } else if (opr->is_double_fpu()) {
 210       return as_float_reg() == opr->as_double_reg();
 211     }
 212   } else if (is_double_fpu()) {
 213     if (opr->is_single_fpu()) {
 214       return as_double_reg() == opr->as_float_reg();
 215     }else if (opr->is_double_fpu()) {
 216       return as_double_reg() == opr->as_double_reg();
 217     }
 218   }
 219   return false;
 220 }
 221 #endif // RISCV
 222 
 223 void LIR_Op2::verify() const {
 224 #ifdef ASSERT
 225   switch (code()) {
 226 #ifndef RISCV
 227     case lir_cmove:
 228 #endif
 229     case lir_xchg:
 230       break;
 231 
 232     default:
 233       assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
 234              "can't produce oops from arith");
 235   }
 236 
 237   if (TwoOperandLIRForm) {
 238 
 239 #ifdef ASSERT
 240     bool threeOperandForm = false;
 241 #ifdef S390
 242     // There are 3 operand shifts on S390 (see LIR_Assembler::shift_op()).
 243     threeOperandForm =
 244       code() == lir_shl ||
 245       ((code() == lir_shr || code() == lir_ushr) && (result_opr()->is_double_cpu() || in_opr1()->type() == T_OBJECT));
 246 #endif
 247 #endif
 248 

 257     case lir_logic_xor:
 258     case lir_shl:
 259     case lir_shr:
 260       assert(in_opr1() == result_opr() || threeOperandForm, "opr1 and result must match");
 261       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 262       break;
 263 
 264     // special handling for lir_ushr because of write barriers
 265     case lir_ushr:
 266       assert(in_opr1() == result_opr() || in_opr2()->is_constant() || threeOperandForm, "opr1 and result must match or shift count is constant");
 267       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 268       break;
 269 
 270     default:
 271       break;
 272     }
 273   }
 274 #endif
 275 }
 276 
 277 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond,
 278 #ifdef RISCV
 279                            LIR_Opr left,
 280                            LIR_Opr right,
 281 #endif
 282                            BlockBegin* block)
 283 #ifdef RISCV
 284   : LIR_Op2(lir_branch, cond, left, right, (CodeEmitInfo*)NULL)
 285 #else
 286   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 287   , _cond(cond)
 288 #endif
 289   , _label(block->label())
 290   , _block(block)
 291   , _ublock(NULL)
 292   , _stub(NULL) {
 293 }
 294 
 295 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond,
 296 #ifdef RISCV
 297                            LIR_Opr left,
 298                            LIR_Opr right,
 299 #endif
 300                            CodeStub* stub)
 301 #ifdef RISCV
 302   : LIR_Op2(lir_branch, cond, left, right, (CodeEmitInfo*)NULL)
 303 #else
 304   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 305   , _cond(cond)
 306 #endif
 307   , _label(stub->entry())
 308   , _block(NULL)
 309   , _ublock(NULL)
 310   , _stub(stub) {
 311 }
 312 
 313 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond,
 314 #ifdef RISCV
 315                            LIR_Opr left,
 316                            LIR_Opr right,
 317 #endif
 318                            BlockBegin* block,
 319                            BlockBegin* ublock)
 320 #ifdef RISCV
 321   : LIR_Op2(lir_branch, cond, left, right, (CodeEmitInfo*)NULL)
 322 #else
 323   : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 324   , _cond(cond)
 325 #endif
 326   , _label(block->label())
 327   , _block(block)
 328   , _ublock(ublock)
 329   , _stub(NULL)
 330 {
 331 }
 332 
 333 void LIR_OpBranch::change_block(BlockBegin* b) {
 334   assert(_block != NULL, "must have old block");
 335   assert(_block->label() == label(), "must be equal");
 336 
 337   _block = b;
 338   _label = b->label();
 339 }
 340 
 341 void LIR_OpBranch::change_ublock(BlockBegin* b) {
 342   assert(_ublock != NULL, "must have old block");
 343   _ublock = b;
 344 }
 345 
 346 void LIR_OpBranch::negate_cond() {
 347   switch (cond()) {
 348     case lir_cond_equal:        set_cond(lir_cond_notEqual);     break;
 349     case lir_cond_notEqual:     set_cond(lir_cond_equal);        break;
 350     case lir_cond_less:         set_cond(lir_cond_greaterEqual); break;
 351     case lir_cond_lessEqual:    set_cond(lir_cond_greater);      break;
 352     case lir_cond_greaterEqual: set_cond(lir_cond_less);         break;
 353     case lir_cond_greater:      set_cond(lir_cond_lessEqual);    break;
 354     default: ShouldNotReachHere();
 355   }
 356 }
 357 
 358 
 359 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
 360                                  LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
 361                                  bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
 362                                  CodeStub* stub)
 363 
 364   : LIR_Op(code, result, NULL)
 365   , _object(object)
 366   , _array(LIR_OprFact::illegalOpr)
 367   , _klass(klass)
 368   , _tmp1(tmp1)
 369   , _tmp2(tmp2)
 370   , _tmp3(tmp3)
 371   , _fast_check(fast_check)
 372   , _info_for_patch(info_for_patch)
 373   , _info_for_exception(info_for_exception)

 560 
 561       assert(opConvert->_info == NULL, "must be");
 562       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 563       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 564 #ifdef PPC32
 565       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 566       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 567 #endif
 568       do_stub(opConvert->_stub);
 569 
 570       break;
 571     }
 572 
 573 // LIR_OpBranch;
 574     case lir_branch:                   // may have info, input and result register always invalid
 575     case lir_cond_float_branch:        // may have info, input and result register always invalid
 576     {
 577       assert(op->as_OpBranch() != NULL, "must be");
 578       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 579 
 580 #ifdef RISCV
 581       // lir_branch and lir_cond_float_branch should be LIR_Op2 if arch has no flag register
 582       if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
 583       if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
 584       if (opBranch->_tmp1->is_valid()) do_temp(opBranch->_tmp1);
 585       if (opBranch->_tmp2->is_valid()) do_temp(opBranch->_tmp2);
 586       if (opBranch->_tmp3->is_valid()) do_temp(opBranch->_tmp3);
 587       if (opBranch->_tmp4->is_valid()) do_temp(opBranch->_tmp4);
 588       if (opBranch->_tmp5->is_valid()) do_temp(opBranch->_tmp5);
 589 #endif
 590 
 591       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 592       assert(opBranch->_result->is_illegal(), "not used");
 593       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 594 
 595       break;
 596     }
 597 
 598 
 599 // LIR_OpAllocObj
 600     case lir_alloc_object:
 601     {
 602       assert(op->as_OpAllocObj() != NULL, "must be");
 603       LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
 604 
 605       if (opAllocObj->_info)                     do_info(opAllocObj->_info);
 606       if (opAllocObj->_opr->is_valid()) {        do_input(opAllocObj->_opr);
 607                                                  do_temp(opAllocObj->_opr);
 608                                         }
 609       if (opAllocObj->_tmp1->is_valid())         do_temp(opAllocObj->_tmp1);
 610       if (opAllocObj->_tmp2->is_valid())         do_temp(opAllocObj->_tmp2);

 614                                                  do_stub(opAllocObj->_stub);
 615       break;
 616     }
 617 
 618 
 619 // LIR_OpRoundFP;
 620     case lir_roundfp: {
 621       assert(op->as_OpRoundFP() != NULL, "must be");
 622       LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
 623 
 624       assert(op->_info == NULL, "info not used by this instruction");
 625       assert(opRoundFP->_tmp->is_illegal(), "not used");
 626       do_input(opRoundFP->_opr);
 627       do_output(opRoundFP->_result);
 628 
 629       break;
 630     }
 631 
 632 
 633 // LIR_Op2
 634 #ifndef RISCV
 635     case lir_cmp:
 636 #endif
 637     case lir_cmp_l2i:
 638     case lir_ucmp_fd2i:
 639     case lir_cmp_fd2i:
 640     case lir_add:
 641     case lir_sub:
 642     case lir_rem:
 643     case lir_sqrt:
 644     case lir_abs:
 645     case lir_neg:
 646     case lir_logic_and:
 647     case lir_logic_or:
 648     case lir_logic_xor:
 649     case lir_shl:
 650     case lir_shr:
 651     case lir_ushr:
 652     case lir_xadd:
 653     case lir_xchg:
 654     case lir_assert:
 655     {
 656       assert(op->as_Op2() != NULL, "must be");

 661       if (op2->_info)                     do_info(op2->_info);
 662       if (op2->_opr1->is_valid())         do_input(op2->_opr1);
 663       if (op2->_opr2->is_valid())         do_input(op2->_opr2);
 664       if (op2->_tmp1->is_valid())         do_temp(op2->_tmp1);
 665       if (op2->_result->is_valid())       do_output(op2->_result);
 666       if (op->code() == lir_xchg || op->code() == lir_xadd) {
 667         // on ARM and PPC, return value is loaded first so could
 668         // destroy inputs. On other platforms that implement those
 669         // (x86, sparc), the extra constrainsts are harmless.
 670         if (op2->_opr1->is_valid())       do_temp(op2->_opr1);
 671         if (op2->_opr2->is_valid())       do_temp(op2->_opr2);
 672       }
 673 
 674       break;
 675     }
 676 
 677     // special handling for cmove: right input operand must not be equal
 678     // to the result operand, otherwise the backend fails
 679     case lir_cmove:
 680     {
 681 #ifdef RISCV
 682       // lir_cmove should be LIR_Op4 on riscv64
 683       assert(op->as_Op4() != NULL, "must be");
 684       LIR_Op4* op4 = (LIR_Op4*)op;
 685 
 686       assert(op4->_info == NULL, "must be");
 687       assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && op4->_opr3->is_valid() &&
 688              op4->_opr4->is_valid() && op4->_result->is_valid(), "used");
 689 
 690       do_input(op4->_opr1);
 691       do_input(op4->_opr2);
 692       do_input(op4->_opr3);
 693       do_input(op4->_opr4);
 694       if (op4->_tmp1->is_valid())  do_temp(op4->_tmp1);
 695       if (op4->_tmp2->is_valid())  do_temp(op4->_tmp2);
 696       if (op4->_tmp3->is_valid())  do_temp(op4->_tmp3);
 697       if (op4->_tmp4->is_valid())  do_temp(op4->_tmp4);
 698       if (op4->_tmp5->is_valid())  do_temp(op4->_tmp5);
 699       do_output(op4->_result);
 700 #else
 701       assert(op->as_Op2() != NULL, "must be");
 702       LIR_Op2* op2 = (LIR_Op2*)op;
 703 
 704       assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
 705              op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 706       assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
 707 
 708       do_input(op2->_opr1);
 709       do_input(op2->_opr2);
 710       do_temp(op2->_opr2);
 711       do_output(op2->_result);
 712 #endif // RISCV
 713 
 714       break;
 715     }
 716 
 717     // vspecial handling for strict operations: register input operands
 718     // as temp to guarantee that they do not overlap with other
 719     // registers
 720     case lir_mul:
 721     case lir_div:
 722     {
 723       assert(op->as_Op2() != NULL, "must be");
 724       LIR_Op2* op2 = (LIR_Op2*)op;
 725 
 726       assert(op2->_info == NULL, "not used");
 727       assert(op2->_opr1->is_valid(), "used");
 728       assert(op2->_opr2->is_valid(), "used");
 729       assert(op2->_result->is_valid(), "used");
 730       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 731              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 732 

1123 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1124   masm->emit_alloc_array(this);
1125   masm->append_code_stub(stub());
1126 }
1127 
1128 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1129   masm->emit_opTypeCheck(this);
1130   if (stub()) {
1131     masm->append_code_stub(stub());
1132   }
1133 }
1134 
1135 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1136   masm->emit_compare_and_swap(this);
1137 }
1138 
1139 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1140   masm->emit_op3(this);
1141 }
1142 
1143 #ifdef RISCV
1144 void LIR_Op4::emit_code(LIR_Assembler* masm) {
1145   masm->emit_op4(this);
1146 }
1147 #endif
1148 
1149 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1150   masm->emit_lock(this);
1151   if (stub()) {
1152     masm->append_code_stub(stub());
1153   }
1154 }
1155 
1156 #ifdef ASSERT
1157 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1158   masm->emit_assert(this);
1159 }
1160 #endif
1161 
1162 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1163   masm->emit_delay(this);
1164 }
1165 
1166 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1167   masm->emit_profile_call(this);
1168 }

1353                     lir_irem,
1354                     left,
1355                     right,
1356                     tmp,
1357                     res,
1358                     info));
1359 }
1360 
1361 
1362 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1363   append(new LIR_Op3(
1364                     lir_irem,
1365                     left,
1366                     LIR_OprFact::intConst(right),
1367                     tmp,
1368                     res,
1369                     info));
1370 }
1371 
1372 
1373 #ifndef RISCV
1374 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1375   append(new LIR_Op2(
1376                     lir_cmp,
1377                     condition,
1378                     LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1379                     LIR_OprFact::intConst(c),
1380                     info));
1381 }
1382 
1383 
1384 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1385   append(new LIR_Op2(
1386                     lir_cmp,
1387                     condition,
1388                     reg,
1389                     LIR_OprFact::address(addr),
1390                     info));
1391 }
1392 #endif
1393 
1394 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1395                                int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1396   append(new LIR_OpAllocObj(
1397                            klass,
1398                            dst,
1399                            t1,
1400                            t2,
1401                            t3,
1402                            t4,
1403                            header_size,
1404                            object_size,
1405                            init_check,
1406                            stub));
1407 }
1408 
1409 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1410   append(new LIR_OpAllocArray(
1411                            klass,
1412                            len,

1508   append(c);
1509 }
1510 
1511 
1512 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1513                            CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1514   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1515   if (profiled_method != NULL) {
1516     c->set_profiled_method(profiled_method);
1517     c->set_profiled_bci(profiled_bci);
1518     c->set_should_profile(true);
1519   }
1520   append(c);
1521 }
1522 
1523 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1524   if (deoptimize_on_null) {
1525     // Emit an explicit null check and deoptimize if opr is null
1526     CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none);
1527     cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1528     branch(lir_cond_equal,
1529 #ifdef RISCV
1530            opr,
1531            LIR_OprFact::oopConst(NULL),
1532 #endif
1533            deopt);
1534   } else {
1535     // Emit an implicit null check
1536     append(new LIR_Op1(lir_null_check, opr, info));
1537   }
1538 }
1539 
1540 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1541                         LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1542   append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1543 }
1544 
1545 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1546                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1547   append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1548 }
1549 
1550 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1551                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1552   append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1553 }

1756      // LIR_Op1
1757      case lir_fxch:                  s = "fxch";          break;
1758      case lir_fld:                   s = "fld";           break;
1759      case lir_push:                  s = "push";          break;
1760      case lir_pop:                   s = "pop";           break;
1761      case lir_null_check:            s = "null_check";    break;
1762      case lir_return:                s = "return";        break;
1763      case lir_safepoint:             s = "safepoint";     break;
1764      case lir_leal:                  s = "leal";          break;
1765      case lir_branch:                s = "branch";        break;
1766      case lir_cond_float_branch:     s = "flt_cond_br";   break;
1767      case lir_move:                  s = "move";          break;
1768      case lir_roundfp:               s = "roundfp";       break;
1769      case lir_rtcall:                s = "rtcall";        break;
1770      case lir_throw:                 s = "throw";         break;
1771      case lir_unwind:                s = "unwind";        break;
1772      case lir_convert:               s = "convert";       break;
1773      case lir_alloc_object:          s = "alloc_obj";     break;
1774      case lir_monaddr:               s = "mon_addr";      break;
1775      // LIR_Op2
1776 #ifndef RISCV
1777      case lir_cmp:                   s = "cmp";           break;
1778 #endif
1779      case lir_cmp_l2i:               s = "cmp_l2i";       break;
1780      case lir_ucmp_fd2i:             s = "ucomp_fd2i";    break;
1781      case lir_cmp_fd2i:              s = "comp_fd2i";     break;
1782      // lir_cmove is LIR_Op4 on riscv64
1783      case lir_cmove:                 s = "cmove";         break;
1784      case lir_add:                   s = "add";           break;
1785      case lir_sub:                   s = "sub";           break;
1786      case lir_mul:                   s = "mul";           break;
1787      case lir_div:                   s = "div";           break;
1788      case lir_rem:                   s = "rem";           break;
1789      case lir_abs:                   s = "abs";           break;
1790      case lir_neg:                   s = "neg";           break;
1791      case lir_sqrt:                  s = "sqrt";          break;
1792      case lir_logic_and:             s = "logic_and";     break;
1793      case lir_logic_or:              s = "logic_or";      break;
1794      case lir_logic_xor:             s = "logic_xor";     break;
1795      case lir_shl:                   s = "shift_left";    break;
1796      case lir_shr:                   s = "shift_right";   break;
1797      case lir_ushr:                  s = "ushift_right";  break;
1798      case lir_alloc_array:           s = "alloc_array";   break;
1799      case lir_xadd:                  s = "xadd";          break;
1800      case lir_xchg:                  s = "xchg";          break;
1801      // LIR_Op3
1802      case lir_idiv:                  s = "idiv";          break;

1919 void LIR_OpRTCall::print_instr(outputStream* out) const {
1920   intx a = (intx)addr();
1921   out->print("%s", Runtime1::name_for_address(addr()));
1922   out->print(" ");
1923   tmp()->print(out);
1924 }
1925 
1926 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1927   switch(code) {
1928     case lir_patch_none:                                 break;
1929     case lir_patch_low:    out->print("[patch_low]");    break;
1930     case lir_patch_high:   out->print("[patch_high]");   break;
1931     case lir_patch_normal: out->print("[patch_normal]"); break;
1932     default: ShouldNotReachHere();
1933   }
1934 }
1935 
1936 // LIR_OpBranch
1937 void LIR_OpBranch::print_instr(outputStream* out) const {
1938   print_condition(out, cond());             out->print(" ");
1939 #ifdef RISCV
1940   in_opr1()->print(out); out->print(" ");
1941   in_opr2()->print(out); out->print(" ");
1942 #endif
1943   if (block() != NULL) {
1944     out->print("[B%d] ", block()->block_id());
1945   } else if (stub() != NULL) {
1946     out->print("[");
1947     stub()->print_name(out);
1948     out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1949     if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1950   } else {
1951     out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1952   }
1953   if (ublock() != NULL) {
1954     out->print("unordered: [B%d] ", ublock()->block_id());
1955   }
1956 }
1957 
1958 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1959   switch(cond) {
1960     case lir_cond_equal:           out->print("[EQ]");      break;
1961     case lir_cond_notEqual:        out->print("[NE]");      break;
1962     case lir_cond_less:            out->print("[LT]");      break;

2009 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2010   klass()->print(out);                      out->print(" ");
2011   obj()->print(out);                        out->print(" ");
2012   tmp1()->print(out);                       out->print(" ");
2013   tmp2()->print(out);                       out->print(" ");
2014   tmp3()->print(out);                       out->print(" ");
2015   tmp4()->print(out);                       out->print(" ");
2016   out->print("[hdr:%d]", header_size()); out->print(" ");
2017   out->print("[obj:%d]", object_size()); out->print(" ");
2018   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2019 }
2020 
2021 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2022   _opr->print(out);         out->print(" ");
2023   tmp()->print(out);        out->print(" ");
2024   result_opr()->print(out); out->print(" ");
2025 }
2026 
2027 // LIR_Op2
2028 void LIR_Op2::print_instr(outputStream* out) const {
2029 #ifdef RISCV
2030   if (code() == lir_branch || code() == lir_cond_float_branch) {
2031 #else
2032   if (code() == lir_cmove || code() == lir_cmp) {
2033 #endif
2034     print_condition(out, condition());         out->print(" ");
2035   }
2036   in_opr1()->print(out);    out->print(" ");
2037   in_opr2()->print(out);    out->print(" ");
2038   if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out);    out->print(" "); }
2039   if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out);    out->print(" "); }
2040   if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out);    out->print(" "); }
2041   if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out);    out->print(" "); }
2042   if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out);    out->print(" "); }
2043   result_opr()->print(out);
2044 }
2045 
2046 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2047   klass()->print(out);                   out->print(" ");
2048   len()->print(out);                     out->print(" ");
2049   obj()->print(out);                     out->print(" ");
2050   tmp1()->print(out);                    out->print(" ");
2051   tmp2()->print(out);                    out->print(" ");
2052   tmp3()->print(out);                    out->print(" ");
2053   tmp4()->print(out);                    out->print(" ");

2064   if (code() != lir_store_check) {
2065     klass()->print_name_on(out);         out->print(" ");
2066     if (fast_check())                 out->print("fast_check ");
2067   }
2068   tmp1()->print(out);                    out->print(" ");
2069   tmp2()->print(out);                    out->print(" ");
2070   tmp3()->print(out);                    out->print(" ");
2071   result_opr()->print(out);              out->print(" ");
2072   if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2073 }
2074 
2075 
2076 // LIR_Op3
2077 void LIR_Op3::print_instr(outputStream* out) const {
2078   in_opr1()->print(out);    out->print(" ");
2079   in_opr2()->print(out);    out->print(" ");
2080   in_opr3()->print(out);    out->print(" ");
2081   result_opr()->print(out);
2082 }
2083 
2084 #ifdef RISCV
2085 // LIR_Op4
2086 void LIR_Op4::print_instr(outputStream* out) const {
2087   print_condition(out, cond()); out->print(" ");
2088   in_opr1()->print(out);        out->print(" ");
2089   in_opr2()->print(out);        out->print(" ");
2090   in_opr3()->print(out);        out->print(" ");
2091   in_opr4()->print(out);        out->print(" ");
2092   result_opr()->print(out);
2093 }
2094 #endif // RISCV
2095 
2096 void LIR_OpLock::print_instr(outputStream* out) const {
2097   hdr_opr()->print(out);   out->print(" ");
2098   obj_opr()->print(out);   out->print(" ");
2099   lock_opr()->print(out);  out->print(" ");
2100   if (_scratch->is_valid()) {
2101     _scratch->print(out);  out->print(" ");
2102   }
2103   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2104 }
2105 
2106 #ifdef ASSERT
2107 void LIR_OpAssert::print_instr(outputStream* out) const {
2108   print_condition(out, condition()); out->print(" ");
2109   in_opr1()->print(out);             out->print(" ");
2110   in_opr2()->print(out);             out->print(", \"");
2111   out->print("%s", msg());          out->print("\"");
2112 }
2113 #endif
2114 
< prev index next >