1 /*
   2  * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "runtime/timerTrace.hpp"
  36 #include "utilities/bitMap.inline.hpp"
  37 
  38 #ifndef PRODUCT
  39 
  40   static LinearScanStatistic _stat_before_alloc;
  41   static LinearScanStatistic _stat_after_asign;
  42   static LinearScanStatistic _stat_final;
  43 
  44   static LinearScanTimers _total_timer;
  45 
  46   // helper macro for short definition of timer
  47   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  48 
  49 #else
  50   #define TIME_LINEAR_SCAN(timer_name)
  51 #endif
  52 
  53 #ifdef ASSERT
  54 
  55   // helper macro for short definition of trace-output inside code
  56   #define TRACE_LINEAR_SCAN(level, code)       \
  57     if (TraceLinearScanLevel >= level) {       \
  58       code;                                    \
  59     }
  60 #else
  61   #define TRACE_LINEAR_SCAN(level, code)
  62 #endif
  63 
  64 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  65 #ifdef _LP64
  66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  67 #else
  68 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  69 #endif
  70 
  71 
  72 // Implementation of LinearScan
  73 
  74 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  75  : _compilation(ir->compilation())
  76  , _ir(ir)
  77  , _gen(gen)
  78  , _frame_map(frame_map)
  79  , _cached_blocks(*ir->linear_scan_order())
  80  , _num_virtual_regs(gen->max_virtual_register_number())
  81  , _has_fpu_registers(false)
  82  , _num_calls(-1)
  83  , _max_spills(0)
  84  , _unused_spill_slot(-1)
  85  , _intervals(0)   // initialized later with correct length
  86  , _new_intervals_from_allocation(NULL)
  87  , _sorted_intervals(NULL)
  88  , _needs_full_resort(false)
  89  , _lir_ops(0)     // initialized later with correct length
  90  , _block_of_op(0) // initialized later with correct length
  91  , _has_info(0)
  92  , _has_call(0)
  93  , _interval_in_loop(0)  // initialized later with correct length
  94  , _scope_value_cache(0) // initialized later with correct length
  95 #ifdef IA32
  96  , _fpu_stack_allocator(NULL)
  97 #endif
  98 {
  99   assert(this->ir() != NULL,          "check if valid");
 100   assert(this->compilation() != NULL, "check if valid");
 101   assert(this->gen() != NULL,         "check if valid");
 102   assert(this->frame_map() != NULL,   "check if valid");
 103 }
 104 
 105 
 106 // ********** functions for converting LIR-Operands to register numbers
 107 //
 108 // Emulate a flat register file comprising physical integer registers,
 109 // physical floating-point registers and virtual registers, in that order.
 110 // Virtual registers already have appropriate numbers, since V0 is
 111 // the number of physical registers.
 112 // Returns -1 for hi word if opr is a single word operand.
 113 //
 114 // Note: the inverse operation (calculating an operand for register numbers)
 115 //       is done in calc_operand_for_interval()
 116 
 117 int LinearScan::reg_num(LIR_Opr opr) {
 118   assert(opr->is_register(), "should not call this otherwise");
 119 
 120   if (opr->is_virtual_register()) {
 121     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 122     return opr->vreg_number();
 123   } else if (opr->is_single_cpu()) {
 124     return opr->cpu_regnr();
 125   } else if (opr->is_double_cpu()) {
 126     return opr->cpu_regnrLo();
 127 #ifdef X86
 128   } else if (opr->is_single_xmm()) {
 129     return opr->fpu_regnr() + pd_first_xmm_reg;
 130   } else if (opr->is_double_xmm()) {
 131     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 132 #endif
 133   } else if (opr->is_single_fpu()) {
 134     return opr->fpu_regnr() + pd_first_fpu_reg;
 135   } else if (opr->is_double_fpu()) {
 136     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 137   } else {
 138     ShouldNotReachHere();
 139     return -1;
 140   }
 141 }
 142 
 143 int LinearScan::reg_numHi(LIR_Opr opr) {
 144   assert(opr->is_register(), "should not call this otherwise");
 145 
 146   if (opr->is_virtual_register()) {
 147     return -1;
 148   } else if (opr->is_single_cpu()) {
 149     return -1;
 150   } else if (opr->is_double_cpu()) {
 151     return opr->cpu_regnrHi();
 152 #ifdef X86
 153   } else if (opr->is_single_xmm()) {
 154     return -1;
 155   } else if (opr->is_double_xmm()) {
 156     return -1;
 157 #endif
 158   } else if (opr->is_single_fpu()) {
 159     return -1;
 160   } else if (opr->is_double_fpu()) {
 161     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 162   } else {
 163     ShouldNotReachHere();
 164     return -1;
 165   }
 166 }
 167 
 168 
 169 // ********** functions for classification of intervals
 170 
 171 bool LinearScan::is_precolored_interval(const Interval* i) {
 172   return i->reg_num() < LinearScan::nof_regs;
 173 }
 174 
 175 bool LinearScan::is_virtual_interval(const Interval* i) {
 176   return i->reg_num() >= LIR_OprDesc::vreg_base;
 177 }
 178 
 179 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 180   return i->reg_num() < LinearScan::nof_cpu_regs;
 181 }
 182 
 183 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 184 #if defined(__SOFTFP__) || defined(E500V2)
 185   return i->reg_num() >= LIR_OprDesc::vreg_base;
 186 #else
 187   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 188 #endif // __SOFTFP__ or E500V2
 189 }
 190 
 191 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 192   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 193 }
 194 
 195 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 196 #if defined(__SOFTFP__) || defined(E500V2)
 197   return false;
 198 #else
 199   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 200 #endif // __SOFTFP__ or E500V2
 201 }
 202 
 203 bool LinearScan::is_in_fpu_register(const Interval* i) {
 204   // fixed intervals not needed for FPU stack allocation
 205   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 206 }
 207 
 208 bool LinearScan::is_oop_interval(const Interval* i) {
 209   // fixed intervals never contain oops
 210   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 211 }
 212 
 213 
 214 // ********** General helper functions
 215 
 216 // compute next unused stack index that can be used for spilling
 217 int LinearScan::allocate_spill_slot(bool double_word) {
 218   int spill_slot;
 219   if (double_word) {
 220     if ((_max_spills & 1) == 1) {
 221       // alignment of double-word values
 222       // the hole because of the alignment is filled with the next single-word value
 223       assert(_unused_spill_slot == -1, "wasting a spill slot");
 224       _unused_spill_slot = _max_spills;
 225       _max_spills++;
 226     }
 227     spill_slot = _max_spills;
 228     _max_spills += 2;
 229 
 230   } else if (_unused_spill_slot != -1) {
 231     // re-use hole that was the result of a previous double-word alignment
 232     spill_slot = _unused_spill_slot;
 233     _unused_spill_slot = -1;
 234 
 235   } else {
 236     spill_slot = _max_spills;
 237     _max_spills++;
 238   }
 239 
 240   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 241 
 242   // if too many slots used, bailout compilation.
 243   if (result > 2000) {
 244     bailout("too many stack slots used");
 245   }
 246 
 247   return result;
 248 }
 249 
 250 void LinearScan::assign_spill_slot(Interval* it) {
 251   // assign the canonical spill slot of the parent (if a part of the interval
 252   // is already spilled) or allocate a new spill slot
 253   if (it->canonical_spill_slot() >= 0) {
 254     it->assign_reg(it->canonical_spill_slot());
 255   } else {
 256     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 257     it->set_canonical_spill_slot(spill);
 258     it->assign_reg(spill);
 259   }
 260 }
 261 
 262 void LinearScan::propagate_spill_slots() {
 263   if (!frame_map()->finalize_frame(max_spills())) {
 264     bailout("frame too large");
 265   }
 266 }
 267 
 268 // create a new interval with a predefined reg_num
 269 // (only used for parent intervals that are created during the building phase)
 270 Interval* LinearScan::create_interval(int reg_num) {
 271   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 272 
 273   Interval* interval = new Interval(reg_num);
 274   _intervals.at_put(reg_num, interval);
 275 
 276   // assign register number for precolored intervals
 277   if (reg_num < LIR_OprDesc::vreg_base) {
 278     interval->assign_reg(reg_num);
 279   }
 280   return interval;
 281 }
 282 
 283 // assign a new reg_num to the interval and append it to the list of intervals
 284 // (only used for child intervals that are created during register allocation)
 285 void LinearScan::append_interval(Interval* it) {
 286   it->set_reg_num(_intervals.length());
 287   _intervals.append(it);
 288   IntervalList* new_intervals = _new_intervals_from_allocation;
 289   if (new_intervals == NULL) {
 290     new_intervals = _new_intervals_from_allocation = new IntervalList();
 291   }
 292   new_intervals->append(it);
 293 }
 294 
 295 // copy the vreg-flags if an interval is split
 296 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 297   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 298     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 299   }
 300   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 301     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 302   }
 303 
 304   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 305   //       intervals (only the very beginning of the interval must be in memory)
 306 }
 307 
 308 
 309 // ********** spill move optimization
 310 // eliminate moves from register to stack if stack slot is known to be correct
 311 
 312 // called during building of intervals
 313 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 314   assert(interval->is_split_parent(), "can only be called for split parents");
 315 
 316   switch (interval->spill_state()) {
 317     case noDefinitionFound:
 318       assert(interval->spill_definition_pos() == -1, "must no be set before");
 319       interval->set_spill_definition_pos(def_pos);
 320       interval->set_spill_state(oneDefinitionFound);
 321       break;
 322 
 323     case oneDefinitionFound:
 324       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 325       if (def_pos < interval->spill_definition_pos() - 2) {
 326         // second definition found, so no spill optimization possible for this interval
 327         interval->set_spill_state(noOptimization);
 328       } else {
 329         // two consecutive definitions (because of two-operand LIR form)
 330         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 331       }
 332       break;
 333 
 334     case noOptimization:
 335       // nothing to do
 336       break;
 337 
 338     default:
 339       assert(false, "other states not allowed at this time");
 340   }
 341 }
 342 
 343 // called during register allocation
 344 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 345   switch (interval->spill_state()) {
 346     case oneDefinitionFound: {
 347       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 348       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 349 
 350       if (def_loop_depth < spill_loop_depth) {
 351         // the loop depth of the spilling position is higher then the loop depth
 352         // at the definition of the interval -> move write to memory out of loop
 353         // by storing at definitin of the interval
 354         interval->set_spill_state(storeAtDefinition);
 355       } else {
 356         // the interval is currently spilled only once, so for now there is no
 357         // reason to store the interval at the definition
 358         interval->set_spill_state(oneMoveInserted);
 359       }
 360       break;
 361     }
 362 
 363     case oneMoveInserted: {
 364       // the interval is spilled more then once, so it is better to store it to
 365       // memory at the definition
 366       interval->set_spill_state(storeAtDefinition);
 367       break;
 368     }
 369 
 370     case storeAtDefinition:
 371     case startInMemory:
 372     case noOptimization:
 373     case noDefinitionFound:
 374       // nothing to do
 375       break;
 376 
 377     default:
 378       assert(false, "other states not allowed at this time");
 379   }
 380 }
 381 
 382 
 383 bool LinearScan::must_store_at_definition(const Interval* i) {
 384   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 385 }
 386 
 387 // called once before asignment of register numbers
 388 void LinearScan::eliminate_spill_moves() {
 389   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 390   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 391 
 392   // collect all intervals that must be stored after their definion.
 393   // the list is sorted by Interval::spill_definition_pos
 394   Interval* interval;
 395   Interval* temp_list;
 396   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 397 
 398 #ifdef ASSERT
 399   Interval* prev = NULL;
 400   Interval* temp = interval;
 401   while (temp != Interval::end()) {
 402     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 403     if (prev != NULL) {
 404       assert(temp->from() >= prev->from(), "intervals not sorted");
 405       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 406     }
 407 
 408     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 409     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 410     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 411 
 412     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 413 
 414     temp = temp->next();
 415   }
 416 #endif
 417 
 418   LIR_InsertionBuffer insertion_buffer;
 419   int num_blocks = block_count();
 420   for (int i = 0; i < num_blocks; i++) {
 421     BlockBegin* block = block_at(i);
 422     LIR_OpList* instructions = block->lir()->instructions_list();
 423     int         num_inst = instructions->length();
 424     bool        has_new = false;
 425 
 426     // iterate all instructions of the block. skip the first because it is always a label
 427     for (int j = 1; j < num_inst; j++) {
 428       LIR_Op* op = instructions->at(j);
 429       int op_id = op->id();
 430 
 431       if (op_id == -1) {
 432         // remove move from register to stack if the stack slot is guaranteed to be correct.
 433         // only moves that have been inserted by LinearScan can be removed.
 434         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 435         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 436         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 437 
 438         LIR_Op1* op1 = (LIR_Op1*)op;
 439         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 440 
 441         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 442           // move target is a stack slot that is always correct, so eliminate instruction
 443           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 444           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 445         }
 446 
 447       } else {
 448         // insert move from register to stack just after the beginning of the interval
 449         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 450         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 451 
 452         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 453           if (!has_new) {
 454             // prepare insertion buffer (appended when all instructions of the block are processed)
 455             insertion_buffer.init(block->lir());
 456             has_new = true;
 457           }
 458 
 459           LIR_Opr from_opr = operand_for_interval(interval);
 460           LIR_Opr to_opr = canonical_spill_opr(interval);
 461           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 462           assert(to_opr->is_stack(), "to operand must be a stack slot");
 463 
 464           insertion_buffer.move(j, from_opr, to_opr);
 465           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 466 
 467           interval = interval->next();
 468         }
 469       }
 470     } // end of instruction iteration
 471 
 472     if (has_new) {
 473       block->lir()->append(&insertion_buffer);
 474     }
 475   } // end of block iteration
 476 
 477   assert(interval == Interval::end(), "missed an interval");
 478 }
 479 
 480 
 481 // ********** Phase 1: number all instructions in all blocks
 482 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 483 
 484 void LinearScan::number_instructions() {
 485   {
 486     // dummy-timer to measure the cost of the timer itself
 487     // (this time is then subtracted from all other timers to get the real value)
 488     TIME_LINEAR_SCAN(timer_do_nothing);
 489   }
 490   TIME_LINEAR_SCAN(timer_number_instructions);
 491 
 492   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 493   int num_blocks = block_count();
 494   int num_instructions = 0;
 495   int i;
 496   for (i = 0; i < num_blocks; i++) {
 497     num_instructions += block_at(i)->lir()->instructions_list()->length();
 498   }
 499 
 500   // initialize with correct length
 501   _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
 502   _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
 503 
 504   int op_id = 0;
 505   int idx = 0;
 506 
 507   for (i = 0; i < num_blocks; i++) {
 508     BlockBegin* block = block_at(i);
 509     block->set_first_lir_instruction_id(op_id);
 510     LIR_OpList* instructions = block->lir()->instructions_list();
 511 
 512     int num_inst = instructions->length();
 513     for (int j = 0; j < num_inst; j++) {
 514       LIR_Op* op = instructions->at(j);
 515       op->set_id(op_id);
 516 
 517       _lir_ops.at_put(idx, op);
 518       _block_of_op.at_put(idx, block);
 519       assert(lir_op_with_id(op_id) == op, "must match");
 520 
 521       idx++;
 522       op_id += 2; // numbering of lir_ops by two
 523     }
 524     block->set_last_lir_instruction_id(op_id - 2);
 525   }
 526   assert(idx == num_instructions, "must match");
 527   assert(idx * 2 == op_id, "must match");
 528 
 529   _has_call.initialize(num_instructions);
 530   _has_info.initialize(num_instructions);
 531 }
 532 
 533 
 534 // ********** Phase 2: compute local live sets separately for each block
 535 // (sets live_gen and live_kill for each block)
 536 
 537 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 538   LIR_Opr opr = value->operand();
 539   Constant* con = value->as_Constant();
 540 
 541   // check some asumptions about debug information
 542   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 543   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 544   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 545 
 546   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 547     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 548     int reg = opr->vreg_number();
 549     if (!live_kill.at(reg)) {
 550       live_gen.set_bit(reg);
 551       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 552     }
 553   }
 554 }
 555 
 556 
 557 void LinearScan::compute_local_live_sets() {
 558   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 559 
 560   int  num_blocks = block_count();
 561   int  live_size = live_set_size();
 562   bool local_has_fpu_registers = false;
 563   int  local_num_calls = 0;
 564   LIR_OpVisitState visitor;
 565 
 566   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 567 
 568   // iterate all blocks
 569   for (int i = 0; i < num_blocks; i++) {
 570     BlockBegin* block = block_at(i);
 571 
 572     ResourceBitMap live_gen(live_size);
 573     ResourceBitMap live_kill(live_size);
 574 
 575     if (block->is_set(BlockBegin::exception_entry_flag)) {
 576       // Phi functions at the begin of an exception handler are
 577       // implicitly defined (= killed) at the beginning of the block.
 578       for_each_phi_fun(block, phi,
 579         if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
 580       );
 581     }
 582 
 583     LIR_OpList* instructions = block->lir()->instructions_list();
 584     int num_inst = instructions->length();
 585 
 586     // iterate all instructions of the block. skip the first because it is always a label
 587     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 588     for (int j = 1; j < num_inst; j++) {
 589       LIR_Op* op = instructions->at(j);
 590 
 591       // visit operation to collect all operands
 592       visitor.visit(op);
 593 
 594       if (visitor.has_call()) {
 595         _has_call.set_bit(op->id() >> 1);
 596         local_num_calls++;
 597       }
 598       if (visitor.info_count() > 0) {
 599         _has_info.set_bit(op->id() >> 1);
 600       }
 601 
 602       // iterate input operands of instruction
 603       int k, n, reg;
 604       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 605       for (k = 0; k < n; k++) {
 606         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 607         assert(opr->is_register(), "visitor should only return register operands");
 608 
 609         if (opr->is_virtual_register()) {
 610           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 611           reg = opr->vreg_number();
 612           if (!live_kill.at(reg)) {
 613             live_gen.set_bit(reg);
 614             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 615           }
 616           if (block->loop_index() >= 0) {
 617             local_interval_in_loop.set_bit(reg, block->loop_index());
 618           }
 619           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 620         }
 621 
 622 #ifdef ASSERT
 623         // fixed intervals are never live at block boundaries, so
 624         // they need not be processed in live sets.
 625         // this is checked by these assertions to be sure about it.
 626         // the entry block may have incoming values in registers, which is ok.
 627         if (!opr->is_virtual_register() && block != ir()->start()) {
 628           reg = reg_num(opr);
 629           if (is_processed_reg_num(reg)) {
 630             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 631           }
 632           reg = reg_numHi(opr);
 633           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 634             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 635           }
 636         }
 637 #endif
 638       }
 639 
 640       // Add uses of live locals from interpreter's point of view for proper debug information generation
 641       n = visitor.info_count();
 642       for (k = 0; k < n; k++) {
 643         CodeEmitInfo* info = visitor.info_at(k);
 644         ValueStack* stack = info->stack();
 645         for_each_state_value(stack, value,
 646           set_live_gen_kill(value, op, live_gen, live_kill);
 647           local_has_fpu_registers = local_has_fpu_registers || value->type()->is_float_kind();
 648         );
 649       }
 650 
 651       // iterate temp operands of instruction
 652       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 653       for (k = 0; k < n; k++) {
 654         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 655         assert(opr->is_register(), "visitor should only return register operands");
 656 
 657         if (opr->is_virtual_register()) {
 658           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 659           reg = opr->vreg_number();
 660           live_kill.set_bit(reg);
 661           if (block->loop_index() >= 0) {
 662             local_interval_in_loop.set_bit(reg, block->loop_index());
 663           }
 664           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 665         }
 666 
 667 #ifdef ASSERT
 668         // fixed intervals are never live at block boundaries, so
 669         // they need not be processed in live sets
 670         // process them only in debug mode so that this can be checked
 671         if (!opr->is_virtual_register()) {
 672           reg = reg_num(opr);
 673           if (is_processed_reg_num(reg)) {
 674             live_kill.set_bit(reg_num(opr));
 675           }
 676           reg = reg_numHi(opr);
 677           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 678             live_kill.set_bit(reg);
 679           }
 680         }
 681 #endif
 682       }
 683 
 684       // iterate output operands of instruction
 685       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 686       for (k = 0; k < n; k++) {
 687         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 688         assert(opr->is_register(), "visitor should only return register operands");
 689 
 690         if (opr->is_virtual_register()) {
 691           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 692           reg = opr->vreg_number();
 693           live_kill.set_bit(reg);
 694           if (block->loop_index() >= 0) {
 695             local_interval_in_loop.set_bit(reg, block->loop_index());
 696           }
 697           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 698         }
 699 
 700 #ifdef ASSERT
 701         // fixed intervals are never live at block boundaries, so
 702         // they need not be processed in live sets
 703         // process them only in debug mode so that this can be checked
 704         if (!opr->is_virtual_register()) {
 705           reg = reg_num(opr);
 706           if (is_processed_reg_num(reg)) {
 707             live_kill.set_bit(reg_num(opr));
 708           }
 709           reg = reg_numHi(opr);
 710           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 711             live_kill.set_bit(reg);
 712           }
 713         }
 714 #endif
 715       }
 716     } // end of instruction iteration
 717 
 718     block->set_live_gen (live_gen);
 719     block->set_live_kill(live_kill);
 720     block->set_live_in  (ResourceBitMap(live_size));
 721     block->set_live_out (ResourceBitMap(live_size));
 722 
 723     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 724     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 725   } // end of block iteration
 726 
 727   // propagate local calculated information into LinearScan object
 728   _has_fpu_registers = local_has_fpu_registers;
 729   compilation()->set_has_fpu_code(local_has_fpu_registers);
 730 
 731   _num_calls = local_num_calls;
 732   _interval_in_loop = local_interval_in_loop;
 733 }
 734 
 735 
 736 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 737 // (sets live_in and live_out for each block)
 738 
 739 void LinearScan::compute_global_live_sets() {
 740   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 741 
 742   int  num_blocks = block_count();
 743   bool change_occurred;
 744   bool change_occurred_in_block;
 745   int  iteration_count = 0;
 746   ResourceBitMap live_out(live_set_size()); // scratch set for calculations
 747 
 748   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 749   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 750   // Exception handlers must be processed because not all live values are
 751   // present in the state array, e.g. because of global value numbering
 752   do {
 753     change_occurred = false;
 754 
 755     // iterate all blocks in reverse order
 756     for (int i = num_blocks - 1; i >= 0; i--) {
 757       BlockBegin* block = block_at(i);
 758 
 759       change_occurred_in_block = false;
 760 
 761       // live_out(block) is the union of live_in(sux), for successors sux of block
 762       int n = block->number_of_sux();
 763       int e = block->number_of_exception_handlers();
 764       if (n + e > 0) {
 765         // block has successors
 766         if (n > 0) {
 767           live_out.set_from(block->sux_at(0)->live_in());
 768           for (int j = 1; j < n; j++) {
 769             live_out.set_union(block->sux_at(j)->live_in());
 770           }
 771         } else {
 772           live_out.clear();
 773         }
 774         for (int j = 0; j < e; j++) {
 775           live_out.set_union(block->exception_handler_at(j)->live_in());
 776         }
 777 
 778         if (!block->live_out().is_same(live_out)) {
 779           // A change occurred.  Swap the old and new live out sets to avoid copying.
 780           ResourceBitMap temp = block->live_out();
 781           block->set_live_out(live_out);
 782           live_out = temp;
 783 
 784           change_occurred = true;
 785           change_occurred_in_block = true;
 786         }
 787       }
 788 
 789       if (iteration_count == 0 || change_occurred_in_block) {
 790         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 791         // note: live_in has to be computed only in first iteration or if live_out has changed!
 792         ResourceBitMap live_in = block->live_in();
 793         live_in.set_from(block->live_out());
 794         live_in.set_difference(block->live_kill());
 795         live_in.set_union(block->live_gen());
 796       }
 797 
 798 #ifdef ASSERT
 799       if (TraceLinearScanLevel >= 4) {
 800         char c = ' ';
 801         if (iteration_count == 0 || change_occurred_in_block) {
 802           c = '*';
 803         }
 804         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 805         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 806       }
 807 #endif
 808     }
 809     iteration_count++;
 810 
 811     if (change_occurred && iteration_count > 50) {
 812       BAILOUT("too many iterations in compute_global_live_sets");
 813     }
 814   } while (change_occurred);
 815 
 816 
 817 #ifdef ASSERT
 818   // check that fixed intervals are not live at block boundaries
 819   // (live set must be empty at fixed intervals)
 820   for (int i = 0; i < num_blocks; i++) {
 821     BlockBegin* block = block_at(i);
 822     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 823       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 824       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 825       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 826     }
 827   }
 828 #endif
 829 
 830   // check that the live_in set of the first block is empty
 831   ResourceBitMap live_in_args(ir()->start()->live_in().size());
 832   if (!ir()->start()->live_in().is_same(live_in_args)) {
 833 #ifdef ASSERT
 834     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 835     tty->print_cr("affected registers:");
 836     print_bitmap(ir()->start()->live_in());
 837 
 838     // print some additional information to simplify debugging
 839     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 840       if (ir()->start()->live_in().at(i)) {
 841         Instruction* instr = gen()->instruction_for_vreg(i);
 842         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 843 
 844         for (int j = 0; j < num_blocks; j++) {
 845           BlockBegin* block = block_at(j);
 846           if (block->live_gen().at(i)) {
 847             tty->print_cr("  used in block B%d", block->block_id());
 848           }
 849           if (block->live_kill().at(i)) {
 850             tty->print_cr("  defined in block B%d", block->block_id());
 851           }
 852         }
 853       }
 854     }
 855 
 856 #endif
 857     // when this fails, virtual registers are used before they are defined.
 858     assert(false, "live_in set of first block must be empty");
 859     // bailout of if this occurs in product mode.
 860     bailout("live_in set of first block not empty");
 861   }
 862 }
 863 
 864 
 865 // ********** Phase 4: build intervals
 866 // (fills the list _intervals)
 867 
 868 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 869   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 870   LIR_Opr opr = value->operand();
 871   Constant* con = value->as_Constant();
 872 
 873   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 874     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 875     add_use(opr, from, to, use_kind);
 876   }
 877 }
 878 
 879 
 880 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 881   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 882   assert(opr->is_register(), "should not be called otherwise");
 883 
 884   if (opr->is_virtual_register()) {
 885     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 886     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 887 
 888   } else {
 889     int reg = reg_num(opr);
 890     if (is_processed_reg_num(reg)) {
 891       add_def(reg, def_pos, use_kind, opr->type_register());
 892     }
 893     reg = reg_numHi(opr);
 894     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 895       add_def(reg, def_pos, use_kind, opr->type_register());
 896     }
 897   }
 898 }
 899 
 900 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 901   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 902   assert(opr->is_register(), "should not be called otherwise");
 903 
 904   if (opr->is_virtual_register()) {
 905     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 906     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 907 
 908   } else {
 909     int reg = reg_num(opr);
 910     if (is_processed_reg_num(reg)) {
 911       add_use(reg, from, to, use_kind, opr->type_register());
 912     }
 913     reg = reg_numHi(opr);
 914     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 915       add_use(reg, from, to, use_kind, opr->type_register());
 916     }
 917   }
 918 }
 919 
 920 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 921   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 922   assert(opr->is_register(), "should not be called otherwise");
 923 
 924   if (opr->is_virtual_register()) {
 925     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 926     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 927 
 928   } else {
 929     int reg = reg_num(opr);
 930     if (is_processed_reg_num(reg)) {
 931       add_temp(reg, temp_pos, use_kind, opr->type_register());
 932     }
 933     reg = reg_numHi(opr);
 934     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 935       add_temp(reg, temp_pos, use_kind, opr->type_register());
 936     }
 937   }
 938 }
 939 
 940 
 941 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 942   Interval* interval = interval_at(reg_num);
 943   if (interval != NULL) {
 944     assert(interval->reg_num() == reg_num, "wrong interval");
 945 
 946     if (type != T_ILLEGAL) {
 947       interval->set_type(type);
 948     }
 949 
 950     Range* r = interval->first();
 951     if (r->from() <= def_pos) {
 952       // Update the starting point (when a range is first created for a use, its
 953       // start is the beginning of the current block until a def is encountered.)
 954       r->set_from(def_pos);
 955       interval->add_use_pos(def_pos, use_kind);
 956 
 957     } else {
 958       // Dead value - make vacuous interval
 959       // also add use_kind for dead intervals
 960       interval->add_range(def_pos, def_pos + 1);
 961       interval->add_use_pos(def_pos, use_kind);
 962       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 963     }
 964 
 965   } else {
 966     // Dead value - make vacuous interval
 967     // also add use_kind for dead intervals
 968     interval = create_interval(reg_num);
 969     if (type != T_ILLEGAL) {
 970       interval->set_type(type);
 971     }
 972 
 973     interval->add_range(def_pos, def_pos + 1);
 974     interval->add_use_pos(def_pos, use_kind);
 975     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 976   }
 977 
 978   change_spill_definition_pos(interval, def_pos);
 979   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 980         // detection of method-parameters and roundfp-results
 981         // TODO: move this directly to position where use-kind is computed
 982     interval->set_spill_state(startInMemory);
 983   }
 984 }
 985 
 986 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 987   Interval* interval = interval_at(reg_num);
 988   if (interval == NULL) {
 989     interval = create_interval(reg_num);
 990   }
 991   assert(interval->reg_num() == reg_num, "wrong interval");
 992 
 993   if (type != T_ILLEGAL) {
 994     interval->set_type(type);
 995   }
 996 
 997   interval->add_range(from, to);
 998   interval->add_use_pos(to, use_kind);
 999 }
1000 
1001 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1002   Interval* interval = interval_at(reg_num);
1003   if (interval == NULL) {
1004     interval = create_interval(reg_num);
1005   }
1006   assert(interval->reg_num() == reg_num, "wrong interval");
1007 
1008   if (type != T_ILLEGAL) {
1009     interval->set_type(type);
1010   }
1011 
1012   interval->add_range(temp_pos, temp_pos + 1);
1013   interval->add_use_pos(temp_pos, use_kind);
1014 }
1015 
1016 
1017 // the results of this functions are used for optimizing spilling and reloading
1018 // if the functions return shouldHaveRegister and the interval is spilled,
1019 // it is not reloaded to a register.
1020 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1021   if (op->code() == lir_move) {
1022     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1023     LIR_Op1* move = (LIR_Op1*)op;
1024     LIR_Opr res = move->result_opr();
1025     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1026 
1027     if (result_in_memory) {
1028       // Begin of an interval with must_start_in_memory set.
1029       // This interval will always get a stack slot first, so return noUse.
1030       return noUse;
1031 
1032     } else if (move->in_opr()->is_stack()) {
1033       // method argument (condition must be equal to handle_method_arguments)
1034       return noUse;
1035 
1036     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1037       // Move from register to register
1038       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1039         // special handling of phi-function moves inside osr-entry blocks
1040         // input operand must have a register instead of output operand (leads to better register allocation)
1041         return shouldHaveRegister;
1042       }
1043     }
1044   }
1045 
1046   if (opr->is_virtual() &&
1047       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1048     // result is a stack-slot, so prevent immediate reloading
1049     return noUse;
1050   }
1051 
1052   // all other operands require a register
1053   return mustHaveRegister;
1054 }
1055 
1056 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1057   if (op->code() == lir_move) {
1058     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1059     LIR_Op1* move = (LIR_Op1*)op;
1060     LIR_Opr res = move->result_opr();
1061     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1062 
1063     if (result_in_memory) {
1064       // Move to an interval with must_start_in_memory set.
1065       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1066       return mustHaveRegister;
1067 
1068     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1069       // Move from register to register
1070       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1071         // special handling of phi-function moves inside osr-entry blocks
1072         // input operand must have a register instead of output operand (leads to better register allocation)
1073         return mustHaveRegister;
1074       }
1075 
1076       // The input operand is not forced to a register (moves from stack to register are allowed),
1077       // but it is faster if the input operand is in a register
1078       return shouldHaveRegister;
1079     }
1080   }
1081 
1082 
1083 #if defined(X86) || defined(S390)
1084   if (op->code() == lir_cmove) {
1085     // conditional moves can handle stack operands
1086     assert(op->result_opr()->is_register(), "result must always be in a register");
1087     return shouldHaveRegister;
1088   }
1089 
1090   // optimizations for second input operand of arithmehtic operations on Intel
1091   // this operand is allowed to be on the stack in some cases
1092   BasicType opr_type = opr->type_register();
1093   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1094     if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1095       // SSE float instruction (T_DOUBLE only supported with SSE2)
1096       switch (op->code()) {
1097         case lir_cmp:
1098         case lir_add:
1099         case lir_sub:
1100         case lir_mul:
1101         case lir_div:
1102         {
1103           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1104           LIR_Op2* op2 = (LIR_Op2*)op;
1105           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1106             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1107             return shouldHaveRegister;
1108           }
1109         }
1110         default:
1111           break;
1112       }
1113     } else {
1114       // FPU stack float instruction
1115       switch (op->code()) {
1116         case lir_add:
1117         case lir_sub:
1118         case lir_mul:
1119         case lir_div:
1120         {
1121           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122           LIR_Op2* op2 = (LIR_Op2*)op;
1123           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125             return shouldHaveRegister;
1126           }
1127         }
1128         default:
1129           break;
1130       }
1131     }
1132     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1133     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1134     // T_OBJECT doesn't get spilled along with T_LONG.
1135   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1136     // integer instruction (note: long operands must always be in register)
1137     switch (op->code()) {
1138       case lir_cmp:
1139       case lir_add:
1140       case lir_sub:
1141       case lir_logic_and:
1142       case lir_logic_or:
1143       case lir_logic_xor:
1144       {
1145         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1146         LIR_Op2* op2 = (LIR_Op2*)op;
1147         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149           return shouldHaveRegister;
1150         }
1151       }
1152       default:
1153         break;
1154     }
1155   }
1156 #endif // X86 || S390
1157 
1158   // all other operands require a register
1159   return mustHaveRegister;
1160 }
1161 
1162 
1163 void LinearScan::handle_method_arguments(LIR_Op* op) {
1164   // special handling for method arguments (moves from stack to virtual register):
1165   // the interval gets no register assigned, but the stack slot.
1166   // it is split before the first use by the register allocator.
1167 
1168   if (op->code() == lir_move) {
1169     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1170     LIR_Op1* move = (LIR_Op1*)op;
1171 
1172     if (move->in_opr()->is_stack()) {
1173 #ifdef ASSERT
1174       int arg_size = compilation()->method()->arg_size();
1175       LIR_Opr o = move->in_opr();
1176       if (o->is_single_stack()) {
1177         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1178       } else if (o->is_double_stack()) {
1179         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1180       } else {
1181         ShouldNotReachHere();
1182       }
1183 
1184       assert(move->id() > 0, "invalid id");
1185       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1186       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1187 
1188       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1189 #endif
1190 
1191       Interval* interval = interval_at(reg_num(move->result_opr()));
1192 
1193       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1194       interval->set_canonical_spill_slot(stack_slot);
1195       interval->assign_reg(stack_slot);
1196     }
1197   }
1198 }
1199 
1200 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1201   // special handling for doubleword move from memory to register:
1202   // in this case the registers of the input address and the result
1203   // registers must not overlap -> add a temp range for the input registers
1204   if (op->code() == lir_move) {
1205     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1206     LIR_Op1* move = (LIR_Op1*)op;
1207 
1208     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1209       LIR_Address* address = move->in_opr()->as_address_ptr();
1210       if (address != NULL) {
1211         if (address->base()->is_valid()) {
1212           add_temp(address->base(), op->id(), noUse);
1213         }
1214         if (address->index()->is_valid()) {
1215           add_temp(address->index(), op->id(), noUse);
1216         }
1217       }
1218     }
1219   }
1220 }
1221 
1222 void LinearScan::add_register_hints(LIR_Op* op) {
1223   switch (op->code()) {
1224     case lir_move:      // fall through
1225     case lir_convert: {
1226       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1227       LIR_Op1* move = (LIR_Op1*)op;
1228 
1229       LIR_Opr move_from = move->in_opr();
1230       LIR_Opr move_to = move->result_opr();
1231 
1232       if (move_to->is_register() && move_from->is_register()) {
1233         Interval* from = interval_at(reg_num(move_from));
1234         Interval* to = interval_at(reg_num(move_to));
1235         if (from != NULL && to != NULL) {
1236           to->set_register_hint(from);
1237           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1238         }
1239       }
1240       break;
1241     }
1242     case lir_cmove: {
1243 #ifdef RISCV
1244       assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4");
1245       LIR_Op4* cmove = (LIR_Op4*)op;
1246 
1247       LIR_Opr move_from = cmove->in_opr3();
1248       LIR_Opr move_to   = cmove->in_opr4();
1249 #else
1250       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1251       LIR_Op2* cmove = (LIR_Op2*)op;
1252 
1253       LIR_Opr move_from = cmove->in_opr1();
1254       LIR_Opr move_to = cmove->result_opr();
1255 #endif
1256 
1257       if (move_to->is_register() && move_from->is_register()) {
1258         Interval* from = interval_at(reg_num(move_from));
1259         Interval* to = interval_at(reg_num(move_to));
1260         if (from != NULL && to != NULL) {
1261           to->set_register_hint(from);
1262           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1263         }
1264       }
1265       break;
1266     }
1267     default:
1268       break;
1269   }
1270 }
1271 
1272 
1273 void LinearScan::build_intervals() {
1274   TIME_LINEAR_SCAN(timer_build_intervals);
1275 
1276   // initialize interval list with expected number of intervals
1277   // (32 is added to have some space for split children without having to resize the list)
1278   _intervals = IntervalList(num_virtual_regs() + 32);
1279   // initialize all slots that are used by build_intervals
1280   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1281 
1282   // create a list with all caller-save registers (cpu, fpu, xmm)
1283   // when an instruction is a call, a temp range is created for all these registers
1284   int num_caller_save_registers = 0;
1285   int caller_save_registers[LinearScan::nof_regs];
1286 
1287   int i;
1288   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1289     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1290     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1291     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1292     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1293   }
1294 
1295   // temp ranges for fpu registers are only created when the method has
1296   // virtual fpu operands. Otherwise no allocation for fpu registers is
1297   // performed and so the temp ranges would be useless
1298   if (has_fpu_registers()) {
1299 #ifdef X86
1300     if (UseSSE < 2) {
1301 #endif // X86
1302       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1303         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1304         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1305         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1306         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1307       }
1308 #ifdef X86
1309     }
1310 #endif // X86
1311 
1312 #ifdef X86
1313     if (UseSSE > 0) {
1314       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1315       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1316         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1317         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1318         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1319         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1320       }
1321     }
1322 #endif // X86
1323   }
1324   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1325 
1326 
1327   LIR_OpVisitState visitor;
1328 
1329   // iterate all blocks in reverse order
1330   for (i = block_count() - 1; i >= 0; i--) {
1331     BlockBegin* block = block_at(i);
1332     LIR_OpList* instructions = block->lir()->instructions_list();
1333     int         block_from =   block->first_lir_instruction_id();
1334     int         block_to =     block->last_lir_instruction_id();
1335 
1336     assert(block_from == instructions->at(0)->id(), "must be");
1337     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1338 
1339     // Update intervals for registers live at the end of this block;
1340     ResourceBitMap live = block->live_out();
1341     int size = (int)live.size();
1342     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1343       assert(live.at(number), "should not stop here otherwise");
1344       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1345       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1346 
1347       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1348 
1349       // add special use positions for loop-end blocks when the
1350       // interval is used anywhere inside this loop.  It's possible
1351       // that the block was part of a non-natural loop, so it might
1352       // have an invalid loop index.
1353       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1354           block->loop_index() != -1 &&
1355           is_interval_in_loop(number, block->loop_index())) {
1356         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1357       }
1358     }
1359 
1360     // iterate all instructions of the block in reverse order.
1361     // skip the first instruction because it is always a label
1362     // definitions of intervals are processed before uses
1363     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1364     for (int j = instructions->length() - 1; j >= 1; j--) {
1365       LIR_Op* op = instructions->at(j);
1366       int op_id = op->id();
1367 
1368       // visit operation to collect all operands
1369       visitor.visit(op);
1370 
1371       // add a temp range for each register if operation destroys caller-save registers
1372       if (visitor.has_call()) {
1373         for (int k = 0; k < num_caller_save_registers; k++) {
1374           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1375         }
1376         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1377       }
1378 
1379       // Add any platform dependent temps
1380       pd_add_temps(op);
1381 
1382       // visit definitions (output and temp operands)
1383       int k, n;
1384       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1385       for (k = 0; k < n; k++) {
1386         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1387         assert(opr->is_register(), "visitor should only return register operands");
1388         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1389       }
1390 
1391       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1392       for (k = 0; k < n; k++) {
1393         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1394         assert(opr->is_register(), "visitor should only return register operands");
1395         add_temp(opr, op_id, mustHaveRegister);
1396       }
1397 
1398       // visit uses (input operands)
1399       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1400       for (k = 0; k < n; k++) {
1401         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1402         assert(opr->is_register(), "visitor should only return register operands");
1403         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1404       }
1405 
1406       // Add uses of live locals from interpreter's point of view for proper
1407       // debug information generation
1408       // Treat these operands as temp values (if the life range is extended
1409       // to a call site, the value would be in a register at the call otherwise)
1410       n = visitor.info_count();
1411       for (k = 0; k < n; k++) {
1412         CodeEmitInfo* info = visitor.info_at(k);
1413         ValueStack* stack = info->stack();
1414         for_each_state_value(stack, value,
1415           add_use(value, block_from, op_id + 1, noUse);
1416         );
1417       }
1418 
1419       // special steps for some instructions (especially moves)
1420       handle_method_arguments(op);
1421       handle_doubleword_moves(op);
1422       add_register_hints(op);
1423 
1424     } // end of instruction iteration
1425   } // end of block iteration
1426 
1427 
1428   // add the range [0, 1[ to all fixed intervals
1429   // -> the register allocator need not handle unhandled fixed intervals
1430   for (int n = 0; n < LinearScan::nof_regs; n++) {
1431     Interval* interval = interval_at(n);
1432     if (interval != NULL) {
1433       interval->add_range(0, 1);
1434     }
1435   }
1436 }
1437 
1438 
1439 // ********** Phase 5: actual register allocation
1440 
1441 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1442   if (*a != NULL) {
1443     if (*b != NULL) {
1444       return (*a)->from() - (*b)->from();
1445     } else {
1446       return -1;
1447     }
1448   } else {
1449     if (*b != NULL) {
1450       return 1;
1451     } else {
1452       return 0;
1453     }
1454   }
1455 }
1456 
1457 #ifndef PRODUCT
1458 int interval_cmp(Interval* const& l, Interval* const& r) {
1459   return l->from() - r->from();
1460 }
1461 
1462 bool find_interval(Interval* interval, IntervalArray* intervals) {
1463   bool found;
1464   int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1465 
1466   if (!found) {
1467     return false;
1468   }
1469 
1470   int from = interval->from();
1471 
1472   // The index we've found using binary search is pointing to an interval
1473   // that is defined in the same place as the interval we were looking for.
1474   // So now we have to look around that index and find exact interval.
1475   for (int i = idx; i >= 0; i--) {
1476     if (intervals->at(i) == interval) {
1477       return true;
1478     }
1479     if (intervals->at(i)->from() != from) {
1480       break;
1481     }
1482   }
1483 
1484   for (int i = idx + 1; i < intervals->length(); i++) {
1485     if (intervals->at(i) == interval) {
1486       return true;
1487     }
1488     if (intervals->at(i)->from() != from) {
1489       break;
1490     }
1491   }
1492 
1493   return false;
1494 }
1495 
1496 bool LinearScan::is_sorted(IntervalArray* intervals) {
1497   int from = -1;
1498   int null_count = 0;
1499 
1500   for (int i = 0; i < intervals->length(); i++) {
1501     Interval* it = intervals->at(i);
1502     if (it != NULL) {
1503       assert(from <= it->from(), "Intervals are unordered");
1504       from = it->from();
1505     } else {
1506       null_count++;
1507     }
1508   }
1509 
1510   assert(null_count == 0, "Sorted intervals should not contain nulls");
1511 
1512   null_count = 0;
1513 
1514   for (int i = 0; i < interval_count(); i++) {
1515     Interval* interval = interval_at(i);
1516     if (interval != NULL) {
1517       assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1518     } else {
1519       null_count++;
1520     }
1521   }
1522 
1523   assert(interval_count() - null_count == intervals->length(),
1524       "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1525 
1526   return true;
1527 }
1528 #endif
1529 
1530 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1531   if (*prev != NULL) {
1532     (*prev)->set_next(interval);
1533   } else {
1534     *first = interval;
1535   }
1536   *prev = interval;
1537 }
1538 
1539 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1540   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1541 
1542   *list1 = *list2 = Interval::end();
1543 
1544   Interval* list1_prev = NULL;
1545   Interval* list2_prev = NULL;
1546   Interval* v;
1547 
1548   const int n = _sorted_intervals->length();
1549   for (int i = 0; i < n; i++) {
1550     v = _sorted_intervals->at(i);
1551     if (v == NULL) continue;
1552 
1553     if (is_list1(v)) {
1554       add_to_list(list1, &list1_prev, v);
1555     } else if (is_list2 == NULL || is_list2(v)) {
1556       add_to_list(list2, &list2_prev, v);
1557     }
1558   }
1559 
1560   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1561   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1562 
1563   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1564   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1565 }
1566 
1567 
1568 void LinearScan::sort_intervals_before_allocation() {
1569   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1570 
1571   if (_needs_full_resort) {
1572     // There is no known reason why this should occur but just in case...
1573     assert(false, "should never occur");
1574     // Re-sort existing interval list because an Interval::from() has changed
1575     _sorted_intervals->sort(interval_cmp);
1576     _needs_full_resort = false;
1577   }
1578 
1579   IntervalList* unsorted_list = &_intervals;
1580   int unsorted_len = unsorted_list->length();
1581   int sorted_len = 0;
1582   int unsorted_idx;
1583   int sorted_idx = 0;
1584   int sorted_from_max = -1;
1585 
1586   // calc number of items for sorted list (sorted list must not contain NULL values)
1587   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1588     if (unsorted_list->at(unsorted_idx) != NULL) {
1589       sorted_len++;
1590     }
1591   }
1592   IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1593 
1594   // special sorting algorithm: the original interval-list is almost sorted,
1595   // only some intervals are swapped. So this is much faster than a complete QuickSort
1596   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1597     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1598 
1599     if (cur_interval != NULL) {
1600       int cur_from = cur_interval->from();
1601 
1602       if (sorted_from_max <= cur_from) {
1603         sorted_list->at_put(sorted_idx++, cur_interval);
1604         sorted_from_max = cur_interval->from();
1605       } else {
1606         // the asumption that the intervals are already sorted failed,
1607         // so this interval must be sorted in manually
1608         int j;
1609         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1610           sorted_list->at_put(j + 1, sorted_list->at(j));
1611         }
1612         sorted_list->at_put(j + 1, cur_interval);
1613         sorted_idx++;
1614       }
1615     }
1616   }
1617   _sorted_intervals = sorted_list;
1618   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1619 }
1620 
1621 void LinearScan::sort_intervals_after_allocation() {
1622   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1623 
1624   if (_needs_full_resort) {
1625     // Re-sort existing interval list because an Interval::from() has changed
1626     _sorted_intervals->sort(interval_cmp);
1627     _needs_full_resort = false;
1628   }
1629 
1630   IntervalArray* old_list = _sorted_intervals;
1631   IntervalList* new_list = _new_intervals_from_allocation;
1632   int old_len = old_list->length();
1633   int new_len = new_list == NULL ? 0 : new_list->length();
1634 
1635   if (new_len == 0) {
1636     // no intervals have been added during allocation, so sorted list is already up to date
1637     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1638     return;
1639   }
1640 
1641   // conventional sort-algorithm for new intervals
1642   new_list->sort(interval_cmp);
1643 
1644   // merge old and new list (both already sorted) into one combined list
1645   int combined_list_len = old_len + new_len;
1646   IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1647   int old_idx = 0;
1648   int new_idx = 0;
1649 
1650   while (old_idx + new_idx < old_len + new_len) {
1651     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1652       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1653       old_idx++;
1654     } else {
1655       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1656       new_idx++;
1657     }
1658   }
1659 
1660   _sorted_intervals = combined_list;
1661   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1662 }
1663 
1664 
1665 void LinearScan::allocate_registers() {
1666   TIME_LINEAR_SCAN(timer_allocate_registers);
1667 
1668   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1669   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1670 
1671   // collect cpu intervals
1672   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1673                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1674 
1675   // collect fpu intervals
1676   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1677                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1678   // this fpu interval collection cannot be moved down below with the allocation section as
1679   // the cpu_lsw.walk() changes interval positions.
1680 
1681   if (!has_fpu_registers()) {
1682 #ifdef ASSERT
1683     assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1684 #else
1685     if (not_precolored_fpu_intervals != Interval::end()) {
1686       BAILOUT("missed an uncolored fpu interval");
1687     }
1688 #endif
1689   }
1690 
1691   // allocate cpu registers
1692   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1693   cpu_lsw.walk();
1694   cpu_lsw.finish_allocation();
1695 
1696   if (has_fpu_registers()) {
1697     // allocate fpu registers
1698     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1699     fpu_lsw.walk();
1700     fpu_lsw.finish_allocation();
1701   }
1702 }
1703 
1704 
1705 // ********** Phase 6: resolve data flow
1706 // (insert moves at edges between blocks if intervals have been split)
1707 
1708 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1709 // instead of returning NULL
1710 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1711   Interval* result = interval->split_child_at_op_id(op_id, mode);
1712   if (result != NULL) {
1713     return result;
1714   }
1715 
1716   assert(false, "must find an interval, but do a clean bailout in product mode");
1717   result = new Interval(LIR_OprDesc::vreg_base);
1718   result->assign_reg(0);
1719   result->set_type(T_INT);
1720   BAILOUT_("LinearScan: interval is NULL", result);
1721 }
1722 
1723 
1724 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1725   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1726   assert(interval_at(reg_num) != NULL, "no interval found");
1727 
1728   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1729 }
1730 
1731 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1732   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1733   assert(interval_at(reg_num) != NULL, "no interval found");
1734 
1735   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1736 }
1737 
1738 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1739   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1740   assert(interval_at(reg_num) != NULL, "no interval found");
1741 
1742   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1743 }
1744 
1745 
1746 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1747   DEBUG_ONLY(move_resolver.check_empty());
1748 
1749   const int size = live_set_size();
1750   const ResourceBitMap live_at_edge = to_block->live_in();
1751 
1752   // visit all registers where the live_at_edge bit is set
1753   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1754     assert(r < num_virtual_regs(), "live information set for not exisiting interval");
1755     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1756 
1757     Interval* from_interval = interval_at_block_end(from_block, r);
1758     Interval* to_interval = interval_at_block_begin(to_block, r);
1759 
1760     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1761       // need to insert move instruction
1762       move_resolver.add_mapping(from_interval, to_interval);
1763     }
1764   }
1765 }
1766 
1767 
1768 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1769   if (from_block->number_of_sux() <= 1) {
1770     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1771 
1772     LIR_OpList* instructions = from_block->lir()->instructions_list();
1773     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1774     if (branch != NULL) {
1775       // insert moves before branch
1776       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1777       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1778     } else {
1779       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1780     }
1781 
1782   } else {
1783     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1784 #ifdef ASSERT
1785     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1786 
1787     // because the number of predecessor edges matches the number of
1788     // successor edges, blocks which are reached by switch statements
1789     // may have be more than one predecessor but it will be guaranteed
1790     // that all predecessors will be the same.
1791     for (int i = 0; i < to_block->number_of_preds(); i++) {
1792       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1793     }
1794 #endif
1795 
1796     move_resolver.set_insert_position(to_block->lir(), 0);
1797   }
1798 }
1799 
1800 
1801 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1802 void LinearScan::resolve_data_flow() {
1803   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1804 
1805   int num_blocks = block_count();
1806   MoveResolver move_resolver(this);
1807   ResourceBitMap block_completed(num_blocks);
1808   ResourceBitMap already_resolved(num_blocks);
1809 
1810   int i;
1811   for (i = 0; i < num_blocks; i++) {
1812     BlockBegin* block = block_at(i);
1813 
1814     // check if block has only one predecessor and only one successor
1815     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1816       LIR_OpList* instructions = block->lir()->instructions_list();
1817       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1818       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1819       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1820 
1821       // check if block is empty (only label and branch)
1822       if (instructions->length() == 2) {
1823         BlockBegin* pred = block->pred_at(0);
1824         BlockBegin* sux = block->sux_at(0);
1825 
1826         // prevent optimization of two consecutive blocks
1827         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1828           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1829           block_completed.set_bit(block->linear_scan_number());
1830 
1831           // directly resolve between pred and sux (without looking at the empty block between)
1832           resolve_collect_mappings(pred, sux, move_resolver);
1833           if (move_resolver.has_mappings()) {
1834             move_resolver.set_insert_position(block->lir(), 0);
1835             move_resolver.resolve_and_append_moves();
1836           }
1837         }
1838       }
1839     }
1840   }
1841 
1842 
1843   for (i = 0; i < num_blocks; i++) {
1844     if (!block_completed.at(i)) {
1845       BlockBegin* from_block = block_at(i);
1846       already_resolved.set_from(block_completed);
1847 
1848       int num_sux = from_block->number_of_sux();
1849       for (int s = 0; s < num_sux; s++) {
1850         BlockBegin* to_block = from_block->sux_at(s);
1851 
1852         // check for duplicate edges between the same blocks (can happen with switch blocks)
1853         if (!already_resolved.at(to_block->linear_scan_number())) {
1854           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1855           already_resolved.set_bit(to_block->linear_scan_number());
1856 
1857           // collect all intervals that have been split between from_block and to_block
1858           resolve_collect_mappings(from_block, to_block, move_resolver);
1859           if (move_resolver.has_mappings()) {
1860             resolve_find_insert_pos(from_block, to_block, move_resolver);
1861             move_resolver.resolve_and_append_moves();
1862           }
1863         }
1864       }
1865     }
1866   }
1867 }
1868 
1869 
1870 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1871   if (interval_at(reg_num) == NULL) {
1872     // if a phi function is never used, no interval is created -> ignore this
1873     return;
1874   }
1875 
1876   Interval* interval = interval_at_block_begin(block, reg_num);
1877   int reg = interval->assigned_reg();
1878   int regHi = interval->assigned_regHi();
1879 
1880   if ((reg < nof_regs && interval->always_in_memory()) ||
1881       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1882     // the interval is split to get a short range that is located on the stack
1883     // in the following two cases:
1884     // * the interval started in memory (e.g. method parameter), but is currently in a register
1885     //   this is an optimization for exception handling that reduces the number of moves that
1886     //   are necessary for resolving the states when an exception uses this exception handler
1887     // * the interval would be on the fpu stack at the begin of the exception handler
1888     //   this is not allowed because of the complicated fpu stack handling on Intel
1889 
1890     // range that will be spilled to memory
1891     int from_op_id = block->first_lir_instruction_id();
1892     int to_op_id = from_op_id + 1;  // short live range of length 1
1893     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1894            "no split allowed between exception entry and first instruction");
1895 
1896     if (interval->from() != from_op_id) {
1897       // the part before from_op_id is unchanged
1898       interval = interval->split(from_op_id);
1899       interval->assign_reg(reg, regHi);
1900       append_interval(interval);
1901     } else {
1902       _needs_full_resort = true;
1903     }
1904     assert(interval->from() == from_op_id, "must be true now");
1905 
1906     Interval* spilled_part = interval;
1907     if (interval->to() != to_op_id) {
1908       // the part after to_op_id is unchanged
1909       spilled_part = interval->split_from_start(to_op_id);
1910       append_interval(spilled_part);
1911       move_resolver.add_mapping(spilled_part, interval);
1912     }
1913     assign_spill_slot(spilled_part);
1914 
1915     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1916   }
1917 }
1918 
1919 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1920   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1921   DEBUG_ONLY(move_resolver.check_empty());
1922 
1923   // visit all registers where the live_in bit is set
1924   int size = live_set_size();
1925   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1926     resolve_exception_entry(block, r, move_resolver);
1927   }
1928 
1929   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1930   for_each_phi_fun(block, phi,
1931     if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1932   );
1933 
1934   if (move_resolver.has_mappings()) {
1935     // insert moves after first instruction
1936     move_resolver.set_insert_position(block->lir(), 0);
1937     move_resolver.resolve_and_append_moves();
1938   }
1939 }
1940 
1941 
1942 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1943   if (interval_at(reg_num) == NULL) {
1944     // if a phi function is never used, no interval is created -> ignore this
1945     return;
1946   }
1947 
1948   // the computation of to_interval is equal to resolve_collect_mappings,
1949   // but from_interval is more complicated because of phi functions
1950   BlockBegin* to_block = handler->entry_block();
1951   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1952 
1953   if (phi != NULL) {
1954     // phi function of the exception entry block
1955     // no moves are created for this phi function in the LIR_Generator, so the
1956     // interval at the throwing instruction must be searched using the operands
1957     // of the phi function
1958     Value from_value = phi->operand_at(handler->phi_operand());
1959 
1960     // with phi functions it can happen that the same from_value is used in
1961     // multiple mappings, so notify move-resolver that this is allowed
1962     move_resolver.set_multiple_reads_allowed();
1963 
1964     Constant* con = from_value->as_Constant();
1965     if (con != NULL && (!con->is_pinned() || con->operand()->is_constant())) {
1966       // Need a mapping from constant to interval if unpinned (may have no register) or if the operand is a constant (no register).
1967       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1968     } else {
1969       // search split child at the throwing op_id
1970       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1971       move_resolver.add_mapping(from_interval, to_interval);
1972     }
1973   } else {
1974     // no phi function, so use reg_num also for from_interval
1975     // search split child at the throwing op_id
1976     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1977     if (from_interval != to_interval) {
1978       // optimization to reduce number of moves: when to_interval is on stack and
1979       // the stack slot is known to be always correct, then no move is necessary
1980       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1981         move_resolver.add_mapping(from_interval, to_interval);
1982       }
1983     }
1984   }
1985 }
1986 
1987 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1988   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1989 
1990   DEBUG_ONLY(move_resolver.check_empty());
1991   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1992   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1993   assert(handler->entry_code() == NULL, "code already present");
1994 
1995   // visit all registers where the live_in bit is set
1996   BlockBegin* block = handler->entry_block();
1997   int size = live_set_size();
1998   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1999     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
2000   }
2001 
2002   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
2003   for_each_phi_fun(block, phi,
2004     if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
2005   );
2006 
2007   if (move_resolver.has_mappings()) {
2008     LIR_List* entry_code = new LIR_List(compilation());
2009     move_resolver.set_insert_position(entry_code, 0);
2010     move_resolver.resolve_and_append_moves();
2011 
2012     entry_code->jump(handler->entry_block());
2013     handler->set_entry_code(entry_code);
2014   }
2015 }
2016 
2017 
2018 void LinearScan::resolve_exception_handlers() {
2019   MoveResolver move_resolver(this);
2020   LIR_OpVisitState visitor;
2021   int num_blocks = block_count();
2022 
2023   int i;
2024   for (i = 0; i < num_blocks; i++) {
2025     BlockBegin* block = block_at(i);
2026     if (block->is_set(BlockBegin::exception_entry_flag)) {
2027       resolve_exception_entry(block, move_resolver);
2028     }
2029   }
2030 
2031   for (i = 0; i < num_blocks; i++) {
2032     BlockBegin* block = block_at(i);
2033     LIR_List* ops = block->lir();
2034     int num_ops = ops->length();
2035 
2036     // iterate all instructions of the block. skip the first because it is always a label
2037     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2038     for (int j = 1; j < num_ops; j++) {
2039       LIR_Op* op = ops->at(j);
2040       int op_id = op->id();
2041 
2042       if (op_id != -1 && has_info(op_id)) {
2043         // visit operation to collect all operands
2044         visitor.visit(op);
2045         assert(visitor.info_count() > 0, "should not visit otherwise");
2046 
2047         XHandlers* xhandlers = visitor.all_xhandler();
2048         int n = xhandlers->length();
2049         for (int k = 0; k < n; k++) {
2050           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2051         }
2052 
2053 #ifdef ASSERT
2054       } else {
2055         visitor.visit(op);
2056         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2057 #endif
2058       }
2059     }
2060   }
2061 }
2062 
2063 
2064 // ********** Phase 7: assign register numbers back to LIR
2065 // (includes computation of debug information and oop maps)
2066 
2067 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2068   VMReg reg = interval->cached_vm_reg();
2069   if (!reg->is_valid() ) {
2070     reg = vm_reg_for_operand(operand_for_interval(interval));
2071     interval->set_cached_vm_reg(reg);
2072   }
2073   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2074   return reg;
2075 }
2076 
2077 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2078   assert(opr->is_oop(), "currently only implemented for oop operands");
2079   return frame_map()->regname(opr);
2080 }
2081 
2082 
2083 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2084   LIR_Opr opr = interval->cached_opr();
2085   if (opr->is_illegal()) {
2086     opr = calc_operand_for_interval(interval);
2087     interval->set_cached_opr(opr);
2088   }
2089 
2090   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2091   return opr;
2092 }
2093 
2094 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2095   int assigned_reg = interval->assigned_reg();
2096   BasicType type = interval->type();
2097 
2098   if (assigned_reg >= nof_regs) {
2099     // stack slot
2100     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2101     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2102 
2103   } else {
2104     // register
2105     switch (type) {
2106       case T_OBJECT: {
2107         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2108         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2109         return LIR_OprFact::single_cpu_oop(assigned_reg);
2110       }
2111 
2112       case T_ADDRESS: {
2113         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2114         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2115         return LIR_OprFact::single_cpu_address(assigned_reg);
2116       }
2117 
2118       case T_METADATA: {
2119         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2120         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2121         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2122       }
2123 
2124 #ifdef __SOFTFP__
2125       case T_FLOAT:  // fall through
2126 #endif // __SOFTFP__
2127       case T_INT: {
2128         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2129         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2130         return LIR_OprFact::single_cpu(assigned_reg);
2131       }
2132 
2133 #ifdef __SOFTFP__
2134       case T_DOUBLE:  // fall through
2135 #endif // __SOFTFP__
2136       case T_LONG: {
2137         int assigned_regHi = interval->assigned_regHi();
2138         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2139         assert(num_physical_regs(T_LONG) == 1 ||
2140                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2141 
2142         assert(assigned_reg != assigned_regHi, "invalid allocation");
2143         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2144                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2145         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2146         if (requires_adjacent_regs(T_LONG)) {
2147           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2148         }
2149 
2150 #ifdef _LP64
2151         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2152 #else
2153 #if defined(PPC32)
2154         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2155 #else
2156         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2157 #endif // PPC32
2158 #endif // LP64
2159       }
2160 
2161 #ifndef __SOFTFP__
2162       case T_FLOAT: {
2163 #ifdef X86
2164         if (UseSSE >= 1) {
2165           int last_xmm_reg = pd_last_xmm_reg;
2166 #ifdef _LP64
2167           if (UseAVX < 3) {
2168             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2169           }
2170 #endif // LP64
2171           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2172           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2173           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2174         }
2175 #endif // X86
2176 
2177         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2178         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2179         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2180       }
2181 
2182       case T_DOUBLE: {
2183 #ifdef X86
2184         if (UseSSE >= 2) {
2185           int last_xmm_reg = pd_last_xmm_reg;
2186 #ifdef _LP64
2187           if (UseAVX < 3) {
2188             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2189           }
2190 #endif // LP64
2191           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2192           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2193           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2194         }
2195 #endif // X86
2196 
2197 #if defined(ARM32)
2198         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2199         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2200         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2201         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2202 #else
2203         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2204         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2205         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2206 #endif
2207         return result;
2208       }
2209 #endif // __SOFTFP__
2210 
2211       default: {
2212         ShouldNotReachHere();
2213         return LIR_OprFact::illegalOpr;
2214       }
2215     }
2216   }
2217 }
2218 
2219 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2220   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2221   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2222 }
2223 
2224 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2225   assert(opr->is_virtual(), "should not call this otherwise");
2226 
2227   Interval* interval = interval_at(opr->vreg_number());
2228   assert(interval != NULL, "interval must exist");
2229 
2230   if (op_id != -1) {
2231 #ifdef ASSERT
2232     BlockBegin* block = block_of_op_with_id(op_id);
2233     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2234       // check if spill moves could have been appended at the end of this block, but
2235       // before the branch instruction. So the split child information for this branch would
2236       // be incorrect.
2237       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2238       if (branch != NULL) {
2239         if (block->live_out().at(opr->vreg_number())) {
2240           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2241           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2242         }
2243       }
2244     }
2245 #endif
2246 
2247     // operands are not changed when an interval is split during allocation,
2248     // so search the right interval here
2249     interval = split_child_at_op_id(interval, op_id, mode);
2250   }
2251 
2252   LIR_Opr res = operand_for_interval(interval);
2253 
2254 #ifdef X86
2255   // new semantic for is_last_use: not only set on definite end of interval,
2256   // but also before hole
2257   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2258   // last use information is completely correct
2259   // information is only needed for fpu stack allocation
2260   if (res->is_fpu_register()) {
2261     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2262       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2263       res = res->make_last_use();
2264     }
2265   }
2266 #endif
2267 
2268   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2269 
2270   return res;
2271 }
2272 
2273 
2274 #ifdef ASSERT
2275 // some methods used to check correctness of debug information
2276 
2277 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2278   if (values == NULL) {
2279     return;
2280   }
2281 
2282   for (int i = 0; i < values->length(); i++) {
2283     ScopeValue* value = values->at(i);
2284 
2285     if (value->is_location()) {
2286       Location location = ((LocationValue*)value)->location();
2287       assert(location.where() == Location::on_stack, "value is in register");
2288     }
2289   }
2290 }
2291 
2292 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2293   if (values == NULL) {
2294     return;
2295   }
2296 
2297   for (int i = 0; i < values->length(); i++) {
2298     MonitorValue* value = values->at(i);
2299 
2300     if (value->owner()->is_location()) {
2301       Location location = ((LocationValue*)value->owner())->location();
2302       assert(location.where() == Location::on_stack, "owner is in register");
2303     }
2304     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2305   }
2306 }
2307 
2308 void assert_equal(Location l1, Location l2) {
2309   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2310 }
2311 
2312 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2313   if (v1->is_location()) {
2314     assert(v2->is_location(), "");
2315     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2316   } else if (v1->is_constant_int()) {
2317     assert(v2->is_constant_int(), "");
2318     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2319   } else if (v1->is_constant_double()) {
2320     assert(v2->is_constant_double(), "");
2321     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2322   } else if (v1->is_constant_long()) {
2323     assert(v2->is_constant_long(), "");
2324     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2325   } else if (v1->is_constant_oop()) {
2326     assert(v2->is_constant_oop(), "");
2327     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2328   } else {
2329     ShouldNotReachHere();
2330   }
2331 }
2332 
2333 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2334   assert_equal(m1->owner(), m2->owner());
2335   assert_equal(m1->basic_lock(), m2->basic_lock());
2336 }
2337 
2338 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2339   assert(d1->scope() == d2->scope(), "not equal");
2340   assert(d1->bci() == d2->bci(), "not equal");
2341 
2342   if (d1->locals() != NULL) {
2343     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2344     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2345     for (int i = 0; i < d1->locals()->length(); i++) {
2346       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2347     }
2348   } else {
2349     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2350   }
2351 
2352   if (d1->expressions() != NULL) {
2353     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2354     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2355     for (int i = 0; i < d1->expressions()->length(); i++) {
2356       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2357     }
2358   } else {
2359     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2360   }
2361 
2362   if (d1->monitors() != NULL) {
2363     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2364     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2365     for (int i = 0; i < d1->monitors()->length(); i++) {
2366       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2367     }
2368   } else {
2369     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2370   }
2371 
2372   if (d1->caller() != NULL) {
2373     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2374     assert_equal(d1->caller(), d2->caller());
2375   } else {
2376     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2377   }
2378 }
2379 
2380 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2381   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2382     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2383     switch (code) {
2384       case Bytecodes::_ifnull    : // fall through
2385       case Bytecodes::_ifnonnull : // fall through
2386       case Bytecodes::_ifeq      : // fall through
2387       case Bytecodes::_ifne      : // fall through
2388       case Bytecodes::_iflt      : // fall through
2389       case Bytecodes::_ifge      : // fall through
2390       case Bytecodes::_ifgt      : // fall through
2391       case Bytecodes::_ifle      : // fall through
2392       case Bytecodes::_if_icmpeq : // fall through
2393       case Bytecodes::_if_icmpne : // fall through
2394       case Bytecodes::_if_icmplt : // fall through
2395       case Bytecodes::_if_icmpge : // fall through
2396       case Bytecodes::_if_icmpgt : // fall through
2397       case Bytecodes::_if_icmple : // fall through
2398       case Bytecodes::_if_acmpeq : // fall through
2399       case Bytecodes::_if_acmpne :
2400         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2401         break;
2402       default:
2403         break;
2404     }
2405   }
2406 }
2407 
2408 #endif // ASSERT
2409 
2410 
2411 IntervalWalker* LinearScan::init_compute_oop_maps() {
2412   // setup lists of potential oops for walking
2413   Interval* oop_intervals;
2414   Interval* non_oop_intervals;
2415 
2416   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2417 
2418   // intervals that have no oops inside need not to be processed
2419   // to ensure a walking until the last instruction id, add a dummy interval
2420   // with a high operation id
2421   non_oop_intervals = new Interval(any_reg);
2422   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2423 
2424   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2425 }
2426 
2427 
2428 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2429   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2430 
2431   // walk before the current operation -> intervals that start at
2432   // the operation (= output operands of the operation) are not
2433   // included in the oop map
2434   iw->walk_before(op->id());
2435 
2436   int frame_size = frame_map()->framesize();
2437   int arg_count = frame_map()->oop_map_arg_count();
2438   OopMap* map = new OopMap(frame_size, arg_count);
2439 
2440   // Iterate through active intervals
2441   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2442     int assigned_reg = interval->assigned_reg();
2443 
2444     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2445     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2446     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2447 
2448     // Check if this range covers the instruction. Intervals that
2449     // start or end at the current operation are not included in the
2450     // oop map, except in the case of patching moves.  For patching
2451     // moves, any intervals which end at this instruction are included
2452     // in the oop map since we may safepoint while doing the patch
2453     // before we've consumed the inputs.
2454     if (op->is_patching() || op->id() < interval->current_to()) {
2455 
2456       // caller-save registers must not be included into oop-maps at calls
2457       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2458 
2459       VMReg name = vm_reg_for_interval(interval);
2460       set_oop(map, name);
2461 
2462       // Spill optimization: when the stack value is guaranteed to be always correct,
2463       // then it must be added to the oop map even if the interval is currently in a register
2464       if (interval->always_in_memory() &&
2465           op->id() > interval->spill_definition_pos() &&
2466           interval->assigned_reg() != interval->canonical_spill_slot()) {
2467         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2468         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2469         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2470 
2471         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2472       }
2473     }
2474   }
2475 
2476   // add oops from lock stack
2477   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2478   int locks_count = info->stack()->total_locks_size();
2479   for (int i = 0; i < locks_count; i++) {
2480     set_oop(map, frame_map()->monitor_object_regname(i));
2481   }
2482 
2483   return map;
2484 }
2485 
2486 
2487 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2488   assert(visitor.info_count() > 0, "no oop map needed");
2489 
2490   // compute oop_map only for first CodeEmitInfo
2491   // because it is (in most cases) equal for all other infos of the same operation
2492   CodeEmitInfo* first_info = visitor.info_at(0);
2493   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2494 
2495   for (int i = 0; i < visitor.info_count(); i++) {
2496     CodeEmitInfo* info = visitor.info_at(i);
2497     OopMap* oop_map = first_oop_map;
2498 
2499     // compute worst case interpreter size in case of a deoptimization
2500     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2501 
2502     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2503       // this info has a different number of locks then the precomputed oop map
2504       // (possible for lock and unlock instructions) -> compute oop map with
2505       // correct lock information
2506       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2507     }
2508 
2509     if (info->_oop_map == NULL) {
2510       info->_oop_map = oop_map;
2511     } else {
2512       // a CodeEmitInfo can not be shared between different LIR-instructions
2513       // because interval splitting can occur anywhere between two instructions
2514       // and so the oop maps must be different
2515       // -> check if the already set oop_map is exactly the one calculated for this operation
2516       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2517     }
2518   }
2519 }
2520 
2521 
2522 // frequently used constants
2523 // Allocate them with new so they are never destroyed (otherwise, a
2524 // forced exit could destroy these objects while they are still in
2525 // use).
2526 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2527 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2528 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue((jint)0);
2529 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2530 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2531 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2532 
2533 void LinearScan::init_compute_debug_info() {
2534   // cache for frequently used scope values
2535   // (cpu registers and stack slots)
2536   int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2537   _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2538 }
2539 
2540 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2541   Location loc;
2542   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2543     bailout("too large frame");
2544   }
2545   ScopeValue* object_scope_value = new LocationValue(loc);
2546 
2547   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2548     bailout("too large frame");
2549   }
2550   return new MonitorValue(object_scope_value, loc);
2551 }
2552 
2553 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2554   Location loc;
2555   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2556     bailout("too large frame");
2557   }
2558   return new LocationValue(loc);
2559 }
2560 
2561 
2562 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2563   assert(opr->is_constant(), "should not be called otherwise");
2564 
2565   LIR_Const* c = opr->as_constant_ptr();
2566   BasicType t = c->type();
2567   switch (t) {
2568     case T_OBJECT: {
2569       jobject value = c->as_jobject();
2570       if (value == NULL) {
2571         scope_values->append(_oop_null_scope_value);
2572       } else {
2573         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2574       }
2575       return 1;
2576     }
2577 
2578     case T_INT: // fall through
2579     case T_FLOAT: {
2580       int value = c->as_jint_bits();
2581       switch (value) {
2582         case -1: scope_values->append(_int_m1_scope_value); break;
2583         case 0:  scope_values->append(_int_0_scope_value); break;
2584         case 1:  scope_values->append(_int_1_scope_value); break;
2585         case 2:  scope_values->append(_int_2_scope_value); break;
2586         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2587       }
2588       return 1;
2589     }
2590 
2591     case T_LONG: // fall through
2592     case T_DOUBLE: {
2593 #ifdef _LP64
2594       scope_values->append(_int_0_scope_value);
2595       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2596 #else
2597       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2598         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2599         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2600       } else {
2601         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2602         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2603       }
2604 #endif
2605       return 2;
2606     }
2607 
2608     case T_ADDRESS: {
2609 #ifdef _LP64
2610       scope_values->append(new ConstantLongValue(c->as_jint()));
2611 #else
2612       scope_values->append(new ConstantIntValue(c->as_jint()));
2613 #endif
2614       return 1;
2615     }
2616 
2617     default:
2618       ShouldNotReachHere();
2619       return -1;
2620   }
2621 }
2622 
2623 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2624   if (opr->is_single_stack()) {
2625     int stack_idx = opr->single_stack_ix();
2626     bool is_oop = opr->is_oop_register();
2627     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2628 
2629     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2630     if (sv == NULL) {
2631       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2632       sv = location_for_name(stack_idx, loc_type);
2633       _scope_value_cache.at_put(cache_idx, sv);
2634     }
2635 
2636     // check if cached value is correct
2637     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2638 
2639     scope_values->append(sv);
2640     return 1;
2641 
2642   } else if (opr->is_single_cpu()) {
2643     bool is_oop = opr->is_oop_register();
2644     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2645     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2646 
2647     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2648     if (sv == NULL) {
2649       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2650       VMReg rname = frame_map()->regname(opr);
2651       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2652       _scope_value_cache.at_put(cache_idx, sv);
2653     }
2654 
2655     // check if cached value is correct
2656     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2657 
2658     scope_values->append(sv);
2659     return 1;
2660 
2661 #ifdef X86
2662   } else if (opr->is_single_xmm()) {
2663     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2664     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2665 
2666     scope_values->append(sv);
2667     return 1;
2668 #endif
2669 
2670   } else if (opr->is_single_fpu()) {
2671 #ifdef IA32
2672     // the exact location of fpu stack values is only known
2673     // during fpu stack allocation, so the stack allocator object
2674     // must be present
2675     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2676     assert(_fpu_stack_allocator != NULL, "must be present");
2677     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2678 #elif defined(AMD64)
2679     assert(false, "FPU not used on x86-64");
2680 #endif
2681 
2682     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2683     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2684 #ifndef __SOFTFP__
2685 #ifndef VM_LITTLE_ENDIAN
2686     // On S390 a (single precision) float value occupies only the high
2687     // word of the full double register. So when the double register is
2688     // stored to memory (e.g. by the RegisterSaver), then the float value
2689     // is found at offset 0. I.e. the code below is not needed on S390.
2690 #ifndef S390
2691     if (! float_saved_as_double) {
2692       // On big endian system, we may have an issue if float registers use only
2693       // the low half of the (same) double registers.
2694       // Both the float and the double could have the same regnr but would correspond
2695       // to two different addresses once saved.
2696 
2697       // get next safely (no assertion checks)
2698       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2699       if (next->is_reg() &&
2700           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2701         // the back-end does use the same numbering for the double and the float
2702         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2703       }
2704     }
2705 #endif // !S390
2706 #endif
2707 #endif
2708     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2709 
2710     scope_values->append(sv);
2711     return 1;
2712 
2713   } else {
2714     // double-size operands
2715 
2716     ScopeValue* first;
2717     ScopeValue* second;
2718 
2719     if (opr->is_double_stack()) {
2720 #ifdef _LP64
2721       Location loc1;
2722       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2723       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2724         bailout("too large frame");
2725       }
2726 
2727       first =  new LocationValue(loc1);
2728       second = _int_0_scope_value;
2729 #else
2730       Location loc1, loc2;
2731       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2732         bailout("too large frame");
2733       }
2734       first =  new LocationValue(loc1);
2735       second = new LocationValue(loc2);
2736 #endif // _LP64
2737 
2738     } else if (opr->is_double_cpu()) {
2739 #ifdef _LP64
2740       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2741       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2742       second = _int_0_scope_value;
2743 #else
2744       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2745       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2746 
2747       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2748         // lo/hi and swapped relative to first and second, so swap them
2749         VMReg tmp = rname_first;
2750         rname_first = rname_second;
2751         rname_second = tmp;
2752       }
2753 
2754       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2755       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2756 #endif //_LP64
2757 
2758 
2759 #ifdef X86
2760     } else if (opr->is_double_xmm()) {
2761       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2762       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2763 #  ifdef _LP64
2764       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2765       second = _int_0_scope_value;
2766 #  else
2767       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2768       // %%% This is probably a waste but we'll keep things as they were for now
2769       if (true) {
2770         VMReg rname_second = rname_first->next();
2771         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2772       }
2773 #  endif
2774 #endif
2775 
2776     } else if (opr->is_double_fpu()) {
2777       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2778       // the double as float registers in the native ordering. On X86,
2779       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2780       // the low-order word of the double and fpu_regnrLo + 1 is the
2781       // name for the other half.  *first and *second must represent the
2782       // least and most significant words, respectively.
2783 
2784 #ifdef IA32
2785       // the exact location of fpu stack values is only known
2786       // during fpu stack allocation, so the stack allocator object
2787       // must be present
2788       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2789       assert(_fpu_stack_allocator != NULL, "must be present");
2790       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2791 
2792       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2793 #endif
2794 #ifdef AMD64
2795       assert(false, "FPU not used on x86-64");
2796 #endif
2797 #ifdef ARM32
2798       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2799 #endif
2800 #ifdef PPC32
2801       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2802 #endif
2803 
2804 #ifdef VM_LITTLE_ENDIAN
2805       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2806 #else
2807       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2808 #endif
2809 
2810 #ifdef _LP64
2811       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2812       second = _int_0_scope_value;
2813 #else
2814       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2815       // %%% This is probably a waste but we'll keep things as they were for now
2816       if (true) {
2817         VMReg rname_second = rname_first->next();
2818         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2819       }
2820 #endif
2821 
2822     } else {
2823       ShouldNotReachHere();
2824       first = NULL;
2825       second = NULL;
2826     }
2827 
2828     assert(first != NULL && second != NULL, "must be set");
2829     // The convention the interpreter uses is that the second local
2830     // holds the first raw word of the native double representation.
2831     // This is actually reasonable, since locals and stack arrays
2832     // grow downwards in all implementations.
2833     // (If, on some machine, the interpreter's Java locals or stack
2834     // were to grow upwards, the embedded doubles would be word-swapped.)
2835     scope_values->append(second);
2836     scope_values->append(first);
2837     return 2;
2838   }
2839 }
2840 
2841 
2842 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2843   if (value != NULL) {
2844     LIR_Opr opr = value->operand();
2845     Constant* con = value->as_Constant();
2846 
2847     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2848     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2849 
2850     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2851       // Unpinned constants may have a virtual operand for a part of the lifetime
2852       // or may be illegal when it was optimized away,
2853       // so always use a constant operand
2854       opr = LIR_OprFact::value_type(con->type());
2855     }
2856     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2857 
2858     if (opr->is_virtual()) {
2859       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2860 
2861       BlockBegin* block = block_of_op_with_id(op_id);
2862       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2863         // generating debug information for the last instruction of a block.
2864         // if this instruction is a branch, spill moves are inserted before this branch
2865         // and so the wrong operand would be returned (spill moves at block boundaries are not
2866         // considered in the live ranges of intervals)
2867         // Solution: use the first op_id of the branch target block instead.
2868         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2869           if (block->live_out().at(opr->vreg_number())) {
2870             op_id = block->sux_at(0)->first_lir_instruction_id();
2871             mode = LIR_OpVisitState::outputMode;
2872           }
2873         }
2874       }
2875 
2876       // Get current location of operand
2877       // The operand must be live because debug information is considered when building the intervals
2878       // if the interval is not live, color_lir_opr will cause an assertion failure
2879       opr = color_lir_opr(opr, op_id, mode);
2880       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2881 
2882       // Append to ScopeValue array
2883       return append_scope_value_for_operand(opr, scope_values);
2884 
2885     } else {
2886       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2887       assert(opr->is_constant(), "operand must be constant");
2888 
2889       return append_scope_value_for_constant(opr, scope_values);
2890     }
2891   } else {
2892     // append a dummy value because real value not needed
2893     scope_values->append(_illegal_value);
2894     return 1;
2895   }
2896 }
2897 
2898 
2899 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2900   IRScopeDebugInfo* caller_debug_info = NULL;
2901 
2902   ValueStack* caller_state = cur_state->caller_state();
2903   if (caller_state != NULL) {
2904     // process recursively to compute outermost scope first
2905     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2906   }
2907 
2908   // initialize these to null.
2909   // If we don't need deopt info or there are no locals, expressions or monitors,
2910   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2911   GrowableArray<ScopeValue*>*   locals      = NULL;
2912   GrowableArray<ScopeValue*>*   expressions = NULL;
2913   GrowableArray<MonitorValue*>* monitors    = NULL;
2914 
2915   // describe local variable values
2916   int nof_locals = cur_state->locals_size();
2917   if (nof_locals > 0) {
2918     locals = new GrowableArray<ScopeValue*>(nof_locals);
2919 
2920     int pos = 0;
2921     while (pos < nof_locals) {
2922       assert(pos < cur_state->locals_size(), "why not?");
2923 
2924       Value local = cur_state->local_at(pos);
2925       pos += append_scope_value(op_id, local, locals);
2926 
2927       assert(locals->length() == pos, "must match");
2928     }
2929     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2930     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2931   } else if (cur_scope->method()->max_locals() > 0) {
2932     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2933     nof_locals = cur_scope->method()->max_locals();
2934     locals = new GrowableArray<ScopeValue*>(nof_locals);
2935     for(int i = 0; i < nof_locals; i++) {
2936       locals->append(_illegal_value);
2937     }
2938   }
2939 
2940   // describe expression stack
2941   int nof_stack = cur_state->stack_size();
2942   if (nof_stack > 0) {
2943     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2944 
2945     int pos = 0;
2946     while (pos < nof_stack) {
2947       Value expression = cur_state->stack_at_inc(pos);
2948       append_scope_value(op_id, expression, expressions);
2949 
2950       assert(expressions->length() == pos, "must match");
2951     }
2952     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2953   }
2954 
2955   // describe monitors
2956   int nof_locks = cur_state->locks_size();
2957   if (nof_locks > 0) {
2958     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2959     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2960     for (int i = 0; i < nof_locks; i++) {
2961       monitors->append(location_for_monitor_index(lock_offset + i));
2962     }
2963   }
2964 
2965   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2966 }
2967 
2968 
2969 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2970   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2971 
2972   IRScope* innermost_scope = info->scope();
2973   ValueStack* innermost_state = info->stack();
2974 
2975   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2976 
2977   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2978 
2979   if (info->_scope_debug_info == NULL) {
2980     // compute debug information
2981     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2982   } else {
2983     // debug information already set. Check that it is correct from the current point of view
2984     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2985   }
2986 }
2987 
2988 
2989 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2990   LIR_OpVisitState visitor;
2991   int num_inst = instructions->length();
2992   bool has_dead = false;
2993 
2994   for (int j = 0; j < num_inst; j++) {
2995     LIR_Op* op = instructions->at(j);
2996     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2997       has_dead = true;
2998       continue;
2999     }
3000     int op_id = op->id();
3001 
3002     // visit instruction to get list of operands
3003     visitor.visit(op);
3004 
3005     // iterate all modes of the visitor and process all virtual operands
3006     for_each_visitor_mode(mode) {
3007       int n = visitor.opr_count(mode);
3008       for (int k = 0; k < n; k++) {
3009         LIR_Opr opr = visitor.opr_at(mode, k);
3010         if (opr->is_virtual_register()) {
3011           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
3012         }
3013       }
3014     }
3015 
3016     if (visitor.info_count() > 0) {
3017       // exception handling
3018       if (compilation()->has_exception_handlers()) {
3019         XHandlers* xhandlers = visitor.all_xhandler();
3020         int n = xhandlers->length();
3021         for (int k = 0; k < n; k++) {
3022           XHandler* handler = xhandlers->handler_at(k);
3023           if (handler->entry_code() != NULL) {
3024             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3025           }
3026         }
3027       } else {
3028         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3029       }
3030 
3031       // compute oop map
3032       assert(iw != NULL, "needed for compute_oop_map");
3033       compute_oop_map(iw, visitor, op);
3034 
3035       // compute debug information
3036       if (!use_fpu_stack_allocation()) {
3037         // compute debug information if fpu stack allocation is not needed.
3038         // when fpu stack allocation is needed, the debug information can not
3039         // be computed here because the exact location of fpu operands is not known
3040         // -> debug information is created inside the fpu stack allocator
3041         int n = visitor.info_count();
3042         for (int k = 0; k < n; k++) {
3043           compute_debug_info(visitor.info_at(k), op_id);
3044         }
3045       }
3046     }
3047 
3048 #ifdef ASSERT
3049     // make sure we haven't made the op invalid.
3050     op->verify();
3051 #endif
3052 
3053     // remove useless moves
3054     if (op->code() == lir_move) {
3055       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3056       LIR_Op1* move = (LIR_Op1*)op;
3057       LIR_Opr src = move->in_opr();
3058       LIR_Opr dst = move->result_opr();
3059       if (dst == src ||
3060           (!dst->is_pointer() && !src->is_pointer() &&
3061            src->is_same_register(dst))) {
3062         instructions->at_put(j, NULL);
3063         has_dead = true;
3064       }
3065     }
3066   }
3067 
3068   if (has_dead) {
3069     // iterate all instructions of the block and remove all null-values.
3070     int insert_point = 0;
3071     for (int j = 0; j < num_inst; j++) {
3072       LIR_Op* op = instructions->at(j);
3073       if (op != NULL) {
3074         if (insert_point != j) {
3075           instructions->at_put(insert_point, op);
3076         }
3077         insert_point++;
3078       }
3079     }
3080     instructions->trunc_to(insert_point);
3081   }
3082 }
3083 
3084 void LinearScan::assign_reg_num() {
3085   TIME_LINEAR_SCAN(timer_assign_reg_num);
3086 
3087   init_compute_debug_info();
3088   IntervalWalker* iw = init_compute_oop_maps();
3089 
3090   int num_blocks = block_count();
3091   for (int i = 0; i < num_blocks; i++) {
3092     BlockBegin* block = block_at(i);
3093     assign_reg_num(block->lir()->instructions_list(), iw);
3094   }
3095 }
3096 
3097 
3098 void LinearScan::do_linear_scan() {
3099   NOT_PRODUCT(_total_timer.begin_method());
3100 
3101   number_instructions();
3102 
3103   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3104 
3105   compute_local_live_sets();
3106   compute_global_live_sets();
3107   CHECK_BAILOUT();
3108 
3109   build_intervals();
3110   CHECK_BAILOUT();
3111   sort_intervals_before_allocation();
3112 
3113   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3114   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3115 
3116   allocate_registers();
3117   CHECK_BAILOUT();
3118 
3119   resolve_data_flow();
3120   if (compilation()->has_exception_handlers()) {
3121     resolve_exception_handlers();
3122   }
3123   // fill in number of spill slots into frame_map
3124   propagate_spill_slots();
3125   CHECK_BAILOUT();
3126 
3127   NOT_PRODUCT(print_intervals("After Register Allocation"));
3128   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3129 
3130   sort_intervals_after_allocation();
3131 
3132   DEBUG_ONLY(verify());
3133 
3134   eliminate_spill_moves();
3135   assign_reg_num();
3136   CHECK_BAILOUT();
3137 
3138   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3139   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3140 
3141   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3142 
3143     if (use_fpu_stack_allocation()) {
3144       allocate_fpu_stack(); // Only has effect on Intel
3145       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3146     }
3147   }
3148 
3149   { TIME_LINEAR_SCAN(timer_optimize_lir);
3150 
3151     EdgeMoveOptimizer::optimize(ir()->code());
3152     ControlFlowOptimizer::optimize(ir()->code());
3153     // check that cfg is still correct after optimizations
3154     ir()->verify();
3155   }
3156 
3157   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3158   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3159   NOT_PRODUCT(_total_timer.end_method(this));
3160 }
3161 
3162 
3163 // ********** Printing functions
3164 
3165 #ifndef PRODUCT
3166 
3167 void LinearScan::print_timers(double total) {
3168   _total_timer.print(total);
3169 }
3170 
3171 void LinearScan::print_statistics() {
3172   _stat_before_alloc.print("before allocation");
3173   _stat_after_asign.print("after assignment of register");
3174   _stat_final.print("after optimization");
3175 }
3176 
3177 void LinearScan::print_bitmap(BitMap& b) {
3178   for (unsigned int i = 0; i < b.size(); i++) {
3179     if (b.at(i)) tty->print("%d ", i);
3180   }
3181   tty->cr();
3182 }
3183 
3184 void LinearScan::print_intervals(const char* label) {
3185   if (TraceLinearScanLevel >= 1) {
3186     int i;
3187     tty->cr();
3188     tty->print_cr("%s", label);
3189 
3190     for (i = 0; i < interval_count(); i++) {
3191       Interval* interval = interval_at(i);
3192       if (interval != NULL) {
3193         interval->print();
3194       }
3195     }
3196 
3197     tty->cr();
3198     tty->print_cr("--- Basic Blocks ---");
3199     for (i = 0; i < block_count(); i++) {
3200       BlockBegin* block = block_at(i);
3201       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3202     }
3203     tty->cr();
3204     tty->cr();
3205   }
3206 
3207   if (PrintCFGToFile) {
3208     CFGPrinter::print_intervals(&_intervals, label);
3209   }
3210 }
3211 
3212 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3213   if (TraceLinearScanLevel >= level) {
3214     tty->cr();
3215     tty->print_cr("%s", label);
3216     print_LIR(ir()->linear_scan_order());
3217     tty->cr();
3218   }
3219 
3220   if (level == 1 && PrintCFGToFile) {
3221     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3222   }
3223 }
3224 
3225 void LinearScan::print_reg_num(outputStream* out, int reg_num) {
3226   if (reg_num == -1) {
3227     out->print("[ANY]");
3228     return;
3229   } else if (reg_num >= LIR_OprDesc::vreg_base) {
3230     out->print("[VREG %d]", reg_num);
3231     return;
3232   }
3233 
3234   LIR_Opr opr = get_operand(reg_num);
3235   assert(opr->is_valid(), "unknown register");
3236   opr->print(out);
3237 }
3238 
3239 LIR_Opr LinearScan::get_operand(int reg_num) {
3240   LIR_Opr opr = LIR_OprFact::illegal();
3241 
3242 #ifdef X86
3243   int last_xmm_reg = pd_last_xmm_reg;
3244 #ifdef _LP64
3245   if (UseAVX < 3) {
3246     last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
3247   }
3248 #endif
3249 #endif
3250   if (reg_num >= pd_first_cpu_reg && reg_num <= pd_last_cpu_reg) {
3251     opr = LIR_OprFact::single_cpu(reg_num);
3252   } else if (reg_num >= pd_first_fpu_reg && reg_num <= pd_last_fpu_reg) {
3253     opr = LIR_OprFact::single_fpu(reg_num - pd_first_fpu_reg);
3254 #ifdef X86
3255   } else if (reg_num >= pd_first_xmm_reg && reg_num <= last_xmm_reg) {
3256     opr = LIR_OprFact::single_xmm(reg_num - pd_first_xmm_reg);
3257 #endif
3258   } else {
3259     // reg_num == -1 or a virtual register, return the illegal operand
3260   }
3261   return opr;
3262 }
3263 
3264 Interval* LinearScan::find_interval_at(int reg_num) const {
3265   if (reg_num < 0 || reg_num >= _intervals.length()) {
3266     return NULL;
3267   }
3268   return interval_at(reg_num);
3269 }
3270 
3271 #endif // PRODUCT
3272 
3273 
3274 // ********** verification functions for allocation
3275 // (check that all intervals have a correct register and that no registers are overwritten)
3276 #ifdef ASSERT
3277 
3278 void LinearScan::verify() {
3279   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3280   verify_intervals();
3281 
3282   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3283   verify_no_oops_in_fixed_intervals();
3284 
3285   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3286   verify_constants();
3287 
3288   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3289   verify_registers();
3290 
3291   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3292 }
3293 
3294 void LinearScan::verify_intervals() {
3295   int len = interval_count();
3296   bool has_error = false;
3297 
3298   for (int i = 0; i < len; i++) {
3299     Interval* i1 = interval_at(i);
3300     if (i1 == NULL) continue;
3301 
3302     i1->check_split_children();
3303 
3304     if (i1->reg_num() != i) {
3305       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3306       has_error = true;
3307     }
3308 
3309     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3310       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3311       has_error = true;
3312     }
3313 
3314     if (i1->assigned_reg() == any_reg) {
3315       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3316       has_error = true;
3317     }
3318 
3319     if (i1->assigned_reg() == i1->assigned_regHi()) {
3320       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3321       has_error = true;
3322     }
3323 
3324     if (!is_processed_reg_num(i1->assigned_reg())) {
3325       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3326       has_error = true;
3327     }
3328 
3329     // special intervals that are created in MoveResolver
3330     // -> ignore them because the range information has no meaning there
3331     if (i1->from() == 1 && i1->to() == 2) continue;
3332 
3333     if (i1->first() == Range::end()) {
3334       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3335       has_error = true;
3336     }
3337 
3338     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3339       if (r->from() >= r->to()) {
3340         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3341         has_error = true;
3342       }
3343     }
3344 
3345     for (int j = i + 1; j < len; j++) {
3346       Interval* i2 = interval_at(j);
3347       if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3348 
3349       int r1 = i1->assigned_reg();
3350       int r1Hi = i1->assigned_regHi();
3351       int r2 = i2->assigned_reg();
3352       int r2Hi = i2->assigned_regHi();
3353       if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3354         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3355         i1->print(); tty->cr();
3356         i2->print(); tty->cr();
3357         has_error = true;
3358       }
3359     }
3360   }
3361 
3362   assert(has_error == false, "register allocation invalid");
3363 }
3364 
3365 
3366 void LinearScan::verify_no_oops_in_fixed_intervals() {
3367   Interval* fixed_intervals;
3368   Interval* other_intervals;
3369   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3370 
3371   // to ensure a walking until the last instruction id, add a dummy interval
3372   // with a high operation id
3373   other_intervals = new Interval(any_reg);
3374   other_intervals->add_range(max_jint - 2, max_jint - 1);
3375   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3376 
3377   LIR_OpVisitState visitor;
3378   for (int i = 0; i < block_count(); i++) {
3379     BlockBegin* block = block_at(i);
3380 
3381     LIR_OpList* instructions = block->lir()->instructions_list();
3382 
3383     for (int j = 0; j < instructions->length(); j++) {
3384       LIR_Op* op = instructions->at(j);
3385       int op_id = op->id();
3386 
3387       visitor.visit(op);
3388 
3389       if (visitor.info_count() > 0) {
3390         iw->walk_before(op->id());
3391         bool check_live = true;
3392         if (op->code() == lir_move) {
3393           LIR_Op1* move = (LIR_Op1*)op;
3394           check_live = (move->patch_code() == lir_patch_none);
3395         }
3396         LIR_OpBranch* branch = op->as_OpBranch();
3397         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3398           // Don't bother checking the stub in this case since the
3399           // exception stub will never return to normal control flow.
3400           check_live = false;
3401         }
3402 
3403         // Make sure none of the fixed registers is live across an
3404         // oopmap since we can't handle that correctly.
3405         if (check_live) {
3406           for (Interval* interval = iw->active_first(fixedKind);
3407                interval != Interval::end();
3408                interval = interval->next()) {
3409             if (interval->current_to() > op->id() + 1) {
3410               // This interval is live out of this op so make sure
3411               // that this interval represents some value that's
3412               // referenced by this op either as an input or output.
3413               bool ok = false;
3414               for_each_visitor_mode(mode) {
3415                 int n = visitor.opr_count(mode);
3416                 for (int k = 0; k < n; k++) {
3417                   LIR_Opr opr = visitor.opr_at(mode, k);
3418                   if (opr->is_fixed_cpu()) {
3419                     if (interval_at(reg_num(opr)) == interval) {
3420                       ok = true;
3421                       break;
3422                     }
3423                     int hi = reg_numHi(opr);
3424                     if (hi != -1 && interval_at(hi) == interval) {
3425                       ok = true;
3426                       break;
3427                     }
3428                   }
3429                 }
3430               }
3431               assert(ok, "fixed intervals should never be live across an oopmap point");
3432             }
3433           }
3434         }
3435       }
3436 
3437       // oop-maps at calls do not contain registers, so check is not needed
3438       if (!visitor.has_call()) {
3439 
3440         for_each_visitor_mode(mode) {
3441           int n = visitor.opr_count(mode);
3442           for (int k = 0; k < n; k++) {
3443             LIR_Opr opr = visitor.opr_at(mode, k);
3444 
3445             if (opr->is_fixed_cpu() && opr->is_oop()) {
3446               // operand is a non-virtual cpu register and contains an oop
3447               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3448 
3449               Interval* interval = interval_at(reg_num(opr));
3450               assert(interval != NULL, "no interval");
3451 
3452               if (mode == LIR_OpVisitState::inputMode) {
3453                 if (interval->to() >= op_id + 1) {
3454                   assert(interval->to() < op_id + 2 ||
3455                          interval->has_hole_between(op_id, op_id + 2),
3456                          "oop input operand live after instruction");
3457                 }
3458               } else if (mode == LIR_OpVisitState::outputMode) {
3459                 if (interval->from() <= op_id - 1) {
3460                   assert(interval->has_hole_between(op_id - 1, op_id),
3461                          "oop input operand live after instruction");
3462                 }
3463               }
3464             }
3465           }
3466         }
3467       }
3468     }
3469   }
3470 }
3471 
3472 
3473 void LinearScan::verify_constants() {
3474   int num_regs = num_virtual_regs();
3475   int size = live_set_size();
3476   int num_blocks = block_count();
3477 
3478   for (int i = 0; i < num_blocks; i++) {
3479     BlockBegin* block = block_at(i);
3480     ResourceBitMap live_at_edge = block->live_in();
3481 
3482     // visit all registers where the live_at_edge bit is set
3483     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3484       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3485 
3486       Value value = gen()->instruction_for_vreg(r);
3487 
3488       assert(value != NULL, "all intervals live across block boundaries must have Value");
3489       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3490       assert(value->operand()->vreg_number() == r, "register number must match");
3491       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3492     }
3493   }
3494 }
3495 
3496 
3497 class RegisterVerifier: public StackObj {
3498  private:
3499   LinearScan*   _allocator;
3500   BlockList     _work_list;      // all blocks that must be processed
3501   IntervalsList _saved_states;   // saved information of previous check
3502 
3503   // simplified access to methods of LinearScan
3504   Compilation*  compilation() const              { return _allocator->compilation(); }
3505   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3506   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3507 
3508   // currently, only registers are processed
3509   int           state_size()                     { return LinearScan::nof_regs; }
3510 
3511   // accessors
3512   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3513   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3514   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3515 
3516   // helper functions
3517   IntervalList* copy(IntervalList* input_state);
3518   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3519   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3520 
3521   void process_block(BlockBegin* block);
3522   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3523   void process_successor(BlockBegin* block, IntervalList* input_state);
3524   void process_operations(LIR_List* ops, IntervalList* input_state);
3525 
3526  public:
3527   RegisterVerifier(LinearScan* allocator)
3528     : _allocator(allocator)
3529     , _work_list(16)
3530     , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3531   { }
3532 
3533   void verify(BlockBegin* start);
3534 };
3535 
3536 
3537 // entry function from LinearScan that starts the verification
3538 void LinearScan::verify_registers() {
3539   RegisterVerifier verifier(this);
3540   verifier.verify(block_at(0));
3541 }
3542 
3543 
3544 void RegisterVerifier::verify(BlockBegin* start) {
3545   // setup input registers (method arguments) for first block
3546   int input_state_len = state_size();
3547   IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3548   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3549   for (int n = 0; n < args->length(); n++) {
3550     LIR_Opr opr = args->at(n);
3551     if (opr->is_register()) {
3552       Interval* interval = interval_at(reg_num(opr));
3553 
3554       if (interval->assigned_reg() < state_size()) {
3555         input_state->at_put(interval->assigned_reg(), interval);
3556       }
3557       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3558         input_state->at_put(interval->assigned_regHi(), interval);
3559       }
3560     }
3561   }
3562 
3563   set_state_for_block(start, input_state);
3564   add_to_work_list(start);
3565 
3566   // main loop for verification
3567   do {
3568     BlockBegin* block = _work_list.at(0);
3569     _work_list.remove_at(0);
3570 
3571     process_block(block);
3572   } while (!_work_list.is_empty());
3573 }
3574 
3575 void RegisterVerifier::process_block(BlockBegin* block) {
3576   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3577 
3578   // must copy state because it is modified
3579   IntervalList* input_state = copy(state_for_block(block));
3580 
3581   if (TraceLinearScanLevel >= 4) {
3582     tty->print_cr("Input-State of intervals:");
3583     tty->print("    ");
3584     for (int i = 0; i < state_size(); i++) {
3585       if (input_state->at(i) != NULL) {
3586         tty->print(" %4d", input_state->at(i)->reg_num());
3587       } else {
3588         tty->print("   __");
3589       }
3590     }
3591     tty->cr();
3592     tty->cr();
3593   }
3594 
3595   // process all operations of the block
3596   process_operations(block->lir(), input_state);
3597 
3598   // iterate all successors
3599   for (int i = 0; i < block->number_of_sux(); i++) {
3600     process_successor(block->sux_at(i), input_state);
3601   }
3602 }
3603 
3604 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3605   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3606 
3607   // must copy state because it is modified
3608   input_state = copy(input_state);
3609 
3610   if (xhandler->entry_code() != NULL) {
3611     process_operations(xhandler->entry_code(), input_state);
3612   }
3613   process_successor(xhandler->entry_block(), input_state);
3614 }
3615 
3616 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3617   IntervalList* saved_state = state_for_block(block);
3618 
3619   if (saved_state != NULL) {
3620     // this block was already processed before.
3621     // check if new input_state is consistent with saved_state
3622 
3623     bool saved_state_correct = true;
3624     for (int i = 0; i < state_size(); i++) {
3625       if (input_state->at(i) != saved_state->at(i)) {
3626         // current input_state and previous saved_state assume a different
3627         // interval in this register -> assume that this register is invalid
3628         if (saved_state->at(i) != NULL) {
3629           // invalidate old calculation only if it assumed that
3630           // register was valid. when the register was already invalid,
3631           // then the old calculation was correct.
3632           saved_state_correct = false;
3633           saved_state->at_put(i, NULL);
3634 
3635           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3636         }
3637       }
3638     }
3639 
3640     if (saved_state_correct) {
3641       // already processed block with correct input_state
3642       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3643     } else {
3644       // must re-visit this block
3645       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3646       add_to_work_list(block);
3647     }
3648 
3649   } else {
3650     // block was not processed before, so set initial input_state
3651     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3652 
3653     set_state_for_block(block, copy(input_state));
3654     add_to_work_list(block);
3655   }
3656 }
3657 
3658 
3659 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3660   IntervalList* copy_state = new IntervalList(input_state->length());
3661   copy_state->appendAll(input_state);
3662   return copy_state;
3663 }
3664 
3665 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3666   if (reg != LinearScan::any_reg && reg < state_size()) {
3667     if (interval != NULL) {
3668       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3669     } else if (input_state->at(reg) != NULL) {
3670       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3671     }
3672 
3673     input_state->at_put(reg, interval);
3674   }
3675 }
3676 
3677 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3678   if (reg != LinearScan::any_reg && reg < state_size()) {
3679     if (input_state->at(reg) != interval) {
3680       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3681       return true;
3682     }
3683   }
3684   return false;
3685 }
3686 
3687 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3688   // visit all instructions of the block
3689   LIR_OpVisitState visitor;
3690   bool has_error = false;
3691 
3692   for (int i = 0; i < ops->length(); i++) {
3693     LIR_Op* op = ops->at(i);
3694     visitor.visit(op);
3695 
3696     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3697 
3698     // check if input operands are correct
3699     int j;
3700     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3701     for (j = 0; j < n; j++) {
3702       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3703       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3704         Interval* interval = interval_at(reg_num(opr));
3705         if (op->id() != -1) {
3706           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3707         }
3708 
3709         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3710         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3711 
3712         // When an operand is marked with is_last_use, then the fpu stack allocator
3713         // removes the register from the fpu stack -> the register contains no value
3714         if (opr->is_last_use()) {
3715           state_put(input_state, interval->assigned_reg(),   NULL);
3716           state_put(input_state, interval->assigned_regHi(), NULL);
3717         }
3718       }
3719     }
3720 
3721     // invalidate all caller save registers at calls
3722     if (visitor.has_call()) {
3723       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3724         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3725       }
3726       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3727         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3728       }
3729 
3730 #ifdef X86
3731       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3732       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3733         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3734       }
3735 #endif
3736     }
3737 
3738     // process xhandler before output and temp operands
3739     XHandlers* xhandlers = visitor.all_xhandler();
3740     n = xhandlers->length();
3741     for (int k = 0; k < n; k++) {
3742       process_xhandler(xhandlers->handler_at(k), input_state);
3743     }
3744 
3745     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3746     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3747     for (j = 0; j < n; j++) {
3748       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3749       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3750         Interval* interval = interval_at(reg_num(opr));
3751         if (op->id() != -1) {
3752           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3753         }
3754 
3755         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3756         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3757       }
3758     }
3759 
3760     // set output operands
3761     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3762     for (j = 0; j < n; j++) {
3763       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3764       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3765         Interval* interval = interval_at(reg_num(opr));
3766         if (op->id() != -1) {
3767           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3768         }
3769 
3770         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3771         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3772       }
3773     }
3774   }
3775   assert(has_error == false, "Error in register allocation");
3776 }
3777 
3778 #endif // ASSERT
3779 
3780 
3781 
3782 // **** Implementation of MoveResolver ******************************
3783 
3784 MoveResolver::MoveResolver(LinearScan* allocator) :
3785   _allocator(allocator),
3786   _insert_list(NULL),
3787   _insert_idx(-1),
3788   _insertion_buffer(),
3789   _mapping_from(8),
3790   _mapping_from_opr(8),
3791   _mapping_to(8),
3792   _multiple_reads_allowed(false)
3793 {
3794   for (int i = 0; i < LinearScan::nof_regs; i++) {
3795     _register_blocked[i] = 0;
3796   }
3797   DEBUG_ONLY(check_empty());
3798 }
3799 
3800 
3801 #ifdef ASSERT
3802 
3803 void MoveResolver::check_empty() {
3804   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3805   for (int i = 0; i < LinearScan::nof_regs; i++) {
3806     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3807   }
3808   assert(_multiple_reads_allowed == false, "must have default value");
3809 }
3810 
3811 void MoveResolver::verify_before_resolve() {
3812   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3813   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3814   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3815 
3816   int i, j;
3817   if (!_multiple_reads_allowed) {
3818     for (i = 0; i < _mapping_from.length(); i++) {
3819       for (j = i + 1; j < _mapping_from.length(); j++) {
3820         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3821       }
3822     }
3823   }
3824 
3825   for (i = 0; i < _mapping_to.length(); i++) {
3826     for (j = i + 1; j < _mapping_to.length(); j++) {
3827       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3828     }
3829   }
3830 
3831 
3832   ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3833   if (!_multiple_reads_allowed) {
3834     for (i = 0; i < _mapping_from.length(); i++) {
3835       Interval* it = _mapping_from.at(i);
3836       if (it != NULL) {
3837         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3838         used_regs.set_bit(it->assigned_reg());
3839 
3840         if (it->assigned_regHi() != LinearScan::any_reg) {
3841           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3842           used_regs.set_bit(it->assigned_regHi());
3843         }
3844       }
3845     }
3846   }
3847 
3848   used_regs.clear();
3849   for (i = 0; i < _mapping_to.length(); i++) {
3850     Interval* it = _mapping_to.at(i);
3851     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3852     used_regs.set_bit(it->assigned_reg());
3853 
3854     if (it->assigned_regHi() != LinearScan::any_reg) {
3855       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3856       used_regs.set_bit(it->assigned_regHi());
3857     }
3858   }
3859 
3860   used_regs.clear();
3861   for (i = 0; i < _mapping_from.length(); i++) {
3862     Interval* it = _mapping_from.at(i);
3863     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3864       used_regs.set_bit(it->assigned_reg());
3865     }
3866   }
3867   for (i = 0; i < _mapping_to.length(); i++) {
3868     Interval* it = _mapping_to.at(i);
3869     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3870   }
3871 }
3872 
3873 #endif // ASSERT
3874 
3875 
3876 // mark assigned_reg and assigned_regHi of the interval as blocked
3877 void MoveResolver::block_registers(Interval* it) {
3878   int reg = it->assigned_reg();
3879   if (reg < LinearScan::nof_regs) {
3880     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3881     set_register_blocked(reg, 1);
3882   }
3883   reg = it->assigned_regHi();
3884   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3885     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3886     set_register_blocked(reg, 1);
3887   }
3888 }
3889 
3890 // mark assigned_reg and assigned_regHi of the interval as unblocked
3891 void MoveResolver::unblock_registers(Interval* it) {
3892   int reg = it->assigned_reg();
3893   if (reg < LinearScan::nof_regs) {
3894     assert(register_blocked(reg) > 0, "register already marked as unused");
3895     set_register_blocked(reg, -1);
3896   }
3897   reg = it->assigned_regHi();
3898   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3899     assert(register_blocked(reg) > 0, "register already marked as unused");
3900     set_register_blocked(reg, -1);
3901   }
3902 }
3903 
3904 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3905 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3906   int from_reg = -1;
3907   int from_regHi = -1;
3908   if (from != NULL) {
3909     from_reg = from->assigned_reg();
3910     from_regHi = from->assigned_regHi();
3911   }
3912 
3913   int reg = to->assigned_reg();
3914   if (reg < LinearScan::nof_regs) {
3915     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3916       return false;
3917     }
3918   }
3919   reg = to->assigned_regHi();
3920   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3921     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3922       return false;
3923     }
3924   }
3925 
3926   return true;
3927 }
3928 
3929 
3930 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3931   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3932   _insertion_buffer.init(list);
3933 }
3934 
3935 void MoveResolver::append_insertion_buffer() {
3936   if (_insertion_buffer.initialized()) {
3937     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3938   }
3939   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3940 
3941   _insert_list = NULL;
3942   _insert_idx = -1;
3943 }
3944 
3945 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3946   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3947   assert(from_interval->type() == to_interval->type(), "move between different types");
3948   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3949   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3950 
3951   LIR_Opr from_opr = get_virtual_register(from_interval);
3952   LIR_Opr to_opr = get_virtual_register(to_interval);
3953 
3954   if (!_multiple_reads_allowed) {
3955     // the last_use flag is an optimization for FPU stack allocation. When the same
3956     // input interval is used in more than one move, then it is too difficult to determine
3957     // if this move is really the last use.
3958     from_opr = from_opr->make_last_use();
3959   }
3960   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3961 
3962   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3963 }
3964 
3965 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3966   assert(from_opr->type() == to_interval->type(), "move between different types");
3967   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3968   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3969 
3970   LIR_Opr to_opr = get_virtual_register(to_interval);
3971   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3972 
3973   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3974 }
3975 
3976 LIR_Opr MoveResolver::get_virtual_register(Interval* interval) {
3977   // Add a little fudge factor for the bailout since the bailout is only checked periodically. This allows us to hand out
3978   // a few extra registers before we really run out which helps to avoid to trip over assertions.
3979   int reg_num = interval->reg_num();
3980   if (reg_num + 20 >= LIR_OprDesc::vreg_max) {
3981     _allocator->bailout("out of virtual registers in linear scan");
3982     if (reg_num + 2 >= LIR_OprDesc::vreg_max) {
3983       // Wrap it around and continue until bailout really happens to avoid hitting assertions.
3984       reg_num = LIR_OprDesc::vreg_base;
3985     }
3986   }
3987   LIR_Opr vreg = LIR_OprFact::virtual_register(reg_num, interval->type());
3988   assert(vreg != LIR_OprFact::illegal(), "ran out of virtual registers");
3989   return vreg;
3990 }
3991 
3992 void MoveResolver::resolve_mappings() {
3993   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3994   DEBUG_ONLY(verify_before_resolve());
3995 
3996   // Block all registers that are used as input operands of a move.
3997   // When a register is blocked, no move to this register is emitted.
3998   // This is necessary for detecting cycles in moves.
3999   int i;
4000   for (i = _mapping_from.length() - 1; i >= 0; i--) {
4001     Interval* from_interval = _mapping_from.at(i);
4002     if (from_interval != NULL) {
4003       block_registers(from_interval);
4004     }
4005   }
4006 
4007   int spill_candidate = -1;
4008   while (_mapping_from.length() > 0) {
4009     bool processed_interval = false;
4010 
4011     for (i = _mapping_from.length() - 1; i >= 0; i--) {
4012       Interval* from_interval = _mapping_from.at(i);
4013       Interval* to_interval = _mapping_to.at(i);
4014 
4015       if (save_to_process_move(from_interval, to_interval)) {
4016         // this inverval can be processed because target is free
4017         if (from_interval != NULL) {
4018           insert_move(from_interval, to_interval);
4019           unblock_registers(from_interval);
4020         } else {
4021           insert_move(_mapping_from_opr.at(i), to_interval);
4022         }
4023         _mapping_from.remove_at(i);
4024         _mapping_from_opr.remove_at(i);
4025         _mapping_to.remove_at(i);
4026 
4027         processed_interval = true;
4028       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
4029         // this interval cannot be processed now because target is not free
4030         // it starts in a register, so it is a possible candidate for spilling
4031         spill_candidate = i;
4032       }
4033     }
4034 
4035     if (!processed_interval) {
4036       // no move could be processed because there is a cycle in the move list
4037       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
4038       guarantee(spill_candidate != -1, "no interval in register for spilling found");
4039 
4040       // create a new spill interval and assign a stack slot to it
4041       Interval* from_interval = _mapping_from.at(spill_candidate);
4042       Interval* spill_interval = new Interval(-1);
4043       spill_interval->set_type(from_interval->type());
4044 
4045       // add a dummy range because real position is difficult to calculate
4046       // Note: this range is a special case when the integrity of the allocation is checked
4047       spill_interval->add_range(1, 2);
4048 
4049       //       do not allocate a new spill slot for temporary interval, but
4050       //       use spill slot assigned to from_interval. Otherwise moves from
4051       //       one stack slot to another can happen (not allowed by LIR_Assembler
4052       int spill_slot = from_interval->canonical_spill_slot();
4053       if (spill_slot < 0) {
4054         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
4055         from_interval->set_canonical_spill_slot(spill_slot);
4056       }
4057       spill_interval->assign_reg(spill_slot);
4058       allocator()->append_interval(spill_interval);
4059 
4060       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
4061 
4062       // insert a move from register to stack and update the mapping
4063       insert_move(from_interval, spill_interval);
4064       _mapping_from.at_put(spill_candidate, spill_interval);
4065       unblock_registers(from_interval);
4066     }
4067   }
4068 
4069   // reset to default value
4070   _multiple_reads_allowed = false;
4071 
4072   // check that all intervals have been processed
4073   DEBUG_ONLY(check_empty());
4074 }
4075 
4076 
4077 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4078   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4079   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4080 
4081   create_insertion_buffer(insert_list);
4082   _insert_list = insert_list;
4083   _insert_idx = insert_idx;
4084 }
4085 
4086 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4087   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4088 
4089   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4090     // insert position changed -> resolve current mappings
4091     resolve_mappings();
4092   }
4093 
4094   if (insert_list != _insert_list) {
4095     // block changed -> append insertion_buffer because it is
4096     // bound to a specific block and create a new insertion_buffer
4097     append_insertion_buffer();
4098     create_insertion_buffer(insert_list);
4099   }
4100 
4101   _insert_list = insert_list;
4102   _insert_idx = insert_idx;
4103 }
4104 
4105 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4106   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4107 
4108   _mapping_from.append(from_interval);
4109   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4110   _mapping_to.append(to_interval);
4111 }
4112 
4113 
4114 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4115   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4116   assert(from_opr->is_constant(), "only for constants");
4117 
4118   _mapping_from.append(NULL);
4119   _mapping_from_opr.append(from_opr);
4120   _mapping_to.append(to_interval);
4121 }
4122 
4123 void MoveResolver::resolve_and_append_moves() {
4124   if (has_mappings()) {
4125     resolve_mappings();
4126   }
4127   append_insertion_buffer();
4128 }
4129 
4130 
4131 
4132 // **** Implementation of Range *************************************
4133 
4134 Range::Range(int from, int to, Range* next) :
4135   _from(from),
4136   _to(to),
4137   _next(next)
4138 {
4139 }
4140 
4141 // initialize sentinel
4142 Range* Range::_end = NULL;
4143 void Range::initialize(Arena* arena) {
4144   _end = new (arena) Range(max_jint, max_jint, NULL);
4145 }
4146 
4147 int Range::intersects_at(Range* r2) const {
4148   const Range* r1 = this;
4149 
4150   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4151   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4152 
4153   do {
4154     if (r1->from() < r2->from()) {
4155       if (r1->to() <= r2->from()) {
4156         r1 = r1->next(); if (r1 == _end) return -1;
4157       } else {
4158         return r2->from();
4159       }
4160     } else if (r2->from() < r1->from()) {
4161       if (r2->to() <= r1->from()) {
4162         r2 = r2->next(); if (r2 == _end) return -1;
4163       } else {
4164         return r1->from();
4165       }
4166     } else { // r1->from() == r2->from()
4167       if (r1->from() == r1->to()) {
4168         r1 = r1->next(); if (r1 == _end) return -1;
4169       } else if (r2->from() == r2->to()) {
4170         r2 = r2->next(); if (r2 == _end) return -1;
4171       } else {
4172         return r1->from();
4173       }
4174     }
4175   } while (true);
4176 }
4177 
4178 #ifndef PRODUCT
4179 void Range::print(outputStream* out) const {
4180   out->print("[%d, %d[ ", _from, _to);
4181 }
4182 #endif
4183 
4184 
4185 
4186 // **** Implementation of Interval **********************************
4187 
4188 // initialize sentinel
4189 Interval* Interval::_end = NULL;
4190 void Interval::initialize(Arena* arena) {
4191   Range::initialize(arena);
4192   _end = new (arena) Interval(-1);
4193 }
4194 
4195 Interval::Interval(int reg_num) :
4196   _reg_num(reg_num),
4197   _type(T_ILLEGAL),
4198   _first(Range::end()),
4199   _use_pos_and_kinds(12),
4200   _current(Range::end()),
4201   _next(_end),
4202   _state(invalidState),
4203   _assigned_reg(LinearScan::any_reg),
4204   _assigned_regHi(LinearScan::any_reg),
4205   _cached_to(-1),
4206   _cached_opr(LIR_OprFact::illegalOpr),
4207   _cached_vm_reg(VMRegImpl::Bad()),
4208   _split_children(NULL),
4209   _canonical_spill_slot(-1),
4210   _insert_move_when_activated(false),
4211   _spill_state(noDefinitionFound),
4212   _spill_definition_pos(-1),
4213   _register_hint(NULL)
4214 {
4215   _split_parent = this;
4216   _current_split_child = this;
4217 }
4218 
4219 int Interval::calc_to() {
4220   assert(_first != Range::end(), "interval has no range");
4221 
4222   Range* r = _first;
4223   while (r->next() != Range::end()) {
4224     r = r->next();
4225   }
4226   return r->to();
4227 }
4228 
4229 
4230 #ifdef ASSERT
4231 // consistency check of split-children
4232 void Interval::check_split_children() {
4233   if (_split_children != NULL && _split_children->length() > 0) {
4234     assert(is_split_parent(), "only split parents can have children");
4235 
4236     for (int i = 0; i < _split_children->length(); i++) {
4237       Interval* i1 = _split_children->at(i);
4238 
4239       assert(i1->split_parent() == this, "not a split child of this interval");
4240       assert(i1->type() == type(), "must be equal for all split children");
4241       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4242 
4243       for (int j = i + 1; j < _split_children->length(); j++) {
4244         Interval* i2 = _split_children->at(j);
4245 
4246         assert(i1->reg_num() != i2->reg_num(), "same register number");
4247 
4248         if (i1->from() < i2->from()) {
4249           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4250         } else {
4251           assert(i2->from() < i1->from(), "intervals start at same op_id");
4252           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4253         }
4254       }
4255     }
4256   }
4257 }
4258 #endif // ASSERT
4259 
4260 Interval* Interval::register_hint(bool search_split_child) const {
4261   if (!search_split_child) {
4262     return _register_hint;
4263   }
4264 
4265   if (_register_hint != NULL) {
4266     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4267 
4268     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4269       return _register_hint;
4270 
4271     } else if (_register_hint->_split_children != NULL && _register_hint->_split_children->length() > 0) {
4272       // search the first split child that has a register assigned
4273       int len = _register_hint->_split_children->length();
4274       for (int i = 0; i < len; i++) {
4275         Interval* cur = _register_hint->_split_children->at(i);
4276 
4277         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4278           return cur;
4279         }
4280       }
4281     }
4282   }
4283 
4284   // no hint interval found that has a register assigned
4285   return NULL;
4286 }
4287 
4288 
4289 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4290   assert(is_split_parent(), "can only be called for split parents");
4291   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4292 
4293   Interval* result;
4294   if (_split_children == NULL || _split_children->length() == 0) {
4295     result = this;
4296   } else {
4297     result = NULL;
4298     int len = _split_children->length();
4299 
4300     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4301     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4302 
4303     int i;
4304     for (i = 0; i < len; i++) {
4305       Interval* cur = _split_children->at(i);
4306       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4307         if (i > 0) {
4308           // exchange current split child to start of list (faster access for next call)
4309           _split_children->at_put(i, _split_children->at(0));
4310           _split_children->at_put(0, cur);
4311         }
4312 
4313         // interval found
4314         result = cur;
4315         break;
4316       }
4317     }
4318 
4319 #ifdef ASSERT
4320     for (i = 0; i < len; i++) {
4321       Interval* tmp = _split_children->at(i);
4322       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4323         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4324         result->print();
4325         tmp->print();
4326         assert(false, "two valid result intervals found");
4327       }
4328     }
4329 #endif
4330   }
4331 
4332   assert(result != NULL, "no matching interval found");
4333   assert(result->covers(op_id, mode), "op_id not covered by interval");
4334 
4335   return result;
4336 }
4337 
4338 
4339 // returns the last split child that ends before the given op_id
4340 Interval* Interval::split_child_before_op_id(int op_id) {
4341   assert(op_id >= 0, "invalid op_id");
4342 
4343   Interval* parent = split_parent();
4344   Interval* result = NULL;
4345 
4346   assert(parent->_split_children != NULL, "no split children available");
4347   int len = parent->_split_children->length();
4348   assert(len > 0, "no split children available");
4349 
4350   for (int i = len - 1; i >= 0; i--) {
4351     Interval* cur = parent->_split_children->at(i);
4352     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4353       result = cur;
4354     }
4355   }
4356 
4357   assert(result != NULL, "no split child found");
4358   return result;
4359 }
4360 
4361 
4362 // Note: use positions are sorted descending -> first use has highest index
4363 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4364   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4365 
4366   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4367     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4368       return _use_pos_and_kinds.at(i);
4369     }
4370   }
4371   return max_jint;
4372 }
4373 
4374 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4375   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4376 
4377   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4378     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4379       return _use_pos_and_kinds.at(i);
4380     }
4381   }
4382   return max_jint;
4383 }
4384 
4385 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4386   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4387 
4388   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4389     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4390       return _use_pos_and_kinds.at(i);
4391     }
4392   }
4393   return max_jint;
4394 }
4395 
4396 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4397   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4398 
4399   int prev = 0;
4400   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4401     if (_use_pos_and_kinds.at(i) > from) {
4402       return prev;
4403     }
4404     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4405       prev = _use_pos_and_kinds.at(i);
4406     }
4407   }
4408   return prev;
4409 }
4410 
4411 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4412   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4413 
4414   // do not add use positions for precolored intervals because
4415   // they are never used
4416   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4417 #ifdef ASSERT
4418     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4419     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4420       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4421       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4422       if (i > 0) {
4423         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4424       }
4425     }
4426 #endif
4427 
4428     // Note: add_use is called in descending order, so list gets sorted
4429     //       automatically by just appending new use positions
4430     int len = _use_pos_and_kinds.length();
4431     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4432       _use_pos_and_kinds.append(pos);
4433       _use_pos_and_kinds.append(use_kind);
4434     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4435       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4436       _use_pos_and_kinds.at_put(len - 1, use_kind);
4437     }
4438   }
4439 }
4440 
4441 void Interval::add_range(int from, int to) {
4442   assert(from < to, "invalid range");
4443   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4444   assert(from <= first()->to(), "not inserting at begin of interval");
4445 
4446   if (first()->from() <= to) {
4447     // join intersecting ranges
4448     first()->set_from(MIN2(from, first()->from()));
4449     first()->set_to  (MAX2(to,   first()->to()));
4450   } else {
4451     // insert new range
4452     _first = new Range(from, to, first());
4453   }
4454 }
4455 
4456 Interval* Interval::new_split_child() {
4457   // allocate new interval
4458   Interval* result = new Interval(-1);
4459   result->set_type(type());
4460 
4461   Interval* parent = split_parent();
4462   result->_split_parent = parent;
4463   result->set_register_hint(parent);
4464 
4465   // insert new interval in children-list of parent
4466   if (parent->_split_children == NULL) {
4467     assert(is_split_parent(), "list must be initialized at first split");
4468 
4469     parent->_split_children = new IntervalList(4);
4470     parent->_split_children->append(this);
4471   }
4472   parent->_split_children->append(result);
4473 
4474   return result;
4475 }
4476 
4477 // split this interval at the specified position and return
4478 // the remainder as a new interval.
4479 //
4480 // when an interval is split, a bi-directional link is established between the original interval
4481 // (the split parent) and the intervals that are split off this interval (the split children)
4482 // When a split child is split again, the new created interval is also a direct child
4483 // of the original parent (there is no tree of split children stored, but a flat list)
4484 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4485 //
4486 // Note: The new interval has no valid reg_num
4487 Interval* Interval::split(int split_pos) {
4488   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4489 
4490   // allocate new interval
4491   Interval* result = new_split_child();
4492 
4493   // split the ranges
4494   Range* prev = NULL;
4495   Range* cur = _first;
4496   while (cur != Range::end() && cur->to() <= split_pos) {
4497     prev = cur;
4498     cur = cur->next();
4499   }
4500   assert(cur != Range::end(), "split interval after end of last range");
4501 
4502   if (cur->from() < split_pos) {
4503     result->_first = new Range(split_pos, cur->to(), cur->next());
4504     cur->set_to(split_pos);
4505     cur->set_next(Range::end());
4506 
4507   } else {
4508     assert(prev != NULL, "split before start of first range");
4509     result->_first = cur;
4510     prev->set_next(Range::end());
4511   }
4512   result->_current = result->_first;
4513   _cached_to = -1; // clear cached value
4514 
4515   // split list of use positions
4516   int total_len = _use_pos_and_kinds.length();
4517   int start_idx = total_len - 2;
4518   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4519     start_idx -= 2;
4520   }
4521 
4522   intStack new_use_pos_and_kinds(total_len - start_idx);
4523   int i;
4524   for (i = start_idx + 2; i < total_len; i++) {
4525     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4526   }
4527 
4528   _use_pos_and_kinds.trunc_to(start_idx + 2);
4529   result->_use_pos_and_kinds = _use_pos_and_kinds;
4530   _use_pos_and_kinds = new_use_pos_and_kinds;
4531 
4532 #ifdef ASSERT
4533   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4534   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4535   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4536 
4537   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4538     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4539     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4540   }
4541   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4542     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4543     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4544   }
4545 #endif
4546 
4547   return result;
4548 }
4549 
4550 // split this interval at the specified position and return
4551 // the head as a new interval (the original interval is the tail)
4552 //
4553 // Currently, only the first range can be split, and the new interval
4554 // must not have split positions
4555 Interval* Interval::split_from_start(int split_pos) {
4556   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4557   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4558   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4559   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4560 
4561   // allocate new interval
4562   Interval* result = new_split_child();
4563 
4564   // the new created interval has only one range (checked by assertion above),
4565   // so the splitting of the ranges is very simple
4566   result->add_range(_first->from(), split_pos);
4567 
4568   if (split_pos == _first->to()) {
4569     assert(_first->next() != Range::end(), "must not be at end");
4570     _first = _first->next();
4571   } else {
4572     _first->set_from(split_pos);
4573   }
4574 
4575   return result;
4576 }
4577 
4578 
4579 // returns true if the op_id is inside the interval
4580 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4581   Range* cur  = _first;
4582 
4583   while (cur != Range::end() && cur->to() < op_id) {
4584     cur = cur->next();
4585   }
4586   if (cur != Range::end()) {
4587     assert(cur->to() != cur->next()->from(), "ranges not separated");
4588 
4589     if (mode == LIR_OpVisitState::outputMode) {
4590       return cur->from() <= op_id && op_id < cur->to();
4591     } else {
4592       return cur->from() <= op_id && op_id <= cur->to();
4593     }
4594   }
4595   return false;
4596 }
4597 
4598 // returns true if the interval has any hole between hole_from and hole_to
4599 // (even if the hole has only the length 1)
4600 bool Interval::has_hole_between(int hole_from, int hole_to) {
4601   assert(hole_from < hole_to, "check");
4602   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4603 
4604   Range* cur  = _first;
4605   while (cur != Range::end()) {
4606     assert(cur->to() < cur->next()->from(), "no space between ranges");
4607 
4608     // hole-range starts before this range -> hole
4609     if (hole_from < cur->from()) {
4610       return true;
4611 
4612     // hole-range completely inside this range -> no hole
4613     } else if (hole_to <= cur->to()) {
4614       return false;
4615 
4616     // overlapping of hole-range with this range -> hole
4617     } else if (hole_from <= cur->to()) {
4618       return true;
4619     }
4620 
4621     cur = cur->next();
4622   }
4623 
4624   return false;
4625 }
4626 
4627 // Check if there is an intersection with any of the split children of 'interval'
4628 bool Interval::intersects_any_children_of(Interval* interval) const {
4629   if (interval->_split_children != NULL) {
4630     for (int i = 0; i < interval->_split_children->length(); i++) {
4631       if (intersects(interval->_split_children->at(i))) {
4632         return true;
4633       }
4634     }
4635   }
4636   return false;
4637 }
4638 
4639 
4640 #ifndef PRODUCT
4641 void Interval::print_on(outputStream* out, bool is_cfg_printer) const {
4642   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4643   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4644 
4645   const char* type_name;
4646   if (reg_num() < LIR_OprDesc::vreg_base) {
4647     type_name = "fixed";
4648   } else {
4649     type_name = type2name(type());
4650   }
4651   out->print("%d %s ", reg_num(), type_name);
4652 
4653   if (is_cfg_printer) {
4654     // Special version for compatibility with C1 Visualizer.
4655     LIR_Opr opr = LinearScan::get_operand(reg_num());
4656     if (opr->is_valid()) {
4657       out->print("\"");
4658       opr->print(out);
4659       out->print("\" ");
4660     }
4661   } else {
4662     // Improved output for normal debugging.
4663     if (reg_num() < LIR_OprDesc::vreg_base) {
4664       LinearScan::print_reg_num(out, assigned_reg());
4665     } else if (assigned_reg() != -1 && (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4666       LinearScan::calc_operand_for_interval(this)->print(out);
4667     } else {
4668       // Virtual register that has no assigned register yet.
4669       out->print("[ANY]");
4670     }
4671     out->print(" ");
4672   }
4673   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4674 
4675   // print ranges
4676   Range* cur = _first;
4677   while (cur != Range::end()) {
4678     cur->print(out);
4679     cur = cur->next();
4680     assert(cur != NULL, "range list not closed with range sentinel");
4681   }
4682 
4683   // print use positions
4684   int prev = 0;
4685   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4686   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4687     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4688     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4689 
4690     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4691     prev = _use_pos_and_kinds.at(i);
4692   }
4693 
4694   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4695   out->cr();
4696 }
4697 
4698 void Interval::print_parent() const {
4699   if (_split_parent != this) {
4700     _split_parent->print_on(tty);
4701   } else {
4702     tty->print_cr("Parent: this");
4703   }
4704 }
4705 
4706 void Interval::print_children() const {
4707   if (_split_children == NULL) {
4708     tty->print_cr("Children: []");
4709   } else {
4710     tty->print_cr("Children:");
4711     for (int i = 0; i < _split_children->length(); i++) {
4712       tty->print("%d: ", i);
4713       _split_children->at(i)->print_on(tty);
4714     }
4715   }
4716 }
4717 #endif // NOT PRODUCT
4718 
4719 
4720 
4721 
4722 // **** Implementation of IntervalWalker ****************************
4723 
4724 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4725  : _compilation(allocator->compilation())
4726  , _allocator(allocator)
4727 {
4728   _unhandled_first[fixedKind] = unhandled_fixed_first;
4729   _unhandled_first[anyKind]   = unhandled_any_first;
4730   _active_first[fixedKind]    = Interval::end();
4731   _inactive_first[fixedKind]  = Interval::end();
4732   _active_first[anyKind]      = Interval::end();
4733   _inactive_first[anyKind]    = Interval::end();
4734   _current_position = -1;
4735   _current = NULL;
4736   next_interval();
4737 }
4738 
4739 
4740 // append interval in order of current range from()
4741 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4742   Interval* prev = NULL;
4743   Interval* cur  = *list;
4744   while (cur->current_from() < interval->current_from()) {
4745     prev = cur; cur = cur->next();
4746   }
4747   if (prev == NULL) {
4748     *list = interval;
4749   } else {
4750     prev->set_next(interval);
4751   }
4752   interval->set_next(cur);
4753 }
4754 
4755 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4756   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4757 
4758   Interval* prev = NULL;
4759   Interval* cur  = *list;
4760   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4761     prev = cur; cur = cur->next();
4762   }
4763   if (prev == NULL) {
4764     *list = interval;
4765   } else {
4766     prev->set_next(interval);
4767   }
4768   interval->set_next(cur);
4769 }
4770 
4771 
4772 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4773   while (*list != Interval::end() && *list != i) {
4774     list = (*list)->next_addr();
4775   }
4776   if (*list != Interval::end()) {
4777     assert(*list == i, "check");
4778     *list = (*list)->next();
4779     return true;
4780   } else {
4781     return false;
4782   }
4783 }
4784 
4785 void IntervalWalker::remove_from_list(Interval* i) {
4786   bool deleted;
4787 
4788   if (i->state() == activeState) {
4789     deleted = remove_from_list(active_first_addr(anyKind), i);
4790   } else {
4791     assert(i->state() == inactiveState, "invalid state");
4792     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4793   }
4794 
4795   assert(deleted, "interval has not been found in list");
4796 }
4797 
4798 
4799 void IntervalWalker::walk_to(IntervalState state, int from) {
4800   assert (state == activeState || state == inactiveState, "wrong state");
4801   for_each_interval_kind(kind) {
4802     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4803     Interval* next   = *prev;
4804     while (next->current_from() <= from) {
4805       Interval* cur = next;
4806       next = cur->next();
4807 
4808       bool range_has_changed = false;
4809       while (cur->current_to() <= from) {
4810         cur->next_range();
4811         range_has_changed = true;
4812       }
4813 
4814       // also handle move from inactive list to active list
4815       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4816 
4817       if (range_has_changed) {
4818         // remove cur from list
4819         *prev = next;
4820         if (cur->current_at_end()) {
4821           // move to handled state (not maintained as a list)
4822           cur->set_state(handledState);
4823           DEBUG_ONLY(interval_moved(cur, kind, state, handledState);)
4824         } else if (cur->current_from() <= from){
4825           // sort into active list
4826           append_sorted(active_first_addr(kind), cur);
4827           cur->set_state(activeState);
4828           if (*prev == cur) {
4829             assert(state == activeState, "check");
4830             prev = cur->next_addr();
4831           }
4832           DEBUG_ONLY(interval_moved(cur, kind, state, activeState);)
4833         } else {
4834           // sort into inactive list
4835           append_sorted(inactive_first_addr(kind), cur);
4836           cur->set_state(inactiveState);
4837           if (*prev == cur) {
4838             assert(state == inactiveState, "check");
4839             prev = cur->next_addr();
4840           }
4841           DEBUG_ONLY(interval_moved(cur, kind, state, inactiveState);)
4842         }
4843       } else {
4844         prev = cur->next_addr();
4845         continue;
4846       }
4847     }
4848   }
4849 }
4850 
4851 
4852 void IntervalWalker::next_interval() {
4853   IntervalKind kind;
4854   Interval* any   = _unhandled_first[anyKind];
4855   Interval* fixed = _unhandled_first[fixedKind];
4856 
4857   if (any != Interval::end()) {
4858     // intervals may start at same position -> prefer fixed interval
4859     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4860 
4861     assert (kind == fixedKind && fixed->from() <= any->from() ||
4862             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4863     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4864 
4865   } else if (fixed != Interval::end()) {
4866     kind = fixedKind;
4867   } else {
4868     _current = NULL; return;
4869   }
4870   _current_kind = kind;
4871   _current = _unhandled_first[kind];
4872   _unhandled_first[kind] = _current->next();
4873   _current->set_next(Interval::end());
4874   _current->rewind_range();
4875 }
4876 
4877 
4878 void IntervalWalker::walk_to(int lir_op_id) {
4879   assert(_current_position <= lir_op_id, "can not walk backwards");
4880   while (current() != NULL) {
4881     bool is_active = current()->from() <= lir_op_id;
4882     int id = is_active ? current()->from() : lir_op_id;
4883 
4884     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4885 
4886     // set _current_position prior to call of walk_to
4887     _current_position = id;
4888 
4889     // call walk_to even if _current_position == id
4890     walk_to(activeState, id);
4891     walk_to(inactiveState, id);
4892 
4893     if (is_active) {
4894       current()->set_state(activeState);
4895       if (activate_current()) {
4896         append_sorted(active_first_addr(current_kind()), current());
4897         DEBUG_ONLY(interval_moved(current(), current_kind(), unhandledState, activeState);)
4898       }
4899 
4900       next_interval();
4901     } else {
4902       return;
4903     }
4904   }
4905 }
4906 
4907 #ifdef ASSERT
4908 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4909   if (TraceLinearScanLevel >= 4) {
4910     #define print_state(state) \
4911     switch(state) {\
4912       case unhandledState: tty->print("unhandled"); break;\
4913       case activeState: tty->print("active"); break;\
4914       case inactiveState: tty->print("inactive"); break;\
4915       case handledState: tty->print("handled"); break;\
4916       default: ShouldNotReachHere(); \
4917     }
4918 
4919     print_state(from); tty->print(" to "); print_state(to);
4920     tty->fill_to(23);
4921     interval->print();
4922 
4923     #undef print_state
4924   }
4925 }
4926 #endif // ASSERT
4927 
4928 // **** Implementation of LinearScanWalker **************************
4929 
4930 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4931   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4932   , _move_resolver(allocator)
4933 {
4934   for (int i = 0; i < LinearScan::nof_regs; i++) {
4935     _spill_intervals[i] = new IntervalList(2);
4936   }
4937 }
4938 
4939 
4940 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4941   for (int i = _first_reg; i <= _last_reg; i++) {
4942     _use_pos[i] = max_jint;
4943 
4944     if (!only_process_use_pos) {
4945       _block_pos[i] = max_jint;
4946       _spill_intervals[i]->clear();
4947     }
4948   }
4949 }
4950 
4951 inline void LinearScanWalker::exclude_from_use(int reg) {
4952   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4953   if (reg >= _first_reg && reg <= _last_reg) {
4954     _use_pos[reg] = 0;
4955   }
4956 }
4957 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4958   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4959 
4960   exclude_from_use(i->assigned_reg());
4961   exclude_from_use(i->assigned_regHi());
4962 }
4963 
4964 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4965   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4966 
4967   if (reg >= _first_reg && reg <= _last_reg) {
4968     if (_use_pos[reg] > use_pos) {
4969       _use_pos[reg] = use_pos;
4970     }
4971     if (!only_process_use_pos) {
4972       _spill_intervals[reg]->append(i);
4973     }
4974   }
4975 }
4976 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4977   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4978   if (use_pos != -1) {
4979     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4980     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4981   }
4982 }
4983 
4984 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4985   if (reg >= _first_reg && reg <= _last_reg) {
4986     if (_block_pos[reg] > block_pos) {
4987       _block_pos[reg] = block_pos;
4988     }
4989     if (_use_pos[reg] > block_pos) {
4990       _use_pos[reg] = block_pos;
4991     }
4992   }
4993 }
4994 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4995   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4996   if (block_pos != -1) {
4997     set_block_pos(i->assigned_reg(), i, block_pos);
4998     set_block_pos(i->assigned_regHi(), i, block_pos);
4999   }
5000 }
5001 
5002 
5003 void LinearScanWalker::free_exclude_active_fixed() {
5004   Interval* list = active_first(fixedKind);
5005   while (list != Interval::end()) {
5006     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
5007     exclude_from_use(list);
5008     list = list->next();
5009   }
5010 }
5011 
5012 void LinearScanWalker::free_exclude_active_any() {
5013   Interval* list = active_first(anyKind);
5014   while (list != Interval::end()) {
5015     exclude_from_use(list);
5016     list = list->next();
5017   }
5018 }
5019 
5020 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
5021   Interval* list = inactive_first(fixedKind);
5022   while (list != Interval::end()) {
5023     if (cur->to() <= list->current_from()) {
5024       assert(list->current_intersects_at(cur) == -1, "must not intersect");
5025       set_use_pos(list, list->current_from(), true);
5026     } else {
5027       set_use_pos(list, list->current_intersects_at(cur), true);
5028     }
5029     list = list->next();
5030   }
5031 }
5032 
5033 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
5034   Interval* list = inactive_first(anyKind);
5035   while (list != Interval::end()) {
5036     set_use_pos(list, list->current_intersects_at(cur), true);
5037     list = list->next();
5038   }
5039 }
5040 
5041 void LinearScanWalker::spill_exclude_active_fixed() {
5042   Interval* list = active_first(fixedKind);
5043   while (list != Interval::end()) {
5044     exclude_from_use(list);
5045     list = list->next();
5046   }
5047 }
5048 
5049 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
5050   Interval* list = inactive_first(fixedKind);
5051   while (list != Interval::end()) {
5052     if (cur->to() > list->current_from()) {
5053       set_block_pos(list, list->current_intersects_at(cur));
5054     } else {
5055       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5056     }
5057 
5058     list = list->next();
5059   }
5060 }
5061 
5062 void LinearScanWalker::spill_collect_active_any() {
5063   Interval* list = active_first(anyKind);
5064   while (list != Interval::end()) {
5065     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5066     list = list->next();
5067   }
5068 }
5069 
5070 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5071   Interval* list = inactive_first(anyKind);
5072   while (list != Interval::end()) {
5073     if (list->current_intersects(cur)) {
5074       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5075     }
5076     list = list->next();
5077   }
5078 }
5079 
5080 
5081 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5082   // output all moves here. When source and target are equal, the move is
5083   // optimized away later in assign_reg_nums
5084 
5085   op_id = (op_id + 1) & ~1;
5086   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5087   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5088 
5089   // calculate index of instruction inside instruction list of current block
5090   // the minimal index (for a block with no spill moves) can be calculated because the
5091   // numbering of instructions is known.
5092   // When the block already contains spill moves, the index must be increased until the
5093   // correct index is reached.
5094   LIR_OpList* list = op_block->lir()->instructions_list();
5095   int index = (op_id - list->at(0)->id()) / 2;
5096   assert(list->at(index)->id() <= op_id, "error in calculation");
5097 
5098   while (list->at(index)->id() != op_id) {
5099     index++;
5100     assert(0 <= index && index < list->length(), "index out of bounds");
5101   }
5102   assert(1 <= index && index < list->length(), "index out of bounds");
5103   assert(list->at(index)->id() == op_id, "error in calculation");
5104 
5105   // insert new instruction before instruction at position index
5106   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5107   _move_resolver.add_mapping(src_it, dst_it);
5108 }
5109 
5110 
5111 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5112   int from_block_nr = min_block->linear_scan_number();
5113   int to_block_nr = max_block->linear_scan_number();
5114 
5115   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5116   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5117   assert(from_block_nr < to_block_nr, "must cross block boundary");
5118 
5119   // Try to split at end of max_block. If this would be after
5120   // max_split_pos, then use the begin of max_block
5121   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5122   if (optimal_split_pos > max_split_pos) {
5123     optimal_split_pos = max_block->first_lir_instruction_id();
5124   }
5125 
5126   int min_loop_depth = max_block->loop_depth();
5127   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5128     BlockBegin* cur = block_at(i);
5129 
5130     if (cur->loop_depth() < min_loop_depth) {
5131       // block with lower loop-depth found -> split at the end of this block
5132       min_loop_depth = cur->loop_depth();
5133       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5134     }
5135   }
5136   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5137 
5138   return optimal_split_pos;
5139 }
5140 
5141 
5142 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5143   int optimal_split_pos = -1;
5144   if (min_split_pos == max_split_pos) {
5145     // trivial case, no optimization of split position possible
5146     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5147     optimal_split_pos = min_split_pos;
5148 
5149   } else {
5150     assert(min_split_pos < max_split_pos, "must be true then");
5151     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5152 
5153     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5154     // beginning of a block, then min_split_pos is also a possible split position.
5155     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5156     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5157 
5158     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5159     // when an interval ends at the end of the last block of the method
5160     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5161     // block at this op_id)
5162     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5163 
5164     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5165     if (min_block == max_block) {
5166       // split position cannot be moved to block boundary, so split as late as possible
5167       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5168       optimal_split_pos = max_split_pos;
5169 
5170     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5171       // Do not move split position if the interval has a hole before max_split_pos.
5172       // Intervals resulting from Phi-Functions have more than one definition (marked
5173       // as mustHaveRegister) with a hole before each definition. When the register is needed
5174       // for the second definition, an earlier reloading is unnecessary.
5175       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5176       optimal_split_pos = max_split_pos;
5177 
5178     } else {
5179       // seach optimal block boundary between min_split_pos and max_split_pos
5180       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5181 
5182       if (do_loop_optimization) {
5183         // Loop optimization: if a loop-end marker is found between min- and max-position,
5184         // then split before this loop
5185         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5186         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5187 
5188         assert(loop_end_pos > min_split_pos, "invalid order");
5189         if (loop_end_pos < max_split_pos) {
5190           // loop-end marker found between min- and max-position
5191           // if it is not the end marker for the same loop as the min-position, then move
5192           // the max-position to this loop block.
5193           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5194           // of the interval (normally, only mustHaveRegister causes a reloading)
5195           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5196 
5197           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5198           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5199 
5200           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5201           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5202             optimal_split_pos = -1;
5203             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5204           } else {
5205             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5206           }
5207         }
5208       }
5209 
5210       if (optimal_split_pos == -1) {
5211         // not calculated by loop optimization
5212         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5213       }
5214     }
5215   }
5216   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5217 
5218   return optimal_split_pos;
5219 }
5220 
5221 
5222 /*
5223   split an interval at the optimal position between min_split_pos and
5224   max_split_pos in two parts:
5225   1) the left part has already a location assigned
5226   2) the right part is sorted into to the unhandled-list
5227 */
5228 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5229   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5230   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5231 
5232   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5233   assert(current_position() < min_split_pos, "cannot split before current position");
5234   assert(min_split_pos <= max_split_pos,     "invalid order");
5235   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5236 
5237   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5238 
5239   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5240   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5241   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5242 
5243   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5244     // the split position would be just before the end of the interval
5245     // -> no split at all necessary
5246     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5247     return;
5248   }
5249 
5250   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5251   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5252 
5253   if (!allocator()->is_block_begin(optimal_split_pos)) {
5254     // move position before actual instruction (odd op_id)
5255     optimal_split_pos = (optimal_split_pos - 1) | 1;
5256   }
5257 
5258   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5259   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5260   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5261 
5262   Interval* split_part = it->split(optimal_split_pos);
5263 
5264   allocator()->append_interval(split_part);
5265   allocator()->copy_register_flags(it, split_part);
5266   split_part->set_insert_move_when_activated(move_necessary);
5267   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5268 
5269   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5270   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5271   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5272 }
5273 
5274 /*
5275   split an interval at the optimal position between min_split_pos and
5276   max_split_pos in two parts:
5277   1) the left part has already a location assigned
5278   2) the right part is always on the stack and therefore ignored in further processing
5279 */
5280 void LinearScanWalker::split_for_spilling(Interval* it) {
5281   // calculate allowed range of splitting position
5282   int max_split_pos = current_position();
5283   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5284 
5285   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5286   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5287 
5288   assert(it->state() == activeState,     "why spill interval that is not active?");
5289   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5290   assert(min_split_pos <= max_split_pos, "invalid order");
5291   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5292   assert(current_position() < it->to(),  "interval must not end before current position");
5293 
5294   if (min_split_pos == it->from()) {
5295     // the whole interval is never used, so spill it entirely to memory
5296     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5297     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5298 
5299     allocator()->assign_spill_slot(it);
5300     allocator()->change_spill_state(it, min_split_pos);
5301 
5302     // Also kick parent intervals out of register to memory when they have no use
5303     // position. This avoids short interval in register surrounded by intervals in
5304     // memory -> avoid useless moves from memory to register and back
5305     Interval* parent = it;
5306     while (parent != NULL && parent->is_split_child()) {
5307       parent = parent->split_child_before_op_id(parent->from());
5308 
5309       if (parent->assigned_reg() < LinearScan::nof_regs) {
5310         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5311           // parent is never used, so kick it out of its assigned register
5312           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5313           allocator()->assign_spill_slot(parent);
5314         } else {
5315           // do not go further back because the register is actually used by the interval
5316           parent = NULL;
5317         }
5318       }
5319     }
5320 
5321   } else {
5322     // search optimal split pos, split interval and spill only the right hand part
5323     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5324 
5325     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5326     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5327     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5328 
5329     if (!allocator()->is_block_begin(optimal_split_pos)) {
5330       // move position before actual instruction (odd op_id)
5331       optimal_split_pos = (optimal_split_pos - 1) | 1;
5332     }
5333 
5334     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5335     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5336     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5337 
5338     Interval* spilled_part = it->split(optimal_split_pos);
5339     allocator()->append_interval(spilled_part);
5340     allocator()->assign_spill_slot(spilled_part);
5341     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5342 
5343     if (!allocator()->is_block_begin(optimal_split_pos)) {
5344       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5345       insert_move(optimal_split_pos, it, spilled_part);
5346     }
5347 
5348     // the current_split_child is needed later when moves are inserted for reloading
5349     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5350     spilled_part->make_current_split_child();
5351 
5352     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5353     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5354     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5355   }
5356 }
5357 
5358 
5359 void LinearScanWalker::split_stack_interval(Interval* it) {
5360   int min_split_pos = current_position() + 1;
5361   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5362 
5363   split_before_usage(it, min_split_pos, max_split_pos);
5364 }
5365 
5366 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5367   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5368   int max_split_pos = register_available_until;
5369 
5370   split_before_usage(it, min_split_pos, max_split_pos);
5371 }
5372 
5373 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5374   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5375 
5376   int current_pos = current_position();
5377   if (it->state() == inactiveState) {
5378     // the interval is currently inactive, so no spill slot is needed for now.
5379     // when the split part is activated, the interval has a new chance to get a register,
5380     // so in the best case no stack slot is necessary
5381     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5382     split_before_usage(it, current_pos + 1, current_pos + 1);
5383 
5384   } else {
5385     // search the position where the interval must have a register and split
5386     // at the optimal position before.
5387     // The new created part is added to the unhandled list and will get a register
5388     // when it is activated
5389     int min_split_pos = current_pos + 1;
5390     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5391 
5392     split_before_usage(it, min_split_pos, max_split_pos);
5393 
5394     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5395     split_for_spilling(it);
5396   }
5397 }
5398 
5399 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5400   int min_full_reg = any_reg;
5401   int max_partial_reg = any_reg;
5402 
5403   for (int i = _first_reg; i <= _last_reg; i++) {
5404     if (i == ignore_reg) {
5405       // this register must be ignored
5406 
5407     } else if (_use_pos[i] >= interval_to) {
5408       // this register is free for the full interval
5409       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5410         min_full_reg = i;
5411       }
5412     } else if (_use_pos[i] > reg_needed_until) {
5413       // this register is at least free until reg_needed_until
5414       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5415         max_partial_reg = i;
5416       }
5417     }
5418   }
5419 
5420   if (min_full_reg != any_reg) {
5421     return min_full_reg;
5422   } else if (max_partial_reg != any_reg) {
5423     *need_split = true;
5424     return max_partial_reg;
5425   } else {
5426     return any_reg;
5427   }
5428 }
5429 
5430 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5431   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5432 
5433   int min_full_reg = any_reg;
5434   int max_partial_reg = any_reg;
5435 
5436   for (int i = _first_reg; i < _last_reg; i+=2) {
5437     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5438       // this register is free for the full interval
5439       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5440         min_full_reg = i;
5441       }
5442     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5443       // this register is at least free until reg_needed_until
5444       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5445         max_partial_reg = i;
5446       }
5447     }
5448   }
5449 
5450   if (min_full_reg != any_reg) {
5451     return min_full_reg;
5452   } else if (max_partial_reg != any_reg) {
5453     *need_split = true;
5454     return max_partial_reg;
5455   } else {
5456     return any_reg;
5457   }
5458 }
5459 
5460 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5461   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5462 
5463   init_use_lists(true);
5464   free_exclude_active_fixed();
5465   free_exclude_active_any();
5466   free_collect_inactive_fixed(cur);
5467   free_collect_inactive_any(cur);
5468   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5469 
5470   // _use_pos contains the start of the next interval that has this register assigned
5471   // (either as a fixed register or a normal allocated register in the past)
5472   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5473 #ifdef ASSERT
5474   if (TraceLinearScanLevel >= 4) {
5475     tty->print_cr("      state of registers:");
5476     for (int i = _first_reg; i <= _last_reg; i++) {
5477       tty->print("      reg %d (", i);
5478       LinearScan::print_reg_num(i);
5479       tty->print_cr("): use_pos: %d", _use_pos[i]);
5480     }
5481   }
5482 #endif
5483 
5484   int hint_reg, hint_regHi;
5485   Interval* register_hint = cur->register_hint();
5486   if (register_hint != NULL) {
5487     hint_reg = register_hint->assigned_reg();
5488     hint_regHi = register_hint->assigned_regHi();
5489 
5490     if (_num_phys_regs == 2 && allocator()->is_precolored_cpu_interval(register_hint)) {
5491       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5492       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5493     }
5494 #ifdef ASSERT
5495     if (TraceLinearScanLevel >= 4) {
5496       tty->print("      hint registers %d (", hint_reg);
5497       LinearScan::print_reg_num(hint_reg);
5498       tty->print("), %d (", hint_regHi);
5499       LinearScan::print_reg_num(hint_regHi);
5500       tty->print(") from interval ");
5501       register_hint->print();
5502     }
5503 #endif
5504   } else {
5505     hint_reg = any_reg;
5506     hint_regHi = any_reg;
5507   }
5508   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5509   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5510 
5511   // the register must be free at least until this position
5512   int reg_needed_until = cur->from() + 1;
5513   int interval_to = cur->to();
5514 
5515   bool need_split = false;
5516   int split_pos;
5517   int reg;
5518   int regHi = any_reg;
5519 
5520   if (_adjacent_regs) {
5521     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5522     regHi = reg + 1;
5523     if (reg == any_reg) {
5524       return false;
5525     }
5526     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5527 
5528   } else {
5529     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5530     if (reg == any_reg) {
5531       return false;
5532     }
5533     split_pos = _use_pos[reg];
5534 
5535     if (_num_phys_regs == 2) {
5536       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5537 
5538       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5539         // do not split interval if only one register can be assigned until the split pos
5540         // (when one register is found for the whole interval, split&spill is only
5541         // performed for the hi register)
5542         return false;
5543 
5544       } else if (regHi != any_reg) {
5545         split_pos = MIN2(split_pos, _use_pos[regHi]);
5546 
5547         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5548         if (reg > regHi) {
5549           int temp = reg;
5550           reg = regHi;
5551           regHi = temp;
5552         }
5553       }
5554     }
5555   }
5556 
5557   cur->assign_reg(reg, regHi);
5558 #ifdef ASSERT
5559   if (TraceLinearScanLevel >= 2) {
5560     tty->print("      selected registers %d (", reg);
5561     LinearScan::print_reg_num(reg);
5562     tty->print("), %d (", regHi);
5563     LinearScan::print_reg_num(regHi);
5564     tty->print_cr(")");
5565   }
5566 #endif
5567   assert(split_pos > 0, "invalid split_pos");
5568   if (need_split) {
5569     // register not available for full interval, so split it
5570     split_when_partial_register_available(cur, split_pos);
5571   }
5572 
5573   // only return true if interval is completely assigned
5574   return _num_phys_regs == 1 || regHi != any_reg;
5575 }
5576 
5577 
5578 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5579   int max_reg = any_reg;
5580 
5581   for (int i = _first_reg; i <= _last_reg; i++) {
5582     if (i == ignore_reg) {
5583       // this register must be ignored
5584 
5585     } else if (_use_pos[i] > reg_needed_until) {
5586       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5587         max_reg = i;
5588       }
5589     }
5590   }
5591 
5592   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5593     *need_split = true;
5594   }
5595 
5596   return max_reg;
5597 }
5598 
5599 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5600   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5601 
5602   int max_reg = any_reg;
5603 
5604   for (int i = _first_reg; i < _last_reg; i+=2) {
5605     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5606       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5607         max_reg = i;
5608       }
5609     }
5610   }
5611 
5612   if (max_reg != any_reg &&
5613       (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5614     *need_split = true;
5615   }
5616 
5617   return max_reg;
5618 }
5619 
5620 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5621   assert(reg != any_reg, "no register assigned");
5622 
5623   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5624     Interval* it = _spill_intervals[reg]->at(i);
5625     remove_from_list(it);
5626     split_and_spill_interval(it);
5627   }
5628 
5629   if (regHi != any_reg) {
5630     IntervalList* processed = _spill_intervals[reg];
5631     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5632       Interval* it = _spill_intervals[regHi]->at(i);
5633       if (processed->find(it) == -1) {
5634         remove_from_list(it);
5635         split_and_spill_interval(it);
5636       }
5637     }
5638   }
5639 }
5640 
5641 
5642 // Split an Interval and spill it to memory so that cur can be placed in a register
5643 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5644   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5645 
5646   // collect current usage of registers
5647   init_use_lists(false);
5648   spill_exclude_active_fixed();
5649   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5650   spill_block_inactive_fixed(cur);
5651   spill_collect_active_any();
5652   spill_collect_inactive_any(cur);
5653 
5654 #ifdef ASSERT
5655   if (TraceLinearScanLevel >= 4) {
5656     tty->print_cr("      state of registers:");
5657     for (int i = _first_reg; i <= _last_reg; i++) {
5658       tty->print("      reg %d(", i);
5659       LinearScan::print_reg_num(i);
5660       tty->print("): use_pos: %d, block_pos: %d, intervals: ", _use_pos[i], _block_pos[i]);
5661       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5662         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5663       }
5664       tty->cr();
5665     }
5666   }
5667 #endif
5668 
5669   // the register must be free at least until this position
5670   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5671   int interval_to = cur->to();
5672   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5673 
5674   int split_pos = 0;
5675   int use_pos = 0;
5676   bool need_split = false;
5677   int reg, regHi;
5678 
5679   if (_adjacent_regs) {
5680     reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5681     regHi = reg + 1;
5682 
5683     if (reg != any_reg) {
5684       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5685       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5686     }
5687   } else {
5688     reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5689     regHi = any_reg;
5690 
5691     if (reg != any_reg) {
5692       use_pos = _use_pos[reg];
5693       split_pos = _block_pos[reg];
5694 
5695       if (_num_phys_regs == 2) {
5696         if (cur->assigned_reg() != any_reg) {
5697           regHi = reg;
5698           reg = cur->assigned_reg();
5699         } else {
5700           regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5701           if (regHi != any_reg) {
5702             use_pos = MIN2(use_pos, _use_pos[regHi]);
5703             split_pos = MIN2(split_pos, _block_pos[regHi]);
5704           }
5705         }
5706 
5707         if (regHi != any_reg && reg > regHi) {
5708           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5709           int temp = reg;
5710           reg = regHi;
5711           regHi = temp;
5712         }
5713       }
5714     }
5715   }
5716 
5717   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5718     // the first use of cur is later than the spilling position -> spill cur
5719     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5720 
5721     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5722       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5723       // assign a reasonable register and do a bailout in product mode to avoid errors
5724       allocator()->assign_spill_slot(cur);
5725       BAILOUT("LinearScan: no register found");
5726     }
5727 
5728     split_and_spill_interval(cur);
5729   } else {
5730 #ifdef ASSERT
5731     if (TraceLinearScanLevel >= 4) {
5732       tty->print("decided to use register %d (", reg);
5733       LinearScan::print_reg_num(reg);
5734       tty->print("), %d (", regHi);
5735       LinearScan::print_reg_num(regHi);
5736       tty->print_cr(")");
5737     }
5738 #endif
5739     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5740     assert(split_pos > 0, "invalid split_pos");
5741     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5742 
5743     cur->assign_reg(reg, regHi);
5744     if (need_split) {
5745       // register not available for full interval, so split it
5746       split_when_partial_register_available(cur, split_pos);
5747     }
5748 
5749     // perform splitting and spilling for all affected intervalls
5750     split_and_spill_intersecting_intervals(reg, regHi);
5751   }
5752 }
5753 
5754 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5755 #ifdef X86
5756   // fast calculation of intervals that can never get a register because the
5757   // the next instruction is a call that blocks all registers
5758   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5759 
5760   // check if this interval is the result of a split operation
5761   // (an interval got a register until this position)
5762   int pos = cur->from();
5763   if ((pos & 1) == 1) {
5764     // the current instruction is a call that blocks all registers
5765     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5766       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5767 
5768       // safety check that there is really no register available
5769       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5770       return true;
5771     }
5772 
5773   }
5774 #endif
5775   return false;
5776 }
5777 
5778 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5779   BasicType type = cur->type();
5780   _num_phys_regs = LinearScan::num_physical_regs(type);
5781   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5782 
5783   if (pd_init_regs_for_alloc(cur)) {
5784     // the appropriate register range was selected.
5785   } else if (type == T_FLOAT || type == T_DOUBLE) {
5786     _first_reg = pd_first_fpu_reg;
5787     _last_reg = pd_last_fpu_reg;
5788   } else {
5789     _first_reg = pd_first_cpu_reg;
5790     _last_reg = FrameMap::last_cpu_reg();
5791   }
5792 
5793   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5794   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5795 }
5796 
5797 
5798 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5799   if (op->code() != lir_move) {
5800     return false;
5801   }
5802   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5803 
5804   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5805   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5806   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5807 }
5808 
5809 // optimization (especially for phi functions of nested loops):
5810 // assign same spill slot to non-intersecting intervals
5811 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5812   if (cur->is_split_child()) {
5813     // optimization is only suitable for split parents
5814     return;
5815   }
5816 
5817   Interval* register_hint = cur->register_hint(false);
5818   if (register_hint == NULL) {
5819     // cur is not the target of a move, otherwise register_hint would be set
5820     return;
5821   }
5822   assert(register_hint->is_split_parent(), "register hint must be split parent");
5823 
5824   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5825     // combining the stack slots for intervals where spill move optimization is applied
5826     // is not benefitial and would cause problems
5827     return;
5828   }
5829 
5830   int begin_pos = cur->from();
5831   int end_pos = cur->to();
5832   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5833     // safety check that lir_op_with_id is allowed
5834     return;
5835   }
5836 
5837   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5838     // cur and register_hint are not connected with two moves
5839     return;
5840   }
5841 
5842   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5843   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5844   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5845     // register_hint must be split, otherwise the re-writing of use positions does not work
5846     return;
5847   }
5848 
5849   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5850   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5851   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5852   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5853 
5854   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5855     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5856     return;
5857   }
5858   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5859   assert(!cur->intersects(register_hint), "cur should not intersect register_hint");
5860 
5861   if (cur->intersects_any_children_of(register_hint)) {
5862     // Bail out if cur intersects any split children of register_hint, which have the same spill slot as their parent. An overlap of two intervals with
5863     // the same spill slot could result in a situation where both intervals are spilled at the same time to the same stack location which is not correct.
5864     return;
5865   }
5866 
5867   // modify intervals such that cur gets the same stack slot as register_hint
5868   // delete use positions to prevent the intervals to get a register at beginning
5869   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5870   cur->remove_first_use_pos();
5871   end_hint->remove_first_use_pos();
5872 }
5873 
5874 
5875 // allocate a physical register or memory location to an interval
5876 bool LinearScanWalker::activate_current() {
5877   Interval* cur = current();
5878   bool result = true;
5879 
5880   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5881   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5882 
5883   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5884     // activating an interval that has a stack slot assigned -> split it at first use position
5885     // used for method parameters
5886     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5887 
5888     split_stack_interval(cur);
5889     result = false;
5890 
5891   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5892     // activating an interval that must start in a stack slot, but may get a register later
5893     // used for lir_roundfp: rounding is done by store to stack and reload later
5894     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5895     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5896 
5897     allocator()->assign_spill_slot(cur);
5898     split_stack_interval(cur);
5899     result = false;
5900 
5901   } else if (cur->assigned_reg() == any_reg) {
5902     // interval has not assigned register -> normal allocation
5903     // (this is the normal case for most intervals)
5904     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5905 
5906     // assign same spill slot to non-intersecting intervals
5907     combine_spilled_intervals(cur);
5908 
5909     init_vars_for_alloc(cur);
5910     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5911       // no empty register available.
5912       // split and spill another interval so that this interval gets a register
5913       alloc_locked_reg(cur);
5914     }
5915 
5916     // spilled intervals need not be move to active-list
5917     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5918       result = false;
5919     }
5920   }
5921 
5922   // load spilled values that become active from stack slot to register
5923   if (cur->insert_move_when_activated()) {
5924     assert(cur->is_split_child(), "must be");
5925     assert(cur->current_split_child() != NULL, "must be");
5926     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5927     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5928 
5929     insert_move(cur->from(), cur->current_split_child(), cur);
5930   }
5931   cur->make_current_split_child();
5932 
5933   return result; // true = interval is moved to active list
5934 }
5935 
5936 
5937 // Implementation of EdgeMoveOptimizer
5938 
5939 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5940   _edge_instructions(4),
5941   _edge_instructions_idx(4)
5942 {
5943 }
5944 
5945 void EdgeMoveOptimizer::optimize(BlockList* code) {
5946   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5947 
5948   // ignore the first block in the list (index 0 is not processed)
5949   for (int i = code->length() - 1; i >= 1; i--) {
5950     BlockBegin* block = code->at(i);
5951 
5952     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5953       optimizer.optimize_moves_at_block_end(block);
5954     }
5955 #ifndef RISCV
5956     if (block->number_of_sux() == 2) {
5957       optimizer.optimize_moves_at_block_begin(block);
5958     }
5959 #endif
5960   }
5961 }
5962 
5963 
5964 // clear all internal data structures
5965 void EdgeMoveOptimizer::init_instructions() {
5966   _edge_instructions.clear();
5967   _edge_instructions_idx.clear();
5968 }
5969 
5970 // append a lir-instruction-list and the index of the current operation in to the list
5971 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5972   _edge_instructions.append(instructions);
5973   _edge_instructions_idx.append(instructions_idx);
5974 }
5975 
5976 // return the current operation of the given edge (predecessor or successor)
5977 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5978   LIR_OpList* instructions = _edge_instructions.at(edge);
5979   int idx = _edge_instructions_idx.at(edge);
5980 
5981   if (idx < instructions->length()) {
5982     return instructions->at(idx);
5983   } else {
5984     return NULL;
5985   }
5986 }
5987 
5988 // removes the current operation of the given edge (predecessor or successor)
5989 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5990   LIR_OpList* instructions = _edge_instructions.at(edge);
5991   int idx = _edge_instructions_idx.at(edge);
5992   instructions->remove_at(idx);
5993 
5994   if (decrement_index) {
5995     _edge_instructions_idx.at_put(edge, idx - 1);
5996   }
5997 }
5998 
5999 
6000 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
6001   if (op1 == NULL || op2 == NULL) {
6002     // at least one block is already empty -> no optimization possible
6003     return true;
6004   }
6005 
6006   if (op1->code() == lir_move && op2->code() == lir_move) {
6007     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
6008     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
6009     LIR_Op1* move1 = (LIR_Op1*)op1;
6010     LIR_Op1* move2 = (LIR_Op1*)op2;
6011     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
6012       // these moves are exactly equal and can be optimized
6013       return false;
6014     }
6015 
6016   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
6017     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
6018     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
6019     LIR_Op1* fxch1 = (LIR_Op1*)op1;
6020     LIR_Op1* fxch2 = (LIR_Op1*)op2;
6021     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
6022       // equal FPU stack operations can be optimized
6023       return false;
6024     }
6025 
6026   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
6027     // equal FPU stack operations can be optimized
6028     return false;
6029   }
6030 
6031   // no optimization possible
6032   return true;
6033 }
6034 
6035 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
6036   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
6037 
6038   if (block->is_predecessor(block)) {
6039     // currently we can't handle this correctly.
6040     return;
6041   }
6042 
6043   init_instructions();
6044   int num_preds = block->number_of_preds();
6045   assert(num_preds > 1, "do not call otherwise");
6046   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6047 
6048   // setup a list with the lir-instructions of all predecessors
6049   int i;
6050   for (i = 0; i < num_preds; i++) {
6051     BlockBegin* pred = block->pred_at(i);
6052     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6053 
6054     if (pred->number_of_sux() != 1) {
6055       // this can happen with switch-statements where multiple edges are between
6056       // the same blocks.
6057       return;
6058     }
6059 
6060     assert(pred->number_of_sux() == 1, "can handle only one successor");
6061     assert(pred->sux_at(0) == block, "invalid control flow");
6062     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6063     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6064     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6065 
6066     if (pred_instructions->last()->info() != NULL) {
6067       // can not optimize instructions when debug info is needed
6068       return;
6069     }
6070 
6071     // ignore the unconditional branch at the end of the block
6072     append_instructions(pred_instructions, pred_instructions->length() - 2);
6073   }
6074 
6075 
6076   // process lir-instructions while all predecessors end with the same instruction
6077   while (true) {
6078     LIR_Op* op = instruction_at(0);
6079     for (i = 1; i < num_preds; i++) {
6080       if (operations_different(op, instruction_at(i))) {
6081         // these instructions are different and cannot be optimized ->
6082         // no further optimization possible
6083         return;
6084       }
6085     }
6086 
6087     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
6088 
6089     // insert the instruction at the beginning of the current block
6090     block->lir()->insert_before(1, op);
6091 
6092     // delete the instruction at the end of all predecessors
6093     for (i = 0; i < num_preds; i++) {
6094       remove_cur_instruction(i, true);
6095     }
6096   }
6097 }
6098 
6099 
6100 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6101   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6102 
6103   init_instructions();
6104   int num_sux = block->number_of_sux();
6105 
6106   LIR_OpList* cur_instructions = block->lir()->instructions_list();
6107 
6108   assert(num_sux == 2, "method should not be called otherwise");
6109   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6110   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6111   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6112 
6113   if (cur_instructions->last()->info() != NULL) {
6114     // can no optimize instructions when debug info is needed
6115     return;
6116   }
6117 
6118   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6119   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6120     // not a valid case for optimization
6121     // currently, only blocks that end with two branches (conditional branch followed
6122     // by unconditional branch) are optimized
6123     return;
6124   }
6125 
6126   // now it is guaranteed that the block ends with two branch instructions.
6127   // the instructions are inserted at the end of the block before these two branches
6128   int insert_idx = cur_instructions->length() - 2;
6129 
6130   int i;
6131 #ifdef ASSERT
6132   for (i = insert_idx - 1; i >= 0; i--) {
6133     LIR_Op* op = cur_instructions->at(i);
6134     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6135       assert(false, "block with two successors can have only two branch instructions");
6136     }
6137   }
6138 #endif
6139 
6140   // setup a list with the lir-instructions of all successors
6141   for (i = 0; i < num_sux; i++) {
6142     BlockBegin* sux = block->sux_at(i);
6143     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6144 
6145     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6146 
6147     if (sux->number_of_preds() != 1) {
6148       // this can happen with switch-statements where multiple edges are between
6149       // the same blocks.
6150       return;
6151     }
6152     assert(sux->pred_at(0) == block, "invalid control flow");
6153     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6154 
6155     // ignore the label at the beginning of the block
6156     append_instructions(sux_instructions, 1);
6157   }
6158 
6159   // process lir-instructions while all successors begin with the same instruction
6160   while (true) {
6161     LIR_Op* op = instruction_at(0);
6162     for (i = 1; i < num_sux; i++) {
6163       if (operations_different(op, instruction_at(i))) {
6164         // these instructions are different and cannot be optimized ->
6165         // no further optimization possible
6166         return;
6167       }
6168     }
6169 
6170     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6171 
6172     // insert instruction at end of current block
6173     block->lir()->insert_before(insert_idx, op);
6174     insert_idx++;
6175 
6176     // delete the instructions at the beginning of all successors
6177     for (i = 0; i < num_sux; i++) {
6178       remove_cur_instruction(i, false);
6179     }
6180   }
6181 }
6182 
6183 
6184 // Implementation of ControlFlowOptimizer
6185 
6186 ControlFlowOptimizer::ControlFlowOptimizer() :
6187   _original_preds(4)
6188 {
6189 }
6190 
6191 void ControlFlowOptimizer::optimize(BlockList* code) {
6192   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6193 
6194   // push the OSR entry block to the end so that we're not jumping over it.
6195   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6196   if (osr_entry) {
6197     int index = osr_entry->linear_scan_number();
6198     assert(code->at(index) == osr_entry, "wrong index");
6199     code->remove_at(index);
6200     code->append(osr_entry);
6201   }
6202 
6203   optimizer.reorder_short_loops(code);
6204   optimizer.delete_empty_blocks(code);
6205 #ifndef RISCV
6206   optimizer.delete_unnecessary_jumps(code);
6207 #endif
6208   optimizer.delete_jumps_to_return(code);
6209 }
6210 
6211 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6212   int i = header_idx + 1;
6213   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6214   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6215     i++;
6216   }
6217 
6218   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6219     int end_idx = i - 1;
6220     BlockBegin* end_block = code->at(end_idx);
6221 
6222     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6223       // short loop from header_idx to end_idx found -> reorder blocks such that
6224       // the header_block is the last block instead of the first block of the loop
6225       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6226                                          end_idx - header_idx + 1,
6227                                          header_block->block_id(), end_block->block_id()));
6228 
6229       for (int j = header_idx; j < end_idx; j++) {
6230         code->at_put(j, code->at(j + 1));
6231       }
6232       code->at_put(end_idx, header_block);
6233 
6234       // correct the flags so that any loop alignment occurs in the right place.
6235       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6236       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6237       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6238     }
6239   }
6240 }
6241 
6242 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6243   for (int i = code->length() - 1; i >= 0; i--) {
6244     BlockBegin* block = code->at(i);
6245 
6246     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6247       reorder_short_loop(code, block, i);
6248     }
6249   }
6250 
6251   DEBUG_ONLY(verify(code));
6252 }
6253 
6254 // only blocks with exactly one successor can be deleted. Such blocks
6255 // must always end with an unconditional branch to this successor
6256 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6257   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6258     return false;
6259   }
6260 
6261   LIR_OpList* instructions = block->lir()->instructions_list();
6262 
6263   assert(instructions->length() >= 2, "block must have label and branch");
6264   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6265   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6266   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6267   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6268 
6269   // block must have exactly one successor
6270 
6271   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6272     return true;
6273   }
6274   return false;
6275 }
6276 
6277 // substitute branch targets in all branch-instructions of this blocks
6278 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6279   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6280 
6281   LIR_OpList* instructions = block->lir()->instructions_list();
6282 
6283   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6284   for (int i = instructions->length() - 1; i >= 1; i--) {
6285     LIR_Op* op = instructions->at(i);
6286 
6287     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6288       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6289       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6290 
6291       if (branch->block() == target_from) {
6292         branch->change_block(target_to);
6293       }
6294       if (branch->ublock() == target_from) {
6295         branch->change_ublock(target_to);
6296       }
6297     }
6298   }
6299 }
6300 
6301 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6302   int old_pos = 0;
6303   int new_pos = 0;
6304   int num_blocks = code->length();
6305 
6306   while (old_pos < num_blocks) {
6307     BlockBegin* block = code->at(old_pos);
6308 
6309     if (can_delete_block(block)) {
6310       BlockBegin* new_target = block->sux_at(0);
6311 
6312       // propagate backward branch target flag for correct code alignment
6313       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6314         new_target->set(BlockBegin::backward_branch_target_flag);
6315       }
6316 
6317       // collect a list with all predecessors that contains each predecessor only once
6318       // the predecessors of cur are changed during the substitution, so a copy of the
6319       // predecessor list is necessary
6320       int j;
6321       _original_preds.clear();
6322       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6323         BlockBegin* pred = block->pred_at(j);
6324         if (_original_preds.find(pred) == -1) {
6325           _original_preds.append(pred);
6326         }
6327       }
6328 
6329       for (j = _original_preds.length() - 1; j >= 0; j--) {
6330         BlockBegin* pred = _original_preds.at(j);
6331         substitute_branch_target(pred, block, new_target);
6332         pred->substitute_sux(block, new_target);
6333       }
6334     } else {
6335       // adjust position of this block in the block list if blocks before
6336       // have been deleted
6337       if (new_pos != old_pos) {
6338         code->at_put(new_pos, code->at(old_pos));
6339       }
6340       new_pos++;
6341     }
6342     old_pos++;
6343   }
6344   code->trunc_to(new_pos);
6345 
6346   DEBUG_ONLY(verify(code));
6347 }
6348 
6349 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6350   // skip the last block because there a branch is always necessary
6351   for (int i = code->length() - 2; i >= 0; i--) {
6352     BlockBegin* block = code->at(i);
6353     LIR_OpList* instructions = block->lir()->instructions_list();
6354 
6355     LIR_Op* last_op = instructions->last();
6356     if (last_op->code() == lir_branch) {
6357       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6358       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6359 
6360       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6361       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6362 
6363       if (last_branch->info() == NULL) {
6364         if (last_branch->block() == code->at(i + 1)) {
6365 
6366           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6367 
6368           // delete last branch instruction
6369           instructions->trunc_to(instructions->length() - 1);
6370 
6371         } else {
6372           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6373           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6374             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6375             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6376 
6377             if (prev_branch->stub() == NULL) {
6378 
6379               LIR_Op2* prev_cmp = NULL;
6380               // There might be a cmove inserted for profiling which depends on the same
6381               // compare. If we change the condition of the respective compare, we have
6382               // to take care of this cmove as well.
6383               LIR_Op2* prev_cmove = NULL;
6384 
6385               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6386                 prev_op = instructions->at(j);
6387                 // check for the cmove
6388                 if (prev_op->code() == lir_cmove) {
6389                   assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6390                   prev_cmove = (LIR_Op2*)prev_op;
6391                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6392                 }
6393                 if (prev_op->code() == lir_cmp) {
6394                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6395                   prev_cmp = (LIR_Op2*)prev_op;
6396                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6397                 }
6398               }
6399               // Guarantee because it is dereferenced below.
6400               guarantee(prev_cmp != NULL, "should have found comp instruction for branch");
6401               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6402 
6403                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6404 
6405                 // eliminate a conditional branch to the immediate successor
6406                 prev_branch->change_block(last_branch->block());
6407                 prev_branch->negate_cond();
6408                 prev_cmp->set_condition(prev_branch->cond());
6409                 instructions->trunc_to(instructions->length() - 1);
6410                 // if we do change the condition, we have to change the cmove as well
6411                 if (prev_cmove != NULL) {
6412                   prev_cmove->set_condition(prev_branch->cond());
6413                   LIR_Opr t = prev_cmove->in_opr1();
6414                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6415                   prev_cmove->set_in_opr2(t);
6416                 }
6417               }
6418             }
6419           }
6420         }
6421       }
6422     }
6423   }
6424 
6425   DEBUG_ONLY(verify(code));
6426 }
6427 
6428 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6429 #ifdef ASSERT
6430   ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6431 #endif
6432 
6433   for (int i = code->length() - 1; i >= 0; i--) {
6434     BlockBegin* block = code->at(i);
6435     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6436     LIR_Op*     cur_last_op = cur_instructions->last();
6437 
6438     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6439     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6440       // the block contains only a label and a return
6441       // if a predecessor ends with an unconditional jump to this block, then the jump
6442       // can be replaced with a return instruction
6443       //
6444       // Note: the original block with only a return statement cannot be deleted completely
6445       //       because the predecessors might have other (conditional) jumps to this block
6446       //       -> this may lead to unnecesary return instructions in the final code
6447 
6448       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6449       assert(block->number_of_sux() == 0 ||
6450              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6451              "blocks that end with return must not have successors");
6452 
6453       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6454       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6455 
6456       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6457         BlockBegin* pred = block->pred_at(j);
6458         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6459         LIR_Op*     pred_last_op = pred_instructions->last();
6460 
6461         if (pred_last_op->code() == lir_branch) {
6462           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6463           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6464 
6465           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6466             // replace the jump to a return with a direct return
6467             // Note: currently the edge between the blocks is not deleted
6468             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_OpReturn(return_opr));
6469 #ifdef ASSERT
6470             return_converted.set_bit(pred->block_id());
6471 #endif
6472           }
6473         }
6474       }
6475     }
6476   }
6477 }
6478 
6479 
6480 #ifdef ASSERT
6481 void ControlFlowOptimizer::verify(BlockList* code) {
6482   for (int i = 0; i < code->length(); i++) {
6483     BlockBegin* block = code->at(i);
6484     LIR_OpList* instructions = block->lir()->instructions_list();
6485 
6486     int j;
6487     for (j = 0; j < instructions->length(); j++) {
6488       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6489 
6490       if (op_branch != NULL) {
6491         assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6492         assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6493       }
6494     }
6495 
6496     for (j = 0; j < block->number_of_sux() - 1; j++) {
6497       BlockBegin* sux = block->sux_at(j);
6498       assert(code->find(sux) != -1, "successor not valid");
6499     }
6500 
6501     for (j = 0; j < block->number_of_preds() - 1; j++) {
6502       BlockBegin* pred = block->pred_at(j);
6503       assert(code->find(pred) != -1, "successor not valid");
6504     }
6505   }
6506 }
6507 #endif
6508 
6509 
6510 #ifndef PRODUCT
6511 
6512 // Implementation of LinearStatistic
6513 
6514 const char* LinearScanStatistic::counter_name(int counter_idx) {
6515   switch (counter_idx) {
6516     case counter_method:          return "compiled methods";
6517     case counter_fpu_method:      return "methods using fpu";
6518     case counter_loop_method:     return "methods with loops";
6519     case counter_exception_method:return "methods with xhandler";
6520 
6521     case counter_loop:            return "loops";
6522     case counter_block:           return "blocks";
6523     case counter_loop_block:      return "blocks inside loop";
6524     case counter_exception_block: return "exception handler entries";
6525     case counter_interval:        return "intervals";
6526     case counter_fixed_interval:  return "fixed intervals";
6527     case counter_range:           return "ranges";
6528     case counter_fixed_range:     return "fixed ranges";
6529     case counter_use_pos:         return "use positions";
6530     case counter_fixed_use_pos:   return "fixed use positions";
6531     case counter_spill_slots:     return "spill slots";
6532 
6533     // counter for classes of lir instructions
6534     case counter_instruction:     return "total instructions";
6535     case counter_label:           return "labels";
6536     case counter_entry:           return "method entries";
6537     case counter_return:          return "method returns";
6538     case counter_call:            return "method calls";
6539     case counter_move:            return "moves";
6540     case counter_cmp:             return "compare";
6541     case counter_cond_branch:     return "conditional branches";
6542     case counter_uncond_branch:   return "unconditional branches";
6543     case counter_stub_branch:     return "branches to stub";
6544     case counter_alu:             return "artithmetic + logic";
6545     case counter_alloc:           return "allocations";
6546     case counter_sync:            return "synchronisation";
6547     case counter_throw:           return "throw";
6548     case counter_unwind:          return "unwind";
6549     case counter_typecheck:       return "type+null-checks";
6550     case counter_fpu_stack:       return "fpu-stack";
6551     case counter_misc_inst:       return "other instructions";
6552     case counter_other_inst:      return "misc. instructions";
6553 
6554     // counter for different types of moves
6555     case counter_move_total:      return "total moves";
6556     case counter_move_reg_reg:    return "register->register";
6557     case counter_move_reg_stack:  return "register->stack";
6558     case counter_move_stack_reg:  return "stack->register";
6559     case counter_move_stack_stack:return "stack->stack";
6560     case counter_move_reg_mem:    return "register->memory";
6561     case counter_move_mem_reg:    return "memory->register";
6562     case counter_move_const_any:  return "constant->any";
6563 
6564     case blank_line_1:            return "";
6565     case blank_line_2:            return "";
6566 
6567     default: ShouldNotReachHere(); return "";
6568   }
6569 }
6570 
6571 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6572   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6573     return counter_method;
6574   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6575     return counter_block;
6576   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6577     return counter_instruction;
6578   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6579     return counter_move_total;
6580   }
6581   return invalid_counter;
6582 }
6583 
6584 LinearScanStatistic::LinearScanStatistic() {
6585   for (int i = 0; i < number_of_counters; i++) {
6586     _counters_sum[i] = 0;
6587     _counters_max[i] = -1;
6588   }
6589 
6590 }
6591 
6592 // add the method-local numbers to the total sum
6593 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6594   for (int i = 0; i < number_of_counters; i++) {
6595     _counters_sum[i] += method_statistic._counters_sum[i];
6596     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6597   }
6598 }
6599 
6600 void LinearScanStatistic::print(const char* title) {
6601   if (CountLinearScan || TraceLinearScanLevel > 0) {
6602     tty->cr();
6603     tty->print_cr("***** LinearScan statistic - %s *****", title);
6604 
6605     for (int i = 0; i < number_of_counters; i++) {
6606       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6607         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6608 
6609         LinearScanStatistic::Counter cntr = base_counter(i);
6610         if (cntr != invalid_counter) {
6611           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6612         } else {
6613           tty->print("           ");
6614         }
6615 
6616         if (_counters_max[i] >= 0) {
6617           tty->print("%8d", _counters_max[i]);
6618         }
6619       }
6620       tty->cr();
6621     }
6622   }
6623 }
6624 
6625 void LinearScanStatistic::collect(LinearScan* allocator) {
6626   inc_counter(counter_method);
6627   if (allocator->has_fpu_registers()) {
6628     inc_counter(counter_fpu_method);
6629   }
6630   if (allocator->num_loops() > 0) {
6631     inc_counter(counter_loop_method);
6632   }
6633   inc_counter(counter_loop, allocator->num_loops());
6634   inc_counter(counter_spill_slots, allocator->max_spills());
6635 
6636   int i;
6637   for (i = 0; i < allocator->interval_count(); i++) {
6638     Interval* cur = allocator->interval_at(i);
6639 
6640     if (cur != NULL) {
6641       inc_counter(counter_interval);
6642       inc_counter(counter_use_pos, cur->num_use_positions());
6643       if (LinearScan::is_precolored_interval(cur)) {
6644         inc_counter(counter_fixed_interval);
6645         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6646       }
6647 
6648       Range* range = cur->first();
6649       while (range != Range::end()) {
6650         inc_counter(counter_range);
6651         if (LinearScan::is_precolored_interval(cur)) {
6652           inc_counter(counter_fixed_range);
6653         }
6654         range = range->next();
6655       }
6656     }
6657   }
6658 
6659   bool has_xhandlers = false;
6660   // Note: only count blocks that are in code-emit order
6661   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6662     BlockBegin* cur = allocator->ir()->code()->at(i);
6663 
6664     inc_counter(counter_block);
6665     if (cur->loop_depth() > 0) {
6666       inc_counter(counter_loop_block);
6667     }
6668     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6669       inc_counter(counter_exception_block);
6670       has_xhandlers = true;
6671     }
6672 
6673     LIR_OpList* instructions = cur->lir()->instructions_list();
6674     for (int j = 0; j < instructions->length(); j++) {
6675       LIR_Op* op = instructions->at(j);
6676 
6677       inc_counter(counter_instruction);
6678 
6679       switch (op->code()) {
6680         case lir_label:           inc_counter(counter_label); break;
6681         case lir_std_entry:
6682         case lir_osr_entry:       inc_counter(counter_entry); break;
6683         case lir_return:          inc_counter(counter_return); break;
6684 
6685         case lir_rtcall:
6686         case lir_static_call:
6687         case lir_optvirtual_call: inc_counter(counter_call); break;
6688 
6689         case lir_move: {
6690           inc_counter(counter_move);
6691           inc_counter(counter_move_total);
6692 
6693           LIR_Opr in = op->as_Op1()->in_opr();
6694           LIR_Opr res = op->as_Op1()->result_opr();
6695           if (in->is_register()) {
6696             if (res->is_register()) {
6697               inc_counter(counter_move_reg_reg);
6698             } else if (res->is_stack()) {
6699               inc_counter(counter_move_reg_stack);
6700             } else if (res->is_address()) {
6701               inc_counter(counter_move_reg_mem);
6702             } else {
6703               ShouldNotReachHere();
6704             }
6705           } else if (in->is_stack()) {
6706             if (res->is_register()) {
6707               inc_counter(counter_move_stack_reg);
6708             } else {
6709               inc_counter(counter_move_stack_stack);
6710             }
6711           } else if (in->is_address()) {
6712             assert(res->is_register(), "must be");
6713             inc_counter(counter_move_mem_reg);
6714           } else if (in->is_constant()) {
6715             inc_counter(counter_move_const_any);
6716           } else {
6717             ShouldNotReachHere();
6718           }
6719           break;
6720         }
6721 
6722 #ifndef RISCV
6723         case lir_cmp:             inc_counter(counter_cmp); break;
6724 #endif
6725 
6726         case lir_branch:
6727         case lir_cond_float_branch: {
6728           LIR_OpBranch* branch = op->as_OpBranch();
6729           if (branch->block() == NULL) {
6730             inc_counter(counter_stub_branch);
6731           } else if (branch->cond() == lir_cond_always) {
6732             inc_counter(counter_uncond_branch);
6733           } else {
6734             inc_counter(counter_cond_branch);
6735           }
6736           break;
6737         }
6738 
6739         case lir_neg:
6740         case lir_add:
6741         case lir_sub:
6742         case lir_mul:
6743         case lir_div:
6744         case lir_rem:
6745         case lir_sqrt:
6746         case lir_abs:
6747         case lir_log10:
6748         case lir_logic_and:
6749         case lir_logic_or:
6750         case lir_logic_xor:
6751         case lir_shl:
6752         case lir_shr:
6753         case lir_ushr:            inc_counter(counter_alu); break;
6754 
6755         case lir_alloc_object:
6756         case lir_alloc_array:     inc_counter(counter_alloc); break;
6757 
6758         case lir_monaddr:
6759         case lir_lock:
6760         case lir_unlock:          inc_counter(counter_sync); break;
6761 
6762         case lir_throw:           inc_counter(counter_throw); break;
6763 
6764         case lir_unwind:          inc_counter(counter_unwind); break;
6765 
6766         case lir_null_check:
6767         case lir_leal:
6768         case lir_instanceof:
6769         case lir_checkcast:
6770         case lir_store_check:     inc_counter(counter_typecheck); break;
6771 
6772         case lir_fpop_raw:
6773         case lir_fxch:
6774         case lir_fld:             inc_counter(counter_fpu_stack); break;
6775 
6776         case lir_nop:
6777         case lir_push:
6778         case lir_pop:
6779         case lir_convert:
6780         case lir_roundfp:
6781         case lir_cmove:           inc_counter(counter_misc_inst); break;
6782 
6783         default:                  inc_counter(counter_other_inst); break;
6784       }
6785     }
6786   }
6787 
6788   if (has_xhandlers) {
6789     inc_counter(counter_exception_method);
6790   }
6791 }
6792 
6793 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6794   if (CountLinearScan || TraceLinearScanLevel > 0) {
6795 
6796     LinearScanStatistic local_statistic = LinearScanStatistic();
6797 
6798     local_statistic.collect(allocator);
6799     global_statistic.sum_up(local_statistic);
6800 
6801     if (TraceLinearScanLevel > 2) {
6802       local_statistic.print("current local statistic");
6803     }
6804   }
6805 }
6806 
6807 
6808 // Implementation of LinearTimers
6809 
6810 LinearScanTimers::LinearScanTimers() {
6811   for (int i = 0; i < number_of_timers; i++) {
6812     timer(i)->reset();
6813   }
6814 }
6815 
6816 const char* LinearScanTimers::timer_name(int idx) {
6817   switch (idx) {
6818     case timer_do_nothing:               return "Nothing (Time Check)";
6819     case timer_number_instructions:      return "Number Instructions";
6820     case timer_compute_local_live_sets:  return "Local Live Sets";
6821     case timer_compute_global_live_sets: return "Global Live Sets";
6822     case timer_build_intervals:          return "Build Intervals";
6823     case timer_sort_intervals_before:    return "Sort Intervals Before";
6824     case timer_allocate_registers:       return "Allocate Registers";
6825     case timer_resolve_data_flow:        return "Resolve Data Flow";
6826     case timer_sort_intervals_after:     return "Sort Intervals After";
6827     case timer_eliminate_spill_moves:    return "Spill optimization";
6828     case timer_assign_reg_num:           return "Assign Reg Num";
6829     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6830     case timer_optimize_lir:             return "Optimize LIR";
6831     default: ShouldNotReachHere();       return "";
6832   }
6833 }
6834 
6835 void LinearScanTimers::begin_method() {
6836   if (TimeEachLinearScan) {
6837     // reset all timers to measure only current method
6838     for (int i = 0; i < number_of_timers; i++) {
6839       timer(i)->reset();
6840     }
6841   }
6842 }
6843 
6844 void LinearScanTimers::end_method(LinearScan* allocator) {
6845   if (TimeEachLinearScan) {
6846 
6847     double c = timer(timer_do_nothing)->seconds();
6848     double total = 0;
6849     for (int i = 1; i < number_of_timers; i++) {
6850       total += timer(i)->seconds() - c;
6851     }
6852 
6853     if (total >= 0.0005) {
6854       // print all information in one line for automatic processing
6855       tty->print("@"); allocator->compilation()->method()->print_name();
6856 
6857       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6858       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6859       tty->print("@ %d ", allocator->block_count());
6860       tty->print("@ %d ", allocator->num_virtual_regs());
6861       tty->print("@ %d ", allocator->interval_count());
6862       tty->print("@ %d ", allocator->_num_calls);
6863       tty->print("@ %d ", allocator->num_loops());
6864 
6865       tty->print("@ %6.6f ", total);
6866       for (int i = 1; i < number_of_timers; i++) {
6867         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6868       }
6869       tty->cr();
6870     }
6871   }
6872 }
6873 
6874 void LinearScanTimers::print(double total_time) {
6875   if (TimeLinearScan) {
6876     // correction value: sum of dummy-timer that only measures the time that
6877     // is necesary to start and stop itself
6878     double c = timer(timer_do_nothing)->seconds();
6879 
6880     for (int i = 0; i < number_of_timers; i++) {
6881       double t = timer(i)->seconds();
6882       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6883     }
6884   }
6885 }
6886 
6887 #endif // #ifndef PRODUCT