1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.hpp"
27 #include "code/codeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "gc/shared/collectedHeap.hpp"
30 #include "nativeInst_aarch64.hpp"
31 #include "oops/oop.inline.hpp"
32 #include "runtime/atomicAccess.hpp"
33 #include "runtime/handles.hpp"
34 #include "runtime/orderAccess.hpp"
35 #include "runtime/sharedRuntime.hpp"
36 #include "runtime/stubRoutines.hpp"
37 #include "utilities/ostream.hpp"
38 #ifdef COMPILER1
39 #include "c1/c1_Runtime1.hpp"
40 #endif
41
42 void NativeCall::verify() {
43 assert(NativeCall::is_call_at((address)this), "unexpected code at call site");
44 }
45
46 void NativeInstruction::wrote(int offset) {
47 ICache::invalidate_word(addr_at(offset));
48 }
49
50 address NativeCall::destination() const {
51 address addr = instruction_address();
52 address destination = addr + displacement();
53
54 // Performance optimization: no need to call find_blob() if it is a self-call
55 if (destination == addr) {
56 return destination;
57 }
58
59 // Do we use a trampoline stub for this call?
60 CodeBlob* cb = CodeCache::find_blob(addr);
61 assert(cb != nullptr && cb->is_nmethod(), "nmethod expected");
62 nmethod *nm = cb->as_nmethod();
63 if (nm->stub_contains(destination) && is_NativeCallTrampolineStub_at(destination)) {
64 // Yes we do, so get the destination from the trampoline stub.
65 const address trampoline_stub_addr = destination;
66 destination = nativeCallTrampolineStub_at(trampoline_stub_addr)->destination();
67 }
68
69 return destination;
70 }
71
72 // Similar to replace_mt_safe, but just changes the destination. The
73 // important thing is that free-running threads are able to execute this
74 // call instruction at all times.
75 //
76 // Used in the runtime linkage of calls; see class CompiledIC.
77 void NativeCall::set_destination_mt_safe(address dest) {
78 assert((CodeCache_lock->is_locked() || SafepointSynchronize::is_at_safepoint()) ||
79 CompiledICLocker::is_safe(addr_at(0)),
80 "concurrent code patching");
81
82 address addr_call = addr_at(0);
83 bool reachable = Assembler::reachable_from_branch_at(addr_call, dest);
84 assert(NativeCall::is_call_at(addr_call), "unexpected code at call site");
85
86 // Patch the constant in the call's trampoline stub.
87 address trampoline_stub_addr = get_trampoline();
88 if (trampoline_stub_addr != nullptr) {
89 assert (! is_NativeCallTrampolineStub_at(dest), "chained trampolines");
90 nativeCallTrampolineStub_at(trampoline_stub_addr)->set_destination(dest);
91 }
92
93 // Patch the call.
94 if (reachable) {
95 set_destination(dest);
96 } else {
97 assert (trampoline_stub_addr != nullptr, "we need a trampoline");
98 set_destination(trampoline_stub_addr);
99 }
100
101 ICache::invalidate_range(addr_call, instruction_size);
102 }
103
104 address NativeCall::get_trampoline() {
105 address call_addr = instruction_address();
106
107 CodeBlob *code = CodeCache::find_blob(call_addr);
108 assert(code != nullptr && code->is_nmethod(), "nmethod expected");
109 nmethod* nm = code->as_nmethod();
110
111 address bl_destination = call_addr + displacement();
112 if (nm->stub_contains(bl_destination) &&
113 is_NativeCallTrampolineStub_at(bl_destination))
114 return bl_destination;
115
116 return trampoline_stub_Relocation::get_trampoline_for(call_addr, nm);
117 }
118
119 // Inserts a native call instruction at a given pc
120 void NativeCall::insert(address code_pos, address entry) { Unimplemented(); }
121
122 //-------------------------------------------------------------------
123
124 void NativeMovConstReg::verify() {
125 if (! (nativeInstruction_at(instruction_address())->is_movz() ||
126 is_adrp_at(instruction_address()) ||
127 is_load_literal_at(instruction_address())) ) {
128 fatal("should be MOVZ or ADRP or LDR (literal)");
129 }
130 }
131
132
133 intptr_t NativeMovConstReg::data() const {
134 address addr = MacroAssembler::target_addr_for_insn(instruction_address());
135 if (maybe_cpool_ref(instruction_address())) {
136 return *(intptr_t*)addr;
137 } else {
138 return (intptr_t)addr;
139 }
140 }
141
142 void NativeMovConstReg::set_data(intptr_t x) {
143 if (maybe_cpool_ref(instruction_address())) {
144 MACOS_AARCH64_ONLY(os::thread_wx_enable_write());
145 address addr = MacroAssembler::target_addr_for_insn(instruction_address());
146 *(intptr_t*)addr = x;
147 } else {
148 // Store x into the instruction stream.
149 MacroAssembler::pd_patch_instruction(instruction_address(), (address)x);
150 ICache::invalidate_range(instruction_address(), instruction_size);
151 }
152
153 // Find and replace the oop/metadata corresponding to this
154 // instruction in oops section.
155 CodeBlob* cb = CodeCache::find_blob(instruction_address());
156 nmethod* nm = cb->as_nmethod_or_null();
157 if (nm != nullptr) {
158 RelocIterator iter(nm, instruction_address(), next_instruction_address());
159 while (iter.next()) {
160 if (iter.type() == relocInfo::oop_type) {
161 oop* oop_addr = iter.oop_reloc()->oop_addr();
162 *oop_addr = cast_to_oop(x);
163 break;
164 } else if (iter.type() == relocInfo::metadata_type) {
165 Metadata** metadata_addr = iter.metadata_reloc()->metadata_addr();
166 *metadata_addr = (Metadata*)x;
167 break;
168 }
169 }
170 }
171 }
172
173 void NativeMovConstReg::print() {
174 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
175 p2i(instruction_address()), data());
176 }
177
178 //-------------------------------------------------------------------
179
180 int NativeMovRegMem::offset() const {
181 address pc = instruction_address();
182 unsigned insn = *(unsigned*)pc;
183 if (Instruction_aarch64::extract(insn, 28, 24) == 0b10000) {
184 address addr = MacroAssembler::target_addr_for_insn(pc);
185 return *addr;
186 } else {
187 return (int)(intptr_t)MacroAssembler::target_addr_for_insn(instruction_address());
188 }
189 }
190
191 void NativeMovRegMem::set_offset(int x) {
192 address pc = instruction_address();
193 if (maybe_cpool_ref(pc)) {
194 address addr = MacroAssembler::target_addr_for_insn(pc);
195 *(int64_t*)addr = x;
196 } else {
197 MacroAssembler::pd_patch_instruction(pc, (address)intptr_t(x));
198 ICache::invalidate_range(instruction_address(), instruction_size);
199 }
200 }
201
202 void NativeMovRegMem::verify() {
203 #ifdef ASSERT
204 MacroAssembler::target_addr_for_insn(instruction_address());
205 #endif
206 }
207
208 //--------------------------------------------------------------------------------
209
210 void NativeJump::verify() { ; }
211
212 address NativeJump::jump_destination() const {
213 address dest = MacroAssembler::target_addr_for_insn(instruction_address());
214
215 // We use jump to self as the unresolved address which the inline
216 // cache code (and relocs) know about
217 // As a special case we also use sequence movptr(r,0); br(r);
218 // i.e. jump to 0 when we need leave space for a wide immediate
219 // load
220
221 // return -1 if jump to self or to 0
222 if ((dest == (address)this) || dest == nullptr) {
223 dest = (address) -1;
224 }
225 return dest;
226 }
227
228 void NativeJump::set_jump_destination(address dest) {
229 // We use jump to self as the unresolved address which the inline
230 // cache code (and relocs) know about
231 if (dest == (address) -1)
232 dest = instruction_address();
233
234 MacroAssembler::pd_patch_instruction(instruction_address(), dest);
235 ICache::invalidate_range(instruction_address(), instruction_size);
236 };
237
238 //-------------------------------------------------------------------
239
240 address NativeGeneralJump::jump_destination() const {
241 NativeMovConstReg* move = nativeMovConstReg_at(instruction_address());
242 address dest = (address) move->data();
243
244 // We use jump to self as the unresolved address which the inline
245 // cache code (and relocs) know about
246 // As a special case we also use jump to 0 when first generating
247 // a general jump
248
249 // return -1 if jump to self or to 0
250 if ((dest == (address)this) || dest == nullptr) {
251 dest = (address) -1;
252 }
253 return dest;
254 }
255
256 void NativeGeneralJump::set_jump_destination(address dest) {
257 NativeMovConstReg* move = nativeMovConstReg_at(instruction_address());
258
259 // We use jump to self as the unresolved address which the inline
260 // cache code (and relocs) know about
261 if (dest == (address) -1) {
262 dest = instruction_address();
263 }
264
265 move->set_data((uintptr_t) dest);
266 };
267
268 //-------------------------------------------------------------------
269
270 bool NativeInstruction::is_safepoint_poll() {
271 // a safepoint_poll is implemented in two steps as either
272 //
273 // adrp(reg, polling_page);
274 // ldrw(zr, [reg, #offset]);
275 //
276 // or
277 //
278 // mov(reg, polling_page);
279 // ldrw(zr, [reg, #offset]);
280 //
281 // or
282 //
283 // ldr(reg, [rthread, #offset]);
284 // ldrw(zr, [reg, #offset]);
285 //
286 // however, we cannot rely on the polling page address load always
287 // directly preceding the read from the page. C1 does that but C2
288 // has to do the load and read as two independent instruction
289 // generation steps. that's because with a single macro sequence the
290 // generic C2 code can only add the oop map before the mov/adrp and
291 // the trap handler expects an oop map to be associated with the
292 // load. with the load scheuled as a prior step the oop map goes
293 // where it is needed.
294 //
295 // so all we can do here is check that marked instruction is a load
296 // word to zr
297 return is_ldrw_to_zr(address(this));
298 }
299
300 bool NativeInstruction::is_adrp_at(address instr) {
301 unsigned insn = *(unsigned*)instr;
302 return (Instruction_aarch64::extract(insn, 31, 24) & 0b10011111) == 0b10010000;
303 }
304
305 bool NativeInstruction::is_load_literal_at(address instr) {
306 unsigned insn = *(unsigned*)instr;
307 return (Instruction_aarch64::extract(insn, 29, 24) & 0b011011) == 0b00011000;
308 }
309
310 bool NativeInstruction::is_ldr_gpr_literal_at(address instr) {
311 unsigned insn = *(unsigned*)instr;
312 return Instruction_aarch64::extract(insn, 31, 24) == 0b01011000;
313 }
314
315 bool NativeInstruction::is_ldrw_gpr_literal_at(address instr) {
316 unsigned insn = *(unsigned*)instr;
317 return Instruction_aarch64::extract(insn, 31, 24) == 0b00011000;
318 }
319
320 bool NativeInstruction::is_ldrw_to_zr(address instr) {
321 unsigned insn = *(unsigned*)instr;
322 return (Instruction_aarch64::extract(insn, 31, 22) == 0b1011100101 &&
323 Instruction_aarch64::extract(insn, 4, 0) == 0b11111);
324 }
325
326 bool NativeInstruction::is_general_jump() {
327 if (is_movz()) {
328 NativeInstruction* inst1 = nativeInstruction_at(addr_at(instruction_size * 1));
329 if (inst1->is_movk()) {
330 NativeInstruction* inst2 = nativeInstruction_at(addr_at(instruction_size * 2));
331 if (inst2->is_movk()) {
332 NativeInstruction* inst3 = nativeInstruction_at(addr_at(instruction_size * 3));
333 if (inst3->is_blr()) {
334 return true;
335 }
336 }
337 }
338 }
339 return false;
340 }
341
342 bool NativeInstruction::is_movz() {
343 return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b10100101;
344 }
345
346 bool NativeInstruction::is_movk() {
347 return Instruction_aarch64::extract(int_at(0), 30, 23) == 0b11100101;
348 }
349
350 void NativeIllegalInstruction::insert(address code_pos) {
351 *(juint*)code_pos = 0xd4bbd5a1; // dcps1 #0xdead
352 }
353
354 bool NativeInstruction::is_stop() {
355 return uint_at(0) == 0xd4bbd5c1; // dcps1 #0xdeae
356 }
357
358 //-------------------------------------------------------------------
359
360 // MT-safe patching of a long jump instruction.
361 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
362 ShouldNotCallThis();
363 }
364
365 address NativeCallTrampolineStub::destination(nmethod *nm) const {
366 return ptr_at(data_offset);
367 }
368
369 void NativeCallTrampolineStub::set_destination(address new_destination) {
370 set_ptr_at(data_offset, new_destination);
371 OrderAccess::release();
372 }
373
374 void NativePostCallNop::make_deopt() {
375 NativeDeoptInstruction::insert(addr_at(0));
376 }
377
378 bool NativePostCallNop::patch(int32_t oopmap_slot, int32_t cb_offset) {
379 if (((oopmap_slot & 0xff) != oopmap_slot) || ((cb_offset & 0xffffff) != cb_offset)) {
380 return false; // cannot encode
381 }
382 uint32_t data = ((uint32_t)oopmap_slot << 24) | cb_offset;
383 #ifdef ASSERT
384 assert(data != 0, "must be");
385 uint32_t insn1 = uint_at(4);
386 uint32_t insn2 = uint_at(8);
387 assert (is_movk_to_zr(insn1) && is_movk_to_zr(insn2), "must be");
388 #endif
389
390 uint32_t lo = data & 0xffff;
391 uint32_t hi = data >> 16;
392 Instruction_aarch64::patch(addr_at(4), 20, 5, lo);
393 Instruction_aarch64::patch(addr_at(8), 20, 5, hi);
394 return true; // successfully encoded
395 }
396
397 void NativeDeoptInstruction::verify() {
398 }
399
400 // Inserts an undefined instruction at a given pc
401 void NativeDeoptInstruction::insert(address code_pos) {
402 // 1 1 0 1 | 0 1 0 0 | 1 0 1 imm16 0 0 0 0 1
403 // d | 4 | a | de | 0 | 0 |
404 // 0xd4, 0x20, 0x00, 0x00
405 uint32_t insn = 0xd4ade001;
406 uint32_t *pos = (uint32_t *) code_pos;
407 *pos = insn;
408 /**code_pos = 0xd4;
409 *(code_pos+1) = 0x60;
410 *(code_pos+2) = 0x00;
411 *(code_pos+3) = 0x00;*/
412 ICache::invalidate_range(code_pos, 4);
413 }