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src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

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  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/barrierSet.hpp"
  39 #include "gc/shared/cardTableBarrierSet.hpp"
  40 #include "gc/shared/collectedHeap.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/sharedRuntime.hpp"

  45 #include "vmreg_aarch64.inline.hpp"
  46 
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,


2801   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2802 
2803   if (left->is_single_cpu()) {
2804     assert(dest->is_single_cpu(), "expect single result reg");
2805     __ negw(dest->as_register(), left->as_register());
2806   } else if (left->is_double_cpu()) {
2807     assert(dest->is_double_cpu(), "expect double result reg");
2808     __ neg(dest->as_register_lo(), left->as_register_lo());
2809   } else if (left->is_single_fpu()) {
2810     assert(dest->is_single_fpu(), "expect single float result reg");
2811     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2812   } else {
2813     assert(left->is_double_fpu(), "expect double float operand reg");
2814     assert(dest->is_double_fpu(), "expect double float result reg");
2815     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2816   }
2817 }
2818 
2819 
2820 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {






2821   assert(patch_code == lir_patch_none, "Patch code not supported");
2822   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2823 }
2824 
2825 
2826 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2827   assert(!tmp->is_valid(), "don't need temporary");
2828 
2829   CodeBlob *cb = CodeCache::find_blob(dest);
2830   if (cb) {
2831     __ far_call(RuntimeAddress(dest));
2832   } else {
2833     __ mov(rscratch1, RuntimeAddress(dest));
2834     __ blr(rscratch1);
2835   }
2836 
2837   if (info != NULL) {
2838     add_call_info_here(info);
2839   }
2840   __ maybe_isb();




  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/barrierSet.hpp"
  39 #include "gc/shared/cardTableBarrierSet.hpp"
  40 #include "gc/shared/collectedHeap.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/sharedRuntime.hpp"
  45 #include "utilities/macros.hpp"
  46 #include "vmreg_aarch64.inline.hpp"
  47 
  48 
  49 
  50 #ifndef PRODUCT
  51 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  52 #else
  53 #define COMMENT(x)
  54 #endif
  55 
  56 NEEDS_CLEANUP // remove this definitions ?
  57 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  58 const Register SYNC_header = r0;   // synchronization header
  59 const Register SHIFT_count = r0;   // where count for shift operations must be
  60 
  61 #define __ _masm->
  62 
  63 
  64 static void select_different_registers(Register preserve,
  65                                        Register extra,


2802   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2803 
2804   if (left->is_single_cpu()) {
2805     assert(dest->is_single_cpu(), "expect single result reg");
2806     __ negw(dest->as_register(), left->as_register());
2807   } else if (left->is_double_cpu()) {
2808     assert(dest->is_double_cpu(), "expect double result reg");
2809     __ neg(dest->as_register_lo(), left->as_register_lo());
2810   } else if (left->is_single_fpu()) {
2811     assert(dest->is_single_fpu(), "expect single float result reg");
2812     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2813   } else {
2814     assert(left->is_double_fpu(), "expect double float operand reg");
2815     assert(dest->is_double_fpu(), "expect double float result reg");
2816     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2817   }
2818 }
2819 
2820 
2821 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2822 #if INCLUDE_SHENANDOAHGC
2823   if (UseShenandoahGC && patch_code != lir_patch_none) {
2824     deoptimize_trap(info);
2825     return;
2826   }
2827 #endif
2828   assert(patch_code == lir_patch_none, "Patch code not supported");
2829   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2830 }
2831 
2832 
2833 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2834   assert(!tmp->is_valid(), "don't need temporary");
2835 
2836   CodeBlob *cb = CodeCache::find_blob(dest);
2837   if (cb) {
2838     __ far_call(RuntimeAddress(dest));
2839   } else {
2840     __ mov(rscratch1, RuntimeAddress(dest));
2841     __ blr(rscratch1);
2842   }
2843 
2844   if (info != NULL) {
2845     add_call_info_here(info);
2846   }
2847   __ maybe_isb();


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