1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2018, Red Hat, Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 
  31 // MacroAssembler extends Assembler by frequently used macros.
  32 //
  33 // Instructions for which a 'better' code sequence exists depending
  34 // on arguments should also go in here.
  35 
  36 class MacroAssembler: public Assembler {
  37   friend class LIR_Assembler;
  38 
  39  public:
  40   using Assembler::mov;
  41   using Assembler::movi;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50   virtual void call_VM_leaf_base(
  51     address entry_point,               // the entry point
  52     int     number_of_arguments,        // the number of arguments to pop after the call
  53     Label *retaddr = NULL
  54   );
  55 
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label &retaddr) {
  60     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  61   }
  62 
  63   // This is the base routine called by the different versions of call_VM. The interpreter
  64   // may customize this version by overriding it for its purposes (e.g., to save/restore
  65   // additional registers when doing a VM call).
  66   //
  67   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  68   // returns the register which contains the thread upon return. If a thread register has been
  69   // specified, the return value will correspond to that register. If no last_java_sp is specified
  70   // (noreg) than rsp will be used instead.
  71   virtual void call_VM_base(           // returns the register containing the thread upon return
  72     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  73     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  74     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  75     address  entry_point,              // the entry point
  76     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  77     bool     check_exceptions          // whether to check for pending exceptions after return
  78   );
  79 
  80   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  81 
  82   // True if an XOR can be used to expand narrow klass references.
  83   bool use_XOR_for_compressed_class_base;
  84 
  85  public:
  86   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  87     use_XOR_for_compressed_class_base
  88       = (operand_valid_for_logical_immediate(false /*is32*/,
  89                                              (uint64_t)Universe::narrow_klass_base())
  90          && ((uint64_t)Universe::narrow_klass_base()
  91              > (1UL << log2_intptr(Universe::narrow_klass_range()))));
  92   }
  93 
  94  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  95  // The implementation is only non-empty for the InterpreterMacroAssembler,
  96  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  97  virtual void check_and_handle_popframe(Register java_thread);
  98  virtual void check_and_handle_earlyret(Register java_thread);
  99 
 100   void safepoint_poll(Label& slow_path);
 101   void safepoint_poll_acquire(Label& slow_path);
 102 
 103   // Biased locking support
 104   // lock_reg and obj_reg must be loaded up with the appropriate values.
 105   // swap_reg is killed.
 106   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 107   // Optional slow case is for implementations (interpreter and C1) which branch to
 108   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 109   // Returns offset of first potentially-faulting instruction for null
 110   // check info (currently consumed only by C1). If
 111   // swap_reg_contains_mark is true then returns -1 as it is assumed
 112   // the calling code has already passed any potential faults.
 113   int biased_locking_enter(Register lock_reg, Register obj_reg,
 114                            Register swap_reg, Register tmp_reg,
 115                            bool swap_reg_contains_mark,
 116                            Label& done, Label* slow_case = NULL,
 117                            BiasedLockingCounters* counters = NULL);
 118   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 119 
 120 
 121   // Helper functions for statistics gathering.
 122   // Unconditional atomic increment.
 123   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 124   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 125     lea(tmp1, counter_addr);
 126     atomic_incw(tmp1, tmp2, tmp3);
 127   }
 128   // Load Effective Address
 129   void lea(Register r, const Address &a) {
 130     InstructionMark im(this);
 131     code_section()->relocate(inst_mark(), a.rspec());
 132     a.lea(this, r);
 133   }
 134 
 135   void addmw(Address a, Register incr, Register scratch) {
 136     ldrw(scratch, a);
 137     addw(scratch, scratch, incr);
 138     strw(scratch, a);
 139   }
 140 
 141   // Add constant to memory word
 142   void addmw(Address a, int imm, Register scratch) {
 143     ldrw(scratch, a);
 144     if (imm > 0)
 145       addw(scratch, scratch, (unsigned)imm);
 146     else
 147       subw(scratch, scratch, (unsigned)-imm);
 148     strw(scratch, a);
 149   }
 150 
 151   void bind(Label& L) {
 152     Assembler::bind(L);
 153     code()->clear_last_insn();
 154   }
 155 
 156   void membar(Membar_mask_bits order_constraint);
 157 
 158   using Assembler::ldr;
 159   using Assembler::str;
 160 
 161   void ldr(Register Rx, const Address &adr);
 162   void ldrw(Register Rw, const Address &adr);
 163   void str(Register Rx, const Address &adr);
 164   void strw(Register Rx, const Address &adr);
 165 
 166   // Frame creation and destruction shared between JITs.
 167   void build_frame(int framesize);
 168   void remove_frame(int framesize);
 169 
 170   virtual void _call_Unimplemented(address call_site) {
 171     mov(rscratch2, call_site);
 172     haltsim();
 173   }
 174 
 175 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 176 
 177   virtual void notify(int type);
 178 
 179   // aliases defined in AARCH64 spec
 180 
 181   template<class T>
 182   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 183   // imm is limited to 12 bits.
 184   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 185 
 186   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 187   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 188 
 189   void cset(Register Rd, Assembler::Condition cond) {
 190     csinc(Rd, zr, zr, ~cond);
 191   }
 192   void csetw(Register Rd, Assembler::Condition cond) {
 193     csincw(Rd, zr, zr, ~cond);
 194   }
 195 
 196   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 197     csneg(Rd, Rn, Rn, ~cond);
 198   }
 199   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 200     csnegw(Rd, Rn, Rn, ~cond);
 201   }
 202 
 203   inline void movw(Register Rd, Register Rn) {
 204     if (Rd == sp || Rn == sp) {
 205       addw(Rd, Rn, 0U);
 206     } else {
 207       orrw(Rd, zr, Rn);
 208     }
 209   }
 210   inline void mov(Register Rd, Register Rn) {
 211     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 212     if (Rd == Rn) {
 213     } else if (Rd == sp || Rn == sp) {
 214       add(Rd, Rn, 0U);
 215     } else {
 216       orr(Rd, zr, Rn);
 217     }
 218   }
 219 
 220   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 221   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 222 
 223   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 224   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 225 
 226   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 227   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 228 
 229   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 230     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 231   }
 232   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 233     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 234   }
 235 
 236   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 237     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 238   }
 239   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     bfm(Rd, Rn, lsb , (lsb + width - 1));
 241   }
 242 
 243   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 244     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 245   }
 246   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 248   }
 249 
 250   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 251     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 252   }
 253   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 255   }
 256 
 257   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 258     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 259   }
 260   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 261     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 262   }
 263 
 264   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 265     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 266   }
 267   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 268     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 269   }
 270 
 271   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 272     sbfmw(Rd, Rn, imm, 31);
 273   }
 274 
 275   inline void asr(Register Rd, Register Rn, unsigned imm) {
 276     sbfm(Rd, Rn, imm, 63);
 277   }
 278 
 279   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 280     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 281   }
 282 
 283   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 284     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 285   }
 286 
 287   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 288     ubfmw(Rd, Rn, imm, 31);
 289   }
 290 
 291   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 292     ubfm(Rd, Rn, imm, 63);
 293   }
 294 
 295   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 296     extrw(Rd, Rn, Rn, imm);
 297   }
 298 
 299   inline void ror(Register Rd, Register Rn, unsigned imm) {
 300     extr(Rd, Rn, Rn, imm);
 301   }
 302 
 303   inline void sxtbw(Register Rd, Register Rn) {
 304     sbfmw(Rd, Rn, 0, 7);
 305   }
 306   inline void sxthw(Register Rd, Register Rn) {
 307     sbfmw(Rd, Rn, 0, 15);
 308   }
 309   inline void sxtb(Register Rd, Register Rn) {
 310     sbfm(Rd, Rn, 0, 7);
 311   }
 312   inline void sxth(Register Rd, Register Rn) {
 313     sbfm(Rd, Rn, 0, 15);
 314   }
 315   inline void sxtw(Register Rd, Register Rn) {
 316     sbfm(Rd, Rn, 0, 31);
 317   }
 318 
 319   inline void uxtbw(Register Rd, Register Rn) {
 320     ubfmw(Rd, Rn, 0, 7);
 321   }
 322   inline void uxthw(Register Rd, Register Rn) {
 323     ubfmw(Rd, Rn, 0, 15);
 324   }
 325   inline void uxtb(Register Rd, Register Rn) {
 326     ubfm(Rd, Rn, 0, 7);
 327   }
 328   inline void uxth(Register Rd, Register Rn) {
 329     ubfm(Rd, Rn, 0, 15);
 330   }
 331   inline void uxtw(Register Rd, Register Rn) {
 332     ubfm(Rd, Rn, 0, 31);
 333   }
 334 
 335   inline void cmnw(Register Rn, Register Rm) {
 336     addsw(zr, Rn, Rm);
 337   }
 338   inline void cmn(Register Rn, Register Rm) {
 339     adds(zr, Rn, Rm);
 340   }
 341 
 342   inline void cmpw(Register Rn, Register Rm) {
 343     subsw(zr, Rn, Rm);
 344   }
 345   inline void cmp(Register Rn, Register Rm) {
 346     subs(zr, Rn, Rm);
 347   }
 348 
 349   inline void negw(Register Rd, Register Rn) {
 350     subw(Rd, zr, Rn);
 351   }
 352 
 353   inline void neg(Register Rd, Register Rn) {
 354     sub(Rd, zr, Rn);
 355   }
 356 
 357   inline void negsw(Register Rd, Register Rn) {
 358     subsw(Rd, zr, Rn);
 359   }
 360 
 361   inline void negs(Register Rd, Register Rn) {
 362     subs(Rd, zr, Rn);
 363   }
 364 
 365   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 366     addsw(zr, Rn, Rm, kind, shift);
 367   }
 368   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 369     adds(zr, Rn, Rm, kind, shift);
 370   }
 371 
 372   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 373     subsw(zr, Rn, Rm, kind, shift);
 374   }
 375   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 376     subs(zr, Rn, Rm, kind, shift);
 377   }
 378 
 379   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 380     subw(Rd, zr, Rn, kind, shift);
 381   }
 382 
 383   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 384     sub(Rd, zr, Rn, kind, shift);
 385   }
 386 
 387   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 388     subsw(Rd, zr, Rn, kind, shift);
 389   }
 390 
 391   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 392     subs(Rd, zr, Rn, kind, shift);
 393   }
 394 
 395   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 396     msubw(Rd, Rn, Rm, zr);
 397   }
 398   inline void mneg(Register Rd, Register Rn, Register Rm) {
 399     msub(Rd, Rn, Rm, zr);
 400   }
 401 
 402   inline void mulw(Register Rd, Register Rn, Register Rm) {
 403     maddw(Rd, Rn, Rm, zr);
 404   }
 405   inline void mul(Register Rd, Register Rn, Register Rm) {
 406     madd(Rd, Rn, Rm, zr);
 407   }
 408 
 409   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 410     smsubl(Rd, Rn, Rm, zr);
 411   }
 412   inline void smull(Register Rd, Register Rn, Register Rm) {
 413     smaddl(Rd, Rn, Rm, zr);
 414   }
 415 
 416   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 417     umsubl(Rd, Rn, Rm, zr);
 418   }
 419   inline void umull(Register Rd, Register Rn, Register Rm) {
 420     umaddl(Rd, Rn, Rm, zr);
 421   }
 422 
 423 #define WRAP(INSN)                                                            \
 424   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 425     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 426       nop();                                                                  \
 427     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 428   }
 429 
 430   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 431   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 432 #undef WRAP
 433 
 434 
 435   // macro assembly operations needed for aarch64
 436 
 437   // first two private routines for loading 32 bit or 64 bit constants
 438 private:
 439 
 440   void mov_immediate64(Register dst, u_int64_t imm64);
 441   void mov_immediate32(Register dst, u_int32_t imm32);
 442 
 443   int push(unsigned int bitset, Register stack);
 444   int pop(unsigned int bitset, Register stack);
 445 
 446   void mov(Register dst, Address a);
 447 
 448 public:
 449   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 450   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 451 
 452   // Push and pop everything that might be clobbered by a native
 453   // runtime call except rscratch1 and rscratch2.  (They are always
 454   // scratch, so we don't have to protect them.)  Only save the lower
 455   // 64 bits of each vector register.
 456   void push_call_clobbered_registers();
 457   void pop_call_clobbered_registers();
 458   void push_call_clobbered_fp_registers();
 459   void pop_call_clobbered_fp_registers();
 460 
 461   // now mov instructions for loading absolute addresses and 32 or
 462   // 64 bit integers
 463 
 464   inline void mov(Register dst, address addr)
 465   {
 466     mov_immediate64(dst, (u_int64_t)addr);
 467   }
 468 
 469   inline void mov(Register dst, u_int64_t imm64)
 470   {
 471     mov_immediate64(dst, imm64);
 472   }
 473 
 474   inline void movw(Register dst, u_int32_t imm32)
 475   {
 476     mov_immediate32(dst, imm32);
 477   }
 478 
 479   inline void mov(Register dst, long l)
 480   {
 481     mov(dst, (u_int64_t)l);
 482   }
 483 
 484   inline void mov(Register dst, int i)
 485   {
 486     mov(dst, (long)i);
 487   }
 488 
 489   void mov(Register dst, RegisterOrConstant src) {
 490     if (src.is_register())
 491       mov(dst, src.as_register());
 492     else
 493       mov(dst, src.as_constant());
 494   }
 495 
 496   void movptr(Register r, uintptr_t imm64);
 497 
 498   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 499 
 500   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 501     orr(Vd, T, Vn, Vn);
 502   }
 503 
 504 public:
 505 
 506   // Generalized Test Bit And Branch, including a "far" variety which
 507   // spans more than 32KiB.
 508   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 509     assert(cond == EQ || cond == NE, "must be");
 510 
 511     if (far)
 512       cond = ~cond;
 513 
 514     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 515     if (cond == Assembler::EQ)
 516       branch = &Assembler::tbz;
 517     else
 518       branch = &Assembler::tbnz;
 519 
 520     if (far) {
 521       Label L;
 522       (this->*branch)(Rt, bitpos, L);
 523       b(dest);
 524       bind(L);
 525     } else {
 526       (this->*branch)(Rt, bitpos, dest);
 527     }
 528   }
 529 
 530   // macro instructions for accessing and updating floating point
 531   // status register
 532   //
 533   // FPSR : op1 == 011
 534   //        CRn == 0100
 535   //        CRm == 0100
 536   //        op2 == 001
 537 
 538   inline void get_fpsr(Register reg)
 539   {
 540     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 541   }
 542 
 543   inline void set_fpsr(Register reg)
 544   {
 545     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 546   }
 547 
 548   inline void clear_fpsr()
 549   {
 550     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 551   }
 552 
 553   // DCZID_EL0: op1 == 011
 554   //            CRn == 0000
 555   //            CRm == 0000
 556   //            op2 == 111
 557   inline void get_dczid_el0(Register reg)
 558   {
 559     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 560   }
 561 
 562   // CTR_EL0:   op1 == 011
 563   //            CRn == 0000
 564   //            CRm == 0000
 565   //            op2 == 001
 566   inline void get_ctr_el0(Register reg)
 567   {
 568     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 569   }
 570 
 571   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 572   int corrected_idivl(Register result, Register ra, Register rb,
 573                       bool want_remainder, Register tmp = rscratch1);
 574   int corrected_idivq(Register result, Register ra, Register rb,
 575                       bool want_remainder, Register tmp = rscratch1);
 576 
 577   // Support for NULL-checks
 578   //
 579   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 580   // If the accessed location is M[reg + offset] and the offset is known, provide the
 581   // offset. No explicit code generation is needed if the offset is within a certain
 582   // range (0 <= offset <= page_size).
 583 
 584   virtual void null_check(Register reg, int offset = -1);
 585   static bool needs_explicit_null_check(intptr_t offset);
 586 
 587   static address target_addr_for_insn(address insn_addr, unsigned insn);
 588   static address target_addr_for_insn(address insn_addr) {
 589     unsigned insn = *(unsigned*)insn_addr;
 590     return target_addr_for_insn(insn_addr, insn);
 591   }
 592 
 593   // Required platform-specific helpers for Label::patch_instructions.
 594   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 595   static int pd_patch_instruction_size(address branch, address target);
 596   static void pd_patch_instruction(address branch, address target) {
 597     pd_patch_instruction_size(branch, target);
 598   }
 599   static address pd_call_destination(address branch) {
 600     return target_addr_for_insn(branch);
 601   }
 602 #ifndef PRODUCT
 603   static void pd_print_patched_instruction(address branch);
 604 #endif
 605 
 606   static int patch_oop(address insn_addr, address o);
 607   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 608 
 609   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 610 
 611   // The following 4 methods return the offset of the appropriate move instruction
 612 
 613   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 614   int load_unsigned_byte(Register dst, Address src);
 615   int load_unsigned_short(Register dst, Address src);
 616 
 617   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 618   int load_signed_byte(Register dst, Address src);
 619   int load_signed_short(Register dst, Address src);
 620 
 621   int load_signed_byte32(Register dst, Address src);
 622   int load_signed_short32(Register dst, Address src);
 623 
 624   // Support for sign-extension (hi:lo = extend_sign(lo))
 625   void extend_sign(Register hi, Register lo);
 626 
 627   // Load and store values by size and signed-ness
 628   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 629   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 630 
 631   // Support for inc/dec with optimal instruction selection depending on value
 632 
 633   // x86_64 aliases an unqualified register/address increment and
 634   // decrement to call incrementq and decrementq but also supports
 635   // explicitly sized calls to incrementq/decrementq or
 636   // incrementl/decrementl
 637 
 638   // for aarch64 the proper convention would be to use
 639   // increment/decrement for 64 bit operatons and
 640   // incrementw/decrementw for 32 bit operations. so when porting
 641   // x86_64 code we can leave calls to increment/decrement as is,
 642   // replace incrementq/decrementq with increment/decrement and
 643   // replace incrementl/decrementl with incrementw/decrementw.
 644 
 645   // n.b. increment/decrement calls with an Address destination will
 646   // need to use a scratch register to load the value to be
 647   // incremented. increment/decrement calls which add or subtract a
 648   // constant value greater than 2^12 will need to use a 2nd scratch
 649   // register to hold the constant. so, a register increment/decrement
 650   // may trash rscratch2 and an address increment/decrement trash
 651   // rscratch and rscratch2
 652 
 653   void decrementw(Address dst, int value = 1);
 654   void decrementw(Register reg, int value = 1);
 655 
 656   void decrement(Register reg, int value = 1);
 657   void decrement(Address dst, int value = 1);
 658 
 659   void incrementw(Address dst, int value = 1);
 660   void incrementw(Register reg, int value = 1);
 661 
 662   void increment(Register reg, int value = 1);
 663   void increment(Address dst, int value = 1);
 664 
 665 
 666   // Alignment
 667   void align(int modulus);
 668 
 669   // Stack frame creation/removal
 670   void enter()
 671   {
 672     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 673     mov(rfp, sp);
 674   }
 675   void leave()
 676   {
 677     mov(sp, rfp);
 678     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 679   }
 680 
 681   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 682   // The pointer will be loaded into the thread register.
 683   void get_thread(Register thread);
 684 
 685 
 686   // Support for VM calls
 687   //
 688   // It is imperative that all calls into the VM are handled via the call_VM macros.
 689   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 690   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 691 
 692 
 693   void call_VM(Register oop_result,
 694                address entry_point,
 695                bool check_exceptions = true);
 696   void call_VM(Register oop_result,
 697                address entry_point,
 698                Register arg_1,
 699                bool check_exceptions = true);
 700   void call_VM(Register oop_result,
 701                address entry_point,
 702                Register arg_1, Register arg_2,
 703                bool check_exceptions = true);
 704   void call_VM(Register oop_result,
 705                address entry_point,
 706                Register arg_1, Register arg_2, Register arg_3,
 707                bool check_exceptions = true);
 708 
 709   // Overloadings with last_Java_sp
 710   void call_VM(Register oop_result,
 711                Register last_java_sp,
 712                address entry_point,
 713                int number_of_arguments = 0,
 714                bool check_exceptions = true);
 715   void call_VM(Register oop_result,
 716                Register last_java_sp,
 717                address entry_point,
 718                Register arg_1, bool
 719                check_exceptions = true);
 720   void call_VM(Register oop_result,
 721                Register last_java_sp,
 722                address entry_point,
 723                Register arg_1, Register arg_2,
 724                bool check_exceptions = true);
 725   void call_VM(Register oop_result,
 726                Register last_java_sp,
 727                address entry_point,
 728                Register arg_1, Register arg_2, Register arg_3,
 729                bool check_exceptions = true);
 730 
 731   void get_vm_result  (Register oop_result, Register thread);
 732   void get_vm_result_2(Register metadata_result, Register thread);
 733 
 734   // These always tightly bind to MacroAssembler::call_VM_base
 735   // bypassing the virtual implementation
 736   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 737   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 738   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 739   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 740   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 741 
 742   void call_VM_leaf(address entry_point,
 743                     int number_of_arguments = 0);
 744   void call_VM_leaf(address entry_point,
 745                     Register arg_1);
 746   void call_VM_leaf(address entry_point,
 747                     Register arg_1, Register arg_2);
 748   void call_VM_leaf(address entry_point,
 749                     Register arg_1, Register arg_2, Register arg_3);
 750 
 751   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 752   // bypassing the virtual implementation
 753   void super_call_VM_leaf(address entry_point);
 754   void super_call_VM_leaf(address entry_point, Register arg_1);
 755   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 756   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 757   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 758 
 759   // last Java Frame (fills frame anchor)
 760   void set_last_Java_frame(Register last_java_sp,
 761                            Register last_java_fp,
 762                            address last_java_pc,
 763                            Register scratch);
 764 
 765   void set_last_Java_frame(Register last_java_sp,
 766                            Register last_java_fp,
 767                            Label &last_java_pc,
 768                            Register scratch);
 769 
 770   void set_last_Java_frame(Register last_java_sp,
 771                            Register last_java_fp,
 772                            Register last_java_pc,
 773                            Register scratch);
 774 
 775   void reset_last_Java_frame(Register thread);
 776 
 777   // thread in the default location (rthread)
 778   void reset_last_Java_frame(bool clear_fp);
 779 
 780   // Stores
 781   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 782   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 783 
 784   void resolve_jobject(Register value, Register thread, Register tmp);
 785 
 786   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 787   void c2bool(Register x);
 788 
 789   // oop manipulations
 790   void load_klass(Register dst, Register src);
 791   void store_klass(Register dst, Register src);
 792   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 793 
 794   void resolve_oop_handle(Register result, Register tmp = r5);
 795   void load_mirror(Register dst, Register method, Register tmp = r5);
 796 
 797   void resolve_for_read(DecoratorSet decorators, Register obj);
 798   void resolve_for_write(DecoratorSet decorators, Register obj);
 799 
 800   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 801                       Register tmp1, Register tmp_thread);
 802 
 803   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 804                        Register tmp1, Register tmp_thread);
 805 
 806   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 807                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 808 
 809   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 810                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 811   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 812                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 813 
 814   // currently unimplemented
 815   // Used for storing NULL. All other oop constants should be
 816   // stored using routines that take a jobject.
 817   void store_heap_oop_null(Address dst);
 818 
 819   void load_prototype_header(Register dst, Register src);
 820 
 821   void store_klass_gap(Register dst, Register src);
 822 
 823   // This dummy is to prevent a call to store_heap_oop from
 824   // converting a zero (like NULL) into a Register by giving
 825   // the compiler two choices it can't resolve
 826 
 827   void store_heap_oop(Address dst, void* dummy);
 828 
 829   void encode_heap_oop(Register d, Register s);
 830   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 831   void decode_heap_oop(Register d, Register s);
 832   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 833   void encode_heap_oop_not_null(Register r);
 834   void decode_heap_oop_not_null(Register r);
 835   void encode_heap_oop_not_null(Register dst, Register src);
 836   void decode_heap_oop_not_null(Register dst, Register src);
 837 
 838   void set_narrow_oop(Register dst, jobject obj);
 839 
 840   void encode_klass_not_null(Register r);
 841   void decode_klass_not_null(Register r);
 842   void encode_klass_not_null(Register dst, Register src);
 843   void decode_klass_not_null(Register dst, Register src);
 844 
 845   void set_narrow_klass(Register dst, Klass* k);
 846 
 847   // if heap base register is used - reinit it with the correct value
 848   void reinit_heapbase();
 849 
 850   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 851 
 852   void push_CPU_state(bool save_vectors = false);
 853   void pop_CPU_state(bool restore_vectors = false) ;
 854 
 855   // Round up to a power of two
 856   void round_to(Register reg, int modulus);
 857 
 858   // allocation
 859   void eden_allocate(
 860     Register obj,                      // result: pointer to object after successful allocation
 861     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 862     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 863     Register t1,                       // temp register
 864     Label&   slow_case                 // continuation point if fast allocation fails
 865   );
 866   void tlab_allocate(
 867     Register obj,                      // result: pointer to object after successful allocation
 868     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 869     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 870     Register t1,                       // temp register
 871     Register t2,                       // temp register
 872     Label&   slow_case                 // continuation point if fast allocation fails
 873   );
 874   void zero_memory(Register addr, Register len, Register t1);
 875   void verify_tlab();
 876 
 877   // interface method calling
 878   void lookup_interface_method(Register recv_klass,
 879                                Register intf_klass,
 880                                RegisterOrConstant itable_index,
 881                                Register method_result,
 882                                Register scan_temp,
 883                                Label& no_such_interface,
 884                    bool return_method = true);
 885 
 886   // virtual method calling
 887   // n.b. x86 allows RegisterOrConstant for vtable_index
 888   void lookup_virtual_method(Register recv_klass,
 889                              RegisterOrConstant vtable_index,
 890                              Register method_result);
 891 
 892   // Test sub_klass against super_klass, with fast and slow paths.
 893 
 894   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 895   // One of the three labels can be NULL, meaning take the fall-through.
 896   // If super_check_offset is -1, the value is loaded up from super_klass.
 897   // No registers are killed, except temp_reg.
 898   void check_klass_subtype_fast_path(Register sub_klass,
 899                                      Register super_klass,
 900                                      Register temp_reg,
 901                                      Label* L_success,
 902                                      Label* L_failure,
 903                                      Label* L_slow_path,
 904                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 905 
 906   // The rest of the type check; must be wired to a corresponding fast path.
 907   // It does not repeat the fast path logic, so don't use it standalone.
 908   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 909   // Updates the sub's secondary super cache as necessary.
 910   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 911   void check_klass_subtype_slow_path(Register sub_klass,
 912                                      Register super_klass,
 913                                      Register temp_reg,
 914                                      Register temp2_reg,
 915                                      Label* L_success,
 916                                      Label* L_failure,
 917                                      bool set_cond_codes = false);
 918 
 919   // Simplified, combined version, good for typical uses.
 920   // Falls through on failure.
 921   void check_klass_subtype(Register sub_klass,
 922                            Register super_klass,
 923                            Register temp_reg,
 924                            Label& L_success);
 925 
 926   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 927 
 928 
 929   // Debugging
 930 
 931   // only if +VerifyOops
 932   void verify_oop(Register reg, const char* s = "broken oop");
 933   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 934 
 935 // TODO: verify method and klass metadata (compare against vptr?)
 936   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 937   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 938 
 939 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 940 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 941 
 942   // only if +VerifyFPU
 943   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 944 
 945   // prints msg, dumps registers and stops execution
 946   void stop(const char* msg);
 947 
 948   // prints msg and continues
 949   void warn(const char* msg);
 950 
 951   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 952 
 953   void untested()                                { stop("untested"); }
 954 
 955   void unimplemented(const char* what = "");
 956 
 957   void should_not_reach_here()                   { stop("should not reach here"); }
 958 
 959   // Stack overflow checking
 960   void bang_stack_with_offset(int offset) {
 961     // stack grows down, caller passes positive offset
 962     assert(offset > 0, "must bang with negative offset");
 963     sub(rscratch2, sp, offset);
 964     str(zr, Address(rscratch2));
 965   }
 966 
 967   // Writes to stack successive pages until offset reached to check for
 968   // stack overflow + shadow pages.  Also, clobbers tmp
 969   void bang_stack_size(Register size, Register tmp);
 970 
 971   // Check for reserved stack access in method being exited (for JIT)
 972   void reserved_stack_check();
 973 
 974   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 975                                                 Register tmp,
 976                                                 int offset);
 977 
 978   // Support for serializing memory accesses between threads
 979   void serialize_memory(Register thread, Register tmp);
 980 
 981   // Arithmetics
 982 
 983   void addptr(const Address &dst, int32_t src);
 984   void cmpptr(Register src1, Address src2);
 985 
 986   void cmpoop(Register obj1, Register obj2);
 987 
 988   // Various forms of CAS
 989 
 990   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
 991                           Label &suceed, Label *fail);
 992   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 993                   Label &suceed, Label *fail);
 994 
 995   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 996                   Label &suceed, Label *fail);
 997 
 998   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 999   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1000   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1001   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1002 
1003   void atomic_xchg(Register prev, Register newv, Register addr);
1004   void atomic_xchgw(Register prev, Register newv, Register addr);
1005   void atomic_xchgal(Register prev, Register newv, Register addr);
1006   void atomic_xchgalw(Register prev, Register newv, Register addr);
1007 
1008   void orptr(Address adr, RegisterOrConstant src) {
1009     ldr(rscratch1, adr);
1010     if (src.is_register())
1011       orr(rscratch1, rscratch1, src.as_register());
1012     else
1013       orr(rscratch1, rscratch1, src.as_constant());
1014     str(rscratch1, adr);
1015   }
1016 
1017   // A generic CAS; success or failure is in the EQ flag.
1018   // Clobbers rscratch1
1019   void cmpxchg(Register addr, Register expected, Register new_val,
1020                enum operand_size size,
1021                bool acquire, bool release, bool weak,
1022                Register result);
1023 
1024 private:
1025   void compare_eq(Register rn, Register rm, enum operand_size size);
1026 
1027 public:
1028   // Calls
1029 
1030   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1031 
1032   static bool far_branches() {
1033     return ReservedCodeCacheSize > branch_range || UseAOT;
1034   }
1035 
1036   // Jumps that can reach anywhere in the code cache.
1037   // Trashes tmp.
1038   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1039   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1040 
1041   static int far_branch_size() {
1042     if (far_branches()) {
1043       return 3 * 4;  // adrp, add, br
1044     } else {
1045       return 4;
1046     }
1047   }
1048 
1049   // Emit the CompiledIC call idiom
1050   address ic_call(address entry, jint method_index = 0);
1051 
1052 public:
1053 
1054   // Data
1055 
1056   void mov_metadata(Register dst, Metadata* obj);
1057   Address allocate_metadata_address(Metadata* obj);
1058   Address constant_oop_address(jobject obj);
1059 
1060   void movoop(Register dst, jobject obj, bool immediate = false);
1061 
1062   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1063   void kernel_crc32(Register crc, Register buf, Register len,
1064         Register table0, Register table1, Register table2, Register table3,
1065         Register tmp, Register tmp2, Register tmp3);
1066   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1067   void kernel_crc32c(Register crc, Register buf, Register len,
1068         Register table0, Register table1, Register table2, Register table3,
1069         Register tmp, Register tmp2, Register tmp3);
1070 
1071   // Stack push and pop individual 64 bit registers
1072   void push(Register src);
1073   void pop(Register dst);
1074 
1075   // push all registers onto the stack
1076   void pusha();
1077   void popa();
1078 
1079   void repne_scan(Register addr, Register value, Register count,
1080                   Register scratch);
1081   void repne_scanw(Register addr, Register value, Register count,
1082                    Register scratch);
1083 
1084   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1085   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1086 
1087   // If a constant does not fit in an immediate field, generate some
1088   // number of MOV instructions and then perform the operation
1089   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1090                              add_sub_imm_insn insn1,
1091                              add_sub_reg_insn insn2);
1092   // Seperate vsn which sets the flags
1093   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1094                              add_sub_imm_insn insn1,
1095                              add_sub_reg_insn insn2);
1096 
1097 #define WRAP(INSN)                                                      \
1098   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1099     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1100   }                                                                     \
1101                                                                         \
1102   void INSN(Register Rd, Register Rn, Register Rm,                      \
1103              enum shift_kind kind, unsigned shift = 0) {                \
1104     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1105   }                                                                     \
1106                                                                         \
1107   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1108     Assembler::INSN(Rd, Rn, Rm);                                        \
1109   }                                                                     \
1110                                                                         \
1111   void INSN(Register Rd, Register Rn, Register Rm,                      \
1112            ext::operation option, int amount = 0) {                     \
1113     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1114   }
1115 
1116   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1117 
1118 #undef WRAP
1119 #define WRAP(INSN)                                                      \
1120   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1121     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1122   }                                                                     \
1123                                                                         \
1124   void INSN(Register Rd, Register Rn, Register Rm,                      \
1125              enum shift_kind kind, unsigned shift = 0) {                \
1126     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1127   }                                                                     \
1128                                                                         \
1129   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1130     Assembler::INSN(Rd, Rn, Rm);                                        \
1131   }                                                                     \
1132                                                                         \
1133   void INSN(Register Rd, Register Rn, Register Rm,                      \
1134            ext::operation option, int amount = 0) {                     \
1135     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1136   }
1137 
1138   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1139 
1140   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1141   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1142   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1143   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1144 
1145   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1146 
1147   void tableswitch(Register index, jint lowbound, jint highbound,
1148                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1149     adr(rscratch1, jumptable);
1150     subsw(rscratch2, index, lowbound);
1151     subsw(zr, rscratch2, highbound - lowbound);
1152     br(Assembler::HS, jumptable_end);
1153     add(rscratch1, rscratch1, rscratch2,
1154         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1155     br(rscratch1);
1156   }
1157 
1158   // Form an address from base + offset in Rd.  Rd may or may not
1159   // actually be used: you must use the Address that is returned.  It
1160   // is up to you to ensure that the shift provided matches the size
1161   // of your data.
1162   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1163 
1164   // Return true iff an address is within the 48-bit AArch64 address
1165   // space.
1166   bool is_valid_AArch64_address(address a) {
1167     return ((uint64_t)a >> 48) == 0;
1168   }
1169 
1170   // Load the base of the cardtable byte map into reg.
1171   void load_byte_map_base(Register reg);
1172 
1173   // Prolog generator routines to support switch between x86 code and
1174   // generated ARM code
1175 
1176   // routine to generate an x86 prolog for a stub function which
1177   // bootstraps into the generated ARM code which directly follows the
1178   // stub
1179   //
1180 
1181   public:
1182   // enum used for aarch64--x86 linkage to define return type of x86 function
1183   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1184 
1185 #ifdef BUILTIN_SIM
1186   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1187 #else
1188   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1189 #endif
1190 
1191   // special version of call_VM_leaf_base needed for aarch64 simulator
1192   // where we need to specify both the gp and fp arg counts and the
1193   // return type so that the linkage routine from aarch64 to x86 and
1194   // back knows which aarch64 registers to copy to x86 registers and
1195   // which x86 result register to copy back to an aarch64 register
1196 
1197   void call_VM_leaf_base1(
1198     address  entry_point,             // the entry point
1199     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1200     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1201     ret_type type,                    // the return type for the call
1202     Label*   retaddr = NULL
1203   );
1204 
1205   void ldr_constant(Register dest, const Address &const_addr) {
1206     if (NearCpool) {
1207       ldr(dest, const_addr);
1208     } else {
1209       unsigned long offset;
1210       adrp(dest, InternalAddress(const_addr.target()), offset);
1211       ldr(dest, Address(dest, offset));
1212     }
1213   }
1214 
1215   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1216   address read_polling_page(Register r, relocInfo::relocType rtype);
1217   void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1218 
1219   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1220   void update_byte_crc32(Register crc, Register val, Register table);
1221   void update_word_crc32(Register crc, Register v, Register tmp,
1222         Register table0, Register table1, Register table2, Register table3,
1223         bool upper = false);
1224 
1225   void string_compare(Register str1, Register str2,
1226                       Register cnt1, Register cnt2, Register result,
1227                       Register tmp1, Register tmp2, FloatRegister vtmp1,
1228                       FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1229 
1230   void has_negatives(Register ary1, Register len, Register result);
1231 
1232   void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1233                      Register tmp1, Register tmp2, Register tmp3, int elem_size);
1234 
1235   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1236                      int elem_size);
1237 
1238   void fill_words(Register base, Register cnt, Register value);
1239   void zero_words(Register base, u_int64_t cnt);
1240   void zero_words(Register ptr, Register cnt);
1241   void zero_dcache_blocks(Register base, Register cnt);
1242 
1243   static const int zero_words_block_size;
1244 
1245   void byte_array_inflate(Register src, Register dst, Register len,
1246                           FloatRegister vtmp1, FloatRegister vtmp2,
1247                           FloatRegister vtmp3, Register tmp4);
1248 
1249   void char_array_compress(Register src, Register dst, Register len,
1250                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1251                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1252                            Register result);
1253 
1254   void encode_iso_array(Register src, Register dst,
1255                         Register len, Register result,
1256                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1257                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1258   void string_indexof(Register str1, Register str2,
1259                       Register cnt1, Register cnt2,
1260                       Register tmp1, Register tmp2,
1261                       Register tmp3, Register tmp4,
1262                       Register tmp5, Register tmp6,
1263                       int int_cnt1, Register result, int ae);
1264   void string_indexof_char(Register str1, Register cnt1,
1265                            Register ch, Register result,
1266                            Register tmp1, Register tmp2, Register tmp3);
1267   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1268                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1269                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1270                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1271                 Register tmp3, Register tmp4, Register tmp5);
1272   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1273       address pio2, address dsin_coef, address dcos_coef);
1274  private:
1275   // begin trigonometric functions support block
1276   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1277   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1278   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1279   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1280   // end trigonometric functions support block
1281   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1282                        Register src1, Register src2);
1283   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1284     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1285   }
1286   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1287                              Register y, Register y_idx, Register z,
1288                              Register carry, Register product,
1289                              Register idx, Register kdx);
1290   void multiply_128_x_128_loop(Register y, Register z,
1291                                Register carry, Register carry2,
1292                                Register idx, Register jdx,
1293                                Register yz_idx1, Register yz_idx2,
1294                                Register tmp, Register tmp3, Register tmp4,
1295                                Register tmp7, Register product_hi);
1296   void kernel_crc32_using_crc32(Register crc, Register buf,
1297         Register len, Register tmp0, Register tmp1, Register tmp2,
1298         Register tmp3);
1299   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1300         Register len, Register tmp0, Register tmp1, Register tmp2,
1301         Register tmp3);
1302 public:
1303   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1304                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1305                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1306   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1307   // ISB may be needed because of a safepoint
1308   void maybe_isb() { isb(); }
1309 
1310 private:
1311   // Return the effective address r + (r1 << ext) + offset.
1312   // Uses rscratch2.
1313   Address offsetted_address(Register r, Register r1, Address::extend ext,
1314                             int offset, int size);
1315 
1316 private:
1317   // Returns an address on the stack which is reachable with a ldr/str of size
1318   // Uses rscratch2 if the address is not directly reachable
1319   Address spill_address(int size, int offset, Register tmp=rscratch2);
1320 
1321   bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1322 
1323   // Check whether two loads/stores can be merged into ldp/stp.
1324   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1325 
1326   // Merge current load/store with previous load/store into ldp/stp.
1327   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1328 
1329   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1330   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1331 
1332 public:
1333   void spill(Register Rx, bool is64, int offset) {
1334     if (is64) {
1335       str(Rx, spill_address(8, offset));
1336     } else {
1337       strw(Rx, spill_address(4, offset));
1338     }
1339   }
1340   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1341     str(Vx, T, spill_address(1 << (int)T, offset));
1342   }
1343   void unspill(Register Rx, bool is64, int offset) {
1344     if (is64) {
1345       ldr(Rx, spill_address(8, offset));
1346     } else {
1347       ldrw(Rx, spill_address(4, offset));
1348     }
1349   }
1350   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1351     ldr(Vx, T, spill_address(1 << (int)T, offset));
1352   }
1353   void spill_copy128(int src_offset, int dst_offset,
1354                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1355     if (src_offset < 512 && (src_offset & 7) == 0 &&
1356         dst_offset < 512 && (dst_offset & 7) == 0) {
1357       ldp(tmp1, tmp2, Address(sp, src_offset));
1358       stp(tmp1, tmp2, Address(sp, dst_offset));
1359     } else {
1360       unspill(tmp1, true, src_offset);
1361       spill(tmp1, true, dst_offset);
1362       unspill(tmp1, true, src_offset+8);
1363       spill(tmp1, true, dst_offset+8);
1364     }
1365   }
1366 };
1367 
1368 #ifdef ASSERT
1369 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1370 #endif
1371 
1372 /**
1373  * class SkipIfEqual:
1374  *
1375  * Instantiating this class will result in assembly code being output that will
1376  * jump around any code emitted between the creation of the instance and it's
1377  * automatic destruction at the end of a scope block, depending on the value of
1378  * the flag passed to the constructor, which will be checked at run-time.
1379  */
1380 class SkipIfEqual {
1381  private:
1382   MacroAssembler* _masm;
1383   Label _label;
1384 
1385  public:
1386    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1387    ~SkipIfEqual();
1388 };
1389 
1390 struct tableswitch {
1391   Register _reg;
1392   int _insn_index; jint _first_key; jint _last_key;
1393   Label _after;
1394   Label _branches;
1395 };
1396 
1397 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP