1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableBarrierSet.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "nativeInst_x86.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "vmreg_x86.inline.hpp"
  44 
  45 
  46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  47 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  48 // fast versions of NegF/NegD and AbsF/AbsD.
  49 
  50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  52   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  53   // of 128-bits operands for SSE instructions.
  54   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  55   // Store the value to a 128-bits operand.
  56   operand[0] = lo;
  57   operand[1] = hi;
  58   return operand;
  59 }
  60 
  61 // Buffer for 128-bits masks used by SSE instructions.
  62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  63 
  64 // Static initialization during VM startup.
  65 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  67 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  69 
  70 
  71 NEEDS_CLEANUP // remove this definitions ?
  72 const Register IC_Klass    = rax;   // where the IC klass is cached
  73 const Register SYNC_header = rax;   // synchronization header
  74 const Register SHIFT_count = rcx;   // where count for shift operations must be
  75 
  76 #define __ _masm->
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2) {
  83   if (tmp1 == preserve) {
  84     assert_different_registers(tmp1, tmp2, extra);
  85     tmp1 = extra;
  86   } else if (tmp2 == preserve) {
  87     assert_different_registers(tmp1, tmp2, extra);
  88     tmp2 = extra;
  89   }
  90   assert_different_registers(preserve, tmp1, tmp2);
  91 }
  92 
  93 
  94 
  95 static void select_different_registers(Register preserve,
  96                                        Register extra,
  97                                        Register &tmp1,
  98                                        Register &tmp2,
  99                                        Register &tmp3) {
 100   if (tmp1 == preserve) {
 101     assert_different_registers(tmp1, tmp2, tmp3, extra);
 102     tmp1 = extra;
 103   } else if (tmp2 == preserve) {
 104     assert_different_registers(tmp1, tmp2, tmp3, extra);
 105     tmp2 = extra;
 106   } else if (tmp3 == preserve) {
 107     assert_different_registers(tmp1, tmp2, tmp3, extra);
 108     tmp3 = extra;
 109   }
 110   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 111 }
 112 
 113 
 114 
 115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 116   if (opr->is_constant()) {
 117     LIR_Const* constant = opr->as_constant_ptr();
 118     switch (constant->type()) {
 119       case T_INT: {
 120         return true;
 121       }
 122 
 123       default:
 124         return false;
 125     }
 126   }
 127   return false;
 128 }
 129 
 130 
 131 LIR_Opr LIR_Assembler::receiverOpr() {
 132   return FrameMap::receiver_opr;
 133 }
 134 
 135 LIR_Opr LIR_Assembler::osrBufferPointer() {
 136   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 137 }
 138 
 139 //--------------fpu register translations-----------------------
 140 
 141 
 142 address LIR_Assembler::float_constant(float f) {
 143   address const_addr = __ float_constant(f);
 144   if (const_addr == NULL) {
 145     bailout("const section overflow");
 146     return __ code()->consts()->start();
 147   } else {
 148     return const_addr;
 149   }
 150 }
 151 
 152 
 153 address LIR_Assembler::double_constant(double d) {
 154   address const_addr = __ double_constant(d);
 155   if (const_addr == NULL) {
 156     bailout("const section overflow");
 157     return __ code()->consts()->start();
 158   } else {
 159     return const_addr;
 160   }
 161 }
 162 
 163 
 164 void LIR_Assembler::set_24bit_FPU() {
 165   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 166 }
 167 
 168 void LIR_Assembler::reset_FPU() {
 169   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 170 }
 171 
 172 void LIR_Assembler::fpop() {
 173   __ fpop();
 174 }
 175 
 176 void LIR_Assembler::fxch(int i) {
 177   __ fxch(i);
 178 }
 179 
 180 void LIR_Assembler::fld(int i) {
 181   __ fld_s(i);
 182 }
 183 
 184 void LIR_Assembler::ffree(int i) {
 185   __ ffree(i);
 186 }
 187 
 188 void LIR_Assembler::breakpoint() {
 189   __ int3();
 190 }
 191 
 192 void LIR_Assembler::push(LIR_Opr opr) {
 193   if (opr->is_single_cpu()) {
 194     __ push_reg(opr->as_register());
 195   } else if (opr->is_double_cpu()) {
 196     NOT_LP64(__ push_reg(opr->as_register_hi()));
 197     __ push_reg(opr->as_register_lo());
 198   } else if (opr->is_stack()) {
 199     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 200   } else if (opr->is_constant()) {
 201     LIR_Const* const_opr = opr->as_constant_ptr();
 202     if (const_opr->type() == T_OBJECT) {
 203       __ push_oop(const_opr->as_jobject());
 204     } else if (const_opr->type() == T_INT) {
 205       __ push_jint(const_opr->as_jint());
 206     } else {
 207       ShouldNotReachHere();
 208     }
 209 
 210   } else {
 211     ShouldNotReachHere();
 212   }
 213 }
 214 
 215 void LIR_Assembler::pop(LIR_Opr opr) {
 216   if (opr->is_single_cpu()) {
 217     __ pop_reg(opr->as_register());
 218   } else {
 219     ShouldNotReachHere();
 220   }
 221 }
 222 
 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 224   return addr->base()->is_illegal() && addr->index()->is_illegal();
 225 }
 226 
 227 //-------------------------------------------
 228 
 229 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 230   return as_Address(addr, rscratch1);
 231 }
 232 
 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 234   if (addr->base()->is_illegal()) {
 235     assert(addr->index()->is_illegal(), "must be illegal too");
 236     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 237     if (! __ reachable(laddr)) {
 238       __ movptr(tmp, laddr.addr());
 239       Address res(tmp, 0);
 240       return res;
 241     } else {
 242       return __ as_Address(laddr);
 243     }
 244   }
 245 
 246   Register base = addr->base()->as_pointer_register();
 247 
 248   if (addr->index()->is_illegal()) {
 249     return Address( base, addr->disp());
 250   } else if (addr->index()->is_cpu_register()) {
 251     Register index = addr->index()->as_pointer_register();
 252     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 253   } else if (addr->index()->is_constant()) {
 254     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 255     assert(Assembler::is_simm32(addr_offset), "must be");
 256 
 257     return Address(base, addr_offset);
 258   } else {
 259     Unimplemented();
 260     return Address();
 261   }
 262 }
 263 
 264 
 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 266   Address base = as_Address(addr);
 267   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 268 }
 269 
 270 
 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 272   return as_Address(addr);
 273 }
 274 
 275 
 276 void LIR_Assembler::osr_entry() {
 277   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 278   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 279   ValueStack* entry_state = osr_entry->state();
 280   int number_of_locks = entry_state->locks_size();
 281 
 282   // we jump here if osr happens with the interpreter
 283   // state set up to continue at the beginning of the
 284   // loop that triggered osr - in particular, we have
 285   // the following registers setup:
 286   //
 287   // rcx: osr buffer
 288   //
 289 
 290   // build frame
 291   ciMethod* m = compilation()->method();
 292   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 293 
 294   // OSR buffer is
 295   //
 296   // locals[nlocals-1..0]
 297   // monitors[0..number_of_locks]
 298   //
 299   // locals is a direct copy of the interpreter frame so in the osr buffer
 300   // so first slot in the local array is the last local from the interpreter
 301   // and last slot is local[0] (receiver) from the interpreter
 302   //
 303   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 304   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 305   // in the interpreter frame (the method lock if a sync method)
 306 
 307   // Initialize monitors in the compiled activation.
 308   //   rcx: pointer to osr buffer
 309   //
 310   // All other registers are dead at this point and the locals will be
 311   // copied into place by code emitted in the IR.
 312 
 313   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 314   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 315     int monitor_offset = BytesPerWord * method()->max_locals() +
 316       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 317     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 318     // the OSR buffer using 2 word entries: first the lock and then
 319     // the oop.
 320     for (int i = 0; i < number_of_locks; i++) {
 321       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 322 #ifdef ASSERT
 323       // verify the interpreter's monitor has a non-null object
 324       {
 325         Label L;
 326         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 327         __ jcc(Assembler::notZero, L);
 328         __ stop("locked object is NULL");
 329         __ bind(L);
 330       }
 331 #endif
 332       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 333       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 334       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 335       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 336     }
 337   }
 338 }
 339 
 340 
 341 // inline cache check; done before the frame is built.
 342 int LIR_Assembler::check_icache() {
 343   Register receiver = FrameMap::receiver_opr->as_register();
 344   Register ic_klass = IC_Klass;
 345   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 346   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 347   if (!do_post_padding) {
 348     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 349     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 350   }
 351   int offset = __ offset();
 352   __ inline_cache_check(receiver, IC_Klass);
 353   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 354   if (do_post_padding) {
 355     // force alignment after the cache check.
 356     // It's been verified to be aligned if !VerifyOops
 357     __ align(CodeEntryAlignment);
 358   }
 359   return offset;
 360 }
 361 
 362 
 363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 364   jobject o = NULL;
 365   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 366   __ movoop(reg, o);
 367   patching_epilog(patch, lir_patch_normal, reg, info);
 368 }
 369 
 370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 371   Metadata* o = NULL;
 372   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 373   __ mov_metadata(reg, o);
 374   patching_epilog(patch, lir_patch_normal, reg, info);
 375 }
 376 
 377 // This specifies the rsp decrement needed to build the frame
 378 int LIR_Assembler::initial_frame_size_in_bytes() const {
 379   // if rounding, must let FrameMap know!
 380 
 381   // The frame_map records size in slots (32bit word)
 382 
 383   // subtract two words to account for return address and link
 384   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 385 }
 386 
 387 
 388 int LIR_Assembler::emit_exception_handler() {
 389   // if the last instruction is a call (typically to do a throw which
 390   // is coming at the end after block reordering) the return address
 391   // must still point into the code area in order to avoid assertion
 392   // failures when searching for the corresponding bci => add a nop
 393   // (was bug 5/14/1999 - gri)
 394   __ nop();
 395 
 396   // generate code for exception handler
 397   address handler_base = __ start_a_stub(exception_handler_size());
 398   if (handler_base == NULL) {
 399     // not enough space left for the handler
 400     bailout("exception handler overflow");
 401     return -1;
 402   }
 403 
 404   int offset = code_offset();
 405 
 406   // the exception oop and pc are in rax, and rdx
 407   // no other registers need to be preserved, so invalidate them
 408   __ invalidate_registers(false, true, true, false, true, true);
 409 
 410   // check that there is really an exception
 411   __ verify_not_null_oop(rax);
 412 
 413   // search an exception handler (rax: exception oop, rdx: throwing pc)
 414   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 415   __ should_not_reach_here();
 416   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 417   __ end_a_stub();
 418 
 419   return offset;
 420 }
 421 
 422 
 423 // Emit the code to remove the frame from the stack in the exception
 424 // unwind path.
 425 int LIR_Assembler::emit_unwind_handler() {
 426 #ifndef PRODUCT
 427   if (CommentedAssembly) {
 428     _masm->block_comment("Unwind handler");
 429   }
 430 #endif
 431 
 432   int offset = code_offset();
 433 
 434   // Fetch the exception from TLS and clear out exception related thread state
 435   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 436   NOT_LP64(__ get_thread(rsi));
 437   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 438   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 439   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 440 
 441   __ bind(_unwind_handler_entry);
 442   __ verify_not_null_oop(rax);
 443   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 444     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 445   }
 446 
 447   // Preform needed unlocking
 448   MonitorExitStub* stub = NULL;
 449   if (method()->is_synchronized()) {
 450     monitor_address(0, FrameMap::rax_opr);
 451     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 452     __ unlock_object(rdi, rsi, rax, *stub->entry());
 453     __ bind(*stub->continuation());
 454   }
 455 
 456   if (compilation()->env()->dtrace_method_probes()) {
 457 #ifdef _LP64
 458     __ mov(rdi, r15_thread);
 459     __ mov_metadata(rsi, method()->constant_encoding());
 460 #else
 461     __ get_thread(rax);
 462     __ movptr(Address(rsp, 0), rax);
 463     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 464 #endif
 465     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 466   }
 467 
 468   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 469     __ mov(rax, rbx);  // Restore the exception
 470   }
 471 
 472   // remove the activation and dispatch to the unwind handler
 473   __ remove_frame(initial_frame_size_in_bytes());
 474   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 475 
 476   // Emit the slow path assembly
 477   if (stub != NULL) {
 478     stub->emit_code(this);
 479   }
 480 
 481   return offset;
 482 }
 483 
 484 
 485 int LIR_Assembler::emit_deopt_handler() {
 486   // if the last instruction is a call (typically to do a throw which
 487   // is coming at the end after block reordering) the return address
 488   // must still point into the code area in order to avoid assertion
 489   // failures when searching for the corresponding bci => add a nop
 490   // (was bug 5/14/1999 - gri)
 491   __ nop();
 492 
 493   // generate code for exception handler
 494   address handler_base = __ start_a_stub(deopt_handler_size());
 495   if (handler_base == NULL) {
 496     // not enough space left for the handler
 497     bailout("deopt handler overflow");
 498     return -1;
 499   }
 500 
 501   int offset = code_offset();
 502   InternalAddress here(__ pc());
 503 
 504   __ pushptr(here.addr());
 505   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 506   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 507   __ end_a_stub();
 508 
 509   return offset;
 510 }
 511 
 512 
 513 void LIR_Assembler::return_op(LIR_Opr result) {
 514   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 515   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 516     assert(result->fpu() == 0, "result must already be on TOS");
 517   }
 518 
 519   // Pop the stack before the safepoint code
 520   __ remove_frame(initial_frame_size_in_bytes());
 521 
 522   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 523     __ reserved_stack_check();
 524   }
 525 
 526   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 527 
 528   // Note: we do not need to round double result; float result has the right precision
 529   // the poll sets the condition code, but no data registers
 530 
 531   if (SafepointMechanism::uses_thread_local_poll()) {
 532 #ifdef _LP64
 533     const Register poll_addr = rscratch1;
 534     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 535 #else
 536     const Register poll_addr = rbx;
 537     assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
 538     __ get_thread(poll_addr);
 539     __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
 540 #endif
 541     __ relocate(relocInfo::poll_return_type);
 542     __ testl(rax, Address(poll_addr, 0));
 543   } else {
 544     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
 545 
 546     if (Assembler::is_polling_page_far()) {
 547       __ lea(rscratch1, polling_page);
 548       __ relocate(relocInfo::poll_return_type);
 549       __ testl(rax, Address(rscratch1, 0));
 550     } else {
 551       __ testl(rax, polling_page);
 552     }
 553   }
 554   __ ret(0);
 555 }
 556 
 557 
 558 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 559   guarantee(info != NULL, "Shouldn't be NULL");
 560   int offset = __ offset();
 561   if (SafepointMechanism::uses_thread_local_poll()) {
 562 #ifdef _LP64
 563     const Register poll_addr = rscratch1;
 564     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 565 #else
 566     assert(tmp->is_cpu_register(), "needed");
 567     const Register poll_addr = tmp->as_register();
 568     __ get_thread(poll_addr);
 569     __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
 570 #endif
 571     add_debug_info_for_branch(info);
 572     __ relocate(relocInfo::poll_type);
 573     address pre_pc = __ pc();
 574     __ testl(rax, Address(poll_addr, 0));
 575     address post_pc = __ pc();
 576     guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 577   } else {
 578     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
 579     if (Assembler::is_polling_page_far()) {
 580       __ lea(rscratch1, polling_page);
 581       offset = __ offset();
 582       add_debug_info_for_branch(info);
 583       __ relocate(relocInfo::poll_type);
 584       __ testl(rax, Address(rscratch1, 0));
 585     } else {
 586       add_debug_info_for_branch(info);
 587       __ testl(rax, polling_page);
 588     }
 589   }
 590   return offset;
 591 }
 592 
 593 
 594 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 595   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 596 }
 597 
 598 void LIR_Assembler::swap_reg(Register a, Register b) {
 599   __ xchgptr(a, b);
 600 }
 601 
 602 
 603 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 604   assert(src->is_constant(), "should not call otherwise");
 605   assert(dest->is_register(), "should not call otherwise");
 606   LIR_Const* c = src->as_constant_ptr();
 607 
 608   switch (c->type()) {
 609     case T_INT: {
 610       assert(patch_code == lir_patch_none, "no patching handled here");
 611       __ movl(dest->as_register(), c->as_jint());
 612       break;
 613     }
 614 
 615     case T_ADDRESS: {
 616       assert(patch_code == lir_patch_none, "no patching handled here");
 617       __ movptr(dest->as_register(), c->as_jint());
 618       break;
 619     }
 620 
 621     case T_LONG: {
 622       assert(patch_code == lir_patch_none, "no patching handled here");
 623 #ifdef _LP64
 624       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 625 #else
 626       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 627       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 628 #endif // _LP64
 629       break;
 630     }
 631 
 632     case T_OBJECT: {
 633       if (patch_code != lir_patch_none) {
 634         jobject2reg_with_patching(dest->as_register(), info);
 635       } else {
 636         __ movoop(dest->as_register(), c->as_jobject());
 637       }
 638       break;
 639     }
 640 
 641     case T_METADATA: {
 642       if (patch_code != lir_patch_none) {
 643         klass2reg_with_patching(dest->as_register(), info);
 644       } else {
 645         __ mov_metadata(dest->as_register(), c->as_metadata());
 646       }
 647       break;
 648     }
 649 
 650     case T_FLOAT: {
 651       if (dest->is_single_xmm()) {
 652         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
 653           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 654         } else {
 655           __ movflt(dest->as_xmm_float_reg(),
 656                    InternalAddress(float_constant(c->as_jfloat())));
 657         }
 658       } else {
 659         assert(dest->is_single_fpu(), "must be");
 660         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 661         if (c->is_zero_float()) {
 662           __ fldz();
 663         } else if (c->is_one_float()) {
 664           __ fld1();
 665         } else {
 666           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 667         }
 668       }
 669       break;
 670     }
 671 
 672     case T_DOUBLE: {
 673       if (dest->is_double_xmm()) {
 674         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
 675           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 676         } else {
 677           __ movdbl(dest->as_xmm_double_reg(),
 678                     InternalAddress(double_constant(c->as_jdouble())));
 679         }
 680       } else {
 681         assert(dest->is_double_fpu(), "must be");
 682         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 683         if (c->is_zero_double()) {
 684           __ fldz();
 685         } else if (c->is_one_double()) {
 686           __ fld1();
 687         } else {
 688           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 689         }
 690       }
 691       break;
 692     }
 693 
 694     default:
 695       ShouldNotReachHere();
 696   }
 697 }
 698 
 699 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 700   assert(src->is_constant(), "should not call otherwise");
 701   assert(dest->is_stack(), "should not call otherwise");
 702   LIR_Const* c = src->as_constant_ptr();
 703 
 704   switch (c->type()) {
 705     case T_INT:  // fall through
 706     case T_FLOAT:
 707       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 708       break;
 709 
 710     case T_ADDRESS:
 711       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 712       break;
 713 
 714     case T_OBJECT:
 715       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 716       break;
 717 
 718     case T_LONG:  // fall through
 719     case T_DOUBLE:
 720 #ifdef _LP64
 721       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 722                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 723 #else
 724       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 725                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 726       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 727                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 728 #endif // _LP64
 729       break;
 730 
 731     default:
 732       ShouldNotReachHere();
 733   }
 734 }
 735 
 736 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 737   assert(src->is_constant(), "should not call otherwise");
 738   assert(dest->is_address(), "should not call otherwise");
 739   LIR_Const* c = src->as_constant_ptr();
 740   LIR_Address* addr = dest->as_address_ptr();
 741 
 742   int null_check_here = code_offset();
 743   switch (type) {
 744     case T_INT:    // fall through
 745     case T_FLOAT:
 746       __ movl(as_Address(addr), c->as_jint_bits());
 747       break;
 748 
 749     case T_ADDRESS:
 750       __ movptr(as_Address(addr), c->as_jint_bits());
 751       break;
 752 
 753     case T_OBJECT:  // fall through
 754     case T_ARRAY:
 755       if (c->as_jobject() == NULL) {
 756         if (UseCompressedOops && !wide) {
 757           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 758         } else {
 759 #ifdef _LP64
 760           __ xorptr(rscratch1, rscratch1);
 761           null_check_here = code_offset();
 762           __ movptr(as_Address(addr), rscratch1);
 763 #else
 764           __ movptr(as_Address(addr), NULL_WORD);
 765 #endif
 766         }
 767       } else {
 768         if (is_literal_address(addr)) {
 769           ShouldNotReachHere();
 770           __ movoop(as_Address(addr, noreg), c->as_jobject());
 771         } else {
 772 #ifdef _LP64
 773           __ movoop(rscratch1, c->as_jobject());
 774           if (UseCompressedOops && !wide) {
 775             __ encode_heap_oop(rscratch1);
 776             null_check_here = code_offset();
 777             __ movl(as_Address_lo(addr), rscratch1);
 778           } else {
 779             null_check_here = code_offset();
 780             __ movptr(as_Address_lo(addr), rscratch1);
 781           }
 782 #else
 783           __ movoop(as_Address(addr), c->as_jobject());
 784 #endif
 785         }
 786       }
 787       break;
 788 
 789     case T_LONG:    // fall through
 790     case T_DOUBLE:
 791 #ifdef _LP64
 792       if (is_literal_address(addr)) {
 793         ShouldNotReachHere();
 794         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 795       } else {
 796         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 797         null_check_here = code_offset();
 798         __ movptr(as_Address_lo(addr), r10);
 799       }
 800 #else
 801       // Always reachable in 32bit so this doesn't produce useless move literal
 802       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 803       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 804 #endif // _LP64
 805       break;
 806 
 807     case T_BOOLEAN: // fall through
 808     case T_BYTE:
 809       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 810       break;
 811 
 812     case T_CHAR:    // fall through
 813     case T_SHORT:
 814       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 815       break;
 816 
 817     default:
 818       ShouldNotReachHere();
 819   };
 820 
 821   if (info != NULL) {
 822     add_debug_info_for_null_check(null_check_here, info);
 823   }
 824 }
 825 
 826 
 827 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 828   assert(src->is_register(), "should not call otherwise");
 829   assert(dest->is_register(), "should not call otherwise");
 830 
 831   // move between cpu-registers
 832   if (dest->is_single_cpu()) {
 833 #ifdef _LP64
 834     if (src->type() == T_LONG) {
 835       // Can do LONG -> OBJECT
 836       move_regs(src->as_register_lo(), dest->as_register());
 837       return;
 838     }
 839 #endif
 840     assert(src->is_single_cpu(), "must match");
 841     if (src->type() == T_OBJECT) {
 842       __ verify_oop(src->as_register());
 843     }
 844     move_regs(src->as_register(), dest->as_register());
 845 
 846   } else if (dest->is_double_cpu()) {
 847 #ifdef _LP64
 848     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 849       // Surprising to me but we can see move of a long to t_object
 850       __ verify_oop(src->as_register());
 851       move_regs(src->as_register(), dest->as_register_lo());
 852       return;
 853     }
 854 #endif
 855     assert(src->is_double_cpu(), "must match");
 856     Register f_lo = src->as_register_lo();
 857     Register f_hi = src->as_register_hi();
 858     Register t_lo = dest->as_register_lo();
 859     Register t_hi = dest->as_register_hi();
 860 #ifdef _LP64
 861     assert(f_hi == f_lo, "must be same");
 862     assert(t_hi == t_lo, "must be same");
 863     move_regs(f_lo, t_lo);
 864 #else
 865     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 866 
 867 
 868     if (f_lo == t_hi && f_hi == t_lo) {
 869       swap_reg(f_lo, f_hi);
 870     } else if (f_hi == t_lo) {
 871       assert(f_lo != t_hi, "overwriting register");
 872       move_regs(f_hi, t_hi);
 873       move_regs(f_lo, t_lo);
 874     } else {
 875       assert(f_hi != t_lo, "overwriting register");
 876       move_regs(f_lo, t_lo);
 877       move_regs(f_hi, t_hi);
 878     }
 879 #endif // LP64
 880 
 881     // special moves from fpu-register to xmm-register
 882     // necessary for method results
 883   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 884     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 885     __ fld_s(Address(rsp, 0));
 886   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 887     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 888     __ fld_d(Address(rsp, 0));
 889   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 890     __ fstp_s(Address(rsp, 0));
 891     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 892   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 893     __ fstp_d(Address(rsp, 0));
 894     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 895 
 896     // move between xmm-registers
 897   } else if (dest->is_single_xmm()) {
 898     assert(src->is_single_xmm(), "must match");
 899     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 900   } else if (dest->is_double_xmm()) {
 901     assert(src->is_double_xmm(), "must match");
 902     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 903 
 904     // move between fpu-registers (no instruction necessary because of fpu-stack)
 905   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 906     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 907     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 908   } else {
 909     ShouldNotReachHere();
 910   }
 911 }
 912 
 913 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 914   assert(src->is_register(), "should not call otherwise");
 915   assert(dest->is_stack(), "should not call otherwise");
 916 
 917   if (src->is_single_cpu()) {
 918     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 919     if (type == T_OBJECT || type == T_ARRAY) {
 920       __ verify_oop(src->as_register());
 921       __ movptr (dst, src->as_register());
 922     } else if (type == T_METADATA) {
 923       __ movptr (dst, src->as_register());
 924     } else {
 925       __ movl (dst, src->as_register());
 926     }
 927 
 928   } else if (src->is_double_cpu()) {
 929     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 930     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 931     __ movptr (dstLO, src->as_register_lo());
 932     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 933 
 934   } else if (src->is_single_xmm()) {
 935     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 936     __ movflt(dst_addr, src->as_xmm_float_reg());
 937 
 938   } else if (src->is_double_xmm()) {
 939     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 940     __ movdbl(dst_addr, src->as_xmm_double_reg());
 941 
 942   } else if (src->is_single_fpu()) {
 943     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 944     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 945     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 946     else                   __ fst_s  (dst_addr);
 947 
 948   } else if (src->is_double_fpu()) {
 949     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 950     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 951     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 952     else                   __ fst_d  (dst_addr);
 953 
 954   } else {
 955     ShouldNotReachHere();
 956   }
 957 }
 958 
 959 
 960 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 961   LIR_Address* to_addr = dest->as_address_ptr();
 962   PatchingStub* patch = NULL;
 963   Register compressed_src = rscratch1;
 964 
 965   if (type == T_ARRAY || type == T_OBJECT) {
 966     __ verify_oop(src->as_register());
 967 #ifdef _LP64
 968     if (UseCompressedOops && !wide) {
 969       __ movptr(compressed_src, src->as_register());
 970       __ encode_heap_oop(compressed_src);
 971       if (patch_code != lir_patch_none) {
 972         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 973       }
 974     }
 975 #endif
 976   }
 977 
 978   if (patch_code != lir_patch_none) {
 979     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 980     Address toa = as_Address(to_addr);
 981     assert(toa.disp() != 0, "must have");
 982   }
 983 
 984   int null_check_here = code_offset();
 985   switch (type) {
 986     case T_FLOAT: {
 987       if (src->is_single_xmm()) {
 988         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 989       } else {
 990         assert(src->is_single_fpu(), "must be");
 991         assert(src->fpu_regnr() == 0, "argument must be on TOS");
 992         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
 993         else                    __ fst_s (as_Address(to_addr));
 994       }
 995       break;
 996     }
 997 
 998     case T_DOUBLE: {
 999       if (src->is_double_xmm()) {
1000         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1001       } else {
1002         assert(src->is_double_fpu(), "must be");
1003         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1004         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1005         else                    __ fst_d (as_Address(to_addr));
1006       }
1007       break;
1008     }
1009 
1010     case T_ARRAY:   // fall through
1011     case T_OBJECT:  // fall through
1012       if (UseCompressedOops && !wide) {
1013         __ movl(as_Address(to_addr), compressed_src);
1014       } else {
1015         __ movptr(as_Address(to_addr), src->as_register());
1016       }
1017       break;
1018     case T_METADATA:
1019       // We get here to store a method pointer to the stack to pass to
1020       // a dtrace runtime call. This can't work on 64 bit with
1021       // compressed klass ptrs: T_METADATA can be a compressed klass
1022       // ptr or a 64 bit method pointer.
1023       LP64_ONLY(ShouldNotReachHere());
1024       __ movptr(as_Address(to_addr), src->as_register());
1025       break;
1026     case T_ADDRESS:
1027       __ movptr(as_Address(to_addr), src->as_register());
1028       break;
1029     case T_INT:
1030       __ movl(as_Address(to_addr), src->as_register());
1031       break;
1032 
1033     case T_LONG: {
1034       Register from_lo = src->as_register_lo();
1035       Register from_hi = src->as_register_hi();
1036 #ifdef _LP64
1037       __ movptr(as_Address_lo(to_addr), from_lo);
1038 #else
1039       Register base = to_addr->base()->as_register();
1040       Register index = noreg;
1041       if (to_addr->index()->is_register()) {
1042         index = to_addr->index()->as_register();
1043       }
1044       if (base == from_lo || index == from_lo) {
1045         assert(base != from_hi, "can't be");
1046         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1047         __ movl(as_Address_hi(to_addr), from_hi);
1048         if (patch != NULL) {
1049           patching_epilog(patch, lir_patch_high, base, info);
1050           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1051           patch_code = lir_patch_low;
1052         }
1053         __ movl(as_Address_lo(to_addr), from_lo);
1054       } else {
1055         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1056         __ movl(as_Address_lo(to_addr), from_lo);
1057         if (patch != NULL) {
1058           patching_epilog(patch, lir_patch_low, base, info);
1059           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1060           patch_code = lir_patch_high;
1061         }
1062         __ movl(as_Address_hi(to_addr), from_hi);
1063       }
1064 #endif // _LP64
1065       break;
1066     }
1067 
1068     case T_BYTE:    // fall through
1069     case T_BOOLEAN: {
1070       Register src_reg = src->as_register();
1071       Address dst_addr = as_Address(to_addr);
1072       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1073       __ movb(dst_addr, src_reg);
1074       break;
1075     }
1076 
1077     case T_CHAR:    // fall through
1078     case T_SHORT:
1079       __ movw(as_Address(to_addr), src->as_register());
1080       break;
1081 
1082     default:
1083       ShouldNotReachHere();
1084   }
1085   if (info != NULL) {
1086     add_debug_info_for_null_check(null_check_here, info);
1087   }
1088 
1089   if (patch_code != lir_patch_none) {
1090     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1091   }
1092 }
1093 
1094 
1095 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1096   assert(src->is_stack(), "should not call otherwise");
1097   assert(dest->is_register(), "should not call otherwise");
1098 
1099   if (dest->is_single_cpu()) {
1100     if (type == T_ARRAY || type == T_OBJECT) {
1101       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1102       __ verify_oop(dest->as_register());
1103     } else if (type == T_METADATA) {
1104       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1105     } else {
1106       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1107     }
1108 
1109   } else if (dest->is_double_cpu()) {
1110     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1111     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1112     __ movptr(dest->as_register_lo(), src_addr_LO);
1113     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1114 
1115   } else if (dest->is_single_xmm()) {
1116     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1117     __ movflt(dest->as_xmm_float_reg(), src_addr);
1118 
1119   } else if (dest->is_double_xmm()) {
1120     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1121     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1122 
1123   } else if (dest->is_single_fpu()) {
1124     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1125     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1126     __ fld_s(src_addr);
1127 
1128   } else if (dest->is_double_fpu()) {
1129     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1130     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1131     __ fld_d(src_addr);
1132 
1133   } else {
1134     ShouldNotReachHere();
1135   }
1136 }
1137 
1138 
1139 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1140   if (src->is_single_stack()) {
1141     if (type == T_OBJECT || type == T_ARRAY) {
1142       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1143       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1144     } else {
1145 #ifndef _LP64
1146       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1147       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1148 #else
1149       //no pushl on 64bits
1150       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1151       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1152 #endif
1153     }
1154 
1155   } else if (src->is_double_stack()) {
1156 #ifdef _LP64
1157     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1158     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1159 #else
1160     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1161     // push and pop the part at src + wordSize, adding wordSize for the previous push
1162     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1163     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1164     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1165 #endif // _LP64
1166 
1167   } else {
1168     ShouldNotReachHere();
1169   }
1170 }
1171 
1172 
1173 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1174   assert(src->is_address(), "should not call otherwise");
1175   assert(dest->is_register(), "should not call otherwise");
1176 
1177   LIR_Address* addr = src->as_address_ptr();
1178   Address from_addr = as_Address(addr);
1179 
1180   if (addr->base()->type() == T_OBJECT) {
1181     __ verify_oop(addr->base()->as_pointer_register());
1182   }
1183 
1184   switch (type) {
1185     case T_BOOLEAN: // fall through
1186     case T_BYTE:    // fall through
1187     case T_CHAR:    // fall through
1188     case T_SHORT:
1189       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1190         // on pre P6 processors we may get partial register stalls
1191         // so blow away the value of to_rinfo before loading a
1192         // partial word into it.  Do it here so that it precedes
1193         // the potential patch point below.
1194         __ xorptr(dest->as_register(), dest->as_register());
1195       }
1196       break;
1197    default:
1198      break;
1199   }
1200 
1201   PatchingStub* patch = NULL;
1202   if (patch_code != lir_patch_none) {
1203     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1204     assert(from_addr.disp() != 0, "must have");
1205   }
1206   if (info != NULL) {
1207     add_debug_info_for_null_check_here(info);
1208   }
1209 
1210   switch (type) {
1211     case T_FLOAT: {
1212       if (dest->is_single_xmm()) {
1213         __ movflt(dest->as_xmm_float_reg(), from_addr);
1214       } else {
1215         assert(dest->is_single_fpu(), "must be");
1216         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1217         __ fld_s(from_addr);
1218       }
1219       break;
1220     }
1221 
1222     case T_DOUBLE: {
1223       if (dest->is_double_xmm()) {
1224         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1225       } else {
1226         assert(dest->is_double_fpu(), "must be");
1227         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1228         __ fld_d(from_addr);
1229       }
1230       break;
1231     }
1232 
1233     case T_OBJECT:  // fall through
1234     case T_ARRAY:   // fall through
1235       if (UseCompressedOops && !wide) {
1236         __ movl(dest->as_register(), from_addr);
1237       } else {
1238         __ movptr(dest->as_register(), from_addr);
1239       }
1240       break;
1241 
1242     case T_ADDRESS:
1243       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1244         __ movl(dest->as_register(), from_addr);
1245       } else {
1246         __ movptr(dest->as_register(), from_addr);
1247       }
1248       break;
1249     case T_INT:
1250       __ movl(dest->as_register(), from_addr);
1251       break;
1252 
1253     case T_LONG: {
1254       Register to_lo = dest->as_register_lo();
1255       Register to_hi = dest->as_register_hi();
1256 #ifdef _LP64
1257       __ movptr(to_lo, as_Address_lo(addr));
1258 #else
1259       Register base = addr->base()->as_register();
1260       Register index = noreg;
1261       if (addr->index()->is_register()) {
1262         index = addr->index()->as_register();
1263       }
1264       if ((base == to_lo && index == to_hi) ||
1265           (base == to_hi && index == to_lo)) {
1266         // addresses with 2 registers are only formed as a result of
1267         // array access so this code will never have to deal with
1268         // patches or null checks.
1269         assert(info == NULL && patch == NULL, "must be");
1270         __ lea(to_hi, as_Address(addr));
1271         __ movl(to_lo, Address(to_hi, 0));
1272         __ movl(to_hi, Address(to_hi, BytesPerWord));
1273       } else if (base == to_lo || index == to_lo) {
1274         assert(base != to_hi, "can't be");
1275         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1276         __ movl(to_hi, as_Address_hi(addr));
1277         if (patch != NULL) {
1278           patching_epilog(patch, lir_patch_high, base, info);
1279           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1280           patch_code = lir_patch_low;
1281         }
1282         __ movl(to_lo, as_Address_lo(addr));
1283       } else {
1284         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1285         __ movl(to_lo, as_Address_lo(addr));
1286         if (patch != NULL) {
1287           patching_epilog(patch, lir_patch_low, base, info);
1288           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1289           patch_code = lir_patch_high;
1290         }
1291         __ movl(to_hi, as_Address_hi(addr));
1292       }
1293 #endif // _LP64
1294       break;
1295     }
1296 
1297     case T_BOOLEAN: // fall through
1298     case T_BYTE: {
1299       Register dest_reg = dest->as_register();
1300       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1301       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1302         __ movsbl(dest_reg, from_addr);
1303       } else {
1304         __ movb(dest_reg, from_addr);
1305         __ shll(dest_reg, 24);
1306         __ sarl(dest_reg, 24);
1307       }
1308       break;
1309     }
1310 
1311     case T_CHAR: {
1312       Register dest_reg = dest->as_register();
1313       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1314       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1315         __ movzwl(dest_reg, from_addr);
1316       } else {
1317         __ movw(dest_reg, from_addr);
1318       }
1319       break;
1320     }
1321 
1322     case T_SHORT: {
1323       Register dest_reg = dest->as_register();
1324       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1325         __ movswl(dest_reg, from_addr);
1326       } else {
1327         __ movw(dest_reg, from_addr);
1328         __ shll(dest_reg, 16);
1329         __ sarl(dest_reg, 16);
1330       }
1331       break;
1332     }
1333 
1334     default:
1335       ShouldNotReachHere();
1336   }
1337 
1338   if (patch != NULL) {
1339     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1340   }
1341 
1342   if (type == T_ARRAY || type == T_OBJECT) {
1343 #ifdef _LP64
1344     if (UseCompressedOops && !wide) {
1345       __ decode_heap_oop(dest->as_register());
1346     }
1347 #endif
1348 
1349     // Load barrier has not yet been applied, so ZGC can't verify the oop here
1350     if (!UseZGC) {
1351       __ verify_oop(dest->as_register());
1352     }
1353   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1354 #ifdef _LP64
1355     if (UseCompressedClassPointers) {
1356       __ decode_klass_not_null(dest->as_register());
1357     }
1358 #endif
1359   }
1360 }
1361 
1362 
1363 NEEDS_CLEANUP; // This could be static?
1364 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1365   int elem_size = type2aelembytes(type);
1366   switch (elem_size) {
1367     case 1: return Address::times_1;
1368     case 2: return Address::times_2;
1369     case 4: return Address::times_4;
1370     case 8: return Address::times_8;
1371   }
1372   ShouldNotReachHere();
1373   return Address::no_scale;
1374 }
1375 
1376 
1377 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1378   switch (op->code()) {
1379     case lir_idiv:
1380     case lir_irem:
1381       arithmetic_idiv(op->code(),
1382                       op->in_opr1(),
1383                       op->in_opr2(),
1384                       op->in_opr3(),
1385                       op->result_opr(),
1386                       op->info());
1387       break;
1388     case lir_fmad:
1389       __ fmad(op->result_opr()->as_xmm_double_reg(),
1390               op->in_opr1()->as_xmm_double_reg(),
1391               op->in_opr2()->as_xmm_double_reg(),
1392               op->in_opr3()->as_xmm_double_reg());
1393       break;
1394     case lir_fmaf:
1395       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1396               op->in_opr1()->as_xmm_float_reg(),
1397               op->in_opr2()->as_xmm_float_reg(),
1398               op->in_opr3()->as_xmm_float_reg());
1399       break;
1400     default:      ShouldNotReachHere(); break;
1401   }
1402 }
1403 
1404 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1405 #ifdef ASSERT
1406   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1407   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1408   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1409 #endif
1410 
1411   if (op->cond() == lir_cond_always) {
1412     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1413     __ jmp (*(op->label()));
1414   } else {
1415     Assembler::Condition acond = Assembler::zero;
1416     if (op->code() == lir_cond_float_branch) {
1417       assert(op->ublock() != NULL, "must have unordered successor");
1418       __ jcc(Assembler::parity, *(op->ublock()->label()));
1419       switch(op->cond()) {
1420         case lir_cond_equal:        acond = Assembler::equal;      break;
1421         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1422         case lir_cond_less:         acond = Assembler::below;      break;
1423         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1424         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1425         case lir_cond_greater:      acond = Assembler::above;      break;
1426         default:                         ShouldNotReachHere();
1427       }
1428     } else {
1429       switch (op->cond()) {
1430         case lir_cond_equal:        acond = Assembler::equal;       break;
1431         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1432         case lir_cond_less:         acond = Assembler::less;        break;
1433         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1434         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1435         case lir_cond_greater:      acond = Assembler::greater;     break;
1436         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1437         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1438         default:                         ShouldNotReachHere();
1439       }
1440     }
1441     __ jcc(acond,*(op->label()));
1442   }
1443 }
1444 
1445 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1446   LIR_Opr src  = op->in_opr();
1447   LIR_Opr dest = op->result_opr();
1448 
1449   switch (op->bytecode()) {
1450     case Bytecodes::_i2l:
1451 #ifdef _LP64
1452       __ movl2ptr(dest->as_register_lo(), src->as_register());
1453 #else
1454       move_regs(src->as_register(), dest->as_register_lo());
1455       move_regs(src->as_register(), dest->as_register_hi());
1456       __ sarl(dest->as_register_hi(), 31);
1457 #endif // LP64
1458       break;
1459 
1460     case Bytecodes::_l2i:
1461 #ifdef _LP64
1462       __ movl(dest->as_register(), src->as_register_lo());
1463 #else
1464       move_regs(src->as_register_lo(), dest->as_register());
1465 #endif
1466       break;
1467 
1468     case Bytecodes::_i2b:
1469       move_regs(src->as_register(), dest->as_register());
1470       __ sign_extend_byte(dest->as_register());
1471       break;
1472 
1473     case Bytecodes::_i2c:
1474       move_regs(src->as_register(), dest->as_register());
1475       __ andl(dest->as_register(), 0xFFFF);
1476       break;
1477 
1478     case Bytecodes::_i2s:
1479       move_regs(src->as_register(), dest->as_register());
1480       __ sign_extend_short(dest->as_register());
1481       break;
1482 
1483 
1484     case Bytecodes::_f2d:
1485     case Bytecodes::_d2f:
1486       if (dest->is_single_xmm()) {
1487         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1488       } else if (dest->is_double_xmm()) {
1489         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1490       } else {
1491         assert(src->fpu() == dest->fpu(), "register must be equal");
1492         // do nothing (float result is rounded later through spilling)
1493       }
1494       break;
1495 
1496     case Bytecodes::_i2f:
1497     case Bytecodes::_i2d:
1498       if (dest->is_single_xmm()) {
1499         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1500       } else if (dest->is_double_xmm()) {
1501         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1502       } else {
1503         assert(dest->fpu() == 0, "result must be on TOS");
1504         __ movl(Address(rsp, 0), src->as_register());
1505         __ fild_s(Address(rsp, 0));
1506       }
1507       break;
1508 
1509     case Bytecodes::_f2i:
1510     case Bytecodes::_d2i:
1511       if (src->is_single_xmm()) {
1512         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1513       } else if (src->is_double_xmm()) {
1514         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1515       } else {
1516         assert(src->fpu() == 0, "input must be on TOS");
1517         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1518         __ fist_s(Address(rsp, 0));
1519         __ movl(dest->as_register(), Address(rsp, 0));
1520         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1521       }
1522 
1523       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1524       assert(op->stub() != NULL, "stub required");
1525       __ cmpl(dest->as_register(), 0x80000000);
1526       __ jcc(Assembler::equal, *op->stub()->entry());
1527       __ bind(*op->stub()->continuation());
1528       break;
1529 
1530     case Bytecodes::_l2f:
1531     case Bytecodes::_l2d:
1532       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1533       assert(dest->fpu() == 0, "result must be on TOS");
1534 
1535       __ movptr(Address(rsp, 0),            src->as_register_lo());
1536       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1537       __ fild_d(Address(rsp, 0));
1538       // float result is rounded later through spilling
1539       break;
1540 
1541     case Bytecodes::_f2l:
1542     case Bytecodes::_d2l:
1543       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1544       assert(src->fpu() == 0, "input must be on TOS");
1545       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1546 
1547       // instruction sequence too long to inline it here
1548       {
1549         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1550       }
1551       break;
1552 
1553     default: ShouldNotReachHere();
1554   }
1555 }
1556 
1557 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1558   if (op->init_check()) {
1559     add_debug_info_for_null_check_here(op->stub()->info());
1560     __ cmpb(Address(op->klass()->as_register(),
1561                     InstanceKlass::init_state_offset()),
1562                     InstanceKlass::fully_initialized);
1563     __ jcc(Assembler::notEqual, *op->stub()->entry());
1564   }
1565   __ allocate_object(op->obj()->as_register(),
1566                      op->tmp1()->as_register(),
1567                      op->tmp2()->as_register(),
1568                      op->header_size(),
1569                      op->object_size(),
1570                      op->klass()->as_register(),
1571                      *op->stub()->entry());
1572   __ bind(*op->stub()->continuation());
1573 }
1574 
1575 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1576   Register len =  op->len()->as_register();
1577   LP64_ONLY( __ movslq(len, len); )
1578 
1579   if (UseSlowPath ||
1580       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1581       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1582     __ jmp(*op->stub()->entry());
1583   } else {
1584     Register tmp1 = op->tmp1()->as_register();
1585     Register tmp2 = op->tmp2()->as_register();
1586     Register tmp3 = op->tmp3()->as_register();
1587     if (len == tmp1) {
1588       tmp1 = tmp3;
1589     } else if (len == tmp2) {
1590       tmp2 = tmp3;
1591     } else if (len == tmp3) {
1592       // everything is ok
1593     } else {
1594       __ mov(tmp3, len);
1595     }
1596     __ allocate_array(op->obj()->as_register(),
1597                       len,
1598                       tmp1,
1599                       tmp2,
1600                       arrayOopDesc::header_size(op->type()),
1601                       array_element_size(op->type()),
1602                       op->klass()->as_register(),
1603                       *op->stub()->entry());
1604   }
1605   __ bind(*op->stub()->continuation());
1606 }
1607 
1608 void LIR_Assembler::type_profile_helper(Register mdo,
1609                                         ciMethodData *md, ciProfileData *data,
1610                                         Register recv, Label* update_done) {
1611   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1612     Label next_test;
1613     // See if the receiver is receiver[n].
1614     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1615     __ jccb(Assembler::notEqual, next_test);
1616     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1617     __ addptr(data_addr, DataLayout::counter_increment);
1618     __ jmp(*update_done);
1619     __ bind(next_test);
1620   }
1621 
1622   // Didn't find receiver; find next empty slot and fill it in
1623   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1624     Label next_test;
1625     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1626     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1627     __ jccb(Assembler::notEqual, next_test);
1628     __ movptr(recv_addr, recv);
1629     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1630     __ jmp(*update_done);
1631     __ bind(next_test);
1632   }
1633 }
1634 
1635 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1636   // we always need a stub for the failure case.
1637   CodeStub* stub = op->stub();
1638   Register obj = op->object()->as_register();
1639   Register k_RInfo = op->tmp1()->as_register();
1640   Register klass_RInfo = op->tmp2()->as_register();
1641   Register dst = op->result_opr()->as_register();
1642   ciKlass* k = op->klass();
1643   Register Rtmp1 = noreg;
1644 
1645   // check if it needs to be profiled
1646   ciMethodData* md = NULL;
1647   ciProfileData* data = NULL;
1648 
1649   if (op->should_profile()) {
1650     ciMethod* method = op->profiled_method();
1651     assert(method != NULL, "Should have method");
1652     int bci = op->profiled_bci();
1653     md = method->method_data_or_null();
1654     assert(md != NULL, "Sanity");
1655     data = md->bci_to_data(bci);
1656     assert(data != NULL,                "need data for type check");
1657     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1658   }
1659   Label profile_cast_success, profile_cast_failure;
1660   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1661   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1662 
1663   if (obj == k_RInfo) {
1664     k_RInfo = dst;
1665   } else if (obj == klass_RInfo) {
1666     klass_RInfo = dst;
1667   }
1668   if (k->is_loaded() && !UseCompressedClassPointers) {
1669     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1670   } else {
1671     Rtmp1 = op->tmp3()->as_register();
1672     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1673   }
1674 
1675   assert_different_registers(obj, k_RInfo, klass_RInfo);
1676 
1677   __ cmpptr(obj, (int32_t)NULL_WORD);
1678   if (op->should_profile()) {
1679     Label not_null;
1680     __ jccb(Assembler::notEqual, not_null);
1681     // Object is null; update MDO and exit
1682     Register mdo  = klass_RInfo;
1683     __ mov_metadata(mdo, md->constant_encoding());
1684     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1685     int header_bits = BitData::null_seen_byte_constant();
1686     __ orb(data_addr, header_bits);
1687     __ jmp(*obj_is_null);
1688     __ bind(not_null);
1689   } else {
1690     __ jcc(Assembler::equal, *obj_is_null);
1691   }
1692 
1693   if (!k->is_loaded()) {
1694     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1695   } else {
1696 #ifdef _LP64
1697     __ mov_metadata(k_RInfo, k->constant_encoding());
1698 #endif // _LP64
1699   }
1700   __ verify_oop(obj);
1701 
1702   if (op->fast_check()) {
1703     // get object class
1704     // not a safepoint as obj null check happens earlier
1705 #ifdef _LP64
1706     if (UseCompressedClassPointers) {
1707       __ load_klass(Rtmp1, obj);
1708       __ cmpptr(k_RInfo, Rtmp1);
1709     } else {
1710       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1711     }
1712 #else
1713     if (k->is_loaded()) {
1714       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1715     } else {
1716       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1717     }
1718 #endif
1719     __ jcc(Assembler::notEqual, *failure_target);
1720     // successful cast, fall through to profile or jump
1721   } else {
1722     // get object class
1723     // not a safepoint as obj null check happens earlier
1724     __ load_klass(klass_RInfo, obj);
1725     if (k->is_loaded()) {
1726       // See if we get an immediate positive hit
1727 #ifdef _LP64
1728       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1729 #else
1730       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1731 #endif // _LP64
1732       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1733         __ jcc(Assembler::notEqual, *failure_target);
1734         // successful cast, fall through to profile or jump
1735       } else {
1736         // See if we get an immediate positive hit
1737         __ jcc(Assembler::equal, *success_target);
1738         // check for self
1739 #ifdef _LP64
1740         __ cmpptr(klass_RInfo, k_RInfo);
1741 #else
1742         __ cmpklass(klass_RInfo, k->constant_encoding());
1743 #endif // _LP64
1744         __ jcc(Assembler::equal, *success_target);
1745 
1746         __ push(klass_RInfo);
1747 #ifdef _LP64
1748         __ push(k_RInfo);
1749 #else
1750         __ pushklass(k->constant_encoding());
1751 #endif // _LP64
1752         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1753         __ pop(klass_RInfo);
1754         __ pop(klass_RInfo);
1755         // result is a boolean
1756         __ cmpl(klass_RInfo, 0);
1757         __ jcc(Assembler::equal, *failure_target);
1758         // successful cast, fall through to profile or jump
1759       }
1760     } else {
1761       // perform the fast part of the checking logic
1762       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1763       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1764       __ push(klass_RInfo);
1765       __ push(k_RInfo);
1766       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1767       __ pop(klass_RInfo);
1768       __ pop(k_RInfo);
1769       // result is a boolean
1770       __ cmpl(k_RInfo, 0);
1771       __ jcc(Assembler::equal, *failure_target);
1772       // successful cast, fall through to profile or jump
1773     }
1774   }
1775   if (op->should_profile()) {
1776     Register mdo  = klass_RInfo, recv = k_RInfo;
1777     __ bind(profile_cast_success);
1778     __ mov_metadata(mdo, md->constant_encoding());
1779     __ load_klass(recv, obj);
1780     Label update_done;
1781     type_profile_helper(mdo, md, data, recv, success);
1782     __ jmp(*success);
1783 
1784     __ bind(profile_cast_failure);
1785     __ mov_metadata(mdo, md->constant_encoding());
1786     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1787     __ subptr(counter_addr, DataLayout::counter_increment);
1788     __ jmp(*failure);
1789   }
1790   __ jmp(*success);
1791 }
1792 
1793 
1794 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1795   LIR_Code code = op->code();
1796   if (code == lir_store_check) {
1797     Register value = op->object()->as_register();
1798     Register array = op->array()->as_register();
1799     Register k_RInfo = op->tmp1()->as_register();
1800     Register klass_RInfo = op->tmp2()->as_register();
1801     Register Rtmp1 = op->tmp3()->as_register();
1802 
1803     CodeStub* stub = op->stub();
1804 
1805     // check if it needs to be profiled
1806     ciMethodData* md = NULL;
1807     ciProfileData* data = NULL;
1808 
1809     if (op->should_profile()) {
1810       ciMethod* method = op->profiled_method();
1811       assert(method != NULL, "Should have method");
1812       int bci = op->profiled_bci();
1813       md = method->method_data_or_null();
1814       assert(md != NULL, "Sanity");
1815       data = md->bci_to_data(bci);
1816       assert(data != NULL,                "need data for type check");
1817       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1818     }
1819     Label profile_cast_success, profile_cast_failure, done;
1820     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1821     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1822 
1823     __ cmpptr(value, (int32_t)NULL_WORD);
1824     if (op->should_profile()) {
1825       Label not_null;
1826       __ jccb(Assembler::notEqual, not_null);
1827       // Object is null; update MDO and exit
1828       Register mdo  = klass_RInfo;
1829       __ mov_metadata(mdo, md->constant_encoding());
1830       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1831       int header_bits = BitData::null_seen_byte_constant();
1832       __ orb(data_addr, header_bits);
1833       __ jmp(done);
1834       __ bind(not_null);
1835     } else {
1836       __ jcc(Assembler::equal, done);
1837     }
1838 
1839     add_debug_info_for_null_check_here(op->info_for_exception());
1840     __ load_klass(k_RInfo, array);
1841     __ load_klass(klass_RInfo, value);
1842 
1843     // get instance klass (it's already uncompressed)
1844     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1845     // perform the fast part of the checking logic
1846     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1847     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1848     __ push(klass_RInfo);
1849     __ push(k_RInfo);
1850     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1851     __ pop(klass_RInfo);
1852     __ pop(k_RInfo);
1853     // result is a boolean
1854     __ cmpl(k_RInfo, 0);
1855     __ jcc(Assembler::equal, *failure_target);
1856     // fall through to the success case
1857 
1858     if (op->should_profile()) {
1859       Register mdo  = klass_RInfo, recv = k_RInfo;
1860       __ bind(profile_cast_success);
1861       __ mov_metadata(mdo, md->constant_encoding());
1862       __ load_klass(recv, value);
1863       Label update_done;
1864       type_profile_helper(mdo, md, data, recv, &done);
1865       __ jmpb(done);
1866 
1867       __ bind(profile_cast_failure);
1868       __ mov_metadata(mdo, md->constant_encoding());
1869       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1870       __ subptr(counter_addr, DataLayout::counter_increment);
1871       __ jmp(*stub->entry());
1872     }
1873 
1874     __ bind(done);
1875   } else
1876     if (code == lir_checkcast) {
1877       Register obj = op->object()->as_register();
1878       Register dst = op->result_opr()->as_register();
1879       Label success;
1880       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1881       __ bind(success);
1882       if (dst != obj) {
1883         __ mov(dst, obj);
1884       }
1885     } else
1886       if (code == lir_instanceof) {
1887         Register obj = op->object()->as_register();
1888         Register dst = op->result_opr()->as_register();
1889         Label success, failure, done;
1890         emit_typecheck_helper(op, &success, &failure, &failure);
1891         __ bind(failure);
1892         __ xorptr(dst, dst);
1893         __ jmpb(done);
1894         __ bind(success);
1895         __ movptr(dst, 1);
1896         __ bind(done);
1897       } else {
1898         ShouldNotReachHere();
1899       }
1900 
1901 }
1902 
1903 
1904 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1905   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1906     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1907     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1908     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1909     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1910     Register addr = op->addr()->as_register();
1911     if (os::is_MP()) {
1912       __ lock();
1913     }
1914     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1915 
1916   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1917     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1918     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1919     Register newval = op->new_value()->as_register();
1920     Register cmpval = op->cmp_value()->as_register();
1921     assert(cmpval == rax, "wrong register");
1922     assert(newval != NULL, "new val must be register");
1923     assert(cmpval != newval, "cmp and new values must be in different registers");
1924     assert(cmpval != addr, "cmp and addr must be in different registers");
1925     assert(newval != addr, "new value and addr must be in different registers");
1926 
1927     if ( op->code() == lir_cas_obj) {
1928 #ifdef _LP64
1929       if (UseCompressedOops) {
1930         __ encode_heap_oop(cmpval);
1931         __ mov(rscratch1, newval);
1932         __ encode_heap_oop(rscratch1);
1933         if (os::is_MP()) {
1934           __ lock();
1935         }
1936         // cmpval (rax) is implicitly used by this instruction
1937         __ cmpxchgl(rscratch1, Address(addr, 0));
1938       } else
1939 #endif
1940       {
1941         if (os::is_MP()) {
1942           __ lock();
1943         }
1944         __ cmpxchgptr(newval, Address(addr, 0));
1945       }
1946     } else {
1947       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1948       if (os::is_MP()) {
1949         __ lock();
1950       }
1951       __ cmpxchgl(newval, Address(addr, 0));
1952     }
1953 #ifdef _LP64
1954   } else if (op->code() == lir_cas_long) {
1955     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1956     Register newval = op->new_value()->as_register_lo();
1957     Register cmpval = op->cmp_value()->as_register_lo();
1958     assert(cmpval == rax, "wrong register");
1959     assert(newval != NULL, "new val must be register");
1960     assert(cmpval != newval, "cmp and new values must be in different registers");
1961     assert(cmpval != addr, "cmp and addr must be in different registers");
1962     assert(newval != addr, "new value and addr must be in different registers");
1963     if (os::is_MP()) {
1964       __ lock();
1965     }
1966     __ cmpxchgq(newval, Address(addr, 0));
1967 #endif // _LP64
1968   } else {
1969     Unimplemented();
1970   }
1971 }
1972 
1973 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1974   Assembler::Condition acond, ncond;
1975   switch (condition) {
1976     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1977     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1978     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
1979     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
1980     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
1981     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
1982     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
1983     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
1984     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
1985                                 ShouldNotReachHere();
1986   }
1987 
1988   if (opr1->is_cpu_register()) {
1989     reg2reg(opr1, result);
1990   } else if (opr1->is_stack()) {
1991     stack2reg(opr1, result, result->type());
1992   } else if (opr1->is_constant()) {
1993     const2reg(opr1, result, lir_patch_none, NULL);
1994   } else {
1995     ShouldNotReachHere();
1996   }
1997 
1998   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1999     // optimized version that does not require a branch
2000     if (opr2->is_single_cpu()) {
2001       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2002       __ cmov(ncond, result->as_register(), opr2->as_register());
2003     } else if (opr2->is_double_cpu()) {
2004       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2005       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2006       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2007       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2008     } else if (opr2->is_single_stack()) {
2009       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2010     } else if (opr2->is_double_stack()) {
2011       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2012       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2013     } else {
2014       ShouldNotReachHere();
2015     }
2016 
2017   } else {
2018     Label skip;
2019     __ jcc (acond, skip);
2020     if (opr2->is_cpu_register()) {
2021       reg2reg(opr2, result);
2022     } else if (opr2->is_stack()) {
2023       stack2reg(opr2, result, result->type());
2024     } else if (opr2->is_constant()) {
2025       const2reg(opr2, result, lir_patch_none, NULL);
2026     } else {
2027       ShouldNotReachHere();
2028     }
2029     __ bind(skip);
2030   }
2031 }
2032 
2033 
2034 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2035   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2036 
2037   if (left->is_single_cpu()) {
2038     assert(left == dest, "left and dest must be equal");
2039     Register lreg = left->as_register();
2040 
2041     if (right->is_single_cpu()) {
2042       // cpu register - cpu register
2043       Register rreg = right->as_register();
2044       switch (code) {
2045         case lir_add: __ addl (lreg, rreg); break;
2046         case lir_sub: __ subl (lreg, rreg); break;
2047         case lir_mul: __ imull(lreg, rreg); break;
2048         default:      ShouldNotReachHere();
2049       }
2050 
2051     } else if (right->is_stack()) {
2052       // cpu register - stack
2053       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2054       switch (code) {
2055         case lir_add: __ addl(lreg, raddr); break;
2056         case lir_sub: __ subl(lreg, raddr); break;
2057         default:      ShouldNotReachHere();
2058       }
2059 
2060     } else if (right->is_constant()) {
2061       // cpu register - constant
2062       jint c = right->as_constant_ptr()->as_jint();
2063       switch (code) {
2064         case lir_add: {
2065           __ incrementl(lreg, c);
2066           break;
2067         }
2068         case lir_sub: {
2069           __ decrementl(lreg, c);
2070           break;
2071         }
2072         default: ShouldNotReachHere();
2073       }
2074 
2075     } else {
2076       ShouldNotReachHere();
2077     }
2078 
2079   } else if (left->is_double_cpu()) {
2080     assert(left == dest, "left and dest must be equal");
2081     Register lreg_lo = left->as_register_lo();
2082     Register lreg_hi = left->as_register_hi();
2083 
2084     if (right->is_double_cpu()) {
2085       // cpu register - cpu register
2086       Register rreg_lo = right->as_register_lo();
2087       Register rreg_hi = right->as_register_hi();
2088       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2089       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2090       switch (code) {
2091         case lir_add:
2092           __ addptr(lreg_lo, rreg_lo);
2093           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2094           break;
2095         case lir_sub:
2096           __ subptr(lreg_lo, rreg_lo);
2097           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2098           break;
2099         case lir_mul:
2100 #ifdef _LP64
2101           __ imulq(lreg_lo, rreg_lo);
2102 #else
2103           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2104           __ imull(lreg_hi, rreg_lo);
2105           __ imull(rreg_hi, lreg_lo);
2106           __ addl (rreg_hi, lreg_hi);
2107           __ mull (rreg_lo);
2108           __ addl (lreg_hi, rreg_hi);
2109 #endif // _LP64
2110           break;
2111         default:
2112           ShouldNotReachHere();
2113       }
2114 
2115     } else if (right->is_constant()) {
2116       // cpu register - constant
2117 #ifdef _LP64
2118       jlong c = right->as_constant_ptr()->as_jlong_bits();
2119       __ movptr(r10, (intptr_t) c);
2120       switch (code) {
2121         case lir_add:
2122           __ addptr(lreg_lo, r10);
2123           break;
2124         case lir_sub:
2125           __ subptr(lreg_lo, r10);
2126           break;
2127         default:
2128           ShouldNotReachHere();
2129       }
2130 #else
2131       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2132       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2133       switch (code) {
2134         case lir_add:
2135           __ addptr(lreg_lo, c_lo);
2136           __ adcl(lreg_hi, c_hi);
2137           break;
2138         case lir_sub:
2139           __ subptr(lreg_lo, c_lo);
2140           __ sbbl(lreg_hi, c_hi);
2141           break;
2142         default:
2143           ShouldNotReachHere();
2144       }
2145 #endif // _LP64
2146 
2147     } else {
2148       ShouldNotReachHere();
2149     }
2150 
2151   } else if (left->is_single_xmm()) {
2152     assert(left == dest, "left and dest must be equal");
2153     XMMRegister lreg = left->as_xmm_float_reg();
2154 
2155     if (right->is_single_xmm()) {
2156       XMMRegister rreg = right->as_xmm_float_reg();
2157       switch (code) {
2158         case lir_add: __ addss(lreg, rreg);  break;
2159         case lir_sub: __ subss(lreg, rreg);  break;
2160         case lir_mul_strictfp: // fall through
2161         case lir_mul: __ mulss(lreg, rreg);  break;
2162         case lir_div_strictfp: // fall through
2163         case lir_div: __ divss(lreg, rreg);  break;
2164         default: ShouldNotReachHere();
2165       }
2166     } else {
2167       Address raddr;
2168       if (right->is_single_stack()) {
2169         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2170       } else if (right->is_constant()) {
2171         // hack for now
2172         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2173       } else {
2174         ShouldNotReachHere();
2175       }
2176       switch (code) {
2177         case lir_add: __ addss(lreg, raddr);  break;
2178         case lir_sub: __ subss(lreg, raddr);  break;
2179         case lir_mul_strictfp: // fall through
2180         case lir_mul: __ mulss(lreg, raddr);  break;
2181         case lir_div_strictfp: // fall through
2182         case lir_div: __ divss(lreg, raddr);  break;
2183         default: ShouldNotReachHere();
2184       }
2185     }
2186 
2187   } else if (left->is_double_xmm()) {
2188     assert(left == dest, "left and dest must be equal");
2189 
2190     XMMRegister lreg = left->as_xmm_double_reg();
2191     if (right->is_double_xmm()) {
2192       XMMRegister rreg = right->as_xmm_double_reg();
2193       switch (code) {
2194         case lir_add: __ addsd(lreg, rreg);  break;
2195         case lir_sub: __ subsd(lreg, rreg);  break;
2196         case lir_mul_strictfp: // fall through
2197         case lir_mul: __ mulsd(lreg, rreg);  break;
2198         case lir_div_strictfp: // fall through
2199         case lir_div: __ divsd(lreg, rreg);  break;
2200         default: ShouldNotReachHere();
2201       }
2202     } else {
2203       Address raddr;
2204       if (right->is_double_stack()) {
2205         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2206       } else if (right->is_constant()) {
2207         // hack for now
2208         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2209       } else {
2210         ShouldNotReachHere();
2211       }
2212       switch (code) {
2213         case lir_add: __ addsd(lreg, raddr);  break;
2214         case lir_sub: __ subsd(lreg, raddr);  break;
2215         case lir_mul_strictfp: // fall through
2216         case lir_mul: __ mulsd(lreg, raddr);  break;
2217         case lir_div_strictfp: // fall through
2218         case lir_div: __ divsd(lreg, raddr);  break;
2219         default: ShouldNotReachHere();
2220       }
2221     }
2222 
2223   } else if (left->is_single_fpu()) {
2224     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2225 
2226     if (right->is_single_fpu()) {
2227       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2228 
2229     } else {
2230       assert(left->fpu_regnr() == 0, "left must be on TOS");
2231       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2232 
2233       Address raddr;
2234       if (right->is_single_stack()) {
2235         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2236       } else if (right->is_constant()) {
2237         address const_addr = float_constant(right->as_jfloat());
2238         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2239         // hack for now
2240         raddr = __ as_Address(InternalAddress(const_addr));
2241       } else {
2242         ShouldNotReachHere();
2243       }
2244 
2245       switch (code) {
2246         case lir_add: __ fadd_s(raddr); break;
2247         case lir_sub: __ fsub_s(raddr); break;
2248         case lir_mul_strictfp: // fall through
2249         case lir_mul: __ fmul_s(raddr); break;
2250         case lir_div_strictfp: // fall through
2251         case lir_div: __ fdiv_s(raddr); break;
2252         default:      ShouldNotReachHere();
2253       }
2254     }
2255 
2256   } else if (left->is_double_fpu()) {
2257     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2258 
2259     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2260       // Double values require special handling for strictfp mul/div on x86
2261       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2262       __ fmulp(left->fpu_regnrLo() + 1);
2263     }
2264 
2265     if (right->is_double_fpu()) {
2266       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2267 
2268     } else {
2269       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2270       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2271 
2272       Address raddr;
2273       if (right->is_double_stack()) {
2274         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2275       } else if (right->is_constant()) {
2276         // hack for now
2277         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2278       } else {
2279         ShouldNotReachHere();
2280       }
2281 
2282       switch (code) {
2283         case lir_add: __ fadd_d(raddr); break;
2284         case lir_sub: __ fsub_d(raddr); break;
2285         case lir_mul_strictfp: // fall through
2286         case lir_mul: __ fmul_d(raddr); break;
2287         case lir_div_strictfp: // fall through
2288         case lir_div: __ fdiv_d(raddr); break;
2289         default: ShouldNotReachHere();
2290       }
2291     }
2292 
2293     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2294       // Double values require special handling for strictfp mul/div on x86
2295       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2296       __ fmulp(dest->fpu_regnrLo() + 1);
2297     }
2298 
2299   } else if (left->is_single_stack() || left->is_address()) {
2300     assert(left == dest, "left and dest must be equal");
2301 
2302     Address laddr;
2303     if (left->is_single_stack()) {
2304       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2305     } else if (left->is_address()) {
2306       laddr = as_Address(left->as_address_ptr());
2307     } else {
2308       ShouldNotReachHere();
2309     }
2310 
2311     if (right->is_single_cpu()) {
2312       Register rreg = right->as_register();
2313       switch (code) {
2314         case lir_add: __ addl(laddr, rreg); break;
2315         case lir_sub: __ subl(laddr, rreg); break;
2316         default:      ShouldNotReachHere();
2317       }
2318     } else if (right->is_constant()) {
2319       jint c = right->as_constant_ptr()->as_jint();
2320       switch (code) {
2321         case lir_add: {
2322           __ incrementl(laddr, c);
2323           break;
2324         }
2325         case lir_sub: {
2326           __ decrementl(laddr, c);
2327           break;
2328         }
2329         default: ShouldNotReachHere();
2330       }
2331     } else {
2332       ShouldNotReachHere();
2333     }
2334 
2335   } else {
2336     ShouldNotReachHere();
2337   }
2338 }
2339 
2340 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2341   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2342   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2343   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2344 
2345   bool left_is_tos = (left_index == 0);
2346   bool dest_is_tos = (dest_index == 0);
2347   int non_tos_index = (left_is_tos ? right_index : left_index);
2348 
2349   switch (code) {
2350     case lir_add:
2351       if (pop_fpu_stack)       __ faddp(non_tos_index);
2352       else if (dest_is_tos)    __ fadd (non_tos_index);
2353       else                     __ fadda(non_tos_index);
2354       break;
2355 
2356     case lir_sub:
2357       if (left_is_tos) {
2358         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2359         else if (dest_is_tos)  __ fsub  (non_tos_index);
2360         else                   __ fsubra(non_tos_index);
2361       } else {
2362         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2363         else if (dest_is_tos)  __ fsubr (non_tos_index);
2364         else                   __ fsuba (non_tos_index);
2365       }
2366       break;
2367 
2368     case lir_mul_strictfp: // fall through
2369     case lir_mul:
2370       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2371       else if (dest_is_tos)    __ fmul (non_tos_index);
2372       else                     __ fmula(non_tos_index);
2373       break;
2374 
2375     case lir_div_strictfp: // fall through
2376     case lir_div:
2377       if (left_is_tos) {
2378         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2379         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2380         else                   __ fdivra(non_tos_index);
2381       } else {
2382         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2383         else if (dest_is_tos)  __ fdivr (non_tos_index);
2384         else                   __ fdiva (non_tos_index);
2385       }
2386       break;
2387 
2388     case lir_rem:
2389       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2390       __ fremr(noreg);
2391       break;
2392 
2393     default:
2394       ShouldNotReachHere();
2395   }
2396 }
2397 
2398 
2399 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2400   if (value->is_double_xmm()) {
2401     switch(code) {
2402       case lir_abs :
2403         {
2404 #ifdef _LP64
2405           if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2406             assert(tmp->is_valid(), "need temporary");
2407             __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2408           } else
2409 #endif
2410           {
2411             if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2412               __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2413             }
2414             assert(!tmp->is_valid(), "do not need temporary");
2415             __ andpd(dest->as_xmm_double_reg(),
2416                      ExternalAddress((address)double_signmask_pool));
2417           }
2418         }
2419         break;
2420 
2421       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2422       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2423       default      : ShouldNotReachHere();
2424     }
2425 
2426   } else if (value->is_double_fpu()) {
2427     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2428     switch(code) {
2429       case lir_abs   : __ fabs() ; break;
2430       case lir_sqrt  : __ fsqrt(); break;
2431       default      : ShouldNotReachHere();
2432     }
2433   } else {
2434     Unimplemented();
2435   }
2436 }
2437 
2438 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2439   // assert(left->destroys_register(), "check");
2440   if (left->is_single_cpu()) {
2441     Register reg = left->as_register();
2442     if (right->is_constant()) {
2443       int val = right->as_constant_ptr()->as_jint();
2444       switch (code) {
2445         case lir_logic_and: __ andl (reg, val); break;
2446         case lir_logic_or:  __ orl  (reg, val); break;
2447         case lir_logic_xor: __ xorl (reg, val); break;
2448         default: ShouldNotReachHere();
2449       }
2450     } else if (right->is_stack()) {
2451       // added support for stack operands
2452       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2453       switch (code) {
2454         case lir_logic_and: __ andl (reg, raddr); break;
2455         case lir_logic_or:  __ orl  (reg, raddr); break;
2456         case lir_logic_xor: __ xorl (reg, raddr); break;
2457         default: ShouldNotReachHere();
2458       }
2459     } else {
2460       Register rright = right->as_register();
2461       switch (code) {
2462         case lir_logic_and: __ andptr (reg, rright); break;
2463         case lir_logic_or : __ orptr  (reg, rright); break;
2464         case lir_logic_xor: __ xorptr (reg, rright); break;
2465         default: ShouldNotReachHere();
2466       }
2467     }
2468     move_regs(reg, dst->as_register());
2469   } else {
2470     Register l_lo = left->as_register_lo();
2471     Register l_hi = left->as_register_hi();
2472     if (right->is_constant()) {
2473 #ifdef _LP64
2474       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2475       switch (code) {
2476         case lir_logic_and:
2477           __ andq(l_lo, rscratch1);
2478           break;
2479         case lir_logic_or:
2480           __ orq(l_lo, rscratch1);
2481           break;
2482         case lir_logic_xor:
2483           __ xorq(l_lo, rscratch1);
2484           break;
2485         default: ShouldNotReachHere();
2486       }
2487 #else
2488       int r_lo = right->as_constant_ptr()->as_jint_lo();
2489       int r_hi = right->as_constant_ptr()->as_jint_hi();
2490       switch (code) {
2491         case lir_logic_and:
2492           __ andl(l_lo, r_lo);
2493           __ andl(l_hi, r_hi);
2494           break;
2495         case lir_logic_or:
2496           __ orl(l_lo, r_lo);
2497           __ orl(l_hi, r_hi);
2498           break;
2499         case lir_logic_xor:
2500           __ xorl(l_lo, r_lo);
2501           __ xorl(l_hi, r_hi);
2502           break;
2503         default: ShouldNotReachHere();
2504       }
2505 #endif // _LP64
2506     } else {
2507 #ifdef _LP64
2508       Register r_lo;
2509       if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2510         r_lo = right->as_register();
2511       } else {
2512         r_lo = right->as_register_lo();
2513       }
2514 #else
2515       Register r_lo = right->as_register_lo();
2516       Register r_hi = right->as_register_hi();
2517       assert(l_lo != r_hi, "overwriting registers");
2518 #endif
2519       switch (code) {
2520         case lir_logic_and:
2521           __ andptr(l_lo, r_lo);
2522           NOT_LP64(__ andptr(l_hi, r_hi);)
2523           break;
2524         case lir_logic_or:
2525           __ orptr(l_lo, r_lo);
2526           NOT_LP64(__ orptr(l_hi, r_hi);)
2527           break;
2528         case lir_logic_xor:
2529           __ xorptr(l_lo, r_lo);
2530           NOT_LP64(__ xorptr(l_hi, r_hi);)
2531           break;
2532         default: ShouldNotReachHere();
2533       }
2534     }
2535 
2536     Register dst_lo = dst->as_register_lo();
2537     Register dst_hi = dst->as_register_hi();
2538 
2539 #ifdef _LP64
2540     move_regs(l_lo, dst_lo);
2541 #else
2542     if (dst_lo == l_hi) {
2543       assert(dst_hi != l_lo, "overwriting registers");
2544       move_regs(l_hi, dst_hi);
2545       move_regs(l_lo, dst_lo);
2546     } else {
2547       assert(dst_lo != l_hi, "overwriting registers");
2548       move_regs(l_lo, dst_lo);
2549       move_regs(l_hi, dst_hi);
2550     }
2551 #endif // _LP64
2552   }
2553 }
2554 
2555 
2556 // we assume that rax, and rdx can be overwritten
2557 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2558 
2559   assert(left->is_single_cpu(),   "left must be register");
2560   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2561   assert(result->is_single_cpu(), "result must be register");
2562 
2563   //  assert(left->destroys_register(), "check");
2564   //  assert(right->destroys_register(), "check");
2565 
2566   Register lreg = left->as_register();
2567   Register dreg = result->as_register();
2568 
2569   if (right->is_constant()) {
2570     jint divisor = right->as_constant_ptr()->as_jint();
2571     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2572     if (code == lir_idiv) {
2573       assert(lreg == rax, "must be rax,");
2574       assert(temp->as_register() == rdx, "tmp register must be rdx");
2575       __ cdql(); // sign extend into rdx:rax
2576       if (divisor == 2) {
2577         __ subl(lreg, rdx);
2578       } else {
2579         __ andl(rdx, divisor - 1);
2580         __ addl(lreg, rdx);
2581       }
2582       __ sarl(lreg, log2_jint(divisor));
2583       move_regs(lreg, dreg);
2584     } else if (code == lir_irem) {
2585       Label done;
2586       __ mov(dreg, lreg);
2587       __ andl(dreg, 0x80000000 | (divisor - 1));
2588       __ jcc(Assembler::positive, done);
2589       __ decrement(dreg);
2590       __ orl(dreg, ~(divisor - 1));
2591       __ increment(dreg);
2592       __ bind(done);
2593     } else {
2594       ShouldNotReachHere();
2595     }
2596   } else {
2597     Register rreg = right->as_register();
2598     assert(lreg == rax, "left register must be rax,");
2599     assert(rreg != rdx, "right register must not be rdx");
2600     assert(temp->as_register() == rdx, "tmp register must be rdx");
2601 
2602     move_regs(lreg, rax);
2603 
2604     int idivl_offset = __ corrected_idivl(rreg);
2605     if (ImplicitDiv0Checks) {
2606       add_debug_info_for_div0(idivl_offset, info);
2607     }
2608     if (code == lir_irem) {
2609       move_regs(rdx, dreg); // result is in rdx
2610     } else {
2611       move_regs(rax, dreg);
2612     }
2613   }
2614 }
2615 
2616 
2617 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2618   if (opr1->is_single_cpu()) {
2619     Register reg1 = opr1->as_register();
2620     if (opr2->is_single_cpu()) {
2621       // cpu register - cpu register
2622       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2623         __ cmpoop(reg1, opr2->as_register());
2624       } else {
2625         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2626         __ cmpl(reg1, opr2->as_register());
2627       }
2628     } else if (opr2->is_stack()) {
2629       // cpu register - stack
2630       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2631         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2632       } else {
2633         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2634       }
2635     } else if (opr2->is_constant()) {
2636       // cpu register - constant
2637       LIR_Const* c = opr2->as_constant_ptr();
2638       if (c->type() == T_INT) {
2639         __ cmpl(reg1, c->as_jint());
2640       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2641         // In 64bit oops are single register
2642         jobject o = c->as_jobject();
2643         if (o == NULL) {
2644           __ cmpptr(reg1, (int32_t)NULL_WORD);
2645         } else {
2646           __ cmpoop(reg1, o);
2647         }
2648       } else {
2649         fatal("unexpected type: %s", basictype_to_str(c->type()));
2650       }
2651       // cpu register - address
2652     } else if (opr2->is_address()) {
2653       if (op->info() != NULL) {
2654         add_debug_info_for_null_check_here(op->info());
2655       }
2656       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2657     } else {
2658       ShouldNotReachHere();
2659     }
2660 
2661   } else if(opr1->is_double_cpu()) {
2662     Register xlo = opr1->as_register_lo();
2663     Register xhi = opr1->as_register_hi();
2664     if (opr2->is_double_cpu()) {
2665 #ifdef _LP64
2666       __ cmpptr(xlo, opr2->as_register_lo());
2667 #else
2668       // cpu register - cpu register
2669       Register ylo = opr2->as_register_lo();
2670       Register yhi = opr2->as_register_hi();
2671       __ subl(xlo, ylo);
2672       __ sbbl(xhi, yhi);
2673       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2674         __ orl(xhi, xlo);
2675       }
2676 #endif // _LP64
2677     } else if (opr2->is_constant()) {
2678       // cpu register - constant 0
2679       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2680 #ifdef _LP64
2681       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2682 #else
2683       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2684       __ orl(xhi, xlo);
2685 #endif // _LP64
2686     } else {
2687       ShouldNotReachHere();
2688     }
2689 
2690   } else if (opr1->is_single_xmm()) {
2691     XMMRegister reg1 = opr1->as_xmm_float_reg();
2692     if (opr2->is_single_xmm()) {
2693       // xmm register - xmm register
2694       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2695     } else if (opr2->is_stack()) {
2696       // xmm register - stack
2697       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2698     } else if (opr2->is_constant()) {
2699       // xmm register - constant
2700       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2701     } else if (opr2->is_address()) {
2702       // xmm register - address
2703       if (op->info() != NULL) {
2704         add_debug_info_for_null_check_here(op->info());
2705       }
2706       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2707     } else {
2708       ShouldNotReachHere();
2709     }
2710 
2711   } else if (opr1->is_double_xmm()) {
2712     XMMRegister reg1 = opr1->as_xmm_double_reg();
2713     if (opr2->is_double_xmm()) {
2714       // xmm register - xmm register
2715       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2716     } else if (opr2->is_stack()) {
2717       // xmm register - stack
2718       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2719     } else if (opr2->is_constant()) {
2720       // xmm register - constant
2721       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2722     } else if (opr2->is_address()) {
2723       // xmm register - address
2724       if (op->info() != NULL) {
2725         add_debug_info_for_null_check_here(op->info());
2726       }
2727       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2728     } else {
2729       ShouldNotReachHere();
2730     }
2731 
2732   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2733     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2734     assert(opr2->is_fpu_register(), "both must be registers");
2735     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2736 
2737   } else if (opr1->is_address() && opr2->is_constant()) {
2738     LIR_Const* c = opr2->as_constant_ptr();
2739 #ifdef _LP64
2740     if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2741       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2742       __ movoop(rscratch1, c->as_jobject());
2743     }
2744 #endif // LP64
2745     if (op->info() != NULL) {
2746       add_debug_info_for_null_check_here(op->info());
2747     }
2748     // special case: address - constant
2749     LIR_Address* addr = opr1->as_address_ptr();
2750     if (c->type() == T_INT) {
2751       __ cmpl(as_Address(addr), c->as_jint());
2752     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2753 #ifdef _LP64
2754       // %%% Make this explode if addr isn't reachable until we figure out a
2755       // better strategy by giving noreg as the temp for as_Address
2756       __ cmpoop(rscratch1, as_Address(addr, noreg));
2757 #else
2758       __ cmpoop(as_Address(addr), c->as_jobject());
2759 #endif // _LP64
2760     } else {
2761       ShouldNotReachHere();
2762     }
2763 
2764   } else {
2765     ShouldNotReachHere();
2766   }
2767 }
2768 
2769 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2770   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2771     if (left->is_single_xmm()) {
2772       assert(right->is_single_xmm(), "must match");
2773       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2774     } else if (left->is_double_xmm()) {
2775       assert(right->is_double_xmm(), "must match");
2776       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2777 
2778     } else {
2779       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2780       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2781 
2782       assert(left->fpu() == 0, "left must be on TOS");
2783       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2784                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2785     }
2786   } else {
2787     assert(code == lir_cmp_l2i, "check");
2788 #ifdef _LP64
2789     Label done;
2790     Register dest = dst->as_register();
2791     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2792     __ movl(dest, -1);
2793     __ jccb(Assembler::less, done);
2794     __ set_byte_if_not_zero(dest);
2795     __ movzbl(dest, dest);
2796     __ bind(done);
2797 #else
2798     __ lcmp2int(left->as_register_hi(),
2799                 left->as_register_lo(),
2800                 right->as_register_hi(),
2801                 right->as_register_lo());
2802     move_regs(left->as_register_hi(), dst->as_register());
2803 #endif // _LP64
2804   }
2805 }
2806 
2807 
2808 void LIR_Assembler::align_call(LIR_Code code) {
2809   if (os::is_MP()) {
2810     // make sure that the displacement word of the call ends up word aligned
2811     int offset = __ offset();
2812     switch (code) {
2813       case lir_static_call:
2814       case lir_optvirtual_call:
2815       case lir_dynamic_call:
2816         offset += NativeCall::displacement_offset;
2817         break;
2818       case lir_icvirtual_call:
2819         offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2820       break;
2821       case lir_virtual_call:  // currently, sparc-specific for niagara
2822       default: ShouldNotReachHere();
2823     }
2824     __ align(BytesPerWord, offset);
2825   }
2826 }
2827 
2828 
2829 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2830   assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2831          "must be aligned");
2832   __ call(AddressLiteral(op->addr(), rtype));
2833   add_call_info(code_offset(), op->info());
2834 }
2835 
2836 
2837 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2838   __ ic_call(op->addr());
2839   add_call_info(code_offset(), op->info());
2840   assert(!os::is_MP() ||
2841          (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2842          "must be aligned");
2843 }
2844 
2845 
2846 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2847 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2848   ShouldNotReachHere();
2849 }
2850 
2851 
2852 void LIR_Assembler::emit_static_call_stub() {
2853   address call_pc = __ pc();
2854   address stub = __ start_a_stub(call_stub_size());
2855   if (stub == NULL) {
2856     bailout("static call stub overflow");
2857     return;
2858   }
2859 
2860   int start = __ offset();
2861   if (os::is_MP()) {
2862     // make sure that the displacement word of the call ends up word aligned
2863     __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2864   }
2865   __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2866   __ mov_metadata(rbx, (Metadata*)NULL);
2867   // must be set to -1 at code generation time
2868   assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2869   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2870   __ jump(RuntimeAddress(__ pc()));
2871 
2872   if (UseAOT) {
2873     // Trampoline to aot code
2874     __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2875 #ifdef _LP64
2876     __ mov64(rax, CONST64(0));  // address is zapped till fixup time.
2877 #else
2878     __ movl(rax, 0xdeadffff);  // address is zapped till fixup time.
2879 #endif
2880     __ jmp(rax);
2881   }
2882   assert(__ offset() - start <= call_stub_size(), "stub too big");
2883   __ end_a_stub();
2884 }
2885 
2886 
2887 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2888   assert(exceptionOop->as_register() == rax, "must match");
2889   assert(exceptionPC->as_register() == rdx, "must match");
2890 
2891   // exception object is not added to oop map by LinearScan
2892   // (LinearScan assumes that no oops are in fixed registers)
2893   info->add_register_oop(exceptionOop);
2894   Runtime1::StubID unwind_id;
2895 
2896   // get current pc information
2897   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2898   int pc_for_athrow_offset = __ offset();
2899   InternalAddress pc_for_athrow(__ pc());
2900   __ lea(exceptionPC->as_register(), pc_for_athrow);
2901   add_call_info(pc_for_athrow_offset, info); // for exception handler
2902 
2903   __ verify_not_null_oop(rax);
2904   // search an exception handler (rax: exception oop, rdx: throwing pc)
2905   if (compilation()->has_fpu_code()) {
2906     unwind_id = Runtime1::handle_exception_id;
2907   } else {
2908     unwind_id = Runtime1::handle_exception_nofpu_id;
2909   }
2910   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2911 
2912   // enough room for two byte trap
2913   __ nop();
2914 }
2915 
2916 
2917 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2918   assert(exceptionOop->as_register() == rax, "must match");
2919 
2920   __ jmp(_unwind_handler_entry);
2921 }
2922 
2923 
2924 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2925 
2926   // optimized version for linear scan:
2927   // * count must be already in ECX (guaranteed by LinearScan)
2928   // * left and dest must be equal
2929   // * tmp must be unused
2930   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2931   assert(left == dest, "left and dest must be equal");
2932   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2933 
2934   if (left->is_single_cpu()) {
2935     Register value = left->as_register();
2936     assert(value != SHIFT_count, "left cannot be ECX");
2937 
2938     switch (code) {
2939       case lir_shl:  __ shll(value); break;
2940       case lir_shr:  __ sarl(value); break;
2941       case lir_ushr: __ shrl(value); break;
2942       default: ShouldNotReachHere();
2943     }
2944   } else if (left->is_double_cpu()) {
2945     Register lo = left->as_register_lo();
2946     Register hi = left->as_register_hi();
2947     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2948 #ifdef _LP64
2949     switch (code) {
2950       case lir_shl:  __ shlptr(lo);        break;
2951       case lir_shr:  __ sarptr(lo);        break;
2952       case lir_ushr: __ shrptr(lo);        break;
2953       default: ShouldNotReachHere();
2954     }
2955 #else
2956 
2957     switch (code) {
2958       case lir_shl:  __ lshl(hi, lo);        break;
2959       case lir_shr:  __ lshr(hi, lo, true);  break;
2960       case lir_ushr: __ lshr(hi, lo, false); break;
2961       default: ShouldNotReachHere();
2962     }
2963 #endif // LP64
2964   } else {
2965     ShouldNotReachHere();
2966   }
2967 }
2968 
2969 
2970 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2971   if (dest->is_single_cpu()) {
2972     // first move left into dest so that left is not destroyed by the shift
2973     Register value = dest->as_register();
2974     count = count & 0x1F; // Java spec
2975 
2976     move_regs(left->as_register(), value);
2977     switch (code) {
2978       case lir_shl:  __ shll(value, count); break;
2979       case lir_shr:  __ sarl(value, count); break;
2980       case lir_ushr: __ shrl(value, count); break;
2981       default: ShouldNotReachHere();
2982     }
2983   } else if (dest->is_double_cpu()) {
2984 #ifndef _LP64
2985     Unimplemented();
2986 #else
2987     // first move left into dest so that left is not destroyed by the shift
2988     Register value = dest->as_register_lo();
2989     count = count & 0x1F; // Java spec
2990 
2991     move_regs(left->as_register_lo(), value);
2992     switch (code) {
2993       case lir_shl:  __ shlptr(value, count); break;
2994       case lir_shr:  __ sarptr(value, count); break;
2995       case lir_ushr: __ shrptr(value, count); break;
2996       default: ShouldNotReachHere();
2997     }
2998 #endif // _LP64
2999   } else {
3000     ShouldNotReachHere();
3001   }
3002 }
3003 
3004 
3005 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3006   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3007   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3008   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3009   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3010 }
3011 
3012 
3013 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3014   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3015   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3016   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3017   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3018 }
3019 
3020 
3021 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
3022   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3023   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3024   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3025   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3026 }
3027 
3028 
3029 void LIR_Assembler::store_parameter(Metadata* m,  int offset_from_rsp_in_words) {
3030   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3031   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3032   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3033   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3034 }
3035 
3036 
3037 // This code replaces a call to arraycopy; no exception may
3038 // be thrown in this code, they must be thrown in the System.arraycopy
3039 // activation frame; we could save some checks if this would not be the case
3040 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3041   ciArrayKlass* default_type = op->expected_type();
3042   Register src = op->src()->as_register();
3043   Register dst = op->dst()->as_register();
3044   Register src_pos = op->src_pos()->as_register();
3045   Register dst_pos = op->dst_pos()->as_register();
3046   Register length  = op->length()->as_register();
3047   Register tmp = op->tmp()->as_register();
3048 
3049   CodeStub* stub = op->stub();
3050   int flags = op->flags();
3051   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3052   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3053 
3054   // if we don't know anything, just go through the generic arraycopy
3055   if (default_type == NULL) {
3056     Label done;
3057     // save outgoing arguments on stack in case call to System.arraycopy is needed
3058     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3059     // for interpreter calling conventions. Now we have to do it in new style conventions.
3060     // For the moment until C1 gets the new register allocator I just force all the
3061     // args to the right place (except the register args) and then on the back side
3062     // reload the register args properly if we go slow path. Yuck
3063 
3064     // These are proper for the calling convention
3065     store_parameter(length, 2);
3066     store_parameter(dst_pos, 1);
3067     store_parameter(dst, 0);
3068 
3069     // these are just temporary placements until we need to reload
3070     store_parameter(src_pos, 3);
3071     store_parameter(src, 4);
3072     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3073 
3074     address copyfunc_addr = StubRoutines::generic_arraycopy();
3075     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3076 
3077     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3078 #ifdef _LP64
3079     // The arguments are in java calling convention so we can trivially shift them to C
3080     // convention
3081     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3082     __ mov(c_rarg0, j_rarg0);
3083     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3084     __ mov(c_rarg1, j_rarg1);
3085     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3086     __ mov(c_rarg2, j_rarg2);
3087     assert_different_registers(c_rarg3, j_rarg4);
3088     __ mov(c_rarg3, j_rarg3);
3089 #ifdef _WIN64
3090     // Allocate abi space for args but be sure to keep stack aligned
3091     __ subptr(rsp, 6*wordSize);
3092     store_parameter(j_rarg4, 4);
3093 #ifndef PRODUCT
3094     if (PrintC1Statistics) {
3095       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3096     }
3097 #endif
3098     __ call(RuntimeAddress(copyfunc_addr));
3099     __ addptr(rsp, 6*wordSize);
3100 #else
3101     __ mov(c_rarg4, j_rarg4);
3102 #ifndef PRODUCT
3103     if (PrintC1Statistics) {
3104       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3105     }
3106 #endif
3107     __ call(RuntimeAddress(copyfunc_addr));
3108 #endif // _WIN64
3109 #else
3110     __ push(length);
3111     __ push(dst_pos);
3112     __ push(dst);
3113     __ push(src_pos);
3114     __ push(src);
3115 
3116 #ifndef PRODUCT
3117     if (PrintC1Statistics) {
3118       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3119     }
3120 #endif
3121     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3122 
3123 #endif // _LP64
3124 
3125     __ cmpl(rax, 0);
3126     __ jcc(Assembler::equal, *stub->continuation());
3127 
3128     __ mov(tmp, rax);
3129     __ xorl(tmp, -1);
3130 
3131     // Reload values from the stack so they are where the stub
3132     // expects them.
3133     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3134     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3135     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3136     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3137     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3138 
3139     __ subl(length, tmp);
3140     __ addl(src_pos, tmp);
3141     __ addl(dst_pos, tmp);
3142     __ jmp(*stub->entry());
3143 
3144     __ bind(*stub->continuation());
3145     return;
3146   }
3147 
3148   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3149 
3150   int elem_size = type2aelembytes(basic_type);
3151   Address::ScaleFactor scale;
3152 
3153   switch (elem_size) {
3154     case 1 :
3155       scale = Address::times_1;
3156       break;
3157     case 2 :
3158       scale = Address::times_2;
3159       break;
3160     case 4 :
3161       scale = Address::times_4;
3162       break;
3163     case 8 :
3164       scale = Address::times_8;
3165       break;
3166     default:
3167       scale = Address::no_scale;
3168       ShouldNotReachHere();
3169   }
3170 
3171   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3172   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3173   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3174   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3175 
3176   // length and pos's are all sign extended at this point on 64bit
3177 
3178   // test for NULL
3179   if (flags & LIR_OpArrayCopy::src_null_check) {
3180     __ testptr(src, src);
3181     __ jcc(Assembler::zero, *stub->entry());
3182   }
3183   if (flags & LIR_OpArrayCopy::dst_null_check) {
3184     __ testptr(dst, dst);
3185     __ jcc(Assembler::zero, *stub->entry());
3186   }
3187 
3188   // If the compiler was not able to prove that exact type of the source or the destination
3189   // of the arraycopy is an array type, check at runtime if the source or the destination is
3190   // an instance type.
3191   if (flags & LIR_OpArrayCopy::type_check) {
3192     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3193       __ load_klass(tmp, dst);
3194       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3195       __ jcc(Assembler::greaterEqual, *stub->entry());
3196     }
3197 
3198     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3199       __ load_klass(tmp, src);
3200       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3201       __ jcc(Assembler::greaterEqual, *stub->entry());
3202     }
3203   }
3204 
3205   // check if negative
3206   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3207     __ testl(src_pos, src_pos);
3208     __ jcc(Assembler::less, *stub->entry());
3209   }
3210   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3211     __ testl(dst_pos, dst_pos);
3212     __ jcc(Assembler::less, *stub->entry());
3213   }
3214 
3215   if (flags & LIR_OpArrayCopy::src_range_check) {
3216     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3217     __ cmpl(tmp, src_length_addr);
3218     __ jcc(Assembler::above, *stub->entry());
3219   }
3220   if (flags & LIR_OpArrayCopy::dst_range_check) {
3221     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3222     __ cmpl(tmp, dst_length_addr);
3223     __ jcc(Assembler::above, *stub->entry());
3224   }
3225 
3226   if (flags & LIR_OpArrayCopy::length_positive_check) {
3227     __ testl(length, length);
3228     __ jcc(Assembler::less, *stub->entry());
3229   }
3230 
3231 #ifdef _LP64
3232   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3233   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3234 #endif
3235 
3236   if (flags & LIR_OpArrayCopy::type_check) {
3237     // We don't know the array types are compatible
3238     if (basic_type != T_OBJECT) {
3239       // Simple test for basic type arrays
3240       if (UseCompressedClassPointers) {
3241         __ movl(tmp, src_klass_addr);
3242         __ cmpl(tmp, dst_klass_addr);
3243       } else {
3244         __ movptr(tmp, src_klass_addr);
3245         __ cmpptr(tmp, dst_klass_addr);
3246       }
3247       __ jcc(Assembler::notEqual, *stub->entry());
3248     } else {
3249       // For object arrays, if src is a sub class of dst then we can
3250       // safely do the copy.
3251       Label cont, slow;
3252 
3253       __ push(src);
3254       __ push(dst);
3255 
3256       __ load_klass(src, src);
3257       __ load_klass(dst, dst);
3258 
3259       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3260 
3261       __ push(src);
3262       __ push(dst);
3263       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3264       __ pop(dst);
3265       __ pop(src);
3266 
3267       __ cmpl(src, 0);
3268       __ jcc(Assembler::notEqual, cont);
3269 
3270       __ bind(slow);
3271       __ pop(dst);
3272       __ pop(src);
3273 
3274       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3275       if (copyfunc_addr != NULL) { // use stub if available
3276         // src is not a sub class of dst so we have to do a
3277         // per-element check.
3278 
3279         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3280         if ((flags & mask) != mask) {
3281           // Check that at least both of them object arrays.
3282           assert(flags & mask, "one of the two should be known to be an object array");
3283 
3284           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3285             __ load_klass(tmp, src);
3286           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3287             __ load_klass(tmp, dst);
3288           }
3289           int lh_offset = in_bytes(Klass::layout_helper_offset());
3290           Address klass_lh_addr(tmp, lh_offset);
3291           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3292           __ cmpl(klass_lh_addr, objArray_lh);
3293           __ jcc(Assembler::notEqual, *stub->entry());
3294         }
3295 
3296        // Spill because stubs can use any register they like and it's
3297        // easier to restore just those that we care about.
3298        store_parameter(dst, 0);
3299        store_parameter(dst_pos, 1);
3300        store_parameter(length, 2);
3301        store_parameter(src_pos, 3);
3302        store_parameter(src, 4);
3303 
3304 #ifndef _LP64
3305         __ movptr(tmp, dst_klass_addr);
3306         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3307         __ push(tmp);
3308         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3309         __ push(tmp);
3310         __ push(length);
3311         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3312         __ push(tmp);
3313         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3314         __ push(tmp);
3315 
3316         __ call_VM_leaf(copyfunc_addr, 5);
3317 #else
3318         __ movl2ptr(length, length); //higher 32bits must be null
3319 
3320         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3321         assert_different_registers(c_rarg0, dst, dst_pos, length);
3322         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3323         assert_different_registers(c_rarg1, dst, length);
3324 
3325         __ mov(c_rarg2, length);
3326         assert_different_registers(c_rarg2, dst);
3327 
3328 #ifdef _WIN64
3329         // Allocate abi space for args but be sure to keep stack aligned
3330         __ subptr(rsp, 6*wordSize);
3331         __ load_klass(c_rarg3, dst);
3332         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3333         store_parameter(c_rarg3, 4);
3334         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3335         __ call(RuntimeAddress(copyfunc_addr));
3336         __ addptr(rsp, 6*wordSize);
3337 #else
3338         __ load_klass(c_rarg4, dst);
3339         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3340         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3341         __ call(RuntimeAddress(copyfunc_addr));
3342 #endif
3343 
3344 #endif
3345 
3346 #ifndef PRODUCT
3347         if (PrintC1Statistics) {
3348           Label failed;
3349           __ testl(rax, rax);
3350           __ jcc(Assembler::notZero, failed);
3351           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3352           __ bind(failed);
3353         }
3354 #endif
3355 
3356         __ testl(rax, rax);
3357         __ jcc(Assembler::zero, *stub->continuation());
3358 
3359 #ifndef PRODUCT
3360         if (PrintC1Statistics) {
3361           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3362         }
3363 #endif
3364 
3365         __ mov(tmp, rax);
3366 
3367         __ xorl(tmp, -1);
3368 
3369         // Restore previously spilled arguments
3370         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3371         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3372         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3373         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3374         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3375 
3376 
3377         __ subl(length, tmp);
3378         __ addl(src_pos, tmp);
3379         __ addl(dst_pos, tmp);
3380       }
3381 
3382       __ jmp(*stub->entry());
3383 
3384       __ bind(cont);
3385       __ pop(dst);
3386       __ pop(src);
3387     }
3388   }
3389 
3390 #ifdef ASSERT
3391   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3392     // Sanity check the known type with the incoming class.  For the
3393     // primitive case the types must match exactly with src.klass and
3394     // dst.klass each exactly matching the default type.  For the
3395     // object array case, if no type check is needed then either the
3396     // dst type is exactly the expected type and the src type is a
3397     // subtype which we can't check or src is the same array as dst
3398     // but not necessarily exactly of type default_type.
3399     Label known_ok, halt;
3400     __ mov_metadata(tmp, default_type->constant_encoding());
3401 #ifdef _LP64
3402     if (UseCompressedClassPointers) {
3403       __ encode_klass_not_null(tmp);
3404     }
3405 #endif
3406 
3407     if (basic_type != T_OBJECT) {
3408 
3409       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3410       else                   __ cmpptr(tmp, dst_klass_addr);
3411       __ jcc(Assembler::notEqual, halt);
3412       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3413       else                   __ cmpptr(tmp, src_klass_addr);
3414       __ jcc(Assembler::equal, known_ok);
3415     } else {
3416       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3417       else                   __ cmpptr(tmp, dst_klass_addr);
3418       __ jcc(Assembler::equal, known_ok);
3419       __ cmpptr(src, dst);
3420       __ jcc(Assembler::equal, known_ok);
3421     }
3422     __ bind(halt);
3423     __ stop("incorrect type information in arraycopy");
3424     __ bind(known_ok);
3425   }
3426 #endif
3427 
3428 #ifndef PRODUCT
3429   if (PrintC1Statistics) {
3430     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3431   }
3432 #endif
3433 
3434 #ifdef _LP64
3435   assert_different_registers(c_rarg0, dst, dst_pos, length);
3436   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3437   assert_different_registers(c_rarg1, length);
3438   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3439   __ mov(c_rarg2, length);
3440 
3441 #else
3442   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3443   store_parameter(tmp, 0);
3444   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3445   store_parameter(tmp, 1);
3446   store_parameter(length, 2);
3447 #endif // _LP64
3448 
3449   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3450   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3451   const char *name;
3452   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3453   __ call_VM_leaf(entry, 0);
3454 
3455   __ bind(*stub->continuation());
3456 }
3457 
3458 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3459   assert(op->crc()->is_single_cpu(),  "crc must be register");
3460   assert(op->val()->is_single_cpu(),  "byte value must be register");
3461   assert(op->result_opr()->is_single_cpu(), "result must be register");
3462   Register crc = op->crc()->as_register();
3463   Register val = op->val()->as_register();
3464   Register res = op->result_opr()->as_register();
3465 
3466   assert_different_registers(val, crc, res);
3467 
3468   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3469   __ notl(crc); // ~crc
3470   __ update_byte_crc32(crc, val, res);
3471   __ notl(crc); // ~crc
3472   __ mov(res, crc);
3473 }
3474 
3475 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3476   Register obj = op->obj_opr()->as_register();  // may not be an oop
3477   Register hdr = op->hdr_opr()->as_register();
3478   Register lock = op->lock_opr()->as_register();
3479   if (!UseFastLocking) {
3480     __ jmp(*op->stub()->entry());
3481   } else if (op->code() == lir_lock) {
3482     Register scratch = noreg;
3483     if (UseBiasedLocking) {
3484       scratch = op->scratch_opr()->as_register();
3485     }
3486     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3487     // add debug info for NullPointerException only if one is possible
3488     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3489     if (op->info() != NULL) {
3490       add_debug_info_for_null_check(null_check_offset, op->info());
3491     }
3492     // done
3493   } else if (op->code() == lir_unlock) {
3494     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3495     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3496   } else {
3497     Unimplemented();
3498   }
3499   __ bind(*op->stub()->continuation());
3500 }
3501 
3502 
3503 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3504   ciMethod* method = op->profiled_method();
3505   int bci          = op->profiled_bci();
3506   ciMethod* callee = op->profiled_callee();
3507 
3508   // Update counter for all call types
3509   ciMethodData* md = method->method_data_or_null();
3510   assert(md != NULL, "Sanity");
3511   ciProfileData* data = md->bci_to_data(bci);
3512   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3513   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3514   Register mdo  = op->mdo()->as_register();
3515   __ mov_metadata(mdo, md->constant_encoding());
3516   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3517   // Perform additional virtual call profiling for invokevirtual and
3518   // invokeinterface bytecodes
3519   if (op->should_profile_receiver_type()) {
3520     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3521     Register recv = op->recv()->as_register();
3522     assert_different_registers(mdo, recv);
3523     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3524     ciKlass* known_klass = op->known_holder();
3525     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3526       // We know the type that will be seen at this call site; we can
3527       // statically update the MethodData* rather than needing to do
3528       // dynamic tests on the receiver type
3529 
3530       // NOTE: we should probably put a lock around this search to
3531       // avoid collisions by concurrent compilations
3532       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3533       uint i;
3534       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3535         ciKlass* receiver = vc_data->receiver(i);
3536         if (known_klass->equals(receiver)) {
3537           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3538           __ addptr(data_addr, DataLayout::counter_increment);
3539           return;
3540         }
3541       }
3542 
3543       // Receiver type not found in profile data; select an empty slot
3544 
3545       // Note that this is less efficient than it should be because it
3546       // always does a write to the receiver part of the
3547       // VirtualCallData rather than just the first time
3548       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3549         ciKlass* receiver = vc_data->receiver(i);
3550         if (receiver == NULL) {
3551           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3552           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3553           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3554           __ addptr(data_addr, DataLayout::counter_increment);
3555           return;
3556         }
3557       }
3558     } else {
3559       __ load_klass(recv, recv);
3560       Label update_done;
3561       type_profile_helper(mdo, md, data, recv, &update_done);
3562       // Receiver did not match any saved receiver and there is no empty row for it.
3563       // Increment total counter to indicate polymorphic case.
3564       __ addptr(counter_addr, DataLayout::counter_increment);
3565 
3566       __ bind(update_done);
3567     }
3568   } else {
3569     // Static call
3570     __ addptr(counter_addr, DataLayout::counter_increment);
3571   }
3572 }
3573 
3574 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3575   Register obj = op->obj()->as_register();
3576   Register tmp = op->tmp()->as_pointer_register();
3577   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3578   ciKlass* exact_klass = op->exact_klass();
3579   intptr_t current_klass = op->current_klass();
3580   bool not_null = op->not_null();
3581   bool no_conflict = op->no_conflict();
3582 
3583   Label update, next, none;
3584 
3585   bool do_null = !not_null;
3586   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3587   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3588 
3589   assert(do_null || do_update, "why are we here?");
3590   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3591 
3592   __ verify_oop(obj);
3593 
3594   if (tmp != obj) {
3595     __ mov(tmp, obj);
3596   }
3597   if (do_null) {
3598     __ testptr(tmp, tmp);
3599     __ jccb(Assembler::notZero, update);
3600     if (!TypeEntries::was_null_seen(current_klass)) {
3601       __ orptr(mdo_addr, TypeEntries::null_seen);
3602     }
3603     if (do_update) {
3604 #ifndef ASSERT
3605       __ jmpb(next);
3606     }
3607 #else
3608       __ jmp(next);
3609     }
3610   } else {
3611     __ testptr(tmp, tmp);
3612     __ jccb(Assembler::notZero, update);
3613     __ stop("unexpect null obj");
3614 #endif
3615   }
3616 
3617   __ bind(update);
3618 
3619   if (do_update) {
3620 #ifdef ASSERT
3621     if (exact_klass != NULL) {
3622       Label ok;
3623       __ load_klass(tmp, tmp);
3624       __ push(tmp);
3625       __ mov_metadata(tmp, exact_klass->constant_encoding());
3626       __ cmpptr(tmp, Address(rsp, 0));
3627       __ jccb(Assembler::equal, ok);
3628       __ stop("exact klass and actual klass differ");
3629       __ bind(ok);
3630       __ pop(tmp);
3631     }
3632 #endif
3633     if (!no_conflict) {
3634       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3635         if (exact_klass != NULL) {
3636           __ mov_metadata(tmp, exact_klass->constant_encoding());
3637         } else {
3638           __ load_klass(tmp, tmp);
3639         }
3640 
3641         __ xorptr(tmp, mdo_addr);
3642         __ testptr(tmp, TypeEntries::type_klass_mask);
3643         // klass seen before, nothing to do. The unknown bit may have been
3644         // set already but no need to check.
3645         __ jccb(Assembler::zero, next);
3646 
3647         __ testptr(tmp, TypeEntries::type_unknown);
3648         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3649 
3650         if (TypeEntries::is_type_none(current_klass)) {
3651           __ cmpptr(mdo_addr, 0);
3652           __ jccb(Assembler::equal, none);
3653           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3654           __ jccb(Assembler::equal, none);
3655           // There is a chance that the checks above (re-reading profiling
3656           // data from memory) fail if another thread has just set the
3657           // profiling to this obj's klass
3658           __ xorptr(tmp, mdo_addr);
3659           __ testptr(tmp, TypeEntries::type_klass_mask);
3660           __ jccb(Assembler::zero, next);
3661         }
3662       } else {
3663         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3664                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3665 
3666         __ movptr(tmp, mdo_addr);
3667         __ testptr(tmp, TypeEntries::type_unknown);
3668         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3669       }
3670 
3671       // different than before. Cannot keep accurate profile.
3672       __ orptr(mdo_addr, TypeEntries::type_unknown);
3673 
3674       if (TypeEntries::is_type_none(current_klass)) {
3675         __ jmpb(next);
3676 
3677         __ bind(none);
3678         // first time here. Set profile type.
3679         __ movptr(mdo_addr, tmp);
3680       }
3681     } else {
3682       // There's a single possible klass at this profile point
3683       assert(exact_klass != NULL, "should be");
3684       if (TypeEntries::is_type_none(current_klass)) {
3685         __ mov_metadata(tmp, exact_klass->constant_encoding());
3686         __ xorptr(tmp, mdo_addr);
3687         __ testptr(tmp, TypeEntries::type_klass_mask);
3688 #ifdef ASSERT
3689         __ jcc(Assembler::zero, next);
3690 
3691         {
3692           Label ok;
3693           __ push(tmp);
3694           __ cmpptr(mdo_addr, 0);
3695           __ jcc(Assembler::equal, ok);
3696           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3697           __ jcc(Assembler::equal, ok);
3698           // may have been set by another thread
3699           __ mov_metadata(tmp, exact_klass->constant_encoding());
3700           __ xorptr(tmp, mdo_addr);
3701           __ testptr(tmp, TypeEntries::type_mask);
3702           __ jcc(Assembler::zero, ok);
3703 
3704           __ stop("unexpected profiling mismatch");
3705           __ bind(ok);
3706           __ pop(tmp);
3707         }
3708 #else
3709         __ jccb(Assembler::zero, next);
3710 #endif
3711         // first time here. Set profile type.
3712         __ movptr(mdo_addr, tmp);
3713       } else {
3714         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3715                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3716 
3717         __ movptr(tmp, mdo_addr);
3718         __ testptr(tmp, TypeEntries::type_unknown);
3719         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3720 
3721         __ orptr(mdo_addr, TypeEntries::type_unknown);
3722       }
3723     }
3724 
3725     __ bind(next);
3726   }
3727 }
3728 
3729 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3730   Unimplemented();
3731 }
3732 
3733 
3734 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3735   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3736 }
3737 
3738 
3739 void LIR_Assembler::align_backward_branch_target() {
3740   __ align(BytesPerWord);
3741 }
3742 
3743 
3744 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3745   if (left->is_single_cpu()) {
3746     __ negl(left->as_register());
3747     move_regs(left->as_register(), dest->as_register());
3748 
3749   } else if (left->is_double_cpu()) {
3750     Register lo = left->as_register_lo();
3751 #ifdef _LP64
3752     Register dst = dest->as_register_lo();
3753     __ movptr(dst, lo);
3754     __ negptr(dst);
3755 #else
3756     Register hi = left->as_register_hi();
3757     __ lneg(hi, lo);
3758     if (dest->as_register_lo() == hi) {
3759       assert(dest->as_register_hi() != lo, "destroying register");
3760       move_regs(hi, dest->as_register_hi());
3761       move_regs(lo, dest->as_register_lo());
3762     } else {
3763       move_regs(lo, dest->as_register_lo());
3764       move_regs(hi, dest->as_register_hi());
3765     }
3766 #endif // _LP64
3767 
3768   } else if (dest->is_single_xmm()) {
3769 #ifdef _LP64
3770     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3771       assert(tmp->is_valid(), "need temporary");
3772       assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3773       __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3774     }
3775     else
3776 #endif
3777     {
3778       assert(!tmp->is_valid(), "do not need temporary");
3779       if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3780         __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3781       }
3782       __ xorps(dest->as_xmm_float_reg(),
3783                ExternalAddress((address)float_signflip_pool));
3784     }
3785   } else if (dest->is_double_xmm()) {
3786 #ifdef _LP64
3787     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3788       assert(tmp->is_valid(), "need temporary");
3789       assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3790       __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3791     }
3792     else
3793 #endif
3794     {
3795       assert(!tmp->is_valid(), "do not need temporary");
3796       if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3797         __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3798       }
3799       __ xorpd(dest->as_xmm_double_reg(),
3800                ExternalAddress((address)double_signflip_pool));
3801     }
3802   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3803     assert(left->fpu() == 0, "arg must be on TOS");
3804     assert(dest->fpu() == 0, "dest must be TOS");
3805     __ fchs();
3806 
3807   } else {
3808     ShouldNotReachHere();
3809   }
3810 }
3811 
3812 
3813 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3814   assert(src->is_address(), "must be an address");
3815   assert(dest->is_register(), "must be a register");
3816 
3817   PatchingStub* patch = NULL;
3818   if (patch_code != lir_patch_none) {
3819     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3820   }
3821 
3822   Register reg = dest->as_pointer_register();
3823   LIR_Address* addr = src->as_address_ptr();
3824   __ lea(reg, as_Address(addr));
3825 
3826   if (patch != NULL) {
3827     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3828   }
3829 }
3830 
3831 
3832 
3833 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3834   assert(!tmp->is_valid(), "don't need temporary");
3835   __ call(RuntimeAddress(dest));
3836   if (info != NULL) {
3837     add_call_info_here(info);
3838   }
3839 }
3840 
3841 
3842 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3843   assert(type == T_LONG, "only for volatile long fields");
3844 
3845   if (info != NULL) {
3846     add_debug_info_for_null_check_here(info);
3847   }
3848 
3849   if (src->is_double_xmm()) {
3850     if (dest->is_double_cpu()) {
3851 #ifdef _LP64
3852       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3853 #else
3854       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3855       __ psrlq(src->as_xmm_double_reg(), 32);
3856       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3857 #endif // _LP64
3858     } else if (dest->is_double_stack()) {
3859       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3860     } else if (dest->is_address()) {
3861       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3862     } else {
3863       ShouldNotReachHere();
3864     }
3865 
3866   } else if (dest->is_double_xmm()) {
3867     if (src->is_double_stack()) {
3868       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3869     } else if (src->is_address()) {
3870       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3871     } else {
3872       ShouldNotReachHere();
3873     }
3874 
3875   } else if (src->is_double_fpu()) {
3876     assert(src->fpu_regnrLo() == 0, "must be TOS");
3877     if (dest->is_double_stack()) {
3878       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3879     } else if (dest->is_address()) {
3880       __ fistp_d(as_Address(dest->as_address_ptr()));
3881     } else {
3882       ShouldNotReachHere();
3883     }
3884 
3885   } else if (dest->is_double_fpu()) {
3886     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3887     if (src->is_double_stack()) {
3888       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3889     } else if (src->is_address()) {
3890       __ fild_d(as_Address(src->as_address_ptr()));
3891     } else {
3892       ShouldNotReachHere();
3893     }
3894   } else {
3895     ShouldNotReachHere();
3896   }
3897 }
3898 
3899 #ifdef ASSERT
3900 // emit run-time assertion
3901 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3902   assert(op->code() == lir_assert, "must be");
3903 
3904   if (op->in_opr1()->is_valid()) {
3905     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3906     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3907   } else {
3908     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3909     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3910   }
3911 
3912   Label ok;
3913   if (op->condition() != lir_cond_always) {
3914     Assembler::Condition acond = Assembler::zero;
3915     switch (op->condition()) {
3916       case lir_cond_equal:        acond = Assembler::equal;       break;
3917       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3918       case lir_cond_less:         acond = Assembler::less;        break;
3919       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3920       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3921       case lir_cond_greater:      acond = Assembler::greater;     break;
3922       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3923       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3924       default:                    ShouldNotReachHere();
3925     }
3926     __ jcc(acond, ok);
3927   }
3928   if (op->halt()) {
3929     const char* str = __ code_string(op->msg());
3930     __ stop(str);
3931   } else {
3932     breakpoint();
3933   }
3934   __ bind(ok);
3935 }
3936 #endif
3937 
3938 void LIR_Assembler::membar() {
3939   // QQQ sparc TSO uses this,
3940   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3941 }
3942 
3943 void LIR_Assembler::membar_acquire() {
3944   // No x86 machines currently require load fences
3945 }
3946 
3947 void LIR_Assembler::membar_release() {
3948   // No x86 machines currently require store fences
3949 }
3950 
3951 void LIR_Assembler::membar_loadload() {
3952   // no-op
3953   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3954 }
3955 
3956 void LIR_Assembler::membar_storestore() {
3957   // no-op
3958   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3959 }
3960 
3961 void LIR_Assembler::membar_loadstore() {
3962   // no-op
3963   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3964 }
3965 
3966 void LIR_Assembler::membar_storeload() {
3967   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3968 }
3969 
3970 void LIR_Assembler::on_spin_wait() {
3971   __ pause ();
3972 }
3973 
3974 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3975   assert(result_reg->is_register(), "check");
3976 #ifdef _LP64
3977   // __ get_thread(result_reg->as_register_lo());
3978   __ mov(result_reg->as_register(), r15_thread);
3979 #else
3980   __ get_thread(result_reg->as_register());
3981 #endif // _LP64
3982 }
3983 
3984 
3985 void LIR_Assembler::peephole(LIR_List*) {
3986   // do nothing for now
3987 }
3988 
3989 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3990   assert(data == dest, "xchg/xadd uses only 2 operands");
3991 
3992   if (data->type() == T_INT) {
3993     if (code == lir_xadd) {
3994       if (os::is_MP()) {
3995         __ lock();
3996       }
3997       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3998     } else {
3999       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4000     }
4001   } else if (data->is_oop()) {
4002     assert (code == lir_xchg, "xadd for oops");
4003     Register obj = data->as_register();
4004 #ifdef _LP64
4005     if (UseCompressedOops) {
4006       __ encode_heap_oop(obj);
4007       __ xchgl(obj, as_Address(src->as_address_ptr()));
4008       __ decode_heap_oop(obj);
4009     } else {
4010       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4011     }
4012 #else
4013     __ xchgl(obj, as_Address(src->as_address_ptr()));
4014 #endif
4015   } else if (data->type() == T_LONG) {
4016 #ifdef _LP64
4017     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4018     if (code == lir_xadd) {
4019       if (os::is_MP()) {
4020         __ lock();
4021       }
4022       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4023     } else {
4024       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4025     }
4026 #else
4027     ShouldNotReachHere();
4028 #endif
4029   } else {
4030     ShouldNotReachHere();
4031   }
4032 }
4033 
4034 #undef __