1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableBarrierSet.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "nativeInst_x86.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "vmreg_x86.inline.hpp"
  44 
  45 
  46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  47 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  48 // fast versions of NegF/NegD and AbsF/AbsD.
  49 
  50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  52   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  53   // of 128-bits operands for SSE instructions.
  54   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  55   // Store the value to a 128-bits operand.
  56   operand[0] = lo;
  57   operand[1] = hi;
  58   return operand;
  59 }
  60 
  61 // Buffer for 128-bits masks used by SSE instructions.
  62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  63 
  64 // Static initialization during VM startup.
  65 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  67 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  69 
  70 
  71 NEEDS_CLEANUP // remove this definitions ?
  72 const Register IC_Klass    = rax;   // where the IC klass is cached
  73 const Register SYNC_header = rax;   // synchronization header
  74 const Register SHIFT_count = rcx;   // where count for shift operations must be
  75 
  76 #define __ _masm->
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2) {
  83   if (tmp1 == preserve) {
  84     assert_different_registers(tmp1, tmp2, extra);
  85     tmp1 = extra;
  86   } else if (tmp2 == preserve) {
  87     assert_different_registers(tmp1, tmp2, extra);
  88     tmp2 = extra;
  89   }
  90   assert_different_registers(preserve, tmp1, tmp2);
  91 }
  92 
  93 
  94 
  95 static void select_different_registers(Register preserve,
  96                                        Register extra,
  97                                        Register &tmp1,
  98                                        Register &tmp2,
  99                                        Register &tmp3) {
 100   if (tmp1 == preserve) {
 101     assert_different_registers(tmp1, tmp2, tmp3, extra);
 102     tmp1 = extra;
 103   } else if (tmp2 == preserve) {
 104     assert_different_registers(tmp1, tmp2, tmp3, extra);
 105     tmp2 = extra;
 106   } else if (tmp3 == preserve) {
 107     assert_different_registers(tmp1, tmp2, tmp3, extra);
 108     tmp3 = extra;
 109   }
 110   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 111 }
 112 
 113 
 114 
 115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 116   if (opr->is_constant()) {
 117     LIR_Const* constant = opr->as_constant_ptr();
 118     switch (constant->type()) {
 119       case T_INT: {
 120         return true;
 121       }
 122 
 123       default:
 124         return false;
 125     }
 126   }
 127   return false;
 128 }
 129 
 130 
 131 LIR_Opr LIR_Assembler::receiverOpr() {
 132   return FrameMap::receiver_opr;
 133 }
 134 
 135 LIR_Opr LIR_Assembler::osrBufferPointer() {
 136   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 137 }
 138 
 139 //--------------fpu register translations-----------------------
 140 
 141 
 142 address LIR_Assembler::float_constant(float f) {
 143   address const_addr = __ float_constant(f);
 144   if (const_addr == NULL) {
 145     bailout("const section overflow");
 146     return __ code()->consts()->start();
 147   } else {
 148     return const_addr;
 149   }
 150 }
 151 
 152 
 153 address LIR_Assembler::double_constant(double d) {
 154   address const_addr = __ double_constant(d);
 155   if (const_addr == NULL) {
 156     bailout("const section overflow");
 157     return __ code()->consts()->start();
 158   } else {
 159     return const_addr;
 160   }
 161 }
 162 
 163 
 164 void LIR_Assembler::set_24bit_FPU() {
 165   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 166 }
 167 
 168 void LIR_Assembler::reset_FPU() {
 169   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 170 }
 171 
 172 void LIR_Assembler::fpop() {
 173   __ fpop();
 174 }
 175 
 176 void LIR_Assembler::fxch(int i) {
 177   __ fxch(i);
 178 }
 179 
 180 void LIR_Assembler::fld(int i) {
 181   __ fld_s(i);
 182 }
 183 
 184 void LIR_Assembler::ffree(int i) {
 185   __ ffree(i);
 186 }
 187 
 188 void LIR_Assembler::breakpoint() {
 189   __ int3();
 190 }
 191 
 192 void LIR_Assembler::push(LIR_Opr opr) {
 193   if (opr->is_single_cpu()) {
 194     __ push_reg(opr->as_register());
 195   } else if (opr->is_double_cpu()) {
 196     NOT_LP64(__ push_reg(opr->as_register_hi()));
 197     __ push_reg(opr->as_register_lo());
 198   } else if (opr->is_stack()) {
 199     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 200   } else if (opr->is_constant()) {
 201     LIR_Const* const_opr = opr->as_constant_ptr();
 202     if (const_opr->type() == T_OBJECT) {
 203       __ push_oop(const_opr->as_jobject());
 204     } else if (const_opr->type() == T_INT) {
 205       __ push_jint(const_opr->as_jint());
 206     } else {
 207       ShouldNotReachHere();
 208     }
 209 
 210   } else {
 211     ShouldNotReachHere();
 212   }
 213 }
 214 
 215 void LIR_Assembler::pop(LIR_Opr opr) {
 216   if (opr->is_single_cpu()) {
 217     __ pop_reg(opr->as_register());
 218   } else {
 219     ShouldNotReachHere();
 220   }
 221 }
 222 
 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 224   return addr->base()->is_illegal() && addr->index()->is_illegal();
 225 }
 226 
 227 //-------------------------------------------
 228 
 229 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 230   return as_Address(addr, rscratch1);
 231 }
 232 
 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 234   if (addr->base()->is_illegal()) {
 235     assert(addr->index()->is_illegal(), "must be illegal too");
 236     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 237     if (! __ reachable(laddr)) {
 238       __ movptr(tmp, laddr.addr());
 239       Address res(tmp, 0);
 240       return res;
 241     } else {
 242       return __ as_Address(laddr);
 243     }
 244   }
 245 
 246   Register base = addr->base()->as_pointer_register();
 247 
 248   if (addr->index()->is_illegal()) {
 249     return Address( base, addr->disp());
 250   } else if (addr->index()->is_cpu_register()) {
 251     Register index = addr->index()->as_pointer_register();
 252     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 253   } else if (addr->index()->is_constant()) {
 254     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 255     assert(Assembler::is_simm32(addr_offset), "must be");
 256 
 257     return Address(base, addr_offset);
 258   } else {
 259     Unimplemented();
 260     return Address();
 261   }
 262 }
 263 
 264 
 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 266   Address base = as_Address(addr);
 267   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 268 }
 269 
 270 
 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 272   return as_Address(addr);
 273 }
 274 
 275 
 276 void LIR_Assembler::osr_entry() {
 277   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 278   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 279   ValueStack* entry_state = osr_entry->state();
 280   int number_of_locks = entry_state->locks_size();
 281 
 282   // we jump here if osr happens with the interpreter
 283   // state set up to continue at the beginning of the
 284   // loop that triggered osr - in particular, we have
 285   // the following registers setup:
 286   //
 287   // rcx: osr buffer
 288   //
 289 
 290   // build frame
 291   ciMethod* m = compilation()->method();
 292   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 293 
 294   // OSR buffer is
 295   //
 296   // locals[nlocals-1..0]
 297   // monitors[0..number_of_locks]
 298   //
 299   // locals is a direct copy of the interpreter frame so in the osr buffer
 300   // so first slot in the local array is the last local from the interpreter
 301   // and last slot is local[0] (receiver) from the interpreter
 302   //
 303   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 304   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 305   // in the interpreter frame (the method lock if a sync method)
 306 
 307   // Initialize monitors in the compiled activation.
 308   //   rcx: pointer to osr buffer
 309   //
 310   // All other registers are dead at this point and the locals will be
 311   // copied into place by code emitted in the IR.
 312 
 313   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 314   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 315     int monitor_offset = BytesPerWord * method()->max_locals() +
 316       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 317     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 318     // the OSR buffer using 2 word entries: first the lock and then
 319     // the oop.
 320     for (int i = 0; i < number_of_locks; i++) {
 321       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 322 #ifdef ASSERT
 323       // verify the interpreter's monitor has a non-null object
 324       {
 325         Label L;
 326         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 327         __ jcc(Assembler::notZero, L);
 328         __ stop("locked object is NULL");
 329         __ bind(L);
 330       }
 331 #endif
 332       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 333       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 334       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 335       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 336     }
 337   }
 338 }
 339 
 340 
 341 // inline cache check; done before the frame is built.
 342 int LIR_Assembler::check_icache() {
 343   Register receiver = FrameMap::receiver_opr->as_register();
 344   Register ic_klass = IC_Klass;
 345   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 346   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 347   if (!do_post_padding) {
 348     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 349     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 350   }
 351   int offset = __ offset();
 352   __ inline_cache_check(receiver, IC_Klass);
 353   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 354   if (do_post_padding) {
 355     // force alignment after the cache check.
 356     // It's been verified to be aligned if !VerifyOops
 357     __ align(CodeEntryAlignment);
 358   }
 359   return offset;
 360 }
 361 
 362 
 363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 364   jobject o = NULL;
 365   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 366   __ movoop(reg, o);
 367   patching_epilog(patch, lir_patch_normal, reg, info);
 368 }
 369 
 370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 371   Metadata* o = NULL;
 372   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 373   __ mov_metadata(reg, o);
 374   patching_epilog(patch, lir_patch_normal, reg, info);
 375 }
 376 
 377 // This specifies the rsp decrement needed to build the frame
 378 int LIR_Assembler::initial_frame_size_in_bytes() const {
 379   // if rounding, must let FrameMap know!
 380 
 381   // The frame_map records size in slots (32bit word)
 382 
 383   // subtract two words to account for return address and link
 384   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 385 }
 386 
 387 
 388 int LIR_Assembler::emit_exception_handler() {
 389   // if the last instruction is a call (typically to do a throw which
 390   // is coming at the end after block reordering) the return address
 391   // must still point into the code area in order to avoid assertion
 392   // failures when searching for the corresponding bci => add a nop
 393   // (was bug 5/14/1999 - gri)
 394   __ nop();
 395 
 396   // generate code for exception handler
 397   address handler_base = __ start_a_stub(exception_handler_size());
 398   if (handler_base == NULL) {
 399     // not enough space left for the handler
 400     bailout("exception handler overflow");
 401     return -1;
 402   }
 403 
 404   int offset = code_offset();
 405 
 406   // the exception oop and pc are in rax, and rdx
 407   // no other registers need to be preserved, so invalidate them
 408   __ invalidate_registers(false, true, true, false, true, true);
 409 
 410   // check that there is really an exception
 411   __ verify_not_null_oop(rax);
 412 
 413   // search an exception handler (rax: exception oop, rdx: throwing pc)
 414   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 415   __ should_not_reach_here();
 416   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 417   __ end_a_stub();
 418 
 419   return offset;
 420 }
 421 
 422 
 423 // Emit the code to remove the frame from the stack in the exception
 424 // unwind path.
 425 int LIR_Assembler::emit_unwind_handler() {
 426 #ifndef PRODUCT
 427   if (CommentedAssembly) {
 428     _masm->block_comment("Unwind handler");
 429   }
 430 #endif
 431 
 432   int offset = code_offset();
 433 
 434   // Fetch the exception from TLS and clear out exception related thread state
 435   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 436   NOT_LP64(__ get_thread(rsi));
 437   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 438   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 439   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 440 
 441   __ bind(_unwind_handler_entry);
 442   __ verify_not_null_oop(rax);
 443   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 444     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 445   }
 446 
 447   // Preform needed unlocking
 448   MonitorExitStub* stub = NULL;
 449   if (method()->is_synchronized()) {
 450     monitor_address(0, FrameMap::rax_opr);
 451     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 452     __ unlock_object(rdi, rsi, rax, *stub->entry());
 453     __ bind(*stub->continuation());
 454   }
 455 
 456   if (compilation()->env()->dtrace_method_probes()) {
 457 #ifdef _LP64
 458     __ mov(rdi, r15_thread);
 459     __ mov_metadata(rsi, method()->constant_encoding());
 460 #else
 461     __ get_thread(rax);
 462     __ movptr(Address(rsp, 0), rax);
 463     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 464 #endif
 465     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 466   }
 467 
 468   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 469     __ mov(rax, rbx);  // Restore the exception
 470   }
 471 
 472   // remove the activation and dispatch to the unwind handler
 473   __ remove_frame(initial_frame_size_in_bytes());
 474   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 475 
 476   // Emit the slow path assembly
 477   if (stub != NULL) {
 478     stub->emit_code(this);
 479   }
 480 
 481   return offset;
 482 }
 483 
 484 
 485 int LIR_Assembler::emit_deopt_handler() {
 486   // if the last instruction is a call (typically to do a throw which
 487   // is coming at the end after block reordering) the return address
 488   // must still point into the code area in order to avoid assertion
 489   // failures when searching for the corresponding bci => add a nop
 490   // (was bug 5/14/1999 - gri)
 491   __ nop();
 492 
 493   // generate code for exception handler
 494   address handler_base = __ start_a_stub(deopt_handler_size());
 495   if (handler_base == NULL) {
 496     // not enough space left for the handler
 497     bailout("deopt handler overflow");
 498     return -1;
 499   }
 500 
 501   int offset = code_offset();
 502   InternalAddress here(__ pc());
 503 
 504   __ pushptr(here.addr());
 505   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 506   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 507   __ end_a_stub();
 508 
 509   return offset;
 510 }
 511 
 512 
 513 void LIR_Assembler::return_op(LIR_Opr result) {
 514   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 515   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 516     assert(result->fpu() == 0, "result must already be on TOS");
 517   }
 518 
 519   // Pop the stack before the safepoint code
 520   __ remove_frame(initial_frame_size_in_bytes());
 521 
 522   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 523     __ reserved_stack_check();
 524   }
 525 
 526   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 527 
 528   // Note: we do not need to round double result; float result has the right precision
 529   // the poll sets the condition code, but no data registers
 530 
 531   if (SafepointMechanism::uses_thread_local_poll()) {
 532 #ifdef _LP64
 533     const Register poll_addr = rscratch1;
 534     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 535 #else
 536     const Register poll_addr = rbx;
 537     assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
 538     __ get_thread(poll_addr);
 539     __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
 540 #endif
 541     __ relocate(relocInfo::poll_return_type);
 542     __ testl(rax, Address(poll_addr, 0));
 543   } else {
 544     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
 545 
 546     if (Assembler::is_polling_page_far()) {
 547       __ lea(rscratch1, polling_page);
 548       __ relocate(relocInfo::poll_return_type);
 549       __ testl(rax, Address(rscratch1, 0));
 550     } else {
 551       __ testl(rax, polling_page);
 552     }
 553   }
 554   __ ret(0);
 555 }
 556 
 557 
 558 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 559   guarantee(info != NULL, "Shouldn't be NULL");
 560   int offset = __ offset();
 561   if (SafepointMechanism::uses_thread_local_poll()) {
 562 #ifdef _LP64
 563     const Register poll_addr = rscratch1;
 564     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 565 #else
 566     assert(tmp->is_cpu_register(), "needed");
 567     const Register poll_addr = tmp->as_register();
 568     __ get_thread(poll_addr);
 569     __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
 570 #endif
 571     add_debug_info_for_branch(info);
 572     __ relocate(relocInfo::poll_type);
 573     address pre_pc = __ pc();
 574     __ testl(rax, Address(poll_addr, 0));
 575     address post_pc = __ pc();
 576     guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 577   } else {
 578     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
 579     if (Assembler::is_polling_page_far()) {
 580       __ lea(rscratch1, polling_page);
 581       offset = __ offset();
 582       add_debug_info_for_branch(info);
 583       __ relocate(relocInfo::poll_type);
 584       __ testl(rax, Address(rscratch1, 0));
 585     } else {
 586       add_debug_info_for_branch(info);
 587       __ testl(rax, polling_page);
 588     }
 589   }
 590   return offset;
 591 }
 592 
 593 
 594 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 595   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 596 }
 597 
 598 void LIR_Assembler::swap_reg(Register a, Register b) {
 599   __ xchgptr(a, b);
 600 }
 601 
 602 
 603 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 604   assert(src->is_constant(), "should not call otherwise");
 605   assert(dest->is_register(), "should not call otherwise");
 606   LIR_Const* c = src->as_constant_ptr();
 607 
 608   switch (c->type()) {
 609     case T_INT: {
 610       assert(patch_code == lir_patch_none, "no patching handled here");
 611       __ movl(dest->as_register(), c->as_jint());
 612       break;
 613     }
 614 
 615     case T_ADDRESS: {
 616       assert(patch_code == lir_patch_none, "no patching handled here");
 617       __ movptr(dest->as_register(), c->as_jint());
 618       break;
 619     }
 620 
 621     case T_LONG: {
 622       assert(patch_code == lir_patch_none, "no patching handled here");
 623 #ifdef _LP64
 624       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 625 #else
 626       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 627       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 628 #endif // _LP64
 629       break;
 630     }
 631 
 632     case T_OBJECT: {
 633       if (patch_code != lir_patch_none) {
 634         jobject2reg_with_patching(dest->as_register(), info);
 635       } else {
 636         __ movoop(dest->as_register(), c->as_jobject());
 637       }
 638       break;
 639     }
 640 
 641     case T_METADATA: {
 642       if (patch_code != lir_patch_none) {
 643         klass2reg_with_patching(dest->as_register(), info);
 644       } else {
 645         __ mov_metadata(dest->as_register(), c->as_metadata());
 646       }
 647       break;
 648     }
 649 
 650     case T_FLOAT: {
 651       if (dest->is_single_xmm()) {
 652         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
 653           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 654         } else {
 655           __ movflt(dest->as_xmm_float_reg(),
 656                    InternalAddress(float_constant(c->as_jfloat())));
 657         }
 658       } else {
 659         assert(dest->is_single_fpu(), "must be");
 660         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 661         if (c->is_zero_float()) {
 662           __ fldz();
 663         } else if (c->is_one_float()) {
 664           __ fld1();
 665         } else {
 666           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 667         }
 668       }
 669       break;
 670     }
 671 
 672     case T_DOUBLE: {
 673       if (dest->is_double_xmm()) {
 674         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
 675           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 676         } else {
 677           __ movdbl(dest->as_xmm_double_reg(),
 678                     InternalAddress(double_constant(c->as_jdouble())));
 679         }
 680       } else {
 681         assert(dest->is_double_fpu(), "must be");
 682         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 683         if (c->is_zero_double()) {
 684           __ fldz();
 685         } else if (c->is_one_double()) {
 686           __ fld1();
 687         } else {
 688           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 689         }
 690       }
 691       break;
 692     }
 693 
 694     default:
 695       ShouldNotReachHere();
 696   }
 697 }
 698 
 699 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 700   assert(src->is_constant(), "should not call otherwise");
 701   assert(dest->is_stack(), "should not call otherwise");
 702   LIR_Const* c = src->as_constant_ptr();
 703 
 704   switch (c->type()) {
 705     case T_INT:  // fall through
 706     case T_FLOAT:
 707       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 708       break;
 709 
 710     case T_ADDRESS:
 711       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 712       break;
 713 
 714     case T_OBJECT:
 715       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 716       break;
 717 
 718     case T_LONG:  // fall through
 719     case T_DOUBLE:
 720 #ifdef _LP64
 721       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 722                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 723 #else
 724       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 725                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 726       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 727                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 728 #endif // _LP64
 729       break;
 730 
 731     default:
 732       ShouldNotReachHere();
 733   }
 734 }
 735 
 736 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 737   assert(src->is_constant(), "should not call otherwise");
 738   assert(dest->is_address(), "should not call otherwise");
 739   LIR_Const* c = src->as_constant_ptr();
 740   LIR_Address* addr = dest->as_address_ptr();
 741 
 742   int null_check_here = code_offset();
 743   switch (type) {
 744     case T_INT:    // fall through
 745     case T_FLOAT:
 746       __ movl(as_Address(addr), c->as_jint_bits());
 747       break;
 748 
 749     case T_ADDRESS:
 750       __ movptr(as_Address(addr), c->as_jint_bits());
 751       break;
 752 
 753     case T_OBJECT:  // fall through
 754     case T_ARRAY:
 755       if (c->as_jobject() == NULL) {
 756         if (UseCompressedOops && !wide) {
 757           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 758         } else {
 759 #ifdef _LP64
 760           __ xorptr(rscratch1, rscratch1);
 761           null_check_here = code_offset();
 762           __ movptr(as_Address(addr), rscratch1);
 763 #else
 764           __ movptr(as_Address(addr), NULL_WORD);
 765 #endif
 766         }
 767       } else {
 768         if (is_literal_address(addr)) {
 769           ShouldNotReachHere();
 770           __ movoop(as_Address(addr, noreg), c->as_jobject());
 771         } else {
 772 #ifdef _LP64
 773           __ movoop(rscratch1, c->as_jobject());
 774           if (UseCompressedOops && !wide) {
 775             __ encode_heap_oop(rscratch1);
 776             null_check_here = code_offset();
 777             __ movl(as_Address_lo(addr), rscratch1);
 778           } else {
 779             null_check_here = code_offset();
 780             __ movptr(as_Address_lo(addr), rscratch1);
 781           }
 782 #else
 783           __ movoop(as_Address(addr), c->as_jobject());
 784 #endif
 785         }
 786       }
 787       break;
 788 
 789     case T_LONG:    // fall through
 790     case T_DOUBLE:
 791 #ifdef _LP64
 792       if (is_literal_address(addr)) {
 793         ShouldNotReachHere();
 794         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 795       } else {
 796         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 797         null_check_here = code_offset();
 798         __ movptr(as_Address_lo(addr), r10);
 799       }
 800 #else
 801       // Always reachable in 32bit so this doesn't produce useless move literal
 802       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 803       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 804 #endif // _LP64
 805       break;
 806 
 807     case T_BOOLEAN: // fall through
 808     case T_BYTE:
 809       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 810       break;
 811 
 812     case T_CHAR:    // fall through
 813     case T_SHORT:
 814       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 815       break;
 816 
 817     default:
 818       ShouldNotReachHere();
 819   };
 820 
 821   if (info != NULL) {
 822     add_debug_info_for_null_check(null_check_here, info);
 823   }
 824 }
 825 
 826 
 827 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 828   assert(src->is_register(), "should not call otherwise");
 829   assert(dest->is_register(), "should not call otherwise");
 830 
 831   // move between cpu-registers
 832   if (dest->is_single_cpu()) {
 833 #ifdef _LP64
 834     if (src->type() == T_LONG) {
 835       // Can do LONG -> OBJECT
 836       move_regs(src->as_register_lo(), dest->as_register());
 837       return;
 838     }
 839 #endif
 840     assert(src->is_single_cpu(), "must match");
 841     if (src->type() == T_OBJECT) {
 842       __ verify_oop(src->as_register());
 843     }
 844     move_regs(src->as_register(), dest->as_register());
 845 
 846   } else if (dest->is_double_cpu()) {
 847 #ifdef _LP64
 848     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 849       // Surprising to me but we can see move of a long to t_object
 850       __ verify_oop(src->as_register());
 851       move_regs(src->as_register(), dest->as_register_lo());
 852       return;
 853     }
 854 #endif
 855     assert(src->is_double_cpu(), "must match");
 856     Register f_lo = src->as_register_lo();
 857     Register f_hi = src->as_register_hi();
 858     Register t_lo = dest->as_register_lo();
 859     Register t_hi = dest->as_register_hi();
 860 #ifdef _LP64
 861     assert(f_hi == f_lo, "must be same");
 862     assert(t_hi == t_lo, "must be same");
 863     move_regs(f_lo, t_lo);
 864 #else
 865     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 866 
 867 
 868     if (f_lo == t_hi && f_hi == t_lo) {
 869       swap_reg(f_lo, f_hi);
 870     } else if (f_hi == t_lo) {
 871       assert(f_lo != t_hi, "overwriting register");
 872       move_regs(f_hi, t_hi);
 873       move_regs(f_lo, t_lo);
 874     } else {
 875       assert(f_hi != t_lo, "overwriting register");
 876       move_regs(f_lo, t_lo);
 877       move_regs(f_hi, t_hi);
 878     }
 879 #endif // LP64
 880 
 881     // special moves from fpu-register to xmm-register
 882     // necessary for method results
 883   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 884     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 885     __ fld_s(Address(rsp, 0));
 886   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 887     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 888     __ fld_d(Address(rsp, 0));
 889   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 890     __ fstp_s(Address(rsp, 0));
 891     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 892   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 893     __ fstp_d(Address(rsp, 0));
 894     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 895 
 896     // move between xmm-registers
 897   } else if (dest->is_single_xmm()) {
 898     assert(src->is_single_xmm(), "must match");
 899     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 900   } else if (dest->is_double_xmm()) {
 901     assert(src->is_double_xmm(), "must match");
 902     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 903 
 904     // move between fpu-registers (no instruction necessary because of fpu-stack)
 905   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 906     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 907     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 908   } else {
 909     ShouldNotReachHere();
 910   }
 911 }
 912 
 913 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 914   assert(src->is_register(), "should not call otherwise");
 915   assert(dest->is_stack(), "should not call otherwise");
 916 
 917   if (src->is_single_cpu()) {
 918     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 919     if (type == T_OBJECT || type == T_ARRAY) {
 920       __ verify_oop(src->as_register());
 921       __ movptr (dst, src->as_register());
 922     } else if (type == T_METADATA) {
 923       __ movptr (dst, src->as_register());
 924     } else {
 925       __ movl (dst, src->as_register());
 926     }
 927 
 928   } else if (src->is_double_cpu()) {
 929     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 930     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 931     __ movptr (dstLO, src->as_register_lo());
 932     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 933 
 934   } else if (src->is_single_xmm()) {
 935     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 936     __ movflt(dst_addr, src->as_xmm_float_reg());
 937 
 938   } else if (src->is_double_xmm()) {
 939     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 940     __ movdbl(dst_addr, src->as_xmm_double_reg());
 941 
 942   } else if (src->is_single_fpu()) {
 943     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 944     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 945     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 946     else                   __ fst_s  (dst_addr);
 947 
 948   } else if (src->is_double_fpu()) {
 949     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 950     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 951     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 952     else                   __ fst_d  (dst_addr);
 953 
 954   } else {
 955     ShouldNotReachHere();
 956   }
 957 }
 958 
 959 
 960 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 961   LIR_Address* to_addr = dest->as_address_ptr();
 962   PatchingStub* patch = NULL;
 963   Register compressed_src = rscratch1;
 964 
 965   if (type == T_ARRAY || type == T_OBJECT) {
 966     __ verify_oop(src->as_register());
 967 #ifdef _LP64
 968     if (UseCompressedOops && !wide) {
 969       __ movptr(compressed_src, src->as_register());
 970       __ encode_heap_oop(compressed_src);
 971       if (patch_code != lir_patch_none) {
 972         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
 973       }
 974     }
 975 #endif
 976   }
 977 
 978   if (patch_code != lir_patch_none) {
 979     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 980     Address toa = as_Address(to_addr);
 981     assert(toa.disp() != 0, "must have");
 982   }
 983 
 984   int null_check_here = code_offset();
 985   switch (type) {
 986     case T_FLOAT: {
 987       if (src->is_single_xmm()) {
 988         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
 989       } else {
 990         assert(src->is_single_fpu(), "must be");
 991         assert(src->fpu_regnr() == 0, "argument must be on TOS");
 992         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
 993         else                    __ fst_s (as_Address(to_addr));
 994       }
 995       break;
 996     }
 997 
 998     case T_DOUBLE: {
 999       if (src->is_double_xmm()) {
1000         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1001       } else {
1002         assert(src->is_double_fpu(), "must be");
1003         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1004         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1005         else                    __ fst_d (as_Address(to_addr));
1006       }
1007       break;
1008     }
1009 
1010     case T_ARRAY:   // fall through
1011     case T_OBJECT:  // fall through
1012       if (UseCompressedOops && !wide) {
1013         __ movl(as_Address(to_addr), compressed_src);
1014       } else {
1015         __ movptr(as_Address(to_addr), src->as_register());
1016       }
1017       break;
1018     case T_METADATA:
1019       // We get here to store a method pointer to the stack to pass to
1020       // a dtrace runtime call. This can't work on 64 bit with
1021       // compressed klass ptrs: T_METADATA can be a compressed klass
1022       // ptr or a 64 bit method pointer.
1023       LP64_ONLY(ShouldNotReachHere());
1024       __ movptr(as_Address(to_addr), src->as_register());
1025       break;
1026     case T_ADDRESS:
1027       __ movptr(as_Address(to_addr), src->as_register());
1028       break;
1029     case T_INT:
1030       __ movl(as_Address(to_addr), src->as_register());
1031       break;
1032 
1033     case T_LONG: {
1034       Register from_lo = src->as_register_lo();
1035       Register from_hi = src->as_register_hi();
1036 #ifdef _LP64
1037       __ movptr(as_Address_lo(to_addr), from_lo);
1038 #else
1039       Register base = to_addr->base()->as_register();
1040       Register index = noreg;
1041       if (to_addr->index()->is_register()) {
1042         index = to_addr->index()->as_register();
1043       }
1044       if (base == from_lo || index == from_lo) {
1045         assert(base != from_hi, "can't be");
1046         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1047         __ movl(as_Address_hi(to_addr), from_hi);
1048         if (patch != NULL) {
1049           patching_epilog(patch, lir_patch_high, base, info);
1050           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1051           patch_code = lir_patch_low;
1052         }
1053         __ movl(as_Address_lo(to_addr), from_lo);
1054       } else {
1055         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1056         __ movl(as_Address_lo(to_addr), from_lo);
1057         if (patch != NULL) {
1058           patching_epilog(patch, lir_patch_low, base, info);
1059           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1060           patch_code = lir_patch_high;
1061         }
1062         __ movl(as_Address_hi(to_addr), from_hi);
1063       }
1064 #endif // _LP64
1065       break;
1066     }
1067 
1068     case T_BYTE:    // fall through
1069     case T_BOOLEAN: {
1070       Register src_reg = src->as_register();
1071       Address dst_addr = as_Address(to_addr);
1072       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1073       __ movb(dst_addr, src_reg);
1074       break;
1075     }
1076 
1077     case T_CHAR:    // fall through
1078     case T_SHORT:
1079       __ movw(as_Address(to_addr), src->as_register());
1080       break;
1081 
1082     default:
1083       ShouldNotReachHere();
1084   }
1085   if (info != NULL) {
1086     add_debug_info_for_null_check(null_check_here, info);
1087   }
1088 
1089   if (patch_code != lir_patch_none) {
1090     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1091   }
1092 }
1093 
1094 
1095 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1096   assert(src->is_stack(), "should not call otherwise");
1097   assert(dest->is_register(), "should not call otherwise");
1098 
1099   if (dest->is_single_cpu()) {
1100     if (type == T_ARRAY || type == T_OBJECT) {
1101       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1102       __ verify_oop(dest->as_register());
1103     } else if (type == T_METADATA) {
1104       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1105     } else {
1106       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1107     }
1108 
1109   } else if (dest->is_double_cpu()) {
1110     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1111     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1112     __ movptr(dest->as_register_lo(), src_addr_LO);
1113     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1114 
1115   } else if (dest->is_single_xmm()) {
1116     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1117     __ movflt(dest->as_xmm_float_reg(), src_addr);
1118 
1119   } else if (dest->is_double_xmm()) {
1120     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1121     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1122 
1123   } else if (dest->is_single_fpu()) {
1124     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1125     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1126     __ fld_s(src_addr);
1127 
1128   } else if (dest->is_double_fpu()) {
1129     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1130     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1131     __ fld_d(src_addr);
1132 
1133   } else {
1134     ShouldNotReachHere();
1135   }
1136 }
1137 
1138 
1139 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1140   if (src->is_single_stack()) {
1141     if (type == T_OBJECT || type == T_ARRAY) {
1142       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1143       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1144     } else {
1145 #ifndef _LP64
1146       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1147       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1148 #else
1149       //no pushl on 64bits
1150       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1151       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1152 #endif
1153     }
1154 
1155   } else if (src->is_double_stack()) {
1156 #ifdef _LP64
1157     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1158     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1159 #else
1160     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1161     // push and pop the part at src + wordSize, adding wordSize for the previous push
1162     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1163     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1164     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1165 #endif // _LP64
1166 
1167   } else {
1168     ShouldNotReachHere();
1169   }
1170 }
1171 
1172 
1173 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1174   assert(src->is_address(), "should not call otherwise");
1175   assert(dest->is_register(), "should not call otherwise");
1176 
1177   LIR_Address* addr = src->as_address_ptr();
1178   Address from_addr = as_Address(addr);
1179 
1180   if (addr->base()->type() == T_OBJECT) {
1181     __ verify_oop(addr->base()->as_pointer_register());
1182   }
1183 
1184   switch (type) {
1185     case T_BOOLEAN: // fall through
1186     case T_BYTE:    // fall through
1187     case T_CHAR:    // fall through
1188     case T_SHORT:
1189       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1190         // on pre P6 processors we may get partial register stalls
1191         // so blow away the value of to_rinfo before loading a
1192         // partial word into it.  Do it here so that it precedes
1193         // the potential patch point below.
1194         __ xorptr(dest->as_register(), dest->as_register());
1195       }
1196       break;
1197    default:
1198      break;
1199   }
1200 
1201   PatchingStub* patch = NULL;
1202   if (patch_code != lir_patch_none) {
1203     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1204     assert(from_addr.disp() != 0, "must have");
1205   }
1206   if (info != NULL) {
1207     add_debug_info_for_null_check_here(info);
1208   }
1209 
1210   switch (type) {
1211     case T_FLOAT: {
1212       if (dest->is_single_xmm()) {
1213         __ movflt(dest->as_xmm_float_reg(), from_addr);
1214       } else {
1215         assert(dest->is_single_fpu(), "must be");
1216         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1217         __ fld_s(from_addr);
1218       }
1219       break;
1220     }
1221 
1222     case T_DOUBLE: {
1223       if (dest->is_double_xmm()) {
1224         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1225       } else {
1226         assert(dest->is_double_fpu(), "must be");
1227         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1228         __ fld_d(from_addr);
1229       }
1230       break;
1231     }
1232 
1233     case T_OBJECT:  // fall through
1234     case T_ARRAY:   // fall through
1235       if (UseCompressedOops && !wide) {
1236         __ movl(dest->as_register(), from_addr);
1237       } else {
1238         __ movptr(dest->as_register(), from_addr);
1239       }
1240       break;
1241 
1242     case T_ADDRESS:
1243       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1244         __ movl(dest->as_register(), from_addr);
1245       } else {
1246         __ movptr(dest->as_register(), from_addr);
1247       }
1248       break;
1249     case T_INT:
1250       __ movl(dest->as_register(), from_addr);
1251       break;
1252 
1253     case T_LONG: {
1254       Register to_lo = dest->as_register_lo();
1255       Register to_hi = dest->as_register_hi();
1256 #ifdef _LP64
1257       __ movptr(to_lo, as_Address_lo(addr));
1258 #else
1259       Register base = addr->base()->as_register();
1260       Register index = noreg;
1261       if (addr->index()->is_register()) {
1262         index = addr->index()->as_register();
1263       }
1264       if ((base == to_lo && index == to_hi) ||
1265           (base == to_hi && index == to_lo)) {
1266         // addresses with 2 registers are only formed as a result of
1267         // array access so this code will never have to deal with
1268         // patches or null checks.
1269         assert(info == NULL && patch == NULL, "must be");
1270         __ lea(to_hi, as_Address(addr));
1271         __ movl(to_lo, Address(to_hi, 0));
1272         __ movl(to_hi, Address(to_hi, BytesPerWord));
1273       } else if (base == to_lo || index == to_lo) {
1274         assert(base != to_hi, "can't be");
1275         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1276         __ movl(to_hi, as_Address_hi(addr));
1277         if (patch != NULL) {
1278           patching_epilog(patch, lir_patch_high, base, info);
1279           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1280           patch_code = lir_patch_low;
1281         }
1282         __ movl(to_lo, as_Address_lo(addr));
1283       } else {
1284         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1285         __ movl(to_lo, as_Address_lo(addr));
1286         if (patch != NULL) {
1287           patching_epilog(patch, lir_patch_low, base, info);
1288           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1289           patch_code = lir_patch_high;
1290         }
1291         __ movl(to_hi, as_Address_hi(addr));
1292       }
1293 #endif // _LP64
1294       break;
1295     }
1296 
1297     case T_BOOLEAN: // fall through
1298     case T_BYTE: {
1299       Register dest_reg = dest->as_register();
1300       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1301       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1302         __ movsbl(dest_reg, from_addr);
1303       } else {
1304         __ movb(dest_reg, from_addr);
1305         __ shll(dest_reg, 24);
1306         __ sarl(dest_reg, 24);
1307       }
1308       break;
1309     }
1310 
1311     case T_CHAR: {
1312       Register dest_reg = dest->as_register();
1313       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1314       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1315         __ movzwl(dest_reg, from_addr);
1316       } else {
1317         __ movw(dest_reg, from_addr);
1318       }
1319       break;
1320     }
1321 
1322     case T_SHORT: {
1323       Register dest_reg = dest->as_register();
1324       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1325         __ movswl(dest_reg, from_addr);
1326       } else {
1327         __ movw(dest_reg, from_addr);
1328         __ shll(dest_reg, 16);
1329         __ sarl(dest_reg, 16);
1330       }
1331       break;
1332     }
1333 
1334     default:
1335       ShouldNotReachHere();
1336   }
1337 
1338   if (patch != NULL) {
1339     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1340   }
1341 
1342   if (type == T_ARRAY || type == T_OBJECT) {
1343 #ifdef _LP64
1344     if (UseCompressedOops && !wide) {
1345       __ decode_heap_oop(dest->as_register());
1346     }
1347 #endif
1348 
1349     // Load barrier has not yet been applied, so ZGC can't verify the oop here
1350     if (!UseZGC) {
1351       __ verify_oop(dest->as_register());
1352     }
1353   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1354 #ifdef _LP64
1355     if (UseCompressedClassPointers) {
1356       __ decode_klass_not_null(dest->as_register());
1357     }
1358 #endif
1359   }
1360 }
1361 
1362 
1363 NEEDS_CLEANUP; // This could be static?
1364 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1365   int elem_size = type2aelembytes(type);
1366   switch (elem_size) {
1367     case 1: return Address::times_1;
1368     case 2: return Address::times_2;
1369     case 4: return Address::times_4;
1370     case 8: return Address::times_8;
1371   }
1372   ShouldNotReachHere();
1373   return Address::no_scale;
1374 }
1375 
1376 
1377 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1378   switch (op->code()) {
1379     case lir_idiv:
1380     case lir_irem:
1381       arithmetic_idiv(op->code(),
1382                       op->in_opr1(),
1383                       op->in_opr2(),
1384                       op->in_opr3(),
1385                       op->result_opr(),
1386                       op->info());
1387       break;
1388     case lir_fmad:
1389       __ fmad(op->result_opr()->as_xmm_double_reg(),
1390               op->in_opr1()->as_xmm_double_reg(),
1391               op->in_opr2()->as_xmm_double_reg(),
1392               op->in_opr3()->as_xmm_double_reg());
1393       break;
1394     case lir_fmaf:
1395       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1396               op->in_opr1()->as_xmm_float_reg(),
1397               op->in_opr2()->as_xmm_float_reg(),
1398               op->in_opr3()->as_xmm_float_reg());
1399       break;
1400     default:      ShouldNotReachHere(); break;
1401   }
1402 }
1403 
1404 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1405 #ifdef ASSERT
1406   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1407   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1408   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1409 #endif
1410 
1411   if (op->cond() == lir_cond_always) {
1412     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1413     __ jmp (*(op->label()));
1414   } else {
1415     Assembler::Condition acond = Assembler::zero;
1416     if (op->code() == lir_cond_float_branch) {
1417       assert(op->ublock() != NULL, "must have unordered successor");
1418       __ jcc(Assembler::parity, *(op->ublock()->label()));
1419       switch(op->cond()) {
1420         case lir_cond_equal:        acond = Assembler::equal;      break;
1421         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1422         case lir_cond_less:         acond = Assembler::below;      break;
1423         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1424         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1425         case lir_cond_greater:      acond = Assembler::above;      break;
1426         default:                         ShouldNotReachHere();
1427       }
1428     } else {
1429       switch (op->cond()) {
1430         case lir_cond_equal:        acond = Assembler::equal;       break;
1431         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1432         case lir_cond_less:         acond = Assembler::less;        break;
1433         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1434         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1435         case lir_cond_greater:      acond = Assembler::greater;     break;
1436         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1437         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1438         default:                         ShouldNotReachHere();
1439       }
1440     }
1441     __ jcc(acond,*(op->label()));
1442   }
1443 }
1444 
1445 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1446   LIR_Opr src  = op->in_opr();
1447   LIR_Opr dest = op->result_opr();
1448 
1449   switch (op->bytecode()) {
1450     case Bytecodes::_i2l:
1451 #ifdef _LP64
1452       __ movl2ptr(dest->as_register_lo(), src->as_register());
1453 #else
1454       move_regs(src->as_register(), dest->as_register_lo());
1455       move_regs(src->as_register(), dest->as_register_hi());
1456       __ sarl(dest->as_register_hi(), 31);
1457 #endif // LP64
1458       break;
1459 
1460     case Bytecodes::_l2i:
1461 #ifdef _LP64
1462       __ movl(dest->as_register(), src->as_register_lo());
1463 #else
1464       move_regs(src->as_register_lo(), dest->as_register());
1465 #endif
1466       break;
1467 
1468     case Bytecodes::_i2b:
1469       move_regs(src->as_register(), dest->as_register());
1470       __ sign_extend_byte(dest->as_register());
1471       break;
1472 
1473     case Bytecodes::_i2c:
1474       move_regs(src->as_register(), dest->as_register());
1475       __ andl(dest->as_register(), 0xFFFF);
1476       break;
1477 
1478     case Bytecodes::_i2s:
1479       move_regs(src->as_register(), dest->as_register());
1480       __ sign_extend_short(dest->as_register());
1481       break;
1482 
1483 
1484     case Bytecodes::_f2d:
1485     case Bytecodes::_d2f:
1486       if (dest->is_single_xmm()) {
1487         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1488       } else if (dest->is_double_xmm()) {
1489         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1490       } else {
1491         assert(src->fpu() == dest->fpu(), "register must be equal");
1492         // do nothing (float result is rounded later through spilling)
1493       }
1494       break;
1495 
1496     case Bytecodes::_i2f:
1497     case Bytecodes::_i2d:
1498       if (dest->is_single_xmm()) {
1499         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1500       } else if (dest->is_double_xmm()) {
1501         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1502       } else {
1503         assert(dest->fpu() == 0, "result must be on TOS");
1504         __ movl(Address(rsp, 0), src->as_register());
1505         __ fild_s(Address(rsp, 0));
1506       }
1507       break;
1508 
1509     case Bytecodes::_f2i:
1510     case Bytecodes::_d2i:
1511       if (src->is_single_xmm()) {
1512         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1513       } else if (src->is_double_xmm()) {
1514         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1515       } else {
1516         assert(src->fpu() == 0, "input must be on TOS");
1517         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1518         __ fist_s(Address(rsp, 0));
1519         __ movl(dest->as_register(), Address(rsp, 0));
1520         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1521       }
1522 
1523       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1524       assert(op->stub() != NULL, "stub required");
1525       __ cmpl(dest->as_register(), 0x80000000);
1526       __ jcc(Assembler::equal, *op->stub()->entry());
1527       __ bind(*op->stub()->continuation());
1528       break;
1529 
1530     case Bytecodes::_l2f:
1531     case Bytecodes::_l2d:
1532       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1533       assert(dest->fpu() == 0, "result must be on TOS");
1534 
1535       __ movptr(Address(rsp, 0),            src->as_register_lo());
1536       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1537       __ fild_d(Address(rsp, 0));
1538       // float result is rounded later through spilling
1539       break;
1540 
1541     case Bytecodes::_f2l:
1542     case Bytecodes::_d2l:
1543       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1544       assert(src->fpu() == 0, "input must be on TOS");
1545       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1546 
1547       // instruction sequence too long to inline it here
1548       {
1549         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1550       }
1551       break;
1552 
1553     default: ShouldNotReachHere();
1554   }
1555 }
1556 
1557 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1558   if (op->init_check()) {
1559     add_debug_info_for_null_check_here(op->stub()->info());
1560     __ cmpb(Address(op->klass()->as_register(),
1561                     InstanceKlass::init_state_offset()),
1562                     InstanceKlass::fully_initialized);
1563     __ jcc(Assembler::notEqual, *op->stub()->entry());
1564   }
1565   __ allocate_object(op->obj()->as_register(),
1566                      op->tmp1()->as_register(),
1567                      op->tmp2()->as_register(),
1568                      op->header_size(),
1569                      op->object_size(),
1570                      op->klass()->as_register(),
1571                      *op->stub()->entry());
1572   __ bind(*op->stub()->continuation());
1573 }
1574 
1575 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1576   Register len =  op->len()->as_register();
1577   LP64_ONLY( __ movslq(len, len); )
1578 
1579   if (UseSlowPath ||
1580       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1581       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1582     __ jmp(*op->stub()->entry());
1583   } else {
1584     Register tmp1 = op->tmp1()->as_register();
1585     Register tmp2 = op->tmp2()->as_register();
1586     Register tmp3 = op->tmp3()->as_register();
1587     if (len == tmp1) {
1588       tmp1 = tmp3;
1589     } else if (len == tmp2) {
1590       tmp2 = tmp3;
1591     } else if (len == tmp3) {
1592       // everything is ok
1593     } else {
1594       __ mov(tmp3, len);
1595     }
1596     __ allocate_array(op->obj()->as_register(),
1597                       len,
1598                       tmp1,
1599                       tmp2,
1600                       arrayOopDesc::header_size(op->type()),
1601                       array_element_size(op->type()),
1602                       op->klass()->as_register(),
1603                       *op->stub()->entry());
1604   }
1605   __ bind(*op->stub()->continuation());
1606 }
1607 
1608 void LIR_Assembler::type_profile_helper(Register mdo,
1609                                         ciMethodData *md, ciProfileData *data,
1610                                         Register recv, Label* update_done) {
1611   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1612     Label next_test;
1613     // See if the receiver is receiver[n].
1614     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1615     __ jccb(Assembler::notEqual, next_test);
1616     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1617     __ addptr(data_addr, DataLayout::counter_increment);
1618     __ jmp(*update_done);
1619     __ bind(next_test);
1620   }
1621 
1622   // Didn't find receiver; find next empty slot and fill it in
1623   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1624     Label next_test;
1625     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1626     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1627     __ jccb(Assembler::notEqual, next_test);
1628     __ movptr(recv_addr, recv);
1629     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1630     __ jmp(*update_done);
1631     __ bind(next_test);
1632   }
1633 }
1634 
1635 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1636   // we always need a stub for the failure case.
1637   CodeStub* stub = op->stub();
1638   Register obj = op->object()->as_register();
1639   Register k_RInfo = op->tmp1()->as_register();
1640   Register klass_RInfo = op->tmp2()->as_register();
1641   Register dst = op->result_opr()->as_register();
1642   ciKlass* k = op->klass();
1643   Register Rtmp1 = noreg;
1644 
1645   // check if it needs to be profiled
1646   ciMethodData* md = NULL;
1647   ciProfileData* data = NULL;
1648 
1649   if (op->should_profile()) {
1650     ciMethod* method = op->profiled_method();
1651     assert(method != NULL, "Should have method");
1652     int bci = op->profiled_bci();
1653     md = method->method_data_or_null();
1654     assert(md != NULL, "Sanity");
1655     data = md->bci_to_data(bci);
1656     assert(data != NULL,                "need data for type check");
1657     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1658   }
1659   Label profile_cast_success, profile_cast_failure;
1660   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1661   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1662 
1663   if (obj == k_RInfo) {
1664     k_RInfo = dst;
1665   } else if (obj == klass_RInfo) {
1666     klass_RInfo = dst;
1667   }
1668   if (k->is_loaded() && !UseCompressedClassPointers) {
1669     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1670   } else {
1671     Rtmp1 = op->tmp3()->as_register();
1672     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1673   }
1674 
1675   assert_different_registers(obj, k_RInfo, klass_RInfo);
1676 
1677   __ cmpptr(obj, (int32_t)NULL_WORD);
1678   if (op->should_profile()) {
1679     Label not_null;
1680     __ jccb(Assembler::notEqual, not_null);
1681     // Object is null; update MDO and exit
1682     Register mdo  = klass_RInfo;
1683     __ mov_metadata(mdo, md->constant_encoding());
1684     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1685     int header_bits = BitData::null_seen_byte_constant();
1686     __ orb(data_addr, header_bits);
1687     __ jmp(*obj_is_null);
1688     __ bind(not_null);
1689   } else {
1690     __ jcc(Assembler::equal, *obj_is_null);
1691   }
1692 
1693   if (!k->is_loaded()) {
1694     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1695   } else {
1696 #ifdef _LP64
1697     __ mov_metadata(k_RInfo, k->constant_encoding());
1698 #endif // _LP64
1699   }
1700   __ verify_oop(obj);
1701 
1702   if (op->fast_check()) {
1703     // get object class
1704     // not a safepoint as obj null check happens earlier
1705 #ifdef _LP64
1706     if (UseCompressedClassPointers) {
1707       __ load_klass(Rtmp1, obj);
1708       __ cmpptr(k_RInfo, Rtmp1);
1709     } else {
1710       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1711     }
1712 #else
1713     if (k->is_loaded()) {
1714       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1715     } else {
1716       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1717     }
1718 #endif
1719     __ jcc(Assembler::notEqual, *failure_target);
1720     // successful cast, fall through to profile or jump
1721   } else {
1722     // get object class
1723     // not a safepoint as obj null check happens earlier
1724     __ load_klass(klass_RInfo, obj);
1725     if (k->is_loaded()) {
1726       // See if we get an immediate positive hit
1727 #ifdef _LP64
1728       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1729 #else
1730       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1731 #endif // _LP64
1732       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1733         __ jcc(Assembler::notEqual, *failure_target);
1734         // successful cast, fall through to profile or jump
1735       } else {
1736         // See if we get an immediate positive hit
1737         __ jcc(Assembler::equal, *success_target);
1738         // check for self
1739 #ifdef _LP64
1740         __ cmpptr(klass_RInfo, k_RInfo);
1741 #else
1742         __ cmpklass(klass_RInfo, k->constant_encoding());
1743 #endif // _LP64
1744         __ jcc(Assembler::equal, *success_target);
1745 
1746         __ push(klass_RInfo);
1747 #ifdef _LP64
1748         __ push(k_RInfo);
1749 #else
1750         __ pushklass(k->constant_encoding());
1751 #endif // _LP64
1752         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1753         __ pop(klass_RInfo);
1754         __ pop(klass_RInfo);
1755         // result is a boolean
1756         __ cmpl(klass_RInfo, 0);
1757         __ jcc(Assembler::equal, *failure_target);
1758         // successful cast, fall through to profile or jump
1759       }
1760     } else {
1761       // perform the fast part of the checking logic
1762       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1763       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1764       __ push(klass_RInfo);
1765       __ push(k_RInfo);
1766       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1767       __ pop(klass_RInfo);
1768       __ pop(k_RInfo);
1769       // result is a boolean
1770       __ cmpl(k_RInfo, 0);
1771       __ jcc(Assembler::equal, *failure_target);
1772       // successful cast, fall through to profile or jump
1773     }
1774   }
1775   if (op->should_profile()) {
1776     Register mdo  = klass_RInfo, recv = k_RInfo;
1777     __ bind(profile_cast_success);
1778     __ mov_metadata(mdo, md->constant_encoding());
1779     __ load_klass(recv, obj);
1780     Label update_done;
1781     type_profile_helper(mdo, md, data, recv, success);
1782     __ jmp(*success);
1783 
1784     __ bind(profile_cast_failure);
1785     __ mov_metadata(mdo, md->constant_encoding());
1786     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1787     __ subptr(counter_addr, DataLayout::counter_increment);
1788     __ jmp(*failure);
1789   }
1790   __ jmp(*success);
1791 }
1792 
1793 
1794 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1795   LIR_Code code = op->code();
1796   if (code == lir_store_check) {
1797     Register value = op->object()->as_register();
1798     Register array = op->array()->as_register();
1799     Register k_RInfo = op->tmp1()->as_register();
1800     Register klass_RInfo = op->tmp2()->as_register();
1801     Register Rtmp1 = op->tmp3()->as_register();
1802 
1803     CodeStub* stub = op->stub();
1804 
1805     // check if it needs to be profiled
1806     ciMethodData* md = NULL;
1807     ciProfileData* data = NULL;
1808 
1809     if (op->should_profile()) {
1810       ciMethod* method = op->profiled_method();
1811       assert(method != NULL, "Should have method");
1812       int bci = op->profiled_bci();
1813       md = method->method_data_or_null();
1814       assert(md != NULL, "Sanity");
1815       data = md->bci_to_data(bci);
1816       assert(data != NULL,                "need data for type check");
1817       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1818     }
1819     Label profile_cast_success, profile_cast_failure, done;
1820     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1821     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1822 
1823     __ cmpptr(value, (int32_t)NULL_WORD);
1824     if (op->should_profile()) {
1825       Label not_null;
1826       __ jccb(Assembler::notEqual, not_null);
1827       // Object is null; update MDO and exit
1828       Register mdo  = klass_RInfo;
1829       __ mov_metadata(mdo, md->constant_encoding());
1830       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1831       int header_bits = BitData::null_seen_byte_constant();
1832       __ orb(data_addr, header_bits);
1833       __ jmp(done);
1834       __ bind(not_null);
1835     } else {
1836       __ jcc(Assembler::equal, done);
1837     }
1838 
1839     add_debug_info_for_null_check_here(op->info_for_exception());
1840     __ load_klass(k_RInfo, array);
1841     __ load_klass(klass_RInfo, value);
1842 
1843     // get instance klass (it's already uncompressed)
1844     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1845     // perform the fast part of the checking logic
1846     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1847     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1848     __ push(klass_RInfo);
1849     __ push(k_RInfo);
1850     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1851     __ pop(klass_RInfo);
1852     __ pop(k_RInfo);
1853     // result is a boolean
1854     __ cmpl(k_RInfo, 0);
1855     __ jcc(Assembler::equal, *failure_target);
1856     // fall through to the success case
1857 
1858     if (op->should_profile()) {
1859       Register mdo  = klass_RInfo, recv = k_RInfo;
1860       __ bind(profile_cast_success);
1861       __ mov_metadata(mdo, md->constant_encoding());
1862       __ load_klass(recv, value);
1863       Label update_done;
1864       type_profile_helper(mdo, md, data, recv, &done);
1865       __ jmpb(done);
1866 
1867       __ bind(profile_cast_failure);
1868       __ mov_metadata(mdo, md->constant_encoding());
1869       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1870       __ subptr(counter_addr, DataLayout::counter_increment);
1871       __ jmp(*stub->entry());
1872     }
1873 
1874     __ bind(done);
1875   } else
1876     if (code == lir_checkcast) {
1877       Register obj = op->object()->as_register();
1878       Register dst = op->result_opr()->as_register();
1879       Label success;
1880       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1881       __ bind(success);
1882       if (dst != obj) {
1883         __ mov(dst, obj);
1884       }
1885     } else
1886       if (code == lir_instanceof) {
1887         Register obj = op->object()->as_register();
1888         Register dst = op->result_opr()->as_register();
1889         Label success, failure, done;
1890         emit_typecheck_helper(op, &success, &failure, &failure);
1891         __ bind(failure);
1892         __ xorptr(dst, dst);
1893         __ jmpb(done);
1894         __ bind(success);
1895         __ movptr(dst, 1);
1896         __ bind(done);
1897       } else {
1898         ShouldNotReachHere();
1899       }
1900 
1901 }
1902 
1903 
1904 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1905   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1906     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1907     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1908     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1909     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1910     Register addr = op->addr()->as_register();
1911     if (os::is_MP()) {
1912       __ lock();
1913     }
1914     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1915 
1916   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1917     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1918     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1919     Register newval = op->new_value()->as_register();
1920     Register cmpval = op->cmp_value()->as_register();
1921     assert(cmpval == rax, "wrong register");
1922     assert(newval != NULL, "new val must be register");
1923     assert(cmpval != newval, "cmp and new values must be in different registers");
1924     assert(cmpval != addr, "cmp and addr must be in different registers");
1925     assert(newval != addr, "new value and addr must be in different registers");
1926 
1927     if ( op->code() == lir_cas_obj) {
1928 #ifdef _LP64
1929       if (UseCompressedOops) {
1930         __ encode_heap_oop(cmpval);
1931         __ mov(rscratch1, newval);
1932         __ encode_heap_oop(rscratch1);
1933         __ lock();
1934         // cmpval (rax) is implicitly used by this instruction
1935         __ cmpxchgl(rscratch1, Address(addr, 0));
1936       } else
1937 #endif
1938       {
1939         __ lock();
1940         __ cmpxchgptr(newval, Address(addr, 0));
1941       }
1942    } else {
1943       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1944       if (os::is_MP()) {
1945         __ lock();
1946       }
1947       __ cmpxchgl(newval, Address(addr, 0));
1948     }
1949 #ifdef _LP64
1950   } else if (op->code() == lir_cas_long) {
1951     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1952     Register newval = op->new_value()->as_register_lo();
1953     Register cmpval = op->cmp_value()->as_register_lo();
1954     assert(cmpval == rax, "wrong register");
1955     assert(newval != NULL, "new val must be register");
1956     assert(cmpval != newval, "cmp and new values must be in different registers");
1957     assert(cmpval != addr, "cmp and addr must be in different registers");
1958     assert(newval != addr, "new value and addr must be in different registers");
1959     if (os::is_MP()) {
1960       __ lock();
1961     }
1962     __ cmpxchgq(newval, Address(addr, 0));
1963 #endif // _LP64
1964   } else {
1965     Unimplemented();
1966   }
1967 }
1968 
1969 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1970   Assembler::Condition acond, ncond;
1971   switch (condition) {
1972     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1973     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1974     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
1975     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
1976     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
1977     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
1978     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
1979     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
1980     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
1981                                 ShouldNotReachHere();
1982   }
1983 
1984   if (opr1->is_cpu_register()) {
1985     reg2reg(opr1, result);
1986   } else if (opr1->is_stack()) {
1987     stack2reg(opr1, result, result->type());
1988   } else if (opr1->is_constant()) {
1989     const2reg(opr1, result, lir_patch_none, NULL);
1990   } else {
1991     ShouldNotReachHere();
1992   }
1993 
1994   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1995     // optimized version that does not require a branch
1996     if (opr2->is_single_cpu()) {
1997       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1998       __ cmov(ncond, result->as_register(), opr2->as_register());
1999     } else if (opr2->is_double_cpu()) {
2000       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2001       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2002       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2003       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2004     } else if (opr2->is_single_stack()) {
2005       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2006     } else if (opr2->is_double_stack()) {
2007       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2008       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2009     } else {
2010       ShouldNotReachHere();
2011     }
2012 
2013   } else {
2014     Label skip;
2015     __ jcc (acond, skip);
2016     if (opr2->is_cpu_register()) {
2017       reg2reg(opr2, result);
2018     } else if (opr2->is_stack()) {
2019       stack2reg(opr2, result, result->type());
2020     } else if (opr2->is_constant()) {
2021       const2reg(opr2, result, lir_patch_none, NULL);
2022     } else {
2023       ShouldNotReachHere();
2024     }
2025     __ bind(skip);
2026   }
2027 }
2028 
2029 
2030 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2031   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2032 
2033   if (left->is_single_cpu()) {
2034     assert(left == dest, "left and dest must be equal");
2035     Register lreg = left->as_register();
2036 
2037     if (right->is_single_cpu()) {
2038       // cpu register - cpu register
2039       Register rreg = right->as_register();
2040       switch (code) {
2041         case lir_add: __ addl (lreg, rreg); break;
2042         case lir_sub: __ subl (lreg, rreg); break;
2043         case lir_mul: __ imull(lreg, rreg); break;
2044         default:      ShouldNotReachHere();
2045       }
2046 
2047     } else if (right->is_stack()) {
2048       // cpu register - stack
2049       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2050       switch (code) {
2051         case lir_add: __ addl(lreg, raddr); break;
2052         case lir_sub: __ subl(lreg, raddr); break;
2053         default:      ShouldNotReachHere();
2054       }
2055 
2056     } else if (right->is_constant()) {
2057       // cpu register - constant
2058       jint c = right->as_constant_ptr()->as_jint();
2059       switch (code) {
2060         case lir_add: {
2061           __ incrementl(lreg, c);
2062           break;
2063         }
2064         case lir_sub: {
2065           __ decrementl(lreg, c);
2066           break;
2067         }
2068         default: ShouldNotReachHere();
2069       }
2070 
2071     } else {
2072       ShouldNotReachHere();
2073     }
2074 
2075   } else if (left->is_double_cpu()) {
2076     assert(left == dest, "left and dest must be equal");
2077     Register lreg_lo = left->as_register_lo();
2078     Register lreg_hi = left->as_register_hi();
2079 
2080     if (right->is_double_cpu()) {
2081       // cpu register - cpu register
2082       Register rreg_lo = right->as_register_lo();
2083       Register rreg_hi = right->as_register_hi();
2084       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2085       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2086       switch (code) {
2087         case lir_add:
2088           __ addptr(lreg_lo, rreg_lo);
2089           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2090           break;
2091         case lir_sub:
2092           __ subptr(lreg_lo, rreg_lo);
2093           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2094           break;
2095         case lir_mul:
2096 #ifdef _LP64
2097           __ imulq(lreg_lo, rreg_lo);
2098 #else
2099           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2100           __ imull(lreg_hi, rreg_lo);
2101           __ imull(rreg_hi, lreg_lo);
2102           __ addl (rreg_hi, lreg_hi);
2103           __ mull (rreg_lo);
2104           __ addl (lreg_hi, rreg_hi);
2105 #endif // _LP64
2106           break;
2107         default:
2108           ShouldNotReachHere();
2109       }
2110 
2111     } else if (right->is_constant()) {
2112       // cpu register - constant
2113 #ifdef _LP64
2114       jlong c = right->as_constant_ptr()->as_jlong_bits();
2115       __ movptr(r10, (intptr_t) c);
2116       switch (code) {
2117         case lir_add:
2118           __ addptr(lreg_lo, r10);
2119           break;
2120         case lir_sub:
2121           __ subptr(lreg_lo, r10);
2122           break;
2123         default:
2124           ShouldNotReachHere();
2125       }
2126 #else
2127       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2128       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2129       switch (code) {
2130         case lir_add:
2131           __ addptr(lreg_lo, c_lo);
2132           __ adcl(lreg_hi, c_hi);
2133           break;
2134         case lir_sub:
2135           __ subptr(lreg_lo, c_lo);
2136           __ sbbl(lreg_hi, c_hi);
2137           break;
2138         default:
2139           ShouldNotReachHere();
2140       }
2141 #endif // _LP64
2142 
2143     } else {
2144       ShouldNotReachHere();
2145     }
2146 
2147   } else if (left->is_single_xmm()) {
2148     assert(left == dest, "left and dest must be equal");
2149     XMMRegister lreg = left->as_xmm_float_reg();
2150 
2151     if (right->is_single_xmm()) {
2152       XMMRegister rreg = right->as_xmm_float_reg();
2153       switch (code) {
2154         case lir_add: __ addss(lreg, rreg);  break;
2155         case lir_sub: __ subss(lreg, rreg);  break;
2156         case lir_mul_strictfp: // fall through
2157         case lir_mul: __ mulss(lreg, rreg);  break;
2158         case lir_div_strictfp: // fall through
2159         case lir_div: __ divss(lreg, rreg);  break;
2160         default: ShouldNotReachHere();
2161       }
2162     } else {
2163       Address raddr;
2164       if (right->is_single_stack()) {
2165         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2166       } else if (right->is_constant()) {
2167         // hack for now
2168         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2169       } else {
2170         ShouldNotReachHere();
2171       }
2172       switch (code) {
2173         case lir_add: __ addss(lreg, raddr);  break;
2174         case lir_sub: __ subss(lreg, raddr);  break;
2175         case lir_mul_strictfp: // fall through
2176         case lir_mul: __ mulss(lreg, raddr);  break;
2177         case lir_div_strictfp: // fall through
2178         case lir_div: __ divss(lreg, raddr);  break;
2179         default: ShouldNotReachHere();
2180       }
2181     }
2182 
2183   } else if (left->is_double_xmm()) {
2184     assert(left == dest, "left and dest must be equal");
2185 
2186     XMMRegister lreg = left->as_xmm_double_reg();
2187     if (right->is_double_xmm()) {
2188       XMMRegister rreg = right->as_xmm_double_reg();
2189       switch (code) {
2190         case lir_add: __ addsd(lreg, rreg);  break;
2191         case lir_sub: __ subsd(lreg, rreg);  break;
2192         case lir_mul_strictfp: // fall through
2193         case lir_mul: __ mulsd(lreg, rreg);  break;
2194         case lir_div_strictfp: // fall through
2195         case lir_div: __ divsd(lreg, rreg);  break;
2196         default: ShouldNotReachHere();
2197       }
2198     } else {
2199       Address raddr;
2200       if (right->is_double_stack()) {
2201         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2202       } else if (right->is_constant()) {
2203         // hack for now
2204         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2205       } else {
2206         ShouldNotReachHere();
2207       }
2208       switch (code) {
2209         case lir_add: __ addsd(lreg, raddr);  break;
2210         case lir_sub: __ subsd(lreg, raddr);  break;
2211         case lir_mul_strictfp: // fall through
2212         case lir_mul: __ mulsd(lreg, raddr);  break;
2213         case lir_div_strictfp: // fall through
2214         case lir_div: __ divsd(lreg, raddr);  break;
2215         default: ShouldNotReachHere();
2216       }
2217     }
2218 
2219   } else if (left->is_single_fpu()) {
2220     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2221 
2222     if (right->is_single_fpu()) {
2223       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2224 
2225     } else {
2226       assert(left->fpu_regnr() == 0, "left must be on TOS");
2227       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2228 
2229       Address raddr;
2230       if (right->is_single_stack()) {
2231         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2232       } else if (right->is_constant()) {
2233         address const_addr = float_constant(right->as_jfloat());
2234         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2235         // hack for now
2236         raddr = __ as_Address(InternalAddress(const_addr));
2237       } else {
2238         ShouldNotReachHere();
2239       }
2240 
2241       switch (code) {
2242         case lir_add: __ fadd_s(raddr); break;
2243         case lir_sub: __ fsub_s(raddr); break;
2244         case lir_mul_strictfp: // fall through
2245         case lir_mul: __ fmul_s(raddr); break;
2246         case lir_div_strictfp: // fall through
2247         case lir_div: __ fdiv_s(raddr); break;
2248         default:      ShouldNotReachHere();
2249       }
2250     }
2251 
2252   } else if (left->is_double_fpu()) {
2253     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2254 
2255     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2256       // Double values require special handling for strictfp mul/div on x86
2257       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2258       __ fmulp(left->fpu_regnrLo() + 1);
2259     }
2260 
2261     if (right->is_double_fpu()) {
2262       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2263 
2264     } else {
2265       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2266       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2267 
2268       Address raddr;
2269       if (right->is_double_stack()) {
2270         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2271       } else if (right->is_constant()) {
2272         // hack for now
2273         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2274       } else {
2275         ShouldNotReachHere();
2276       }
2277 
2278       switch (code) {
2279         case lir_add: __ fadd_d(raddr); break;
2280         case lir_sub: __ fsub_d(raddr); break;
2281         case lir_mul_strictfp: // fall through
2282         case lir_mul: __ fmul_d(raddr); break;
2283         case lir_div_strictfp: // fall through
2284         case lir_div: __ fdiv_d(raddr); break;
2285         default: ShouldNotReachHere();
2286       }
2287     }
2288 
2289     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2290       // Double values require special handling for strictfp mul/div on x86
2291       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2292       __ fmulp(dest->fpu_regnrLo() + 1);
2293     }
2294 
2295   } else if (left->is_single_stack() || left->is_address()) {
2296     assert(left == dest, "left and dest must be equal");
2297 
2298     Address laddr;
2299     if (left->is_single_stack()) {
2300       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2301     } else if (left->is_address()) {
2302       laddr = as_Address(left->as_address_ptr());
2303     } else {
2304       ShouldNotReachHere();
2305     }
2306 
2307     if (right->is_single_cpu()) {
2308       Register rreg = right->as_register();
2309       switch (code) {
2310         case lir_add: __ addl(laddr, rreg); break;
2311         case lir_sub: __ subl(laddr, rreg); break;
2312         default:      ShouldNotReachHere();
2313       }
2314     } else if (right->is_constant()) {
2315       jint c = right->as_constant_ptr()->as_jint();
2316       switch (code) {
2317         case lir_add: {
2318           __ incrementl(laddr, c);
2319           break;
2320         }
2321         case lir_sub: {
2322           __ decrementl(laddr, c);
2323           break;
2324         }
2325         default: ShouldNotReachHere();
2326       }
2327     } else {
2328       ShouldNotReachHere();
2329     }
2330 
2331   } else {
2332     ShouldNotReachHere();
2333   }
2334 }
2335 
2336 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2337   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2338   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2339   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2340 
2341   bool left_is_tos = (left_index == 0);
2342   bool dest_is_tos = (dest_index == 0);
2343   int non_tos_index = (left_is_tos ? right_index : left_index);
2344 
2345   switch (code) {
2346     case lir_add:
2347       if (pop_fpu_stack)       __ faddp(non_tos_index);
2348       else if (dest_is_tos)    __ fadd (non_tos_index);
2349       else                     __ fadda(non_tos_index);
2350       break;
2351 
2352     case lir_sub:
2353       if (left_is_tos) {
2354         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2355         else if (dest_is_tos)  __ fsub  (non_tos_index);
2356         else                   __ fsubra(non_tos_index);
2357       } else {
2358         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2359         else if (dest_is_tos)  __ fsubr (non_tos_index);
2360         else                   __ fsuba (non_tos_index);
2361       }
2362       break;
2363 
2364     case lir_mul_strictfp: // fall through
2365     case lir_mul:
2366       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2367       else if (dest_is_tos)    __ fmul (non_tos_index);
2368       else                     __ fmula(non_tos_index);
2369       break;
2370 
2371     case lir_div_strictfp: // fall through
2372     case lir_div:
2373       if (left_is_tos) {
2374         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2375         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2376         else                   __ fdivra(non_tos_index);
2377       } else {
2378         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2379         else if (dest_is_tos)  __ fdivr (non_tos_index);
2380         else                   __ fdiva (non_tos_index);
2381       }
2382       break;
2383 
2384     case lir_rem:
2385       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2386       __ fremr(noreg);
2387       break;
2388 
2389     default:
2390       ShouldNotReachHere();
2391   }
2392 }
2393 
2394 
2395 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2396   if (value->is_double_xmm()) {
2397     switch(code) {
2398       case lir_abs :
2399         {
2400 #ifdef _LP64
2401           if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2402             assert(tmp->is_valid(), "need temporary");
2403             __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2404           } else
2405 #endif
2406           {
2407             if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2408               __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2409             }
2410             assert(!tmp->is_valid(), "do not need temporary");
2411             __ andpd(dest->as_xmm_double_reg(),
2412                      ExternalAddress((address)double_signmask_pool));
2413           }
2414         }
2415         break;
2416 
2417       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2418       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2419       default      : ShouldNotReachHere();
2420     }
2421 
2422   } else if (value->is_double_fpu()) {
2423     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2424     switch(code) {
2425       case lir_abs   : __ fabs() ; break;
2426       case lir_sqrt  : __ fsqrt(); break;
2427       default      : ShouldNotReachHere();
2428     }
2429   } else {
2430     Unimplemented();
2431   }
2432 }
2433 
2434 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2435   // assert(left->destroys_register(), "check");
2436   if (left->is_single_cpu()) {
2437     Register reg = left->as_register();
2438     if (right->is_constant()) {
2439       int val = right->as_constant_ptr()->as_jint();
2440       switch (code) {
2441         case lir_logic_and: __ andl (reg, val); break;
2442         case lir_logic_or:  __ orl  (reg, val); break;
2443         case lir_logic_xor: __ xorl (reg, val); break;
2444         default: ShouldNotReachHere();
2445       }
2446     } else if (right->is_stack()) {
2447       // added support for stack operands
2448       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2449       switch (code) {
2450         case lir_logic_and: __ andl (reg, raddr); break;
2451         case lir_logic_or:  __ orl  (reg, raddr); break;
2452         case lir_logic_xor: __ xorl (reg, raddr); break;
2453         default: ShouldNotReachHere();
2454       }
2455     } else {
2456       Register rright = right->as_register();
2457       switch (code) {
2458         case lir_logic_and: __ andptr (reg, rright); break;
2459         case lir_logic_or : __ orptr  (reg, rright); break;
2460         case lir_logic_xor: __ xorptr (reg, rright); break;
2461         default: ShouldNotReachHere();
2462       }
2463     }
2464     move_regs(reg, dst->as_register());
2465   } else {
2466     Register l_lo = left->as_register_lo();
2467     Register l_hi = left->as_register_hi();
2468     if (right->is_constant()) {
2469 #ifdef _LP64
2470       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2471       switch (code) {
2472         case lir_logic_and:
2473           __ andq(l_lo, rscratch1);
2474           break;
2475         case lir_logic_or:
2476           __ orq(l_lo, rscratch1);
2477           break;
2478         case lir_logic_xor:
2479           __ xorq(l_lo, rscratch1);
2480           break;
2481         default: ShouldNotReachHere();
2482       }
2483 #else
2484       int r_lo = right->as_constant_ptr()->as_jint_lo();
2485       int r_hi = right->as_constant_ptr()->as_jint_hi();
2486       switch (code) {
2487         case lir_logic_and:
2488           __ andl(l_lo, r_lo);
2489           __ andl(l_hi, r_hi);
2490           break;
2491         case lir_logic_or:
2492           __ orl(l_lo, r_lo);
2493           __ orl(l_hi, r_hi);
2494           break;
2495         case lir_logic_xor:
2496           __ xorl(l_lo, r_lo);
2497           __ xorl(l_hi, r_hi);
2498           break;
2499         default: ShouldNotReachHere();
2500       }
2501 #endif // _LP64
2502     } else {
2503 #ifdef _LP64
2504       Register r_lo;
2505       if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2506         r_lo = right->as_register();
2507       } else {
2508         r_lo = right->as_register_lo();
2509       }
2510 #else
2511       Register r_lo = right->as_register_lo();
2512       Register r_hi = right->as_register_hi();
2513       assert(l_lo != r_hi, "overwriting registers");
2514 #endif
2515       switch (code) {
2516         case lir_logic_and:
2517           __ andptr(l_lo, r_lo);
2518           NOT_LP64(__ andptr(l_hi, r_hi);)
2519           break;
2520         case lir_logic_or:
2521           __ orptr(l_lo, r_lo);
2522           NOT_LP64(__ orptr(l_hi, r_hi);)
2523           break;
2524         case lir_logic_xor:
2525           __ xorptr(l_lo, r_lo);
2526           NOT_LP64(__ xorptr(l_hi, r_hi);)
2527           break;
2528         default: ShouldNotReachHere();
2529       }
2530     }
2531 
2532     Register dst_lo = dst->as_register_lo();
2533     Register dst_hi = dst->as_register_hi();
2534 
2535 #ifdef _LP64
2536     move_regs(l_lo, dst_lo);
2537 #else
2538     if (dst_lo == l_hi) {
2539       assert(dst_hi != l_lo, "overwriting registers");
2540       move_regs(l_hi, dst_hi);
2541       move_regs(l_lo, dst_lo);
2542     } else {
2543       assert(dst_lo != l_hi, "overwriting registers");
2544       move_regs(l_lo, dst_lo);
2545       move_regs(l_hi, dst_hi);
2546     }
2547 #endif // _LP64
2548   }
2549 }
2550 
2551 
2552 // we assume that rax, and rdx can be overwritten
2553 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2554 
2555   assert(left->is_single_cpu(),   "left must be register");
2556   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2557   assert(result->is_single_cpu(), "result must be register");
2558 
2559   //  assert(left->destroys_register(), "check");
2560   //  assert(right->destroys_register(), "check");
2561 
2562   Register lreg = left->as_register();
2563   Register dreg = result->as_register();
2564 
2565   if (right->is_constant()) {
2566     jint divisor = right->as_constant_ptr()->as_jint();
2567     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2568     if (code == lir_idiv) {
2569       assert(lreg == rax, "must be rax,");
2570       assert(temp->as_register() == rdx, "tmp register must be rdx");
2571       __ cdql(); // sign extend into rdx:rax
2572       if (divisor == 2) {
2573         __ subl(lreg, rdx);
2574       } else {
2575         __ andl(rdx, divisor - 1);
2576         __ addl(lreg, rdx);
2577       }
2578       __ sarl(lreg, log2_jint(divisor));
2579       move_regs(lreg, dreg);
2580     } else if (code == lir_irem) {
2581       Label done;
2582       __ mov(dreg, lreg);
2583       __ andl(dreg, 0x80000000 | (divisor - 1));
2584       __ jcc(Assembler::positive, done);
2585       __ decrement(dreg);
2586       __ orl(dreg, ~(divisor - 1));
2587       __ increment(dreg);
2588       __ bind(done);
2589     } else {
2590       ShouldNotReachHere();
2591     }
2592   } else {
2593     Register rreg = right->as_register();
2594     assert(lreg == rax, "left register must be rax,");
2595     assert(rreg != rdx, "right register must not be rdx");
2596     assert(temp->as_register() == rdx, "tmp register must be rdx");
2597 
2598     move_regs(lreg, rax);
2599 
2600     int idivl_offset = __ corrected_idivl(rreg);
2601     if (ImplicitDiv0Checks) {
2602       add_debug_info_for_div0(idivl_offset, info);
2603     }
2604     if (code == lir_irem) {
2605       move_regs(rdx, dreg); // result is in rdx
2606     } else {
2607       move_regs(rax, dreg);
2608     }
2609   }
2610 }
2611 
2612 
2613 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2614   if (opr1->is_single_cpu()) {
2615     Register reg1 = opr1->as_register();
2616     if (opr2->is_single_cpu()) {
2617       // cpu register - cpu register
2618       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2619         __ cmpoop(reg1, opr2->as_register());
2620       } else {
2621         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2622         __ cmpl(reg1, opr2->as_register());
2623       }
2624     } else if (opr2->is_stack()) {
2625       // cpu register - stack
2626       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2627         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2628       } else {
2629         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2630       }
2631     } else if (opr2->is_constant()) {
2632       // cpu register - constant
2633       LIR_Const* c = opr2->as_constant_ptr();
2634       if (c->type() == T_INT) {
2635         __ cmpl(reg1, c->as_jint());
2636       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2637         // In 64bit oops are single register
2638         jobject o = c->as_jobject();
2639         if (o == NULL) {
2640           __ cmpptr(reg1, (int32_t)NULL_WORD);
2641         } else {
2642           __ cmpoop(reg1, o);
2643         }
2644       } else {
2645         fatal("unexpected type: %s", basictype_to_str(c->type()));
2646       }
2647       // cpu register - address
2648     } else if (opr2->is_address()) {
2649       if (op->info() != NULL) {
2650         add_debug_info_for_null_check_here(op->info());
2651       }
2652       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2653     } else {
2654       ShouldNotReachHere();
2655     }
2656 
2657   } else if(opr1->is_double_cpu()) {
2658     Register xlo = opr1->as_register_lo();
2659     Register xhi = opr1->as_register_hi();
2660     if (opr2->is_double_cpu()) {
2661 #ifdef _LP64
2662       __ cmpptr(xlo, opr2->as_register_lo());
2663 #else
2664       // cpu register - cpu register
2665       Register ylo = opr2->as_register_lo();
2666       Register yhi = opr2->as_register_hi();
2667       __ subl(xlo, ylo);
2668       __ sbbl(xhi, yhi);
2669       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2670         __ orl(xhi, xlo);
2671       }
2672 #endif // _LP64
2673     } else if (opr2->is_constant()) {
2674       // cpu register - constant 0
2675       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2676 #ifdef _LP64
2677       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2678 #else
2679       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2680       __ orl(xhi, xlo);
2681 #endif // _LP64
2682     } else {
2683       ShouldNotReachHere();
2684     }
2685 
2686   } else if (opr1->is_single_xmm()) {
2687     XMMRegister reg1 = opr1->as_xmm_float_reg();
2688     if (opr2->is_single_xmm()) {
2689       // xmm register - xmm register
2690       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2691     } else if (opr2->is_stack()) {
2692       // xmm register - stack
2693       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2694     } else if (opr2->is_constant()) {
2695       // xmm register - constant
2696       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2697     } else if (opr2->is_address()) {
2698       // xmm register - address
2699       if (op->info() != NULL) {
2700         add_debug_info_for_null_check_here(op->info());
2701       }
2702       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2703     } else {
2704       ShouldNotReachHere();
2705     }
2706 
2707   } else if (opr1->is_double_xmm()) {
2708     XMMRegister reg1 = opr1->as_xmm_double_reg();
2709     if (opr2->is_double_xmm()) {
2710       // xmm register - xmm register
2711       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2712     } else if (opr2->is_stack()) {
2713       // xmm register - stack
2714       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2715     } else if (opr2->is_constant()) {
2716       // xmm register - constant
2717       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2718     } else if (opr2->is_address()) {
2719       // xmm register - address
2720       if (op->info() != NULL) {
2721         add_debug_info_for_null_check_here(op->info());
2722       }
2723       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2724     } else {
2725       ShouldNotReachHere();
2726     }
2727 
2728   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2729     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2730     assert(opr2->is_fpu_register(), "both must be registers");
2731     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2732 
2733   } else if (opr1->is_address() && opr2->is_constant()) {
2734     LIR_Const* c = opr2->as_constant_ptr();
2735 #ifdef _LP64
2736     if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2737       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2738       __ movoop(rscratch1, c->as_jobject());
2739     }
2740 #endif // LP64
2741     if (op->info() != NULL) {
2742       add_debug_info_for_null_check_here(op->info());
2743     }
2744     // special case: address - constant
2745     LIR_Address* addr = opr1->as_address_ptr();
2746     if (c->type() == T_INT) {
2747       __ cmpl(as_Address(addr), c->as_jint());
2748     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2749 #ifdef _LP64
2750       // %%% Make this explode if addr isn't reachable until we figure out a
2751       // better strategy by giving noreg as the temp for as_Address
2752       __ cmpoop(rscratch1, as_Address(addr, noreg));
2753 #else
2754       __ cmpoop(as_Address(addr), c->as_jobject());
2755 #endif // _LP64
2756     } else {
2757       ShouldNotReachHere();
2758     }
2759 
2760   } else {
2761     ShouldNotReachHere();
2762   }
2763 }
2764 
2765 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2766   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2767     if (left->is_single_xmm()) {
2768       assert(right->is_single_xmm(), "must match");
2769       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2770     } else if (left->is_double_xmm()) {
2771       assert(right->is_double_xmm(), "must match");
2772       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2773 
2774     } else {
2775       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2776       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2777 
2778       assert(left->fpu() == 0, "left must be on TOS");
2779       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2780                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2781     }
2782   } else {
2783     assert(code == lir_cmp_l2i, "check");
2784 #ifdef _LP64
2785     Label done;
2786     Register dest = dst->as_register();
2787     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2788     __ movl(dest, -1);
2789     __ jccb(Assembler::less, done);
2790     __ set_byte_if_not_zero(dest);
2791     __ movzbl(dest, dest);
2792     __ bind(done);
2793 #else
2794     __ lcmp2int(left->as_register_hi(),
2795                 left->as_register_lo(),
2796                 right->as_register_hi(),
2797                 right->as_register_lo());
2798     move_regs(left->as_register_hi(), dst->as_register());
2799 #endif // _LP64
2800   }
2801 }
2802 
2803 
2804 void LIR_Assembler::align_call(LIR_Code code) {
2805   if (os::is_MP()) {
2806     // make sure that the displacement word of the call ends up word aligned
2807     int offset = __ offset();
2808     switch (code) {
2809       case lir_static_call:
2810       case lir_optvirtual_call:
2811       case lir_dynamic_call:
2812         offset += NativeCall::displacement_offset;
2813         break;
2814       case lir_icvirtual_call:
2815         offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2816       break;
2817       case lir_virtual_call:  // currently, sparc-specific for niagara
2818       default: ShouldNotReachHere();
2819     }
2820     __ align(BytesPerWord, offset);
2821   }
2822 }
2823 
2824 
2825 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2826   assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2827          "must be aligned");
2828   __ call(AddressLiteral(op->addr(), rtype));
2829   add_call_info(code_offset(), op->info());
2830 }
2831 
2832 
2833 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2834   __ ic_call(op->addr());
2835   add_call_info(code_offset(), op->info());
2836   assert(!os::is_MP() ||
2837          (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2838          "must be aligned");
2839 }
2840 
2841 
2842 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2843 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2844   ShouldNotReachHere();
2845 }
2846 
2847 
2848 void LIR_Assembler::emit_static_call_stub() {
2849   address call_pc = __ pc();
2850   address stub = __ start_a_stub(call_stub_size());
2851   if (stub == NULL) {
2852     bailout("static call stub overflow");
2853     return;
2854   }
2855 
2856   int start = __ offset();
2857   if (os::is_MP()) {
2858     // make sure that the displacement word of the call ends up word aligned
2859     __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2860   }
2861   __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2862   __ mov_metadata(rbx, (Metadata*)NULL);
2863   // must be set to -1 at code generation time
2864   assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2865   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2866   __ jump(RuntimeAddress(__ pc()));
2867 
2868   if (UseAOT) {
2869     // Trampoline to aot code
2870     __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2871 #ifdef _LP64
2872     __ mov64(rax, CONST64(0));  // address is zapped till fixup time.
2873 #else
2874     __ movl(rax, 0xdeadffff);  // address is zapped till fixup time.
2875 #endif
2876     __ jmp(rax);
2877   }
2878   assert(__ offset() - start <= call_stub_size(), "stub too big");
2879   __ end_a_stub();
2880 }
2881 
2882 
2883 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2884   assert(exceptionOop->as_register() == rax, "must match");
2885   assert(exceptionPC->as_register() == rdx, "must match");
2886 
2887   // exception object is not added to oop map by LinearScan
2888   // (LinearScan assumes that no oops are in fixed registers)
2889   info->add_register_oop(exceptionOop);
2890   Runtime1::StubID unwind_id;
2891 
2892   // get current pc information
2893   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2894   int pc_for_athrow_offset = __ offset();
2895   InternalAddress pc_for_athrow(__ pc());
2896   __ lea(exceptionPC->as_register(), pc_for_athrow);
2897   add_call_info(pc_for_athrow_offset, info); // for exception handler
2898 
2899   __ verify_not_null_oop(rax);
2900   // search an exception handler (rax: exception oop, rdx: throwing pc)
2901   if (compilation()->has_fpu_code()) {
2902     unwind_id = Runtime1::handle_exception_id;
2903   } else {
2904     unwind_id = Runtime1::handle_exception_nofpu_id;
2905   }
2906   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2907 
2908   // enough room for two byte trap
2909   __ nop();
2910 }
2911 
2912 
2913 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2914   assert(exceptionOop->as_register() == rax, "must match");
2915 
2916   __ jmp(_unwind_handler_entry);
2917 }
2918 
2919 
2920 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2921 
2922   // optimized version for linear scan:
2923   // * count must be already in ECX (guaranteed by LinearScan)
2924   // * left and dest must be equal
2925   // * tmp must be unused
2926   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2927   assert(left == dest, "left and dest must be equal");
2928   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2929 
2930   if (left->is_single_cpu()) {
2931     Register value = left->as_register();
2932     assert(value != SHIFT_count, "left cannot be ECX");
2933 
2934     switch (code) {
2935       case lir_shl:  __ shll(value); break;
2936       case lir_shr:  __ sarl(value); break;
2937       case lir_ushr: __ shrl(value); break;
2938       default: ShouldNotReachHere();
2939     }
2940   } else if (left->is_double_cpu()) {
2941     Register lo = left->as_register_lo();
2942     Register hi = left->as_register_hi();
2943     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2944 #ifdef _LP64
2945     switch (code) {
2946       case lir_shl:  __ shlptr(lo);        break;
2947       case lir_shr:  __ sarptr(lo);        break;
2948       case lir_ushr: __ shrptr(lo);        break;
2949       default: ShouldNotReachHere();
2950     }
2951 #else
2952 
2953     switch (code) {
2954       case lir_shl:  __ lshl(hi, lo);        break;
2955       case lir_shr:  __ lshr(hi, lo, true);  break;
2956       case lir_ushr: __ lshr(hi, lo, false); break;
2957       default: ShouldNotReachHere();
2958     }
2959 #endif // LP64
2960   } else {
2961     ShouldNotReachHere();
2962   }
2963 }
2964 
2965 
2966 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2967   if (dest->is_single_cpu()) {
2968     // first move left into dest so that left is not destroyed by the shift
2969     Register value = dest->as_register();
2970     count = count & 0x1F; // Java spec
2971 
2972     move_regs(left->as_register(), value);
2973     switch (code) {
2974       case lir_shl:  __ shll(value, count); break;
2975       case lir_shr:  __ sarl(value, count); break;
2976       case lir_ushr: __ shrl(value, count); break;
2977       default: ShouldNotReachHere();
2978     }
2979   } else if (dest->is_double_cpu()) {
2980 #ifndef _LP64
2981     Unimplemented();
2982 #else
2983     // first move left into dest so that left is not destroyed by the shift
2984     Register value = dest->as_register_lo();
2985     count = count & 0x1F; // Java spec
2986 
2987     move_regs(left->as_register_lo(), value);
2988     switch (code) {
2989       case lir_shl:  __ shlptr(value, count); break;
2990       case lir_shr:  __ sarptr(value, count); break;
2991       case lir_ushr: __ shrptr(value, count); break;
2992       default: ShouldNotReachHere();
2993     }
2994 #endif // _LP64
2995   } else {
2996     ShouldNotReachHere();
2997   }
2998 }
2999 
3000 
3001 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3002   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3003   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3004   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3005   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3006 }
3007 
3008 
3009 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3010   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3011   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3012   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3013   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3014 }
3015 
3016 
3017 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
3018   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3019   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3020   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3021   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3022 }
3023 
3024 
3025 void LIR_Assembler::store_parameter(Metadata* m,  int offset_from_rsp_in_words) {
3026   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3027   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3028   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3029   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3030 }
3031 
3032 
3033 // This code replaces a call to arraycopy; no exception may
3034 // be thrown in this code, they must be thrown in the System.arraycopy
3035 // activation frame; we could save some checks if this would not be the case
3036 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3037   ciArrayKlass* default_type = op->expected_type();
3038   Register src = op->src()->as_register();
3039   Register dst = op->dst()->as_register();
3040   Register src_pos = op->src_pos()->as_register();
3041   Register dst_pos = op->dst_pos()->as_register();
3042   Register length  = op->length()->as_register();
3043   Register tmp = op->tmp()->as_register();
3044 
3045   __ resolve_for_read(IN_HEAP, src);
3046   __ resolve_for_write(IN_HEAP, dst);
3047 
3048   CodeStub* stub = op->stub();
3049   int flags = op->flags();
3050   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3051   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3052 
3053   // if we don't know anything, just go through the generic arraycopy
3054   if (default_type == NULL) {
3055     Label done;
3056     // save outgoing arguments on stack in case call to System.arraycopy is needed
3057     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3058     // for interpreter calling conventions. Now we have to do it in new style conventions.
3059     // For the moment until C1 gets the new register allocator I just force all the
3060     // args to the right place (except the register args) and then on the back side
3061     // reload the register args properly if we go slow path. Yuck
3062 
3063     // These are proper for the calling convention
3064     store_parameter(length, 2);
3065     store_parameter(dst_pos, 1);
3066     store_parameter(dst, 0);
3067 
3068     // these are just temporary placements until we need to reload
3069     store_parameter(src_pos, 3);
3070     store_parameter(src, 4);
3071     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3072 
3073     address copyfunc_addr = StubRoutines::generic_arraycopy();
3074     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3075 
3076     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3077 #ifdef _LP64
3078     // The arguments are in java calling convention so we can trivially shift them to C
3079     // convention
3080     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3081     __ mov(c_rarg0, j_rarg0);
3082     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3083     __ mov(c_rarg1, j_rarg1);
3084     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3085     __ mov(c_rarg2, j_rarg2);
3086     assert_different_registers(c_rarg3, j_rarg4);
3087     __ mov(c_rarg3, j_rarg3);
3088 #ifdef _WIN64
3089     // Allocate abi space for args but be sure to keep stack aligned
3090     __ subptr(rsp, 6*wordSize);
3091     store_parameter(j_rarg4, 4);
3092 #ifndef PRODUCT
3093     if (PrintC1Statistics) {
3094       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3095     }
3096 #endif
3097     __ call(RuntimeAddress(copyfunc_addr));
3098     __ addptr(rsp, 6*wordSize);
3099 #else
3100     __ mov(c_rarg4, j_rarg4);
3101 #ifndef PRODUCT
3102     if (PrintC1Statistics) {
3103       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3104     }
3105 #endif
3106     __ call(RuntimeAddress(copyfunc_addr));
3107 #endif // _WIN64
3108 #else
3109     __ push(length);
3110     __ push(dst_pos);
3111     __ push(dst);
3112     __ push(src_pos);
3113     __ push(src);
3114 
3115 #ifndef PRODUCT
3116     if (PrintC1Statistics) {
3117       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3118     }
3119 #endif
3120     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3121 
3122 #endif // _LP64
3123 
3124     __ cmpl(rax, 0);
3125     __ jcc(Assembler::equal, *stub->continuation());
3126 
3127     __ mov(tmp, rax);
3128     __ xorl(tmp, -1);
3129 
3130     // Reload values from the stack so they are where the stub
3131     // expects them.
3132     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3133     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3134     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3135     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3136     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3137 
3138     __ subl(length, tmp);
3139     __ addl(src_pos, tmp);
3140     __ addl(dst_pos, tmp);
3141     __ jmp(*stub->entry());
3142 
3143     __ bind(*stub->continuation());
3144     return;
3145   }
3146 
3147   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3148 
3149   int elem_size = type2aelembytes(basic_type);
3150   Address::ScaleFactor scale;
3151 
3152   switch (elem_size) {
3153     case 1 :
3154       scale = Address::times_1;
3155       break;
3156     case 2 :
3157       scale = Address::times_2;
3158       break;
3159     case 4 :
3160       scale = Address::times_4;
3161       break;
3162     case 8 :
3163       scale = Address::times_8;
3164       break;
3165     default:
3166       scale = Address::no_scale;
3167       ShouldNotReachHere();
3168   }
3169 
3170   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3171   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3172   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3173   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3174 
3175   // length and pos's are all sign extended at this point on 64bit
3176 
3177   // test for NULL
3178   if (flags & LIR_OpArrayCopy::src_null_check) {
3179     __ testptr(src, src);
3180     __ jcc(Assembler::zero, *stub->entry());
3181   }
3182   if (flags & LIR_OpArrayCopy::dst_null_check) {
3183     __ testptr(dst, dst);
3184     __ jcc(Assembler::zero, *stub->entry());
3185   }
3186 
3187   // If the compiler was not able to prove that exact type of the source or the destination
3188   // of the arraycopy is an array type, check at runtime if the source or the destination is
3189   // an instance type.
3190   if (flags & LIR_OpArrayCopy::type_check) {
3191     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3192       __ load_klass(tmp, dst);
3193       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3194       __ jcc(Assembler::greaterEqual, *stub->entry());
3195     }
3196 
3197     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3198       __ load_klass(tmp, src);
3199       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3200       __ jcc(Assembler::greaterEqual, *stub->entry());
3201     }
3202   }
3203 
3204   // check if negative
3205   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3206     __ testl(src_pos, src_pos);
3207     __ jcc(Assembler::less, *stub->entry());
3208   }
3209   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3210     __ testl(dst_pos, dst_pos);
3211     __ jcc(Assembler::less, *stub->entry());
3212   }
3213 
3214   if (flags & LIR_OpArrayCopy::src_range_check) {
3215     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3216     __ cmpl(tmp, src_length_addr);
3217     __ jcc(Assembler::above, *stub->entry());
3218   }
3219   if (flags & LIR_OpArrayCopy::dst_range_check) {
3220     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3221     __ cmpl(tmp, dst_length_addr);
3222     __ jcc(Assembler::above, *stub->entry());
3223   }
3224 
3225   if (flags & LIR_OpArrayCopy::length_positive_check) {
3226     __ testl(length, length);
3227     __ jcc(Assembler::less, *stub->entry());
3228   }
3229 
3230 #ifdef _LP64
3231   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3232   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3233 #endif
3234 
3235   if (flags & LIR_OpArrayCopy::type_check) {
3236     // We don't know the array types are compatible
3237     if (basic_type != T_OBJECT) {
3238       // Simple test for basic type arrays
3239       if (UseCompressedClassPointers) {
3240         __ movl(tmp, src_klass_addr);
3241         __ cmpl(tmp, dst_klass_addr);
3242       } else {
3243         __ movptr(tmp, src_klass_addr);
3244         __ cmpptr(tmp, dst_klass_addr);
3245       }
3246       __ jcc(Assembler::notEqual, *stub->entry());
3247     } else {
3248       // For object arrays, if src is a sub class of dst then we can
3249       // safely do the copy.
3250       Label cont, slow;
3251 
3252       __ push(src);
3253       __ push(dst);
3254 
3255       __ load_klass(src, src);
3256       __ load_klass(dst, dst);
3257 
3258       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3259 
3260       __ push(src);
3261       __ push(dst);
3262       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3263       __ pop(dst);
3264       __ pop(src);
3265 
3266       __ cmpl(src, 0);
3267       __ jcc(Assembler::notEqual, cont);
3268 
3269       __ bind(slow);
3270       __ pop(dst);
3271       __ pop(src);
3272 
3273       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3274       if (copyfunc_addr != NULL) { // use stub if available
3275         // src is not a sub class of dst so we have to do a
3276         // per-element check.
3277 
3278         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3279         if ((flags & mask) != mask) {
3280           // Check that at least both of them object arrays.
3281           assert(flags & mask, "one of the two should be known to be an object array");
3282 
3283           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3284             __ load_klass(tmp, src);
3285           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3286             __ load_klass(tmp, dst);
3287           }
3288           int lh_offset = in_bytes(Klass::layout_helper_offset());
3289           Address klass_lh_addr(tmp, lh_offset);
3290           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3291           __ cmpl(klass_lh_addr, objArray_lh);
3292           __ jcc(Assembler::notEqual, *stub->entry());
3293         }
3294 
3295        // Spill because stubs can use any register they like and it's
3296        // easier to restore just those that we care about.
3297        store_parameter(dst, 0);
3298        store_parameter(dst_pos, 1);
3299        store_parameter(length, 2);
3300        store_parameter(src_pos, 3);
3301        store_parameter(src, 4);
3302 
3303 #ifndef _LP64
3304         __ movptr(tmp, dst_klass_addr);
3305         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3306         __ push(tmp);
3307         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3308         __ push(tmp);
3309         __ push(length);
3310         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3311         __ push(tmp);
3312         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3313         __ push(tmp);
3314 
3315         __ call_VM_leaf(copyfunc_addr, 5);
3316 #else
3317         __ movl2ptr(length, length); //higher 32bits must be null
3318 
3319         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3320         assert_different_registers(c_rarg0, dst, dst_pos, length);
3321         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3322         assert_different_registers(c_rarg1, dst, length);
3323 
3324         __ mov(c_rarg2, length);
3325         assert_different_registers(c_rarg2, dst);
3326 
3327 #ifdef _WIN64
3328         // Allocate abi space for args but be sure to keep stack aligned
3329         __ subptr(rsp, 6*wordSize);
3330         __ load_klass(c_rarg3, dst);
3331         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3332         store_parameter(c_rarg3, 4);
3333         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3334         __ call(RuntimeAddress(copyfunc_addr));
3335         __ addptr(rsp, 6*wordSize);
3336 #else
3337         __ load_klass(c_rarg4, dst);
3338         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3339         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3340         __ call(RuntimeAddress(copyfunc_addr));
3341 #endif
3342 
3343 #endif
3344 
3345 #ifndef PRODUCT
3346         if (PrintC1Statistics) {
3347           Label failed;
3348           __ testl(rax, rax);
3349           __ jcc(Assembler::notZero, failed);
3350           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3351           __ bind(failed);
3352         }
3353 #endif
3354 
3355         __ testl(rax, rax);
3356         __ jcc(Assembler::zero, *stub->continuation());
3357 
3358 #ifndef PRODUCT
3359         if (PrintC1Statistics) {
3360           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3361         }
3362 #endif
3363 
3364         __ mov(tmp, rax);
3365 
3366         __ xorl(tmp, -1);
3367 
3368         // Restore previously spilled arguments
3369         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3370         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3371         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3372         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3373         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3374 
3375 
3376         __ subl(length, tmp);
3377         __ addl(src_pos, tmp);
3378         __ addl(dst_pos, tmp);
3379       }
3380 
3381       __ jmp(*stub->entry());
3382 
3383       __ bind(cont);
3384       __ pop(dst);
3385       __ pop(src);
3386     }
3387   }
3388 
3389 #ifdef ASSERT
3390   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3391     // Sanity check the known type with the incoming class.  For the
3392     // primitive case the types must match exactly with src.klass and
3393     // dst.klass each exactly matching the default type.  For the
3394     // object array case, if no type check is needed then either the
3395     // dst type is exactly the expected type and the src type is a
3396     // subtype which we can't check or src is the same array as dst
3397     // but not necessarily exactly of type default_type.
3398     Label known_ok, halt;
3399     __ mov_metadata(tmp, default_type->constant_encoding());
3400 #ifdef _LP64
3401     if (UseCompressedClassPointers) {
3402       __ encode_klass_not_null(tmp);
3403     }
3404 #endif
3405 
3406     if (basic_type != T_OBJECT) {
3407 
3408       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3409       else                   __ cmpptr(tmp, dst_klass_addr);
3410       __ jcc(Assembler::notEqual, halt);
3411       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3412       else                   __ cmpptr(tmp, src_klass_addr);
3413       __ jcc(Assembler::equal, known_ok);
3414     } else {
3415       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3416       else                   __ cmpptr(tmp, dst_klass_addr);
3417       __ jcc(Assembler::equal, known_ok);
3418       __ cmpptr(src, dst);
3419       __ jcc(Assembler::equal, known_ok);
3420     }
3421     __ bind(halt);
3422     __ stop("incorrect type information in arraycopy");
3423     __ bind(known_ok);
3424   }
3425 #endif
3426 
3427 #ifndef PRODUCT
3428   if (PrintC1Statistics) {
3429     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3430   }
3431 #endif
3432 
3433 #ifdef _LP64
3434   assert_different_registers(c_rarg0, dst, dst_pos, length);
3435   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3436   assert_different_registers(c_rarg1, length);
3437   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3438   __ mov(c_rarg2, length);
3439 
3440 #else
3441   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3442   store_parameter(tmp, 0);
3443   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3444   store_parameter(tmp, 1);
3445   store_parameter(length, 2);
3446 #endif // _LP64
3447 
3448   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3449   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3450   const char *name;
3451   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3452   __ call_VM_leaf(entry, 0);
3453 
3454   __ bind(*stub->continuation());
3455 }
3456 
3457 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3458   assert(op->crc()->is_single_cpu(),  "crc must be register");
3459   assert(op->val()->is_single_cpu(),  "byte value must be register");
3460   assert(op->result_opr()->is_single_cpu(), "result must be register");
3461   Register crc = op->crc()->as_register();
3462   Register val = op->val()->as_register();
3463   Register res = op->result_opr()->as_register();
3464 
3465   assert_different_registers(val, crc, res);
3466 
3467   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3468   __ notl(crc); // ~crc
3469   __ update_byte_crc32(crc, val, res);
3470   __ notl(crc); // ~crc
3471   __ mov(res, crc);
3472 }
3473 
3474 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3475   Register obj = op->obj_opr()->as_register();  // may not be an oop
3476   Register hdr = op->hdr_opr()->as_register();
3477   Register lock = op->lock_opr()->as_register();
3478   if (!UseFastLocking) {
3479     __ jmp(*op->stub()->entry());
3480   } else if (op->code() == lir_lock) {
3481     Register scratch = noreg;
3482     if (UseBiasedLocking) {
3483       scratch = op->scratch_opr()->as_register();
3484     }
3485     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3486     __ resolve_for_write(IN_HEAP, obj);
3487     // add debug info for NullPointerException only if one is possible
3488     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3489     if (op->info() != NULL) {
3490       add_debug_info_for_null_check(null_check_offset, op->info());
3491     }
3492     // done
3493   } else if (op->code() == lir_unlock) {
3494     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3495     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3496   } else {
3497     Unimplemented();
3498   }
3499   __ bind(*op->stub()->continuation());
3500 }
3501 
3502 
3503 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3504   ciMethod* method = op->profiled_method();
3505   int bci          = op->profiled_bci();
3506   ciMethod* callee = op->profiled_callee();
3507 
3508   // Update counter for all call types
3509   ciMethodData* md = method->method_data_or_null();
3510   assert(md != NULL, "Sanity");
3511   ciProfileData* data = md->bci_to_data(bci);
3512   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3513   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3514   Register mdo  = op->mdo()->as_register();
3515   __ mov_metadata(mdo, md->constant_encoding());
3516   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3517   // Perform additional virtual call profiling for invokevirtual and
3518   // invokeinterface bytecodes
3519   if (op->should_profile_receiver_type()) {
3520     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3521     Register recv = op->recv()->as_register();
3522     assert_different_registers(mdo, recv);
3523     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3524     ciKlass* known_klass = op->known_holder();
3525     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3526       // We know the type that will be seen at this call site; we can
3527       // statically update the MethodData* rather than needing to do
3528       // dynamic tests on the receiver type
3529 
3530       // NOTE: we should probably put a lock around this search to
3531       // avoid collisions by concurrent compilations
3532       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3533       uint i;
3534       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3535         ciKlass* receiver = vc_data->receiver(i);
3536         if (known_klass->equals(receiver)) {
3537           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3538           __ addptr(data_addr, DataLayout::counter_increment);
3539           return;
3540         }
3541       }
3542 
3543       // Receiver type not found in profile data; select an empty slot
3544 
3545       // Note that this is less efficient than it should be because it
3546       // always does a write to the receiver part of the
3547       // VirtualCallData rather than just the first time
3548       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3549         ciKlass* receiver = vc_data->receiver(i);
3550         if (receiver == NULL) {
3551           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3552           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3553           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3554           __ addptr(data_addr, DataLayout::counter_increment);
3555           return;
3556         }
3557       }
3558     } else {
3559       __ load_klass(recv, recv);
3560       Label update_done;
3561       type_profile_helper(mdo, md, data, recv, &update_done);
3562       // Receiver did not match any saved receiver and there is no empty row for it.
3563       // Increment total counter to indicate polymorphic case.
3564       __ addptr(counter_addr, DataLayout::counter_increment);
3565 
3566       __ bind(update_done);
3567     }
3568   } else {
3569     // Static call
3570     __ addptr(counter_addr, DataLayout::counter_increment);
3571   }
3572 }
3573 
3574 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3575   Register obj = op->obj()->as_register();
3576   Register tmp = op->tmp()->as_pointer_register();
3577   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3578   ciKlass* exact_klass = op->exact_klass();
3579   intptr_t current_klass = op->current_klass();
3580   bool not_null = op->not_null();
3581   bool no_conflict = op->no_conflict();
3582 
3583   Label update, next, none;
3584 
3585   bool do_null = !not_null;
3586   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3587   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3588 
3589   assert(do_null || do_update, "why are we here?");
3590   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3591 
3592   __ verify_oop(obj);
3593 
3594   if (tmp != obj) {
3595     __ mov(tmp, obj);
3596   }
3597   if (do_null) {
3598     __ testptr(tmp, tmp);
3599     __ jccb(Assembler::notZero, update);
3600     if (!TypeEntries::was_null_seen(current_klass)) {
3601       __ orptr(mdo_addr, TypeEntries::null_seen);
3602     }
3603     if (do_update) {
3604 #ifndef ASSERT
3605       __ jmpb(next);
3606     }
3607 #else
3608       __ jmp(next);
3609     }
3610   } else {
3611     __ testptr(tmp, tmp);
3612     __ jccb(Assembler::notZero, update);
3613     __ stop("unexpect null obj");
3614 #endif
3615   }
3616 
3617   __ bind(update);
3618 
3619   if (do_update) {
3620 #ifdef ASSERT
3621     if (exact_klass != NULL) {
3622       Label ok;
3623       __ load_klass(tmp, tmp);
3624       __ push(tmp);
3625       __ mov_metadata(tmp, exact_klass->constant_encoding());
3626       __ cmpptr(tmp, Address(rsp, 0));
3627       __ jccb(Assembler::equal, ok);
3628       __ stop("exact klass and actual klass differ");
3629       __ bind(ok);
3630       __ pop(tmp);
3631     }
3632 #endif
3633     if (!no_conflict) {
3634       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3635         if (exact_klass != NULL) {
3636           __ mov_metadata(tmp, exact_klass->constant_encoding());
3637         } else {
3638           __ load_klass(tmp, tmp);
3639         }
3640 
3641         __ xorptr(tmp, mdo_addr);
3642         __ testptr(tmp, TypeEntries::type_klass_mask);
3643         // klass seen before, nothing to do. The unknown bit may have been
3644         // set already but no need to check.
3645         __ jccb(Assembler::zero, next);
3646 
3647         __ testptr(tmp, TypeEntries::type_unknown);
3648         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3649 
3650         if (TypeEntries::is_type_none(current_klass)) {
3651           __ cmpptr(mdo_addr, 0);
3652           __ jccb(Assembler::equal, none);
3653           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3654           __ jccb(Assembler::equal, none);
3655           // There is a chance that the checks above (re-reading profiling
3656           // data from memory) fail if another thread has just set the
3657           // profiling to this obj's klass
3658           __ xorptr(tmp, mdo_addr);
3659           __ testptr(tmp, TypeEntries::type_klass_mask);
3660           __ jccb(Assembler::zero, next);
3661         }
3662       } else {
3663         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3664                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3665 
3666         __ movptr(tmp, mdo_addr);
3667         __ testptr(tmp, TypeEntries::type_unknown);
3668         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3669       }
3670 
3671       // different than before. Cannot keep accurate profile.
3672       __ orptr(mdo_addr, TypeEntries::type_unknown);
3673 
3674       if (TypeEntries::is_type_none(current_klass)) {
3675         __ jmpb(next);
3676 
3677         __ bind(none);
3678         // first time here. Set profile type.
3679         __ movptr(mdo_addr, tmp);
3680       }
3681     } else {
3682       // There's a single possible klass at this profile point
3683       assert(exact_klass != NULL, "should be");
3684       if (TypeEntries::is_type_none(current_klass)) {
3685         __ mov_metadata(tmp, exact_klass->constant_encoding());
3686         __ xorptr(tmp, mdo_addr);
3687         __ testptr(tmp, TypeEntries::type_klass_mask);
3688 #ifdef ASSERT
3689         __ jcc(Assembler::zero, next);
3690 
3691         {
3692           Label ok;
3693           __ push(tmp);
3694           __ cmpptr(mdo_addr, 0);
3695           __ jcc(Assembler::equal, ok);
3696           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3697           __ jcc(Assembler::equal, ok);
3698           // may have been set by another thread
3699           __ mov_metadata(tmp, exact_klass->constant_encoding());
3700           __ xorptr(tmp, mdo_addr);
3701           __ testptr(tmp, TypeEntries::type_mask);
3702           __ jcc(Assembler::zero, ok);
3703 
3704           __ stop("unexpected profiling mismatch");
3705           __ bind(ok);
3706           __ pop(tmp);
3707         }
3708 #else
3709         __ jccb(Assembler::zero, next);
3710 #endif
3711         // first time here. Set profile type.
3712         __ movptr(mdo_addr, tmp);
3713       } else {
3714         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3715                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3716 
3717         __ movptr(tmp, mdo_addr);
3718         __ testptr(tmp, TypeEntries::type_unknown);
3719         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3720 
3721         __ orptr(mdo_addr, TypeEntries::type_unknown);
3722       }
3723     }
3724 
3725     __ bind(next);
3726   }
3727 }
3728 
3729 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3730   Unimplemented();
3731 }
3732 
3733 
3734 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3735   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3736 }
3737 
3738 
3739 void LIR_Assembler::align_backward_branch_target() {
3740   __ align(BytesPerWord);
3741 }
3742 
3743 
3744 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3745   if (left->is_single_cpu()) {
3746     __ negl(left->as_register());
3747     move_regs(left->as_register(), dest->as_register());
3748 
3749   } else if (left->is_double_cpu()) {
3750     Register lo = left->as_register_lo();
3751 #ifdef _LP64
3752     Register dst = dest->as_register_lo();
3753     __ movptr(dst, lo);
3754     __ negptr(dst);
3755 #else
3756     Register hi = left->as_register_hi();
3757     __ lneg(hi, lo);
3758     if (dest->as_register_lo() == hi) {
3759       assert(dest->as_register_hi() != lo, "destroying register");
3760       move_regs(hi, dest->as_register_hi());
3761       move_regs(lo, dest->as_register_lo());
3762     } else {
3763       move_regs(lo, dest->as_register_lo());
3764       move_regs(hi, dest->as_register_hi());
3765     }
3766 #endif // _LP64
3767 
3768   } else if (dest->is_single_xmm()) {
3769 #ifdef _LP64
3770     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3771       assert(tmp->is_valid(), "need temporary");
3772       assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3773       __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3774     }
3775     else
3776 #endif
3777     {
3778       assert(!tmp->is_valid(), "do not need temporary");
3779       if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3780         __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3781       }
3782       __ xorps(dest->as_xmm_float_reg(),
3783                ExternalAddress((address)float_signflip_pool));
3784     }
3785   } else if (dest->is_double_xmm()) {
3786 #ifdef _LP64
3787     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3788       assert(tmp->is_valid(), "need temporary");
3789       assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3790       __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3791     }
3792     else
3793 #endif
3794     {
3795       assert(!tmp->is_valid(), "do not need temporary");
3796       if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3797         __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3798       }
3799       __ xorpd(dest->as_xmm_double_reg(),
3800                ExternalAddress((address)double_signflip_pool));
3801     }
3802   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3803     assert(left->fpu() == 0, "arg must be on TOS");
3804     assert(dest->fpu() == 0, "dest must be TOS");
3805     __ fchs();
3806 
3807   } else {
3808     ShouldNotReachHere();
3809   }
3810 }
3811 
3812 
3813 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3814   assert(src->is_address(), "must be an address");
3815   assert(dest->is_register(), "must be a register");
3816 
3817   PatchingStub* patch = NULL;
3818   if (patch_code != lir_patch_none) {
3819     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3820   }
3821 
3822   Register reg = dest->as_pointer_register();
3823   LIR_Address* addr = src->as_address_ptr();
3824   __ lea(reg, as_Address(addr));
3825 
3826   if (patch != NULL) {
3827     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3828   }
3829 }
3830 
3831 
3832 
3833 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3834   assert(!tmp->is_valid(), "don't need temporary");
3835   __ call(RuntimeAddress(dest));
3836   if (info != NULL) {
3837     add_call_info_here(info);
3838   }
3839 }
3840 
3841 
3842 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3843   assert(type == T_LONG, "only for volatile long fields");
3844 
3845   if (info != NULL) {
3846     add_debug_info_for_null_check_here(info);
3847   }
3848 
3849   if (src->is_double_xmm()) {
3850     if (dest->is_double_cpu()) {
3851 #ifdef _LP64
3852       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3853 #else
3854       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3855       __ psrlq(src->as_xmm_double_reg(), 32);
3856       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3857 #endif // _LP64
3858     } else if (dest->is_double_stack()) {
3859       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3860     } else if (dest->is_address()) {
3861       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3862     } else {
3863       ShouldNotReachHere();
3864     }
3865 
3866   } else if (dest->is_double_xmm()) {
3867     if (src->is_double_stack()) {
3868       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3869     } else if (src->is_address()) {
3870       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3871     } else {
3872       ShouldNotReachHere();
3873     }
3874 
3875   } else if (src->is_double_fpu()) {
3876     assert(src->fpu_regnrLo() == 0, "must be TOS");
3877     if (dest->is_double_stack()) {
3878       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3879     } else if (dest->is_address()) {
3880       __ fistp_d(as_Address(dest->as_address_ptr()));
3881     } else {
3882       ShouldNotReachHere();
3883     }
3884 
3885   } else if (dest->is_double_fpu()) {
3886     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3887     if (src->is_double_stack()) {
3888       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3889     } else if (src->is_address()) {
3890       __ fild_d(as_Address(src->as_address_ptr()));
3891     } else {
3892       ShouldNotReachHere();
3893     }
3894   } else {
3895     ShouldNotReachHere();
3896   }
3897 }
3898 
3899 #ifdef ASSERT
3900 // emit run-time assertion
3901 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3902   assert(op->code() == lir_assert, "must be");
3903 
3904   if (op->in_opr1()->is_valid()) {
3905     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3906     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3907   } else {
3908     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3909     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3910   }
3911 
3912   Label ok;
3913   if (op->condition() != lir_cond_always) {
3914     Assembler::Condition acond = Assembler::zero;
3915     switch (op->condition()) {
3916       case lir_cond_equal:        acond = Assembler::equal;       break;
3917       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3918       case lir_cond_less:         acond = Assembler::less;        break;
3919       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3920       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3921       case lir_cond_greater:      acond = Assembler::greater;     break;
3922       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3923       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3924       default:                    ShouldNotReachHere();
3925     }
3926     __ jcc(acond, ok);
3927   }
3928   if (op->halt()) {
3929     const char* str = __ code_string(op->msg());
3930     __ stop(str);
3931   } else {
3932     breakpoint();
3933   }
3934   __ bind(ok);
3935 }
3936 #endif
3937 
3938 void LIR_Assembler::membar() {
3939   // QQQ sparc TSO uses this,
3940   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3941 }
3942 
3943 void LIR_Assembler::membar_acquire() {
3944   // No x86 machines currently require load fences
3945 }
3946 
3947 void LIR_Assembler::membar_release() {
3948   // No x86 machines currently require store fences
3949 }
3950 
3951 void LIR_Assembler::membar_loadload() {
3952   // no-op
3953   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3954 }
3955 
3956 void LIR_Assembler::membar_storestore() {
3957   // no-op
3958   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3959 }
3960 
3961 void LIR_Assembler::membar_loadstore() {
3962   // no-op
3963   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3964 }
3965 
3966 void LIR_Assembler::membar_storeload() {
3967   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3968 }
3969 
3970 void LIR_Assembler::on_spin_wait() {
3971   __ pause ();
3972 }
3973 
3974 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3975   assert(result_reg->is_register(), "check");
3976 #ifdef _LP64
3977   // __ get_thread(result_reg->as_register_lo());
3978   __ mov(result_reg->as_register(), r15_thread);
3979 #else
3980   __ get_thread(result_reg->as_register());
3981 #endif // _LP64
3982 }
3983 
3984 
3985 void LIR_Assembler::peephole(LIR_List*) {
3986   // do nothing for now
3987 }
3988 
3989 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3990   assert(data == dest, "xchg/xadd uses only 2 operands");
3991 
3992   if (data->type() == T_INT) {
3993     if (code == lir_xadd) {
3994       if (os::is_MP()) {
3995         __ lock();
3996       }
3997       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3998     } else {
3999       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4000     }
4001   } else if (data->is_oop()) {
4002     assert (code == lir_xchg, "xadd for oops");
4003     Register obj = data->as_register();
4004 #ifdef _LP64
4005     if (UseCompressedOops) {
4006       __ encode_heap_oop(obj);
4007       __ xchgl(obj, as_Address(src->as_address_ptr()));
4008       __ decode_heap_oop(obj);
4009     } else {
4010       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4011     }
4012 #else
4013     __ xchgl(obj, as_Address(src->as_address_ptr()));
4014 #endif
4015   } else if (data->type() == T_LONG) {
4016 #ifdef _LP64
4017     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4018     if (code == lir_xadd) {
4019       if (os::is_MP()) {
4020         __ lock();
4021       }
4022       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4023     } else {
4024       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4025     }
4026 #else
4027     ShouldNotReachHere();
4028 #endif
4029   } else {
4030     ShouldNotReachHere();
4031   }
4032 }
4033 
4034 #undef __