1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/disassembler.hpp"
  30 #include "gc/shared/barrierSet.hpp"
  31 #include "gc/shared/barrierSetAssembler.hpp"
  32 #include "gc/shared/collectedHeap.inline.hpp"
  33 #include "interpreter/interpreter.hpp"
  34 #include "memory/resourceArea.hpp"
  35 #include "memory/universe.hpp"
  36 #include "oops/accessDecorators.hpp"
  37 #include "oops/klass.inline.hpp"
  38 #include "prims/methodHandles.hpp"
  39 #include "runtime/biasedLocking.hpp"
  40 #include "runtime/flags/flagSetting.hpp"
  41 #include "runtime/interfaceSupport.inline.hpp"
  42 #include "runtime/objectMonitor.hpp"
  43 #include "runtime/os.hpp"
  44 #include "runtime/safepoint.hpp"
  45 #include "runtime/safepointMechanism.hpp"
  46 #include "runtime/sharedRuntime.hpp"
  47 #include "runtime/stubRoutines.hpp"
  48 #include "runtime/thread.hpp"
  49 #include "utilities/macros.hpp"
  50 #include "crc32c.h"
  51 #ifdef COMPILER2
  52 #include "opto/intrinsicnode.hpp"
  53 #endif
  54 
  55 #ifdef PRODUCT
  56 #define BLOCK_COMMENT(str) /* nothing */
  57 #define STOP(error) stop(error)
  58 #else
  59 #define BLOCK_COMMENT(str) block_comment(str)
  60 #define STOP(error) block_comment(error); stop(error)
  61 #endif
  62 
  63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  64 
  65 #ifdef ASSERT
  66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  67 #endif
  68 
  69 static Assembler::Condition reverse[] = {
  70     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  71     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  72     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  73     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  74     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  75     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  76     Assembler::above          /* belowEqual    = 0x6 */ ,
  77     Assembler::belowEqual     /* above         = 0x7 */ ,
  78     Assembler::positive       /* negative      = 0x8 */ ,
  79     Assembler::negative       /* positive      = 0x9 */ ,
  80     Assembler::noParity       /* parity        = 0xa */ ,
  81     Assembler::parity         /* noParity      = 0xb */ ,
  82     Assembler::greaterEqual   /* less          = 0xc */ ,
  83     Assembler::less           /* greaterEqual  = 0xd */ ,
  84     Assembler::greater        /* lessEqual     = 0xe */ ,
  85     Assembler::lessEqual      /* greater       = 0xf, */
  86 
  87 };
  88 
  89 
  90 // Implementation of MacroAssembler
  91 
  92 // First all the versions that have distinct versions depending on 32/64 bit
  93 // Unless the difference is trivial (1 line or so).
  94 
  95 #ifndef _LP64
  96 
  97 // 32bit versions
  98 
  99 Address MacroAssembler::as_Address(AddressLiteral adr) {
 100   return Address(adr.target(), adr.rspec());
 101 }
 102 
 103 Address MacroAssembler::as_Address(ArrayAddress adr) {
 104   return Address::make_array(adr);
 105 }
 106 
 107 void MacroAssembler::call_VM_leaf_base(address entry_point,
 108                                        int number_of_arguments) {
 109   call(RuntimeAddress(entry_point));
 110   increment(rsp, number_of_arguments * wordSize);
 111 }
 112 
 113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 114   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 115 }
 116 
 117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 118   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 119 }
 120 
 121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
 122   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 123 }
 124 
 125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
 126   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 127 }
 128 
 129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 130   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 131   bs->obj_equals(this, src1, obj);
 132 }
 133 
 134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 135   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 136   bs->obj_equals(this, src1, obj);
 137 }
 138 
 139 void MacroAssembler::extend_sign(Register hi, Register lo) {
 140   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 141   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 142     cdql();
 143   } else {
 144     movl(hi, lo);
 145     sarl(hi, 31);
 146   }
 147 }
 148 
 149 void MacroAssembler::jC2(Register tmp, Label& L) {
 150   // set parity bit if FPU flag C2 is set (via rax)
 151   save_rax(tmp);
 152   fwait(); fnstsw_ax();
 153   sahf();
 154   restore_rax(tmp);
 155   // branch
 156   jcc(Assembler::parity, L);
 157 }
 158 
 159 void MacroAssembler::jnC2(Register tmp, Label& L) {
 160   // set parity bit if FPU flag C2 is set (via rax)
 161   save_rax(tmp);
 162   fwait(); fnstsw_ax();
 163   sahf();
 164   restore_rax(tmp);
 165   // branch
 166   jcc(Assembler::noParity, L);
 167 }
 168 
 169 // 32bit can do a case table jump in one instruction but we no longer allow the base
 170 // to be installed in the Address class
 171 void MacroAssembler::jump(ArrayAddress entry) {
 172   jmp(as_Address(entry));
 173 }
 174 
 175 // Note: y_lo will be destroyed
 176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 177   // Long compare for Java (semantics as described in JVM spec.)
 178   Label high, low, done;
 179 
 180   cmpl(x_hi, y_hi);
 181   jcc(Assembler::less, low);
 182   jcc(Assembler::greater, high);
 183   // x_hi is the return register
 184   xorl(x_hi, x_hi);
 185   cmpl(x_lo, y_lo);
 186   jcc(Assembler::below, low);
 187   jcc(Assembler::equal, done);
 188 
 189   bind(high);
 190   xorl(x_hi, x_hi);
 191   increment(x_hi);
 192   jmp(done);
 193 
 194   bind(low);
 195   xorl(x_hi, x_hi);
 196   decrementl(x_hi);
 197 
 198   bind(done);
 199 }
 200 
 201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 202     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 203 }
 204 
 205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 206   // leal(dst, as_Address(adr));
 207   // see note in movl as to why we must use a move
 208   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 209 }
 210 
 211 void MacroAssembler::leave() {
 212   mov(rsp, rbp);
 213   pop(rbp);
 214 }
 215 
 216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 217   // Multiplication of two Java long values stored on the stack
 218   // as illustrated below. Result is in rdx:rax.
 219   //
 220   // rsp ---> [  ??  ] \               \
 221   //            ....    | y_rsp_offset  |
 222   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 223   //          [ y_hi ]                  | (in bytes)
 224   //            ....                    |
 225   //          [ x_lo ]                 /
 226   //          [ x_hi ]
 227   //            ....
 228   //
 229   // Basic idea: lo(result) = lo(x_lo * y_lo)
 230   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 231   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 232   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 233   Label quick;
 234   // load x_hi, y_hi and check if quick
 235   // multiplication is possible
 236   movl(rbx, x_hi);
 237   movl(rcx, y_hi);
 238   movl(rax, rbx);
 239   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 240   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 241   // do full multiplication
 242   // 1st step
 243   mull(y_lo);                                    // x_hi * y_lo
 244   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 245   // 2nd step
 246   movl(rax, x_lo);
 247   mull(rcx);                                     // x_lo * y_hi
 248   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 249   // 3rd step
 250   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 251   movl(rax, x_lo);
 252   mull(y_lo);                                    // x_lo * y_lo
 253   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 254 }
 255 
 256 void MacroAssembler::lneg(Register hi, Register lo) {
 257   negl(lo);
 258   adcl(hi, 0);
 259   negl(hi);
 260 }
 261 
 262 void MacroAssembler::lshl(Register hi, Register lo) {
 263   // Java shift left long support (semantics as described in JVM spec., p.305)
 264   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 265   // shift value is in rcx !
 266   assert(hi != rcx, "must not use rcx");
 267   assert(lo != rcx, "must not use rcx");
 268   const Register s = rcx;                        // shift count
 269   const int      n = BitsPerWord;
 270   Label L;
 271   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 272   cmpl(s, n);                                    // if (s < n)
 273   jcc(Assembler::less, L);                       // else (s >= n)
 274   movl(hi, lo);                                  // x := x << n
 275   xorl(lo, lo);
 276   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 277   bind(L);                                       // s (mod n) < n
 278   shldl(hi, lo);                                 // x := x << s
 279   shll(lo);
 280 }
 281 
 282 
 283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 284   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 285   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 286   assert(hi != rcx, "must not use rcx");
 287   assert(lo != rcx, "must not use rcx");
 288   const Register s = rcx;                        // shift count
 289   const int      n = BitsPerWord;
 290   Label L;
 291   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 292   cmpl(s, n);                                    // if (s < n)
 293   jcc(Assembler::less, L);                       // else (s >= n)
 294   movl(lo, hi);                                  // x := x >> n
 295   if (sign_extension) sarl(hi, 31);
 296   else                xorl(hi, hi);
 297   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 298   bind(L);                                       // s (mod n) < n
 299   shrdl(lo, hi);                                 // x := x >> s
 300   if (sign_extension) sarl(hi);
 301   else                shrl(hi);
 302 }
 303 
 304 void MacroAssembler::movoop(Register dst, jobject obj) {
 305   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 306 }
 307 
 308 void MacroAssembler::movoop(Address dst, jobject obj) {
 309   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 310 }
 311 
 312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 313   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 314 }
 315 
 316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 317   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 318 }
 319 
 320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 321   // scratch register is not used,
 322   // it is defined to match parameters of 64-bit version of this method.
 323   if (src.is_lval()) {
 324     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 325   } else {
 326     movl(dst, as_Address(src));
 327   }
 328 }
 329 
 330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 331   movl(as_Address(dst), src);
 332 }
 333 
 334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 335   movl(dst, as_Address(src));
 336 }
 337 
 338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 339 void MacroAssembler::movptr(Address dst, intptr_t src) {
 340   movl(dst, src);
 341 }
 342 
 343 
 344 void MacroAssembler::pop_callee_saved_registers() {
 345   pop(rcx);
 346   pop(rdx);
 347   pop(rdi);
 348   pop(rsi);
 349 }
 350 
 351 void MacroAssembler::pop_fTOS() {
 352   fld_d(Address(rsp, 0));
 353   addl(rsp, 2 * wordSize);
 354 }
 355 
 356 void MacroAssembler::push_callee_saved_registers() {
 357   push(rsi);
 358   push(rdi);
 359   push(rdx);
 360   push(rcx);
 361 }
 362 
 363 void MacroAssembler::push_fTOS() {
 364   subl(rsp, 2 * wordSize);
 365   fstp_d(Address(rsp, 0));
 366 }
 367 
 368 
 369 void MacroAssembler::pushoop(jobject obj) {
 370   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 371 }
 372 
 373 void MacroAssembler::pushklass(Metadata* obj) {
 374   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 375 }
 376 
 377 void MacroAssembler::pushptr(AddressLiteral src) {
 378   if (src.is_lval()) {
 379     push_literal32((int32_t)src.target(), src.rspec());
 380   } else {
 381     pushl(as_Address(src));
 382   }
 383 }
 384 
 385 void MacroAssembler::set_word_if_not_zero(Register dst) {
 386   xorl(dst, dst);
 387   set_byte_if_not_zero(dst);
 388 }
 389 
 390 static void pass_arg0(MacroAssembler* masm, Register arg) {
 391   masm->push(arg);
 392 }
 393 
 394 static void pass_arg1(MacroAssembler* masm, Register arg) {
 395   masm->push(arg);
 396 }
 397 
 398 static void pass_arg2(MacroAssembler* masm, Register arg) {
 399   masm->push(arg);
 400 }
 401 
 402 static void pass_arg3(MacroAssembler* masm, Register arg) {
 403   masm->push(arg);
 404 }
 405 
 406 #ifndef PRODUCT
 407 extern "C" void findpc(intptr_t x);
 408 #endif
 409 
 410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 411   // In order to get locks to work, we need to fake a in_VM state
 412   JavaThread* thread = JavaThread::current();
 413   JavaThreadState saved_state = thread->thread_state();
 414   thread->set_thread_state(_thread_in_vm);
 415   if (ShowMessageBoxOnError) {
 416     JavaThread* thread = JavaThread::current();
 417     JavaThreadState saved_state = thread->thread_state();
 418     thread->set_thread_state(_thread_in_vm);
 419     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 420       ttyLocker ttyl;
 421       BytecodeCounter::print();
 422     }
 423     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 424     // This is the value of eip which points to where verify_oop will return.
 425     if (os::message_box(msg, "Execution stopped, print registers?")) {
 426       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 427       BREAKPOINT;
 428     }
 429   } else {
 430     ttyLocker ttyl;
 431     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
 432   }
 433   // Don't assert holding the ttyLock
 434     assert(false, "DEBUG MESSAGE: %s", msg);
 435   ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 436 }
 437 
 438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 439   ttyLocker ttyl;
 440   FlagSetting fs(Debugging, true);
 441   tty->print_cr("eip = 0x%08x", eip);
 442 #ifndef PRODUCT
 443   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 444     tty->cr();
 445     findpc(eip);
 446     tty->cr();
 447   }
 448 #endif
 449 #define PRINT_REG(rax) \
 450   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 451   PRINT_REG(rax);
 452   PRINT_REG(rbx);
 453   PRINT_REG(rcx);
 454   PRINT_REG(rdx);
 455   PRINT_REG(rdi);
 456   PRINT_REG(rsi);
 457   PRINT_REG(rbp);
 458   PRINT_REG(rsp);
 459 #undef PRINT_REG
 460   // Print some words near top of staack.
 461   int* dump_sp = (int*) rsp;
 462   for (int col1 = 0; col1 < 8; col1++) {
 463     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 464     os::print_location(tty, *dump_sp++);
 465   }
 466   for (int row = 0; row < 16; row++) {
 467     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 468     for (int col = 0; col < 8; col++) {
 469       tty->print(" 0x%08x", *dump_sp++);
 470     }
 471     tty->cr();
 472   }
 473   // Print some instructions around pc:
 474   Disassembler::decode((address)eip-64, (address)eip);
 475   tty->print_cr("--------");
 476   Disassembler::decode((address)eip, (address)eip+32);
 477 }
 478 
 479 void MacroAssembler::stop(const char* msg) {
 480   ExternalAddress message((address)msg);
 481   // push address of message
 482   pushptr(message.addr());
 483   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 484   pusha();                                            // push registers
 485   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 486   hlt();
 487 }
 488 
 489 void MacroAssembler::warn(const char* msg) {
 490   push_CPU_state();
 491 
 492   ExternalAddress message((address) msg);
 493   // push address of message
 494   pushptr(message.addr());
 495 
 496   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 497   addl(rsp, wordSize);       // discard argument
 498   pop_CPU_state();
 499 }
 500 
 501 void MacroAssembler::print_state() {
 502   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 503   pusha();                                            // push registers
 504 
 505   push_CPU_state();
 506   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 507   pop_CPU_state();
 508 
 509   popa();
 510   addl(rsp, wordSize);
 511 }
 512 
 513 #else // _LP64
 514 
 515 // 64 bit versions
 516 
 517 Address MacroAssembler::as_Address(AddressLiteral adr) {
 518   // amd64 always does this as a pc-rel
 519   // we can be absolute or disp based on the instruction type
 520   // jmp/call are displacements others are absolute
 521   assert(!adr.is_lval(), "must be rval");
 522   assert(reachable(adr), "must be");
 523   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 524 
 525 }
 526 
 527 Address MacroAssembler::as_Address(ArrayAddress adr) {
 528   AddressLiteral base = adr.base();
 529   lea(rscratch1, base);
 530   Address index = adr.index();
 531   assert(index._disp == 0, "must not have disp"); // maybe it can?
 532   Address array(rscratch1, index._index, index._scale, index._disp);
 533   return array;
 534 }
 535 
 536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 537   Label L, E;
 538 
 539 #ifdef _WIN64
 540   // Windows always allocates space for it's register args
 541   assert(num_args <= 4, "only register arguments supported");
 542   subq(rsp,  frame::arg_reg_save_area_bytes);
 543 #endif
 544 
 545   // Align stack if necessary
 546   testl(rsp, 15);
 547   jcc(Assembler::zero, L);
 548 
 549   subq(rsp, 8);
 550   {
 551     call(RuntimeAddress(entry_point));
 552   }
 553   addq(rsp, 8);
 554   jmp(E);
 555 
 556   bind(L);
 557   {
 558     call(RuntimeAddress(entry_point));
 559   }
 560 
 561   bind(E);
 562 
 563 #ifdef _WIN64
 564   // restore stack pointer
 565   addq(rsp, frame::arg_reg_save_area_bytes);
 566 #endif
 567 
 568 }
 569 
 570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 571   assert(!src2.is_lval(), "should use cmpptr");
 572 
 573   if (reachable(src2)) {
 574     cmpq(src1, as_Address(src2));
 575   } else {
 576     lea(rscratch1, src2);
 577     Assembler::cmpq(src1, Address(rscratch1, 0));
 578   }
 579 }
 580 
 581 int MacroAssembler::corrected_idivq(Register reg) {
 582   // Full implementation of Java ldiv and lrem; checks for special
 583   // case as described in JVM spec., p.243 & p.271.  The function
 584   // returns the (pc) offset of the idivl instruction - may be needed
 585   // for implicit exceptions.
 586   //
 587   //         normal case                           special case
 588   //
 589   // input : rax: dividend                         min_long
 590   //         reg: divisor   (may not be eax/edx)   -1
 591   //
 592   // output: rax: quotient  (= rax idiv reg)       min_long
 593   //         rdx: remainder (= rax irem reg)       0
 594   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 595   static const int64_t min_long = 0x8000000000000000;
 596   Label normal_case, special_case;
 597 
 598   // check for special case
 599   cmp64(rax, ExternalAddress((address) &min_long));
 600   jcc(Assembler::notEqual, normal_case);
 601   xorl(rdx, rdx); // prepare rdx for possible special case (where
 602                   // remainder = 0)
 603   cmpq(reg, -1);
 604   jcc(Assembler::equal, special_case);
 605 
 606   // handle normal case
 607   bind(normal_case);
 608   cdqq();
 609   int idivq_offset = offset();
 610   idivq(reg);
 611 
 612   // normal and special case exit
 613   bind(special_case);
 614 
 615   return idivq_offset;
 616 }
 617 
 618 void MacroAssembler::decrementq(Register reg, int value) {
 619   if (value == min_jint) { subq(reg, value); return; }
 620   if (value <  0) { incrementq(reg, -value); return; }
 621   if (value == 0) {                        ; return; }
 622   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 623   /* else */      { subq(reg, value)       ; return; }
 624 }
 625 
 626 void MacroAssembler::decrementq(Address dst, int value) {
 627   if (value == min_jint) { subq(dst, value); return; }
 628   if (value <  0) { incrementq(dst, -value); return; }
 629   if (value == 0) {                        ; return; }
 630   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 631   /* else */      { subq(dst, value)       ; return; }
 632 }
 633 
 634 void MacroAssembler::incrementq(AddressLiteral dst) {
 635   if (reachable(dst)) {
 636     incrementq(as_Address(dst));
 637   } else {
 638     lea(rscratch1, dst);
 639     incrementq(Address(rscratch1, 0));
 640   }
 641 }
 642 
 643 void MacroAssembler::incrementq(Register reg, int value) {
 644   if (value == min_jint) { addq(reg, value); return; }
 645   if (value <  0) { decrementq(reg, -value); return; }
 646   if (value == 0) {                        ; return; }
 647   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 648   /* else */      { addq(reg, value)       ; return; }
 649 }
 650 
 651 void MacroAssembler::incrementq(Address dst, int value) {
 652   if (value == min_jint) { addq(dst, value); return; }
 653   if (value <  0) { decrementq(dst, -value); return; }
 654   if (value == 0) {                        ; return; }
 655   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 656   /* else */      { addq(dst, value)       ; return; }
 657 }
 658 
 659 // 32bit can do a case table jump in one instruction but we no longer allow the base
 660 // to be installed in the Address class
 661 void MacroAssembler::jump(ArrayAddress entry) {
 662   lea(rscratch1, entry.base());
 663   Address dispatch = entry.index();
 664   assert(dispatch._base == noreg, "must be");
 665   dispatch._base = rscratch1;
 666   jmp(dispatch);
 667 }
 668 
 669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 670   ShouldNotReachHere(); // 64bit doesn't use two regs
 671   cmpq(x_lo, y_lo);
 672 }
 673 
 674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 675     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 676 }
 677 
 678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 679   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 680   movptr(dst, rscratch1);
 681 }
 682 
 683 void MacroAssembler::leave() {
 684   // %%% is this really better? Why not on 32bit too?
 685   emit_int8((unsigned char)0xC9); // LEAVE
 686 }
 687 
 688 void MacroAssembler::lneg(Register hi, Register lo) {
 689   ShouldNotReachHere(); // 64bit doesn't use two regs
 690   negq(lo);
 691 }
 692 
 693 void MacroAssembler::movoop(Register dst, jobject obj) {
 694   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 695 }
 696 
 697 void MacroAssembler::movoop(Address dst, jobject obj) {
 698   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 699   movq(dst, rscratch1);
 700 }
 701 
 702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 703   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 704 }
 705 
 706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 707   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 708   movq(dst, rscratch1);
 709 }
 710 
 711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 712   if (src.is_lval()) {
 713     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 714   } else {
 715     if (reachable(src)) {
 716       movq(dst, as_Address(src));
 717     } else {
 718       lea(scratch, src);
 719       movq(dst, Address(scratch, 0));
 720     }
 721   }
 722 }
 723 
 724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 725   movq(as_Address(dst), src);
 726 }
 727 
 728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 729   movq(dst, as_Address(src));
 730 }
 731 
 732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 733 void MacroAssembler::movptr(Address dst, intptr_t src) {
 734   mov64(rscratch1, src);
 735   movq(dst, rscratch1);
 736 }
 737 
 738 // These are mostly for initializing NULL
 739 void MacroAssembler::movptr(Address dst, int32_t src) {
 740   movslq(dst, src);
 741 }
 742 
 743 void MacroAssembler::movptr(Register dst, int32_t src) {
 744   mov64(dst, (intptr_t)src);
 745 }
 746 
 747 void MacroAssembler::pushoop(jobject obj) {
 748   movoop(rscratch1, obj);
 749   push(rscratch1);
 750 }
 751 
 752 void MacroAssembler::pushklass(Metadata* obj) {
 753   mov_metadata(rscratch1, obj);
 754   push(rscratch1);
 755 }
 756 
 757 void MacroAssembler::pushptr(AddressLiteral src) {
 758   lea(rscratch1, src);
 759   if (src.is_lval()) {
 760     push(rscratch1);
 761   } else {
 762     pushq(Address(rscratch1, 0));
 763   }
 764 }
 765 
 766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 767   // we must set sp to zero to clear frame
 768   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
 769   // must clear fp, so that compiled frames are not confused; it is
 770   // possible that we need it only for debugging
 771   if (clear_fp) {
 772     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
 773   }
 774 
 775   // Always clear the pc because it could have been set by make_walkable()
 776   movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
 777   vzeroupper();
 778 }
 779 
 780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 781                                          Register last_java_fp,
 782                                          address  last_java_pc) {
 783   vzeroupper();
 784   // determine last_java_sp register
 785   if (!last_java_sp->is_valid()) {
 786     last_java_sp = rsp;
 787   }
 788 
 789   // last_java_fp is optional
 790   if (last_java_fp->is_valid()) {
 791     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 792            last_java_fp);
 793   }
 794 
 795   // last_java_pc is optional
 796   if (last_java_pc != NULL) {
 797     Address java_pc(r15_thread,
 798                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 799     lea(rscratch1, InternalAddress(last_java_pc));
 800     movptr(java_pc, rscratch1);
 801   }
 802 
 803   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 804 }
 805 
 806 static void pass_arg0(MacroAssembler* masm, Register arg) {
 807   if (c_rarg0 != arg ) {
 808     masm->mov(c_rarg0, arg);
 809   }
 810 }
 811 
 812 static void pass_arg1(MacroAssembler* masm, Register arg) {
 813   if (c_rarg1 != arg ) {
 814     masm->mov(c_rarg1, arg);
 815   }
 816 }
 817 
 818 static void pass_arg2(MacroAssembler* masm, Register arg) {
 819   if (c_rarg2 != arg ) {
 820     masm->mov(c_rarg2, arg);
 821   }
 822 }
 823 
 824 static void pass_arg3(MacroAssembler* masm, Register arg) {
 825   if (c_rarg3 != arg ) {
 826     masm->mov(c_rarg3, arg);
 827   }
 828 }
 829 
 830 void MacroAssembler::stop(const char* msg) {
 831   address rip = pc();
 832   pusha(); // get regs on stack
 833   lea(c_rarg0, ExternalAddress((address) msg));
 834   lea(c_rarg1, InternalAddress(rip));
 835   movq(c_rarg2, rsp); // pass pointer to regs array
 836   andq(rsp, -16); // align stack as required by ABI
 837   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 838   hlt();
 839 }
 840 
 841 void MacroAssembler::warn(const char* msg) {
 842   push(rbp);
 843   movq(rbp, rsp);
 844   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 845   push_CPU_state();   // keeps alignment at 16 bytes
 846   lea(c_rarg0, ExternalAddress((address) msg));
 847   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 848   call(rax);
 849   pop_CPU_state();
 850   mov(rsp, rbp);
 851   pop(rbp);
 852 }
 853 
 854 void MacroAssembler::print_state() {
 855   address rip = pc();
 856   pusha();            // get regs on stack
 857   push(rbp);
 858   movq(rbp, rsp);
 859   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 860   push_CPU_state();   // keeps alignment at 16 bytes
 861 
 862   lea(c_rarg0, InternalAddress(rip));
 863   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 864   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 865 
 866   pop_CPU_state();
 867   mov(rsp, rbp);
 868   pop(rbp);
 869   popa();
 870 }
 871 
 872 #ifndef PRODUCT
 873 extern "C" void findpc(intptr_t x);
 874 #endif
 875 
 876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 877   // In order to get locks to work, we need to fake a in_VM state
 878   if (ShowMessageBoxOnError) {
 879     JavaThread* thread = JavaThread::current();
 880     JavaThreadState saved_state = thread->thread_state();
 881     thread->set_thread_state(_thread_in_vm);
 882 #ifndef PRODUCT
 883     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 884       ttyLocker ttyl;
 885       BytecodeCounter::print();
 886     }
 887 #endif
 888     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 889     // XXX correct this offset for amd64
 890     // This is the value of eip which points to where verify_oop will return.
 891     if (os::message_box(msg, "Execution stopped, print registers?")) {
 892       print_state64(pc, regs);
 893       BREAKPOINT;
 894       assert(false, "start up GDB");
 895     }
 896     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 897   } else {
 898     ttyLocker ttyl;
 899     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
 900                     msg);
 901     assert(false, "DEBUG MESSAGE: %s", msg);
 902   }
 903 }
 904 
 905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 906   ttyLocker ttyl;
 907   FlagSetting fs(Debugging, true);
 908   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 909 #ifndef PRODUCT
 910   tty->cr();
 911   findpc(pc);
 912   tty->cr();
 913 #endif
 914 #define PRINT_REG(rax, value) \
 915   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 916   PRINT_REG(rax, regs[15]);
 917   PRINT_REG(rbx, regs[12]);
 918   PRINT_REG(rcx, regs[14]);
 919   PRINT_REG(rdx, regs[13]);
 920   PRINT_REG(rdi, regs[8]);
 921   PRINT_REG(rsi, regs[9]);
 922   PRINT_REG(rbp, regs[10]);
 923   PRINT_REG(rsp, regs[11]);
 924   PRINT_REG(r8 , regs[7]);
 925   PRINT_REG(r9 , regs[6]);
 926   PRINT_REG(r10, regs[5]);
 927   PRINT_REG(r11, regs[4]);
 928   PRINT_REG(r12, regs[3]);
 929   PRINT_REG(r13, regs[2]);
 930   PRINT_REG(r14, regs[1]);
 931   PRINT_REG(r15, regs[0]);
 932 #undef PRINT_REG
 933   // Print some words near top of staack.
 934   int64_t* rsp = (int64_t*) regs[11];
 935   int64_t* dump_sp = rsp;
 936   for (int col1 = 0; col1 < 8; col1++) {
 937     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 938     os::print_location(tty, *dump_sp++);
 939   }
 940   for (int row = 0; row < 25; row++) {
 941     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 942     for (int col = 0; col < 4; col++) {
 943       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 944     }
 945     tty->cr();
 946   }
 947   // Print some instructions around pc:
 948   Disassembler::decode((address)pc-64, (address)pc);
 949   tty->print_cr("--------");
 950   Disassembler::decode((address)pc, (address)pc+32);
 951 }
 952 
 953 #endif // _LP64
 954 
 955 // Now versions that are common to 32/64 bit
 956 
 957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
 958   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
 959 }
 960 
 961 void MacroAssembler::addptr(Register dst, Register src) {
 962   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 963 }
 964 
 965 void MacroAssembler::addptr(Address dst, Register src) {
 966   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 967 }
 968 
 969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
 970   if (reachable(src)) {
 971     Assembler::addsd(dst, as_Address(src));
 972   } else {
 973     lea(rscratch1, src);
 974     Assembler::addsd(dst, Address(rscratch1, 0));
 975   }
 976 }
 977 
 978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
 979   if (reachable(src)) {
 980     addss(dst, as_Address(src));
 981   } else {
 982     lea(rscratch1, src);
 983     addss(dst, Address(rscratch1, 0));
 984   }
 985 }
 986 
 987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
 988   if (reachable(src)) {
 989     Assembler::addpd(dst, as_Address(src));
 990   } else {
 991     lea(rscratch1, src);
 992     Assembler::addpd(dst, Address(rscratch1, 0));
 993   }
 994 }
 995 
 996 void MacroAssembler::align(int modulus) {
 997   align(modulus, offset());
 998 }
 999 
1000 void MacroAssembler::align(int modulus, int target) {
1001   if (target % modulus != 0) {
1002     nop(modulus - (target % modulus));
1003   }
1004 }
1005 
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1007   // Used in sign-masking with aligned address.
1008   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009   if (reachable(src)) {
1010     Assembler::andpd(dst, as_Address(src));
1011   } else {
1012     lea(rscratch1, src);
1013     Assembler::andpd(dst, Address(rscratch1, 0));
1014   }
1015 }
1016 
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1018   // Used in sign-masking with aligned address.
1019   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020   if (reachable(src)) {
1021     Assembler::andps(dst, as_Address(src));
1022   } else {
1023     lea(rscratch1, src);
1024     Assembler::andps(dst, Address(rscratch1, 0));
1025   }
1026 }
1027 
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031 
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033   if (os::is_MP())
1034     lock();
1035   incrementl(counter_addr);
1036 }
1037 
1038 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1039   if (reachable(counter_addr)) {
1040     atomic_incl(as_Address(counter_addr));
1041   } else {
1042     lea(scr, counter_addr);
1043     atomic_incl(Address(scr, 0));
1044   }
1045 }
1046 
1047 #ifdef _LP64
1048 void MacroAssembler::atomic_incq(Address counter_addr) {
1049   if (os::is_MP())
1050     lock();
1051   incrementq(counter_addr);
1052 }
1053 
1054 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1055   if (reachable(counter_addr)) {
1056     atomic_incq(as_Address(counter_addr));
1057   } else {
1058     lea(scr, counter_addr);
1059     atomic_incq(Address(scr, 0));
1060   }
1061 }
1062 #endif
1063 
1064 // Writes to stack successive pages until offset reached to check for
1065 // stack overflow + shadow pages.  This clobbers tmp.
1066 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1067   movptr(tmp, rsp);
1068   // Bang stack for total size given plus shadow page size.
1069   // Bang one page at a time because large size can bang beyond yellow and
1070   // red zones.
1071   Label loop;
1072   bind(loop);
1073   movl(Address(tmp, (-os::vm_page_size())), size );
1074   subptr(tmp, os::vm_page_size());
1075   subl(size, os::vm_page_size());
1076   jcc(Assembler::greater, loop);
1077 
1078   // Bang down shadow pages too.
1079   // At this point, (tmp-0) is the last address touched, so don't
1080   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1081   // was post-decremented.)  Skip this address by starting at i=1, and
1082   // touch a few more pages below.  N.B.  It is important to touch all
1083   // the way down including all pages in the shadow zone.
1084   for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1085     // this could be any sized move but this is can be a debugging crumb
1086     // so the bigger the better.
1087     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1088   }
1089 }
1090 
1091 void MacroAssembler::reserved_stack_check() {
1092     // testing if reserved zone needs to be enabled
1093     Label no_reserved_zone_enabling;
1094     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1095     NOT_LP64(get_thread(rsi);)
1096 
1097     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1098     jcc(Assembler::below, no_reserved_zone_enabling);
1099 
1100     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1101     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1102     should_not_reach_here();
1103 
1104     bind(no_reserved_zone_enabling);
1105 }
1106 
1107 int MacroAssembler::biased_locking_enter(Register lock_reg,
1108                                          Register obj_reg,
1109                                          Register swap_reg,
1110                                          Register tmp_reg,
1111                                          bool swap_reg_contains_mark,
1112                                          Label& done,
1113                                          Label* slow_case,
1114                                          BiasedLockingCounters* counters) {
1115   assert(UseBiasedLocking, "why call this otherwise?");
1116   assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1117   assert(tmp_reg != noreg, "tmp_reg must be supplied");
1118   assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1119   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1120   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
1121   NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1122 
1123   if (PrintBiasedLockingStatistics && counters == NULL) {
1124     counters = BiasedLocking::counters();
1125   }
1126   // Biased locking
1127   // See whether the lock is currently biased toward our thread and
1128   // whether the epoch is still valid
1129   // Note that the runtime guarantees sufficient alignment of JavaThread
1130   // pointers to allow age to be placed into low bits
1131   // First check to see whether biasing is even enabled for this object
1132   Label cas_label;
1133   int null_check_offset = -1;
1134   if (!swap_reg_contains_mark) {
1135     null_check_offset = offset();
1136     movptr(swap_reg, mark_addr);
1137   }
1138   movptr(tmp_reg, swap_reg);
1139   andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1140   cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1141   jcc(Assembler::notEqual, cas_label);
1142   // The bias pattern is present in the object's header. Need to check
1143   // whether the bias owner and the epoch are both still current.
1144 #ifndef _LP64
1145   // Note that because there is no current thread register on x86_32 we
1146   // need to store off the mark word we read out of the object to
1147   // avoid reloading it and needing to recheck invariants below. This
1148   // store is unfortunate but it makes the overall code shorter and
1149   // simpler.
1150   movptr(saved_mark_addr, swap_reg);
1151 #endif
1152   if (swap_reg_contains_mark) {
1153     null_check_offset = offset();
1154   }
1155   load_prototype_header(tmp_reg, obj_reg);
1156 #ifdef _LP64
1157   orptr(tmp_reg, r15_thread);
1158   xorptr(tmp_reg, swap_reg);
1159   Register header_reg = tmp_reg;
1160 #else
1161   xorptr(tmp_reg, swap_reg);
1162   get_thread(swap_reg);
1163   xorptr(swap_reg, tmp_reg);
1164   Register header_reg = swap_reg;
1165 #endif
1166   andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1167   if (counters != NULL) {
1168     cond_inc32(Assembler::zero,
1169                ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1170   }
1171   jcc(Assembler::equal, done);
1172 
1173   Label try_revoke_bias;
1174   Label try_rebias;
1175 
1176   // At this point we know that the header has the bias pattern and
1177   // that we are not the bias owner in the current epoch. We need to
1178   // figure out more details about the state of the header in order to
1179   // know what operations can be legally performed on the object's
1180   // header.
1181 
1182   // If the low three bits in the xor result aren't clear, that means
1183   // the prototype header is no longer biased and we have to revoke
1184   // the bias on this object.
1185   testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1186   jccb(Assembler::notZero, try_revoke_bias);
1187 
1188   // Biasing is still enabled for this data type. See whether the
1189   // epoch of the current bias is still valid, meaning that the epoch
1190   // bits of the mark word are equal to the epoch bits of the
1191   // prototype header. (Note that the prototype header's epoch bits
1192   // only change at a safepoint.) If not, attempt to rebias the object
1193   // toward the current thread. Note that we must be absolutely sure
1194   // that the current epoch is invalid in order to do this because
1195   // otherwise the manipulations it performs on the mark word are
1196   // illegal.
1197   testptr(header_reg, markOopDesc::epoch_mask_in_place);
1198   jccb(Assembler::notZero, try_rebias);
1199 
1200   // The epoch of the current bias is still valid but we know nothing
1201   // about the owner; it might be set or it might be clear. Try to
1202   // acquire the bias of the object using an atomic operation. If this
1203   // fails we will go in to the runtime to revoke the object's bias.
1204   // Note that we first construct the presumed unbiased header so we
1205   // don't accidentally blow away another thread's valid bias.
1206   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1207   andptr(swap_reg,
1208          markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1209 #ifdef _LP64
1210   movptr(tmp_reg, swap_reg);
1211   orptr(tmp_reg, r15_thread);
1212 #else
1213   get_thread(tmp_reg);
1214   orptr(tmp_reg, swap_reg);
1215 #endif
1216   if (os::is_MP()) {
1217     lock();
1218   }
1219   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1220   // If the biasing toward our thread failed, this means that
1221   // another thread succeeded in biasing it toward itself and we
1222   // need to revoke that bias. The revocation will occur in the
1223   // interpreter runtime in the slow case.
1224   if (counters != NULL) {
1225     cond_inc32(Assembler::zero,
1226                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1227   }
1228   if (slow_case != NULL) {
1229     jcc(Assembler::notZero, *slow_case);
1230   }
1231   jmp(done);
1232 
1233   bind(try_rebias);
1234   // At this point we know the epoch has expired, meaning that the
1235   // current "bias owner", if any, is actually invalid. Under these
1236   // circumstances _only_, we are allowed to use the current header's
1237   // value as the comparison value when doing the cas to acquire the
1238   // bias in the current epoch. In other words, we allow transfer of
1239   // the bias from one thread to another directly in this situation.
1240   //
1241   // FIXME: due to a lack of registers we currently blow away the age
1242   // bits in this situation. Should attempt to preserve them.
1243   load_prototype_header(tmp_reg, obj_reg);
1244 #ifdef _LP64
1245   orptr(tmp_reg, r15_thread);
1246 #else
1247   get_thread(swap_reg);
1248   orptr(tmp_reg, swap_reg);
1249   movptr(swap_reg, saved_mark_addr);
1250 #endif
1251   if (os::is_MP()) {
1252     lock();
1253   }
1254   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1255   // If the biasing toward our thread failed, then another thread
1256   // succeeded in biasing it toward itself and we need to revoke that
1257   // bias. The revocation will occur in the runtime in the slow case.
1258   if (counters != NULL) {
1259     cond_inc32(Assembler::zero,
1260                ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1261   }
1262   if (slow_case != NULL) {
1263     jcc(Assembler::notZero, *slow_case);
1264   }
1265   jmp(done);
1266 
1267   bind(try_revoke_bias);
1268   // The prototype mark in the klass doesn't have the bias bit set any
1269   // more, indicating that objects of this data type are not supposed
1270   // to be biased any more. We are going to try to reset the mark of
1271   // this object to the prototype value and fall through to the
1272   // CAS-based locking scheme. Note that if our CAS fails, it means
1273   // that another thread raced us for the privilege of revoking the
1274   // bias of this particular object, so it's okay to continue in the
1275   // normal locking code.
1276   //
1277   // FIXME: due to a lack of registers we currently blow away the age
1278   // bits in this situation. Should attempt to preserve them.
1279   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1280   load_prototype_header(tmp_reg, obj_reg);
1281   if (os::is_MP()) {
1282     lock();
1283   }
1284   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1285   // Fall through to the normal CAS-based lock, because no matter what
1286   // the result of the above CAS, some thread must have succeeded in
1287   // removing the bias bit from the object's header.
1288   if (counters != NULL) {
1289     cond_inc32(Assembler::zero,
1290                ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1291   }
1292 
1293   bind(cas_label);
1294 
1295   return null_check_offset;
1296 }
1297 
1298 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1299   assert(UseBiasedLocking, "why call this otherwise?");
1300 
1301   // Check for biased locking unlock case, which is a no-op
1302   // Note: we do not have to check the thread ID for two reasons.
1303   // First, the interpreter checks for IllegalMonitorStateException at
1304   // a higher level. Second, if the bias was revoked while we held the
1305   // lock, the object could not be rebiased toward another thread, so
1306   // the bias bit would be clear.
1307   movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1308   andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1309   cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1310   jcc(Assembler::equal, done);
1311 }
1312 
1313 #ifdef COMPILER2
1314 
1315 #if INCLUDE_RTM_OPT
1316 
1317 // Update rtm_counters based on abort status
1318 // input: abort_status
1319 //        rtm_counters (RTMLockingCounters*)
1320 // flags are killed
1321 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1322 
1323   atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1324   if (PrintPreciseRTMLockingStatistics) {
1325     for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1326       Label check_abort;
1327       testl(abort_status, (1<<i));
1328       jccb(Assembler::equal, check_abort);
1329       atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1330       bind(check_abort);
1331     }
1332   }
1333 }
1334 
1335 // Branch if (random & (count-1) != 0), count is 2^n
1336 // tmp, scr and flags are killed
1337 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1338   assert(tmp == rax, "");
1339   assert(scr == rdx, "");
1340   rdtsc(); // modifies EDX:EAX
1341   andptr(tmp, count-1);
1342   jccb(Assembler::notZero, brLabel);
1343 }
1344 
1345 // Perform abort ratio calculation, set no_rtm bit if high ratio
1346 // input:  rtm_counters_Reg (RTMLockingCounters* address)
1347 // tmpReg, rtm_counters_Reg and flags are killed
1348 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1349                                                  Register rtm_counters_Reg,
1350                                                  RTMLockingCounters* rtm_counters,
1351                                                  Metadata* method_data) {
1352   Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1353 
1354   if (RTMLockingCalculationDelay > 0) {
1355     // Delay calculation
1356     movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1357     testptr(tmpReg, tmpReg);
1358     jccb(Assembler::equal, L_done);
1359   }
1360   // Abort ratio calculation only if abort_count > RTMAbortThreshold
1361   //   Aborted transactions = abort_count * 100
1362   //   All transactions = total_count *  RTMTotalCountIncrRate
1363   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1364 
1365   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1366   cmpptr(tmpReg, RTMAbortThreshold);
1367   jccb(Assembler::below, L_check_always_rtm2);
1368   imulptr(tmpReg, tmpReg, 100);
1369 
1370   Register scrReg = rtm_counters_Reg;
1371   movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1372   imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1373   imulptr(scrReg, scrReg, RTMAbortRatio);
1374   cmpptr(tmpReg, scrReg);
1375   jccb(Assembler::below, L_check_always_rtm1);
1376   if (method_data != NULL) {
1377     // set rtm_state to "no rtm" in MDO
1378     mov_metadata(tmpReg, method_data);
1379     if (os::is_MP()) {
1380       lock();
1381     }
1382     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1383   }
1384   jmpb(L_done);
1385   bind(L_check_always_rtm1);
1386   // Reload RTMLockingCounters* address
1387   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1388   bind(L_check_always_rtm2);
1389   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1390   cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1391   jccb(Assembler::below, L_done);
1392   if (method_data != NULL) {
1393     // set rtm_state to "always rtm" in MDO
1394     mov_metadata(tmpReg, method_data);
1395     if (os::is_MP()) {
1396       lock();
1397     }
1398     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1399   }
1400   bind(L_done);
1401 }
1402 
1403 // Update counters and perform abort ratio calculation
1404 // input:  abort_status_Reg
1405 // rtm_counters_Reg, flags are killed
1406 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1407                                    Register rtm_counters_Reg,
1408                                    RTMLockingCounters* rtm_counters,
1409                                    Metadata* method_data,
1410                                    bool profile_rtm) {
1411 
1412   assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1413   // update rtm counters based on rax value at abort
1414   // reads abort_status_Reg, updates flags
1415   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1416   rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1417   if (profile_rtm) {
1418     // Save abort status because abort_status_Reg is used by following code.
1419     if (RTMRetryCount > 0) {
1420       push(abort_status_Reg);
1421     }
1422     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1423     rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1424     // restore abort status
1425     if (RTMRetryCount > 0) {
1426       pop(abort_status_Reg);
1427     }
1428   }
1429 }
1430 
1431 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1432 // inputs: retry_count_Reg
1433 //       : abort_status_Reg
1434 // output: retry_count_Reg decremented by 1
1435 // flags are killed
1436 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1437   Label doneRetry;
1438   assert(abort_status_Reg == rax, "");
1439   // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1440   // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1441   // if reason is in 0x6 and retry count != 0 then retry
1442   andptr(abort_status_Reg, 0x6);
1443   jccb(Assembler::zero, doneRetry);
1444   testl(retry_count_Reg, retry_count_Reg);
1445   jccb(Assembler::zero, doneRetry);
1446   pause();
1447   decrementl(retry_count_Reg);
1448   jmp(retryLabel);
1449   bind(doneRetry);
1450 }
1451 
1452 // Spin and retry if lock is busy,
1453 // inputs: box_Reg (monitor address)
1454 //       : retry_count_Reg
1455 // output: retry_count_Reg decremented by 1
1456 //       : clear z flag if retry count exceeded
1457 // tmp_Reg, scr_Reg, flags are killed
1458 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1459                                             Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1460   Label SpinLoop, SpinExit, doneRetry;
1461   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1462 
1463   testl(retry_count_Reg, retry_count_Reg);
1464   jccb(Assembler::zero, doneRetry);
1465   decrementl(retry_count_Reg);
1466   movptr(scr_Reg, RTMSpinLoopCount);
1467 
1468   bind(SpinLoop);
1469   pause();
1470   decrementl(scr_Reg);
1471   jccb(Assembler::lessEqual, SpinExit);
1472   movptr(tmp_Reg, Address(box_Reg, owner_offset));
1473   testptr(tmp_Reg, tmp_Reg);
1474   jccb(Assembler::notZero, SpinLoop);
1475 
1476   bind(SpinExit);
1477   jmp(retryLabel);
1478   bind(doneRetry);
1479   incrementl(retry_count_Reg); // clear z flag
1480 }
1481 
1482 // Use RTM for normal stack locks
1483 // Input: objReg (object to lock)
1484 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1485                                        Register retry_on_abort_count_Reg,
1486                                        RTMLockingCounters* stack_rtm_counters,
1487                                        Metadata* method_data, bool profile_rtm,
1488                                        Label& DONE_LABEL, Label& IsInflated) {
1489   assert(UseRTMForStackLocks, "why call this otherwise?");
1490   assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1491   assert(tmpReg == rax, "");
1492   assert(scrReg == rdx, "");
1493   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1494 
1495   if (RTMRetryCount > 0) {
1496     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1497     bind(L_rtm_retry);
1498   }
1499   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1500   testptr(tmpReg, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
1501   jcc(Assembler::notZero, IsInflated);
1502 
1503   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1504     Label L_noincrement;
1505     if (RTMTotalCountIncrRate > 1) {
1506       // tmpReg, scrReg and flags are killed
1507       branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1508     }
1509     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1510     atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1511     bind(L_noincrement);
1512   }
1513   xbegin(L_on_abort);
1514   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));       // fetch markword
1515   andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1516   cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1517   jcc(Assembler::equal, DONE_LABEL);        // all done if unlocked
1518 
1519   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1520   if (UseRTMXendForLockBusy) {
1521     xend();
1522     movptr(abort_status_Reg, 0x2);   // Set the abort status to 2 (so we can retry)
1523     jmp(L_decrement_retry);
1524   }
1525   else {
1526     xabort(0);
1527   }
1528   bind(L_on_abort);
1529   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1530     rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1531   }
1532   bind(L_decrement_retry);
1533   if (RTMRetryCount > 0) {
1534     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1535     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1536   }
1537 }
1538 
1539 // Use RTM for inflating locks
1540 // inputs: objReg (object to lock)
1541 //         boxReg (on-stack box address (displaced header location) - KILLED)
1542 //         tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1543 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1544                                           Register scrReg, Register retry_on_busy_count_Reg,
1545                                           Register retry_on_abort_count_Reg,
1546                                           RTMLockingCounters* rtm_counters,
1547                                           Metadata* method_data, bool profile_rtm,
1548                                           Label& DONE_LABEL) {
1549   assert(UseRTMLocking, "why call this otherwise?");
1550   assert(tmpReg == rax, "");
1551   assert(scrReg == rdx, "");
1552   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1553   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1554 
1555   // Without cast to int32_t a movptr will destroy r10 which is typically obj
1556   movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1557   movptr(boxReg, tmpReg); // Save ObjectMonitor address
1558 
1559   if (RTMRetryCount > 0) {
1560     movl(retry_on_busy_count_Reg, RTMRetryCount);  // Retry on lock busy
1561     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1562     bind(L_rtm_retry);
1563   }
1564   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1565     Label L_noincrement;
1566     if (RTMTotalCountIncrRate > 1) {
1567       // tmpReg, scrReg and flags are killed
1568       branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1569     }
1570     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1571     atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1572     bind(L_noincrement);
1573   }
1574   xbegin(L_on_abort);
1575   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1576   movptr(tmpReg, Address(tmpReg, owner_offset));
1577   testptr(tmpReg, tmpReg);
1578   jcc(Assembler::zero, DONE_LABEL);
1579   if (UseRTMXendForLockBusy) {
1580     xend();
1581     jmp(L_decrement_retry);
1582   }
1583   else {
1584     xabort(0);
1585   }
1586   bind(L_on_abort);
1587   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1588   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1589     rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1590   }
1591   if (RTMRetryCount > 0) {
1592     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1593     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1594   }
1595 
1596   movptr(tmpReg, Address(boxReg, owner_offset)) ;
1597   testptr(tmpReg, tmpReg) ;
1598   jccb(Assembler::notZero, L_decrement_retry) ;
1599 
1600   // Appears unlocked - try to swing _owner from null to non-null.
1601   // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1602 #ifdef _LP64
1603   Register threadReg = r15_thread;
1604 #else
1605   get_thread(scrReg);
1606   Register threadReg = scrReg;
1607 #endif
1608   if (os::is_MP()) {
1609     lock();
1610   }
1611   cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1612 
1613   if (RTMRetryCount > 0) {
1614     // success done else retry
1615     jccb(Assembler::equal, DONE_LABEL) ;
1616     bind(L_decrement_retry);
1617     // Spin and retry if lock is busy.
1618     rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1619   }
1620   else {
1621     bind(L_decrement_retry);
1622   }
1623 }
1624 
1625 #endif //  INCLUDE_RTM_OPT
1626 
1627 // Fast_Lock and Fast_Unlock used by C2
1628 
1629 // Because the transitions from emitted code to the runtime
1630 // monitorenter/exit helper stubs are so slow it's critical that
1631 // we inline both the stack-locking fast-path and the inflated fast path.
1632 //
1633 // See also: cmpFastLock and cmpFastUnlock.
1634 //
1635 // What follows is a specialized inline transliteration of the code
1636 // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
1637 // another option would be to emit TrySlowEnter and TrySlowExit methods
1638 // at startup-time.  These methods would accept arguments as
1639 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1640 // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
1641 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1642 // In practice, however, the # of lock sites is bounded and is usually small.
1643 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1644 // if the processor uses simple bimodal branch predictors keyed by EIP
1645 // Since the helper routines would be called from multiple synchronization
1646 // sites.
1647 //
1648 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1649 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1650 // to those specialized methods.  That'd give us a mostly platform-independent
1651 // implementation that the JITs could optimize and inline at their pleasure.
1652 // Done correctly, the only time we'd need to cross to native could would be
1653 // to park() or unpark() threads.  We'd also need a few more unsafe operators
1654 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1655 // (b) explicit barriers or fence operations.
1656 //
1657 // TODO:
1658 //
1659 // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1660 //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1661 //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
1662 //    the lock operators would typically be faster than reifying Self.
1663 //
1664 // *  Ideally I'd define the primitives as:
1665 //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1666 //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1667 //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
1668 //    Instead, we're stuck with a rather awkward and brittle register assignments below.
1669 //    Furthermore the register assignments are overconstrained, possibly resulting in
1670 //    sub-optimal code near the synchronization site.
1671 //
1672 // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
1673 //    Alternately, use a better sp-proximity test.
1674 //
1675 // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1676 //    Either one is sufficient to uniquely identify a thread.
1677 //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1678 //
1679 // *  Intrinsify notify() and notifyAll() for the common cases where the
1680 //    object is locked by the calling thread but the waitlist is empty.
1681 //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1682 //
1683 // *  use jccb and jmpb instead of jcc and jmp to improve code density.
1684 //    But beware of excessive branch density on AMD Opterons.
1685 //
1686 // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1687 //    or failure of the fast-path.  If the fast-path fails then we pass
1688 //    control to the slow-path, typically in C.  In Fast_Lock and
1689 //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1690 //    will emit a conditional branch immediately after the node.
1691 //    So we have branches to branches and lots of ICC.ZF games.
1692 //    Instead, it might be better to have C2 pass a "FailureLabel"
1693 //    into Fast_Lock and Fast_Unlock.  In the case of success, control
1694 //    will drop through the node.  ICC.ZF is undefined at exit.
1695 //    In the case of failure, the node will branch directly to the
1696 //    FailureLabel
1697 
1698 
1699 // obj: object to lock
1700 // box: on-stack box address (displaced header location) - KILLED
1701 // rax,: tmp -- KILLED
1702 // scr: tmp -- KILLED
1703 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1704                                Register scrReg, Register cx1Reg, Register cx2Reg,
1705                                BiasedLockingCounters* counters,
1706                                RTMLockingCounters* rtm_counters,
1707                                RTMLockingCounters* stack_rtm_counters,
1708                                Metadata* method_data,
1709                                bool use_rtm, bool profile_rtm) {
1710   // Ensure the register assignments are disjoint
1711   assert(tmpReg == rax, "");
1712 
1713   if (use_rtm) {
1714     assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1715   } else {
1716     assert(cx1Reg == noreg, "");
1717     assert(cx2Reg == noreg, "");
1718     assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1719   }
1720 
1721   if (counters != NULL) {
1722     atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1723   }
1724   if (EmitSync & 1) {
1725       // set box->dhw = markOopDesc::unused_mark()
1726       // Force all sync thru slow-path: slow_enter() and slow_exit()
1727       movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1728       cmpptr (rsp, (int32_t)NULL_WORD);
1729   } else {
1730     // Possible cases that we'll encounter in fast_lock
1731     // ------------------------------------------------
1732     // * Inflated
1733     //    -- unlocked
1734     //    -- Locked
1735     //       = by self
1736     //       = by other
1737     // * biased
1738     //    -- by Self
1739     //    -- by other
1740     // * neutral
1741     // * stack-locked
1742     //    -- by self
1743     //       = sp-proximity test hits
1744     //       = sp-proximity test generates false-negative
1745     //    -- by other
1746     //
1747 
1748     Label IsInflated, DONE_LABEL;
1749 
1750     // it's stack-locked, biased or neutral
1751     // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1752     // order to reduce the number of conditional branches in the most common cases.
1753     // Beware -- there's a subtle invariant that fetch of the markword
1754     // at [FETCH], below, will never observe a biased encoding (*101b).
1755     // If this invariant is not held we risk exclusion (safety) failure.
1756     if (UseBiasedLocking && !UseOptoBiasInlining) {
1757       biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1758     }
1759 
1760 #if INCLUDE_RTM_OPT
1761     if (UseRTMForStackLocks && use_rtm) {
1762       rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1763                         stack_rtm_counters, method_data, profile_rtm,
1764                         DONE_LABEL, IsInflated);
1765     }
1766 #endif // INCLUDE_RTM_OPT
1767 
1768     movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));          // [FETCH]
1769     testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1770     jccb(Assembler::notZero, IsInflated);
1771 
1772     // Attempt stack-locking ...
1773     orptr (tmpReg, markOopDesc::unlocked_value);
1774     movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
1775     if (os::is_MP()) {
1776       lock();
1777     }
1778     cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes()));      // Updates tmpReg
1779     if (counters != NULL) {
1780       cond_inc32(Assembler::equal,
1781                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1782     }
1783     jcc(Assembler::equal, DONE_LABEL);           // Success
1784 
1785     // Recursive locking.
1786     // The object is stack-locked: markword contains stack pointer to BasicLock.
1787     // Locked by current thread if difference with current SP is less than one page.
1788     subptr(tmpReg, rsp);
1789     // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1790     andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1791     movptr(Address(boxReg, 0), tmpReg);
1792     if (counters != NULL) {
1793       cond_inc32(Assembler::equal,
1794                  ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795     }
1796     jmp(DONE_LABEL);
1797 
1798     bind(IsInflated);
1799     // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1800 
1801 #if INCLUDE_RTM_OPT
1802     // Use the same RTM locking code in 32- and 64-bit VM.
1803     if (use_rtm) {
1804       rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1805                            rtm_counters, method_data, profile_rtm, DONE_LABEL);
1806     } else {
1807 #endif // INCLUDE_RTM_OPT
1808 
1809 #ifndef _LP64
1810     // The object is inflated.
1811 
1812     // boxReg refers to the on-stack BasicLock in the current frame.
1813     // We'd like to write:
1814     //   set box->_displaced_header = markOopDesc::unused_mark().  Any non-0 value suffices.
1815     // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
1816     // additional latency as we have another ST in the store buffer that must drain.
1817 
1818     if (EmitSync & 8192) {
1819        movptr(Address(boxReg, 0), 3);            // results in ST-before-CAS penalty
1820        get_thread (scrReg);
1821        movptr(boxReg, tmpReg);                    // consider: LEA box, [tmp-2]
1822        movptr(tmpReg, NULL_WORD);                 // consider: xor vs mov
1823        if (os::is_MP()) {
1824          lock();
1825        }
1826        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1827     } else
1828     if ((EmitSync & 128) == 0) {                      // avoid ST-before-CAS
1829        // register juggle because we need tmpReg for cmpxchgptr below
1830        movptr(scrReg, boxReg);
1831        movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2]
1832 
1833        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1834        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1835           // prefetchw [eax + Offset(_owner)-2]
1836           prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1837        }
1838 
1839        if ((EmitSync & 64) == 0) {
1840          // Optimistic form: consider XORL tmpReg,tmpReg
1841          movptr(tmpReg, NULL_WORD);
1842        } else {
1843          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1844          // Test-And-CAS instead of CAS
1845          movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));   // rax, = m->_owner
1846          testptr(tmpReg, tmpReg);                   // Locked ?
1847          jccb  (Assembler::notZero, DONE_LABEL);
1848        }
1849 
1850        // Appears unlocked - try to swing _owner from null to non-null.
1851        // Ideally, I'd manifest "Self" with get_thread and then attempt
1852        // to CAS the register containing Self into m->Owner.
1853        // But we don't have enough registers, so instead we can either try to CAS
1854        // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
1855        // we later store "Self" into m->Owner.  Transiently storing a stack address
1856        // (rsp or the address of the box) into  m->owner is harmless.
1857        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1858        if (os::is_MP()) {
1859          lock();
1860        }
1861        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1862        movptr(Address(scrReg, 0), 3);          // box->_displaced_header = 3
1863        // If we weren't able to swing _owner from NULL to the BasicLock
1864        // then take the slow path.
1865        jccb  (Assembler::notZero, DONE_LABEL);
1866        // update _owner from BasicLock to thread
1867        get_thread (scrReg);                    // beware: clobbers ICCs
1868        movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1869        xorptr(boxReg, boxReg);                 // set icc.ZFlag = 1 to indicate success
1870 
1871        // If the CAS fails we can either retry or pass control to the slow-path.
1872        // We use the latter tactic.
1873        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1874        // If the CAS was successful ...
1875        //   Self has acquired the lock
1876        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1877        // Intentional fall-through into DONE_LABEL ...
1878     } else {
1879        movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark()));  // results in ST-before-CAS penalty
1880        movptr(boxReg, tmpReg);
1881 
1882        // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1883        if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1884           // prefetchw [eax + Offset(_owner)-2]
1885           prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1886        }
1887 
1888        if ((EmitSync & 64) == 0) {
1889          // Optimistic form
1890          xorptr  (tmpReg, tmpReg);
1891        } else {
1892          // Can suffer RTS->RTO upgrades on shared or cold $ lines
1893          movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));   // rax, = m->_owner
1894          testptr(tmpReg, tmpReg);                   // Locked ?
1895          jccb  (Assembler::notZero, DONE_LABEL);
1896        }
1897 
1898        // Appears unlocked - try to swing _owner from null to non-null.
1899        // Use either "Self" (in scr) or rsp as thread identity in _owner.
1900        // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1901        get_thread (scrReg);
1902        if (os::is_MP()) {
1903          lock();
1904        }
1905        cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1906 
1907        // If the CAS fails we can either retry or pass control to the slow-path.
1908        // We use the latter tactic.
1909        // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1910        // If the CAS was successful ...
1911        //   Self has acquired the lock
1912        //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1913        // Intentional fall-through into DONE_LABEL ...
1914     }
1915 #else // _LP64
1916     // It's inflated
1917     movq(scrReg, tmpReg);
1918     xorq(tmpReg, tmpReg);
1919 
1920     if (os::is_MP()) {
1921       lock();
1922     }
1923     cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1924     // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1925     // Without cast to int32_t movptr will destroy r10 which is typically obj.
1926     movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1927     // Intentional fall-through into DONE_LABEL ...
1928     // Propagate ICC.ZF from CAS above into DONE_LABEL.
1929 #endif // _LP64
1930 #if INCLUDE_RTM_OPT
1931     } // use_rtm()
1932 #endif
1933     // DONE_LABEL is a hot target - we'd really like to place it at the
1934     // start of cache line by padding with NOPs.
1935     // See the AMD and Intel software optimization manuals for the
1936     // most efficient "long" NOP encodings.
1937     // Unfortunately none of our alignment mechanisms suffice.
1938     bind(DONE_LABEL);
1939 
1940     // At DONE_LABEL the icc ZFlag is set as follows ...
1941     // Fast_Unlock uses the same protocol.
1942     // ZFlag == 1 -> Success
1943     // ZFlag == 0 -> Failure - force control through the slow-path
1944   }
1945 }
1946 
1947 // obj: object to unlock
1948 // box: box address (displaced header location), killed.  Must be EAX.
1949 // tmp: killed, cannot be obj nor box.
1950 //
1951 // Some commentary on balanced locking:
1952 //
1953 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1954 // Methods that don't have provably balanced locking are forced to run in the
1955 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1956 // The interpreter provides two properties:
1957 // I1:  At return-time the interpreter automatically and quietly unlocks any
1958 //      objects acquired the current activation (frame).  Recall that the
1959 //      interpreter maintains an on-stack list of locks currently held by
1960 //      a frame.
1961 // I2:  If a method attempts to unlock an object that is not held by the
1962 //      the frame the interpreter throws IMSX.
1963 //
1964 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1965 // B() doesn't have provably balanced locking so it runs in the interpreter.
1966 // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
1967 // is still locked by A().
1968 //
1969 // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
1970 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1971 // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
1972 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1973 // Arguably given that the spec legislates the JNI case as undefined our implementation
1974 // could reasonably *avoid* checking owner in Fast_Unlock().
1975 // In the interest of performance we elide m->Owner==Self check in unlock.
1976 // A perfectly viable alternative is to elide the owner check except when
1977 // Xcheck:jni is enabled.
1978 
1979 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1980   assert(boxReg == rax, "");
1981   assert_different_registers(objReg, boxReg, tmpReg);
1982 
1983   if (EmitSync & 4) {
1984     // Disable - inhibit all inlining.  Force control through the slow-path
1985     cmpptr (rsp, 0);
1986   } else {
1987     Label DONE_LABEL, Stacked, CheckSucc;
1988 
1989     // Critically, the biased locking test must have precedence over
1990     // and appear before the (box->dhw == 0) recursive stack-lock test.
1991     if (UseBiasedLocking && !UseOptoBiasInlining) {
1992        biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1993     }
1994 
1995 #if INCLUDE_RTM_OPT
1996     if (UseRTMForStackLocks && use_rtm) {
1997       assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1998       Label L_regular_unlock;
1999       movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));           // fetch markword
2000       andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2001       cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
2002       jccb(Assembler::notEqual, L_regular_unlock);  // if !HLE RegularLock
2003       xend();                                       // otherwise end...
2004       jmp(DONE_LABEL);                              // ... and we're done
2005       bind(L_regular_unlock);
2006     }
2007 #endif
2008 
2009     cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2010     jcc   (Assembler::zero, DONE_LABEL);            // 0 indicates recursive stack-lock
2011     movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));             // Examine the object's markword
2012     testptr(tmpReg, markOopDesc::monitor_value);    // Inflated?
2013     jccb  (Assembler::zero, Stacked);
2014 
2015     // It's inflated.
2016 #if INCLUDE_RTM_OPT
2017     if (use_rtm) {
2018       Label L_regular_inflated_unlock;
2019       int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2020       movptr(boxReg, Address(tmpReg, owner_offset));
2021       testptr(boxReg, boxReg);
2022       jccb(Assembler::notZero, L_regular_inflated_unlock);
2023       xend();
2024       jmpb(DONE_LABEL);
2025       bind(L_regular_inflated_unlock);
2026     }
2027 #endif
2028 
2029     // Despite our balanced locking property we still check that m->_owner == Self
2030     // as java routines or native JNI code called by this thread might
2031     // have released the lock.
2032     // Refer to the comments in synchronizer.cpp for how we might encode extra
2033     // state in _succ so we can avoid fetching EntryList|cxq.
2034     //
2035     // I'd like to add more cases in fast_lock() and fast_unlock() --
2036     // such as recursive enter and exit -- but we have to be wary of
2037     // I$ bloat, T$ effects and BP$ effects.
2038     //
2039     // If there's no contention try a 1-0 exit.  That is, exit without
2040     // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
2041     // we detect and recover from the race that the 1-0 exit admits.
2042     //
2043     // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2044     // before it STs null into _owner, releasing the lock.  Updates
2045     // to data protected by the critical section must be visible before
2046     // we drop the lock (and thus before any other thread could acquire
2047     // the lock and observe the fields protected by the lock).
2048     // IA32's memory-model is SPO, so STs are ordered with respect to
2049     // each other and there's no need for an explicit barrier (fence).
2050     // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2051 #ifndef _LP64
2052     get_thread (boxReg);
2053     if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2054       // prefetchw [ebx + Offset(_owner)-2]
2055       prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2056     }
2057 
2058     // Note that we could employ various encoding schemes to reduce
2059     // the number of loads below (currently 4) to just 2 or 3.
2060     // Refer to the comments in synchronizer.cpp.
2061     // In practice the chain of fetches doesn't seem to impact performance, however.
2062     xorptr(boxReg, boxReg);
2063     if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2064        // Attempt to reduce branch density - AMD's branch predictor.
2065        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2066        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2067        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2068        jccb  (Assembler::notZero, DONE_LABEL);
2069        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2070        jmpb  (DONE_LABEL);
2071     } else {
2072        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2073        jccb  (Assembler::notZero, DONE_LABEL);
2074        movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2075        orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2076        jccb  (Assembler::notZero, CheckSucc);
2077        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2078        jmpb  (DONE_LABEL);
2079     }
2080 
2081     // The Following code fragment (EmitSync & 65536) improves the performance of
2082     // contended applications and contended synchronization microbenchmarks.
2083     // Unfortunately the emission of the code - even though not executed - causes regressions
2084     // in scimark and jetstream, evidently because of $ effects.  Replacing the code
2085     // with an equal number of never-executed NOPs results in the same regression.
2086     // We leave it off by default.
2087 
2088     if ((EmitSync & 65536) != 0) {
2089        Label LSuccess, LGoSlowPath ;
2090 
2091        bind  (CheckSucc);
2092 
2093        // Optional pre-test ... it's safe to elide this
2094        cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2095        jccb(Assembler::zero, LGoSlowPath);
2096 
2097        // We have a classic Dekker-style idiom:
2098        //    ST m->_owner = 0 ; MEMBAR; LD m->_succ
2099        // There are a number of ways to implement the barrier:
2100        // (1) lock:andl &m->_owner, 0
2101        //     is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2102        //     LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2103        //     Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2104        // (2) If supported, an explicit MFENCE is appealing.
2105        //     In older IA32 processors MFENCE is slower than lock:add or xchg
2106        //     particularly if the write-buffer is full as might be the case if
2107        //     if stores closely precede the fence or fence-equivalent instruction.
2108        //     See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2109        //     as the situation has changed with Nehalem and Shanghai.
2110        // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2111        //     The $lines underlying the top-of-stack should be in M-state.
2112        //     The locked add instruction is serializing, of course.
2113        // (4) Use xchg, which is serializing
2114        //     mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2115        // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2116        //     The integer condition codes will tell us if succ was 0.
2117        //     Since _succ and _owner should reside in the same $line and
2118        //     we just stored into _owner, it's likely that the $line
2119        //     remains in M-state for the lock:orl.
2120        //
2121        // We currently use (3), although it's likely that switching to (2)
2122        // is correct for the future.
2123 
2124        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2125        if (os::is_MP()) {
2126          lock(); addptr(Address(rsp, 0), 0);
2127        }
2128        // Ratify _succ remains non-null
2129        cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2130        jccb  (Assembler::notZero, LSuccess);
2131 
2132        xorptr(boxReg, boxReg);                  // box is really EAX
2133        if (os::is_MP()) { lock(); }
2134        cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2135        // There's no successor so we tried to regrab the lock with the
2136        // placeholder value. If that didn't work, then another thread
2137        // grabbed the lock so we're done (and exit was a success).
2138        jccb  (Assembler::notEqual, LSuccess);
2139        // Since we're low on registers we installed rsp as a placeholding in _owner.
2140        // Now install Self over rsp.  This is safe as we're transitioning from
2141        // non-null to non=null
2142        get_thread (boxReg);
2143        movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2144        // Intentional fall-through into LGoSlowPath ...
2145 
2146        bind  (LGoSlowPath);
2147        orptr(boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2148        jmpb  (DONE_LABEL);
2149 
2150        bind  (LSuccess);
2151        xorptr(boxReg, boxReg);                 // set ICC.ZF=1 to indicate success
2152        jmpb  (DONE_LABEL);
2153     }
2154 
2155     bind (Stacked);
2156     // It's not inflated and it's not recursively stack-locked and it's not biased.
2157     // It must be stack-locked.
2158     // Try to reset the header to displaced header.
2159     // The "box" value on the stack is stable, so we can reload
2160     // and be assured we observe the same value as above.
2161     movptr(tmpReg, Address(boxReg, 0));
2162     if (os::is_MP()) {
2163       lock();
2164     }
2165     cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2166     // Intention fall-thru into DONE_LABEL
2167 
2168     // DONE_LABEL is a hot target - we'd really like to place it at the
2169     // start of cache line by padding with NOPs.
2170     // See the AMD and Intel software optimization manuals for the
2171     // most efficient "long" NOP encodings.
2172     // Unfortunately none of our alignment mechanisms suffice.
2173     if ((EmitSync & 65536) == 0) {
2174        bind (CheckSucc);
2175     }
2176 #else // _LP64
2177     // It's inflated
2178     if (EmitSync & 1024) {
2179       // Emit code to check that _owner == Self
2180       // We could fold the _owner test into subsequent code more efficiently
2181       // than using a stand-alone check, but since _owner checking is off by
2182       // default we don't bother. We also might consider predicating the
2183       // _owner==Self check on Xcheck:jni or running on a debug build.
2184       movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2185       xorptr(boxReg, r15_thread);
2186     } else {
2187       xorptr(boxReg, boxReg);
2188     }
2189     orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2190     jccb  (Assembler::notZero, DONE_LABEL);
2191     movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2192     orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2193     jccb  (Assembler::notZero, CheckSucc);
2194     movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2195     jmpb  (DONE_LABEL);
2196 
2197     if ((EmitSync & 65536) == 0) {
2198       // Try to avoid passing control into the slow_path ...
2199       Label LSuccess, LGoSlowPath ;
2200       bind  (CheckSucc);
2201 
2202       // The following optional optimization can be elided if necessary
2203       // Effectively: if (succ == null) goto SlowPath
2204       // The code reduces the window for a race, however,
2205       // and thus benefits performance.
2206       cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2207       jccb  (Assembler::zero, LGoSlowPath);
2208 
2209       xorptr(boxReg, boxReg);
2210       if ((EmitSync & 16) && os::is_MP()) {
2211         xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2212       } else {
2213         movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2214         if (os::is_MP()) {
2215           // Memory barrier/fence
2216           // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2217           // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2218           // This is faster on Nehalem and AMD Shanghai/Barcelona.
2219           // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2220           // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2221           // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2222           lock(); addl(Address(rsp, 0), 0);
2223         }
2224       }
2225       cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2226       jccb  (Assembler::notZero, LSuccess);
2227 
2228       // Rare inopportune interleaving - race.
2229       // The successor vanished in the small window above.
2230       // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2231       // We need to ensure progress and succession.
2232       // Try to reacquire the lock.
2233       // If that fails then the new owner is responsible for succession and this
2234       // thread needs to take no further action and can exit via the fast path (success).
2235       // If the re-acquire succeeds then pass control into the slow path.
2236       // As implemented, this latter mode is horrible because we generated more
2237       // coherence traffic on the lock *and* artifically extended the critical section
2238       // length while by virtue of passing control into the slow path.
2239 
2240       // box is really RAX -- the following CMPXCHG depends on that binding
2241       // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2242       if (os::is_MP()) { lock(); }
2243       cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2244       // There's no successor so we tried to regrab the lock.
2245       // If that didn't work, then another thread grabbed the
2246       // lock so we're done (and exit was a success).
2247       jccb  (Assembler::notEqual, LSuccess);
2248       // Intentional fall-through into slow-path
2249 
2250       bind  (LGoSlowPath);
2251       orl   (boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2252       jmpb  (DONE_LABEL);
2253 
2254       bind  (LSuccess);
2255       testl (boxReg, 0);                      // set ICC.ZF=1 to indicate success
2256       jmpb  (DONE_LABEL);
2257     }
2258 
2259     bind  (Stacked);
2260     movptr(tmpReg, Address (boxReg, 0));      // re-fetch
2261     if (os::is_MP()) { lock(); }
2262     cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2263 
2264     if (EmitSync & 65536) {
2265        bind (CheckSucc);
2266     }
2267 #endif
2268     bind(DONE_LABEL);
2269   }
2270 }
2271 #endif // COMPILER2
2272 
2273 void MacroAssembler::c2bool(Register x) {
2274   // implements x == 0 ? 0 : 1
2275   // note: must only look at least-significant byte of x
2276   //       since C-style booleans are stored in one byte
2277   //       only! (was bug)
2278   andl(x, 0xFF);
2279   setb(Assembler::notZero, x);
2280 }
2281 
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284   Assembler::call(L, rtype);
2285 }
2286 
2287 void MacroAssembler::call(Register entry) {
2288   Assembler::call(entry);
2289 }
2290 
2291 void MacroAssembler::call(AddressLiteral entry) {
2292   if (reachable(entry)) {
2293     Assembler::call_literal(entry.target(), entry.rspec());
2294   } else {
2295     lea(rscratch1, entry);
2296     Assembler::call(rscratch1);
2297   }
2298 }
2299 
2300 void MacroAssembler::ic_call(address entry, jint method_index) {
2301   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2302   movptr(rax, (intptr_t)Universe::non_oop_word());
2303   call(AddressLiteral(entry, rh));
2304 }
2305 
2306 // Implementation of call_VM versions
2307 
2308 void MacroAssembler::call_VM(Register oop_result,
2309                              address entry_point,
2310                              bool check_exceptions) {
2311   Label C, E;
2312   call(C, relocInfo::none);
2313   jmp(E);
2314 
2315   bind(C);
2316   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317   ret(0);
2318 
2319   bind(E);
2320 }
2321 
2322 void MacroAssembler::call_VM(Register oop_result,
2323                              address entry_point,
2324                              Register arg_1,
2325                              bool check_exceptions) {
2326   Label C, E;
2327   call(C, relocInfo::none);
2328   jmp(E);
2329 
2330   bind(C);
2331   pass_arg1(this, arg_1);
2332   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333   ret(0);
2334 
2335   bind(E);
2336 }
2337 
2338 void MacroAssembler::call_VM(Register oop_result,
2339                              address entry_point,
2340                              Register arg_1,
2341                              Register arg_2,
2342                              bool check_exceptions) {
2343   Label C, E;
2344   call(C, relocInfo::none);
2345   jmp(E);
2346 
2347   bind(C);
2348 
2349   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350 
2351   pass_arg2(this, arg_2);
2352   pass_arg1(this, arg_1);
2353   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354   ret(0);
2355 
2356   bind(E);
2357 }
2358 
2359 void MacroAssembler::call_VM(Register oop_result,
2360                              address entry_point,
2361                              Register arg_1,
2362                              Register arg_2,
2363                              Register arg_3,
2364                              bool check_exceptions) {
2365   Label C, E;
2366   call(C, relocInfo::none);
2367   jmp(E);
2368 
2369   bind(C);
2370 
2371   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373   pass_arg3(this, arg_3);
2374 
2375   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376   pass_arg2(this, arg_2);
2377 
2378   pass_arg1(this, arg_1);
2379   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380   ret(0);
2381 
2382   bind(E);
2383 }
2384 
2385 void MacroAssembler::call_VM(Register oop_result,
2386                              Register last_java_sp,
2387                              address entry_point,
2388                              int number_of_arguments,
2389                              bool check_exceptions) {
2390   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393 
2394 void MacroAssembler::call_VM(Register oop_result,
2395                              Register last_java_sp,
2396                              address entry_point,
2397                              Register arg_1,
2398                              bool check_exceptions) {
2399   pass_arg1(this, arg_1);
2400   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402 
2403 void MacroAssembler::call_VM(Register oop_result,
2404                              Register last_java_sp,
2405                              address entry_point,
2406                              Register arg_1,
2407                              Register arg_2,
2408                              bool check_exceptions) {
2409 
2410   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411   pass_arg2(this, arg_2);
2412   pass_arg1(this, arg_1);
2413   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415 
2416 void MacroAssembler::call_VM(Register oop_result,
2417                              Register last_java_sp,
2418                              address entry_point,
2419                              Register arg_1,
2420                              Register arg_2,
2421                              Register arg_3,
2422                              bool check_exceptions) {
2423   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425   pass_arg3(this, arg_3);
2426   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427   pass_arg2(this, arg_2);
2428   pass_arg1(this, arg_1);
2429   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431 
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433                                    Register last_java_sp,
2434                                    address entry_point,
2435                                    int number_of_arguments,
2436                                    bool check_exceptions) {
2437   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440 
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442                                    Register last_java_sp,
2443                                    address entry_point,
2444                                    Register arg_1,
2445                                    bool check_exceptions) {
2446   pass_arg1(this, arg_1);
2447   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449 
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451                                    Register last_java_sp,
2452                                    address entry_point,
2453                                    Register arg_1,
2454                                    Register arg_2,
2455                                    bool check_exceptions) {
2456 
2457   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458   pass_arg2(this, arg_2);
2459   pass_arg1(this, arg_1);
2460   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462 
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464                                    Register last_java_sp,
2465                                    address entry_point,
2466                                    Register arg_1,
2467                                    Register arg_2,
2468                                    Register arg_3,
2469                                    bool check_exceptions) {
2470   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472   pass_arg3(this, arg_3);
2473   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474   pass_arg2(this, arg_2);
2475   pass_arg1(this, arg_1);
2476   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478 
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480                                   Register java_thread,
2481                                   Register last_java_sp,
2482                                   address  entry_point,
2483                                   int      number_of_arguments,
2484                                   bool     check_exceptions) {
2485   // determine java_thread register
2486   if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488     java_thread = r15_thread;
2489 #else
2490     java_thread = rdi;
2491     get_thread(java_thread);
2492 #endif // LP64
2493   }
2494   // determine last_java_sp register
2495   if (!last_java_sp->is_valid()) {
2496     last_java_sp = rsp;
2497   }
2498   // debugging support
2499   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
2500   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503   // r12 is the heapbase.
2504   LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506 
2507   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
2508   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509 
2510   // push java thread (becomes first argument of C function)
2511 
2512   NOT_LP64(push(java_thread); number_of_arguments++);
2513   LP64_ONLY(mov(c_rarg0, r15_thread));
2514 
2515   // set last Java frame before call
2516   assert(last_java_sp != rbp, "can't use ebp/rbp");
2517 
2518   // Only interpreter should have to set fp
2519   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520 
2521   // do the call, remove parameters
2522   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523 
2524   // restore the thread (cannot use the pushed argument since arguments
2525   // may be overwritten by C code generated by an optimizing compiler);
2526   // however can use the register value directly if it is callee saved.
2527   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528     // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530     guarantee(java_thread != rax, "change this code");
2531     push(rax);
2532     { Label L;
2533       get_thread(rax);
2534       cmpptr(java_thread, rax);
2535       jcc(Assembler::equal, L);
2536       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537       bind(L);
2538     }
2539     pop(rax);
2540 #endif
2541   } else {
2542     get_thread(java_thread);
2543   }
2544   // reset last Java frame
2545   // Only interpreter should have to clear fp
2546   reset_last_Java_frame(java_thread, true);
2547 
2548    // C++ interp handles this in the interpreter
2549   check_and_handle_popframe(java_thread);
2550   check_and_handle_earlyret(java_thread);
2551 
2552   if (check_exceptions) {
2553     // check for pending exceptions (java_thread is set upon return)
2554     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2555 #ifndef _LP64
2556     jump_cc(Assembler::notEqual,
2557             RuntimeAddress(StubRoutines::forward_exception_entry()));
2558 #else
2559     // This used to conditionally jump to forward_exception however it is
2560     // possible if we relocate that the branch will not reach. So we must jump
2561     // around so we can always reach
2562 
2563     Label ok;
2564     jcc(Assembler::equal, ok);
2565     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2566     bind(ok);
2567 #endif // LP64
2568   }
2569 
2570   // get oop result if there is one and reset the value in the thread
2571   if (oop_result->is_valid()) {
2572     get_vm_result(oop_result, java_thread);
2573   }
2574 }
2575 
2576 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2577 
2578   // Calculate the value for last_Java_sp
2579   // somewhat subtle. call_VM does an intermediate call
2580   // which places a return address on the stack just under the
2581   // stack pointer as the user finsihed with it. This allows
2582   // use to retrieve last_Java_pc from last_Java_sp[-1].
2583   // On 32bit we then have to push additional args on the stack to accomplish
2584   // the actual requested call. On 64bit call_VM only can use register args
2585   // so the only extra space is the return address that call_VM created.
2586   // This hopefully explains the calculations here.
2587 
2588 #ifdef _LP64
2589   // We've pushed one address, correct last_Java_sp
2590   lea(rax, Address(rsp, wordSize));
2591 #else
2592   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2593 #endif // LP64
2594 
2595   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2596 
2597 }
2598 
2599 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2600 void MacroAssembler::call_VM_leaf0(address entry_point) {
2601   MacroAssembler::call_VM_leaf_base(entry_point, 0);
2602 }
2603 
2604 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2605   call_VM_leaf_base(entry_point, number_of_arguments);
2606 }
2607 
2608 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2609   pass_arg0(this, arg_0);
2610   call_VM_leaf(entry_point, 1);
2611 }
2612 
2613 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2614 
2615   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2616   pass_arg1(this, arg_1);
2617   pass_arg0(this, arg_0);
2618   call_VM_leaf(entry_point, 2);
2619 }
2620 
2621 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2622   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2623   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2624   pass_arg2(this, arg_2);
2625   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2626   pass_arg1(this, arg_1);
2627   pass_arg0(this, arg_0);
2628   call_VM_leaf(entry_point, 3);
2629 }
2630 
2631 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2632   pass_arg0(this, arg_0);
2633   MacroAssembler::call_VM_leaf_base(entry_point, 1);
2634 }
2635 
2636 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2637 
2638   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2639   pass_arg1(this, arg_1);
2640   pass_arg0(this, arg_0);
2641   MacroAssembler::call_VM_leaf_base(entry_point, 2);
2642 }
2643 
2644 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2645   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647   pass_arg2(this, arg_2);
2648   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649   pass_arg1(this, arg_1);
2650   pass_arg0(this, arg_0);
2651   MacroAssembler::call_VM_leaf_base(entry_point, 3);
2652 }
2653 
2654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2655   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2656   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2657   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2658   pass_arg3(this, arg_3);
2659   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2660   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2661   pass_arg2(this, arg_2);
2662   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2663   pass_arg1(this, arg_1);
2664   pass_arg0(this, arg_0);
2665   MacroAssembler::call_VM_leaf_base(entry_point, 4);
2666 }
2667 
2668 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2669   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2670   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2671   verify_oop(oop_result, "broken oop in call_VM_base");
2672 }
2673 
2674 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2675   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2676   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2677 }
2678 
2679 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2680 }
2681 
2682 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2683 }
2684 
2685 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2686   if (reachable(src1)) {
2687     cmpl(as_Address(src1), imm);
2688   } else {
2689     lea(rscratch1, src1);
2690     cmpl(Address(rscratch1, 0), imm);
2691   }
2692 }
2693 
2694 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2695   assert(!src2.is_lval(), "use cmpptr");
2696   if (reachable(src2)) {
2697     cmpl(src1, as_Address(src2));
2698   } else {
2699     lea(rscratch1, src2);
2700     cmpl(src1, Address(rscratch1, 0));
2701   }
2702 }
2703 
2704 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2705   Assembler::cmpl(src1, imm);
2706 }
2707 
2708 void MacroAssembler::cmp32(Register src1, Address src2) {
2709   Assembler::cmpl(src1, src2);
2710 }
2711 
2712 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2713   ucomisd(opr1, opr2);
2714 
2715   Label L;
2716   if (unordered_is_less) {
2717     movl(dst, -1);
2718     jcc(Assembler::parity, L);
2719     jcc(Assembler::below , L);
2720     movl(dst, 0);
2721     jcc(Assembler::equal , L);
2722     increment(dst);
2723   } else { // unordered is greater
2724     movl(dst, 1);
2725     jcc(Assembler::parity, L);
2726     jcc(Assembler::above , L);
2727     movl(dst, 0);
2728     jcc(Assembler::equal , L);
2729     decrementl(dst);
2730   }
2731   bind(L);
2732 }
2733 
2734 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2735   ucomiss(opr1, opr2);
2736 
2737   Label L;
2738   if (unordered_is_less) {
2739     movl(dst, -1);
2740     jcc(Assembler::parity, L);
2741     jcc(Assembler::below , L);
2742     movl(dst, 0);
2743     jcc(Assembler::equal , L);
2744     increment(dst);
2745   } else { // unordered is greater
2746     movl(dst, 1);
2747     jcc(Assembler::parity, L);
2748     jcc(Assembler::above , L);
2749     movl(dst, 0);
2750     jcc(Assembler::equal , L);
2751     decrementl(dst);
2752   }
2753   bind(L);
2754 }
2755 
2756 
2757 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2758   if (reachable(src1)) {
2759     cmpb(as_Address(src1), imm);
2760   } else {
2761     lea(rscratch1, src1);
2762     cmpb(Address(rscratch1, 0), imm);
2763   }
2764 }
2765 
2766 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2767 #ifdef _LP64
2768   if (src2.is_lval()) {
2769     movptr(rscratch1, src2);
2770     Assembler::cmpq(src1, rscratch1);
2771   } else if (reachable(src2)) {
2772     cmpq(src1, as_Address(src2));
2773   } else {
2774     lea(rscratch1, src2);
2775     Assembler::cmpq(src1, Address(rscratch1, 0));
2776   }
2777 #else
2778   if (src2.is_lval()) {
2779     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780   } else {
2781     cmpl(src1, as_Address(src2));
2782   }
2783 #endif // _LP64
2784 }
2785 
2786 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2787   assert(src2.is_lval(), "not a mem-mem compare");
2788 #ifdef _LP64
2789   // moves src2's literal address
2790   movptr(rscratch1, src2);
2791   Assembler::cmpq(src1, rscratch1);
2792 #else
2793   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2794 #endif // _LP64
2795 }
2796 
2797 void MacroAssembler::cmpoop(Register src1, Register src2) {
2798   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2799   bs->obj_equals(this, src1, src2);
2800 }
2801 
2802 void MacroAssembler::cmpoop(Register src1, Address src2) {
2803   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2804   bs->obj_equals(this, src1, src2);
2805 }
2806 
2807 #ifdef _LP64
2808 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2809   movoop(rscratch1, src2);
2810   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2811   bs->obj_equals(this, src1, rscratch1);
2812 }
2813 #endif
2814 
2815 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2816   if (reachable(adr)) {
2817     if (os::is_MP())
2818       lock();
2819     cmpxchgptr(reg, as_Address(adr));
2820   } else {
2821     lea(rscratch1, adr);
2822     if (os::is_MP())
2823       lock();
2824     cmpxchgptr(reg, Address(rscratch1, 0));
2825   }
2826 }
2827 
2828 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2829   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2830 }
2831 
2832 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2833   if (reachable(src)) {
2834     Assembler::comisd(dst, as_Address(src));
2835   } else {
2836     lea(rscratch1, src);
2837     Assembler::comisd(dst, Address(rscratch1, 0));
2838   }
2839 }
2840 
2841 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2842   if (reachable(src)) {
2843     Assembler::comiss(dst, as_Address(src));
2844   } else {
2845     lea(rscratch1, src);
2846     Assembler::comiss(dst, Address(rscratch1, 0));
2847   }
2848 }
2849 
2850 
2851 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2852   Condition negated_cond = negate_condition(cond);
2853   Label L;
2854   jcc(negated_cond, L);
2855   pushf(); // Preserve flags
2856   atomic_incl(counter_addr);
2857   popf();
2858   bind(L);
2859 }
2860 
2861 int MacroAssembler::corrected_idivl(Register reg) {
2862   // Full implementation of Java idiv and irem; checks for
2863   // special case as described in JVM spec., p.243 & p.271.
2864   // The function returns the (pc) offset of the idivl
2865   // instruction - may be needed for implicit exceptions.
2866   //
2867   //         normal case                           special case
2868   //
2869   // input : rax,: dividend                         min_int
2870   //         reg: divisor   (may not be rax,/rdx)   -1
2871   //
2872   // output: rax,: quotient  (= rax, idiv reg)       min_int
2873   //         rdx: remainder (= rax, irem reg)       0
2874   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2875   const int min_int = 0x80000000;
2876   Label normal_case, special_case;
2877 
2878   // check for special case
2879   cmpl(rax, min_int);
2880   jcc(Assembler::notEqual, normal_case);
2881   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2882   cmpl(reg, -1);
2883   jcc(Assembler::equal, special_case);
2884 
2885   // handle normal case
2886   bind(normal_case);
2887   cdql();
2888   int idivl_offset = offset();
2889   idivl(reg);
2890 
2891   // normal and special case exit
2892   bind(special_case);
2893 
2894   return idivl_offset;
2895 }
2896 
2897 
2898 
2899 void MacroAssembler::decrementl(Register reg, int value) {
2900   if (value == min_jint) {subl(reg, value) ; return; }
2901   if (value <  0) { incrementl(reg, -value); return; }
2902   if (value == 0) {                        ; return; }
2903   if (value == 1 && UseIncDec) { decl(reg) ; return; }
2904   /* else */      { subl(reg, value)       ; return; }
2905 }
2906 
2907 void MacroAssembler::decrementl(Address dst, int value) {
2908   if (value == min_jint) {subl(dst, value) ; return; }
2909   if (value <  0) { incrementl(dst, -value); return; }
2910   if (value == 0) {                        ; return; }
2911   if (value == 1 && UseIncDec) { decl(dst) ; return; }
2912   /* else */      { subl(dst, value)       ; return; }
2913 }
2914 
2915 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2916   assert (shift_value > 0, "illegal shift value");
2917   Label _is_positive;
2918   testl (reg, reg);
2919   jcc (Assembler::positive, _is_positive);
2920   int offset = (1 << shift_value) - 1 ;
2921 
2922   if (offset == 1) {
2923     incrementl(reg);
2924   } else {
2925     addl(reg, offset);
2926   }
2927 
2928   bind (_is_positive);
2929   sarl(reg, shift_value);
2930 }
2931 
2932 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2933   if (reachable(src)) {
2934     Assembler::divsd(dst, as_Address(src));
2935   } else {
2936     lea(rscratch1, src);
2937     Assembler::divsd(dst, Address(rscratch1, 0));
2938   }
2939 }
2940 
2941 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2942   if (reachable(src)) {
2943     Assembler::divss(dst, as_Address(src));
2944   } else {
2945     lea(rscratch1, src);
2946     Assembler::divss(dst, Address(rscratch1, 0));
2947   }
2948 }
2949 
2950 // !defined(COMPILER2) is because of stupid core builds
2951 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2952 void MacroAssembler::empty_FPU_stack() {
2953   if (VM_Version::supports_mmx()) {
2954     emms();
2955   } else {
2956     for (int i = 8; i-- > 0; ) ffree(i);
2957   }
2958 }
2959 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2960 
2961 
2962 void MacroAssembler::enter() {
2963   push(rbp);
2964   mov(rbp, rsp);
2965 }
2966 
2967 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2968 void MacroAssembler::fat_nop() {
2969   if (UseAddressNop) {
2970     addr_nop_5();
2971   } else {
2972     emit_int8(0x26); // es:
2973     emit_int8(0x2e); // cs:
2974     emit_int8(0x64); // fs:
2975     emit_int8(0x65); // gs:
2976     emit_int8((unsigned char)0x90);
2977   }
2978 }
2979 
2980 void MacroAssembler::fcmp(Register tmp) {
2981   fcmp(tmp, 1, true, true);
2982 }
2983 
2984 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2985   assert(!pop_right || pop_left, "usage error");
2986   if (VM_Version::supports_cmov()) {
2987     assert(tmp == noreg, "unneeded temp");
2988     if (pop_left) {
2989       fucomip(index);
2990     } else {
2991       fucomi(index);
2992     }
2993     if (pop_right) {
2994       fpop();
2995     }
2996   } else {
2997     assert(tmp != noreg, "need temp");
2998     if (pop_left) {
2999       if (pop_right) {
3000         fcompp();
3001       } else {
3002         fcomp(index);
3003       }
3004     } else {
3005       fcom(index);
3006     }
3007     // convert FPU condition into eflags condition via rax,
3008     save_rax(tmp);
3009     fwait(); fnstsw_ax();
3010     sahf();
3011     restore_rax(tmp);
3012   }
3013   // condition codes set as follows:
3014   //
3015   // CF (corresponds to C0) if x < y
3016   // PF (corresponds to C2) if unordered
3017   // ZF (corresponds to C3) if x = y
3018 }
3019 
3020 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3021   fcmp2int(dst, unordered_is_less, 1, true, true);
3022 }
3023 
3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3025   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3026   Label L;
3027   if (unordered_is_less) {
3028     movl(dst, -1);
3029     jcc(Assembler::parity, L);
3030     jcc(Assembler::below , L);
3031     movl(dst, 0);
3032     jcc(Assembler::equal , L);
3033     increment(dst);
3034   } else { // unordered is greater
3035     movl(dst, 1);
3036     jcc(Assembler::parity, L);
3037     jcc(Assembler::above , L);
3038     movl(dst, 0);
3039     jcc(Assembler::equal , L);
3040     decrementl(dst);
3041   }
3042   bind(L);
3043 }
3044 
3045 void MacroAssembler::fld_d(AddressLiteral src) {
3046   fld_d(as_Address(src));
3047 }
3048 
3049 void MacroAssembler::fld_s(AddressLiteral src) {
3050   fld_s(as_Address(src));
3051 }
3052 
3053 void MacroAssembler::fld_x(AddressLiteral src) {
3054   Assembler::fld_x(as_Address(src));
3055 }
3056 
3057 void MacroAssembler::fldcw(AddressLiteral src) {
3058   Assembler::fldcw(as_Address(src));
3059 }
3060 
3061 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3062   if (reachable(src)) {
3063     Assembler::mulpd(dst, as_Address(src));
3064   } else {
3065     lea(rscratch1, src);
3066     Assembler::mulpd(dst, Address(rscratch1, 0));
3067   }
3068 }
3069 
3070 void MacroAssembler::increase_precision() {
3071   subptr(rsp, BytesPerWord);
3072   fnstcw(Address(rsp, 0));
3073   movl(rax, Address(rsp, 0));
3074   orl(rax, 0x300);
3075   push(rax);
3076   fldcw(Address(rsp, 0));
3077   pop(rax);
3078 }
3079 
3080 void MacroAssembler::restore_precision() {
3081   fldcw(Address(rsp, 0));
3082   addptr(rsp, BytesPerWord);
3083 }
3084 
3085 void MacroAssembler::fpop() {
3086   ffree();
3087   fincstp();
3088 }
3089 
3090 void MacroAssembler::load_float(Address src) {
3091   if (UseSSE >= 1) {
3092     movflt(xmm0, src);
3093   } else {
3094     LP64_ONLY(ShouldNotReachHere());
3095     NOT_LP64(fld_s(src));
3096   }
3097 }
3098 
3099 void MacroAssembler::store_float(Address dst) {
3100   if (UseSSE >= 1) {
3101     movflt(dst, xmm0);
3102   } else {
3103     LP64_ONLY(ShouldNotReachHere());
3104     NOT_LP64(fstp_s(dst));
3105   }
3106 }
3107 
3108 void MacroAssembler::load_double(Address src) {
3109   if (UseSSE >= 2) {
3110     movdbl(xmm0, src);
3111   } else {
3112     LP64_ONLY(ShouldNotReachHere());
3113     NOT_LP64(fld_d(src));
3114   }
3115 }
3116 
3117 void MacroAssembler::store_double(Address dst) {
3118   if (UseSSE >= 2) {
3119     movdbl(dst, xmm0);
3120   } else {
3121     LP64_ONLY(ShouldNotReachHere());
3122     NOT_LP64(fstp_d(dst));
3123   }
3124 }
3125 
3126 void MacroAssembler::fremr(Register tmp) {
3127   save_rax(tmp);
3128   { Label L;
3129     bind(L);
3130     fprem();
3131     fwait(); fnstsw_ax();
3132 #ifdef _LP64
3133     testl(rax, 0x400);
3134     jcc(Assembler::notEqual, L);
3135 #else
3136     sahf();
3137     jcc(Assembler::parity, L);
3138 #endif // _LP64
3139   }
3140   restore_rax(tmp);
3141   // Result is in ST0.
3142   // Note: fxch & fpop to get rid of ST1
3143   // (otherwise FPU stack could overflow eventually)
3144   fxch(1);
3145   fpop();
3146 }
3147 
3148 // dst = c = a * b + c
3149 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3150   Assembler::vfmadd231sd(c, a, b);
3151   if (dst != c) {
3152     movdbl(dst, c);
3153   }
3154 }
3155 
3156 // dst = c = a * b + c
3157 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3158   Assembler::vfmadd231ss(c, a, b);
3159   if (dst != c) {
3160     movflt(dst, c);
3161   }
3162 }
3163 
3164 // dst = c = a * b + c
3165 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3166   Assembler::vfmadd231pd(c, a, b, vector_len);
3167   if (dst != c) {
3168     vmovdqu(dst, c);
3169   }
3170 }
3171 
3172 // dst = c = a * b + c
3173 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
3174   Assembler::vfmadd231ps(c, a, b, vector_len);
3175   if (dst != c) {
3176     vmovdqu(dst, c);
3177   }
3178 }
3179 
3180 // dst = c = a * b + c
3181 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3182   Assembler::vfmadd231pd(c, a, b, vector_len);
3183   if (dst != c) {
3184     vmovdqu(dst, c);
3185   }
3186 }
3187 
3188 // dst = c = a * b + c
3189 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
3190   Assembler::vfmadd231ps(c, a, b, vector_len);
3191   if (dst != c) {
3192     vmovdqu(dst, c);
3193   }
3194 }
3195 
3196 void MacroAssembler::incrementl(AddressLiteral dst) {
3197   if (reachable(dst)) {
3198     incrementl(as_Address(dst));
3199   } else {
3200     lea(rscratch1, dst);
3201     incrementl(Address(rscratch1, 0));
3202   }
3203 }
3204 
3205 void MacroAssembler::incrementl(ArrayAddress dst) {
3206   incrementl(as_Address(dst));
3207 }
3208 
3209 void MacroAssembler::incrementl(Register reg, int value) {
3210   if (value == min_jint) {addl(reg, value) ; return; }
3211   if (value <  0) { decrementl(reg, -value); return; }
3212   if (value == 0) {                        ; return; }
3213   if (value == 1 && UseIncDec) { incl(reg) ; return; }
3214   /* else */      { addl(reg, value)       ; return; }
3215 }
3216 
3217 void MacroAssembler::incrementl(Address dst, int value) {
3218   if (value == min_jint) {addl(dst, value) ; return; }
3219   if (value <  0) { decrementl(dst, -value); return; }
3220   if (value == 0) {                        ; return; }
3221   if (value == 1 && UseIncDec) { incl(dst) ; return; }
3222   /* else */      { addl(dst, value)       ; return; }
3223 }
3224 
3225 void MacroAssembler::jump(AddressLiteral dst) {
3226   if (reachable(dst)) {
3227     jmp_literal(dst.target(), dst.rspec());
3228   } else {
3229     lea(rscratch1, dst);
3230     jmp(rscratch1);
3231   }
3232 }
3233 
3234 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3235   if (reachable(dst)) {
3236     InstructionMark im(this);
3237     relocate(dst.reloc());
3238     const int short_size = 2;
3239     const int long_size = 6;
3240     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3241     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3242       // 0111 tttn #8-bit disp
3243       emit_int8(0x70 | cc);
3244       emit_int8((offs - short_size) & 0xFF);
3245     } else {
3246       // 0000 1111 1000 tttn #32-bit disp
3247       emit_int8(0x0F);
3248       emit_int8((unsigned char)(0x80 | cc));
3249       emit_int32(offs - long_size);
3250     }
3251   } else {
3252 #ifdef ASSERT
3253     warning("reversing conditional branch");
3254 #endif /* ASSERT */
3255     Label skip;
3256     jccb(reverse[cc], skip);
3257     lea(rscratch1, dst);
3258     Assembler::jmp(rscratch1);
3259     bind(skip);
3260   }
3261 }
3262 
3263 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3264   if (reachable(src)) {
3265     Assembler::ldmxcsr(as_Address(src));
3266   } else {
3267     lea(rscratch1, src);
3268     Assembler::ldmxcsr(Address(rscratch1, 0));
3269   }
3270 }
3271 
3272 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3273   int off;
3274   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3275     off = offset();
3276     movsbl(dst, src); // movsxb
3277   } else {
3278     off = load_unsigned_byte(dst, src);
3279     shll(dst, 24);
3280     sarl(dst, 24);
3281   }
3282   return off;
3283 }
3284 
3285 // Note: load_signed_short used to be called load_signed_word.
3286 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3287 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3288 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3289 int MacroAssembler::load_signed_short(Register dst, Address src) {
3290   int off;
3291   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3292     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3293     // version but this is what 64bit has always done. This seems to imply
3294     // that users are only using 32bits worth.
3295     off = offset();
3296     movswl(dst, src); // movsxw
3297   } else {
3298     off = load_unsigned_short(dst, src);
3299     shll(dst, 16);
3300     sarl(dst, 16);
3301   }
3302   return off;
3303 }
3304 
3305 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3306   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3307   // and "3.9 Partial Register Penalties", p. 22).
3308   int off;
3309   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3310     off = offset();
3311     movzbl(dst, src); // movzxb
3312   } else {
3313     xorl(dst, dst);
3314     off = offset();
3315     movb(dst, src);
3316   }
3317   return off;
3318 }
3319 
3320 // Note: load_unsigned_short used to be called load_unsigned_word.
3321 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3322   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3323   // and "3.9 Partial Register Penalties", p. 22).
3324   int off;
3325   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3326     off = offset();
3327     movzwl(dst, src); // movzxw
3328   } else {
3329     xorl(dst, dst);
3330     off = offset();
3331     movw(dst, src);
3332   }
3333   return off;
3334 }
3335 
3336 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3337   switch (size_in_bytes) {
3338 #ifndef _LP64
3339   case  8:
3340     assert(dst2 != noreg, "second dest register required");
3341     movl(dst,  src);
3342     movl(dst2, src.plus_disp(BytesPerInt));
3343     break;
3344 #else
3345   case  8:  movq(dst, src); break;
3346 #endif
3347   case  4:  movl(dst, src); break;
3348   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3349   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3350   default:  ShouldNotReachHere();
3351   }
3352 }
3353 
3354 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3355   switch (size_in_bytes) {
3356 #ifndef _LP64
3357   case  8:
3358     assert(src2 != noreg, "second source register required");
3359     movl(dst,                        src);
3360     movl(dst.plus_disp(BytesPerInt), src2);
3361     break;
3362 #else
3363   case  8:  movq(dst, src); break;
3364 #endif
3365   case  4:  movl(dst, src); break;
3366   case  2:  movw(dst, src); break;
3367   case  1:  movb(dst, src); break;
3368   default:  ShouldNotReachHere();
3369   }
3370 }
3371 
3372 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3373   if (reachable(dst)) {
3374     movl(as_Address(dst), src);
3375   } else {
3376     lea(rscratch1, dst);
3377     movl(Address(rscratch1, 0), src);
3378   }
3379 }
3380 
3381 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3382   if (reachable(src)) {
3383     movl(dst, as_Address(src));
3384   } else {
3385     lea(rscratch1, src);
3386     movl(dst, Address(rscratch1, 0));
3387   }
3388 }
3389 
3390 // C++ bool manipulation
3391 
3392 void MacroAssembler::movbool(Register dst, Address src) {
3393   if(sizeof(bool) == 1)
3394     movb(dst, src);
3395   else if(sizeof(bool) == 2)
3396     movw(dst, src);
3397   else if(sizeof(bool) == 4)
3398     movl(dst, src);
3399   else
3400     // unsupported
3401     ShouldNotReachHere();
3402 }
3403 
3404 void MacroAssembler::movbool(Address dst, bool boolconst) {
3405   if(sizeof(bool) == 1)
3406     movb(dst, (int) boolconst);
3407   else if(sizeof(bool) == 2)
3408     movw(dst, (int) boolconst);
3409   else if(sizeof(bool) == 4)
3410     movl(dst, (int) boolconst);
3411   else
3412     // unsupported
3413     ShouldNotReachHere();
3414 }
3415 
3416 void MacroAssembler::movbool(Address dst, Register src) {
3417   if(sizeof(bool) == 1)
3418     movb(dst, src);
3419   else if(sizeof(bool) == 2)
3420     movw(dst, src);
3421   else if(sizeof(bool) == 4)
3422     movl(dst, src);
3423   else
3424     // unsupported
3425     ShouldNotReachHere();
3426 }
3427 
3428 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3429   movb(as_Address(dst), src);
3430 }
3431 
3432 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3433   if (reachable(src)) {
3434     movdl(dst, as_Address(src));
3435   } else {
3436     lea(rscratch1, src);
3437     movdl(dst, Address(rscratch1, 0));
3438   }
3439 }
3440 
3441 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3442   if (reachable(src)) {
3443     movq(dst, as_Address(src));
3444   } else {
3445     lea(rscratch1, src);
3446     movq(dst, Address(rscratch1, 0));
3447   }
3448 }
3449 
3450 #ifdef COMPILER2
3451 void MacroAssembler::setvectmask(Register dst, Register src) {
3452   guarantee(PostLoopMultiversioning, "must be");
3453   Assembler::movl(dst, 1);
3454   Assembler::shlxl(dst, dst, src);
3455   Assembler::decl(dst);
3456   Assembler::kmovdl(k1, dst);
3457   Assembler::movl(dst, src);
3458 }
3459 
3460 void MacroAssembler::restorevectmask() {
3461   guarantee(PostLoopMultiversioning, "must be");
3462   Assembler::knotwl(k1, k0);
3463 }
3464 #endif // COMPILER2
3465 
3466 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3467   if (reachable(src)) {
3468     if (UseXmmLoadAndClearUpper) {
3469       movsd (dst, as_Address(src));
3470     } else {
3471       movlpd(dst, as_Address(src));
3472     }
3473   } else {
3474     lea(rscratch1, src);
3475     if (UseXmmLoadAndClearUpper) {
3476       movsd (dst, Address(rscratch1, 0));
3477     } else {
3478       movlpd(dst, Address(rscratch1, 0));
3479     }
3480   }
3481 }
3482 
3483 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3484   if (reachable(src)) {
3485     movss(dst, as_Address(src));
3486   } else {
3487     lea(rscratch1, src);
3488     movss(dst, Address(rscratch1, 0));
3489   }
3490 }
3491 
3492 void MacroAssembler::movptr(Register dst, Register src) {
3493   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3494 }
3495 
3496 void MacroAssembler::movptr(Register dst, Address src) {
3497   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3498 }
3499 
3500 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3501 void MacroAssembler::movptr(Register dst, intptr_t src) {
3502   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3503 }
3504 
3505 void MacroAssembler::movptr(Address dst, Register src) {
3506   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3507 }
3508 
3509 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3510     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3511     Assembler::movdqu(dst, src);
3512 }
3513 
3514 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3515     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3516     Assembler::movdqu(dst, src);
3517 }
3518 
3519 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3520     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3521     Assembler::movdqu(dst, src);
3522 }
3523 
3524 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3525   if (reachable(src)) {
3526     movdqu(dst, as_Address(src));
3527   } else {
3528     lea(scratchReg, src);
3529     movdqu(dst, Address(scratchReg, 0));
3530   }
3531 }
3532 
3533 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3534     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3535     Assembler::vmovdqu(dst, src);
3536 }
3537 
3538 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3539     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3540     Assembler::vmovdqu(dst, src);
3541 }
3542 
3543 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3544     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3545     Assembler::vmovdqu(dst, src);
3546 }
3547 
3548 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3549   if (reachable(src)) {
3550     vmovdqu(dst, as_Address(src));
3551   }
3552   else {
3553     lea(rscratch1, src);
3554     vmovdqu(dst, Address(rscratch1, 0));
3555   }
3556 }
3557 
3558 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3559   if (reachable(src)) {
3560     Assembler::evmovdquq(dst, as_Address(src), vector_len);
3561   } else {
3562     lea(rscratch, src);
3563     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3564   }
3565 }
3566 
3567 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3568   if (reachable(src)) {
3569     Assembler::movdqa(dst, as_Address(src));
3570   } else {
3571     lea(rscratch1, src);
3572     Assembler::movdqa(dst, Address(rscratch1, 0));
3573   }
3574 }
3575 
3576 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3577   if (reachable(src)) {
3578     Assembler::movsd(dst, as_Address(src));
3579   } else {
3580     lea(rscratch1, src);
3581     Assembler::movsd(dst, Address(rscratch1, 0));
3582   }
3583 }
3584 
3585 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3586   if (reachable(src)) {
3587     Assembler::movss(dst, as_Address(src));
3588   } else {
3589     lea(rscratch1, src);
3590     Assembler::movss(dst, Address(rscratch1, 0));
3591   }
3592 }
3593 
3594 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3595   if (reachable(src)) {
3596     Assembler::mulsd(dst, as_Address(src));
3597   } else {
3598     lea(rscratch1, src);
3599     Assembler::mulsd(dst, Address(rscratch1, 0));
3600   }
3601 }
3602 
3603 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3604   if (reachable(src)) {
3605     Assembler::mulss(dst, as_Address(src));
3606   } else {
3607     lea(rscratch1, src);
3608     Assembler::mulss(dst, Address(rscratch1, 0));
3609   }
3610 }
3611 
3612 void MacroAssembler::null_check(Register reg, int offset) {
3613   if (needs_explicit_null_check(offset)) {
3614     // provoke OS NULL exception if reg = NULL by
3615     // accessing M[reg] w/o changing any (non-CC) registers
3616     // NOTE: cmpl is plenty here to provoke a segv
3617     cmpptr(rax, Address(reg, 0));
3618     // Note: should probably use testl(rax, Address(reg, 0));
3619     //       may be shorter code (however, this version of
3620     //       testl needs to be implemented first)
3621   } else {
3622     // nothing to do, (later) access of M[reg + offset]
3623     // will provoke OS NULL exception if reg = NULL
3624   }
3625 }
3626 
3627 void MacroAssembler::os_breakpoint() {
3628   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3629   // (e.g., MSVC can't call ps() otherwise)
3630   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3631 }
3632 
3633 void MacroAssembler::unimplemented(const char* what) {
3634   const char* buf = NULL;
3635   {
3636     ResourceMark rm;
3637     stringStream ss;
3638     ss.print("unimplemented: %s", what);
3639     buf = code_string(ss.as_string());
3640   }
3641   stop(buf);
3642 }
3643 
3644 #ifdef _LP64
3645 #define XSTATE_BV 0x200
3646 #endif
3647 
3648 void MacroAssembler::pop_CPU_state() {
3649   pop_FPU_state();
3650   pop_IU_state();
3651 }
3652 
3653 void MacroAssembler::pop_FPU_state() {
3654 #ifndef _LP64
3655   frstor(Address(rsp, 0));
3656 #else
3657   fxrstor(Address(rsp, 0));
3658 #endif
3659   addptr(rsp, FPUStateSizeInWords * wordSize);
3660 }
3661 
3662 void MacroAssembler::pop_IU_state() {
3663   popa();
3664   LP64_ONLY(addq(rsp, 8));
3665   popf();
3666 }
3667 
3668 // Save Integer and Float state
3669 // Warning: Stack must be 16 byte aligned (64bit)
3670 void MacroAssembler::push_CPU_state() {
3671   push_IU_state();
3672   push_FPU_state();
3673 }
3674 
3675 void MacroAssembler::push_FPU_state() {
3676   subptr(rsp, FPUStateSizeInWords * wordSize);
3677 #ifndef _LP64
3678   fnsave(Address(rsp, 0));
3679   fwait();
3680 #else
3681   fxsave(Address(rsp, 0));
3682 #endif // LP64
3683 }
3684 
3685 void MacroAssembler::push_IU_state() {
3686   // Push flags first because pusha kills them
3687   pushf();
3688   // Make sure rsp stays 16-byte aligned
3689   LP64_ONLY(subq(rsp, 8));
3690   pusha();
3691 }
3692 
3693 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3694   if (!java_thread->is_valid()) {
3695     java_thread = rdi;
3696     get_thread(java_thread);
3697   }
3698   // we must set sp to zero to clear frame
3699   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3700   if (clear_fp) {
3701     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3702   }
3703 
3704   // Always clear the pc because it could have been set by make_walkable()
3705   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3706 
3707   vzeroupper();
3708 }
3709 
3710 void MacroAssembler::restore_rax(Register tmp) {
3711   if (tmp == noreg) pop(rax);
3712   else if (tmp != rax) mov(rax, tmp);
3713 }
3714 
3715 void MacroAssembler::round_to(Register reg, int modulus) {
3716   addptr(reg, modulus - 1);
3717   andptr(reg, -modulus);
3718 }
3719 
3720 void MacroAssembler::save_rax(Register tmp) {
3721   if (tmp == noreg) push(rax);
3722   else if (tmp != rax) mov(tmp, rax);
3723 }
3724 
3725 // Write serialization page so VM thread can do a pseudo remote membar.
3726 // We use the current thread pointer to calculate a thread specific
3727 // offset to write to within the page. This minimizes bus traffic
3728 // due to cache line collision.
3729 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3730   movl(tmp, thread);
3731   shrl(tmp, os::get_serialize_page_shift_count());
3732   andl(tmp, (os::vm_page_size() - sizeof(int)));
3733 
3734   Address index(noreg, tmp, Address::times_1);
3735   ExternalAddress page(os::get_memory_serialize_page());
3736 
3737   // Size of store must match masking code above
3738   movl(as_Address(ArrayAddress(page, index)), tmp);
3739 }
3740 
3741 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3742   if (SafepointMechanism::uses_thread_local_poll()) {
3743 #ifdef _LP64
3744     assert(thread_reg == r15_thread, "should be");
3745 #else
3746     if (thread_reg == noreg) {
3747       thread_reg = temp_reg;
3748       get_thread(thread_reg);
3749     }
3750 #endif
3751     testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3752     jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3753   } else {
3754     cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3755         SafepointSynchronize::_not_synchronized);
3756     jcc(Assembler::notEqual, slow_path);
3757   }
3758 }
3759 
3760 // Calls to C land
3761 //
3762 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3763 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3764 // has to be reset to 0. This is required to allow proper stack traversal.
3765 void MacroAssembler::set_last_Java_frame(Register java_thread,
3766                                          Register last_java_sp,
3767                                          Register last_java_fp,
3768                                          address  last_java_pc) {
3769   vzeroupper();
3770   // determine java_thread register
3771   if (!java_thread->is_valid()) {
3772     java_thread = rdi;
3773     get_thread(java_thread);
3774   }
3775   // determine last_java_sp register
3776   if (!last_java_sp->is_valid()) {
3777     last_java_sp = rsp;
3778   }
3779 
3780   // last_java_fp is optional
3781 
3782   if (last_java_fp->is_valid()) {
3783     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3784   }
3785 
3786   // last_java_pc is optional
3787 
3788   if (last_java_pc != NULL) {
3789     lea(Address(java_thread,
3790                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3791         InternalAddress(last_java_pc));
3792 
3793   }
3794   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3795 }
3796 
3797 void MacroAssembler::shlptr(Register dst, int imm8) {
3798   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3799 }
3800 
3801 void MacroAssembler::shrptr(Register dst, int imm8) {
3802   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3803 }
3804 
3805 void MacroAssembler::sign_extend_byte(Register reg) {
3806   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3807     movsbl(reg, reg); // movsxb
3808   } else {
3809     shll(reg, 24);
3810     sarl(reg, 24);
3811   }
3812 }
3813 
3814 void MacroAssembler::sign_extend_short(Register reg) {
3815   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3816     movswl(reg, reg); // movsxw
3817   } else {
3818     shll(reg, 16);
3819     sarl(reg, 16);
3820   }
3821 }
3822 
3823 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3824   assert(reachable(src), "Address should be reachable");
3825   testl(dst, as_Address(src));
3826 }
3827 
3828 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3829   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3830   Assembler::pcmpeqb(dst, src);
3831 }
3832 
3833 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3834   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3835   Assembler::pcmpeqw(dst, src);
3836 }
3837 
3838 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3839   assert((dst->encoding() < 16),"XMM register should be 0-15");
3840   Assembler::pcmpestri(dst, src, imm8);
3841 }
3842 
3843 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3844   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3845   Assembler::pcmpestri(dst, src, imm8);
3846 }
3847 
3848 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3849   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3850   Assembler::pmovzxbw(dst, src);
3851 }
3852 
3853 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3854   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3855   Assembler::pmovzxbw(dst, src);
3856 }
3857 
3858 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3859   assert((src->encoding() < 16),"XMM register should be 0-15");
3860   Assembler::pmovmskb(dst, src);
3861 }
3862 
3863 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3864   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3865   Assembler::ptest(dst, src);
3866 }
3867 
3868 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3869   if (reachable(src)) {
3870     Assembler::sqrtsd(dst, as_Address(src));
3871   } else {
3872     lea(rscratch1, src);
3873     Assembler::sqrtsd(dst, Address(rscratch1, 0));
3874   }
3875 }
3876 
3877 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3878   if (reachable(src)) {
3879     Assembler::sqrtss(dst, as_Address(src));
3880   } else {
3881     lea(rscratch1, src);
3882     Assembler::sqrtss(dst, Address(rscratch1, 0));
3883   }
3884 }
3885 
3886 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3887   if (reachable(src)) {
3888     Assembler::subsd(dst, as_Address(src));
3889   } else {
3890     lea(rscratch1, src);
3891     Assembler::subsd(dst, Address(rscratch1, 0));
3892   }
3893 }
3894 
3895 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3896   if (reachable(src)) {
3897     Assembler::subss(dst, as_Address(src));
3898   } else {
3899     lea(rscratch1, src);
3900     Assembler::subss(dst, Address(rscratch1, 0));
3901   }
3902 }
3903 
3904 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3905   if (reachable(src)) {
3906     Assembler::ucomisd(dst, as_Address(src));
3907   } else {
3908     lea(rscratch1, src);
3909     Assembler::ucomisd(dst, Address(rscratch1, 0));
3910   }
3911 }
3912 
3913 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3914   if (reachable(src)) {
3915     Assembler::ucomiss(dst, as_Address(src));
3916   } else {
3917     lea(rscratch1, src);
3918     Assembler::ucomiss(dst, Address(rscratch1, 0));
3919   }
3920 }
3921 
3922 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3923   // Used in sign-bit flipping with aligned address.
3924   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3925   if (reachable(src)) {
3926     Assembler::xorpd(dst, as_Address(src));
3927   } else {
3928     lea(rscratch1, src);
3929     Assembler::xorpd(dst, Address(rscratch1, 0));
3930   }
3931 }
3932 
3933 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3934   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3935     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3936   }
3937   else {
3938     Assembler::xorpd(dst, src);
3939   }
3940 }
3941 
3942 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3943   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3944     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3945   } else {
3946     Assembler::xorps(dst, src);
3947   }
3948 }
3949 
3950 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3951   // Used in sign-bit flipping with aligned address.
3952   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3953   if (reachable(src)) {
3954     Assembler::xorps(dst, as_Address(src));
3955   } else {
3956     lea(rscratch1, src);
3957     Assembler::xorps(dst, Address(rscratch1, 0));
3958   }
3959 }
3960 
3961 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3962   // Used in sign-bit flipping with aligned address.
3963   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3964   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3965   if (reachable(src)) {
3966     Assembler::pshufb(dst, as_Address(src));
3967   } else {
3968     lea(rscratch1, src);
3969     Assembler::pshufb(dst, Address(rscratch1, 0));
3970   }
3971 }
3972 
3973 // AVX 3-operands instructions
3974 
3975 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3976   if (reachable(src)) {
3977     vaddsd(dst, nds, as_Address(src));
3978   } else {
3979     lea(rscratch1, src);
3980     vaddsd(dst, nds, Address(rscratch1, 0));
3981   }
3982 }
3983 
3984 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3985   if (reachable(src)) {
3986     vaddss(dst, nds, as_Address(src));
3987   } else {
3988     lea(rscratch1, src);
3989     vaddss(dst, nds, Address(rscratch1, 0));
3990   }
3991 }
3992 
3993 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3994   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3995   vandps(dst, nds, negate_field, vector_len);
3996 }
3997 
3998 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3999   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4000   vandpd(dst, nds, negate_field, vector_len);
4001 }
4002 
4003 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4004   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4005   Assembler::vpaddb(dst, nds, src, vector_len);
4006 }
4007 
4008 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4009   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()), "XMM register should be 0-15");
4010   Assembler::vpaddb(dst, nds, src, vector_len);
4011 }
4012 
4013 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4014   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4015   Assembler::vpaddw(dst, nds, src, vector_len);
4016 }
4017 
4018 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4019   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4020   Assembler::vpaddw(dst, nds, src, vector_len);
4021 }
4022 
4023 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4024   if (reachable(src)) {
4025     Assembler::vpand(dst, nds, as_Address(src), vector_len);
4026   } else {
4027     lea(rscratch1, src);
4028     Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4029   }
4030 }
4031 
4032 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
4033   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4034   Assembler::vpbroadcastw(dst, src, vector_len);
4035 }
4036 
4037 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4038   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4039   Assembler::vpcmpeqb(dst, nds, src, vector_len);
4040 }
4041 
4042 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4043   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4044   Assembler::vpcmpeqw(dst, nds, src, vector_len);
4045 }
4046 
4047 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4048   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4049   Assembler::vpmovzxbw(dst, src, vector_len);
4050 }
4051 
4052 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4053   assert((src->encoding() < 16),"XMM register should be 0-15");
4054   Assembler::vpmovmskb(dst, src);
4055 }
4056 
4057 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4058   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4059   Assembler::vpmullw(dst, nds, src, vector_len);
4060 }
4061 
4062 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4063   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4064   Assembler::vpmullw(dst, nds, src, vector_len);
4065 }
4066 
4067 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4068   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4069   Assembler::vpsubb(dst, nds, src, vector_len);
4070 }
4071 
4072 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4073   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4074   Assembler::vpsubb(dst, nds, src, vector_len);
4075 }
4076 
4077 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4078   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4079   Assembler::vpsubw(dst, nds, src, vector_len);
4080 }
4081 
4082 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4083   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4084   Assembler::vpsubw(dst, nds, src, vector_len);
4085 }
4086 
4087 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4088   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4089   Assembler::vpsraw(dst, nds, shift, vector_len);
4090 }
4091 
4092 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4093   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4094   Assembler::vpsraw(dst, nds, shift, vector_len);
4095 }
4096 
4097 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4098   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4099   Assembler::vpsrlw(dst, nds, shift, vector_len);
4100 }
4101 
4102 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4103   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4104   Assembler::vpsrlw(dst, nds, shift, vector_len);
4105 }
4106 
4107 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4108   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4109   Assembler::vpsllw(dst, nds, shift, vector_len);
4110 }
4111 
4112 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4113   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4114   Assembler::vpsllw(dst, nds, shift, vector_len);
4115 }
4116 
4117 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4118   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
4119   Assembler::vptest(dst, src);
4120 }
4121 
4122 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4123   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4124   Assembler::punpcklbw(dst, src);
4125 }
4126 
4127 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4128   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
4129   Assembler::pshufd(dst, src, mode);
4130 }
4131 
4132 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4133   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
4134   Assembler::pshuflw(dst, src, mode);
4135 }
4136 
4137 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4138   if (reachable(src)) {
4139     vandpd(dst, nds, as_Address(src), vector_len);
4140   } else {
4141     lea(rscratch1, src);
4142     vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4143   }
4144 }
4145 
4146 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4147   if (reachable(src)) {
4148     vandps(dst, nds, as_Address(src), vector_len);
4149   } else {
4150     lea(rscratch1, src);
4151     vandps(dst, nds, Address(rscratch1, 0), vector_len);
4152   }
4153 }
4154 
4155 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4156   if (reachable(src)) {
4157     vdivsd(dst, nds, as_Address(src));
4158   } else {
4159     lea(rscratch1, src);
4160     vdivsd(dst, nds, Address(rscratch1, 0));
4161   }
4162 }
4163 
4164 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4165   if (reachable(src)) {
4166     vdivss(dst, nds, as_Address(src));
4167   } else {
4168     lea(rscratch1, src);
4169     vdivss(dst, nds, Address(rscratch1, 0));
4170   }
4171 }
4172 
4173 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4174   if (reachable(src)) {
4175     vmulsd(dst, nds, as_Address(src));
4176   } else {
4177     lea(rscratch1, src);
4178     vmulsd(dst, nds, Address(rscratch1, 0));
4179   }
4180 }
4181 
4182 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4183   if (reachable(src)) {
4184     vmulss(dst, nds, as_Address(src));
4185   } else {
4186     lea(rscratch1, src);
4187     vmulss(dst, nds, Address(rscratch1, 0));
4188   }
4189 }
4190 
4191 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4192   if (reachable(src)) {
4193     vsubsd(dst, nds, as_Address(src));
4194   } else {
4195     lea(rscratch1, src);
4196     vsubsd(dst, nds, Address(rscratch1, 0));
4197   }
4198 }
4199 
4200 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4201   if (reachable(src)) {
4202     vsubss(dst, nds, as_Address(src));
4203   } else {
4204     lea(rscratch1, src);
4205     vsubss(dst, nds, Address(rscratch1, 0));
4206   }
4207 }
4208 
4209 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4210   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4211   vxorps(dst, nds, src, Assembler::AVX_128bit);
4212 }
4213 
4214 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4215   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4216   vxorpd(dst, nds, src, Assembler::AVX_128bit);
4217 }
4218 
4219 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4220   if (reachable(src)) {
4221     vxorpd(dst, nds, as_Address(src), vector_len);
4222   } else {
4223     lea(rscratch1, src);
4224     vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4225   }
4226 }
4227 
4228 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4229   if (reachable(src)) {
4230     vxorps(dst, nds, as_Address(src), vector_len);
4231   } else {
4232     lea(rscratch1, src);
4233     vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4234   }
4235 }
4236 
4237 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4238   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4239   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4240   // The inverted mask is sign-extended
4241   andptr(possibly_jweak, inverted_jweak_mask);
4242 }
4243 
4244 void MacroAssembler::resolve_jobject(Register value,
4245                                      Register thread,
4246                                      Register tmp) {
4247   assert_different_registers(value, thread, tmp);
4248   Label done, not_weak;
4249   testptr(value, value);
4250   jcc(Assembler::zero, done);                // Use NULL as-is.
4251   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4252   jcc(Assembler::zero, not_weak);
4253   // Resolve jweak.
4254   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4255                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4256   verify_oop(value);
4257   jmp(done);
4258   bind(not_weak);
4259   // Resolve (untagged) jobject.
4260   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4261   verify_oop(value);
4262   bind(done);
4263 }
4264 
4265 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4266   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4267 }
4268 
4269 // Force generation of a 4 byte immediate value even if it fits into 8bit
4270 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4271   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4272 }
4273 
4274 void MacroAssembler::subptr(Register dst, Register src) {
4275   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4276 }
4277 
4278 // C++ bool manipulation
4279 void MacroAssembler::testbool(Register dst) {
4280   if(sizeof(bool) == 1)
4281     testb(dst, 0xff);
4282   else if(sizeof(bool) == 2) {
4283     // testw implementation needed for two byte bools
4284     ShouldNotReachHere();
4285   } else if(sizeof(bool) == 4)
4286     testl(dst, dst);
4287   else
4288     // unsupported
4289     ShouldNotReachHere();
4290 }
4291 
4292 void MacroAssembler::testptr(Register dst, Register src) {
4293   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4294 }
4295 
4296 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4297 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4298                                    Register var_size_in_bytes,
4299                                    int con_size_in_bytes,
4300                                    Register t1,
4301                                    Register t2,
4302                                    Label& slow_case) {
4303   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4304   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4305 }
4306 
4307 // Defines obj, preserves var_size_in_bytes
4308 void MacroAssembler::eden_allocate(Register thread, Register obj,
4309                                    Register var_size_in_bytes,
4310                                    int con_size_in_bytes,
4311                                    Register t1,
4312                                    Label& slow_case) {
4313   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4314   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4315 }
4316 
4317 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4318 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4319   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4320   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4321   Label done;
4322 
4323   testptr(length_in_bytes, length_in_bytes);
4324   jcc(Assembler::zero, done);
4325 
4326   // initialize topmost word, divide index by 2, check if odd and test if zero
4327   // note: for the remaining code to work, index must be a multiple of BytesPerWord
4328 #ifdef ASSERT
4329   {
4330     Label L;
4331     testptr(length_in_bytes, BytesPerWord - 1);
4332     jcc(Assembler::zero, L);
4333     stop("length must be a multiple of BytesPerWord");
4334     bind(L);
4335   }
4336 #endif
4337   Register index = length_in_bytes;
4338   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
4339   if (UseIncDec) {
4340     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
4341   } else {
4342     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
4343     shrptr(index, 1);
4344   }
4345 #ifndef _LP64
4346   // index could have not been a multiple of 8 (i.e., bit 2 was set)
4347   {
4348     Label even;
4349     // note: if index was a multiple of 8, then it cannot
4350     //       be 0 now otherwise it must have been 0 before
4351     //       => if it is even, we don't need to check for 0 again
4352     jcc(Assembler::carryClear, even);
4353     // clear topmost word (no jump would be needed if conditional assignment worked here)
4354     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4355     // index could be 0 now, must check again
4356     jcc(Assembler::zero, done);
4357     bind(even);
4358   }
4359 #endif // !_LP64
4360   // initialize remaining object fields: index is a multiple of 2 now
4361   {
4362     Label loop;
4363     bind(loop);
4364     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4365     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4366     decrement(index);
4367     jcc(Assembler::notZero, loop);
4368   }
4369 
4370   bind(done);
4371 }
4372 
4373 // Look up the method for a megamorphic invokeinterface call.
4374 // The target method is determined by <intf_klass, itable_index>.
4375 // The receiver klass is in recv_klass.
4376 // On success, the result will be in method_result, and execution falls through.
4377 // On failure, execution transfers to the given label.
4378 void MacroAssembler::lookup_interface_method(Register recv_klass,
4379                                              Register intf_klass,
4380                                              RegisterOrConstant itable_index,
4381                                              Register method_result,
4382                                              Register scan_temp,
4383                                              Label& L_no_such_interface,
4384                                              bool return_method) {
4385   assert_different_registers(recv_klass, intf_klass, scan_temp);
4386   assert_different_registers(method_result, intf_klass, scan_temp);
4387   assert(recv_klass != method_result || !return_method,
4388          "recv_klass can be destroyed when method isn't needed");
4389 
4390   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4391          "caller must use same register for non-constant itable index as for method");
4392 
4393   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4394   int vtable_base = in_bytes(Klass::vtable_start_offset());
4395   int itentry_off = itableMethodEntry::method_offset_in_bytes();
4396   int scan_step   = itableOffsetEntry::size() * wordSize;
4397   int vte_size    = vtableEntry::size_in_bytes();
4398   Address::ScaleFactor times_vte_scale = Address::times_ptr;
4399   assert(vte_size == wordSize, "else adjust times_vte_scale");
4400 
4401   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4402 
4403   // %%% Could store the aligned, prescaled offset in the klassoop.
4404   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4405 
4406   if (return_method) {
4407     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4408     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4409     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4410   }
4411 
4412   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4413   //   if (scan->interface() == intf) {
4414   //     result = (klass + scan->offset() + itable_index);
4415   //   }
4416   // }
4417   Label search, found_method;
4418 
4419   for (int peel = 1; peel >= 0; peel--) {
4420     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4421     cmpptr(intf_klass, method_result);
4422 
4423     if (peel) {
4424       jccb(Assembler::equal, found_method);
4425     } else {
4426       jccb(Assembler::notEqual, search);
4427       // (invert the test to fall through to found_method...)
4428     }
4429 
4430     if (!peel)  break;
4431 
4432     bind(search);
4433 
4434     // Check that the previous entry is non-null.  A null entry means that
4435     // the receiver class doesn't implement the interface, and wasn't the
4436     // same as when the caller was compiled.
4437     testptr(method_result, method_result);
4438     jcc(Assembler::zero, L_no_such_interface);
4439     addptr(scan_temp, scan_step);
4440   }
4441 
4442   bind(found_method);
4443 
4444   if (return_method) {
4445     // Got a hit.
4446     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4447     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4448   }
4449 }
4450 
4451 
4452 // virtual method calling
4453 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4454                                            RegisterOrConstant vtable_index,
4455                                            Register method_result) {
4456   const int base = in_bytes(Klass::vtable_start_offset());
4457   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4458   Address vtable_entry_addr(recv_klass,
4459                             vtable_index, Address::times_ptr,
4460                             base + vtableEntry::method_offset_in_bytes());
4461   movptr(method_result, vtable_entry_addr);
4462 }
4463 
4464 
4465 void MacroAssembler::check_klass_subtype(Register sub_klass,
4466                            Register super_klass,
4467                            Register temp_reg,
4468                            Label& L_success) {
4469   Label L_failure;
4470   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
4471   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4472   bind(L_failure);
4473 }
4474 
4475 
4476 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4477                                                    Register super_klass,
4478                                                    Register temp_reg,
4479                                                    Label* L_success,
4480                                                    Label* L_failure,
4481                                                    Label* L_slow_path,
4482                                         RegisterOrConstant super_check_offset) {
4483   assert_different_registers(sub_klass, super_klass, temp_reg);
4484   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4485   if (super_check_offset.is_register()) {
4486     assert_different_registers(sub_klass, super_klass,
4487                                super_check_offset.as_register());
4488   } else if (must_load_sco) {
4489     assert(temp_reg != noreg, "supply either a temp or a register offset");
4490   }
4491 
4492   Label L_fallthrough;
4493   int label_nulls = 0;
4494   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4495   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4496   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4497   assert(label_nulls <= 1, "at most one NULL in the batch");
4498 
4499   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4500   int sco_offset = in_bytes(Klass::super_check_offset_offset());
4501   Address super_check_offset_addr(super_klass, sco_offset);
4502 
4503   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4504   // range of a jccb.  If this routine grows larger, reconsider at
4505   // least some of these.
4506 #define local_jcc(assembler_cond, label)                                \
4507   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
4508   else                             jcc( assembler_cond, label) /*omit semi*/
4509 
4510   // Hacked jmp, which may only be used just before L_fallthrough.
4511 #define final_jmp(label)                                                \
4512   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
4513   else                            jmp(label)                /*omit semi*/
4514 
4515   // If the pointers are equal, we are done (e.g., String[] elements).
4516   // This self-check enables sharing of secondary supertype arrays among
4517   // non-primary types such as array-of-interface.  Otherwise, each such
4518   // type would need its own customized SSA.
4519   // We move this check to the front of the fast path because many
4520   // type checks are in fact trivially successful in this manner,
4521   // so we get a nicely predicted branch right at the start of the check.
4522   cmpptr(sub_klass, super_klass);
4523   local_jcc(Assembler::equal, *L_success);
4524 
4525   // Check the supertype display:
4526   if (must_load_sco) {
4527     // Positive movl does right thing on LP64.
4528     movl(temp_reg, super_check_offset_addr);
4529     super_check_offset = RegisterOrConstant(temp_reg);
4530   }
4531   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4532   cmpptr(super_klass, super_check_addr); // load displayed supertype
4533 
4534   // This check has worked decisively for primary supers.
4535   // Secondary supers are sought in the super_cache ('super_cache_addr').
4536   // (Secondary supers are interfaces and very deeply nested subtypes.)
4537   // This works in the same check above because of a tricky aliasing
4538   // between the super_cache and the primary super display elements.
4539   // (The 'super_check_addr' can address either, as the case requires.)
4540   // Note that the cache is updated below if it does not help us find
4541   // what we need immediately.
4542   // So if it was a primary super, we can just fail immediately.
4543   // Otherwise, it's the slow path for us (no success at this point).
4544 
4545   if (super_check_offset.is_register()) {
4546     local_jcc(Assembler::equal, *L_success);
4547     cmpl(super_check_offset.as_register(), sc_offset);
4548     if (L_failure == &L_fallthrough) {
4549       local_jcc(Assembler::equal, *L_slow_path);
4550     } else {
4551       local_jcc(Assembler::notEqual, *L_failure);
4552       final_jmp(*L_slow_path);
4553     }
4554   } else if (super_check_offset.as_constant() == sc_offset) {
4555     // Need a slow path; fast failure is impossible.
4556     if (L_slow_path == &L_fallthrough) {
4557       local_jcc(Assembler::equal, *L_success);
4558     } else {
4559       local_jcc(Assembler::notEqual, *L_slow_path);
4560       final_jmp(*L_success);
4561     }
4562   } else {
4563     // No slow path; it's a fast decision.
4564     if (L_failure == &L_fallthrough) {
4565       local_jcc(Assembler::equal, *L_success);
4566     } else {
4567       local_jcc(Assembler::notEqual, *L_failure);
4568       final_jmp(*L_success);
4569     }
4570   }
4571 
4572   bind(L_fallthrough);
4573 
4574 #undef local_jcc
4575 #undef final_jmp
4576 }
4577 
4578 
4579 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4580                                                    Register super_klass,
4581                                                    Register temp_reg,
4582                                                    Register temp2_reg,
4583                                                    Label* L_success,
4584                                                    Label* L_failure,
4585                                                    bool set_cond_codes) {
4586   assert_different_registers(sub_klass, super_klass, temp_reg);
4587   if (temp2_reg != noreg)
4588     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4589 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4590 
4591   Label L_fallthrough;
4592   int label_nulls = 0;
4593   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4594   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4595   assert(label_nulls <= 1, "at most one NULL in the batch");
4596 
4597   // a couple of useful fields in sub_klass:
4598   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4599   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4600   Address secondary_supers_addr(sub_klass, ss_offset);
4601   Address super_cache_addr(     sub_klass, sc_offset);
4602 
4603   // Do a linear scan of the secondary super-klass chain.
4604   // This code is rarely used, so simplicity is a virtue here.
4605   // The repne_scan instruction uses fixed registers, which we must spill.
4606   // Don't worry too much about pre-existing connections with the input regs.
4607 
4608   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4609   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4610 
4611   // Get super_klass value into rax (even if it was in rdi or rcx).
4612   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4613   if (super_klass != rax || UseCompressedOops) {
4614     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4615     mov(rax, super_klass);
4616   }
4617   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4618   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4619 
4620 #ifndef PRODUCT
4621   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4622   ExternalAddress pst_counter_addr((address) pst_counter);
4623   NOT_LP64(  incrementl(pst_counter_addr) );
4624   LP64_ONLY( lea(rcx, pst_counter_addr) );
4625   LP64_ONLY( incrementl(Address(rcx, 0)) );
4626 #endif //PRODUCT
4627 
4628   // We will consult the secondary-super array.
4629   movptr(rdi, secondary_supers_addr);
4630   // Load the array length.  (Positive movl does right thing on LP64.)
4631   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4632   // Skip to start of data.
4633   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4634 
4635   // Scan RCX words at [RDI] for an occurrence of RAX.
4636   // Set NZ/Z based on last compare.
4637   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4638   // not change flags (only scas instruction which is repeated sets flags).
4639   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4640 
4641     testptr(rax,rax); // Set Z = 0
4642     repne_scan();
4643 
4644   // Unspill the temp. registers:
4645   if (pushed_rdi)  pop(rdi);
4646   if (pushed_rcx)  pop(rcx);
4647   if (pushed_rax)  pop(rax);
4648 
4649   if (set_cond_codes) {
4650     // Special hack for the AD files:  rdi is guaranteed non-zero.
4651     assert(!pushed_rdi, "rdi must be left non-NULL");
4652     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4653   }
4654 
4655   if (L_failure == &L_fallthrough)
4656         jccb(Assembler::notEqual, *L_failure);
4657   else  jcc(Assembler::notEqual, *L_failure);
4658 
4659   // Success.  Cache the super we found and proceed in triumph.
4660   movptr(super_cache_addr, super_klass);
4661 
4662   if (L_success != &L_fallthrough) {
4663     jmp(*L_success);
4664   }
4665 
4666 #undef IS_A_TEMP
4667 
4668   bind(L_fallthrough);
4669 }
4670 
4671 
4672 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4673   if (VM_Version::supports_cmov()) {
4674     cmovl(cc, dst, src);
4675   } else {
4676     Label L;
4677     jccb(negate_condition(cc), L);
4678     movl(dst, src);
4679     bind(L);
4680   }
4681 }
4682 
4683 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4684   if (VM_Version::supports_cmov()) {
4685     cmovl(cc, dst, src);
4686   } else {
4687     Label L;
4688     jccb(negate_condition(cc), L);
4689     movl(dst, src);
4690     bind(L);
4691   }
4692 }
4693 
4694 void MacroAssembler::verify_oop(Register reg, const char* s) {
4695   if (!VerifyOops) return;
4696 
4697   // Pass register number to verify_oop_subroutine
4698   const char* b = NULL;
4699   {
4700     ResourceMark rm;
4701     stringStream ss;
4702     ss.print("verify_oop: %s: %s", reg->name(), s);
4703     b = code_string(ss.as_string());
4704   }
4705   BLOCK_COMMENT("verify_oop {");
4706 #ifdef _LP64
4707   push(rscratch1);                    // save r10, trashed by movptr()
4708 #endif
4709   push(rax);                          // save rax,
4710   push(reg);                          // pass register argument
4711   ExternalAddress buffer((address) b);
4712   // avoid using pushptr, as it modifies scratch registers
4713   // and our contract is not to modify anything
4714   movptr(rax, buffer.addr());
4715   push(rax);
4716   // call indirectly to solve generation ordering problem
4717   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4718   call(rax);
4719   // Caller pops the arguments (oop, message) and restores rax, r10
4720   BLOCK_COMMENT("} verify_oop");
4721 }
4722 
4723 
4724 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4725                                                       Register tmp,
4726                                                       int offset) {
4727   intptr_t value = *delayed_value_addr;
4728   if (value != 0)
4729     return RegisterOrConstant(value + offset);
4730 
4731   // load indirectly to solve generation ordering problem
4732   movptr(tmp, ExternalAddress((address) delayed_value_addr));
4733 
4734 #ifdef ASSERT
4735   { Label L;
4736     testptr(tmp, tmp);
4737     if (WizardMode) {
4738       const char* buf = NULL;
4739       {
4740         ResourceMark rm;
4741         stringStream ss;
4742         ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4743         buf = code_string(ss.as_string());
4744       }
4745       jcc(Assembler::notZero, L);
4746       STOP(buf);
4747     } else {
4748       jccb(Assembler::notZero, L);
4749       hlt();
4750     }
4751     bind(L);
4752   }
4753 #endif
4754 
4755   if (offset != 0)
4756     addptr(tmp, offset);
4757 
4758   return RegisterOrConstant(tmp);
4759 }
4760 
4761 
4762 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4763                                          int extra_slot_offset) {
4764   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4765   int stackElementSize = Interpreter::stackElementSize;
4766   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4767 #ifdef ASSERT
4768   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4769   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4770 #endif
4771   Register             scale_reg    = noreg;
4772   Address::ScaleFactor scale_factor = Address::no_scale;
4773   if (arg_slot.is_constant()) {
4774     offset += arg_slot.as_constant() * stackElementSize;
4775   } else {
4776     scale_reg    = arg_slot.as_register();
4777     scale_factor = Address::times(stackElementSize);
4778   }
4779   offset += wordSize;           // return PC is on stack
4780   return Address(rsp, scale_reg, scale_factor, offset);
4781 }
4782 
4783 
4784 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4785   if (!VerifyOops) return;
4786 
4787   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4788   // Pass register number to verify_oop_subroutine
4789   const char* b = NULL;
4790   {
4791     ResourceMark rm;
4792     stringStream ss;
4793     ss.print("verify_oop_addr: %s", s);
4794     b = code_string(ss.as_string());
4795   }
4796 #ifdef _LP64
4797   push(rscratch1);                    // save r10, trashed by movptr()
4798 #endif
4799   push(rax);                          // save rax,
4800   // addr may contain rsp so we will have to adjust it based on the push
4801   // we just did (and on 64 bit we do two pushes)
4802   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4803   // stores rax into addr which is backwards of what was intended.
4804   if (addr.uses(rsp)) {
4805     lea(rax, addr);
4806     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4807   } else {
4808     pushptr(addr);
4809   }
4810 
4811   ExternalAddress buffer((address) b);
4812   // pass msg argument
4813   // avoid using pushptr, as it modifies scratch registers
4814   // and our contract is not to modify anything
4815   movptr(rax, buffer.addr());
4816   push(rax);
4817 
4818   // call indirectly to solve generation ordering problem
4819   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4820   call(rax);
4821   // Caller pops the arguments (addr, message) and restores rax, r10.
4822 }
4823 
4824 void MacroAssembler::verify_tlab() {
4825 #ifdef ASSERT
4826   if (UseTLAB && VerifyOops) {
4827     Label next, ok;
4828     Register t1 = rsi;
4829     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4830 
4831     push(t1);
4832     NOT_LP64(push(thread_reg));
4833     NOT_LP64(get_thread(thread_reg));
4834 
4835     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4836     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4837     jcc(Assembler::aboveEqual, next);
4838     STOP("assert(top >= start)");
4839     should_not_reach_here();
4840 
4841     bind(next);
4842     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4843     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4844     jcc(Assembler::aboveEqual, ok);
4845     STOP("assert(top <= end)");
4846     should_not_reach_here();
4847 
4848     bind(ok);
4849     NOT_LP64(pop(thread_reg));
4850     pop(t1);
4851   }
4852 #endif
4853 }
4854 
4855 class ControlWord {
4856  public:
4857   int32_t _value;
4858 
4859   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4860   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4861   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4862   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4863   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4864   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4865   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4866   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4867 
4868   void print() const {
4869     // rounding control
4870     const char* rc;
4871     switch (rounding_control()) {
4872       case 0: rc = "round near"; break;
4873       case 1: rc = "round down"; break;
4874       case 2: rc = "round up  "; break;
4875       case 3: rc = "chop      "; break;
4876     };
4877     // precision control
4878     const char* pc;
4879     switch (precision_control()) {
4880       case 0: pc = "24 bits "; break;
4881       case 1: pc = "reserved"; break;
4882       case 2: pc = "53 bits "; break;
4883       case 3: pc = "64 bits "; break;
4884     };
4885     // flags
4886     char f[9];
4887     f[0] = ' ';
4888     f[1] = ' ';
4889     f[2] = (precision   ()) ? 'P' : 'p';
4890     f[3] = (underflow   ()) ? 'U' : 'u';
4891     f[4] = (overflow    ()) ? 'O' : 'o';
4892     f[5] = (zero_divide ()) ? 'Z' : 'z';
4893     f[6] = (denormalized()) ? 'D' : 'd';
4894     f[7] = (invalid     ()) ? 'I' : 'i';
4895     f[8] = '\x0';
4896     // output
4897     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4898   }
4899 
4900 };
4901 
4902 class StatusWord {
4903  public:
4904   int32_t _value;
4905 
4906   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4907   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4908   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4909   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4910   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4911   int  top() const                     { return  (_value >> 11) & 7      ; }
4912   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4913   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4914   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4915   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4916   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4917   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4918   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4919   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4920 
4921   void print() const {
4922     // condition codes
4923     char c[5];
4924     c[0] = (C3()) ? '3' : '-';
4925     c[1] = (C2()) ? '2' : '-';
4926     c[2] = (C1()) ? '1' : '-';
4927     c[3] = (C0()) ? '0' : '-';
4928     c[4] = '\x0';
4929     // flags
4930     char f[9];
4931     f[0] = (error_status()) ? 'E' : '-';
4932     f[1] = (stack_fault ()) ? 'S' : '-';
4933     f[2] = (precision   ()) ? 'P' : '-';
4934     f[3] = (underflow   ()) ? 'U' : '-';
4935     f[4] = (overflow    ()) ? 'O' : '-';
4936     f[5] = (zero_divide ()) ? 'Z' : '-';
4937     f[6] = (denormalized()) ? 'D' : '-';
4938     f[7] = (invalid     ()) ? 'I' : '-';
4939     f[8] = '\x0';
4940     // output
4941     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4942   }
4943 
4944 };
4945 
4946 class TagWord {
4947  public:
4948   int32_t _value;
4949 
4950   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4951 
4952   void print() const {
4953     printf("%04x", _value & 0xFFFF);
4954   }
4955 
4956 };
4957 
4958 class FPU_Register {
4959  public:
4960   int32_t _m0;
4961   int32_t _m1;
4962   int16_t _ex;
4963 
4964   bool is_indefinite() const           {
4965     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4966   }
4967 
4968   void print() const {
4969     char  sign = (_ex < 0) ? '-' : '+';
4970     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4971     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4972   };
4973 
4974 };
4975 
4976 class FPU_State {
4977  public:
4978   enum {
4979     register_size       = 10,
4980     number_of_registers =  8,
4981     register_mask       =  7
4982   };
4983 
4984   ControlWord  _control_word;
4985   StatusWord   _status_word;
4986   TagWord      _tag_word;
4987   int32_t      _error_offset;
4988   int32_t      _error_selector;
4989   int32_t      _data_offset;
4990   int32_t      _data_selector;
4991   int8_t       _register[register_size * number_of_registers];
4992 
4993   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4994   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4995 
4996   const char* tag_as_string(int tag) const {
4997     switch (tag) {
4998       case 0: return "valid";
4999       case 1: return "zero";
5000       case 2: return "special";
5001       case 3: return "empty";
5002     }
5003     ShouldNotReachHere();
5004     return NULL;
5005   }
5006 
5007   void print() const {
5008     // print computation registers
5009     { int t = _status_word.top();
5010       for (int i = 0; i < number_of_registers; i++) {
5011         int j = (i - t) & register_mask;
5012         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5013         st(j)->print();
5014         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5015       }
5016     }
5017     printf("\n");
5018     // print control registers
5019     printf("ctrl = "); _control_word.print(); printf("\n");
5020     printf("stat = "); _status_word .print(); printf("\n");
5021     printf("tags = "); _tag_word    .print(); printf("\n");
5022   }
5023 
5024 };
5025 
5026 class Flag_Register {
5027  public:
5028   int32_t _value;
5029 
5030   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
5031   bool direction() const               { return ((_value >> 10) & 1) != 0; }
5032   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
5033   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
5034   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
5035   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
5036   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
5037 
5038   void print() const {
5039     // flags
5040     char f[8];
5041     f[0] = (overflow       ()) ? 'O' : '-';
5042     f[1] = (direction      ()) ? 'D' : '-';
5043     f[2] = (sign           ()) ? 'S' : '-';
5044     f[3] = (zero           ()) ? 'Z' : '-';
5045     f[4] = (auxiliary_carry()) ? 'A' : '-';
5046     f[5] = (parity         ()) ? 'P' : '-';
5047     f[6] = (carry          ()) ? 'C' : '-';
5048     f[7] = '\x0';
5049     // output
5050     printf("%08x  flags = %s", _value, f);
5051   }
5052 
5053 };
5054 
5055 class IU_Register {
5056  public:
5057   int32_t _value;
5058 
5059   void print() const {
5060     printf("%08x  %11d", _value, _value);
5061   }
5062 
5063 };
5064 
5065 class IU_State {
5066  public:
5067   Flag_Register _eflags;
5068   IU_Register   _rdi;
5069   IU_Register   _rsi;
5070   IU_Register   _rbp;
5071   IU_Register   _rsp;
5072   IU_Register   _rbx;
5073   IU_Register   _rdx;
5074   IU_Register   _rcx;
5075   IU_Register   _rax;
5076 
5077   void print() const {
5078     // computation registers
5079     printf("rax,  = "); _rax.print(); printf("\n");
5080     printf("rbx,  = "); _rbx.print(); printf("\n");
5081     printf("rcx  = "); _rcx.print(); printf("\n");
5082     printf("rdx  = "); _rdx.print(); printf("\n");
5083     printf("rdi  = "); _rdi.print(); printf("\n");
5084     printf("rsi  = "); _rsi.print(); printf("\n");
5085     printf("rbp,  = "); _rbp.print(); printf("\n");
5086     printf("rsp  = "); _rsp.print(); printf("\n");
5087     printf("\n");
5088     // control registers
5089     printf("flgs = "); _eflags.print(); printf("\n");
5090   }
5091 };
5092 
5093 
5094 class CPU_State {
5095  public:
5096   FPU_State _fpu_state;
5097   IU_State  _iu_state;
5098 
5099   void print() const {
5100     printf("--------------------------------------------------\n");
5101     _iu_state .print();
5102     printf("\n");
5103     _fpu_state.print();
5104     printf("--------------------------------------------------\n");
5105   }
5106 
5107 };
5108 
5109 
5110 static void _print_CPU_state(CPU_State* state) {
5111   state->print();
5112 };
5113 
5114 
5115 void MacroAssembler::print_CPU_state() {
5116   push_CPU_state();
5117   push(rsp);                // pass CPU state
5118   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5119   addptr(rsp, wordSize);       // discard argument
5120   pop_CPU_state();
5121 }
5122 
5123 
5124 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5125   static int counter = 0;
5126   FPU_State* fs = &state->_fpu_state;
5127   counter++;
5128   // For leaf calls, only verify that the top few elements remain empty.
5129   // We only need 1 empty at the top for C2 code.
5130   if( stack_depth < 0 ) {
5131     if( fs->tag_for_st(7) != 3 ) {
5132       printf("FPR7 not empty\n");
5133       state->print();
5134       assert(false, "error");
5135       return false;
5136     }
5137     return true;                // All other stack states do not matter
5138   }
5139 
5140   assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5141          "bad FPU control word");
5142 
5143   // compute stack depth
5144   int i = 0;
5145   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
5146   int d = i;
5147   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5148   // verify findings
5149   if (i != FPU_State::number_of_registers) {
5150     // stack not contiguous
5151     printf("%s: stack not contiguous at ST%d\n", s, i);
5152     state->print();
5153     assert(false, "error");
5154     return false;
5155   }
5156   // check if computed stack depth corresponds to expected stack depth
5157   if (stack_depth < 0) {
5158     // expected stack depth is -stack_depth or less
5159     if (d > -stack_depth) {
5160       // too many elements on the stack
5161       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5162       state->print();
5163       assert(false, "error");
5164       return false;
5165     }
5166   } else {
5167     // expected stack depth is stack_depth
5168     if (d != stack_depth) {
5169       // wrong stack depth
5170       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5171       state->print();
5172       assert(false, "error");
5173       return false;
5174     }
5175   }
5176   // everything is cool
5177   return true;
5178 }
5179 
5180 
5181 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5182   if (!VerifyFPU) return;
5183   push_CPU_state();
5184   push(rsp);                // pass CPU state
5185   ExternalAddress msg((address) s);
5186   // pass message string s
5187   pushptr(msg.addr());
5188   push(stack_depth);        // pass stack depth
5189   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5190   addptr(rsp, 3 * wordSize);   // discard arguments
5191   // check for error
5192   { Label L;
5193     testl(rax, rax);
5194     jcc(Assembler::notZero, L);
5195     int3();                  // break if error condition
5196     bind(L);
5197   }
5198   pop_CPU_state();
5199 }
5200 
5201 void MacroAssembler::restore_cpu_control_state_after_jni() {
5202   // Either restore the MXCSR register after returning from the JNI Call
5203   // or verify that it wasn't changed (with -Xcheck:jni flag).
5204   if (VM_Version::supports_sse()) {
5205     if (RestoreMXCSROnJNICalls) {
5206       ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5207     } else if (CheckJNICalls) {
5208       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5209     }
5210   }
5211   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5212   vzeroupper();
5213   // Reset k1 to 0xffff.
5214 
5215 #ifdef COMPILER2
5216   if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5217     push(rcx);
5218     movl(rcx, 0xffff);
5219     kmovwl(k1, rcx);
5220     pop(rcx);
5221   }
5222 #endif // COMPILER2
5223 
5224 #ifndef _LP64
5225   // Either restore the x87 floating pointer control word after returning
5226   // from the JNI call or verify that it wasn't changed.
5227   if (CheckJNICalls) {
5228     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5229   }
5230 #endif // _LP64
5231 }
5232 
5233 // ((OopHandle)result).resolve();
5234 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5235   assert_different_registers(result, tmp);
5236 
5237   // Only 64 bit platforms support GCs that require a tmp register
5238   // Only IN_HEAP loads require a thread_tmp register
5239   // OopHandle::resolve is an indirection like jobject.
5240   access_load_at(T_OBJECT, IN_NATIVE,
5241                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5242 }
5243 
5244 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5245   // get mirror
5246   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5247   movptr(mirror, Address(method, Method::const_offset()));
5248   movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
5249   movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
5250   movptr(mirror, Address(mirror, mirror_offset));
5251   resolve_oop_handle(mirror, tmp);
5252 }
5253 
5254 void MacroAssembler::load_klass(Register dst, Register src) {
5255 #ifdef _LP64
5256   if (UseCompressedClassPointers) {
5257     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5258     decode_klass_not_null(dst);
5259   } else
5260 #endif
5261     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5262 }
5263 
5264 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5265   load_klass(dst, src);
5266   movptr(dst, Address(dst, Klass::prototype_header_offset()));
5267 }
5268 
5269 void MacroAssembler::store_klass(Register dst, Register src) {
5270 #ifdef _LP64
5271   if (UseCompressedClassPointers) {
5272     encode_klass_not_null(src);
5273     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5274   } else
5275 #endif
5276     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5277 }
5278 
5279 void MacroAssembler::resolve_for_read(DecoratorSet decorators, Register obj) {
5280   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5281   bs->resolve_for_read(this, decorators, obj);
5282 }
5283 
5284 void MacroAssembler::resolve_for_write(DecoratorSet decorators, Register obj) {
5285   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5286   bs->resolve_for_write(this, decorators, obj);
5287 }
5288 
5289 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5290                                     Register tmp1, Register thread_tmp) {
5291   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5292   decorators = AccessInternal::decorator_fixup(decorators);
5293   bool as_raw = (decorators & AS_RAW) != 0;
5294   if (as_raw) {
5295     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5296   } else {
5297     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5298   }
5299 }
5300 
5301 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5302                                      Register tmp1, Register tmp2) {
5303   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5304   decorators = AccessInternal::decorator_fixup(decorators);
5305   bool as_raw = (decorators & AS_RAW) != 0;
5306   if (as_raw) {
5307     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5308   } else {
5309     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5310   }
5311 }
5312 
5313 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5314                                    Register thread_tmp, DecoratorSet decorators) {
5315   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5316 }
5317 
5318 // Doesn't do verfication, generates fixed size code
5319 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5320                                             Register thread_tmp, DecoratorSet decorators) {
5321   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5322 }
5323 
5324 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5325                                     Register tmp2, DecoratorSet decorators) {
5326   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5327 }
5328 
5329 // Used for storing NULLs.
5330 void MacroAssembler::store_heap_oop_null(Address dst) {
5331   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5332 }
5333 
5334 #ifdef _LP64
5335 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5336   if (UseCompressedClassPointers) {
5337     // Store to klass gap in destination
5338     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5339   }
5340 }
5341 
5342 #ifdef ASSERT
5343 void MacroAssembler::verify_heapbase(const char* msg) {
5344   assert (UseCompressedOops, "should be compressed");
5345   assert (Universe::heap() != NULL, "java heap should be initialized");
5346   if (CheckCompressedOops) {
5347     Label ok;
5348     push(rscratch1); // cmpptr trashes rscratch1
5349     cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5350     jcc(Assembler::equal, ok);
5351     STOP(msg);
5352     bind(ok);
5353     pop(rscratch1);
5354   }
5355 }
5356 #endif
5357 
5358 // Algorithm must match oop.inline.hpp encode_heap_oop.
5359 void MacroAssembler::encode_heap_oop(Register r) {
5360 #ifdef ASSERT
5361   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5362 #endif
5363   verify_oop(r, "broken oop in encode_heap_oop");
5364   if (Universe::narrow_oop_base() == NULL) {
5365     if (Universe::narrow_oop_shift() != 0) {
5366       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5367       shrq(r, LogMinObjAlignmentInBytes);
5368     }
5369     return;
5370   }
5371   testq(r, r);
5372   cmovq(Assembler::equal, r, r12_heapbase);
5373   subq(r, r12_heapbase);
5374   shrq(r, LogMinObjAlignmentInBytes);
5375 }
5376 
5377 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5378 #ifdef ASSERT
5379   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5380   if (CheckCompressedOops) {
5381     Label ok;
5382     testq(r, r);
5383     jcc(Assembler::notEqual, ok);
5384     STOP("null oop passed to encode_heap_oop_not_null");
5385     bind(ok);
5386   }
5387 #endif
5388   verify_oop(r, "broken oop in encode_heap_oop_not_null");
5389   if (Universe::narrow_oop_base() != NULL) {
5390     subq(r, r12_heapbase);
5391   }
5392   if (Universe::narrow_oop_shift() != 0) {
5393     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5394     shrq(r, LogMinObjAlignmentInBytes);
5395   }
5396 }
5397 
5398 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5399 #ifdef ASSERT
5400   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5401   if (CheckCompressedOops) {
5402     Label ok;
5403     testq(src, src);
5404     jcc(Assembler::notEqual, ok);
5405     STOP("null oop passed to encode_heap_oop_not_null2");
5406     bind(ok);
5407   }
5408 #endif
5409   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5410   if (dst != src) {
5411     movq(dst, src);
5412   }
5413   if (Universe::narrow_oop_base() != NULL) {
5414     subq(dst, r12_heapbase);
5415   }
5416   if (Universe::narrow_oop_shift() != 0) {
5417     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5418     shrq(dst, LogMinObjAlignmentInBytes);
5419   }
5420 }
5421 
5422 void  MacroAssembler::decode_heap_oop(Register r) {
5423 #ifdef ASSERT
5424   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5425 #endif
5426   if (Universe::narrow_oop_base() == NULL) {
5427     if (Universe::narrow_oop_shift() != 0) {
5428       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5429       shlq(r, LogMinObjAlignmentInBytes);
5430     }
5431   } else {
5432     Label done;
5433     shlq(r, LogMinObjAlignmentInBytes);
5434     jccb(Assembler::equal, done);
5435     addq(r, r12_heapbase);
5436     bind(done);
5437   }
5438   verify_oop(r, "broken oop in decode_heap_oop");
5439 }
5440 
5441 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
5442   // Note: it will change flags
5443   assert (UseCompressedOops, "should only be used for compressed headers");
5444   assert (Universe::heap() != NULL, "java heap should be initialized");
5445   // Cannot assert, unverified entry point counts instructions (see .ad file)
5446   // vtableStubs also counts instructions in pd_code_size_limit.
5447   // Also do not verify_oop as this is called by verify_oop.
5448   if (Universe::narrow_oop_shift() != 0) {
5449     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5450     shlq(r, LogMinObjAlignmentInBytes);
5451     if (Universe::narrow_oop_base() != NULL) {
5452       addq(r, r12_heapbase);
5453     }
5454   } else {
5455     assert (Universe::narrow_oop_base() == NULL, "sanity");
5456   }
5457 }
5458 
5459 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5460   // Note: it will change flags
5461   assert (UseCompressedOops, "should only be used for compressed headers");
5462   assert (Universe::heap() != NULL, "java heap should be initialized");
5463   // Cannot assert, unverified entry point counts instructions (see .ad file)
5464   // vtableStubs also counts instructions in pd_code_size_limit.
5465   // Also do not verify_oop as this is called by verify_oop.
5466   if (Universe::narrow_oop_shift() != 0) {
5467     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5468     if (LogMinObjAlignmentInBytes == Address::times_8) {
5469       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5470     } else {
5471       if (dst != src) {
5472         movq(dst, src);
5473       }
5474       shlq(dst, LogMinObjAlignmentInBytes);
5475       if (Universe::narrow_oop_base() != NULL) {
5476         addq(dst, r12_heapbase);
5477       }
5478     }
5479   } else {
5480     assert (Universe::narrow_oop_base() == NULL, "sanity");
5481     if (dst != src) {
5482       movq(dst, src);
5483     }
5484   }
5485 }
5486 
5487 void MacroAssembler::encode_klass_not_null(Register r) {
5488   if (Universe::narrow_klass_base() != NULL) {
5489     // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5490     assert(r != r12_heapbase, "Encoding a klass in r12");
5491     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5492     subq(r, r12_heapbase);
5493   }
5494   if (Universe::narrow_klass_shift() != 0) {
5495     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5496     shrq(r, LogKlassAlignmentInBytes);
5497   }
5498   if (Universe::narrow_klass_base() != NULL) {
5499     reinit_heapbase();
5500   }
5501 }
5502 
5503 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5504   if (dst == src) {
5505     encode_klass_not_null(src);
5506   } else {
5507     if (Universe::narrow_klass_base() != NULL) {
5508       mov64(dst, (int64_t)Universe::narrow_klass_base());
5509       negq(dst);
5510       addq(dst, src);
5511     } else {
5512       movptr(dst, src);
5513     }
5514     if (Universe::narrow_klass_shift() != 0) {
5515       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5516       shrq(dst, LogKlassAlignmentInBytes);
5517     }
5518   }
5519 }
5520 
5521 // Function instr_size_for_decode_klass_not_null() counts the instructions
5522 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5523 // when (Universe::heap() != NULL).  Hence, if the instructions they
5524 // generate change, then this method needs to be updated.
5525 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5526   assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5527   if (Universe::narrow_klass_base() != NULL) {
5528     // mov64 + addq + shlq? + mov64  (for reinit_heapbase()).
5529     return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5530   } else {
5531     // longest load decode klass function, mov64, leaq
5532     return 16;
5533   }
5534 }
5535 
5536 // !!! If the instructions that get generated here change then function
5537 // instr_size_for_decode_klass_not_null() needs to get updated.
5538 void  MacroAssembler::decode_klass_not_null(Register r) {
5539   // Note: it will change flags
5540   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5541   assert(r != r12_heapbase, "Decoding a klass in r12");
5542   // Cannot assert, unverified entry point counts instructions (see .ad file)
5543   // vtableStubs also counts instructions in pd_code_size_limit.
5544   // Also do not verify_oop as this is called by verify_oop.
5545   if (Universe::narrow_klass_shift() != 0) {
5546     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5547     shlq(r, LogKlassAlignmentInBytes);
5548   }
5549   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5550   if (Universe::narrow_klass_base() != NULL) {
5551     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5552     addq(r, r12_heapbase);
5553     reinit_heapbase();
5554   }
5555 }
5556 
5557 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5558   // Note: it will change flags
5559   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5560   if (dst == src) {
5561     decode_klass_not_null(dst);
5562   } else {
5563     // Cannot assert, unverified entry point counts instructions (see .ad file)
5564     // vtableStubs also counts instructions in pd_code_size_limit.
5565     // Also do not verify_oop as this is called by verify_oop.
5566     mov64(dst, (int64_t)Universe::narrow_klass_base());
5567     if (Universe::narrow_klass_shift() != 0) {
5568       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5569       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5570       leaq(dst, Address(dst, src, Address::times_8, 0));
5571     } else {
5572       addq(dst, src);
5573     }
5574   }
5575 }
5576 
5577 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5578   assert (UseCompressedOops, "should only be used for compressed headers");
5579   assert (Universe::heap() != NULL, "java heap should be initialized");
5580   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5581   int oop_index = oop_recorder()->find_index(obj);
5582   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5583   mov_narrow_oop(dst, oop_index, rspec);
5584 }
5585 
5586 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5587   assert (UseCompressedOops, "should only be used for compressed headers");
5588   assert (Universe::heap() != NULL, "java heap should be initialized");
5589   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5590   int oop_index = oop_recorder()->find_index(obj);
5591   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5592   mov_narrow_oop(dst, oop_index, rspec);
5593 }
5594 
5595 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5596   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5597   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5598   int klass_index = oop_recorder()->find_index(k);
5599   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5600   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5601 }
5602 
5603 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5604   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5605   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5606   int klass_index = oop_recorder()->find_index(k);
5607   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5608   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5609 }
5610 
5611 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5612   assert (UseCompressedOops, "should only be used for compressed headers");
5613   assert (Universe::heap() != NULL, "java heap should be initialized");
5614   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5615   int oop_index = oop_recorder()->find_index(obj);
5616   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5617   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5618 }
5619 
5620 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5621   assert (UseCompressedOops, "should only be used for compressed headers");
5622   assert (Universe::heap() != NULL, "java heap should be initialized");
5623   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5624   int oop_index = oop_recorder()->find_index(obj);
5625   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5626   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5627 }
5628 
5629 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5630   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5631   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5632   int klass_index = oop_recorder()->find_index(k);
5633   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5634   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5635 }
5636 
5637 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5638   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5639   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5640   int klass_index = oop_recorder()->find_index(k);
5641   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5642   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5643 }
5644 
5645 void MacroAssembler::reinit_heapbase() {
5646   if (UseCompressedOops || UseCompressedClassPointers) {
5647     if (Universe::heap() != NULL) {
5648       if (Universe::narrow_oop_base() == NULL) {
5649         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5650       } else {
5651         mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
5652       }
5653     } else {
5654       movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5655     }
5656   }
5657 }
5658 
5659 #endif // _LP64
5660 
5661 // C2 compiled method's prolog code.
5662 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
5663 
5664   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5665   // NativeJump::patch_verified_entry will be able to patch out the entry
5666   // code safely. The push to verify stack depth is ok at 5 bytes,
5667   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5668   // stack bang then we must use the 6 byte frame allocation even if
5669   // we have no frame. :-(
5670   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5671 
5672   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5673   // Remove word for return addr
5674   framesize -= wordSize;
5675   stack_bang_size -= wordSize;
5676 
5677   // Calls to C2R adapters often do not accept exceptional returns.
5678   // We require that their callers must bang for them.  But be careful, because
5679   // some VM calls (such as call site linkage) can use several kilobytes of
5680   // stack.  But the stack safety zone should account for that.
5681   // See bugs 4446381, 4468289, 4497237.
5682   if (stack_bang_size > 0) {
5683     generate_stack_overflow_check(stack_bang_size);
5684 
5685     // We always push rbp, so that on return to interpreter rbp, will be
5686     // restored correctly and we can correct the stack.
5687     push(rbp);
5688     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5689     if (PreserveFramePointer) {
5690       mov(rbp, rsp);
5691     }
5692     // Remove word for ebp
5693     framesize -= wordSize;
5694 
5695     // Create frame
5696     if (framesize) {
5697       subptr(rsp, framesize);
5698     }
5699   } else {
5700     // Create frame (force generation of a 4 byte immediate value)
5701     subptr_imm32(rsp, framesize);
5702 
5703     // Save RBP register now.
5704     framesize -= wordSize;
5705     movptr(Address(rsp, framesize), rbp);
5706     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5707     if (PreserveFramePointer) {
5708       movptr(rbp, rsp);
5709       if (framesize > 0) {
5710         addptr(rbp, framesize);
5711       }
5712     }
5713   }
5714 
5715   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5716     framesize -= wordSize;
5717     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5718   }
5719 
5720 #ifndef _LP64
5721   // If method sets FPU control word do it now
5722   if (fp_mode_24b) {
5723     fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5724   }
5725   if (UseSSE >= 2 && VerifyFPU) {
5726     verify_FPU(0, "FPU stack must be clean on entry");
5727   }
5728 #endif
5729 
5730 #ifdef ASSERT
5731   if (VerifyStackAtCalls) {
5732     Label L;
5733     push(rax);
5734     mov(rax, rsp);
5735     andptr(rax, StackAlignmentInBytes-1);
5736     cmpptr(rax, StackAlignmentInBytes-wordSize);
5737     pop(rax);
5738     jcc(Assembler::equal, L);
5739     STOP("Stack is not properly aligned!");
5740     bind(L);
5741   }
5742 #endif
5743 
5744 }
5745 
5746 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5747 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5748   // cnt - number of qwords (8-byte words).
5749   // base - start address, qword aligned.
5750   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5751   if (UseAVX >= 2) {
5752     vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5753   } else {
5754     pxor(xtmp, xtmp);
5755   }
5756   jmp(L_zero_64_bytes);
5757 
5758   BIND(L_loop);
5759   if (UseAVX >= 2) {
5760     vmovdqu(Address(base,  0), xtmp);
5761     vmovdqu(Address(base, 32), xtmp);
5762   } else {
5763     movdqu(Address(base,  0), xtmp);
5764     movdqu(Address(base, 16), xtmp);
5765     movdqu(Address(base, 32), xtmp);
5766     movdqu(Address(base, 48), xtmp);
5767   }
5768   addptr(base, 64);
5769 
5770   BIND(L_zero_64_bytes);
5771   subptr(cnt, 8);
5772   jccb(Assembler::greaterEqual, L_loop);
5773   addptr(cnt, 4);
5774   jccb(Assembler::less, L_tail);
5775   // Copy trailing 32 bytes
5776   if (UseAVX >= 2) {
5777     vmovdqu(Address(base, 0), xtmp);
5778   } else {
5779     movdqu(Address(base,  0), xtmp);
5780     movdqu(Address(base, 16), xtmp);
5781   }
5782   addptr(base, 32);
5783   subptr(cnt, 4);
5784 
5785   BIND(L_tail);
5786   addptr(cnt, 4);
5787   jccb(Assembler::lessEqual, L_end);
5788   decrement(cnt);
5789 
5790   BIND(L_sloop);
5791   movq(Address(base, 0), xtmp);
5792   addptr(base, 8);
5793   decrement(cnt);
5794   jccb(Assembler::greaterEqual, L_sloop);
5795   BIND(L_end);
5796 }
5797 
5798 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5799   // cnt - number of qwords (8-byte words).
5800   // base - start address, qword aligned.
5801   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5802   assert(base==rdi, "base register must be edi for rep stos");
5803   assert(tmp==rax,   "tmp register must be eax for rep stos");
5804   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5805   assert(InitArrayShortSize % BytesPerLong == 0,
5806     "InitArrayShortSize should be the multiple of BytesPerLong");
5807 
5808   Label DONE;
5809 
5810   if (!is_large || !UseXMMForObjInit) {
5811     xorptr(tmp, tmp);
5812   }
5813 
5814   if (!is_large) {
5815     Label LOOP, LONG;
5816     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5817     jccb(Assembler::greater, LONG);
5818 
5819     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5820 
5821     decrement(cnt);
5822     jccb(Assembler::negative, DONE); // Zero length
5823 
5824     // Use individual pointer-sized stores for small counts:
5825     BIND(LOOP);
5826     movptr(Address(base, cnt, Address::times_ptr), tmp);
5827     decrement(cnt);
5828     jccb(Assembler::greaterEqual, LOOP);
5829     jmpb(DONE);
5830 
5831     BIND(LONG);
5832   }
5833 
5834   // Use longer rep-prefixed ops for non-small counts:
5835   if (UseFastStosb) {
5836     shlptr(cnt, 3); // convert to number of bytes
5837     rep_stosb();
5838   } else if (UseXMMForObjInit) {
5839     movptr(tmp, base);
5840     xmm_clear_mem(tmp, cnt, xtmp);
5841   } else {
5842     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5843     rep_stos();
5844   }
5845 
5846   BIND(DONE);
5847 }
5848 
5849 #ifdef COMPILER2
5850 
5851 // IndexOf for constant substrings with size >= 8 chars
5852 // which don't need to be loaded through stack.
5853 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5854                                       Register cnt1, Register cnt2,
5855                                       int int_cnt2,  Register result,
5856                                       XMMRegister vec, Register tmp,
5857                                       int ae) {
5858   ShortBranchVerifier sbv(this);
5859   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5860   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5861 
5862   // This method uses the pcmpestri instruction with bound registers
5863   //   inputs:
5864   //     xmm - substring
5865   //     rax - substring length (elements count)
5866   //     mem - scanned string
5867   //     rdx - string length (elements count)
5868   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5869   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5870   //   outputs:
5871   //     rcx - matched index in string
5872   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5873   int mode   = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5874   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5875   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5876   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5877 
5878   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5879         RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5880         MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5881 
5882   // Note, inline_string_indexOf() generates checks:
5883   // if (substr.count > string.count) return -1;
5884   // if (substr.count == 0) return 0;
5885   assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5886 
5887   // Load substring.
5888   if (ae == StrIntrinsicNode::UL) {
5889     pmovzxbw(vec, Address(str2, 0));
5890   } else {
5891     movdqu(vec, Address(str2, 0));
5892   }
5893   movl(cnt2, int_cnt2);
5894   movptr(result, str1); // string addr
5895 
5896   if (int_cnt2 > stride) {
5897     jmpb(SCAN_TO_SUBSTR);
5898 
5899     // Reload substr for rescan, this code
5900     // is executed only for large substrings (> 8 chars)
5901     bind(RELOAD_SUBSTR);
5902     if (ae == StrIntrinsicNode::UL) {
5903       pmovzxbw(vec, Address(str2, 0));
5904     } else {
5905       movdqu(vec, Address(str2, 0));
5906     }
5907     negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5908 
5909     bind(RELOAD_STR);
5910     // We came here after the beginning of the substring was
5911     // matched but the rest of it was not so we need to search
5912     // again. Start from the next element after the previous match.
5913 
5914     // cnt2 is number of substring reminding elements and
5915     // cnt1 is number of string reminding elements when cmp failed.
5916     // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5917     subl(cnt1, cnt2);
5918     addl(cnt1, int_cnt2);
5919     movl(cnt2, int_cnt2); // Now restore cnt2
5920 
5921     decrementl(cnt1);     // Shift to next element
5922     cmpl(cnt1, cnt2);
5923     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5924 
5925     addptr(result, (1<<scale1));
5926 
5927   } // (int_cnt2 > 8)
5928 
5929   // Scan string for start of substr in 16-byte vectors
5930   bind(SCAN_TO_SUBSTR);
5931   pcmpestri(vec, Address(result, 0), mode);
5932   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
5933   subl(cnt1, stride);
5934   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5935   cmpl(cnt1, cnt2);
5936   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5937   addptr(result, 16);
5938   jmpb(SCAN_TO_SUBSTR);
5939 
5940   // Found a potential substr
5941   bind(FOUND_CANDIDATE);
5942   // Matched whole vector if first element matched (tmp(rcx) == 0).
5943   if (int_cnt2 == stride) {
5944     jccb(Assembler::overflow, RET_FOUND);    // OF == 1
5945   } else { // int_cnt2 > 8
5946     jccb(Assembler::overflow, FOUND_SUBSTR);
5947   }
5948   // After pcmpestri tmp(rcx) contains matched element index
5949   // Compute start addr of substr
5950   lea(result, Address(result, tmp, scale1));
5951 
5952   // Make sure string is still long enough
5953   subl(cnt1, tmp);
5954   cmpl(cnt1, cnt2);
5955   if (int_cnt2 == stride) {
5956     jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5957   } else { // int_cnt2 > 8
5958     jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5959   }
5960   // Left less then substring.
5961 
5962   bind(RET_NOT_FOUND);
5963   movl(result, -1);
5964   jmp(EXIT);
5965 
5966   if (int_cnt2 > stride) {
5967     // This code is optimized for the case when whole substring
5968     // is matched if its head is matched.
5969     bind(MATCH_SUBSTR_HEAD);
5970     pcmpestri(vec, Address(result, 0), mode);
5971     // Reload only string if does not match
5972     jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5973 
5974     Label CONT_SCAN_SUBSTR;
5975     // Compare the rest of substring (> 8 chars).
5976     bind(FOUND_SUBSTR);
5977     // First 8 chars are already matched.
5978     negptr(cnt2);
5979     addptr(cnt2, stride);
5980 
5981     bind(SCAN_SUBSTR);
5982     subl(cnt1, stride);
5983     cmpl(cnt2, -stride); // Do not read beyond substring
5984     jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5985     // Back-up strings to avoid reading beyond substring:
5986     // cnt1 = cnt1 - cnt2 + 8
5987     addl(cnt1, cnt2); // cnt2 is negative
5988     addl(cnt1, stride);
5989     movl(cnt2, stride); negptr(cnt2);
5990     bind(CONT_SCAN_SUBSTR);
5991     if (int_cnt2 < (int)G) {
5992       int tail_off1 = int_cnt2<<scale1;
5993       int tail_off2 = int_cnt2<<scale2;
5994       if (ae == StrIntrinsicNode::UL) {
5995         pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
5996       } else {
5997         movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
5998       }
5999       pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6000     } else {
6001       // calculate index in register to avoid integer overflow (int_cnt2*2)
6002       movl(tmp, int_cnt2);
6003       addptr(tmp, cnt2);
6004       if (ae == StrIntrinsicNode::UL) {
6005         pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6006       } else {
6007         movdqu(vec, Address(str2, tmp, scale2, 0));
6008       }
6009       pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6010     }
6011     // Need to reload strings pointers if not matched whole vector
6012     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6013     addptr(cnt2, stride);
6014     jcc(Assembler::negative, SCAN_SUBSTR);
6015     // Fall through if found full substring
6016 
6017   } // (int_cnt2 > 8)
6018 
6019   bind(RET_FOUND);
6020   // Found result if we matched full small substring.
6021   // Compute substr offset
6022   subptr(result, str1);
6023   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6024     shrl(result, 1); // index
6025   }
6026   bind(EXIT);
6027 
6028 } // string_indexofC8
6029 
6030 // Small strings are loaded through stack if they cross page boundary.
6031 void MacroAssembler::string_indexof(Register str1, Register str2,
6032                                     Register cnt1, Register cnt2,
6033                                     int int_cnt2,  Register result,
6034                                     XMMRegister vec, Register tmp,
6035                                     int ae) {
6036   ShortBranchVerifier sbv(this);
6037   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6038   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6039 
6040   //
6041   // int_cnt2 is length of small (< 8 chars) constant substring
6042   // or (-1) for non constant substring in which case its length
6043   // is in cnt2 register.
6044   //
6045   // Note, inline_string_indexOf() generates checks:
6046   // if (substr.count > string.count) return -1;
6047   // if (substr.count == 0) return 0;
6048   //
6049   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6050   assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6051   // This method uses the pcmpestri instruction with bound registers
6052   //   inputs:
6053   //     xmm - substring
6054   //     rax - substring length (elements count)
6055   //     mem - scanned string
6056   //     rdx - string length (elements count)
6057   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6058   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6059   //   outputs:
6060   //     rcx - matched index in string
6061   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6062   int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6063   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6064   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6065 
6066   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6067         RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6068         FOUND_CANDIDATE;
6069 
6070   { //========================================================
6071     // We don't know where these strings are located
6072     // and we can't read beyond them. Load them through stack.
6073     Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6074 
6075     movptr(tmp, rsp); // save old SP
6076 
6077     if (int_cnt2 > 0) {     // small (< 8 chars) constant substring
6078       if (int_cnt2 == (1>>scale2)) { // One byte
6079         assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6080         load_unsigned_byte(result, Address(str2, 0));
6081         movdl(vec, result); // move 32 bits
6082       } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) {  // Three bytes
6083         // Not enough header space in 32-bit VM: 12+3 = 15.
6084         movl(result, Address(str2, -1));
6085         shrl(result, 8);
6086         movdl(vec, result); // move 32 bits
6087       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) {  // One char
6088         load_unsigned_short(result, Address(str2, 0));
6089         movdl(vec, result); // move 32 bits
6090       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6091         movdl(vec, Address(str2, 0)); // move 32 bits
6092       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6093         movq(vec, Address(str2, 0));  // move 64 bits
6094       } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6095         // Array header size is 12 bytes in 32-bit VM
6096         // + 6 bytes for 3 chars == 18 bytes,
6097         // enough space to load vec and shift.
6098         assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6099         if (ae == StrIntrinsicNode::UL) {
6100           int tail_off = int_cnt2-8;
6101           pmovzxbw(vec, Address(str2, tail_off));
6102           psrldq(vec, -2*tail_off);
6103         }
6104         else {
6105           int tail_off = int_cnt2*(1<<scale2);
6106           movdqu(vec, Address(str2, tail_off-16));
6107           psrldq(vec, 16-tail_off);
6108         }
6109       }
6110     } else { // not constant substring
6111       cmpl(cnt2, stride);
6112       jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6113 
6114       // We can read beyond string if srt+16 does not cross page boundary
6115       // since heaps are aligned and mapped by pages.
6116       assert(os::vm_page_size() < (int)G, "default page should be small");
6117       movl(result, str2); // We need only low 32 bits
6118       andl(result, (os::vm_page_size()-1));
6119       cmpl(result, (os::vm_page_size()-16));
6120       jccb(Assembler::belowEqual, CHECK_STR);
6121 
6122       // Move small strings to stack to allow load 16 bytes into vec.
6123       subptr(rsp, 16);
6124       int stk_offset = wordSize-(1<<scale2);
6125       push(cnt2);
6126 
6127       bind(COPY_SUBSTR);
6128       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6129         load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6130         movb(Address(rsp, cnt2, scale2, stk_offset), result);
6131       } else if (ae == StrIntrinsicNode::UU) {
6132         load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
6133         movw(Address(rsp, cnt2, scale2, stk_offset), result);
6134       }
6135       decrement(cnt2);
6136       jccb(Assembler::notZero, COPY_SUBSTR);
6137 
6138       pop(cnt2);
6139       movptr(str2, rsp);  // New substring address
6140     } // non constant
6141 
6142     bind(CHECK_STR);
6143     cmpl(cnt1, stride);
6144     jccb(Assembler::aboveEqual, BIG_STRINGS);
6145 
6146     // Check cross page boundary.
6147     movl(result, str1); // We need only low 32 bits
6148     andl(result, (os::vm_page_size()-1));
6149     cmpl(result, (os::vm_page_size()-16));
6150     jccb(Assembler::belowEqual, BIG_STRINGS);
6151 
6152     subptr(rsp, 16);
6153     int stk_offset = -(1<<scale1);
6154     if (int_cnt2 < 0) { // not constant
6155       push(cnt2);
6156       stk_offset += wordSize;
6157     }
6158     movl(cnt2, cnt1);
6159 
6160     bind(COPY_STR);
6161     if (ae == StrIntrinsicNode::LL) {
6162       load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
6163       movb(Address(rsp, cnt2, scale1, stk_offset), result);
6164     } else {
6165       load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
6166       movw(Address(rsp, cnt2, scale1, stk_offset), result);
6167     }
6168     decrement(cnt2);
6169     jccb(Assembler::notZero, COPY_STR);
6170 
6171     if (int_cnt2 < 0) { // not constant
6172       pop(cnt2);
6173     }
6174     movptr(str1, rsp);  // New string address
6175 
6176     bind(BIG_STRINGS);
6177     // Load substring.
6178     if (int_cnt2 < 0) { // -1
6179       if (ae == StrIntrinsicNode::UL) {
6180         pmovzxbw(vec, Address(str2, 0));
6181       } else {
6182         movdqu(vec, Address(str2, 0));
6183       }
6184       push(cnt2);       // substr count
6185       push(str2);       // substr addr
6186       push(str1);       // string addr
6187     } else {
6188       // Small (< 8 chars) constant substrings are loaded already.
6189       movl(cnt2, int_cnt2);
6190     }
6191     push(tmp);  // original SP
6192 
6193   } // Finished loading
6194 
6195   //========================================================
6196   // Start search
6197   //
6198 
6199   movptr(result, str1); // string addr
6200 
6201   if (int_cnt2  < 0) {  // Only for non constant substring
6202     jmpb(SCAN_TO_SUBSTR);
6203 
6204     // SP saved at sp+0
6205     // String saved at sp+1*wordSize
6206     // Substr saved at sp+2*wordSize
6207     // Substr count saved at sp+3*wordSize
6208 
6209     // Reload substr for rescan, this code
6210     // is executed only for large substrings (> 8 chars)
6211     bind(RELOAD_SUBSTR);
6212     movptr(str2, Address(rsp, 2*wordSize));
6213     movl(cnt2, Address(rsp, 3*wordSize));
6214     if (ae == StrIntrinsicNode::UL) {
6215       pmovzxbw(vec, Address(str2, 0));
6216     } else {
6217       movdqu(vec, Address(str2, 0));
6218     }
6219     // We came here after the beginning of the substring was
6220     // matched but the rest of it was not so we need to search
6221     // again. Start from the next element after the previous match.
6222     subptr(str1, result); // Restore counter
6223     if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6224       shrl(str1, 1);
6225     }
6226     addl(cnt1, str1);
6227     decrementl(cnt1);   // Shift to next element
6228     cmpl(cnt1, cnt2);
6229     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6230 
6231     addptr(result, (1<<scale1));
6232   } // non constant
6233 
6234   // Scan string for start of substr in 16-byte vectors
6235   bind(SCAN_TO_SUBSTR);
6236   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6237   pcmpestri(vec, Address(result, 0), mode);
6238   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
6239   subl(cnt1, stride);
6240   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6241   cmpl(cnt1, cnt2);
6242   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6243   addptr(result, 16);
6244 
6245   bind(ADJUST_STR);
6246   cmpl(cnt1, stride); // Do not read beyond string
6247   jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6248   // Back-up string to avoid reading beyond string.
6249   lea(result, Address(result, cnt1, scale1, -16));
6250   movl(cnt1, stride);
6251   jmpb(SCAN_TO_SUBSTR);
6252 
6253   // Found a potential substr
6254   bind(FOUND_CANDIDATE);
6255   // After pcmpestri tmp(rcx) contains matched element index
6256 
6257   // Make sure string is still long enough
6258   subl(cnt1, tmp);
6259   cmpl(cnt1, cnt2);
6260   jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6261   // Left less then substring.
6262 
6263   bind(RET_NOT_FOUND);
6264   movl(result, -1);
6265   jmpb(CLEANUP);
6266 
6267   bind(FOUND_SUBSTR);
6268   // Compute start addr of substr
6269   lea(result, Address(result, tmp, scale1));
6270   if (int_cnt2 > 0) { // Constant substring
6271     // Repeat search for small substring (< 8 chars)
6272     // from new point without reloading substring.
6273     // Have to check that we don't read beyond string.
6274     cmpl(tmp, stride-int_cnt2);
6275     jccb(Assembler::greater, ADJUST_STR);
6276     // Fall through if matched whole substring.
6277   } else { // non constant
6278     assert(int_cnt2 == -1, "should be != 0");
6279 
6280     addl(tmp, cnt2);
6281     // Found result if we matched whole substring.
6282     cmpl(tmp, stride);
6283     jccb(Assembler::lessEqual, RET_FOUND);
6284 
6285     // Repeat search for small substring (<= 8 chars)
6286     // from new point 'str1' without reloading substring.
6287     cmpl(cnt2, stride);
6288     // Have to check that we don't read beyond string.
6289     jccb(Assembler::lessEqual, ADJUST_STR);
6290 
6291     Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6292     // Compare the rest of substring (> 8 chars).
6293     movptr(str1, result);
6294 
6295     cmpl(tmp, cnt2);
6296     // First 8 chars are already matched.
6297     jccb(Assembler::equal, CHECK_NEXT);
6298 
6299     bind(SCAN_SUBSTR);
6300     pcmpestri(vec, Address(str1, 0), mode);
6301     // Need to reload strings pointers if not matched whole vector
6302     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6303 
6304     bind(CHECK_NEXT);
6305     subl(cnt2, stride);
6306     jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6307     addptr(str1, 16);
6308     if (ae == StrIntrinsicNode::UL) {
6309       addptr(str2, 8);
6310     } else {
6311       addptr(str2, 16);
6312     }
6313     subl(cnt1, stride);
6314     cmpl(cnt2, stride); // Do not read beyond substring
6315     jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6316     // Back-up strings to avoid reading beyond substring.
6317 
6318     if (ae == StrIntrinsicNode::UL) {
6319       lea(str2, Address(str2, cnt2, scale2, -8));
6320       lea(str1, Address(str1, cnt2, scale1, -16));
6321     } else {
6322       lea(str2, Address(str2, cnt2, scale2, -16));
6323       lea(str1, Address(str1, cnt2, scale1, -16));
6324     }
6325     subl(cnt1, cnt2);
6326     movl(cnt2, stride);
6327     addl(cnt1, stride);
6328     bind(CONT_SCAN_SUBSTR);
6329     if (ae == StrIntrinsicNode::UL) {
6330       pmovzxbw(vec, Address(str2, 0));
6331     } else {
6332       movdqu(vec, Address(str2, 0));
6333     }
6334     jmp(SCAN_SUBSTR);
6335 
6336     bind(RET_FOUND_LONG);
6337     movptr(str1, Address(rsp, wordSize));
6338   } // non constant
6339 
6340   bind(RET_FOUND);
6341   // Compute substr offset
6342   subptr(result, str1);
6343   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6344     shrl(result, 1); // index
6345   }
6346   bind(CLEANUP);
6347   pop(rsp); // restore SP
6348 
6349 } // string_indexof
6350 
6351 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6352                                          XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6353   ShortBranchVerifier sbv(this);
6354   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6355 
6356   int stride = 8;
6357 
6358   Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6359         SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6360         RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6361         FOUND_SEQ_CHAR, DONE_LABEL;
6362 
6363   movptr(result, str1);
6364   if (UseAVX >= 2) {
6365     cmpl(cnt1, stride);
6366     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6367     cmpl(cnt1, 2*stride);
6368     jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6369     movdl(vec1, ch);
6370     vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6371     vpxor(vec2, vec2);
6372     movl(tmp, cnt1);
6373     andl(tmp, 0xFFFFFFF0);  //vector count (in chars)
6374     andl(cnt1,0x0000000F);  //tail count (in chars)
6375 
6376     bind(SCAN_TO_16_CHAR_LOOP);
6377     vmovdqu(vec3, Address(result, 0));
6378     vpcmpeqw(vec3, vec3, vec1, 1);
6379     vptest(vec2, vec3);
6380     jcc(Assembler::carryClear, FOUND_CHAR);
6381     addptr(result, 32);
6382     subl(tmp, 2*stride);
6383     jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6384     jmp(SCAN_TO_8_CHAR);
6385     bind(SCAN_TO_8_CHAR_INIT);
6386     movdl(vec1, ch);
6387     pshuflw(vec1, vec1, 0x00);
6388     pshufd(vec1, vec1, 0);
6389     pxor(vec2, vec2);
6390   }
6391   bind(SCAN_TO_8_CHAR);
6392   cmpl(cnt1, stride);
6393   if (UseAVX >= 2) {
6394     jcc(Assembler::less, SCAN_TO_CHAR);
6395   } else {
6396     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6397     movdl(vec1, ch);
6398     pshuflw(vec1, vec1, 0x00);
6399     pshufd(vec1, vec1, 0);
6400     pxor(vec2, vec2);
6401   }
6402   movl(tmp, cnt1);
6403   andl(tmp, 0xFFFFFFF8);  //vector count (in chars)
6404   andl(cnt1,0x00000007);  //tail count (in chars)
6405 
6406   bind(SCAN_TO_8_CHAR_LOOP);
6407   movdqu(vec3, Address(result, 0));
6408   pcmpeqw(vec3, vec1);
6409   ptest(vec2, vec3);
6410   jcc(Assembler::carryClear, FOUND_CHAR);
6411   addptr(result, 16);
6412   subl(tmp, stride);
6413   jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6414   bind(SCAN_TO_CHAR);
6415   testl(cnt1, cnt1);
6416   jcc(Assembler::zero, RET_NOT_FOUND);
6417   bind(SCAN_TO_CHAR_LOOP);
6418   load_unsigned_short(tmp, Address(result, 0));
6419   cmpl(ch, tmp);
6420   jccb(Assembler::equal, FOUND_SEQ_CHAR);
6421   addptr(result, 2);
6422   subl(cnt1, 1);
6423   jccb(Assembler::zero, RET_NOT_FOUND);
6424   jmp(SCAN_TO_CHAR_LOOP);
6425 
6426   bind(RET_NOT_FOUND);
6427   movl(result, -1);
6428   jmpb(DONE_LABEL);
6429 
6430   bind(FOUND_CHAR);
6431   if (UseAVX >= 2) {
6432     vpmovmskb(tmp, vec3);
6433   } else {
6434     pmovmskb(tmp, vec3);
6435   }
6436   bsfl(ch, tmp);
6437   addl(result, ch);
6438 
6439   bind(FOUND_SEQ_CHAR);
6440   subptr(result, str1);
6441   shrl(result, 1);
6442 
6443   bind(DONE_LABEL);
6444 } // string_indexof_char
6445 
6446 // helper function for string_compare
6447 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6448                                         Address::ScaleFactor scale, Address::ScaleFactor scale1,
6449                                         Address::ScaleFactor scale2, Register index, int ae) {
6450   if (ae == StrIntrinsicNode::LL) {
6451     load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6452     load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6453   } else if (ae == StrIntrinsicNode::UU) {
6454     load_unsigned_short(elem1, Address(str1, index, scale, 0));
6455     load_unsigned_short(elem2, Address(str2, index, scale, 0));
6456   } else {
6457     load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6458     load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6459   }
6460 }
6461 
6462 // Compare strings, used for char[] and byte[].
6463 void MacroAssembler::string_compare(Register str1, Register str2,
6464                                     Register cnt1, Register cnt2, Register result,
6465                                     XMMRegister vec1, int ae) {
6466   ShortBranchVerifier sbv(this);
6467   Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6468   Label COMPARE_WIDE_VECTORS_LOOP_FAILED;  // used only _LP64 && AVX3
6469   int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6470   int stride2x2 = 0x40;
6471   Address::ScaleFactor scale = Address::no_scale;
6472   Address::ScaleFactor scale1 = Address::no_scale;
6473   Address::ScaleFactor scale2 = Address::no_scale;
6474 
6475   if (ae != StrIntrinsicNode::LL) {
6476     stride2x2 = 0x20;
6477   }
6478 
6479   if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6480     shrl(cnt2, 1);
6481   }
6482   // Compute the minimum of the string lengths and the
6483   // difference of the string lengths (stack).
6484   // Do the conditional move stuff
6485   movl(result, cnt1);
6486   subl(cnt1, cnt2);
6487   push(cnt1);
6488   cmov32(Assembler::lessEqual, cnt2, result);    // cnt2 = min(cnt1, cnt2)
6489 
6490   // Is the minimum length zero?
6491   testl(cnt2, cnt2);
6492   jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6493   if (ae == StrIntrinsicNode::LL) {
6494     // Load first bytes
6495     load_unsigned_byte(result, Address(str1, 0));  // result = str1[0]
6496     load_unsigned_byte(cnt1, Address(str2, 0));    // cnt1   = str2[0]
6497   } else if (ae == StrIntrinsicNode::UU) {
6498     // Load first characters
6499     load_unsigned_short(result, Address(str1, 0));
6500     load_unsigned_short(cnt1, Address(str2, 0));
6501   } else {
6502     load_unsigned_byte(result, Address(str1, 0));
6503     load_unsigned_short(cnt1, Address(str2, 0));
6504   }
6505   subl(result, cnt1);
6506   jcc(Assembler::notZero,  POP_LABEL);
6507 
6508   if (ae == StrIntrinsicNode::UU) {
6509     // Divide length by 2 to get number of chars
6510     shrl(cnt2, 1);
6511   }
6512   cmpl(cnt2, 1);
6513   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6514 
6515   // Check if the strings start at the same location and setup scale and stride
6516   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6517     cmpptr(str1, str2);
6518     jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6519     if (ae == StrIntrinsicNode::LL) {
6520       scale = Address::times_1;
6521       stride = 16;
6522     } else {
6523       scale = Address::times_2;
6524       stride = 8;
6525     }
6526   } else {
6527     scale1 = Address::times_1;
6528     scale2 = Address::times_2;
6529     // scale not used
6530     stride = 8;
6531   }
6532 
6533   if (UseAVX >= 2 && UseSSE42Intrinsics) {
6534     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6535     Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6536     Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6537     Label COMPARE_TAIL_LONG;
6538     Label COMPARE_WIDE_VECTORS_LOOP_AVX3;  // used only _LP64 && AVX3
6539 
6540     int pcmpmask = 0x19;
6541     if (ae == StrIntrinsicNode::LL) {
6542       pcmpmask &= ~0x01;
6543     }
6544 
6545     // Setup to compare 16-chars (32-bytes) vectors,
6546     // start from first character again because it has aligned address.
6547     if (ae == StrIntrinsicNode::LL) {
6548       stride2 = 32;
6549     } else {
6550       stride2 = 16;
6551     }
6552     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6553       adr_stride = stride << scale;
6554     } else {
6555       adr_stride1 = 8;  //stride << scale1;
6556       adr_stride2 = 16; //stride << scale2;
6557     }
6558 
6559     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6560     // rax and rdx are used by pcmpestri as elements counters
6561     movl(result, cnt2);
6562     andl(cnt2, ~(stride2-1));   // cnt2 holds the vector count
6563     jcc(Assembler::zero, COMPARE_TAIL_LONG);
6564 
6565     // fast path : compare first 2 8-char vectors.
6566     bind(COMPARE_16_CHARS);
6567     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6568       movdqu(vec1, Address(str1, 0));
6569     } else {
6570       pmovzxbw(vec1, Address(str1, 0));
6571     }
6572     pcmpestri(vec1, Address(str2, 0), pcmpmask);
6573     jccb(Assembler::below, COMPARE_INDEX_CHAR);
6574 
6575     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6576       movdqu(vec1, Address(str1, adr_stride));
6577       pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6578     } else {
6579       pmovzxbw(vec1, Address(str1, adr_stride1));
6580       pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6581     }
6582     jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6583     addl(cnt1, stride);
6584 
6585     // Compare the characters at index in cnt1
6586     bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6587     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6588     subl(result, cnt2);
6589     jmp(POP_LABEL);
6590 
6591     // Setup the registers to start vector comparison loop
6592     bind(COMPARE_WIDE_VECTORS);
6593     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6594       lea(str1, Address(str1, result, scale));
6595       lea(str2, Address(str2, result, scale));
6596     } else {
6597       lea(str1, Address(str1, result, scale1));
6598       lea(str2, Address(str2, result, scale2));
6599     }
6600     subl(result, stride2);
6601     subl(cnt2, stride2);
6602     jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6603     negptr(result);
6604 
6605     //  In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6606     bind(COMPARE_WIDE_VECTORS_LOOP);
6607 
6608 #ifdef _LP64
6609     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6610       cmpl(cnt2, stride2x2);
6611       jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6612       testl(cnt2, stride2x2-1);   // cnt2 holds the vector count
6613       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2);   // means we cannot subtract by 0x40
6614 
6615       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6616       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6617         evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6618         evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6619       } else {
6620         vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6621         evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6622       }
6623       kortestql(k7, k7);
6624       jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED);     // miscompare
6625       addptr(result, stride2x2);  // update since we already compared at this addr
6626       subl(cnt2, stride2x2);      // and sub the size too
6627       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6628 
6629       vpxor(vec1, vec1);
6630       jmpb(COMPARE_WIDE_TAIL);
6631     }//if (VM_Version::supports_avx512vlbw())
6632 #endif // _LP64
6633 
6634 
6635     bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6636     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6637       vmovdqu(vec1, Address(str1, result, scale));
6638       vpxor(vec1, Address(str2, result, scale));
6639     } else {
6640       vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6641       vpxor(vec1, Address(str2, result, scale2));
6642     }
6643     vptest(vec1, vec1);
6644     jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6645     addptr(result, stride2);
6646     subl(cnt2, stride2);
6647     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6648     // clean upper bits of YMM registers
6649     vpxor(vec1, vec1);
6650 
6651     // compare wide vectors tail
6652     bind(COMPARE_WIDE_TAIL);
6653     testptr(result, result);
6654     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6655 
6656     movl(result, stride2);
6657     movl(cnt2, result);
6658     negptr(result);
6659     jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6660 
6661     // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6662     bind(VECTOR_NOT_EQUAL);
6663     // clean upper bits of YMM registers
6664     vpxor(vec1, vec1);
6665     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6666       lea(str1, Address(str1, result, scale));
6667       lea(str2, Address(str2, result, scale));
6668     } else {
6669       lea(str1, Address(str1, result, scale1));
6670       lea(str2, Address(str2, result, scale2));
6671     }
6672     jmp(COMPARE_16_CHARS);
6673 
6674     // Compare tail chars, length between 1 to 15 chars
6675     bind(COMPARE_TAIL_LONG);
6676     movl(cnt2, result);
6677     cmpl(cnt2, stride);
6678     jcc(Assembler::less, COMPARE_SMALL_STR);
6679 
6680     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6681       movdqu(vec1, Address(str1, 0));
6682     } else {
6683       pmovzxbw(vec1, Address(str1, 0));
6684     }
6685     pcmpestri(vec1, Address(str2, 0), pcmpmask);
6686     jcc(Assembler::below, COMPARE_INDEX_CHAR);
6687     subptr(cnt2, stride);
6688     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6689     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6690       lea(str1, Address(str1, result, scale));
6691       lea(str2, Address(str2, result, scale));
6692     } else {
6693       lea(str1, Address(str1, result, scale1));
6694       lea(str2, Address(str2, result, scale2));
6695     }
6696     negptr(cnt2);
6697     jmpb(WHILE_HEAD_LABEL);
6698 
6699     bind(COMPARE_SMALL_STR);
6700   } else if (UseSSE42Intrinsics) {
6701     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6702     int pcmpmask = 0x19;
6703     // Setup to compare 8-char (16-byte) vectors,
6704     // start from first character again because it has aligned address.
6705     movl(result, cnt2);
6706     andl(cnt2, ~(stride - 1));   // cnt2 holds the vector count
6707     if (ae == StrIntrinsicNode::LL) {
6708       pcmpmask &= ~0x01;
6709     }
6710     jcc(Assembler::zero, COMPARE_TAIL);
6711     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6712       lea(str1, Address(str1, result, scale));
6713       lea(str2, Address(str2, result, scale));
6714     } else {
6715       lea(str1, Address(str1, result, scale1));
6716       lea(str2, Address(str2, result, scale2));
6717     }
6718     negptr(result);
6719 
6720     // pcmpestri
6721     //   inputs:
6722     //     vec1- substring
6723     //     rax - negative string length (elements count)
6724     //     mem - scanned string
6725     //     rdx - string length (elements count)
6726     //     pcmpmask - cmp mode: 11000 (string compare with negated result)
6727     //               + 00 (unsigned bytes) or  + 01 (unsigned shorts)
6728     //   outputs:
6729     //     rcx - first mismatched element index
6730     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6731 
6732     bind(COMPARE_WIDE_VECTORS);
6733     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6734       movdqu(vec1, Address(str1, result, scale));
6735       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6736     } else {
6737       pmovzxbw(vec1, Address(str1, result, scale1));
6738       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6739     }
6740     // After pcmpestri cnt1(rcx) contains mismatched element index
6741 
6742     jccb(Assembler::below, VECTOR_NOT_EQUAL);  // CF==1
6743     addptr(result, stride);
6744     subptr(cnt2, stride);
6745     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6746 
6747     // compare wide vectors tail
6748     testptr(result, result);
6749     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6750 
6751     movl(cnt2, stride);
6752     movl(result, stride);
6753     negptr(result);
6754     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6755       movdqu(vec1, Address(str1, result, scale));
6756       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6757     } else {
6758       pmovzxbw(vec1, Address(str1, result, scale1));
6759       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6760     }
6761     jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6762 
6763     // Mismatched characters in the vectors
6764     bind(VECTOR_NOT_EQUAL);
6765     addptr(cnt1, result);
6766     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6767     subl(result, cnt2);
6768     jmpb(POP_LABEL);
6769 
6770     bind(COMPARE_TAIL); // limit is zero
6771     movl(cnt2, result);
6772     // Fallthru to tail compare
6773   }
6774   // Shift str2 and str1 to the end of the arrays, negate min
6775   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6776     lea(str1, Address(str1, cnt2, scale));
6777     lea(str2, Address(str2, cnt2, scale));
6778   } else {
6779     lea(str1, Address(str1, cnt2, scale1));
6780     lea(str2, Address(str2, cnt2, scale2));
6781   }
6782   decrementl(cnt2);  // first character was compared already
6783   negptr(cnt2);
6784 
6785   // Compare the rest of the elements
6786   bind(WHILE_HEAD_LABEL);
6787   load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6788   subl(result, cnt1);
6789   jccb(Assembler::notZero, POP_LABEL);
6790   increment(cnt2);
6791   jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6792 
6793   // Strings are equal up to min length.  Return the length difference.
6794   bind(LENGTH_DIFF_LABEL);
6795   pop(result);
6796   if (ae == StrIntrinsicNode::UU) {
6797     // Divide diff by 2 to get number of chars
6798     sarl(result, 1);
6799   }
6800   jmpb(DONE_LABEL);
6801 
6802 #ifdef _LP64
6803   if (VM_Version::supports_avx512vlbw()) {
6804 
6805     bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6806 
6807     kmovql(cnt1, k7);
6808     notq(cnt1);
6809     bsfq(cnt2, cnt1);
6810     if (ae != StrIntrinsicNode::LL) {
6811       // Divide diff by 2 to get number of chars
6812       sarl(cnt2, 1);
6813     }
6814     addq(result, cnt2);
6815     if (ae == StrIntrinsicNode::LL) {
6816       load_unsigned_byte(cnt1, Address(str2, result));
6817       load_unsigned_byte(result, Address(str1, result));
6818     } else if (ae == StrIntrinsicNode::UU) {
6819       load_unsigned_short(cnt1, Address(str2, result, scale));
6820       load_unsigned_short(result, Address(str1, result, scale));
6821     } else {
6822       load_unsigned_short(cnt1, Address(str2, result, scale2));
6823       load_unsigned_byte(result, Address(str1, result, scale1));
6824     }
6825     subl(result, cnt1);
6826     jmpb(POP_LABEL);
6827   }//if (VM_Version::supports_avx512vlbw())
6828 #endif // _LP64
6829 
6830   // Discard the stored length difference
6831   bind(POP_LABEL);
6832   pop(cnt1);
6833 
6834   // That's it
6835   bind(DONE_LABEL);
6836   if(ae == StrIntrinsicNode::UL) {
6837     negl(result);
6838   }
6839 
6840 }
6841 
6842 // Search for Non-ASCII character (Negative byte value) in a byte array,
6843 // return true if it has any and false otherwise.
6844 //   ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6845 //   @HotSpotIntrinsicCandidate
6846 //   private static boolean hasNegatives(byte[] ba, int off, int len) {
6847 //     for (int i = off; i < off + len; i++) {
6848 //       if (ba[i] < 0) {
6849 //         return true;
6850 //       }
6851 //     }
6852 //     return false;
6853 //   }
6854 void MacroAssembler::has_negatives(Register ary1, Register len,
6855   Register result, Register tmp1,
6856   XMMRegister vec1, XMMRegister vec2) {
6857   // rsi: byte array
6858   // rcx: len
6859   // rax: result
6860   ShortBranchVerifier sbv(this);
6861   assert_different_registers(ary1, len, result, tmp1);
6862   assert_different_registers(vec1, vec2);
6863   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6864 
6865   // len == 0
6866   testl(len, len);
6867   jcc(Assembler::zero, FALSE_LABEL);
6868 
6869   if ((UseAVX > 2) && // AVX512
6870     VM_Version::supports_avx512vlbw() &&
6871     VM_Version::supports_bmi2()) {
6872 
6873     Label test_64_loop, test_tail;
6874     Register tmp3_aliased = len;
6875 
6876     movl(tmp1, len);
6877     vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6878 
6879     andl(tmp1, 64 - 1);   // tail count (in chars) 0x3F
6880     andl(len, ~(64 - 1));    // vector count (in chars)
6881     jccb(Assembler::zero, test_tail);
6882 
6883     lea(ary1, Address(ary1, len, Address::times_1));
6884     negptr(len);
6885 
6886     bind(test_64_loop);
6887     // Check whether our 64 elements of size byte contain negatives
6888     evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6889     kortestql(k2, k2);
6890     jcc(Assembler::notZero, TRUE_LABEL);
6891 
6892     addptr(len, 64);
6893     jccb(Assembler::notZero, test_64_loop);
6894 
6895 
6896     bind(test_tail);
6897     // bail out when there is nothing to be done
6898     testl(tmp1, -1);
6899     jcc(Assembler::zero, FALSE_LABEL);
6900 
6901     // ~(~0 << len) applied up to two times (for 32-bit scenario)
6902 #ifdef _LP64
6903     mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6904     shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6905     notq(tmp3_aliased);
6906     kmovql(k3, tmp3_aliased);
6907 #else
6908     Label k_init;
6909     jmp(k_init);
6910 
6911     // We could not read 64-bits from a general purpose register thus we move
6912     // data required to compose 64 1's to the instruction stream
6913     // We emit 64 byte wide series of elements from 0..63 which later on would
6914     // be used as a compare targets with tail count contained in tmp1 register.
6915     // Result would be a k register having tmp1 consecutive number or 1
6916     // counting from least significant bit.
6917     address tmp = pc();
6918     emit_int64(0x0706050403020100);
6919     emit_int64(0x0F0E0D0C0B0A0908);
6920     emit_int64(0x1716151413121110);
6921     emit_int64(0x1F1E1D1C1B1A1918);
6922     emit_int64(0x2726252423222120);
6923     emit_int64(0x2F2E2D2C2B2A2928);
6924     emit_int64(0x3736353433323130);
6925     emit_int64(0x3F3E3D3C3B3A3938);
6926 
6927     bind(k_init);
6928     lea(len, InternalAddress(tmp));
6929     // create mask to test for negative byte inside a vector
6930     evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6931     evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
6932 
6933 #endif
6934     evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6935     ktestq(k2, k3);
6936     jcc(Assembler::notZero, TRUE_LABEL);
6937 
6938     jmp(FALSE_LABEL);
6939   } else {
6940     movl(result, len); // copy
6941 
6942     if (UseAVX == 2 && UseSSE >= 2) {
6943       // With AVX2, use 32-byte vector compare
6944       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6945 
6946       // Compare 32-byte vectors
6947       andl(result, 0x0000001f);  //   tail count (in bytes)
6948       andl(len, 0xffffffe0);   // vector count (in bytes)
6949       jccb(Assembler::zero, COMPARE_TAIL);
6950 
6951       lea(ary1, Address(ary1, len, Address::times_1));
6952       negptr(len);
6953 
6954       movl(tmp1, 0x80808080);   // create mask to test for Unicode chars in vector
6955       movdl(vec2, tmp1);
6956       vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6957 
6958       bind(COMPARE_WIDE_VECTORS);
6959       vmovdqu(vec1, Address(ary1, len, Address::times_1));
6960       vptest(vec1, vec2);
6961       jccb(Assembler::notZero, TRUE_LABEL);
6962       addptr(len, 32);
6963       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6964 
6965       testl(result, result);
6966       jccb(Assembler::zero, FALSE_LABEL);
6967 
6968       vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6969       vptest(vec1, vec2);
6970       jccb(Assembler::notZero, TRUE_LABEL);
6971       jmpb(FALSE_LABEL);
6972 
6973       bind(COMPARE_TAIL); // len is zero
6974       movl(len, result);
6975       // Fallthru to tail compare
6976     } else if (UseSSE42Intrinsics) {
6977       // With SSE4.2, use double quad vector compare
6978       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6979 
6980       // Compare 16-byte vectors
6981       andl(result, 0x0000000f);  //   tail count (in bytes)
6982       andl(len, 0xfffffff0);   // vector count (in bytes)
6983       jccb(Assembler::zero, COMPARE_TAIL);
6984 
6985       lea(ary1, Address(ary1, len, Address::times_1));
6986       negptr(len);
6987 
6988       movl(tmp1, 0x80808080);
6989       movdl(vec2, tmp1);
6990       pshufd(vec2, vec2, 0);
6991 
6992       bind(COMPARE_WIDE_VECTORS);
6993       movdqu(vec1, Address(ary1, len, Address::times_1));
6994       ptest(vec1, vec2);
6995       jccb(Assembler::notZero, TRUE_LABEL);
6996       addptr(len, 16);
6997       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6998 
6999       testl(result, result);
7000       jccb(Assembler::zero, FALSE_LABEL);
7001 
7002       movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7003       ptest(vec1, vec2);
7004       jccb(Assembler::notZero, TRUE_LABEL);
7005       jmpb(FALSE_LABEL);
7006 
7007       bind(COMPARE_TAIL); // len is zero
7008       movl(len, result);
7009       // Fallthru to tail compare
7010     }
7011   }
7012   // Compare 4-byte vectors
7013   andl(len, 0xfffffffc); // vector count (in bytes)
7014   jccb(Assembler::zero, COMPARE_CHAR);
7015 
7016   lea(ary1, Address(ary1, len, Address::times_1));
7017   negptr(len);
7018 
7019   bind(COMPARE_VECTORS);
7020   movl(tmp1, Address(ary1, len, Address::times_1));
7021   andl(tmp1, 0x80808080);
7022   jccb(Assembler::notZero, TRUE_LABEL);
7023   addptr(len, 4);
7024   jcc(Assembler::notZero, COMPARE_VECTORS);
7025 
7026   // Compare trailing char (final 2 bytes), if any
7027   bind(COMPARE_CHAR);
7028   testl(result, 0x2);   // tail  char
7029   jccb(Assembler::zero, COMPARE_BYTE);
7030   load_unsigned_short(tmp1, Address(ary1, 0));
7031   andl(tmp1, 0x00008080);
7032   jccb(Assembler::notZero, TRUE_LABEL);
7033   subptr(result, 2);
7034   lea(ary1, Address(ary1, 2));
7035 
7036   bind(COMPARE_BYTE);
7037   testl(result, 0x1);   // tail  byte
7038   jccb(Assembler::zero, FALSE_LABEL);
7039   load_unsigned_byte(tmp1, Address(ary1, 0));
7040   andl(tmp1, 0x00000080);
7041   jccb(Assembler::notEqual, TRUE_LABEL);
7042   jmpb(FALSE_LABEL);
7043 
7044   bind(TRUE_LABEL);
7045   movl(result, 1);   // return true
7046   jmpb(DONE);
7047 
7048   bind(FALSE_LABEL);
7049   xorl(result, result); // return false
7050 
7051   // That's it
7052   bind(DONE);
7053   if (UseAVX >= 2 && UseSSE >= 2) {
7054     // clean upper bits of YMM registers
7055     vpxor(vec1, vec1);
7056     vpxor(vec2, vec2);
7057   }
7058 }
7059 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
7060 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7061                                    Register limit, Register result, Register chr,
7062                                    XMMRegister vec1, XMMRegister vec2, bool is_char) {
7063   ShortBranchVerifier sbv(this);
7064   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7065 
7066   int length_offset  = arrayOopDesc::length_offset_in_bytes();
7067   int base_offset    = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7068 
7069   if (is_array_equ) {
7070     // Check the input args
7071     cmpoop(ary1, ary2);
7072     jcc(Assembler::equal, TRUE_LABEL);
7073 
7074     // Need additional checks for arrays_equals.
7075     testptr(ary1, ary1);
7076     jcc(Assembler::zero, FALSE_LABEL);
7077     testptr(ary2, ary2);
7078     jcc(Assembler::zero, FALSE_LABEL);
7079 
7080     // Check the lengths
7081     movl(limit, Address(ary1, length_offset));
7082     cmpl(limit, Address(ary2, length_offset));
7083     jcc(Assembler::notEqual, FALSE_LABEL);
7084   }
7085 
7086   // count == 0
7087   testl(limit, limit);
7088   jcc(Assembler::zero, TRUE_LABEL);
7089 
7090   if (is_array_equ) {
7091     // Load array address
7092     lea(ary1, Address(ary1, base_offset));
7093     lea(ary2, Address(ary2, base_offset));
7094   }
7095 
7096   if (is_array_equ && is_char) {
7097     // arrays_equals when used for char[].
7098     shll(limit, 1);      // byte count != 0
7099   }
7100   movl(result, limit); // copy
7101 
7102   if (UseAVX >= 2) {
7103     // With AVX2, use 32-byte vector compare
7104     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7105 
7106     // Compare 32-byte vectors
7107     andl(result, 0x0000001f);  //   tail count (in bytes)
7108     andl(limit, 0xffffffe0);   // vector count (in bytes)
7109     jcc(Assembler::zero, COMPARE_TAIL);
7110 
7111     lea(ary1, Address(ary1, limit, Address::times_1));
7112     lea(ary2, Address(ary2, limit, Address::times_1));
7113     negptr(limit);
7114 
7115     bind(COMPARE_WIDE_VECTORS);
7116 
7117 #ifdef _LP64
7118     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7119       Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7120 
7121       cmpl(limit, -64);
7122       jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7123 
7124       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7125 
7126       evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
7127       evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
7128       kortestql(k7, k7);
7129       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
7130       addptr(limit, 64);  // update since we already compared at this addr
7131       cmpl(limit, -64);
7132       jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7133 
7134       // At this point we may still need to compare -limit+result bytes.
7135       // We could execute the next two instruction and just continue via non-wide path:
7136       //  cmpl(limit, 0);
7137       //  jcc(Assembler::equal, COMPARE_TAIL);  // true
7138       // But since we stopped at the points ary{1,2}+limit which are
7139       // not farther than 64 bytes from the ends of arrays ary{1,2}+result
7140       // (|limit| <= 32 and result < 32),
7141       // we may just compare the last 64 bytes.
7142       //
7143       addptr(result, -64);   // it is safe, bc we just came from this area
7144       evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
7145       evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
7146       kortestql(k7, k7);
7147       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
7148 
7149       jmp(TRUE_LABEL);
7150 
7151       bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7152 
7153     }//if (VM_Version::supports_avx512vlbw())
7154 #endif //_LP64
7155 
7156     vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7157     vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7158     vpxor(vec1, vec2);
7159 
7160     vptest(vec1, vec1);
7161     jcc(Assembler::notZero, FALSE_LABEL);
7162     addptr(limit, 32);
7163     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7164 
7165     testl(result, result);
7166     jcc(Assembler::zero, TRUE_LABEL);
7167 
7168     vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7169     vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7170     vpxor(vec1, vec2);
7171 
7172     vptest(vec1, vec1);
7173     jccb(Assembler::notZero, FALSE_LABEL);
7174     jmpb(TRUE_LABEL);
7175 
7176     bind(COMPARE_TAIL); // limit is zero
7177     movl(limit, result);
7178     // Fallthru to tail compare
7179   } else if (UseSSE42Intrinsics) {
7180     // With SSE4.2, use double quad vector compare
7181     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7182 
7183     // Compare 16-byte vectors
7184     andl(result, 0x0000000f);  //   tail count (in bytes)
7185     andl(limit, 0xfffffff0);   // vector count (in bytes)
7186     jcc(Assembler::zero, COMPARE_TAIL);
7187 
7188     lea(ary1, Address(ary1, limit, Address::times_1));
7189     lea(ary2, Address(ary2, limit, Address::times_1));
7190     negptr(limit);
7191 
7192     bind(COMPARE_WIDE_VECTORS);
7193     movdqu(vec1, Address(ary1, limit, Address::times_1));
7194     movdqu(vec2, Address(ary2, limit, Address::times_1));
7195     pxor(vec1, vec2);
7196 
7197     ptest(vec1, vec1);
7198     jcc(Assembler::notZero, FALSE_LABEL);
7199     addptr(limit, 16);
7200     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7201 
7202     testl(result, result);
7203     jcc(Assembler::zero, TRUE_LABEL);
7204 
7205     movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7206     movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7207     pxor(vec1, vec2);
7208 
7209     ptest(vec1, vec1);
7210     jccb(Assembler::notZero, FALSE_LABEL);
7211     jmpb(TRUE_LABEL);
7212 
7213     bind(COMPARE_TAIL); // limit is zero
7214     movl(limit, result);
7215     // Fallthru to tail compare
7216   }
7217 
7218   // Compare 4-byte vectors
7219   andl(limit, 0xfffffffc); // vector count (in bytes)
7220   jccb(Assembler::zero, COMPARE_CHAR);
7221 
7222   lea(ary1, Address(ary1, limit, Address::times_1));
7223   lea(ary2, Address(ary2, limit, Address::times_1));
7224   negptr(limit);
7225 
7226   bind(COMPARE_VECTORS);
7227   movl(chr, Address(ary1, limit, Address::times_1));
7228   cmpl(chr, Address(ary2, limit, Address::times_1));
7229   jccb(Assembler::notEqual, FALSE_LABEL);
7230   addptr(limit, 4);
7231   jcc(Assembler::notZero, COMPARE_VECTORS);
7232 
7233   // Compare trailing char (final 2 bytes), if any
7234   bind(COMPARE_CHAR);
7235   testl(result, 0x2);   // tail  char
7236   jccb(Assembler::zero, COMPARE_BYTE);
7237   load_unsigned_short(chr, Address(ary1, 0));
7238   load_unsigned_short(limit, Address(ary2, 0));
7239   cmpl(chr, limit);
7240   jccb(Assembler::notEqual, FALSE_LABEL);
7241 
7242   if (is_array_equ && is_char) {
7243     bind(COMPARE_BYTE);
7244   } else {
7245     lea(ary1, Address(ary1, 2));
7246     lea(ary2, Address(ary2, 2));
7247 
7248     bind(COMPARE_BYTE);
7249     testl(result, 0x1);   // tail  byte
7250     jccb(Assembler::zero, TRUE_LABEL);
7251     load_unsigned_byte(chr, Address(ary1, 0));
7252     load_unsigned_byte(limit, Address(ary2, 0));
7253     cmpl(chr, limit);
7254     jccb(Assembler::notEqual, FALSE_LABEL);
7255   }
7256   bind(TRUE_LABEL);
7257   movl(result, 1);   // return true
7258   jmpb(DONE);
7259 
7260   bind(FALSE_LABEL);
7261   xorl(result, result); // return false
7262 
7263   // That's it
7264   bind(DONE);
7265   if (UseAVX >= 2) {
7266     // clean upper bits of YMM registers
7267     vpxor(vec1, vec1);
7268     vpxor(vec2, vec2);
7269   }
7270 }
7271 
7272 #endif
7273 
7274 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7275                                    Register to, Register value, Register count,
7276                                    Register rtmp, XMMRegister xtmp) {
7277   ShortBranchVerifier sbv(this);
7278   assert_different_registers(to, value, count, rtmp);
7279   Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
7280   Label L_fill_2_bytes, L_fill_4_bytes;
7281 
7282   int shift = -1;
7283   switch (t) {
7284     case T_BYTE:
7285       shift = 2;
7286       break;
7287     case T_SHORT:
7288       shift = 1;
7289       break;
7290     case T_INT:
7291       shift = 0;
7292       break;
7293     default: ShouldNotReachHere();
7294   }
7295 
7296   if (t == T_BYTE) {
7297     andl(value, 0xff);
7298     movl(rtmp, value);
7299     shll(rtmp, 8);
7300     orl(value, rtmp);
7301   }
7302   if (t == T_SHORT) {
7303     andl(value, 0xffff);
7304   }
7305   if (t == T_BYTE || t == T_SHORT) {
7306     movl(rtmp, value);
7307     shll(rtmp, 16);
7308     orl(value, rtmp);
7309   }
7310 
7311   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7312   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7313   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7314     // align source address at 4 bytes address boundary
7315     if (t == T_BYTE) {
7316       // One byte misalignment happens only for byte arrays
7317       testptr(to, 1);
7318       jccb(Assembler::zero, L_skip_align1);
7319       movb(Address(to, 0), value);
7320       increment(to);
7321       decrement(count);
7322       BIND(L_skip_align1);
7323     }
7324     // Two bytes misalignment happens only for byte and short (char) arrays
7325     testptr(to, 2);
7326     jccb(Assembler::zero, L_skip_align2);
7327     movw(Address(to, 0), value);
7328     addptr(to, 2);
7329     subl(count, 1<<(shift-1));
7330     BIND(L_skip_align2);
7331   }
7332   if (UseSSE < 2) {
7333     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7334     // Fill 32-byte chunks
7335     subl(count, 8 << shift);
7336     jcc(Assembler::less, L_check_fill_8_bytes);
7337     align(16);
7338 
7339     BIND(L_fill_32_bytes_loop);
7340 
7341     for (int i = 0; i < 32; i += 4) {
7342       movl(Address(to, i), value);
7343     }
7344 
7345     addptr(to, 32);
7346     subl(count, 8 << shift);
7347     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7348     BIND(L_check_fill_8_bytes);
7349     addl(count, 8 << shift);
7350     jccb(Assembler::zero, L_exit);
7351     jmpb(L_fill_8_bytes);
7352 
7353     //
7354     // length is too short, just fill qwords
7355     //
7356     BIND(L_fill_8_bytes_loop);
7357     movl(Address(to, 0), value);
7358     movl(Address(to, 4), value);
7359     addptr(to, 8);
7360     BIND(L_fill_8_bytes);
7361     subl(count, 1 << (shift + 1));
7362     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7363     // fall through to fill 4 bytes
7364   } else {
7365     Label L_fill_32_bytes;
7366     if (!UseUnalignedLoadStores) {
7367       // align to 8 bytes, we know we are 4 byte aligned to start
7368       testptr(to, 4);
7369       jccb(Assembler::zero, L_fill_32_bytes);
7370       movl(Address(to, 0), value);
7371       addptr(to, 4);
7372       subl(count, 1<<shift);
7373     }
7374     BIND(L_fill_32_bytes);
7375     {
7376       assert( UseSSE >= 2, "supported cpu only" );
7377       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7378       movdl(xtmp, value);
7379       if (UseAVX > 2 && UseUnalignedLoadStores) {
7380         // Fill 64-byte chunks
7381         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7382         vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7383 
7384         subl(count, 16 << shift);
7385         jcc(Assembler::less, L_check_fill_32_bytes);
7386         align(16);
7387 
7388         BIND(L_fill_64_bytes_loop);
7389         evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7390         addptr(to, 64);
7391         subl(count, 16 << shift);
7392         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7393 
7394         BIND(L_check_fill_32_bytes);
7395         addl(count, 8 << shift);
7396         jccb(Assembler::less, L_check_fill_8_bytes);
7397         vmovdqu(Address(to, 0), xtmp);
7398         addptr(to, 32);
7399         subl(count, 8 << shift);
7400 
7401         BIND(L_check_fill_8_bytes);
7402       } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7403         // Fill 64-byte chunks
7404         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7405         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7406 
7407         subl(count, 16 << shift);
7408         jcc(Assembler::less, L_check_fill_32_bytes);
7409         align(16);
7410 
7411         BIND(L_fill_64_bytes_loop);
7412         vmovdqu(Address(to, 0), xtmp);
7413         vmovdqu(Address(to, 32), xtmp);
7414         addptr(to, 64);
7415         subl(count, 16 << shift);
7416         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7417 
7418         BIND(L_check_fill_32_bytes);
7419         addl(count, 8 << shift);
7420         jccb(Assembler::less, L_check_fill_8_bytes);
7421         vmovdqu(Address(to, 0), xtmp);
7422         addptr(to, 32);
7423         subl(count, 8 << shift);
7424 
7425         BIND(L_check_fill_8_bytes);
7426         // clean upper bits of YMM registers
7427         movdl(xtmp, value);
7428         pshufd(xtmp, xtmp, 0);
7429       } else {
7430         // Fill 32-byte chunks
7431         pshufd(xtmp, xtmp, 0);
7432 
7433         subl(count, 8 << shift);
7434         jcc(Assembler::less, L_check_fill_8_bytes);
7435         align(16);
7436 
7437         BIND(L_fill_32_bytes_loop);
7438 
7439         if (UseUnalignedLoadStores) {
7440           movdqu(Address(to, 0), xtmp);
7441           movdqu(Address(to, 16), xtmp);
7442         } else {
7443           movq(Address(to, 0), xtmp);
7444           movq(Address(to, 8), xtmp);
7445           movq(Address(to, 16), xtmp);
7446           movq(Address(to, 24), xtmp);
7447         }
7448 
7449         addptr(to, 32);
7450         subl(count, 8 << shift);
7451         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7452 
7453         BIND(L_check_fill_8_bytes);
7454       }
7455       addl(count, 8 << shift);
7456       jccb(Assembler::zero, L_exit);
7457       jmpb(L_fill_8_bytes);
7458 
7459       //
7460       // length is too short, just fill qwords
7461       //
7462       BIND(L_fill_8_bytes_loop);
7463       movq(Address(to, 0), xtmp);
7464       addptr(to, 8);
7465       BIND(L_fill_8_bytes);
7466       subl(count, 1 << (shift + 1));
7467       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7468     }
7469   }
7470   // fill trailing 4 bytes
7471   BIND(L_fill_4_bytes);
7472   testl(count, 1<<shift);
7473   jccb(Assembler::zero, L_fill_2_bytes);
7474   movl(Address(to, 0), value);
7475   if (t == T_BYTE || t == T_SHORT) {
7476     addptr(to, 4);
7477     BIND(L_fill_2_bytes);
7478     // fill trailing 2 bytes
7479     testl(count, 1<<(shift-1));
7480     jccb(Assembler::zero, L_fill_byte);
7481     movw(Address(to, 0), value);
7482     if (t == T_BYTE) {
7483       addptr(to, 2);
7484       BIND(L_fill_byte);
7485       // fill trailing byte
7486       testl(count, 1);
7487       jccb(Assembler::zero, L_exit);
7488       movb(Address(to, 0), value);
7489     } else {
7490       BIND(L_fill_byte);
7491     }
7492   } else {
7493     BIND(L_fill_2_bytes);
7494   }
7495   BIND(L_exit);
7496 }
7497 
7498 // encode char[] to byte[] in ISO_8859_1
7499    //@HotSpotIntrinsicCandidate
7500    //private static int implEncodeISOArray(byte[] sa, int sp,
7501    //byte[] da, int dp, int len) {
7502    //  int i = 0;
7503    //  for (; i < len; i++) {
7504    //    char c = StringUTF16.getChar(sa, sp++);
7505    //    if (c > '\u00FF')
7506    //      break;
7507    //    da[dp++] = (byte)c;
7508    //  }
7509    //  return i;
7510    //}
7511 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7512   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7513   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7514   Register tmp5, Register result) {
7515 
7516   // rsi: src
7517   // rdi: dst
7518   // rdx: len
7519   // rcx: tmp5
7520   // rax: result
7521   ShortBranchVerifier sbv(this);
7522   assert_different_registers(src, dst, len, tmp5, result);
7523   Label L_done, L_copy_1_char, L_copy_1_char_exit;
7524 
7525   // set result
7526   xorl(result, result);
7527   // check for zero length
7528   testl(len, len);
7529   jcc(Assembler::zero, L_done);
7530 
7531   movl(result, len);
7532 
7533   // Setup pointers
7534   lea(src, Address(src, len, Address::times_2)); // char[]
7535   lea(dst, Address(dst, len, Address::times_1)); // byte[]
7536   negptr(len);
7537 
7538   if (UseSSE42Intrinsics || UseAVX >= 2) {
7539     Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7540     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7541 
7542     if (UseAVX >= 2) {
7543       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7544       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
7545       movdl(tmp1Reg, tmp5);
7546       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7547       jmp(L_chars_32_check);
7548 
7549       bind(L_copy_32_chars);
7550       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7551       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7552       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7553       vptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
7554       jccb(Assembler::notZero, L_copy_32_chars_exit);
7555       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7556       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7557       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7558 
7559       bind(L_chars_32_check);
7560       addptr(len, 32);
7561       jcc(Assembler::lessEqual, L_copy_32_chars);
7562 
7563       bind(L_copy_32_chars_exit);
7564       subptr(len, 16);
7565       jccb(Assembler::greater, L_copy_16_chars_exit);
7566 
7567     } else if (UseSSE42Intrinsics) {
7568       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
7569       movdl(tmp1Reg, tmp5);
7570       pshufd(tmp1Reg, tmp1Reg, 0);
7571       jmpb(L_chars_16_check);
7572     }
7573 
7574     bind(L_copy_16_chars);
7575     if (UseAVX >= 2) {
7576       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7577       vptest(tmp2Reg, tmp1Reg);
7578       jcc(Assembler::notZero, L_copy_16_chars_exit);
7579       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7580       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7581     } else {
7582       if (UseAVX > 0) {
7583         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7584         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7585         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7586       } else {
7587         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7588         por(tmp2Reg, tmp3Reg);
7589         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7590         por(tmp2Reg, tmp4Reg);
7591       }
7592       ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
7593       jccb(Assembler::notZero, L_copy_16_chars_exit);
7594       packuswb(tmp3Reg, tmp4Reg);
7595     }
7596     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7597 
7598     bind(L_chars_16_check);
7599     addptr(len, 16);
7600     jcc(Assembler::lessEqual, L_copy_16_chars);
7601 
7602     bind(L_copy_16_chars_exit);
7603     if (UseAVX >= 2) {
7604       // clean upper bits of YMM registers
7605       vpxor(tmp2Reg, tmp2Reg);
7606       vpxor(tmp3Reg, tmp3Reg);
7607       vpxor(tmp4Reg, tmp4Reg);
7608       movdl(tmp1Reg, tmp5);
7609       pshufd(tmp1Reg, tmp1Reg, 0);
7610     }
7611     subptr(len, 8);
7612     jccb(Assembler::greater, L_copy_8_chars_exit);
7613 
7614     bind(L_copy_8_chars);
7615     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7616     ptest(tmp3Reg, tmp1Reg);
7617     jccb(Assembler::notZero, L_copy_8_chars_exit);
7618     packuswb(tmp3Reg, tmp1Reg);
7619     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7620     addptr(len, 8);
7621     jccb(Assembler::lessEqual, L_copy_8_chars);
7622 
7623     bind(L_copy_8_chars_exit);
7624     subptr(len, 8);
7625     jccb(Assembler::zero, L_done);
7626   }
7627 
7628   bind(L_copy_1_char);
7629   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7630   testl(tmp5, 0xff00);      // check if Unicode char
7631   jccb(Assembler::notZero, L_copy_1_char_exit);
7632   movb(Address(dst, len, Address::times_1, 0), tmp5);
7633   addptr(len, 1);
7634   jccb(Assembler::less, L_copy_1_char);
7635 
7636   bind(L_copy_1_char_exit);
7637   addptr(result, len); // len is negative count of not processed elements
7638 
7639   bind(L_done);
7640 }
7641 
7642 #ifdef _LP64
7643 /**
7644  * Helper for multiply_to_len().
7645  */
7646 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7647   addq(dest_lo, src1);
7648   adcq(dest_hi, 0);
7649   addq(dest_lo, src2);
7650   adcq(dest_hi, 0);
7651 }
7652 
7653 /**
7654  * Multiply 64 bit by 64 bit first loop.
7655  */
7656 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7657                                            Register y, Register y_idx, Register z,
7658                                            Register carry, Register product,
7659                                            Register idx, Register kdx) {
7660   //
7661   //  jlong carry, x[], y[], z[];
7662   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7663   //    huge_128 product = y[idx] * x[xstart] + carry;
7664   //    z[kdx] = (jlong)product;
7665   //    carry  = (jlong)(product >>> 64);
7666   //  }
7667   //  z[xstart] = carry;
7668   //
7669 
7670   Label L_first_loop, L_first_loop_exit;
7671   Label L_one_x, L_one_y, L_multiply;
7672 
7673   decrementl(xstart);
7674   jcc(Assembler::negative, L_one_x);
7675 
7676   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
7677   rorq(x_xstart, 32); // convert big-endian to little-endian
7678 
7679   bind(L_first_loop);
7680   decrementl(idx);
7681   jcc(Assembler::negative, L_first_loop_exit);
7682   decrementl(idx);
7683   jcc(Assembler::negative, L_one_y);
7684   movq(y_idx, Address(y, idx, Address::times_4,  0));
7685   rorq(y_idx, 32); // convert big-endian to little-endian
7686   bind(L_multiply);
7687   movq(product, x_xstart);
7688   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7689   addq(product, carry);
7690   adcq(rdx, 0);
7691   subl(kdx, 2);
7692   movl(Address(z, kdx, Address::times_4,  4), product);
7693   shrq(product, 32);
7694   movl(Address(z, kdx, Address::times_4,  0), product);
7695   movq(carry, rdx);
7696   jmp(L_first_loop);
7697 
7698   bind(L_one_y);
7699   movl(y_idx, Address(y,  0));
7700   jmp(L_multiply);
7701 
7702   bind(L_one_x);
7703   movl(x_xstart, Address(x,  0));
7704   jmp(L_first_loop);
7705 
7706   bind(L_first_loop_exit);
7707 }
7708 
7709 /**
7710  * Multiply 64 bit by 64 bit and add 128 bit.
7711  */
7712 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7713                                             Register yz_idx, Register idx,
7714                                             Register carry, Register product, int offset) {
7715   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7716   //     z[kdx] = (jlong)product;
7717 
7718   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
7719   rorq(yz_idx, 32); // convert big-endian to little-endian
7720   movq(product, x_xstart);
7721   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
7722   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
7723   rorq(yz_idx, 32); // convert big-endian to little-endian
7724 
7725   add2_with_carry(rdx, product, carry, yz_idx);
7726 
7727   movl(Address(z, idx, Address::times_4,  offset+4), product);
7728   shrq(product, 32);
7729   movl(Address(z, idx, Address::times_4,  offset), product);
7730 
7731 }
7732 
7733 /**
7734  * Multiply 128 bit by 128 bit. Unrolled inner loop.
7735  */
7736 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7737                                              Register yz_idx, Register idx, Register jdx,
7738                                              Register carry, Register product,
7739                                              Register carry2) {
7740   //   jlong carry, x[], y[], z[];
7741   //   int kdx = ystart+1;
7742   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7743   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7744   //     z[kdx+idx+1] = (jlong)product;
7745   //     jlong carry2  = (jlong)(product >>> 64);
7746   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7747   //     z[kdx+idx] = (jlong)product;
7748   //     carry  = (jlong)(product >>> 64);
7749   //   }
7750   //   idx += 2;
7751   //   if (idx > 0) {
7752   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7753   //     z[kdx+idx] = (jlong)product;
7754   //     carry  = (jlong)(product >>> 64);
7755   //   }
7756   //
7757 
7758   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7759 
7760   movl(jdx, idx);
7761   andl(jdx, 0xFFFFFFFC);
7762   shrl(jdx, 2);
7763 
7764   bind(L_third_loop);
7765   subl(jdx, 1);
7766   jcc(Assembler::negative, L_third_loop_exit);
7767   subl(idx, 4);
7768 
7769   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7770   movq(carry2, rdx);
7771 
7772   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7773   movq(carry, rdx);
7774   jmp(L_third_loop);
7775 
7776   bind (L_third_loop_exit);
7777 
7778   andl (idx, 0x3);
7779   jcc(Assembler::zero, L_post_third_loop_done);
7780 
7781   Label L_check_1;
7782   subl(idx, 2);
7783   jcc(Assembler::negative, L_check_1);
7784 
7785   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7786   movq(carry, rdx);
7787 
7788   bind (L_check_1);
7789   addl (idx, 0x2);
7790   andl (idx, 0x1);
7791   subl(idx, 1);
7792   jcc(Assembler::negative, L_post_third_loop_done);
7793 
7794   movl(yz_idx, Address(y, idx, Address::times_4,  0));
7795   movq(product, x_xstart);
7796   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7797   movl(yz_idx, Address(z, idx, Address::times_4,  0));
7798 
7799   add2_with_carry(rdx, product, yz_idx, carry);
7800 
7801   movl(Address(z, idx, Address::times_4,  0), product);
7802   shrq(product, 32);
7803 
7804   shlq(rdx, 32);
7805   orq(product, rdx);
7806   movq(carry, product);
7807 
7808   bind(L_post_third_loop_done);
7809 }
7810 
7811 /**
7812  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7813  *
7814  */
7815 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7816                                                   Register carry, Register carry2,
7817                                                   Register idx, Register jdx,
7818                                                   Register yz_idx1, Register yz_idx2,
7819                                                   Register tmp, Register tmp3, Register tmp4) {
7820   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7821 
7822   //   jlong carry, x[], y[], z[];
7823   //   int kdx = ystart+1;
7824   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7825   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7826   //     jlong carry2  = (jlong)(tmp3 >>> 64);
7827   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
7828   //     carry  = (jlong)(tmp4 >>> 64);
7829   //     z[kdx+idx+1] = (jlong)tmp3;
7830   //     z[kdx+idx] = (jlong)tmp4;
7831   //   }
7832   //   idx += 2;
7833   //   if (idx > 0) {
7834   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7835   //     z[kdx+idx] = (jlong)yz_idx1;
7836   //     carry  = (jlong)(yz_idx1 >>> 64);
7837   //   }
7838   //
7839 
7840   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7841 
7842   movl(jdx, idx);
7843   andl(jdx, 0xFFFFFFFC);
7844   shrl(jdx, 2);
7845 
7846   bind(L_third_loop);
7847   subl(jdx, 1);
7848   jcc(Assembler::negative, L_third_loop_exit);
7849   subl(idx, 4);
7850 
7851   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
7852   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7853   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
7854   rorxq(yz_idx2, yz_idx2, 32);
7855 
7856   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
7857   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
7858 
7859   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
7860   rorxq(yz_idx1, yz_idx1, 32);
7861   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
7862   rorxq(yz_idx2, yz_idx2, 32);
7863 
7864   if (VM_Version::supports_adx()) {
7865     adcxq(tmp3, carry);
7866     adoxq(tmp3, yz_idx1);
7867 
7868     adcxq(tmp4, tmp);
7869     adoxq(tmp4, yz_idx2);
7870 
7871     movl(carry, 0); // does not affect flags
7872     adcxq(carry2, carry);
7873     adoxq(carry2, carry);
7874   } else {
7875     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7876     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7877   }
7878   movq(carry, carry2);
7879 
7880   movl(Address(z, idx, Address::times_4, 12), tmp3);
7881   shrq(tmp3, 32);
7882   movl(Address(z, idx, Address::times_4,  8), tmp3);
7883 
7884   movl(Address(z, idx, Address::times_4,  4), tmp4);
7885   shrq(tmp4, 32);
7886   movl(Address(z, idx, Address::times_4,  0), tmp4);
7887 
7888   jmp(L_third_loop);
7889 
7890   bind (L_third_loop_exit);
7891 
7892   andl (idx, 0x3);
7893   jcc(Assembler::zero, L_post_third_loop_done);
7894 
7895   Label L_check_1;
7896   subl(idx, 2);
7897   jcc(Assembler::negative, L_check_1);
7898 
7899   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
7900   rorxq(yz_idx1, yz_idx1, 32);
7901   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
7902   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
7903   rorxq(yz_idx2, yz_idx2, 32);
7904 
7905   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7906 
7907   movl(Address(z, idx, Address::times_4,  4), tmp3);
7908   shrq(tmp3, 32);
7909   movl(Address(z, idx, Address::times_4,  0), tmp3);
7910   movq(carry, tmp4);
7911 
7912   bind (L_check_1);
7913   addl (idx, 0x2);
7914   andl (idx, 0x1);
7915   subl(idx, 1);
7916   jcc(Assembler::negative, L_post_third_loop_done);
7917   movl(tmp4, Address(y, idx, Address::times_4,  0));
7918   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
7919   movl(tmp4, Address(z, idx, Address::times_4,  0));
7920 
7921   add2_with_carry(carry2, tmp3, tmp4, carry);
7922 
7923   movl(Address(z, idx, Address::times_4,  0), tmp3);
7924   shrq(tmp3, 32);
7925 
7926   shlq(carry2, 32);
7927   orq(tmp3, carry2);
7928   movq(carry, tmp3);
7929 
7930   bind(L_post_third_loop_done);
7931 }
7932 
7933 /**
7934  * Code for BigInteger::multiplyToLen() instrinsic.
7935  *
7936  * rdi: x
7937  * rax: xlen
7938  * rsi: y
7939  * rcx: ylen
7940  * r8:  z
7941  * r11: zlen
7942  * r12: tmp1
7943  * r13: tmp2
7944  * r14: tmp3
7945  * r15: tmp4
7946  * rbx: tmp5
7947  *
7948  */
7949 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7950                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7951   ShortBranchVerifier sbv(this);
7952   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7953 
7954   push(tmp1);
7955   push(tmp2);
7956   push(tmp3);
7957   push(tmp4);
7958   push(tmp5);
7959 
7960   push(xlen);
7961   push(zlen);
7962 
7963   const Register idx = tmp1;
7964   const Register kdx = tmp2;
7965   const Register xstart = tmp3;
7966 
7967   const Register y_idx = tmp4;
7968   const Register carry = tmp5;
7969   const Register product  = xlen;
7970   const Register x_xstart = zlen;  // reuse register
7971 
7972   // First Loop.
7973   //
7974   //  final static long LONG_MASK = 0xffffffffL;
7975   //  int xstart = xlen - 1;
7976   //  int ystart = ylen - 1;
7977   //  long carry = 0;
7978   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7979   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7980   //    z[kdx] = (int)product;
7981   //    carry = product >>> 32;
7982   //  }
7983   //  z[xstart] = (int)carry;
7984   //
7985 
7986   movl(idx, ylen);      // idx = ylen;
7987   movl(kdx, zlen);      // kdx = xlen+ylen;
7988   xorq(carry, carry);   // carry = 0;
7989 
7990   Label L_done;
7991 
7992   movl(xstart, xlen);
7993   decrementl(xstart);
7994   jcc(Assembler::negative, L_done);
7995 
7996   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7997 
7998   Label L_second_loop;
7999   testl(kdx, kdx);
8000   jcc(Assembler::zero, L_second_loop);
8001 
8002   Label L_carry;
8003   subl(kdx, 1);
8004   jcc(Assembler::zero, L_carry);
8005 
8006   movl(Address(z, kdx, Address::times_4,  0), carry);
8007   shrq(carry, 32);
8008   subl(kdx, 1);
8009 
8010   bind(L_carry);
8011   movl(Address(z, kdx, Address::times_4,  0), carry);
8012 
8013   // Second and third (nested) loops.
8014   //
8015   // for (int i = xstart-1; i >= 0; i--) { // Second loop
8016   //   carry = 0;
8017   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8018   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8019   //                    (z[k] & LONG_MASK) + carry;
8020   //     z[k] = (int)product;
8021   //     carry = product >>> 32;
8022   //   }
8023   //   z[i] = (int)carry;
8024   // }
8025   //
8026   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8027 
8028   const Register jdx = tmp1;
8029 
8030   bind(L_second_loop);
8031   xorl(carry, carry);    // carry = 0;
8032   movl(jdx, ylen);       // j = ystart+1
8033 
8034   subl(xstart, 1);       // i = xstart-1;
8035   jcc(Assembler::negative, L_done);
8036 
8037   push (z);
8038 
8039   Label L_last_x;
8040   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8041   subl(xstart, 1);       // i = xstart-1;
8042   jcc(Assembler::negative, L_last_x);
8043 
8044   if (UseBMI2Instructions) {
8045     movq(rdx,  Address(x, xstart, Address::times_4,  0));
8046     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8047   } else {
8048     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
8049     rorq(x_xstart, 32);  // convert big-endian to little-endian
8050   }
8051 
8052   Label L_third_loop_prologue;
8053   bind(L_third_loop_prologue);
8054 
8055   push (x);
8056   push (xstart);
8057   push (ylen);
8058 
8059 
8060   if (UseBMI2Instructions) {
8061     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8062   } else { // !UseBMI2Instructions
8063     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8064   }
8065 
8066   pop(ylen);
8067   pop(xlen);
8068   pop(x);
8069   pop(z);
8070 
8071   movl(tmp3, xlen);
8072   addl(tmp3, 1);
8073   movl(Address(z, tmp3, Address::times_4,  0), carry);
8074   subl(tmp3, 1);
8075   jccb(Assembler::negative, L_done);
8076 
8077   shrq(carry, 32);
8078   movl(Address(z, tmp3, Address::times_4,  0), carry);
8079   jmp(L_second_loop);
8080 
8081   // Next infrequent code is moved outside loops.
8082   bind(L_last_x);
8083   if (UseBMI2Instructions) {
8084     movl(rdx, Address(x,  0));
8085   } else {
8086     movl(x_xstart, Address(x,  0));
8087   }
8088   jmp(L_third_loop_prologue);
8089 
8090   bind(L_done);
8091 
8092   pop(zlen);
8093   pop(xlen);
8094 
8095   pop(tmp5);
8096   pop(tmp4);
8097   pop(tmp3);
8098   pop(tmp2);
8099   pop(tmp1);
8100 }
8101 
8102 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8103   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8104   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8105   Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8106   Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8107   Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
8108   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8109   Label SAME_TILL_END, DONE;
8110   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8111 
8112   //scale is in rcx in both Win64 and Unix
8113   ShortBranchVerifier sbv(this);
8114 
8115   shlq(length);
8116   xorq(result, result);
8117 
8118   if ((UseAVX > 2) &&
8119       VM_Version::supports_avx512vlbw()) {
8120     cmpq(length, 64);
8121     jcc(Assembler::less, VECTOR32_TAIL);
8122     movq(tmp1, length);
8123     andq(tmp1, 0x3F);      // tail count
8124     andq(length, ~(0x3F)); //vector count
8125 
8126     bind(VECTOR64_LOOP);
8127     // AVX512 code to compare 64 byte vectors.
8128     evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
8129     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
8130     kortestql(k7, k7);
8131     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
8132     addq(result, 64);
8133     subq(length, 64);
8134     jccb(Assembler::notZero, VECTOR64_LOOP);
8135 
8136     //bind(VECTOR64_TAIL);
8137     testq(tmp1, tmp1);
8138     jcc(Assembler::zero, SAME_TILL_END);
8139 
8140     bind(VECTOR64_TAIL);
8141     // AVX512 code to compare upto 63 byte vectors.
8142     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
8143     shlxq(tmp2, tmp2, tmp1);
8144     notq(tmp2);
8145     kmovql(k3, tmp2);
8146 
8147     evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
8148     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
8149 
8150     ktestql(k7, k3);
8151     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
8152 
8153     bind(VECTOR64_NOT_EQUAL);
8154     kmovql(tmp1, k7);
8155     notq(tmp1);
8156     tzcntq(tmp1, tmp1);
8157     addq(result, tmp1);
8158     shrq(result);
8159     jmp(DONE);
8160     bind(VECTOR32_TAIL);
8161   }
8162 
8163   cmpq(length, 8);
8164   jcc(Assembler::equal, VECTOR8_LOOP);
8165   jcc(Assembler::less, VECTOR4_TAIL);
8166 
8167   if (UseAVX >= 2) {
8168 
8169     cmpq(length, 16);
8170     jcc(Assembler::equal, VECTOR16_LOOP);
8171     jcc(Assembler::less, VECTOR8_LOOP);
8172 
8173     cmpq(length, 32);
8174     jccb(Assembler::less, VECTOR16_TAIL);
8175 
8176     subq(length, 32);
8177     bind(VECTOR32_LOOP);
8178     vmovdqu(rymm0, Address(obja, result));
8179     vmovdqu(rymm1, Address(objb, result));
8180     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8181     vptest(rymm2, rymm2);
8182     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8183     addq(result, 32);
8184     subq(length, 32);
8185     jccb(Assembler::greaterEqual, VECTOR32_LOOP);
8186     addq(length, 32);
8187     jcc(Assembler::equal, SAME_TILL_END);
8188     //falling through if less than 32 bytes left //close the branch here.
8189 
8190     bind(VECTOR16_TAIL);
8191     cmpq(length, 16);
8192     jccb(Assembler::less, VECTOR8_TAIL);
8193     bind(VECTOR16_LOOP);
8194     movdqu(rymm0, Address(obja, result));
8195     movdqu(rymm1, Address(objb, result));
8196     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8197     ptest(rymm2, rymm2);
8198     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8199     addq(result, 16);
8200     subq(length, 16);
8201     jcc(Assembler::equal, SAME_TILL_END);
8202     //falling through if less than 16 bytes left
8203   } else {//regular intrinsics
8204 
8205     cmpq(length, 16);
8206     jccb(Assembler::less, VECTOR8_TAIL);
8207 
8208     subq(length, 16);
8209     bind(VECTOR16_LOOP);
8210     movdqu(rymm0, Address(obja, result));
8211     movdqu(rymm1, Address(objb, result));
8212     pxor(rymm0, rymm1);
8213     ptest(rymm0, rymm0);
8214     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8215     addq(result, 16);
8216     subq(length, 16);
8217     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8218     addq(length, 16);
8219     jcc(Assembler::equal, SAME_TILL_END);
8220     //falling through if less than 16 bytes left
8221   }
8222 
8223   bind(VECTOR8_TAIL);
8224   cmpq(length, 8);
8225   jccb(Assembler::less, VECTOR4_TAIL);
8226   bind(VECTOR8_LOOP);
8227   movq(tmp1, Address(obja, result));
8228   movq(tmp2, Address(objb, result));
8229   xorq(tmp1, tmp2);
8230   testq(tmp1, tmp1);
8231   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8232   addq(result, 8);
8233   subq(length, 8);
8234   jcc(Assembler::equal, SAME_TILL_END);
8235   //falling through if less than 8 bytes left
8236 
8237   bind(VECTOR4_TAIL);
8238   cmpq(length, 4);
8239   jccb(Assembler::less, BYTES_TAIL);
8240   bind(VECTOR4_LOOP);
8241   movl(tmp1, Address(obja, result));
8242   xorl(tmp1, Address(objb, result));
8243   testl(tmp1, tmp1);
8244   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8245   addq(result, 4);
8246   subq(length, 4);
8247   jcc(Assembler::equal, SAME_TILL_END);
8248   //falling through if less than 4 bytes left
8249 
8250   bind(BYTES_TAIL);
8251   bind(BYTES_LOOP);
8252   load_unsigned_byte(tmp1, Address(obja, result));
8253   load_unsigned_byte(tmp2, Address(objb, result));
8254   xorl(tmp1, tmp2);
8255   testl(tmp1, tmp1);
8256   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8257   decq(length);
8258   jccb(Assembler::zero, SAME_TILL_END);
8259   incq(result);
8260   load_unsigned_byte(tmp1, Address(obja, result));
8261   load_unsigned_byte(tmp2, Address(objb, result));
8262   xorl(tmp1, tmp2);
8263   testl(tmp1, tmp1);
8264   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8265   decq(length);
8266   jccb(Assembler::zero, SAME_TILL_END);
8267   incq(result);
8268   load_unsigned_byte(tmp1, Address(obja, result));
8269   load_unsigned_byte(tmp2, Address(objb, result));
8270   xorl(tmp1, tmp2);
8271   testl(tmp1, tmp1);
8272   jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8273   jmpb(SAME_TILL_END);
8274 
8275   if (UseAVX >= 2) {
8276     bind(VECTOR32_NOT_EQUAL);
8277     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8278     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8279     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8280     vpmovmskb(tmp1, rymm0);
8281     bsfq(tmp1, tmp1);
8282     addq(result, tmp1);
8283     shrq(result);
8284     jmpb(DONE);
8285   }
8286 
8287   bind(VECTOR16_NOT_EQUAL);
8288   if (UseAVX >= 2) {
8289     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8290     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8291     pxor(rymm0, rymm2);
8292   } else {
8293     pcmpeqb(rymm2, rymm2);
8294     pxor(rymm0, rymm1);
8295     pcmpeqb(rymm0, rymm1);
8296     pxor(rymm0, rymm2);
8297   }
8298   pmovmskb(tmp1, rymm0);
8299   bsfq(tmp1, tmp1);
8300   addq(result, tmp1);
8301   shrq(result);
8302   jmpb(DONE);
8303 
8304   bind(VECTOR8_NOT_EQUAL);
8305   bind(VECTOR4_NOT_EQUAL);
8306   bsfq(tmp1, tmp1);
8307   shrq(tmp1, 3);
8308   addq(result, tmp1);
8309   bind(BYTES_NOT_EQUAL);
8310   shrq(result);
8311   jmpb(DONE);
8312 
8313   bind(SAME_TILL_END);
8314   mov64(result, -1);
8315 
8316   bind(DONE);
8317 }
8318 
8319 //Helper functions for square_to_len()
8320 
8321 /**
8322  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8323  * Preserves x and z and modifies rest of the registers.
8324  */
8325 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8326   // Perform square and right shift by 1
8327   // Handle odd xlen case first, then for even xlen do the following
8328   // jlong carry = 0;
8329   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8330   //     huge_128 product = x[j:j+1] * x[j:j+1];
8331   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8332   //     z[i+2:i+3] = (jlong)(product >>> 1);
8333   //     carry = (jlong)product;
8334   // }
8335 
8336   xorq(tmp5, tmp5);     // carry
8337   xorq(rdxReg, rdxReg);
8338   xorl(tmp1, tmp1);     // index for x
8339   xorl(tmp4, tmp4);     // index for z
8340 
8341   Label L_first_loop, L_first_loop_exit;
8342 
8343   testl(xlen, 1);
8344   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8345 
8346   // Square and right shift by 1 the odd element using 32 bit multiply
8347   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8348   imulq(raxReg, raxReg);
8349   shrq(raxReg, 1);
8350   adcq(tmp5, 0);
8351   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8352   incrementl(tmp1);
8353   addl(tmp4, 2);
8354 
8355   // Square and  right shift by 1 the rest using 64 bit multiply
8356   bind(L_first_loop);
8357   cmpptr(tmp1, xlen);
8358   jccb(Assembler::equal, L_first_loop_exit);
8359 
8360   // Square
8361   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
8362   rorq(raxReg, 32);    // convert big-endian to little-endian
8363   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
8364 
8365   // Right shift by 1 and save carry
8366   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8367   rcrq(rdxReg, 1);
8368   rcrq(raxReg, 1);
8369   adcq(tmp5, 0);
8370 
8371   // Store result in z
8372   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8373   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8374 
8375   // Update indices for x and z
8376   addl(tmp1, 2);
8377   addl(tmp4, 4);
8378   jmp(L_first_loop);
8379 
8380   bind(L_first_loop_exit);
8381 }
8382 
8383 
8384 /**
8385  * Perform the following multiply add operation using BMI2 instructions
8386  * carry:sum = sum + op1*op2 + carry
8387  * op2 should be in rdx
8388  * op2 is preserved, all other registers are modified
8389  */
8390 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8391   // assert op2 is rdx
8392   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
8393   addq(sum, carry);
8394   adcq(tmp2, 0);
8395   addq(sum, op1);
8396   adcq(tmp2, 0);
8397   movq(carry, tmp2);
8398 }
8399 
8400 /**
8401  * Perform the following multiply add operation:
8402  * carry:sum = sum + op1*op2 + carry
8403  * Preserves op1, op2 and modifies rest of registers
8404  */
8405 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8406   // rdx:rax = op1 * op2
8407   movq(raxReg, op2);
8408   mulq(op1);
8409 
8410   //  rdx:rax = sum + carry + rdx:rax
8411   addq(sum, carry);
8412   adcq(rdxReg, 0);
8413   addq(sum, raxReg);
8414   adcq(rdxReg, 0);
8415 
8416   // carry:sum = rdx:sum
8417   movq(carry, rdxReg);
8418 }
8419 
8420 /**
8421  * Add 64 bit long carry into z[] with carry propogation.
8422  * Preserves z and carry register values and modifies rest of registers.
8423  *
8424  */
8425 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8426   Label L_fourth_loop, L_fourth_loop_exit;
8427 
8428   movl(tmp1, 1);
8429   subl(zlen, 2);
8430   addq(Address(z, zlen, Address::times_4, 0), carry);
8431 
8432   bind(L_fourth_loop);
8433   jccb(Assembler::carryClear, L_fourth_loop_exit);
8434   subl(zlen, 2);
8435   jccb(Assembler::negative, L_fourth_loop_exit);
8436   addq(Address(z, zlen, Address::times_4, 0), tmp1);
8437   jmp(L_fourth_loop);
8438   bind(L_fourth_loop_exit);
8439 }
8440 
8441 /**
8442  * Shift z[] left by 1 bit.
8443  * Preserves x, len, z and zlen registers and modifies rest of the registers.
8444  *
8445  */
8446 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8447 
8448   Label L_fifth_loop, L_fifth_loop_exit;
8449 
8450   // Fifth loop
8451   // Perform primitiveLeftShift(z, zlen, 1)
8452 
8453   const Register prev_carry = tmp1;
8454   const Register new_carry = tmp4;
8455   const Register value = tmp2;
8456   const Register zidx = tmp3;
8457 
8458   // int zidx, carry;
8459   // long value;
8460   // carry = 0;
8461   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8462   //    (carry:value)  = (z[i] << 1) | carry ;
8463   //    z[i] = value;
8464   // }
8465 
8466   movl(zidx, zlen);
8467   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8468 
8469   bind(L_fifth_loop);
8470   decl(zidx);  // Use decl to preserve carry flag
8471   decl(zidx);
8472   jccb(Assembler::negative, L_fifth_loop_exit);
8473 
8474   if (UseBMI2Instructions) {
8475      movq(value, Address(z, zidx, Address::times_4, 0));
8476      rclq(value, 1);
8477      rorxq(value, value, 32);
8478      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
8479   }
8480   else {
8481     // clear new_carry
8482     xorl(new_carry, new_carry);
8483 
8484     // Shift z[i] by 1, or in previous carry and save new carry
8485     movq(value, Address(z, zidx, Address::times_4, 0));
8486     shlq(value, 1);
8487     adcl(new_carry, 0);
8488 
8489     orq(value, prev_carry);
8490     rorq(value, 0x20);
8491     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
8492 
8493     // Set previous carry = new carry
8494     movl(prev_carry, new_carry);
8495   }
8496   jmp(L_fifth_loop);
8497 
8498   bind(L_fifth_loop_exit);
8499 }
8500 
8501 
8502 /**
8503  * Code for BigInteger::squareToLen() intrinsic
8504  *
8505  * rdi: x
8506  * rsi: len
8507  * r8:  z
8508  * rcx: zlen
8509  * r12: tmp1
8510  * r13: tmp2
8511  * r14: tmp3
8512  * r15: tmp4
8513  * rbx: tmp5
8514  *
8515  */
8516 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8517 
8518   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
8519   push(tmp1);
8520   push(tmp2);
8521   push(tmp3);
8522   push(tmp4);
8523   push(tmp5);
8524 
8525   // First loop
8526   // Store the squares, right shifted one bit (i.e., divided by 2).
8527   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8528 
8529   // Add in off-diagonal sums.
8530   //
8531   // Second, third (nested) and fourth loops.
8532   // zlen +=2;
8533   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8534   //    carry = 0;
8535   //    long op2 = x[xidx:xidx+1];
8536   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8537   //       k -= 2;
8538   //       long op1 = x[j:j+1];
8539   //       long sum = z[k:k+1];
8540   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8541   //       z[k:k+1] = sum;
8542   //    }
8543   //    add_one_64(z, k, carry, tmp_regs);
8544   // }
8545 
8546   const Register carry = tmp5;
8547   const Register sum = tmp3;
8548   const Register op1 = tmp4;
8549   Register op2 = tmp2;
8550 
8551   push(zlen);
8552   push(len);
8553   addl(zlen,2);
8554   bind(L_second_loop);
8555   xorq(carry, carry);
8556   subl(zlen, 4);
8557   subl(len, 2);
8558   push(zlen);
8559   push(len);
8560   cmpl(len, 0);
8561   jccb(Assembler::lessEqual, L_second_loop_exit);
8562 
8563   // Multiply an array by one 64 bit long.
8564   if (UseBMI2Instructions) {
8565     op2 = rdxReg;
8566     movq(op2, Address(x, len, Address::times_4,  0));
8567     rorxq(op2, op2, 32);
8568   }
8569   else {
8570     movq(op2, Address(x, len, Address::times_4,  0));
8571     rorq(op2, 32);
8572   }
8573 
8574   bind(L_third_loop);
8575   decrementl(len);
8576   jccb(Assembler::negative, L_third_loop_exit);
8577   decrementl(len);
8578   jccb(Assembler::negative, L_last_x);
8579 
8580   movq(op1, Address(x, len, Address::times_4,  0));
8581   rorq(op1, 32);
8582 
8583   bind(L_multiply);
8584   subl(zlen, 2);
8585   movq(sum, Address(z, zlen, Address::times_4,  0));
8586 
8587   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8588   if (UseBMI2Instructions) {
8589     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8590   }
8591   else {
8592     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8593   }
8594 
8595   movq(Address(z, zlen, Address::times_4, 0), sum);
8596 
8597   jmp(L_third_loop);
8598   bind(L_third_loop_exit);
8599 
8600   // Fourth loop
8601   // Add 64 bit long carry into z with carry propogation.
8602   // Uses offsetted zlen.
8603   add_one_64(z, zlen, carry, tmp1);
8604 
8605   pop(len);
8606   pop(zlen);
8607   jmp(L_second_loop);
8608 
8609   // Next infrequent code is moved outside loops.
8610   bind(L_last_x);
8611   movl(op1, Address(x, 0));
8612   jmp(L_multiply);
8613 
8614   bind(L_second_loop_exit);
8615   pop(len);
8616   pop(zlen);
8617   pop(len);
8618   pop(zlen);
8619 
8620   // Fifth loop
8621   // Shift z left 1 bit.
8622   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8623 
8624   // z[zlen-1] |= x[len-1] & 1;
8625   movl(tmp3, Address(x, len, Address::times_4, -4));
8626   andl(tmp3, 1);
8627   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
8628 
8629   pop(tmp5);
8630   pop(tmp4);
8631   pop(tmp3);
8632   pop(tmp2);
8633   pop(tmp1);
8634 }
8635 
8636 /**
8637  * Helper function for mul_add()
8638  * Multiply the in[] by int k and add to out[] starting at offset offs using
8639  * 128 bit by 32 bit multiply and return the carry in tmp5.
8640  * Only quad int aligned length of in[] is operated on in this function.
8641  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8642  * This function preserves out, in and k registers.
8643  * len and offset point to the appropriate index in "in" & "out" correspondingly
8644  * tmp5 has the carry.
8645  * other registers are temporary and are modified.
8646  *
8647  */
8648 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8649   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8650   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8651 
8652   Label L_first_loop, L_first_loop_exit;
8653 
8654   movl(tmp1, len);
8655   shrl(tmp1, 2);
8656 
8657   bind(L_first_loop);
8658   subl(tmp1, 1);
8659   jccb(Assembler::negative, L_first_loop_exit);
8660 
8661   subl(len, 4);
8662   subl(offset, 4);
8663 
8664   Register op2 = tmp2;
8665   const Register sum = tmp3;
8666   const Register op1 = tmp4;
8667   const Register carry = tmp5;
8668 
8669   if (UseBMI2Instructions) {
8670     op2 = rdxReg;
8671   }
8672 
8673   movq(op1, Address(in, len, Address::times_4,  8));
8674   rorq(op1, 32);
8675   movq(sum, Address(out, offset, Address::times_4,  8));
8676   rorq(sum, 32);
8677   if (UseBMI2Instructions) {
8678     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8679   }
8680   else {
8681     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8682   }
8683   // Store back in big endian from little endian
8684   rorq(sum, 0x20);
8685   movq(Address(out, offset, Address::times_4,  8), sum);
8686 
8687   movq(op1, Address(in, len, Address::times_4,  0));
8688   rorq(op1, 32);
8689   movq(sum, Address(out, offset, Address::times_4,  0));
8690   rorq(sum, 32);
8691   if (UseBMI2Instructions) {
8692     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8693   }
8694   else {
8695     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8696   }
8697   // Store back in big endian from little endian
8698   rorq(sum, 0x20);
8699   movq(Address(out, offset, Address::times_4,  0), sum);
8700 
8701   jmp(L_first_loop);
8702   bind(L_first_loop_exit);
8703 }
8704 
8705 /**
8706  * Code for BigInteger::mulAdd() intrinsic
8707  *
8708  * rdi: out
8709  * rsi: in
8710  * r11: offs (out.length - offset)
8711  * rcx: len
8712  * r8:  k
8713  * r12: tmp1
8714  * r13: tmp2
8715  * r14: tmp3
8716  * r15: tmp4
8717  * rbx: tmp5
8718  * Multiply the in[] by word k and add to out[], return the carry in rax
8719  */
8720 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8721    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8722    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8723 
8724   Label L_carry, L_last_in, L_done;
8725 
8726 // carry = 0;
8727 // for (int j=len-1; j >= 0; j--) {
8728 //    long product = (in[j] & LONG_MASK) * kLong +
8729 //                   (out[offs] & LONG_MASK) + carry;
8730 //    out[offs--] = (int)product;
8731 //    carry = product >>> 32;
8732 // }
8733 //
8734   push(tmp1);
8735   push(tmp2);
8736   push(tmp3);
8737   push(tmp4);
8738   push(tmp5);
8739 
8740   Register op2 = tmp2;
8741   const Register sum = tmp3;
8742   const Register op1 = tmp4;
8743   const Register carry =  tmp5;
8744 
8745   if (UseBMI2Instructions) {
8746     op2 = rdxReg;
8747     movl(op2, k);
8748   }
8749   else {
8750     movl(op2, k);
8751   }
8752 
8753   xorq(carry, carry);
8754 
8755   //First loop
8756 
8757   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8758   //The carry is in tmp5
8759   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8760 
8761   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8762   decrementl(len);
8763   jccb(Assembler::negative, L_carry);
8764   decrementl(len);
8765   jccb(Assembler::negative, L_last_in);
8766 
8767   movq(op1, Address(in, len, Address::times_4,  0));
8768   rorq(op1, 32);
8769 
8770   subl(offs, 2);
8771   movq(sum, Address(out, offs, Address::times_4,  0));
8772   rorq(sum, 32);
8773 
8774   if (UseBMI2Instructions) {
8775     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8776   }
8777   else {
8778     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8779   }
8780 
8781   // Store back in big endian from little endian
8782   rorq(sum, 0x20);
8783   movq(Address(out, offs, Address::times_4,  0), sum);
8784 
8785   testl(len, len);
8786   jccb(Assembler::zero, L_carry);
8787 
8788   //Multiply the last in[] entry, if any
8789   bind(L_last_in);
8790   movl(op1, Address(in, 0));
8791   movl(sum, Address(out, offs, Address::times_4,  -4));
8792 
8793   movl(raxReg, k);
8794   mull(op1); //tmp4 * eax -> edx:eax
8795   addl(sum, carry);
8796   adcl(rdxReg, 0);
8797   addl(sum, raxReg);
8798   adcl(rdxReg, 0);
8799   movl(carry, rdxReg);
8800 
8801   movl(Address(out, offs, Address::times_4,  -4), sum);
8802 
8803   bind(L_carry);
8804   //return tmp5/carry as carry in rax
8805   movl(rax, carry);
8806 
8807   bind(L_done);
8808   pop(tmp5);
8809   pop(tmp4);
8810   pop(tmp3);
8811   pop(tmp2);
8812   pop(tmp1);
8813 }
8814 #endif
8815 
8816 /**
8817  * Emits code to update CRC-32 with a byte value according to constants in table
8818  *
8819  * @param [in,out]crc   Register containing the crc.
8820  * @param [in]val       Register containing the byte to fold into the CRC.
8821  * @param [in]table     Register containing the table of crc constants.
8822  *
8823  * uint32_t crc;
8824  * val = crc_table[(val ^ crc) & 0xFF];
8825  * crc = val ^ (crc >> 8);
8826  *
8827  */
8828 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8829   xorl(val, crc);
8830   andl(val, 0xFF);
8831   shrl(crc, 8); // unsigned shift
8832   xorl(crc, Address(table, val, Address::times_4, 0));
8833 }
8834 
8835 /**
8836 * Fold four 128-bit data chunks
8837 */
8838 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8839   evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8840   evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8841   evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8842   evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8843 }
8844 
8845 /**
8846  * Fold 128-bit data chunk
8847  */
8848 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8849   if (UseAVX > 0) {
8850     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8851     vpclmulldq(xcrc, xK, xcrc); // [63:0]
8852     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8853     pxor(xcrc, xtmp);
8854   } else {
8855     movdqa(xtmp, xcrc);
8856     pclmulhdq(xtmp, xK);   // [123:64]
8857     pclmulldq(xcrc, xK);   // [63:0]
8858     pxor(xcrc, xtmp);
8859     movdqu(xtmp, Address(buf, offset));
8860     pxor(xcrc, xtmp);
8861   }
8862 }
8863 
8864 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8865   if (UseAVX > 0) {
8866     vpclmulhdq(xtmp, xK, xcrc);
8867     vpclmulldq(xcrc, xK, xcrc);
8868     pxor(xcrc, xbuf);
8869     pxor(xcrc, xtmp);
8870   } else {
8871     movdqa(xtmp, xcrc);
8872     pclmulhdq(xtmp, xK);
8873     pclmulldq(xcrc, xK);
8874     pxor(xcrc, xbuf);
8875     pxor(xcrc, xtmp);
8876   }
8877 }
8878 
8879 /**
8880  * 8-bit folds to compute 32-bit CRC
8881  *
8882  * uint64_t xcrc;
8883  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8884  */
8885 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8886   movdl(tmp, xcrc);
8887   andl(tmp, 0xFF);
8888   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8889   psrldq(xcrc, 1); // unsigned shift one byte
8890   pxor(xcrc, xtmp);
8891 }
8892 
8893 /**
8894  * uint32_t crc;
8895  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8896  */
8897 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8898   movl(tmp, crc);
8899   andl(tmp, 0xFF);
8900   shrl(crc, 8);
8901   xorl(crc, Address(table, tmp, Address::times_4, 0));
8902 }
8903 
8904 /**
8905  * @param crc   register containing existing CRC (32-bit)
8906  * @param buf   register pointing to input byte buffer (byte*)
8907  * @param len   register containing number of bytes
8908  * @param table register that will contain address of CRC table
8909  * @param tmp   scratch register
8910  */
8911 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8912   assert_different_registers(crc, buf, len, table, tmp, rax);
8913 
8914   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8915   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8916 
8917   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8918   // context for the registers used, where all instructions below are using 128-bit mode
8919   // On EVEX without VL and BW, these instructions will all be AVX.
8920   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8921   notl(crc); // ~crc
8922   cmpl(len, 16);
8923   jcc(Assembler::less, L_tail);
8924 
8925   // Align buffer to 16 bytes
8926   movl(tmp, buf);
8927   andl(tmp, 0xF);
8928   jccb(Assembler::zero, L_aligned);
8929   subl(tmp,  16);
8930   addl(len, tmp);
8931 
8932   align(4);
8933   BIND(L_align_loop);
8934   movsbl(rax, Address(buf, 0)); // load byte with sign extension
8935   update_byte_crc32(crc, rax, table);
8936   increment(buf);
8937   incrementl(tmp);
8938   jccb(Assembler::less, L_align_loop);
8939 
8940   BIND(L_aligned);
8941   movl(tmp, len); // save
8942   shrl(len, 4);
8943   jcc(Assembler::zero, L_tail_restore);
8944 
8945   // Fold total 512 bits of polynomial on each iteration
8946   if (VM_Version::supports_vpclmulqdq()) {
8947     Label Parallel_loop, L_No_Parallel;
8948 
8949     cmpl(len, 8);
8950     jccb(Assembler::less, L_No_Parallel);
8951 
8952     movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8953     evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
8954     movdl(xmm5, crc);
8955     evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
8956     addptr(buf, 64);
8957     subl(len, 7);
8958     evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
8959 
8960     BIND(Parallel_loop);
8961     fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
8962     addptr(buf, 64);
8963     subl(len, 4);
8964     jcc(Assembler::greater, Parallel_loop);
8965 
8966     vextracti64x2(xmm2, xmm1, 0x01);
8967     vextracti64x2(xmm3, xmm1, 0x02);
8968     vextracti64x2(xmm4, xmm1, 0x03);
8969     jmp(L_fold_512b);
8970 
8971     BIND(L_No_Parallel);
8972   }
8973   // Fold crc into first bytes of vector
8974   movdqa(xmm1, Address(buf, 0));
8975   movdl(rax, xmm1);
8976   xorl(crc, rax);
8977   if (VM_Version::supports_sse4_1()) {
8978     pinsrd(xmm1, crc, 0);
8979   } else {
8980     pinsrw(xmm1, crc, 0);
8981     shrl(crc, 16);
8982     pinsrw(xmm1, crc, 1);
8983   }
8984   addptr(buf, 16);
8985   subl(len, 4); // len > 0
8986   jcc(Assembler::less, L_fold_tail);
8987 
8988   movdqa(xmm2, Address(buf,  0));
8989   movdqa(xmm3, Address(buf, 16));
8990   movdqa(xmm4, Address(buf, 32));
8991   addptr(buf, 48);
8992   subl(len, 3);
8993   jcc(Assembler::lessEqual, L_fold_512b);
8994 
8995   // Fold total 512 bits of polynomial on each iteration,
8996   // 128 bits per each of 4 parallel streams.
8997   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8998 
8999   align(32);
9000   BIND(L_fold_512b_loop);
9001   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
9002   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
9003   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
9004   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
9005   addptr(buf, 64);
9006   subl(len, 4);
9007   jcc(Assembler::greater, L_fold_512b_loop);
9008 
9009   // Fold 512 bits to 128 bits.
9010   BIND(L_fold_512b);
9011   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9012   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
9013   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
9014   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
9015 
9016   // Fold the rest of 128 bits data chunks
9017   BIND(L_fold_tail);
9018   addl(len, 3);
9019   jccb(Assembler::lessEqual, L_fold_128b);
9020   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
9021 
9022   BIND(L_fold_tail_loop);
9023   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
9024   addptr(buf, 16);
9025   decrementl(len);
9026   jccb(Assembler::greater, L_fold_tail_loop);
9027 
9028   // Fold 128 bits in xmm1 down into 32 bits in crc register.
9029   BIND(L_fold_128b);
9030   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9031   if (UseAVX > 0) {
9032     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9033     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9034     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9035   } else {
9036     movdqa(xmm2, xmm0);
9037     pclmulqdq(xmm2, xmm1, 0x1);
9038     movdqa(xmm3, xmm0);
9039     pand(xmm3, xmm2);
9040     pclmulqdq(xmm0, xmm3, 0x1);
9041   }
9042   psrldq(xmm1, 8);
9043   psrldq(xmm2, 4);
9044   pxor(xmm0, xmm1);
9045   pxor(xmm0, xmm2);
9046 
9047   // 8 8-bit folds to compute 32-bit CRC.
9048   for (int j = 0; j < 4; j++) {
9049     fold_8bit_crc32(xmm0, table, xmm1, rax);
9050   }
9051   movdl(crc, xmm0); // mov 32 bits to general register
9052   for (int j = 0; j < 4; j++) {
9053     fold_8bit_crc32(crc, table, rax);
9054   }
9055 
9056   BIND(L_tail_restore);
9057   movl(len, tmp); // restore
9058   BIND(L_tail);
9059   andl(len, 0xf);
9060   jccb(Assembler::zero, L_exit);
9061 
9062   // Fold the rest of bytes
9063   align(4);
9064   BIND(L_tail_loop);
9065   movsbl(rax, Address(buf, 0)); // load byte with sign extension
9066   update_byte_crc32(crc, rax, table);
9067   increment(buf);
9068   decrementl(len);
9069   jccb(Assembler::greater, L_tail_loop);
9070 
9071   BIND(L_exit);
9072   notl(crc); // ~c
9073 }
9074 
9075 #ifdef _LP64
9076 // S. Gueron / Information Processing Letters 112 (2012) 184
9077 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9078 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9079 // Output: the 64-bit carry-less product of B * CONST
9080 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9081                                      Register tmp1, Register tmp2, Register tmp3) {
9082   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9083   if (n > 0) {
9084     addq(tmp3, n * 256 * 8);
9085   }
9086   //    Q1 = TABLEExt[n][B & 0xFF];
9087   movl(tmp1, in);
9088   andl(tmp1, 0x000000FF);
9089   shll(tmp1, 3);
9090   addq(tmp1, tmp3);
9091   movq(tmp1, Address(tmp1, 0));
9092 
9093   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
9094   movl(tmp2, in);
9095   shrl(tmp2, 8);
9096   andl(tmp2, 0x000000FF);
9097   shll(tmp2, 3);
9098   addq(tmp2, tmp3);
9099   movq(tmp2, Address(tmp2, 0));
9100 
9101   shlq(tmp2, 8);
9102   xorq(tmp1, tmp2);
9103 
9104   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
9105   movl(tmp2, in);
9106   shrl(tmp2, 16);
9107   andl(tmp2, 0x000000FF);
9108   shll(tmp2, 3);
9109   addq(tmp2, tmp3);
9110   movq(tmp2, Address(tmp2, 0));
9111 
9112   shlq(tmp2, 16);
9113   xorq(tmp1, tmp2);
9114 
9115   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
9116   shrl(in, 24);
9117   andl(in, 0x000000FF);
9118   shll(in, 3);
9119   addq(in, tmp3);
9120   movq(in, Address(in, 0));
9121 
9122   shlq(in, 24);
9123   xorq(in, tmp1);
9124   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9125 }
9126 
9127 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9128                                       Register in_out,
9129                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9130                                       XMMRegister w_xtmp2,
9131                                       Register tmp1,
9132                                       Register n_tmp2, Register n_tmp3) {
9133   if (is_pclmulqdq_supported) {
9134     movdl(w_xtmp1, in_out); // modified blindly
9135 
9136     movl(tmp1, const_or_pre_comp_const_index);
9137     movdl(w_xtmp2, tmp1);
9138     pclmulqdq(w_xtmp1, w_xtmp2, 0);
9139 
9140     movdq(in_out, w_xtmp1);
9141   } else {
9142     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9143   }
9144 }
9145 
9146 // Recombination Alternative 2: No bit-reflections
9147 // T1 = (CRC_A * U1) << 1
9148 // T2 = (CRC_B * U2) << 1
9149 // C1 = T1 >> 32
9150 // C2 = T2 >> 32
9151 // T1 = T1 & 0xFFFFFFFF
9152 // T2 = T2 & 0xFFFFFFFF
9153 // T1 = CRC32(0, T1)
9154 // T2 = CRC32(0, T2)
9155 // C1 = C1 ^ T1
9156 // C2 = C2 ^ T2
9157 // CRC = C1 ^ C2 ^ CRC_C
9158 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9159                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9160                                      Register tmp1, Register tmp2,
9161                                      Register n_tmp3) {
9162   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9163   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9164   shlq(in_out, 1);
9165   movl(tmp1, in_out);
9166   shrq(in_out, 32);
9167   xorl(tmp2, tmp2);
9168   crc32(tmp2, tmp1, 4);
9169   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9170   shlq(in1, 1);
9171   movl(tmp1, in1);
9172   shrq(in1, 32);
9173   xorl(tmp2, tmp2);
9174   crc32(tmp2, tmp1, 4);
9175   xorl(in1, tmp2);
9176   xorl(in_out, in1);
9177   xorl(in_out, in2);
9178 }
9179 
9180 // Set N to predefined value
9181 // Subtract from a lenght of a buffer
9182 // execute in a loop:
9183 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9184 // for i = 1 to N do
9185 //  CRC_A = CRC32(CRC_A, A[i])
9186 //  CRC_B = CRC32(CRC_B, B[i])
9187 //  CRC_C = CRC32(CRC_C, C[i])
9188 // end for
9189 // Recombine
9190 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9191                                        Register in_out1, Register in_out2, Register in_out3,
9192                                        Register tmp1, Register tmp2, Register tmp3,
9193                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9194                                        Register tmp4, Register tmp5,
9195                                        Register n_tmp6) {
9196   Label L_processPartitions;
9197   Label L_processPartition;
9198   Label L_exit;
9199 
9200   bind(L_processPartitions);
9201   cmpl(in_out1, 3 * size);
9202   jcc(Assembler::less, L_exit);
9203     xorl(tmp1, tmp1);
9204     xorl(tmp2, tmp2);
9205     movq(tmp3, in_out2);
9206     addq(tmp3, size);
9207 
9208     bind(L_processPartition);
9209       crc32(in_out3, Address(in_out2, 0), 8);
9210       crc32(tmp1, Address(in_out2, size), 8);
9211       crc32(tmp2, Address(in_out2, size * 2), 8);
9212       addq(in_out2, 8);
9213       cmpq(in_out2, tmp3);
9214       jcc(Assembler::less, L_processPartition);
9215     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9216             w_xtmp1, w_xtmp2, w_xtmp3,
9217             tmp4, tmp5,
9218             n_tmp6);
9219     addq(in_out2, 2 * size);
9220     subl(in_out1, 3 * size);
9221     jmp(L_processPartitions);
9222 
9223   bind(L_exit);
9224 }
9225 #else
9226 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9227                                      Register tmp1, Register tmp2, Register tmp3,
9228                                      XMMRegister xtmp1, XMMRegister xtmp2) {
9229   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9230   if (n > 0) {
9231     addl(tmp3, n * 256 * 8);
9232   }
9233   //    Q1 = TABLEExt[n][B & 0xFF];
9234   movl(tmp1, in_out);
9235   andl(tmp1, 0x000000FF);
9236   shll(tmp1, 3);
9237   addl(tmp1, tmp3);
9238   movq(xtmp1, Address(tmp1, 0));
9239 
9240   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
9241   movl(tmp2, in_out);
9242   shrl(tmp2, 8);
9243   andl(tmp2, 0x000000FF);
9244   shll(tmp2, 3);
9245   addl(tmp2, tmp3);
9246   movq(xtmp2, Address(tmp2, 0));
9247 
9248   psllq(xtmp2, 8);
9249   pxor(xtmp1, xtmp2);
9250 
9251   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
9252   movl(tmp2, in_out);
9253   shrl(tmp2, 16);
9254   andl(tmp2, 0x000000FF);
9255   shll(tmp2, 3);
9256   addl(tmp2, tmp3);
9257   movq(xtmp2, Address(tmp2, 0));
9258 
9259   psllq(xtmp2, 16);
9260   pxor(xtmp1, xtmp2);
9261 
9262   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
9263   shrl(in_out, 24);
9264   andl(in_out, 0x000000FF);
9265   shll(in_out, 3);
9266   addl(in_out, tmp3);
9267   movq(xtmp2, Address(in_out, 0));
9268 
9269   psllq(xtmp2, 24);
9270   pxor(xtmp1, xtmp2); // Result in CXMM
9271   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9272 }
9273 
9274 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9275                                       Register in_out,
9276                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9277                                       XMMRegister w_xtmp2,
9278                                       Register tmp1,
9279                                       Register n_tmp2, Register n_tmp3) {
9280   if (is_pclmulqdq_supported) {
9281     movdl(w_xtmp1, in_out);
9282 
9283     movl(tmp1, const_or_pre_comp_const_index);
9284     movdl(w_xtmp2, tmp1);
9285     pclmulqdq(w_xtmp1, w_xtmp2, 0);
9286     // Keep result in XMM since GPR is 32 bit in length
9287   } else {
9288     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9289   }
9290 }
9291 
9292 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9293                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9294                                      Register tmp1, Register tmp2,
9295                                      Register n_tmp3) {
9296   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9297   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9298 
9299   psllq(w_xtmp1, 1);
9300   movdl(tmp1, w_xtmp1);
9301   psrlq(w_xtmp1, 32);
9302   movdl(in_out, w_xtmp1);
9303 
9304   xorl(tmp2, tmp2);
9305   crc32(tmp2, tmp1, 4);
9306   xorl(in_out, tmp2);
9307 
9308   psllq(w_xtmp2, 1);
9309   movdl(tmp1, w_xtmp2);
9310   psrlq(w_xtmp2, 32);
9311   movdl(in1, w_xtmp2);
9312 
9313   xorl(tmp2, tmp2);
9314   crc32(tmp2, tmp1, 4);
9315   xorl(in1, tmp2);
9316   xorl(in_out, in1);
9317   xorl(in_out, in2);
9318 }
9319 
9320 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9321                                        Register in_out1, Register in_out2, Register in_out3,
9322                                        Register tmp1, Register tmp2, Register tmp3,
9323                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9324                                        Register tmp4, Register tmp5,
9325                                        Register n_tmp6) {
9326   Label L_processPartitions;
9327   Label L_processPartition;
9328   Label L_exit;
9329 
9330   bind(L_processPartitions);
9331   cmpl(in_out1, 3 * size);
9332   jcc(Assembler::less, L_exit);
9333     xorl(tmp1, tmp1);
9334     xorl(tmp2, tmp2);
9335     movl(tmp3, in_out2);
9336     addl(tmp3, size);
9337 
9338     bind(L_processPartition);
9339       crc32(in_out3, Address(in_out2, 0), 4);
9340       crc32(tmp1, Address(in_out2, size), 4);
9341       crc32(tmp2, Address(in_out2, size*2), 4);
9342       crc32(in_out3, Address(in_out2, 0+4), 4);
9343       crc32(tmp1, Address(in_out2, size+4), 4);
9344       crc32(tmp2, Address(in_out2, size*2+4), 4);
9345       addl(in_out2, 8);
9346       cmpl(in_out2, tmp3);
9347       jcc(Assembler::less, L_processPartition);
9348 
9349         push(tmp3);
9350         push(in_out1);
9351         push(in_out2);
9352         tmp4 = tmp3;
9353         tmp5 = in_out1;
9354         n_tmp6 = in_out2;
9355 
9356       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9357             w_xtmp1, w_xtmp2, w_xtmp3,
9358             tmp4, tmp5,
9359             n_tmp6);
9360 
9361         pop(in_out2);
9362         pop(in_out1);
9363         pop(tmp3);
9364 
9365     addl(in_out2, 2 * size);
9366     subl(in_out1, 3 * size);
9367     jmp(L_processPartitions);
9368 
9369   bind(L_exit);
9370 }
9371 #endif //LP64
9372 
9373 #ifdef _LP64
9374 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9375 // Input: A buffer I of L bytes.
9376 // Output: the CRC32C value of the buffer.
9377 // Notations:
9378 // Write L = 24N + r, with N = floor (L/24).
9379 // r = L mod 24 (0 <= r < 24).
9380 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9381 // N quadwords, and R consists of r bytes.
9382 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9383 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9384 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9385 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9386 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9387                                           Register tmp1, Register tmp2, Register tmp3,
9388                                           Register tmp4, Register tmp5, Register tmp6,
9389                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9390                                           bool is_pclmulqdq_supported) {
9391   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9392   Label L_wordByWord;
9393   Label L_byteByByteProlog;
9394   Label L_byteByByte;
9395   Label L_exit;
9396 
9397   if (is_pclmulqdq_supported ) {
9398     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9399     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9400 
9401     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9402     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9403 
9404     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9405     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9406     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9407   } else {
9408     const_or_pre_comp_const_index[0] = 1;
9409     const_or_pre_comp_const_index[1] = 0;
9410 
9411     const_or_pre_comp_const_index[2] = 3;
9412     const_or_pre_comp_const_index[3] = 2;
9413 
9414     const_or_pre_comp_const_index[4] = 5;
9415     const_or_pre_comp_const_index[5] = 4;
9416    }
9417   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9418                     in2, in1, in_out,
9419                     tmp1, tmp2, tmp3,
9420                     w_xtmp1, w_xtmp2, w_xtmp3,
9421                     tmp4, tmp5,
9422                     tmp6);
9423   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9424                     in2, in1, in_out,
9425                     tmp1, tmp2, tmp3,
9426                     w_xtmp1, w_xtmp2, w_xtmp3,
9427                     tmp4, tmp5,
9428                     tmp6);
9429   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9430                     in2, in1, in_out,
9431                     tmp1, tmp2, tmp3,
9432                     w_xtmp1, w_xtmp2, w_xtmp3,
9433                     tmp4, tmp5,
9434                     tmp6);
9435   movl(tmp1, in2);
9436   andl(tmp1, 0x00000007);
9437   negl(tmp1);
9438   addl(tmp1, in2);
9439   addq(tmp1, in1);
9440 
9441   BIND(L_wordByWord);
9442   cmpq(in1, tmp1);
9443   jcc(Assembler::greaterEqual, L_byteByByteProlog);
9444     crc32(in_out, Address(in1, 0), 4);
9445     addq(in1, 4);
9446     jmp(L_wordByWord);
9447 
9448   BIND(L_byteByByteProlog);
9449   andl(in2, 0x00000007);
9450   movl(tmp2, 1);
9451 
9452   BIND(L_byteByByte);
9453   cmpl(tmp2, in2);
9454   jccb(Assembler::greater, L_exit);
9455     crc32(in_out, Address(in1, 0), 1);
9456     incq(in1);
9457     incl(tmp2);
9458     jmp(L_byteByByte);
9459 
9460   BIND(L_exit);
9461 }
9462 #else
9463 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9464                                           Register tmp1, Register  tmp2, Register tmp3,
9465                                           Register tmp4, Register  tmp5, Register tmp6,
9466                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9467                                           bool is_pclmulqdq_supported) {
9468   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9469   Label L_wordByWord;
9470   Label L_byteByByteProlog;
9471   Label L_byteByByte;
9472   Label L_exit;
9473 
9474   if (is_pclmulqdq_supported) {
9475     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9476     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9477 
9478     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9479     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9480 
9481     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9482     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9483   } else {
9484     const_or_pre_comp_const_index[0] = 1;
9485     const_or_pre_comp_const_index[1] = 0;
9486 
9487     const_or_pre_comp_const_index[2] = 3;
9488     const_or_pre_comp_const_index[3] = 2;
9489 
9490     const_or_pre_comp_const_index[4] = 5;
9491     const_or_pre_comp_const_index[5] = 4;
9492   }
9493   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9494                     in2, in1, in_out,
9495                     tmp1, tmp2, tmp3,
9496                     w_xtmp1, w_xtmp2, w_xtmp3,
9497                     tmp4, tmp5,
9498                     tmp6);
9499   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9500                     in2, in1, in_out,
9501                     tmp1, tmp2, tmp3,
9502                     w_xtmp1, w_xtmp2, w_xtmp3,
9503                     tmp4, tmp5,
9504                     tmp6);
9505   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9506                     in2, in1, in_out,
9507                     tmp1, tmp2, tmp3,
9508                     w_xtmp1, w_xtmp2, w_xtmp3,
9509                     tmp4, tmp5,
9510                     tmp6);
9511   movl(tmp1, in2);
9512   andl(tmp1, 0x00000007);
9513   negl(tmp1);
9514   addl(tmp1, in2);
9515   addl(tmp1, in1);
9516 
9517   BIND(L_wordByWord);
9518   cmpl(in1, tmp1);
9519   jcc(Assembler::greaterEqual, L_byteByByteProlog);
9520     crc32(in_out, Address(in1,0), 4);
9521     addl(in1, 4);
9522     jmp(L_wordByWord);
9523 
9524   BIND(L_byteByByteProlog);
9525   andl(in2, 0x00000007);
9526   movl(tmp2, 1);
9527 
9528   BIND(L_byteByByte);
9529   cmpl(tmp2, in2);
9530   jccb(Assembler::greater, L_exit);
9531     movb(tmp1, Address(in1, 0));
9532     crc32(in_out, tmp1, 1);
9533     incl(in1);
9534     incl(tmp2);
9535     jmp(L_byteByByte);
9536 
9537   BIND(L_exit);
9538 }
9539 #endif // LP64
9540 #undef BIND
9541 #undef BLOCK_COMMENT
9542 
9543 // Compress char[] array to byte[].
9544 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9545 //   @HotSpotIntrinsicCandidate
9546 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9547 //     for (int i = 0; i < len; i++) {
9548 //       int c = src[srcOff++];
9549 //       if (c >>> 8 != 0) {
9550 //         return 0;
9551 //       }
9552 //       dst[dstOff++] = (byte)c;
9553 //     }
9554 //     return len;
9555 //   }
9556 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9557   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9558   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9559   Register tmp5, Register result) {
9560   Label copy_chars_loop, return_length, return_zero, done;
9561 
9562   // rsi: src
9563   // rdi: dst
9564   // rdx: len
9565   // rcx: tmp5
9566   // rax: result
9567 
9568   // rsi holds start addr of source char[] to be compressed
9569   // rdi holds start addr of destination byte[]
9570   // rdx holds length
9571 
9572   assert(len != result, "");
9573 
9574   // save length for return
9575   push(len);
9576 
9577   if ((UseAVX > 2) && // AVX512
9578     VM_Version::supports_avx512vlbw() &&
9579     VM_Version::supports_bmi2()) {
9580 
9581     Label copy_32_loop, copy_loop_tail, below_threshold;
9582 
9583     // alignment
9584     Label post_alignment;
9585 
9586     // if length of the string is less than 16, handle it in an old fashioned way
9587     testl(len, -32);
9588     jcc(Assembler::zero, below_threshold);
9589 
9590     // First check whether a character is compressable ( <= 0xFF).
9591     // Create mask to test for Unicode chars inside zmm vector
9592     movl(result, 0x00FF);
9593     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9594 
9595     testl(len, -64);
9596     jcc(Assembler::zero, post_alignment);
9597 
9598     movl(tmp5, dst);
9599     andl(tmp5, (32 - 1));
9600     negl(tmp5);
9601     andl(tmp5, (32 - 1));
9602 
9603     // bail out when there is nothing to be done
9604     testl(tmp5, 0xFFFFFFFF);
9605     jcc(Assembler::zero, post_alignment);
9606 
9607     // ~(~0 << len), where len is the # of remaining elements to process
9608     movl(result, 0xFFFFFFFF);
9609     shlxl(result, result, tmp5);
9610     notl(result);
9611     kmovdl(k3, result);
9612 
9613     evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9614     evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9615     ktestd(k2, k3);
9616     jcc(Assembler::carryClear, return_zero);
9617 
9618     evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9619 
9620     addptr(src, tmp5);
9621     addptr(src, tmp5);
9622     addptr(dst, tmp5);
9623     subl(len, tmp5);
9624 
9625     bind(post_alignment);
9626     // end of alignment
9627 
9628     movl(tmp5, len);
9629     andl(tmp5, (32 - 1));    // tail count (in chars)
9630     andl(len, ~(32 - 1));    // vector count (in chars)
9631     jcc(Assembler::zero, copy_loop_tail);
9632 
9633     lea(src, Address(src, len, Address::times_2));
9634     lea(dst, Address(dst, len, Address::times_1));
9635     negptr(len);
9636 
9637     bind(copy_32_loop);
9638     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9639     evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9640     kortestdl(k2, k2);
9641     jcc(Assembler::carryClear, return_zero);
9642 
9643     // All elements in current processed chunk are valid candidates for
9644     // compression. Write a truncated byte elements to the memory.
9645     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9646     addptr(len, 32);
9647     jcc(Assembler::notZero, copy_32_loop);
9648 
9649     bind(copy_loop_tail);
9650     // bail out when there is nothing to be done
9651     testl(tmp5, 0xFFFFFFFF);
9652     jcc(Assembler::zero, return_length);
9653 
9654     movl(len, tmp5);
9655 
9656     // ~(~0 << len), where len is the # of remaining elements to process
9657     movl(result, 0xFFFFFFFF);
9658     shlxl(result, result, len);
9659     notl(result);
9660 
9661     kmovdl(k3, result);
9662 
9663     evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9664     evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9665     ktestd(k2, k3);
9666     jcc(Assembler::carryClear, return_zero);
9667 
9668     evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9669     jmp(return_length);
9670 
9671     bind(below_threshold);
9672   }
9673 
9674   if (UseSSE42Intrinsics) {
9675     Label copy_32_loop, copy_16, copy_tail;
9676 
9677     movl(result, len);
9678 
9679     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
9680 
9681     // vectored compression
9682     andl(len, 0xfffffff0);    // vector count (in chars)
9683     andl(result, 0x0000000f);    // tail count (in chars)
9684     testl(len, len);
9685     jccb(Assembler::zero, copy_16);
9686 
9687     // compress 16 chars per iter
9688     movdl(tmp1Reg, tmp5);
9689     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
9690     pxor(tmp4Reg, tmp4Reg);
9691 
9692     lea(src, Address(src, len, Address::times_2));
9693     lea(dst, Address(dst, len, Address::times_1));
9694     negptr(len);
9695 
9696     bind(copy_32_loop);
9697     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
9698     por(tmp4Reg, tmp2Reg);
9699     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9700     por(tmp4Reg, tmp3Reg);
9701     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
9702     jcc(Assembler::notZero, return_zero);
9703     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
9704     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9705     addptr(len, 16);
9706     jcc(Assembler::notZero, copy_32_loop);
9707 
9708     // compress next vector of 8 chars (if any)
9709     bind(copy_16);
9710     movl(len, result);
9711     andl(len, 0xfffffff8);    // vector count (in chars)
9712     andl(result, 0x00000007);    // tail count (in chars)
9713     testl(len, len);
9714     jccb(Assembler::zero, copy_tail);
9715 
9716     movdl(tmp1Reg, tmp5);
9717     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
9718     pxor(tmp3Reg, tmp3Reg);
9719 
9720     movdqu(tmp2Reg, Address(src, 0));
9721     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
9722     jccb(Assembler::notZero, return_zero);
9723     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
9724     movq(Address(dst, 0), tmp2Reg);
9725     addptr(src, 16);
9726     addptr(dst, 8);
9727 
9728     bind(copy_tail);
9729     movl(len, result);
9730   }
9731   // compress 1 char per iter
9732   testl(len, len);
9733   jccb(Assembler::zero, return_length);
9734   lea(src, Address(src, len, Address::times_2));
9735   lea(dst, Address(dst, len, Address::times_1));
9736   negptr(len);
9737 
9738   bind(copy_chars_loop);
9739   load_unsigned_short(result, Address(src, len, Address::times_2));
9740   testl(result, 0xff00);      // check if Unicode char
9741   jccb(Assembler::notZero, return_zero);
9742   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
9743   increment(len);
9744   jcc(Assembler::notZero, copy_chars_loop);
9745 
9746   // if compression succeeded, return length
9747   bind(return_length);
9748   pop(result);
9749   jmpb(done);
9750 
9751   // if compression failed, return 0
9752   bind(return_zero);
9753   xorl(result, result);
9754   addptr(rsp, wordSize);
9755 
9756   bind(done);
9757 }
9758 
9759 // Inflate byte[] array to char[].
9760 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9761 //   @HotSpotIntrinsicCandidate
9762 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9763 //     for (int i = 0; i < len; i++) {
9764 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9765 //     }
9766 //   }
9767 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9768   XMMRegister tmp1, Register tmp2) {
9769   Label copy_chars_loop, done, below_threshold;
9770   // rsi: src
9771   // rdi: dst
9772   // rdx: len
9773   // rcx: tmp2
9774 
9775   // rsi holds start addr of source byte[] to be inflated
9776   // rdi holds start addr of destination char[]
9777   // rdx holds length
9778   assert_different_registers(src, dst, len, tmp2);
9779 
9780   if ((UseAVX > 2) && // AVX512
9781     VM_Version::supports_avx512vlbw() &&
9782     VM_Version::supports_bmi2()) {
9783 
9784     Label copy_32_loop, copy_tail;
9785     Register tmp3_aliased = len;
9786 
9787     // if length of the string is less than 16, handle it in an old fashioned way
9788     testl(len, -16);
9789     jcc(Assembler::zero, below_threshold);
9790 
9791     // In order to use only one arithmetic operation for the main loop we use
9792     // this pre-calculation
9793     movl(tmp2, len);
9794     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9795     andl(len, -32);     // vector count
9796     jccb(Assembler::zero, copy_tail);
9797 
9798     lea(src, Address(src, len, Address::times_1));
9799     lea(dst, Address(dst, len, Address::times_2));
9800     negptr(len);
9801 
9802 
9803     // inflate 32 chars per iter
9804     bind(copy_32_loop);
9805     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9806     evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9807     addptr(len, 32);
9808     jcc(Assembler::notZero, copy_32_loop);
9809 
9810     bind(copy_tail);
9811     // bail out when there is nothing to be done
9812     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9813     jcc(Assembler::zero, done);
9814 
9815     // ~(~0 << length), where length is the # of remaining elements to process
9816     movl(tmp3_aliased, -1);
9817     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9818     notl(tmp3_aliased);
9819     kmovdl(k2, tmp3_aliased);
9820     evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9821     evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9822 
9823     jmp(done);
9824   }
9825   if (UseSSE42Intrinsics) {
9826     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9827 
9828     movl(tmp2, len);
9829 
9830     if (UseAVX > 1) {
9831       andl(tmp2, (16 - 1));
9832       andl(len, -16);
9833       jccb(Assembler::zero, copy_new_tail);
9834     } else {
9835       andl(tmp2, 0x00000007);   // tail count (in chars)
9836       andl(len, 0xfffffff8);    // vector count (in chars)
9837       jccb(Assembler::zero, copy_tail);
9838     }
9839 
9840     // vectored inflation
9841     lea(src, Address(src, len, Address::times_1));
9842     lea(dst, Address(dst, len, Address::times_2));
9843     negptr(len);
9844 
9845     if (UseAVX > 1) {
9846       bind(copy_16_loop);
9847       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9848       vmovdqu(Address(dst, len, Address::times_2), tmp1);
9849       addptr(len, 16);
9850       jcc(Assembler::notZero, copy_16_loop);
9851 
9852       bind(below_threshold);
9853       bind(copy_new_tail);
9854       if ((UseAVX > 2) &&
9855         VM_Version::supports_avx512vlbw() &&
9856         VM_Version::supports_bmi2()) {
9857         movl(tmp2, len);
9858       } else {
9859         movl(len, tmp2);
9860       }
9861       andl(tmp2, 0x00000007);
9862       andl(len, 0xFFFFFFF8);
9863       jccb(Assembler::zero, copy_tail);
9864 
9865       pmovzxbw(tmp1, Address(src, 0));
9866       movdqu(Address(dst, 0), tmp1);
9867       addptr(src, 8);
9868       addptr(dst, 2 * 8);
9869 
9870       jmp(copy_tail, true);
9871     }
9872 
9873     // inflate 8 chars per iter
9874     bind(copy_8_loop);
9875     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
9876     movdqu(Address(dst, len, Address::times_2), tmp1);
9877     addptr(len, 8);
9878     jcc(Assembler::notZero, copy_8_loop);
9879 
9880     bind(copy_tail);
9881     movl(len, tmp2);
9882 
9883     cmpl(len, 4);
9884     jccb(Assembler::less, copy_bytes);
9885 
9886     movdl(tmp1, Address(src, 0));  // load 4 byte chars
9887     pmovzxbw(tmp1, tmp1);
9888     movq(Address(dst, 0), tmp1);
9889     subptr(len, 4);
9890     addptr(src, 4);
9891     addptr(dst, 8);
9892 
9893     bind(copy_bytes);
9894   } else {
9895     bind(below_threshold);
9896   }
9897 
9898   testl(len, len);
9899   jccb(Assembler::zero, done);
9900   lea(src, Address(src, len, Address::times_1));
9901   lea(dst, Address(dst, len, Address::times_2));
9902   negptr(len);
9903 
9904   // inflate 1 char per iter
9905   bind(copy_chars_loop);
9906   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
9907   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
9908   increment(len);
9909   jcc(Assembler::notZero, copy_chars_loop);
9910 
9911   bind(done);
9912 }
9913 
9914 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9915   switch (cond) {
9916     // Note some conditions are synonyms for others
9917     case Assembler::zero:         return Assembler::notZero;
9918     case Assembler::notZero:      return Assembler::zero;
9919     case Assembler::less:         return Assembler::greaterEqual;
9920     case Assembler::lessEqual:    return Assembler::greater;
9921     case Assembler::greater:      return Assembler::lessEqual;
9922     case Assembler::greaterEqual: return Assembler::less;
9923     case Assembler::below:        return Assembler::aboveEqual;
9924     case Assembler::belowEqual:   return Assembler::above;
9925     case Assembler::above:        return Assembler::belowEqual;
9926     case Assembler::aboveEqual:   return Assembler::below;
9927     case Assembler::overflow:     return Assembler::noOverflow;
9928     case Assembler::noOverflow:   return Assembler::overflow;
9929     case Assembler::negative:     return Assembler::positive;
9930     case Assembler::positive:     return Assembler::negative;
9931     case Assembler::parity:       return Assembler::noParity;
9932     case Assembler::noParity:     return Assembler::parity;
9933   }
9934   ShouldNotReachHere(); return Assembler::overflow;
9935 }
9936 
9937 SkipIfEqual::SkipIfEqual(
9938     MacroAssembler* masm, const bool* flag_addr, bool value) {
9939   _masm = masm;
9940   _masm->cmp8(ExternalAddress((address)flag_addr), value);
9941   _masm->jcc(Assembler::equal, _label);
9942 }
9943 
9944 SkipIfEqual::~SkipIfEqual() {
9945   _masm->bind(_label);
9946 }
9947 
9948 // 32-bit Windows has its own fast-path implementation
9949 // of get_thread
9950 #if !defined(WIN32) || defined(_LP64)
9951 
9952 // This is simply a call to Thread::current()
9953 void MacroAssembler::get_thread(Register thread) {
9954   if (thread != rax) {
9955     push(rax);
9956   }
9957   LP64_ONLY(push(rdi);)
9958   LP64_ONLY(push(rsi);)
9959   push(rdx);
9960   push(rcx);
9961 #ifdef _LP64
9962   push(r8);
9963   push(r9);
9964   push(r10);
9965   push(r11);
9966 #endif
9967 
9968   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9969 
9970 #ifdef _LP64
9971   pop(r11);
9972   pop(r10);
9973   pop(r9);
9974   pop(r8);
9975 #endif
9976   pop(rcx);
9977   pop(rdx);
9978   LP64_ONLY(pop(rsi);)
9979   LP64_ONLY(pop(rdi);)
9980   if (thread != rax) {
9981     mov(thread, rax);
9982     pop(rax);
9983   }
9984 }
9985 
9986 #endif