1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  public:
  42   // Support for VM calls
  43   //
  44   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  45   // may customize this version by overriding it for its purposes (e.g., to save/restore
  46   // additional registers when doing a VM call).
  47 
  48   virtual void call_VM_leaf_base(
  49     address entry_point,               // the entry point
  50     int     number_of_arguments        // the number of arguments to pop after the call
  51   );
  52 
  53  protected:
  54   // This is the base routine called by the different versions of call_VM. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   //
  58   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  59   // returns the register which contains the thread upon return. If a thread register has been
  60   // specified, the return value will correspond to that register. If no last_java_sp is specified
  61   // (noreg) than rsp will be used instead.
  62   virtual void call_VM_base(           // returns the register containing the thread upon return
  63     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  64     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  65     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  66     address  entry_point,              // the entry point
  67     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  68     bool     check_exceptions          // whether to check for pending exceptions after return
  69   );
  70 
  71   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  72 
  73   // helpers for FPU flag access
  74   // tmp is a temporary register, if none is available use noreg
  75   void save_rax   (Register tmp);
  76   void restore_rax(Register tmp);
  77 
  78  public:
  79   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  80 
  81  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82  // The implementation is only non-empty for the InterpreterMacroAssembler,
  83  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84  virtual void check_and_handle_popframe(Register java_thread);
  85  virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   Address as_Address(AddressLiteral adr);
  88   Address as_Address(ArrayAddress adr);
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99 
 100   // Required platform-specific helpers for Label::patch_instructions.
 101   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 102   void pd_patch_instruction(address branch, address target) {
 103     unsigned char op = branch[0];
 104     assert(op == 0xE8 /* call */ ||
 105         op == 0xE9 /* jmp */ ||
 106         op == 0xEB /* short jmp */ ||
 107         (op & 0xF0) == 0x70 /* short jcc */ ||
 108         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 109         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 110         "Invalid opcode at patch point");
 111 
 112     if (op == 0xEB || (op & 0xF0) == 0x70) {
 113       // short offset operators (jmp and jcc)
 114       char* disp = (char*) &branch[1];
 115       int imm8 = target - (address) &disp[1];
 116       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
 117       *disp = imm8;
 118     } else {
 119       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 120       int imm32 = target - (address) &disp[1];
 121       *disp = imm32;
 122     }
 123   }
 124 
 125   // The following 4 methods return the offset of the appropriate move instruction
 126 
 127   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 128   int load_unsigned_byte(Register dst, Address src);
 129   int load_unsigned_short(Register dst, Address src);
 130 
 131   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 132   int load_signed_byte(Register dst, Address src);
 133   int load_signed_short(Register dst, Address src);
 134 
 135   // Support for sign-extension (hi:lo = extend_sign(lo))
 136   void extend_sign(Register hi, Register lo);
 137 
 138   // Load and store values by size and signed-ness
 139   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 140   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 141 
 142   // Support for inc/dec with optimal instruction selection depending on value
 143 
 144   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 145   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 146 
 147   void decrementl(Address dst, int value = 1);
 148   void decrementl(Register reg, int value = 1);
 149 
 150   void decrementq(Register reg, int value = 1);
 151   void decrementq(Address dst, int value = 1);
 152 
 153   void incrementl(Address dst, int value = 1);
 154   void incrementl(Register reg, int value = 1);
 155 
 156   void incrementq(Register reg, int value = 1);
 157   void incrementq(Address dst, int value = 1);
 158 
 159 #ifdef COMPILER2
 160   // special instructions for EVEX
 161   void setvectmask(Register dst, Register src);
 162   void restorevectmask();
 163 #endif
 164 
 165   // Support optimal SSE move instructions.
 166   void movflt(XMMRegister dst, XMMRegister src) {
 167     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 168     else                       { movss (dst, src); return; }
 169   }
 170   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 171   void movflt(XMMRegister dst, AddressLiteral src);
 172   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 173 
 174   void movdbl(XMMRegister dst, XMMRegister src) {
 175     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 176     else                       { movsd (dst, src); return; }
 177   }
 178 
 179   void movdbl(XMMRegister dst, AddressLiteral src);
 180 
 181   void movdbl(XMMRegister dst, Address src) {
 182     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 183     else                         { movlpd(dst, src); return; }
 184   }
 185   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 186 
 187   void incrementl(AddressLiteral dst);
 188   void incrementl(ArrayAddress dst);
 189 
 190   void incrementq(AddressLiteral dst);
 191 
 192   // Alignment
 193   void align(int modulus);
 194   void align(int modulus, int target);
 195 
 196   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 197   void fat_nop();
 198 
 199   // Stack frame creation/removal
 200   void enter();
 201   void leave();
 202 
 203   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 204   // The pointer will be loaded into the thread register.
 205   void get_thread(Register thread);
 206 
 207 
 208   // Support for VM calls
 209   //
 210   // It is imperative that all calls into the VM are handled via the call_VM macros.
 211   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 212   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 213 
 214 
 215   void call_VM(Register oop_result,
 216                address entry_point,
 217                bool check_exceptions = true);
 218   void call_VM(Register oop_result,
 219                address entry_point,
 220                Register arg_1,
 221                bool check_exceptions = true);
 222   void call_VM(Register oop_result,
 223                address entry_point,
 224                Register arg_1, Register arg_2,
 225                bool check_exceptions = true);
 226   void call_VM(Register oop_result,
 227                address entry_point,
 228                Register arg_1, Register arg_2, Register arg_3,
 229                bool check_exceptions = true);
 230 
 231   // Overloadings with last_Java_sp
 232   void call_VM(Register oop_result,
 233                Register last_java_sp,
 234                address entry_point,
 235                int number_of_arguments = 0,
 236                bool check_exceptions = true);
 237   void call_VM(Register oop_result,
 238                Register last_java_sp,
 239                address entry_point,
 240                Register arg_1, bool
 241                check_exceptions = true);
 242   void call_VM(Register oop_result,
 243                Register last_java_sp,
 244                address entry_point,
 245                Register arg_1, Register arg_2,
 246                bool check_exceptions = true);
 247   void call_VM(Register oop_result,
 248                Register last_java_sp,
 249                address entry_point,
 250                Register arg_1, Register arg_2, Register arg_3,
 251                bool check_exceptions = true);
 252 
 253   void get_vm_result  (Register oop_result, Register thread);
 254   void get_vm_result_2(Register metadata_result, Register thread);
 255 
 256   // These always tightly bind to MacroAssembler::call_VM_base
 257   // bypassing the virtual implementation
 258   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 259   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 260   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 261   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 263 
 264   void call_VM_leaf0(address entry_point);
 265   void call_VM_leaf(address entry_point,
 266                     int number_of_arguments = 0);
 267   void call_VM_leaf(address entry_point,
 268                     Register arg_1);
 269   void call_VM_leaf(address entry_point,
 270                     Register arg_1, Register arg_2);
 271   void call_VM_leaf(address entry_point,
 272                     Register arg_1, Register arg_2, Register arg_3);
 273 
 274   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 275   // bypassing the virtual implementation
 276   void super_call_VM_leaf(address entry_point);
 277   void super_call_VM_leaf(address entry_point, Register arg_1);
 278   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 279   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 280   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 281 
 282   // last Java Frame (fills frame anchor)
 283   void set_last_Java_frame(Register thread,
 284                            Register last_java_sp,
 285                            Register last_java_fp,
 286                            address last_java_pc);
 287 
 288   // thread in the default location (r15_thread on 64bit)
 289   void set_last_Java_frame(Register last_java_sp,
 290                            Register last_java_fp,
 291                            address last_java_pc);
 292 
 293   void reset_last_Java_frame(Register thread, bool clear_fp);
 294 
 295   // thread in the default location (r15_thread on 64bit)
 296   void reset_last_Java_frame(bool clear_fp);
 297 
 298   // jobjects
 299   void clear_jweak_tag(Register possibly_jweak);
 300   void resolve_jobject(Register value, Register thread, Register tmp);
 301 
 302   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 303   void c2bool(Register x);
 304 
 305   // C++ bool manipulation
 306 
 307   void movbool(Register dst, Address src);
 308   void movbool(Address dst, bool boolconst);
 309   void movbool(Address dst, Register src);
 310   void testbool(Register dst);
 311 
 312   void resolve_oop_handle(Register result, Register tmp = rscratch2);
 313   void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
 314 
 315   // oop manipulations
 316   void load_klass(Register dst, Register src);
 317   void store_klass(Register dst, Register src);
 318 
 319   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 320                       Register tmp1, Register thread_tmp);
 321   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 322                        Register tmp1, Register tmp2);
 323 
 324   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 325                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 326   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 327                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 328   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 329                       Register tmp2 = noreg, DecoratorSet decorators = 0);
 330 
 331   // Used for storing NULL. All other oop constants should be
 332   // stored using routines that take a jobject.
 333   void store_heap_oop_null(Address dst);
 334 
 335   void load_prototype_header(Register dst, Register src);
 336 
 337 #ifdef _LP64
 338   void store_klass_gap(Register dst, Register src);
 339 
 340   // This dummy is to prevent a call to store_heap_oop from
 341   // converting a zero (like NULL) into a Register by giving
 342   // the compiler two choices it can't resolve
 343 
 344   void store_heap_oop(Address dst, void* dummy);
 345 
 346   void encode_heap_oop(Register r);
 347   void decode_heap_oop(Register r);
 348   void encode_heap_oop_not_null(Register r);
 349   void decode_heap_oop_not_null(Register r);
 350   void encode_heap_oop_not_null(Register dst, Register src);
 351   void decode_heap_oop_not_null(Register dst, Register src);
 352 
 353   void set_narrow_oop(Register dst, jobject obj);
 354   void set_narrow_oop(Address dst, jobject obj);
 355   void cmp_narrow_oop(Register dst, jobject obj);
 356   void cmp_narrow_oop(Address dst, jobject obj);
 357 
 358   void encode_klass_not_null(Register r);
 359   void decode_klass_not_null(Register r);
 360   void encode_klass_not_null(Register dst, Register src);
 361   void decode_klass_not_null(Register dst, Register src);
 362   void set_narrow_klass(Register dst, Klass* k);
 363   void set_narrow_klass(Address dst, Klass* k);
 364   void cmp_narrow_klass(Register dst, Klass* k);
 365   void cmp_narrow_klass(Address dst, Klass* k);
 366 
 367   // Returns the byte size of the instructions generated by decode_klass_not_null()
 368   // when compressed klass pointers are being used.
 369   static int instr_size_for_decode_klass_not_null();
 370 
 371   // if heap base register is used - reinit it with the correct value
 372   void reinit_heapbase();
 373 
 374   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 375 
 376 #endif // _LP64
 377 
 378   // Int division/remainder for Java
 379   // (as idivl, but checks for special case as described in JVM spec.)
 380   // returns idivl instruction offset for implicit exception handling
 381   int corrected_idivl(Register reg);
 382 
 383   // Long division/remainder for Java
 384   // (as idivq, but checks for special case as described in JVM spec.)
 385   // returns idivq instruction offset for implicit exception handling
 386   int corrected_idivq(Register reg);
 387 
 388   void int3();
 389 
 390   // Long operation macros for a 32bit cpu
 391   // Long negation for Java
 392   void lneg(Register hi, Register lo);
 393 
 394   // Long multiplication for Java
 395   // (destroys contents of eax, ebx, ecx and edx)
 396   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 397 
 398   // Long shifts for Java
 399   // (semantics as described in JVM spec.)
 400   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 401   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 402 
 403   // Long compare for Java
 404   // (semantics as described in JVM spec.)
 405   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 406 
 407 
 408   // misc
 409 
 410   // Sign extension
 411   void sign_extend_short(Register reg);
 412   void sign_extend_byte(Register reg);
 413 
 414   // Division by power of 2, rounding towards 0
 415   void division_with_shift(Register reg, int shift_value);
 416 
 417   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 418   //
 419   // CF (corresponds to C0) if x < y
 420   // PF (corresponds to C2) if unordered
 421   // ZF (corresponds to C3) if x = y
 422   //
 423   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 424   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 425   void fcmp(Register tmp);
 426   // Variant of the above which allows y to be further down the stack
 427   // and which only pops x and y if specified. If pop_right is
 428   // specified then pop_left must also be specified.
 429   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 430 
 431   // Floating-point comparison for Java
 432   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 433   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 434   // (semantics as described in JVM spec.)
 435   void fcmp2int(Register dst, bool unordered_is_less);
 436   // Variant of the above which allows y to be further down the stack
 437   // and which only pops x and y if specified. If pop_right is
 438   // specified then pop_left must also be specified.
 439   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 440 
 441   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 442   // tmp is a temporary register, if none is available use noreg
 443   void fremr(Register tmp);
 444 
 445   // dst = c = a * b + c
 446   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 447   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 448 
 449   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 450   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 451   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 452   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 453 
 454 
 455   // same as fcmp2int, but using SSE2
 456   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 457   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 458 
 459   // branch to L if FPU flag C2 is set/not set
 460   // tmp is a temporary register, if none is available use noreg
 461   void jC2 (Register tmp, Label& L);
 462   void jnC2(Register tmp, Label& L);
 463 
 464   // Pop ST (ffree & fincstp combined)
 465   void fpop();
 466 
 467   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 468   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 469   void load_float(Address src);
 470 
 471   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 472   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 473   void store_float(Address dst);
 474 
 475   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 476   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 477   void load_double(Address src);
 478 
 479   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 480   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 481   void store_double(Address dst);
 482 
 483   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 484   void push_fTOS();
 485 
 486   // pops double TOS element from CPU stack and pushes on FPU stack
 487   void pop_fTOS();
 488 
 489   void empty_FPU_stack();
 490 
 491   void push_IU_state();
 492   void pop_IU_state();
 493 
 494   void push_FPU_state();
 495   void pop_FPU_state();
 496 
 497   void push_CPU_state();
 498   void pop_CPU_state();
 499 
 500   // Round up to a power of two
 501   void round_to(Register reg, int modulus);
 502 
 503   // Callee saved registers handling
 504   void push_callee_saved_registers();
 505   void pop_callee_saved_registers();
 506 
 507   // allocation
 508   void eden_allocate(
 509     Register thread,                   // Current thread
 510     Register obj,                      // result: pointer to object after successful allocation
 511     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 512     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 513     Register t1,                       // temp register
 514     Label&   slow_case                 // continuation point if fast allocation fails
 515   );
 516   void tlab_allocate(
 517     Register thread,                   // Current thread
 518     Register obj,                      // result: pointer to object after successful allocation
 519     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 520     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 521     Register t1,                       // temp register
 522     Register t2,                       // temp register
 523     Label&   slow_case                 // continuation point if fast allocation fails
 524   );
 525   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 526 
 527   // interface method calling
 528   void lookup_interface_method(Register recv_klass,
 529                                Register intf_klass,
 530                                RegisterOrConstant itable_index,
 531                                Register method_result,
 532                                Register scan_temp,
 533                                Label& no_such_interface,
 534                                bool return_method = true);
 535 
 536   // virtual method calling
 537   void lookup_virtual_method(Register recv_klass,
 538                              RegisterOrConstant vtable_index,
 539                              Register method_result);
 540 
 541   // Test sub_klass against super_klass, with fast and slow paths.
 542 
 543   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 544   // One of the three labels can be NULL, meaning take the fall-through.
 545   // If super_check_offset is -1, the value is loaded up from super_klass.
 546   // No registers are killed, except temp_reg.
 547   void check_klass_subtype_fast_path(Register sub_klass,
 548                                      Register super_klass,
 549                                      Register temp_reg,
 550                                      Label* L_success,
 551                                      Label* L_failure,
 552                                      Label* L_slow_path,
 553                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 554 
 555   // The rest of the type check; must be wired to a corresponding fast path.
 556   // It does not repeat the fast path logic, so don't use it standalone.
 557   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 558   // Updates the sub's secondary super cache as necessary.
 559   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 560   void check_klass_subtype_slow_path(Register sub_klass,
 561                                      Register super_klass,
 562                                      Register temp_reg,
 563                                      Register temp2_reg,
 564                                      Label* L_success,
 565                                      Label* L_failure,
 566                                      bool set_cond_codes = false);
 567 
 568   // Simplified, combined version, good for typical uses.
 569   // Falls through on failure.
 570   void check_klass_subtype(Register sub_klass,
 571                            Register super_klass,
 572                            Register temp_reg,
 573                            Label& L_success);
 574 
 575   // method handles (JSR 292)
 576   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 577 
 578   //----
 579   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 580 
 581   // Debugging
 582 
 583   // only if +VerifyOops
 584   // TODO: Make these macros with file and line like sparc version!
 585   void verify_oop(Register reg, const char* s = "broken oop");
 586   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 587 
 588   // TODO: verify method and klass metadata (compare against vptr?)
 589   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 590   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 591 
 592 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 593 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 594 
 595   // only if +VerifyFPU
 596   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 597 
 598   // Verify or restore cpu control state after JNI call
 599   void restore_cpu_control_state_after_jni();
 600 
 601   // prints msg, dumps registers and stops execution
 602   void stop(const char* msg);
 603 
 604   // prints msg and continues
 605   void warn(const char* msg);
 606 
 607   // dumps registers and other state
 608   void print_state();
 609 
 610   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 611   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 612   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 613   static void print_state64(int64_t pc, int64_t regs[]);
 614 
 615   void os_breakpoint();
 616 
 617   void untested()                                { stop("untested"); }
 618 
 619   void unimplemented(const char* what = "");
 620 
 621   void should_not_reach_here()                   { stop("should not reach here"); }
 622 
 623   void print_CPU_state();
 624 
 625   // Stack overflow checking
 626   void bang_stack_with_offset(int offset) {
 627     // stack grows down, caller passes positive offset
 628     assert(offset > 0, "must bang with negative offset");
 629     movl(Address(rsp, (-offset)), rax);
 630   }
 631 
 632   // Writes to stack successive pages until offset reached to check for
 633   // stack overflow + shadow pages.  Also, clobbers tmp
 634   void bang_stack_size(Register size, Register tmp);
 635 
 636   // Check for reserved stack access in method being exited (for JIT)
 637   void reserved_stack_check();
 638 
 639   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 640                                                 Register tmp,
 641                                                 int offset);
 642 
 643   // Support for serializing memory accesses between threads
 644   void serialize_memory(Register thread, Register tmp);
 645 
 646   // If thread_reg is != noreg the code assumes the register passed contains
 647   // the thread (required on 64 bit).
 648   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 649 
 650   void verify_tlab();
 651 
 652   // Biased locking support
 653   // lock_reg and obj_reg must be loaded up with the appropriate values.
 654   // swap_reg must be rax, and is killed.
 655   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 656   // be killed; if not supplied, push/pop will be used internally to
 657   // allocate a temporary (inefficient, avoid if possible).
 658   // Optional slow case is for implementations (interpreter and C1) which branch to
 659   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 660   // Returns offset of first potentially-faulting instruction for null
 661   // check info (currently consumed only by C1). If
 662   // swap_reg_contains_mark is true then returns -1 as it is assumed
 663   // the calling code has already passed any potential faults.
 664   int biased_locking_enter(Register lock_reg, Register obj_reg,
 665                            Register swap_reg, Register tmp_reg,
 666                            bool swap_reg_contains_mark,
 667                            Label& done, Label* slow_case = NULL,
 668                            BiasedLockingCounters* counters = NULL);
 669   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 670 #ifdef COMPILER2
 671   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 672   // See full desription in macroAssembler_x86.cpp.
 673   void fast_lock(Register obj, Register box, Register tmp,
 674                  Register scr, Register cx1, Register cx2,
 675                  BiasedLockingCounters* counters,
 676                  RTMLockingCounters* rtm_counters,
 677                  RTMLockingCounters* stack_rtm_counters,
 678                  Metadata* method_data,
 679                  bool use_rtm, bool profile_rtm);
 680   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 681 #if INCLUDE_RTM_OPT
 682   void rtm_counters_update(Register abort_status, Register rtm_counters);
 683   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 684   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 685                                    RTMLockingCounters* rtm_counters,
 686                                    Metadata* method_data);
 687   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 688                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 689   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 690   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 691   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 692                          Register retry_on_abort_count,
 693                          RTMLockingCounters* stack_rtm_counters,
 694                          Metadata* method_data, bool profile_rtm,
 695                          Label& DONE_LABEL, Label& IsInflated);
 696   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 697                             Register scr, Register retry_on_busy_count,
 698                             Register retry_on_abort_count,
 699                             RTMLockingCounters* rtm_counters,
 700                             Metadata* method_data, bool profile_rtm,
 701                             Label& DONE_LABEL);
 702 #endif
 703 #endif
 704 
 705   Condition negate_condition(Condition cond);
 706 
 707   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 708   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 709   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 710   // here in MacroAssembler. The major exception to this rule is call
 711 
 712   // Arithmetics
 713 
 714 
 715   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 716   void addptr(Address dst, Register src);
 717 
 718   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 719   void addptr(Register dst, int32_t src);
 720   void addptr(Register dst, Register src);
 721   void addptr(Register dst, RegisterOrConstant src) {
 722     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 723     else                   addptr(dst,       src.as_register());
 724   }
 725 
 726   void andptr(Register dst, int32_t src);
 727   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 728 
 729   void cmp8(AddressLiteral src1, int imm);
 730 
 731   // renamed to drag out the casting of address to int32_t/intptr_t
 732   void cmp32(Register src1, int32_t imm);
 733 
 734   void cmp32(AddressLiteral src1, int32_t imm);
 735   // compare reg - mem, or reg - &mem
 736   void cmp32(Register src1, AddressLiteral src2);
 737 
 738   void cmp32(Register src1, Address src2);
 739 
 740 #ifndef _LP64
 741   void cmpklass(Address dst, Metadata* obj);
 742   void cmpklass(Register dst, Metadata* obj);
 743   void cmpoop(Address dst, jobject obj);
 744   void cmpoop_raw(Address dst, jobject obj);
 745 #endif // _LP64
 746 
 747   void cmpoop(Register src1, Register src2);
 748   void cmpoop(Register src1, Address src2);
 749   void cmpoop(Register dst, jobject obj);
 750   void cmpoop_raw(Register dst, jobject obj);
 751 
 752   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 753   void cmpptr(Address src1, AddressLiteral src2);
 754 
 755   void cmpptr(Register src1, AddressLiteral src2);
 756 
 757   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 758   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 759   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 760 
 761   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 762   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 763 
 764   // cmp64 to avoild hiding cmpq
 765   void cmp64(Register src1, AddressLiteral src);
 766 
 767   void cmpxchgptr(Register reg, Address adr);
 768 
 769   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 770 
 771 
 772   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 773   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 774 
 775 
 776   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 777 
 778   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 779 
 780   void shlptr(Register dst, int32_t shift);
 781   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 782 
 783   void shrptr(Register dst, int32_t shift);
 784   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 785 
 786   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 787   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 788 
 789   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 790 
 791   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 792   void subptr(Register dst, int32_t src);
 793   // Force generation of a 4 byte immediate value even if it fits into 8bit
 794   void subptr_imm32(Register dst, int32_t src);
 795   void subptr(Register dst, Register src);
 796   void subptr(Register dst, RegisterOrConstant src) {
 797     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 798     else                   subptr(dst,       src.as_register());
 799   }
 800 
 801   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 802   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 803 
 804   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 805   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 806 
 807   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 808 
 809 
 810 
 811   // Helper functions for statistics gathering.
 812   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 813   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 814   // Unconditional atomic increment.
 815   void atomic_incl(Address counter_addr);
 816   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 817 #ifdef _LP64
 818   void atomic_incq(Address counter_addr);
 819   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 820 #endif
 821   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 822   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 823 
 824   void lea(Register dst, AddressLiteral adr);
 825   void lea(Address dst, AddressLiteral adr);
 826   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 827 
 828   void leal32(Register dst, Address src) { leal(dst, src); }
 829 
 830   // Import other testl() methods from the parent class or else
 831   // they will be hidden by the following overriding declaration.
 832   using Assembler::testl;
 833   void testl(Register dst, AddressLiteral src);
 834 
 835   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 836   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 837   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 838   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 839 
 840   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 841   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 842   void testptr(Register src1, Register src2);
 843 
 844   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 845   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 846 
 847   // Calls
 848 
 849   void call(Label& L, relocInfo::relocType rtype);
 850   void call(Register entry);
 851 
 852   // NOTE: this call transfers to the effective address of entry NOT
 853   // the address contained by entry. This is because this is more natural
 854   // for jumps/calls.
 855   void call(AddressLiteral entry);
 856 
 857   // Emit the CompiledIC call idiom
 858   void ic_call(address entry, jint method_index = 0);
 859 
 860   // Jumps
 861 
 862   // NOTE: these jumps tranfer to the effective address of dst NOT
 863   // the address contained by dst. This is because this is more natural
 864   // for jumps/calls.
 865   void jump(AddressLiteral dst);
 866   void jump_cc(Condition cc, AddressLiteral dst);
 867 
 868   // 32bit can do a case table jump in one instruction but we no longer allow the base
 869   // to be installed in the Address class. This jump will tranfers to the address
 870   // contained in the location described by entry (not the address of entry)
 871   void jump(ArrayAddress entry);
 872 
 873   // Floating
 874 
 875   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 876   void andpd(XMMRegister dst, AddressLiteral src);
 877   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 878 
 879   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 880   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 881   void andps(XMMRegister dst, AddressLiteral src);
 882 
 883   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 884   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 885   void comiss(XMMRegister dst, AddressLiteral src);
 886 
 887   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 888   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 889   void comisd(XMMRegister dst, AddressLiteral src);
 890 
 891   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 892   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 893 
 894   void fldcw(Address src) { Assembler::fldcw(src); }
 895   void fldcw(AddressLiteral src);
 896 
 897   void fld_s(int index)   { Assembler::fld_s(index); }
 898   void fld_s(Address src) { Assembler::fld_s(src); }
 899   void fld_s(AddressLiteral src);
 900 
 901   void fld_d(Address src) { Assembler::fld_d(src); }
 902   void fld_d(AddressLiteral src);
 903 
 904   void fld_x(Address src) { Assembler::fld_x(src); }
 905   void fld_x(AddressLiteral src);
 906 
 907   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 908   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 909 
 910   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 911   void ldmxcsr(AddressLiteral src);
 912 
 913 #ifdef _LP64
 914  private:
 915   void sha256_AVX2_one_round_compute(
 916     Register  reg_old_h,
 917     Register  reg_a,
 918     Register  reg_b,
 919     Register  reg_c,
 920     Register  reg_d,
 921     Register  reg_e,
 922     Register  reg_f,
 923     Register  reg_g,
 924     Register  reg_h,
 925     int iter);
 926   void sha256_AVX2_four_rounds_compute_first(int start);
 927   void sha256_AVX2_four_rounds_compute_last(int start);
 928   void sha256_AVX2_one_round_and_sched(
 929         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 930         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 931         XMMRegister xmm_2,     /* ymm6 */
 932         XMMRegister xmm_3,     /* ymm7 */
 933         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 934         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 935         Register    reg_c,      /* edi */
 936         Register    reg_d,      /* esi */
 937         Register    reg_e,      /* r8d */
 938         Register    reg_f,      /* r9d */
 939         Register    reg_g,      /* r10d */
 940         Register    reg_h,      /* r11d */
 941         int iter);
 942 
 943   void addm(int disp, Register r1, Register r2);
 944 
 945  public:
 946   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 947                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 948                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 949                    bool multi_block, XMMRegister shuf_mask);
 950 #endif
 951 
 952 #ifdef _LP64
 953  private:
 954   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 955                                      Register e, Register f, Register g, Register h, int iteration);
 956 
 957   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 958                                           Register a, Register b, Register c, Register d, Register e, Register f,
 959                                           Register g, Register h, int iteration);
 960 
 961   void addmq(int disp, Register r1, Register r2);
 962  public:
 963   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 964                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 965                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 966                    XMMRegister shuf_mask);
 967 #endif
 968 
 969   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 970                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 971                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 972                  bool multi_block);
 973 
 974 #ifdef _LP64
 975   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 976                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 977                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 978                    bool multi_block, XMMRegister shuf_mask);
 979 #else
 980   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 981                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 982                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 983                    bool multi_block);
 984 #endif
 985 
 986   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 987                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 988                 Register rax, Register rcx, Register rdx, Register tmp);
 989 
 990 #ifdef _LP64
 991   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 992                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 993                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
 994 
 995   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 996                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 997                   Register rax, Register rcx, Register rdx, Register r11);
 998 
 999   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1000                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1001                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1002 
1003   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1004                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1005                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1006                 Register tmp3, Register tmp4);
1007 
1008   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1009                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1010                 Register rax, Register rcx, Register rdx, Register tmp1,
1011                 Register tmp2, Register tmp3, Register tmp4);
1012   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1013                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1014                 Register rax, Register rcx, Register rdx, Register tmp1,
1015                 Register tmp2, Register tmp3, Register tmp4);
1016 #else
1017   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1018                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1019                 Register rax, Register rcx, Register rdx, Register tmp1);
1020 
1021   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1022                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1023                 Register rax, Register rcx, Register rdx, Register tmp);
1024 
1025   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1026                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1027                 Register rdx, Register tmp);
1028 
1029   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1030                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1031                 Register rax, Register rbx, Register rdx);
1032 
1033   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1034                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1035                 Register rax, Register rcx, Register rdx, Register tmp);
1036 
1037   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1038                         Register edx, Register ebx, Register esi, Register edi,
1039                         Register ebp, Register esp);
1040 
1041   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1042                          Register esi, Register edi, Register ebp, Register esp);
1043 
1044   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1045                         Register edx, Register ebx, Register esi, Register edi,
1046                         Register ebp, Register esp);
1047 
1048   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1049                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1050                 Register rax, Register rcx, Register rdx, Register tmp);
1051 #endif
1052 
1053   void increase_precision();
1054   void restore_precision();
1055 
1056 private:
1057 
1058   // these are private because users should be doing movflt/movdbl
1059 
1060   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1061   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1062   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1063   void movss(XMMRegister dst, AddressLiteral src);
1064 
1065   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1066   void movlpd(XMMRegister dst, AddressLiteral src);
1067 
1068 public:
1069 
1070   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1071   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1072   void addsd(XMMRegister dst, AddressLiteral src);
1073 
1074   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1075   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1076   void addss(XMMRegister dst, AddressLiteral src);
1077 
1078   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1079   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1080   void addpd(XMMRegister dst, AddressLiteral src);
1081 
1082   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1083   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1084   void divsd(XMMRegister dst, AddressLiteral src);
1085 
1086   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1087   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1088   void divss(XMMRegister dst, AddressLiteral src);
1089 
1090   // Move Unaligned Double Quadword
1091   void movdqu(Address     dst, XMMRegister src);
1092   void movdqu(XMMRegister dst, Address src);
1093   void movdqu(XMMRegister dst, XMMRegister src);
1094   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1095   // AVX Unaligned forms
1096   void vmovdqu(Address     dst, XMMRegister src);
1097   void vmovdqu(XMMRegister dst, Address src);
1098   void vmovdqu(XMMRegister dst, XMMRegister src);
1099   void vmovdqu(XMMRegister dst, AddressLiteral src);
1100   void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1101   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1102   void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1103   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1104 
1105   // Move Aligned Double Quadword
1106   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1107   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1108   void movdqa(XMMRegister dst, AddressLiteral src);
1109 
1110   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1111   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1112   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1113   void movsd(XMMRegister dst, AddressLiteral src);
1114 
1115   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1116   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1117   void mulpd(XMMRegister dst, AddressLiteral src);
1118 
1119   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1120   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1121   void mulsd(XMMRegister dst, AddressLiteral src);
1122 
1123   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1124   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1125   void mulss(XMMRegister dst, AddressLiteral src);
1126 
1127   // Carry-Less Multiplication Quadword
1128   void pclmulldq(XMMRegister dst, XMMRegister src) {
1129     // 0x00 - multiply lower 64 bits [0:63]
1130     Assembler::pclmulqdq(dst, src, 0x00);
1131   }
1132   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1133     // 0x11 - multiply upper 64 bits [64:127]
1134     Assembler::pclmulqdq(dst, src, 0x11);
1135   }
1136 
1137   void pcmpeqb(XMMRegister dst, XMMRegister src);
1138   void pcmpeqw(XMMRegister dst, XMMRegister src);
1139 
1140   void pcmpestri(XMMRegister dst, Address src, int imm8);
1141   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1142 
1143   void pmovzxbw(XMMRegister dst, XMMRegister src);
1144   void pmovzxbw(XMMRegister dst, Address src);
1145 
1146   void pmovmskb(Register dst, XMMRegister src);
1147 
1148   void ptest(XMMRegister dst, XMMRegister src);
1149 
1150   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1151   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1152   void sqrtsd(XMMRegister dst, AddressLiteral src);
1153 
1154   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1155   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1156   void sqrtss(XMMRegister dst, AddressLiteral src);
1157 
1158   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1159   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1160   void subsd(XMMRegister dst, AddressLiteral src);
1161 
1162   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1163   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1164   void subss(XMMRegister dst, AddressLiteral src);
1165 
1166   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1167   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1168   void ucomiss(XMMRegister dst, AddressLiteral src);
1169 
1170   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1171   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1172   void ucomisd(XMMRegister dst, AddressLiteral src);
1173 
1174   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1175   void xorpd(XMMRegister dst, XMMRegister src);
1176   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1177   void xorpd(XMMRegister dst, AddressLiteral src);
1178 
1179   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1180   void xorps(XMMRegister dst, XMMRegister src);
1181   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1182   void xorps(XMMRegister dst, AddressLiteral src);
1183 
1184   // Shuffle Bytes
1185   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1186   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1187   void pshufb(XMMRegister dst, AddressLiteral src);
1188   // AVX 3-operands instructions
1189 
1190   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1191   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1192   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1193 
1194   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1195   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1196   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1197 
1198   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1199   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1200 
1201   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1202   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1203 
1204   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1205   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1206 
1207   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1208   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1209   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1210 
1211   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1212   void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1213 
1214   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1215 
1216   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1217 
1218   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1219   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1220 
1221   void vpmovmskb(Register dst, XMMRegister src);
1222 
1223   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1224   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1225 
1226   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1227   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1228 
1229   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1230   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1231 
1232   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1233   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1234 
1235   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1236   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1237 
1238   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1239   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1240 
1241   void vptest(XMMRegister dst, XMMRegister src);
1242 
1243   void punpcklbw(XMMRegister dst, XMMRegister src);
1244   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1245 
1246   void pshufd(XMMRegister dst, Address src, int mode);
1247   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1248 
1249   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1250   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1251 
1252   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1253   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1254   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1255 
1256   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1257   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1258   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1259 
1260   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1261   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1262   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1263 
1264   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1265   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1266   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1267 
1268   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1269   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1270   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1271 
1272   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1273   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1274   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1275 
1276   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1277   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1278   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1279 
1280   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1281   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1282   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1283 
1284   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1285   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1286 
1287   // AVX Vector instructions
1288 
1289   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1290   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1291   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1292 
1293   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1294   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1295   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1296 
1297   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1298     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1299       Assembler::vpxor(dst, nds, src, vector_len);
1300     else
1301       Assembler::vxorpd(dst, nds, src, vector_len);
1302   }
1303   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1304     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1305       Assembler::vpxor(dst, nds, src, vector_len);
1306     else
1307       Assembler::vxorpd(dst, nds, src, vector_len);
1308   }
1309 
1310   // Simple version for AVX2 256bit vectors
1311   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1312   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1313 
1314   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1315     if (UseAVX > 2) {
1316       Assembler::vinserti32x4(dst, dst, src, imm8);
1317     } else if (UseAVX > 1) {
1318       // vinserti128 is available only in AVX2
1319       Assembler::vinserti128(dst, nds, src, imm8);
1320     } else {
1321       Assembler::vinsertf128(dst, nds, src, imm8);
1322     }
1323   }
1324 
1325   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1326     if (UseAVX > 2) {
1327       Assembler::vinserti32x4(dst, dst, src, imm8);
1328     } else if (UseAVX > 1) {
1329       // vinserti128 is available only in AVX2
1330       Assembler::vinserti128(dst, nds, src, imm8);
1331     } else {
1332       Assembler::vinsertf128(dst, nds, src, imm8);
1333     }
1334   }
1335 
1336   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1337     if (UseAVX > 2) {
1338       Assembler::vextracti32x4(dst, src, imm8);
1339     } else if (UseAVX > 1) {
1340       // vextracti128 is available only in AVX2
1341       Assembler::vextracti128(dst, src, imm8);
1342     } else {
1343       Assembler::vextractf128(dst, src, imm8);
1344     }
1345   }
1346 
1347   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1348     if (UseAVX > 2) {
1349       Assembler::vextracti32x4(dst, src, imm8);
1350     } else if (UseAVX > 1) {
1351       // vextracti128 is available only in AVX2
1352       Assembler::vextracti128(dst, src, imm8);
1353     } else {
1354       Assembler::vextractf128(dst, src, imm8);
1355     }
1356   }
1357 
1358   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1359   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1360     vinserti128(dst, dst, src, 1);
1361   }
1362   void vinserti128_high(XMMRegister dst, Address src) {
1363     vinserti128(dst, dst, src, 1);
1364   }
1365   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1366     vextracti128(dst, src, 1);
1367   }
1368   void vextracti128_high(Address dst, XMMRegister src) {
1369     vextracti128(dst, src, 1);
1370   }
1371 
1372   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1373     if (UseAVX > 2) {
1374       Assembler::vinsertf32x4(dst, dst, src, 1);
1375     } else {
1376       Assembler::vinsertf128(dst, dst, src, 1);
1377     }
1378   }
1379 
1380   void vinsertf128_high(XMMRegister dst, Address src) {
1381     if (UseAVX > 2) {
1382       Assembler::vinsertf32x4(dst, dst, src, 1);
1383     } else {
1384       Assembler::vinsertf128(dst, dst, src, 1);
1385     }
1386   }
1387 
1388   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1389     if (UseAVX > 2) {
1390       Assembler::vextractf32x4(dst, src, 1);
1391     } else {
1392       Assembler::vextractf128(dst, src, 1);
1393     }
1394   }
1395 
1396   void vextractf128_high(Address dst, XMMRegister src) {
1397     if (UseAVX > 2) {
1398       Assembler::vextractf32x4(dst, src, 1);
1399     } else {
1400       Assembler::vextractf128(dst, src, 1);
1401     }
1402   }
1403 
1404   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1405   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1406     Assembler::vinserti64x4(dst, dst, src, 1);
1407   }
1408   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1409     Assembler::vinsertf64x4(dst, dst, src, 1);
1410   }
1411   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1412     Assembler::vextracti64x4(dst, src, 1);
1413   }
1414   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1415     Assembler::vextractf64x4(dst, src, 1);
1416   }
1417   void vextractf64x4_high(Address dst, XMMRegister src) {
1418     Assembler::vextractf64x4(dst, src, 1);
1419   }
1420   void vinsertf64x4_high(XMMRegister dst, Address src) {
1421     Assembler::vinsertf64x4(dst, dst, src, 1);
1422   }
1423 
1424   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1425   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1426     vinserti128(dst, dst, src, 0);
1427   }
1428   void vinserti128_low(XMMRegister dst, Address src) {
1429     vinserti128(dst, dst, src, 0);
1430   }
1431   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1432     vextracti128(dst, src, 0);
1433   }
1434   void vextracti128_low(Address dst, XMMRegister src) {
1435     vextracti128(dst, src, 0);
1436   }
1437 
1438   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1439     if (UseAVX > 2) {
1440       Assembler::vinsertf32x4(dst, dst, src, 0);
1441     } else {
1442       Assembler::vinsertf128(dst, dst, src, 0);
1443     }
1444   }
1445 
1446   void vinsertf128_low(XMMRegister dst, Address src) {
1447     if (UseAVX > 2) {
1448       Assembler::vinsertf32x4(dst, dst, src, 0);
1449     } else {
1450       Assembler::vinsertf128(dst, dst, src, 0);
1451     }
1452   }
1453 
1454   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1455     if (UseAVX > 2) {
1456       Assembler::vextractf32x4(dst, src, 0);
1457     } else {
1458       Assembler::vextractf128(dst, src, 0);
1459     }
1460   }
1461 
1462   void vextractf128_low(Address dst, XMMRegister src) {
1463     if (UseAVX > 2) {
1464       Assembler::vextractf32x4(dst, src, 0);
1465     } else {
1466       Assembler::vextractf128(dst, src, 0);
1467     }
1468   }
1469 
1470   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1471   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1472     Assembler::vinserti64x4(dst, dst, src, 0);
1473   }
1474   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1475     Assembler::vinsertf64x4(dst, dst, src, 0);
1476   }
1477   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1478     Assembler::vextracti64x4(dst, src, 0);
1479   }
1480   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1481     Assembler::vextractf64x4(dst, src, 0);
1482   }
1483   void vextractf64x4_low(Address dst, XMMRegister src) {
1484     Assembler::vextractf64x4(dst, src, 0);
1485   }
1486   void vinsertf64x4_low(XMMRegister dst, Address src) {
1487     Assembler::vinsertf64x4(dst, dst, src, 0);
1488   }
1489 
1490   // Carry-Less Multiplication Quadword
1491   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1492     // 0x00 - multiply lower 64 bits [0:63]
1493     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1494   }
1495   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1496     // 0x11 - multiply upper 64 bits [64:127]
1497     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1498   }
1499   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1500     // 0x00 - multiply lower 64 bits [0:63]
1501     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1502   }
1503   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1504     // 0x11 - multiply upper 64 bits [64:127]
1505     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1506   }
1507 
1508   // Data
1509 
1510   void cmov32( Condition cc, Register dst, Address  src);
1511   void cmov32( Condition cc, Register dst, Register src);
1512 
1513   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1514 
1515   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1516   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1517 
1518   void movoop(Register dst, jobject obj);
1519   void movoop(Address dst, jobject obj);
1520 
1521   void mov_metadata(Register dst, Metadata* obj);
1522   void mov_metadata(Address dst, Metadata* obj);
1523 
1524   void movptr(ArrayAddress dst, Register src);
1525   // can this do an lea?
1526   void movptr(Register dst, ArrayAddress src);
1527 
1528   void movptr(Register dst, Address src);
1529 
1530 #ifdef _LP64
1531   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1532 #else
1533   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1534 #endif
1535 
1536   void movptr(Register dst, intptr_t src);
1537   void movptr(Register dst, Register src);
1538   void movptr(Address dst, intptr_t src);
1539 
1540   void movptr(Address dst, Register src);
1541 
1542   void movptr(Register dst, RegisterOrConstant src) {
1543     if (src.is_constant()) movptr(dst, src.as_constant());
1544     else                   movptr(dst, src.as_register());
1545   }
1546 
1547 #ifdef _LP64
1548   // Generally the next two are only used for moving NULL
1549   // Although there are situations in initializing the mark word where
1550   // they could be used. They are dangerous.
1551 
1552   // They only exist on LP64 so that int32_t and intptr_t are not the same
1553   // and we have ambiguous declarations.
1554 
1555   void movptr(Address dst, int32_t imm32);
1556   void movptr(Register dst, int32_t imm32);
1557 #endif // _LP64
1558 
1559   // to avoid hiding movl
1560   void mov32(AddressLiteral dst, Register src);
1561   void mov32(Register dst, AddressLiteral src);
1562 
1563   // to avoid hiding movb
1564   void movbyte(ArrayAddress dst, int src);
1565 
1566   // Import other mov() methods from the parent class or else
1567   // they will be hidden by the following overriding declaration.
1568   using Assembler::movdl;
1569   using Assembler::movq;
1570   void movdl(XMMRegister dst, AddressLiteral src);
1571   void movq(XMMRegister dst, AddressLiteral src);
1572 
1573   // Can push value or effective address
1574   void pushptr(AddressLiteral src);
1575 
1576   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1577   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1578 
1579   void pushoop(jobject obj);
1580   void pushklass(Metadata* obj);
1581 
1582   // sign extend as need a l to ptr sized element
1583   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1584   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1585 
1586   // C2 compiled method's prolog code.
1587   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1588 
1589   // clear memory of size 'cnt' qwords, starting at 'base';
1590   // if 'is_large' is set, do not try to produce short loop
1591   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1592 
1593   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1594   void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1595 
1596 #ifdef COMPILER2
1597   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1598                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1599 
1600   // IndexOf strings.
1601   // Small strings are loaded through stack if they cross page boundary.
1602   void string_indexof(Register str1, Register str2,
1603                       Register cnt1, Register cnt2,
1604                       int int_cnt2,  Register result,
1605                       XMMRegister vec, Register tmp,
1606                       int ae);
1607 
1608   // IndexOf for constant substrings with size >= 8 elements
1609   // which don't need to be loaded through stack.
1610   void string_indexofC8(Register str1, Register str2,
1611                       Register cnt1, Register cnt2,
1612                       int int_cnt2,  Register result,
1613                       XMMRegister vec, Register tmp,
1614                       int ae);
1615 
1616     // Smallest code: we don't need to load through stack,
1617     // check string tail.
1618 
1619   // helper function for string_compare
1620   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1621                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1622                           Address::ScaleFactor scale2, Register index, int ae);
1623   // Compare strings.
1624   void string_compare(Register str1, Register str2,
1625                       Register cnt1, Register cnt2, Register result,
1626                       XMMRegister vec1, int ae);
1627 
1628   // Search for Non-ASCII character (Negative byte value) in a byte array,
1629   // return true if it has any and false otherwise.
1630   void has_negatives(Register ary1, Register len,
1631                      Register result, Register tmp1,
1632                      XMMRegister vec1, XMMRegister vec2);
1633 
1634   // Compare char[] or byte[] arrays.
1635   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1636                      Register limit, Register result, Register chr,
1637                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1638 
1639 #endif
1640 
1641   // Fill primitive arrays
1642   void generate_fill(BasicType t, bool aligned,
1643                      Register to, Register value, Register count,
1644                      Register rtmp, XMMRegister xtmp);
1645 
1646   void encode_iso_array(Register src, Register dst, Register len,
1647                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1648                         XMMRegister tmp4, Register tmp5, Register result);
1649 
1650 #ifdef _LP64
1651   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1652   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1653                              Register y, Register y_idx, Register z,
1654                              Register carry, Register product,
1655                              Register idx, Register kdx);
1656   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1657                               Register yz_idx, Register idx,
1658                               Register carry, Register product, int offset);
1659   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1660                                     Register carry, Register carry2,
1661                                     Register idx, Register jdx,
1662                                     Register yz_idx1, Register yz_idx2,
1663                                     Register tmp, Register tmp3, Register tmp4);
1664   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1665                                Register yz_idx, Register idx, Register jdx,
1666                                Register carry, Register product,
1667                                Register carry2);
1668   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1669                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1670   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1671                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1672   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1673                             Register tmp2);
1674   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1675                        Register rdxReg, Register raxReg);
1676   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1677   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1678                        Register tmp3, Register tmp4);
1679   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1680                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1681 
1682   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1683                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1684                Register raxReg);
1685   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1686                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1687                Register raxReg);
1688   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1689                            Register result, Register tmp1, Register tmp2,
1690                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1691 #endif
1692 
1693   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1694   void update_byte_crc32(Register crc, Register val, Register table);
1695   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1696   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1697   // Note on a naming convention:
1698   // Prefix w = register only used on a Westmere+ architecture
1699   // Prefix n = register only used on a Nehalem architecture
1700 #ifdef _LP64
1701   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1702                        Register tmp1, Register tmp2, Register tmp3);
1703 #else
1704   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1705                        Register tmp1, Register tmp2, Register tmp3,
1706                        XMMRegister xtmp1, XMMRegister xtmp2);
1707 #endif
1708   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1709                         Register in_out,
1710                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1711                         XMMRegister w_xtmp2,
1712                         Register tmp1,
1713                         Register n_tmp2, Register n_tmp3);
1714   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1715                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1716                        Register tmp1, Register tmp2,
1717                        Register n_tmp3);
1718   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1719                          Register in_out1, Register in_out2, Register in_out3,
1720                          Register tmp1, Register tmp2, Register tmp3,
1721                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1722                          Register tmp4, Register tmp5,
1723                          Register n_tmp6);
1724   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1725                             Register tmp1, Register tmp2, Register tmp3,
1726                             Register tmp4, Register tmp5, Register tmp6,
1727                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1728                             bool is_pclmulqdq_supported);
1729   // Fold 128-bit data chunk
1730   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1731   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1732   // Fold 8-bit data
1733   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1734   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1735   void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1736 
1737   // Compress char[] array to byte[].
1738   void char_array_compress(Register src, Register dst, Register len,
1739                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1740                            XMMRegister tmp4, Register tmp5, Register result);
1741 
1742   // Inflate byte[] array to char[].
1743   void byte_array_inflate(Register src, Register dst, Register len,
1744                           XMMRegister tmp1, Register tmp2);
1745 
1746 };
1747 
1748 /**
1749  * class SkipIfEqual:
1750  *
1751  * Instantiating this class will result in assembly code being output that will
1752  * jump around any code emitted between the creation of the instance and it's
1753  * automatic destruction at the end of a scope block, depending on the value of
1754  * the flag passed to the constructor, which will be checked at run-time.
1755  */
1756 class SkipIfEqual {
1757  private:
1758   MacroAssembler* _masm;
1759   Label _label;
1760 
1761  public:
1762    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1763    ~SkipIfEqual();
1764 };
1765 
1766 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP