1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  public:
  42   // Support for VM calls
  43   //
  44   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  45   // may customize this version by overriding it for its purposes (e.g., to save/restore
  46   // additional registers when doing a VM call).
  47 
  48   virtual void call_VM_leaf_base(
  49     address entry_point,               // the entry point
  50     int     number_of_arguments        // the number of arguments to pop after the call
  51   );
  52 
  53  protected:
  54   // This is the base routine called by the different versions of call_VM. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   //
  58   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  59   // returns the register which contains the thread upon return. If a thread register has been
  60   // specified, the return value will correspond to that register. If no last_java_sp is specified
  61   // (noreg) than rsp will be used instead.
  62   virtual void call_VM_base(           // returns the register containing the thread upon return
  63     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  64     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  65     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  66     address  entry_point,              // the entry point
  67     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  68     bool     check_exceptions          // whether to check for pending exceptions after return
  69   );
  70 
  71   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  72 
  73   // helpers for FPU flag access
  74   // tmp is a temporary register, if none is available use noreg
  75   void save_rax   (Register tmp);
  76   void restore_rax(Register tmp);
  77 
  78  public:
  79   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  80 
  81  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82  // The implementation is only non-empty for the InterpreterMacroAssembler,
  83  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84  virtual void check_and_handle_popframe(Register java_thread);
  85  virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   Address as_Address(AddressLiteral adr);
  88   Address as_Address(ArrayAddress adr);
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99 
 100   // Required platform-specific helpers for Label::patch_instructions.
 101   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 102   void pd_patch_instruction(address branch, address target) {
 103     unsigned char op = branch[0];
 104     assert(op == 0xE8 /* call */ ||
 105         op == 0xE9 /* jmp */ ||
 106         op == 0xEB /* short jmp */ ||
 107         (op & 0xF0) == 0x70 /* short jcc */ ||
 108         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 109         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 110         "Invalid opcode at patch point");
 111 
 112     if (op == 0xEB || (op & 0xF0) == 0x70) {
 113       // short offset operators (jmp and jcc)
 114       char* disp = (char*) &branch[1];
 115       int imm8 = target - (address) &disp[1];
 116       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
 117       *disp = imm8;
 118     } else {
 119       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 120       int imm32 = target - (address) &disp[1];
 121       *disp = imm32;
 122     }
 123   }
 124 
 125   // The following 4 methods return the offset of the appropriate move instruction
 126 
 127   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 128   int load_unsigned_byte(Register dst, Address src);
 129   int load_unsigned_short(Register dst, Address src);
 130 
 131   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 132   int load_signed_byte(Register dst, Address src);
 133   int load_signed_short(Register dst, Address src);
 134 
 135   // Support for sign-extension (hi:lo = extend_sign(lo))
 136   void extend_sign(Register hi, Register lo);
 137 
 138   // Load and store values by size and signed-ness
 139   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 140   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 141 
 142   // Support for inc/dec with optimal instruction selection depending on value
 143 
 144   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 145   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 146 
 147   void decrementl(Address dst, int value = 1);
 148   void decrementl(Register reg, int value = 1);
 149 
 150   void decrementq(Register reg, int value = 1);
 151   void decrementq(Address dst, int value = 1);
 152 
 153   void incrementl(Address dst, int value = 1);
 154   void incrementl(Register reg, int value = 1);
 155 
 156   void incrementq(Register reg, int value = 1);
 157   void incrementq(Address dst, int value = 1);
 158 
 159 #ifdef COMPILER2
 160   // special instructions for EVEX
 161   void setvectmask(Register dst, Register src);
 162   void restorevectmask();
 163 #endif
 164 
 165   // Support optimal SSE move instructions.
 166   void movflt(XMMRegister dst, XMMRegister src) {
 167     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 168     else                       { movss (dst, src); return; }
 169   }
 170   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 171   void movflt(XMMRegister dst, AddressLiteral src);
 172   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 173 
 174   void movdbl(XMMRegister dst, XMMRegister src) {
 175     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 176     else                       { movsd (dst, src); return; }
 177   }
 178 
 179   void movdbl(XMMRegister dst, AddressLiteral src);
 180 
 181   void movdbl(XMMRegister dst, Address src) {
 182     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 183     else                         { movlpd(dst, src); return; }
 184   }
 185   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 186 
 187   void incrementl(AddressLiteral dst);
 188   void incrementl(ArrayAddress dst);
 189 
 190   void incrementq(AddressLiteral dst);
 191 
 192   // Alignment
 193   void align(int modulus);
 194   void align(int modulus, int target);
 195 
 196   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 197   void fat_nop();
 198 
 199   // Stack frame creation/removal
 200   void enter();
 201   void leave();
 202 
 203   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 204   // The pointer will be loaded into the thread register.
 205   void get_thread(Register thread);
 206 
 207 
 208   // Support for VM calls
 209   //
 210   // It is imperative that all calls into the VM are handled via the call_VM macros.
 211   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 212   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 213 
 214 
 215   void call_VM(Register oop_result,
 216                address entry_point,
 217                bool check_exceptions = true);
 218   void call_VM(Register oop_result,
 219                address entry_point,
 220                Register arg_1,
 221                bool check_exceptions = true);
 222   void call_VM(Register oop_result,
 223                address entry_point,
 224                Register arg_1, Register arg_2,
 225                bool check_exceptions = true);
 226   void call_VM(Register oop_result,
 227                address entry_point,
 228                Register arg_1, Register arg_2, Register arg_3,
 229                bool check_exceptions = true);
 230 
 231   // Overloadings with last_Java_sp
 232   void call_VM(Register oop_result,
 233                Register last_java_sp,
 234                address entry_point,
 235                int number_of_arguments = 0,
 236                bool check_exceptions = true);
 237   void call_VM(Register oop_result,
 238                Register last_java_sp,
 239                address entry_point,
 240                Register arg_1, bool
 241                check_exceptions = true);
 242   void call_VM(Register oop_result,
 243                Register last_java_sp,
 244                address entry_point,
 245                Register arg_1, Register arg_2,
 246                bool check_exceptions = true);
 247   void call_VM(Register oop_result,
 248                Register last_java_sp,
 249                address entry_point,
 250                Register arg_1, Register arg_2, Register arg_3,
 251                bool check_exceptions = true);
 252 
 253   void get_vm_result  (Register oop_result, Register thread);
 254   void get_vm_result_2(Register metadata_result, Register thread);
 255 
 256   // These always tightly bind to MacroAssembler::call_VM_base
 257   // bypassing the virtual implementation
 258   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 259   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 260   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 261   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 263 
 264   void call_VM_leaf0(address entry_point);
 265   void call_VM_leaf(address entry_point,
 266                     int number_of_arguments = 0);
 267   void call_VM_leaf(address entry_point,
 268                     Register arg_1);
 269   void call_VM_leaf(address entry_point,
 270                     Register arg_1, Register arg_2);
 271   void call_VM_leaf(address entry_point,
 272                     Register arg_1, Register arg_2, Register arg_3);
 273 
 274   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 275   // bypassing the virtual implementation
 276   void super_call_VM_leaf(address entry_point);
 277   void super_call_VM_leaf(address entry_point, Register arg_1);
 278   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 279   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 280   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 281 
 282   // last Java Frame (fills frame anchor)
 283   void set_last_Java_frame(Register thread,
 284                            Register last_java_sp,
 285                            Register last_java_fp,
 286                            address last_java_pc);
 287 
 288   // thread in the default location (r15_thread on 64bit)
 289   void set_last_Java_frame(Register last_java_sp,
 290                            Register last_java_fp,
 291                            address last_java_pc);
 292 
 293   void reset_last_Java_frame(Register thread, bool clear_fp);
 294 
 295   // thread in the default location (r15_thread on 64bit)
 296   void reset_last_Java_frame(bool clear_fp);
 297 
 298   // jobjects
 299   void clear_jweak_tag(Register possibly_jweak);
 300   void resolve_jobject(Register value, Register thread, Register tmp);
 301 
 302   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 303   void c2bool(Register x);
 304 
 305   // C++ bool manipulation
 306 
 307   void movbool(Register dst, Address src);
 308   void movbool(Address dst, bool boolconst);
 309   void movbool(Address dst, Register src);
 310   void testbool(Register dst);
 311 
 312   void resolve_oop_handle(Register result, Register tmp = rscratch2);
 313   void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
 314 
 315   // oop manipulations
 316   void load_klass(Register dst, Register src);
 317   void store_klass(Register dst, Register src);
 318 
 319   void resolve_for_read(DecoratorSet decorators, Register obj);
 320   void resolve_for_write(DecoratorSet decorators, Register obj);
 321 
 322   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 323                       Register tmp1, Register thread_tmp);
 324   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 325                        Register tmp1, Register tmp2);
 326 
 327   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 328                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 329   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 330                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 331   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 332                       Register tmp2 = noreg, DecoratorSet decorators = 0);
 333 
 334   // Used for storing NULL. All other oop constants should be
 335   // stored using routines that take a jobject.
 336   void store_heap_oop_null(Address dst);
 337 
 338   void load_prototype_header(Register dst, Register src);
 339 
 340 #ifdef _LP64
 341   void store_klass_gap(Register dst, Register src);
 342 
 343   // This dummy is to prevent a call to store_heap_oop from
 344   // converting a zero (like NULL) into a Register by giving
 345   // the compiler two choices it can't resolve
 346 
 347   void store_heap_oop(Address dst, void* dummy);
 348 
 349   void encode_heap_oop(Register r);
 350   void decode_heap_oop(Register r);
 351   void encode_heap_oop_not_null(Register r);
 352   void decode_heap_oop_not_null(Register r);
 353   void encode_heap_oop_not_null(Register dst, Register src);
 354   void decode_heap_oop_not_null(Register dst, Register src);
 355 
 356   void set_narrow_oop(Register dst, jobject obj);
 357   void set_narrow_oop(Address dst, jobject obj);
 358   void cmp_narrow_oop(Register dst, jobject obj);
 359   void cmp_narrow_oop(Address dst, jobject obj);
 360 
 361   void encode_klass_not_null(Register r);
 362   void decode_klass_not_null(Register r);
 363   void encode_klass_not_null(Register dst, Register src);
 364   void decode_klass_not_null(Register dst, Register src);
 365   void set_narrow_klass(Register dst, Klass* k);
 366   void set_narrow_klass(Address dst, Klass* k);
 367   void cmp_narrow_klass(Register dst, Klass* k);
 368   void cmp_narrow_klass(Address dst, Klass* k);
 369 
 370   // Returns the byte size of the instructions generated by decode_klass_not_null()
 371   // when compressed klass pointers are being used.
 372   static int instr_size_for_decode_klass_not_null();
 373 
 374   // if heap base register is used - reinit it with the correct value
 375   void reinit_heapbase();
 376 
 377   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 378 
 379 #endif // _LP64
 380 
 381   // Int division/remainder for Java
 382   // (as idivl, but checks for special case as described in JVM spec.)
 383   // returns idivl instruction offset for implicit exception handling
 384   int corrected_idivl(Register reg);
 385 
 386   // Long division/remainder for Java
 387   // (as idivq, but checks for special case as described in JVM spec.)
 388   // returns idivq instruction offset for implicit exception handling
 389   int corrected_idivq(Register reg);
 390 
 391   void int3();
 392 
 393   // Long operation macros for a 32bit cpu
 394   // Long negation for Java
 395   void lneg(Register hi, Register lo);
 396 
 397   // Long multiplication for Java
 398   // (destroys contents of eax, ebx, ecx and edx)
 399   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 400 
 401   // Long shifts for Java
 402   // (semantics as described in JVM spec.)
 403   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 404   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 405 
 406   // Long compare for Java
 407   // (semantics as described in JVM spec.)
 408   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 409 
 410 
 411   // misc
 412 
 413   // Sign extension
 414   void sign_extend_short(Register reg);
 415   void sign_extend_byte(Register reg);
 416 
 417   // Division by power of 2, rounding towards 0
 418   void division_with_shift(Register reg, int shift_value);
 419 
 420   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 421   //
 422   // CF (corresponds to C0) if x < y
 423   // PF (corresponds to C2) if unordered
 424   // ZF (corresponds to C3) if x = y
 425   //
 426   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 427   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 428   void fcmp(Register tmp);
 429   // Variant of the above which allows y to be further down the stack
 430   // and which only pops x and y if specified. If pop_right is
 431   // specified then pop_left must also be specified.
 432   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 433 
 434   // Floating-point comparison for Java
 435   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 436   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 437   // (semantics as described in JVM spec.)
 438   void fcmp2int(Register dst, bool unordered_is_less);
 439   // Variant of the above which allows y to be further down the stack
 440   // and which only pops x and y if specified. If pop_right is
 441   // specified then pop_left must also be specified.
 442   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 443 
 444   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 445   // tmp is a temporary register, if none is available use noreg
 446   void fremr(Register tmp);
 447 
 448   // dst = c = a * b + c
 449   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 450   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 451 
 452   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 453   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 454   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 455   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 456 
 457 
 458   // same as fcmp2int, but using SSE2
 459   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 460   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 461 
 462   // branch to L if FPU flag C2 is set/not set
 463   // tmp is a temporary register, if none is available use noreg
 464   void jC2 (Register tmp, Label& L);
 465   void jnC2(Register tmp, Label& L);
 466 
 467   // Pop ST (ffree & fincstp combined)
 468   void fpop();
 469 
 470   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 471   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 472   void load_float(Address src);
 473 
 474   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 475   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 476   void store_float(Address dst);
 477 
 478   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 479   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 480   void load_double(Address src);
 481 
 482   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 483   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 484   void store_double(Address dst);
 485 
 486   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 487   void push_fTOS();
 488 
 489   // pops double TOS element from CPU stack and pushes on FPU stack
 490   void pop_fTOS();
 491 
 492   void empty_FPU_stack();
 493 
 494   void push_IU_state();
 495   void pop_IU_state();
 496 
 497   void push_FPU_state();
 498   void pop_FPU_state();
 499 
 500   void push_CPU_state();
 501   void pop_CPU_state();
 502 
 503   // Round up to a power of two
 504   void round_to(Register reg, int modulus);
 505 
 506   // Callee saved registers handling
 507   void push_callee_saved_registers();
 508   void pop_callee_saved_registers();
 509 
 510   // allocation
 511   void eden_allocate(
 512     Register thread,                   // Current thread
 513     Register obj,                      // result: pointer to object after successful allocation
 514     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 515     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 516     Register t1,                       // temp register
 517     Label&   slow_case                 // continuation point if fast allocation fails
 518   );
 519   void tlab_allocate(
 520     Register thread,                   // Current thread
 521     Register obj,                      // result: pointer to object after successful allocation
 522     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 523     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 524     Register t1,                       // temp register
 525     Register t2,                       // temp register
 526     Label&   slow_case                 // continuation point if fast allocation fails
 527   );
 528   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 529 
 530   // interface method calling
 531   void lookup_interface_method(Register recv_klass,
 532                                Register intf_klass,
 533                                RegisterOrConstant itable_index,
 534                                Register method_result,
 535                                Register scan_temp,
 536                                Label& no_such_interface,
 537                                bool return_method = true);
 538 
 539   // virtual method calling
 540   void lookup_virtual_method(Register recv_klass,
 541                              RegisterOrConstant vtable_index,
 542                              Register method_result);
 543 
 544   // Test sub_klass against super_klass, with fast and slow paths.
 545 
 546   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 547   // One of the three labels can be NULL, meaning take the fall-through.
 548   // If super_check_offset is -1, the value is loaded up from super_klass.
 549   // No registers are killed, except temp_reg.
 550   void check_klass_subtype_fast_path(Register sub_klass,
 551                                      Register super_klass,
 552                                      Register temp_reg,
 553                                      Label* L_success,
 554                                      Label* L_failure,
 555                                      Label* L_slow_path,
 556                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 557 
 558   // The rest of the type check; must be wired to a corresponding fast path.
 559   // It does not repeat the fast path logic, so don't use it standalone.
 560   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 561   // Updates the sub's secondary super cache as necessary.
 562   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 563   void check_klass_subtype_slow_path(Register sub_klass,
 564                                      Register super_klass,
 565                                      Register temp_reg,
 566                                      Register temp2_reg,
 567                                      Label* L_success,
 568                                      Label* L_failure,
 569                                      bool set_cond_codes = false);
 570 
 571   // Simplified, combined version, good for typical uses.
 572   // Falls through on failure.
 573   void check_klass_subtype(Register sub_klass,
 574                            Register super_klass,
 575                            Register temp_reg,
 576                            Label& L_success);
 577 
 578   // method handles (JSR 292)
 579   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 580 
 581   //----
 582   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 583 
 584   // Debugging
 585 
 586   // only if +VerifyOops
 587   // TODO: Make these macros with file and line like sparc version!
 588   void verify_oop(Register reg, const char* s = "broken oop");
 589   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 590 
 591   // TODO: verify method and klass metadata (compare against vptr?)
 592   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 593   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 594 
 595 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 596 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 597 
 598   // only if +VerifyFPU
 599   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 600 
 601   // Verify or restore cpu control state after JNI call
 602   void restore_cpu_control_state_after_jni();
 603 
 604   // prints msg, dumps registers and stops execution
 605   void stop(const char* msg);
 606 
 607   // prints msg and continues
 608   void warn(const char* msg);
 609 
 610   // dumps registers and other state
 611   void print_state();
 612 
 613   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 614   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 615   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 616   static void print_state64(int64_t pc, int64_t regs[]);
 617 
 618   void os_breakpoint();
 619 
 620   void untested()                                { stop("untested"); }
 621 
 622   void unimplemented(const char* what = "");
 623 
 624   void should_not_reach_here()                   { stop("should not reach here"); }
 625 
 626   void print_CPU_state();
 627 
 628   // Stack overflow checking
 629   void bang_stack_with_offset(int offset) {
 630     // stack grows down, caller passes positive offset
 631     assert(offset > 0, "must bang with negative offset");
 632     movl(Address(rsp, (-offset)), rax);
 633   }
 634 
 635   // Writes to stack successive pages until offset reached to check for
 636   // stack overflow + shadow pages.  Also, clobbers tmp
 637   void bang_stack_size(Register size, Register tmp);
 638 
 639   // Check for reserved stack access in method being exited (for JIT)
 640   void reserved_stack_check();
 641 
 642   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 643                                                 Register tmp,
 644                                                 int offset);
 645 
 646   // Support for serializing memory accesses between threads
 647   void serialize_memory(Register thread, Register tmp);
 648 
 649   // If thread_reg is != noreg the code assumes the register passed contains
 650   // the thread (required on 64 bit).
 651   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 652 
 653   void verify_tlab();
 654 
 655   // Biased locking support
 656   // lock_reg and obj_reg must be loaded up with the appropriate values.
 657   // swap_reg must be rax, and is killed.
 658   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 659   // be killed; if not supplied, push/pop will be used internally to
 660   // allocate a temporary (inefficient, avoid if possible).
 661   // Optional slow case is for implementations (interpreter and C1) which branch to
 662   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 663   // Returns offset of first potentially-faulting instruction for null
 664   // check info (currently consumed only by C1). If
 665   // swap_reg_contains_mark is true then returns -1 as it is assumed
 666   // the calling code has already passed any potential faults.
 667   int biased_locking_enter(Register lock_reg, Register obj_reg,
 668                            Register swap_reg, Register tmp_reg,
 669                            bool swap_reg_contains_mark,
 670                            Label& done, Label* slow_case = NULL,
 671                            BiasedLockingCounters* counters = NULL);
 672   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 673 #ifdef COMPILER2
 674   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 675   // See full desription in macroAssembler_x86.cpp.
 676   void fast_lock(Register obj, Register box, Register tmp,
 677                  Register scr, Register cx1, Register cx2,
 678                  BiasedLockingCounters* counters,
 679                  RTMLockingCounters* rtm_counters,
 680                  RTMLockingCounters* stack_rtm_counters,
 681                  Metadata* method_data,
 682                  bool use_rtm, bool profile_rtm);
 683   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 684 #if INCLUDE_RTM_OPT
 685   void rtm_counters_update(Register abort_status, Register rtm_counters);
 686   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 687   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 688                                    RTMLockingCounters* rtm_counters,
 689                                    Metadata* method_data);
 690   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 691                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 692   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 693   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 694   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 695                          Register retry_on_abort_count,
 696                          RTMLockingCounters* stack_rtm_counters,
 697                          Metadata* method_data, bool profile_rtm,
 698                          Label& DONE_LABEL, Label& IsInflated);
 699   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 700                             Register scr, Register retry_on_busy_count,
 701                             Register retry_on_abort_count,
 702                             RTMLockingCounters* rtm_counters,
 703                             Metadata* method_data, bool profile_rtm,
 704                             Label& DONE_LABEL);
 705 #endif
 706 #endif
 707 
 708   Condition negate_condition(Condition cond);
 709 
 710   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 711   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 712   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 713   // here in MacroAssembler. The major exception to this rule is call
 714 
 715   // Arithmetics
 716 
 717 
 718   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 719   void addptr(Address dst, Register src);
 720 
 721   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 722   void addptr(Register dst, int32_t src);
 723   void addptr(Register dst, Register src);
 724   void addptr(Register dst, RegisterOrConstant src) {
 725     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 726     else                   addptr(dst,       src.as_register());
 727   }
 728 
 729   void andptr(Register dst, int32_t src);
 730   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 731 
 732   void cmp8(AddressLiteral src1, int imm);
 733 
 734   // renamed to drag out the casting of address to int32_t/intptr_t
 735   void cmp32(Register src1, int32_t imm);
 736 
 737   void cmp32(AddressLiteral src1, int32_t imm);
 738   // compare reg - mem, or reg - &mem
 739   void cmp32(Register src1, AddressLiteral src2);
 740 
 741   void cmp32(Register src1, Address src2);
 742 
 743 #ifndef _LP64
 744   void cmpklass(Address dst, Metadata* obj);
 745   void cmpklass(Register dst, Metadata* obj);
 746   void cmpoop(Address dst, jobject obj);
 747   void cmpoop_raw(Address dst, jobject obj);
 748 #endif // _LP64
 749 
 750   void cmpoop(Register src1, Register src2);
 751   void cmpoop(Register src1, Address src2);
 752   void cmpoop(Register dst, jobject obj);
 753   void cmpoop_raw(Register dst, jobject obj);
 754 
 755   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 756   void cmpptr(Address src1, AddressLiteral src2);
 757 
 758   void cmpptr(Register src1, AddressLiteral src2);
 759 
 760   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 761   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 762   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 763 
 764   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 765   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 766 
 767   // cmp64 to avoild hiding cmpq
 768   void cmp64(Register src1, AddressLiteral src);
 769 
 770   void cmpxchgptr(Register reg, Address adr);
 771 
 772   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 773 
 774 
 775   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 776   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 777 
 778 
 779   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 780 
 781   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 782 
 783   void shlptr(Register dst, int32_t shift);
 784   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 785 
 786   void shrptr(Register dst, int32_t shift);
 787   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 788 
 789   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 790   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 791 
 792   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 793 
 794   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 795   void subptr(Register dst, int32_t src);
 796   // Force generation of a 4 byte immediate value even if it fits into 8bit
 797   void subptr_imm32(Register dst, int32_t src);
 798   void subptr(Register dst, Register src);
 799   void subptr(Register dst, RegisterOrConstant src) {
 800     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 801     else                   subptr(dst,       src.as_register());
 802   }
 803 
 804   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 805   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 806 
 807   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 808   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 809 
 810   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 811 
 812 
 813 
 814   // Helper functions for statistics gathering.
 815   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 816   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 817   // Unconditional atomic increment.
 818   void atomic_incl(Address counter_addr);
 819   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 820 #ifdef _LP64
 821   void atomic_incq(Address counter_addr);
 822   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 823 #endif
 824   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 825   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 826 
 827   void lea(Register dst, AddressLiteral adr);
 828   void lea(Address dst, AddressLiteral adr);
 829   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 830 
 831   void leal32(Register dst, Address src) { leal(dst, src); }
 832 
 833   // Import other testl() methods from the parent class or else
 834   // they will be hidden by the following overriding declaration.
 835   using Assembler::testl;
 836   void testl(Register dst, AddressLiteral src);
 837 
 838   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 839   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 840   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 841   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 842 
 843   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 844   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 845   void testptr(Register src1, Register src2);
 846 
 847   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 848   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 849 
 850   // Calls
 851 
 852   void call(Label& L, relocInfo::relocType rtype);
 853   void call(Register entry);
 854 
 855   // NOTE: this call transfers to the effective address of entry NOT
 856   // the address contained by entry. This is because this is more natural
 857   // for jumps/calls.
 858   void call(AddressLiteral entry);
 859 
 860   // Emit the CompiledIC call idiom
 861   void ic_call(address entry, jint method_index = 0);
 862 
 863   // Jumps
 864 
 865   // NOTE: these jumps tranfer to the effective address of dst NOT
 866   // the address contained by dst. This is because this is more natural
 867   // for jumps/calls.
 868   void jump(AddressLiteral dst);
 869   void jump_cc(Condition cc, AddressLiteral dst);
 870 
 871   // 32bit can do a case table jump in one instruction but we no longer allow the base
 872   // to be installed in the Address class. This jump will tranfers to the address
 873   // contained in the location described by entry (not the address of entry)
 874   void jump(ArrayAddress entry);
 875 
 876   // Floating
 877 
 878   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 879   void andpd(XMMRegister dst, AddressLiteral src);
 880   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 881 
 882   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 883   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 884   void andps(XMMRegister dst, AddressLiteral src);
 885 
 886   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 887   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 888   void comiss(XMMRegister dst, AddressLiteral src);
 889 
 890   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 891   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 892   void comisd(XMMRegister dst, AddressLiteral src);
 893 
 894   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 895   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 896 
 897   void fldcw(Address src) { Assembler::fldcw(src); }
 898   void fldcw(AddressLiteral src);
 899 
 900   void fld_s(int index)   { Assembler::fld_s(index); }
 901   void fld_s(Address src) { Assembler::fld_s(src); }
 902   void fld_s(AddressLiteral src);
 903 
 904   void fld_d(Address src) { Assembler::fld_d(src); }
 905   void fld_d(AddressLiteral src);
 906 
 907   void fld_x(Address src) { Assembler::fld_x(src); }
 908   void fld_x(AddressLiteral src);
 909 
 910   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 911   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 912 
 913   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 914   void ldmxcsr(AddressLiteral src);
 915 
 916 #ifdef _LP64
 917  private:
 918   void sha256_AVX2_one_round_compute(
 919     Register  reg_old_h,
 920     Register  reg_a,
 921     Register  reg_b,
 922     Register  reg_c,
 923     Register  reg_d,
 924     Register  reg_e,
 925     Register  reg_f,
 926     Register  reg_g,
 927     Register  reg_h,
 928     int iter);
 929   void sha256_AVX2_four_rounds_compute_first(int start);
 930   void sha256_AVX2_four_rounds_compute_last(int start);
 931   void sha256_AVX2_one_round_and_sched(
 932         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 933         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 934         XMMRegister xmm_2,     /* ymm6 */
 935         XMMRegister xmm_3,     /* ymm7 */
 936         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 937         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 938         Register    reg_c,      /* edi */
 939         Register    reg_d,      /* esi */
 940         Register    reg_e,      /* r8d */
 941         Register    reg_f,      /* r9d */
 942         Register    reg_g,      /* r10d */
 943         Register    reg_h,      /* r11d */
 944         int iter);
 945 
 946   void addm(int disp, Register r1, Register r2);
 947 
 948  public:
 949   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 950                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 951                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 952                    bool multi_block, XMMRegister shuf_mask);
 953 #endif
 954 
 955 #ifdef _LP64
 956  private:
 957   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 958                                      Register e, Register f, Register g, Register h, int iteration);
 959 
 960   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 961                                           Register a, Register b, Register c, Register d, Register e, Register f,
 962                                           Register g, Register h, int iteration);
 963 
 964   void addmq(int disp, Register r1, Register r2);
 965  public:
 966   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 967                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 968                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 969                    XMMRegister shuf_mask);
 970 #endif
 971 
 972   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 973                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 974                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 975                  bool multi_block);
 976 
 977 #ifdef _LP64
 978   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 979                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 980                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 981                    bool multi_block, XMMRegister shuf_mask);
 982 #else
 983   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 984                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 985                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 986                    bool multi_block);
 987 #endif
 988 
 989   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 990                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 991                 Register rax, Register rcx, Register rdx, Register tmp);
 992 
 993 #ifdef _LP64
 994   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 995                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 996                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
 997 
 998   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 999                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1000                   Register rax, Register rcx, Register rdx, Register r11);
1001 
1002   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1003                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1004                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1005 
1006   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1007                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1008                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1009                 Register tmp3, Register tmp4);
1010 
1011   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1012                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1013                 Register rax, Register rcx, Register rdx, Register tmp1,
1014                 Register tmp2, Register tmp3, Register tmp4);
1015   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1016                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1017                 Register rax, Register rcx, Register rdx, Register tmp1,
1018                 Register tmp2, Register tmp3, Register tmp4);
1019 #else
1020   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1021                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1022                 Register rax, Register rcx, Register rdx, Register tmp1);
1023 
1024   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1025                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1026                 Register rax, Register rcx, Register rdx, Register tmp);
1027 
1028   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1029                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1030                 Register rdx, Register tmp);
1031 
1032   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1033                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1034                 Register rax, Register rbx, Register rdx);
1035 
1036   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1037                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1038                 Register rax, Register rcx, Register rdx, Register tmp);
1039 
1040   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1041                         Register edx, Register ebx, Register esi, Register edi,
1042                         Register ebp, Register esp);
1043 
1044   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1045                          Register esi, Register edi, Register ebp, Register esp);
1046 
1047   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1048                         Register edx, Register ebx, Register esi, Register edi,
1049                         Register ebp, Register esp);
1050 
1051   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1052                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1053                 Register rax, Register rcx, Register rdx, Register tmp);
1054 #endif
1055 
1056   void increase_precision();
1057   void restore_precision();
1058 
1059 private:
1060 
1061   // these are private because users should be doing movflt/movdbl
1062 
1063   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1064   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1065   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1066   void movss(XMMRegister dst, AddressLiteral src);
1067 
1068   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1069   void movlpd(XMMRegister dst, AddressLiteral src);
1070 
1071 public:
1072 
1073   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1074   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1075   void addsd(XMMRegister dst, AddressLiteral src);
1076 
1077   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1078   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1079   void addss(XMMRegister dst, AddressLiteral src);
1080 
1081   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1082   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1083   void addpd(XMMRegister dst, AddressLiteral src);
1084 
1085   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1086   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1087   void divsd(XMMRegister dst, AddressLiteral src);
1088 
1089   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1090   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1091   void divss(XMMRegister dst, AddressLiteral src);
1092 
1093   // Move Unaligned Double Quadword
1094   void movdqu(Address     dst, XMMRegister src);
1095   void movdqu(XMMRegister dst, Address src);
1096   void movdqu(XMMRegister dst, XMMRegister src);
1097   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1098   // AVX Unaligned forms
1099   void vmovdqu(Address     dst, XMMRegister src);
1100   void vmovdqu(XMMRegister dst, Address src);
1101   void vmovdqu(XMMRegister dst, XMMRegister src);
1102   void vmovdqu(XMMRegister dst, AddressLiteral src);
1103   void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1104   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1105   void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1106   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1107 
1108   // Move Aligned Double Quadword
1109   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1110   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1111   void movdqa(XMMRegister dst, AddressLiteral src);
1112 
1113   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1114   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1115   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1116   void movsd(XMMRegister dst, AddressLiteral src);
1117 
1118   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1119   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1120   void mulpd(XMMRegister dst, AddressLiteral src);
1121 
1122   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1123   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1124   void mulsd(XMMRegister dst, AddressLiteral src);
1125 
1126   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1127   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1128   void mulss(XMMRegister dst, AddressLiteral src);
1129 
1130   // Carry-Less Multiplication Quadword
1131   void pclmulldq(XMMRegister dst, XMMRegister src) {
1132     // 0x00 - multiply lower 64 bits [0:63]
1133     Assembler::pclmulqdq(dst, src, 0x00);
1134   }
1135   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1136     // 0x11 - multiply upper 64 bits [64:127]
1137     Assembler::pclmulqdq(dst, src, 0x11);
1138   }
1139 
1140   void pcmpeqb(XMMRegister dst, XMMRegister src);
1141   void pcmpeqw(XMMRegister dst, XMMRegister src);
1142 
1143   void pcmpestri(XMMRegister dst, Address src, int imm8);
1144   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1145 
1146   void pmovzxbw(XMMRegister dst, XMMRegister src);
1147   void pmovzxbw(XMMRegister dst, Address src);
1148 
1149   void pmovmskb(Register dst, XMMRegister src);
1150 
1151   void ptest(XMMRegister dst, XMMRegister src);
1152 
1153   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1154   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1155   void sqrtsd(XMMRegister dst, AddressLiteral src);
1156 
1157   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1158   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1159   void sqrtss(XMMRegister dst, AddressLiteral src);
1160 
1161   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1162   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1163   void subsd(XMMRegister dst, AddressLiteral src);
1164 
1165   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1166   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1167   void subss(XMMRegister dst, AddressLiteral src);
1168 
1169   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1170   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1171   void ucomiss(XMMRegister dst, AddressLiteral src);
1172 
1173   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1174   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1175   void ucomisd(XMMRegister dst, AddressLiteral src);
1176 
1177   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1178   void xorpd(XMMRegister dst, XMMRegister src);
1179   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1180   void xorpd(XMMRegister dst, AddressLiteral src);
1181 
1182   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1183   void xorps(XMMRegister dst, XMMRegister src);
1184   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1185   void xorps(XMMRegister dst, AddressLiteral src);
1186 
1187   // Shuffle Bytes
1188   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1189   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1190   void pshufb(XMMRegister dst, AddressLiteral src);
1191   // AVX 3-operands instructions
1192 
1193   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1194   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1195   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1196 
1197   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1198   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1199   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1200 
1201   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1202   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1203 
1204   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1205   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1206 
1207   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1208   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1209 
1210   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1211   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1212   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1213 
1214   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1215   void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1216 
1217   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1218 
1219   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1220 
1221   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1222   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1223 
1224   void vpmovmskb(Register dst, XMMRegister src);
1225 
1226   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1227   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1228 
1229   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1230   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1231 
1232   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1233   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1234 
1235   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1236   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1237 
1238   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1239   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1240 
1241   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1242   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1243 
1244   void vptest(XMMRegister dst, XMMRegister src);
1245 
1246   void punpcklbw(XMMRegister dst, XMMRegister src);
1247   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1248 
1249   void pshufd(XMMRegister dst, Address src, int mode);
1250   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1251 
1252   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1253   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1254 
1255   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1256   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1257   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1258 
1259   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1260   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1261   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1262 
1263   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1264   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1265   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1266 
1267   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1268   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1269   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1270 
1271   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1272   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1273   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1274 
1275   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1276   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1277   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1278 
1279   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1280   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1281   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1282 
1283   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1284   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1285   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1286 
1287   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1288   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1289 
1290   // AVX Vector instructions
1291 
1292   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1293   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1294   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1295 
1296   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1297   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1298   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1299 
1300   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1301     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1302       Assembler::vpxor(dst, nds, src, vector_len);
1303     else
1304       Assembler::vxorpd(dst, nds, src, vector_len);
1305   }
1306   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1307     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1308       Assembler::vpxor(dst, nds, src, vector_len);
1309     else
1310       Assembler::vxorpd(dst, nds, src, vector_len);
1311   }
1312 
1313   // Simple version for AVX2 256bit vectors
1314   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1315   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1316 
1317   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1318     if (UseAVX > 2) {
1319       Assembler::vinserti32x4(dst, dst, src, imm8);
1320     } else if (UseAVX > 1) {
1321       // vinserti128 is available only in AVX2
1322       Assembler::vinserti128(dst, nds, src, imm8);
1323     } else {
1324       Assembler::vinsertf128(dst, nds, src, imm8);
1325     }
1326   }
1327 
1328   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1329     if (UseAVX > 2) {
1330       Assembler::vinserti32x4(dst, dst, src, imm8);
1331     } else if (UseAVX > 1) {
1332       // vinserti128 is available only in AVX2
1333       Assembler::vinserti128(dst, nds, src, imm8);
1334     } else {
1335       Assembler::vinsertf128(dst, nds, src, imm8);
1336     }
1337   }
1338 
1339   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1340     if (UseAVX > 2) {
1341       Assembler::vextracti32x4(dst, src, imm8);
1342     } else if (UseAVX > 1) {
1343       // vextracti128 is available only in AVX2
1344       Assembler::vextracti128(dst, src, imm8);
1345     } else {
1346       Assembler::vextractf128(dst, src, imm8);
1347     }
1348   }
1349 
1350   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1351     if (UseAVX > 2) {
1352       Assembler::vextracti32x4(dst, src, imm8);
1353     } else if (UseAVX > 1) {
1354       // vextracti128 is available only in AVX2
1355       Assembler::vextracti128(dst, src, imm8);
1356     } else {
1357       Assembler::vextractf128(dst, src, imm8);
1358     }
1359   }
1360 
1361   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1362   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1363     vinserti128(dst, dst, src, 1);
1364   }
1365   void vinserti128_high(XMMRegister dst, Address src) {
1366     vinserti128(dst, dst, src, 1);
1367   }
1368   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1369     vextracti128(dst, src, 1);
1370   }
1371   void vextracti128_high(Address dst, XMMRegister src) {
1372     vextracti128(dst, src, 1);
1373   }
1374 
1375   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1376     if (UseAVX > 2) {
1377       Assembler::vinsertf32x4(dst, dst, src, 1);
1378     } else {
1379       Assembler::vinsertf128(dst, dst, src, 1);
1380     }
1381   }
1382 
1383   void vinsertf128_high(XMMRegister dst, Address src) {
1384     if (UseAVX > 2) {
1385       Assembler::vinsertf32x4(dst, dst, src, 1);
1386     } else {
1387       Assembler::vinsertf128(dst, dst, src, 1);
1388     }
1389   }
1390 
1391   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1392     if (UseAVX > 2) {
1393       Assembler::vextractf32x4(dst, src, 1);
1394     } else {
1395       Assembler::vextractf128(dst, src, 1);
1396     }
1397   }
1398 
1399   void vextractf128_high(Address dst, XMMRegister src) {
1400     if (UseAVX > 2) {
1401       Assembler::vextractf32x4(dst, src, 1);
1402     } else {
1403       Assembler::vextractf128(dst, src, 1);
1404     }
1405   }
1406 
1407   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1408   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1409     Assembler::vinserti64x4(dst, dst, src, 1);
1410   }
1411   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1412     Assembler::vinsertf64x4(dst, dst, src, 1);
1413   }
1414   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1415     Assembler::vextracti64x4(dst, src, 1);
1416   }
1417   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1418     Assembler::vextractf64x4(dst, src, 1);
1419   }
1420   void vextractf64x4_high(Address dst, XMMRegister src) {
1421     Assembler::vextractf64x4(dst, src, 1);
1422   }
1423   void vinsertf64x4_high(XMMRegister dst, Address src) {
1424     Assembler::vinsertf64x4(dst, dst, src, 1);
1425   }
1426 
1427   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1428   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1429     vinserti128(dst, dst, src, 0);
1430   }
1431   void vinserti128_low(XMMRegister dst, Address src) {
1432     vinserti128(dst, dst, src, 0);
1433   }
1434   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1435     vextracti128(dst, src, 0);
1436   }
1437   void vextracti128_low(Address dst, XMMRegister src) {
1438     vextracti128(dst, src, 0);
1439   }
1440 
1441   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1442     if (UseAVX > 2) {
1443       Assembler::vinsertf32x4(dst, dst, src, 0);
1444     } else {
1445       Assembler::vinsertf128(dst, dst, src, 0);
1446     }
1447   }
1448 
1449   void vinsertf128_low(XMMRegister dst, Address src) {
1450     if (UseAVX > 2) {
1451       Assembler::vinsertf32x4(dst, dst, src, 0);
1452     } else {
1453       Assembler::vinsertf128(dst, dst, src, 0);
1454     }
1455   }
1456 
1457   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1458     if (UseAVX > 2) {
1459       Assembler::vextractf32x4(dst, src, 0);
1460     } else {
1461       Assembler::vextractf128(dst, src, 0);
1462     }
1463   }
1464 
1465   void vextractf128_low(Address dst, XMMRegister src) {
1466     if (UseAVX > 2) {
1467       Assembler::vextractf32x4(dst, src, 0);
1468     } else {
1469       Assembler::vextractf128(dst, src, 0);
1470     }
1471   }
1472 
1473   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1474   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1475     Assembler::vinserti64x4(dst, dst, src, 0);
1476   }
1477   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1478     Assembler::vinsertf64x4(dst, dst, src, 0);
1479   }
1480   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1481     Assembler::vextracti64x4(dst, src, 0);
1482   }
1483   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1484     Assembler::vextractf64x4(dst, src, 0);
1485   }
1486   void vextractf64x4_low(Address dst, XMMRegister src) {
1487     Assembler::vextractf64x4(dst, src, 0);
1488   }
1489   void vinsertf64x4_low(XMMRegister dst, Address src) {
1490     Assembler::vinsertf64x4(dst, dst, src, 0);
1491   }
1492 
1493   // Carry-Less Multiplication Quadword
1494   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1495     // 0x00 - multiply lower 64 bits [0:63]
1496     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1497   }
1498   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1499     // 0x11 - multiply upper 64 bits [64:127]
1500     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1501   }
1502   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1503     // 0x00 - multiply lower 64 bits [0:63]
1504     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1505   }
1506   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1507     // 0x11 - multiply upper 64 bits [64:127]
1508     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1509   }
1510 
1511   // Data
1512 
1513   void cmov32( Condition cc, Register dst, Address  src);
1514   void cmov32( Condition cc, Register dst, Register src);
1515 
1516   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1517 
1518   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1519   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1520 
1521   void movoop(Register dst, jobject obj);
1522   void movoop(Address dst, jobject obj);
1523 
1524   void mov_metadata(Register dst, Metadata* obj);
1525   void mov_metadata(Address dst, Metadata* obj);
1526 
1527   void movptr(ArrayAddress dst, Register src);
1528   // can this do an lea?
1529   void movptr(Register dst, ArrayAddress src);
1530 
1531   void movptr(Register dst, Address src);
1532 
1533 #ifdef _LP64
1534   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1535 #else
1536   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1537 #endif
1538 
1539   void movptr(Register dst, intptr_t src);
1540   void movptr(Register dst, Register src);
1541   void movptr(Address dst, intptr_t src);
1542 
1543   void movptr(Address dst, Register src);
1544 
1545   void movptr(Register dst, RegisterOrConstant src) {
1546     if (src.is_constant()) movptr(dst, src.as_constant());
1547     else                   movptr(dst, src.as_register());
1548   }
1549 
1550 #ifdef _LP64
1551   // Generally the next two are only used for moving NULL
1552   // Although there are situations in initializing the mark word where
1553   // they could be used. They are dangerous.
1554 
1555   // They only exist on LP64 so that int32_t and intptr_t are not the same
1556   // and we have ambiguous declarations.
1557 
1558   void movptr(Address dst, int32_t imm32);
1559   void movptr(Register dst, int32_t imm32);
1560 #endif // _LP64
1561 
1562   // to avoid hiding movl
1563   void mov32(AddressLiteral dst, Register src);
1564   void mov32(Register dst, AddressLiteral src);
1565 
1566   // to avoid hiding movb
1567   void movbyte(ArrayAddress dst, int src);
1568 
1569   // Import other mov() methods from the parent class or else
1570   // they will be hidden by the following overriding declaration.
1571   using Assembler::movdl;
1572   using Assembler::movq;
1573   void movdl(XMMRegister dst, AddressLiteral src);
1574   void movq(XMMRegister dst, AddressLiteral src);
1575 
1576   // Can push value or effective address
1577   void pushptr(AddressLiteral src);
1578 
1579   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1580   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1581 
1582   void pushoop(jobject obj);
1583   void pushklass(Metadata* obj);
1584 
1585   // sign extend as need a l to ptr sized element
1586   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1587   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1588 
1589   // C2 compiled method's prolog code.
1590   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1591 
1592   // clear memory of size 'cnt' qwords, starting at 'base';
1593   // if 'is_large' is set, do not try to produce short loop
1594   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1595 
1596   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1597   void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1598 
1599 #ifdef COMPILER2
1600   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1601                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1602 
1603   // IndexOf strings.
1604   // Small strings are loaded through stack if they cross page boundary.
1605   void string_indexof(Register str1, Register str2,
1606                       Register cnt1, Register cnt2,
1607                       int int_cnt2,  Register result,
1608                       XMMRegister vec, Register tmp,
1609                       int ae);
1610 
1611   // IndexOf for constant substrings with size >= 8 elements
1612   // which don't need to be loaded through stack.
1613   void string_indexofC8(Register str1, Register str2,
1614                       Register cnt1, Register cnt2,
1615                       int int_cnt2,  Register result,
1616                       XMMRegister vec, Register tmp,
1617                       int ae);
1618 
1619     // Smallest code: we don't need to load through stack,
1620     // check string tail.
1621 
1622   // helper function for string_compare
1623   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1624                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1625                           Address::ScaleFactor scale2, Register index, int ae);
1626   // Compare strings.
1627   void string_compare(Register str1, Register str2,
1628                       Register cnt1, Register cnt2, Register result,
1629                       XMMRegister vec1, int ae);
1630 
1631   // Search for Non-ASCII character (Negative byte value) in a byte array,
1632   // return true if it has any and false otherwise.
1633   void has_negatives(Register ary1, Register len,
1634                      Register result, Register tmp1,
1635                      XMMRegister vec1, XMMRegister vec2);
1636 
1637   // Compare char[] or byte[] arrays.
1638   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1639                      Register limit, Register result, Register chr,
1640                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1641 
1642 #endif
1643 
1644   // Fill primitive arrays
1645   void generate_fill(BasicType t, bool aligned,
1646                      Register to, Register value, Register count,
1647                      Register rtmp, XMMRegister xtmp);
1648 
1649   void encode_iso_array(Register src, Register dst, Register len,
1650                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1651                         XMMRegister tmp4, Register tmp5, Register result);
1652 
1653 #ifdef _LP64
1654   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1655   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1656                              Register y, Register y_idx, Register z,
1657                              Register carry, Register product,
1658                              Register idx, Register kdx);
1659   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1660                               Register yz_idx, Register idx,
1661                               Register carry, Register product, int offset);
1662   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1663                                     Register carry, Register carry2,
1664                                     Register idx, Register jdx,
1665                                     Register yz_idx1, Register yz_idx2,
1666                                     Register tmp, Register tmp3, Register tmp4);
1667   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1668                                Register yz_idx, Register idx, Register jdx,
1669                                Register carry, Register product,
1670                                Register carry2);
1671   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1672                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1673   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1674                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1675   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1676                             Register tmp2);
1677   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1678                        Register rdxReg, Register raxReg);
1679   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1680   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1681                        Register tmp3, Register tmp4);
1682   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1683                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1684 
1685   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1686                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1687                Register raxReg);
1688   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1689                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1690                Register raxReg);
1691   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1692                            Register result, Register tmp1, Register tmp2,
1693                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1694 #endif
1695 
1696   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1697   void update_byte_crc32(Register crc, Register val, Register table);
1698   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1699   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1700   // Note on a naming convention:
1701   // Prefix w = register only used on a Westmere+ architecture
1702   // Prefix n = register only used on a Nehalem architecture
1703 #ifdef _LP64
1704   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1705                        Register tmp1, Register tmp2, Register tmp3);
1706 #else
1707   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1708                        Register tmp1, Register tmp2, Register tmp3,
1709                        XMMRegister xtmp1, XMMRegister xtmp2);
1710 #endif
1711   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1712                         Register in_out,
1713                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1714                         XMMRegister w_xtmp2,
1715                         Register tmp1,
1716                         Register n_tmp2, Register n_tmp3);
1717   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1718                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1719                        Register tmp1, Register tmp2,
1720                        Register n_tmp3);
1721   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1722                          Register in_out1, Register in_out2, Register in_out3,
1723                          Register tmp1, Register tmp2, Register tmp3,
1724                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1725                          Register tmp4, Register tmp5,
1726                          Register n_tmp6);
1727   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1728                             Register tmp1, Register tmp2, Register tmp3,
1729                             Register tmp4, Register tmp5, Register tmp6,
1730                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1731                             bool is_pclmulqdq_supported);
1732   // Fold 128-bit data chunk
1733   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1734   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1735   // Fold 8-bit data
1736   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1737   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1738   void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1739 
1740   // Compress char[] array to byte[].
1741   void char_array_compress(Register src, Register dst, Register len,
1742                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1743                            XMMRegister tmp4, Register tmp5, Register result);
1744 
1745   // Inflate byte[] array to char[].
1746   void byte_array_inflate(Register src, Register dst, Register len,
1747                           XMMRegister tmp1, Register tmp2);
1748 
1749 };
1750 
1751 /**
1752  * class SkipIfEqual:
1753  *
1754  * Instantiating this class will result in assembly code being output that will
1755  * jump around any code emitted between the creation of the instance and it's
1756  * automatic destruction at the end of a scope block, depending on the value of
1757  * the flag passed to the constructor, which will be checked at run-time.
1758  */
1759 class SkipIfEqual {
1760  private:
1761   MacroAssembler* _masm;
1762   Label _label;
1763 
1764  public:
1765    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1766    ~SkipIfEqual();
1767 };
1768 
1769 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP