1 //
   2 // Copyright (c) 2003, 2017, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // AMD64 Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 
  32 register %{
  33 //----------Architecture Description Register Definitions----------------------
  34 // General Registers
  35 // "reg_def"  name ( register save type, C convention save type,
  36 //                   ideal register type, encoding );
  37 // Register Save Types:
  38 //
  39 // NS  = No-Save:       The register allocator assumes that these registers
  40 //                      can be used without saving upon entry to the method, &
  41 //                      that they do not need to be saved at call sites.
  42 //
  43 // SOC = Save-On-Call:  The register allocator assumes that these registers
  44 //                      can be used without saving upon entry to the method,
  45 //                      but that they must be saved at call sites.
  46 //
  47 // SOE = Save-On-Entry: The register allocator assumes that these registers
  48 //                      must be saved before using them upon entry to the
  49 //                      method, but they do not need to be saved at call
  50 //                      sites.
  51 //
  52 // AS  = Always-Save:   The register allocator assumes that these registers
  53 //                      must be saved before using them upon entry to the
  54 //                      method, & that they must be saved at call sites.
  55 //
  56 // Ideal Register Type is used to determine how to save & restore a
  57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  59 //
  60 // The encoding number is the actual bit-pattern placed into the opcodes.
  61 
  62 // General Registers
  63 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when
  64 // used as byte registers)
  65 
  66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
  67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
  68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
  69 
  70 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
  71 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
  72 
  73 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
  74 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
  75 
  76 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
  77 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
  78 
  79 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
  80 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
  81 
  82 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
  83 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
  84 
  85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
  86 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
  87 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
  88 
  89 #ifdef _WIN64
  90 
  91 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
  92 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
  93 
  94 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
  95 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
  96 
  97 #else
  98 
  99 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
 100 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
 101 
 102 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
 103 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
 104 
 105 #endif
 106 
 107 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
 108 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
 109 
 110 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
 111 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
 112 
 113 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
 115 
 116 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
 118 
 119 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
 121 
 122 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
 124 
 125 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
 127 
 128 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
 130 
 131 
 132 // Floating Point Registers
 133 
 134 // Specify priority of register selection within phases of register
 135 // allocation.  Highest priority is first.  A useful heuristic is to
 136 // give registers a low priority when they are required by machine
 137 // instructions, like EAX and EDX on I486, and choose no-save registers
 138 // before save-on-call, & save-on-call before save-on-entry.  Registers
 139 // which participate in fixed calling sequences should come last.
 140 // Registers which are used as pairs must fall on an even boundary.
 141 
 142 alloc_class chunk0(R10,         R10_H,
 143                    R11,         R11_H,
 144                    R8,          R8_H,
 145                    R9,          R9_H,
 146                    R12,         R12_H,
 147                    RCX,         RCX_H,
 148                    RBX,         RBX_H,
 149                    RDI,         RDI_H,
 150                    RDX,         RDX_H,
 151                    RSI,         RSI_H,
 152                    RAX,         RAX_H,
 153                    RBP,         RBP_H,
 154                    R13,         R13_H,
 155                    R14,         R14_H,
 156                    R15,         R15_H,
 157                    RSP,         RSP_H);
 158 
 159 
 160 //----------Architecture Description Register Classes--------------------------
 161 // Several register classes are automatically defined based upon information in
 162 // this architecture description.
 163 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
 164 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )
 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 167 //
 168 
 169 // Empty register class.
 170 reg_class no_reg();
 171 
 172 // Class for all pointer registers (including RSP and RBP)
 173 reg_class any_reg_with_rbp(RAX, RAX_H,
 174                            RDX, RDX_H,
 175                            RBP, RBP_H,
 176                            RDI, RDI_H,
 177                            RSI, RSI_H,
 178                            RCX, RCX_H,
 179                            RBX, RBX_H,
 180                            RSP, RSP_H,
 181                            R8,  R8_H,
 182                            R9,  R9_H,
 183                            R10, R10_H,
 184                            R11, R11_H,
 185                            R12, R12_H,
 186                            R13, R13_H,
 187                            R14, R14_H,
 188                            R15, R15_H);
 189 
 190 // Class for all pointer registers (including RSP, but excluding RBP)
 191 reg_class any_reg_no_rbp(RAX, RAX_H,
 192                          RDX, RDX_H,
 193                          RDI, RDI_H,
 194                          RSI, RSI_H,
 195                          RCX, RCX_H,
 196                          RBX, RBX_H,
 197                          RSP, RSP_H,
 198                          R8,  R8_H,
 199                          R9,  R9_H,
 200                          R10, R10_H,
 201                          R11, R11_H,
 202                          R12, R12_H,
 203                          R13, R13_H,
 204                          R14, R14_H,
 205                          R15, R15_H);
 206 
 207 // Dynamic register class that selects at runtime between register classes
 208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
 209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
 210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
 211 
 212 // Class for all pointer registers (excluding RSP)
 213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
 214                            RDX, RDX_H,
 215                            RBP, RBP_H,
 216                            RDI, RDI_H,
 217                            RSI, RSI_H,
 218                            RCX, RCX_H,
 219                            RBX, RBX_H,
 220                            R8,  R8_H,
 221                            R9,  R9_H,
 222                            R10, R10_H,
 223                            R11, R11_H,
 224                            R13, R13_H,
 225                            R14, R14_H);
 226 
 227 // Class for all pointer registers (excluding RSP and RBP)
 228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
 229                          RDX, RDX_H,
 230                          RDI, RDI_H,
 231                          RSI, RSI_H,
 232                          RCX, RCX_H,
 233                          RBX, RBX_H,
 234                          R8,  R8_H,
 235                          R9,  R9_H,
 236                          R10, R10_H,
 237                          R11, R11_H,
 238                          R13, R13_H,
 239                          R14, R14_H);
 240 
 241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
 242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
 243 
 244 // Class for all pointer registers (excluding RAX and RSP)
 245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
 246                                   RBP, RBP_H,
 247                                   RDI, RDI_H,
 248                                   RSI, RSI_H,
 249                                   RCX, RCX_H,
 250                                   RBX, RBX_H,
 251                                   R8,  R8_H,
 252                                   R9,  R9_H,
 253                                   R10, R10_H,
 254                                   R11, R11_H,
 255                                   R13, R13_H,
 256                                   R14, R14_H);
 257 
 258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
 259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
 260                                 RDI, RDI_H,
 261                                 RSI, RSI_H,
 262                                 RCX, RCX_H,
 263                                 RBX, RBX_H,
 264                                 R8,  R8_H,
 265                                 R9,  R9_H,
 266                                 R10, R10_H,
 267                                 R11, R11_H,
 268                                 R13, R13_H,
 269                                 R14, R14_H);
 270 
 271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
 272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
 273 
 274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
 275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
 276                                       RBP, RBP_H,
 277                                       RDI, RDI_H,
 278                                       RSI, RSI_H,
 279                                       RCX, RCX_H,
 280                                       R8,  R8_H,
 281                                       R9,  R9_H,
 282                                       R10, R10_H,
 283                                       R11, R11_H,
 284                                       R13, R13_H,
 285                                       R14, R14_H);
 286 
 287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
 288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
 289                                     RDI, RDI_H,
 290                                     RSI, RSI_H,
 291                                     RCX, RCX_H,
 292                                     R8,  R8_H,
 293                                     R9,  R9_H,
 294                                     R10, R10_H,
 295                                     R11, R11_H,
 296                                     R13, R13_H,
 297                                     R14, R14_H);
 298 
 299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
 300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
 301 
 302 // Singleton class for RAX pointer register
 303 reg_class ptr_rax_reg(RAX, RAX_H);
 304 
 305 // Singleton class for RBX pointer register
 306 reg_class ptr_rbx_reg(RBX, RBX_H);
 307 
 308 // Singleton class for RSI pointer register
 309 reg_class ptr_rsi_reg(RSI, RSI_H);
 310 
 311 // Singleton class for RDI pointer register
 312 reg_class ptr_rdi_reg(RDI, RDI_H);
 313 
 314 // Singleton class for stack pointer
 315 reg_class ptr_rsp_reg(RSP, RSP_H);
 316 
 317 // Singleton class for TLS pointer
 318 reg_class ptr_r15_reg(R15, R15_H);
 319 
 320 // The registers which can be used for
 321 // a thread local safepoint poll
 322 // * R12 is reserved for heap base
 323 // * R13 cannot be encoded for addressing without an offset byte
 324 // * R15 is reserved for the JavaThread
 325 reg_class ptr_rex_reg(R8,  R8_H,
 326                       R9,  R9_H,
 327                       R10, R10_H,
 328                       R11, R11_H,
 329                       R14, R14_H);
 330 
 331 
 332 // Class for all long registers (excluding RSP)
 333 reg_class long_reg_with_rbp(RAX, RAX_H,
 334                             RDX, RDX_H,
 335                             RBP, RBP_H,
 336                             RDI, RDI_H,
 337                             RSI, RSI_H,
 338                             RCX, RCX_H,
 339                             RBX, RBX_H,
 340                             R8,  R8_H,
 341                             R9,  R9_H,
 342                             R10, R10_H,
 343                             R11, R11_H,
 344                             R13, R13_H,
 345                             R14, R14_H);
 346 
 347 // Class for all long registers (excluding RSP and RBP)
 348 reg_class long_reg_no_rbp(RAX, RAX_H,
 349                           RDX, RDX_H,
 350                           RDI, RDI_H,
 351                           RSI, RSI_H,
 352                           RCX, RCX_H,
 353                           RBX, RBX_H,
 354                           R8,  R8_H,
 355                           R9,  R9_H,
 356                           R10, R10_H,
 357                           R11, R11_H,
 358                           R13, R13_H,
 359                           R14, R14_H);
 360 
 361 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
 362 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
 363 
 364 // Class for all long registers (excluding RAX, RDX and RSP)
 365 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
 366                                        RDI, RDI_H,
 367                                        RSI, RSI_H,
 368                                        RCX, RCX_H,
 369                                        RBX, RBX_H,
 370                                        R8,  R8_H,
 371                                        R9,  R9_H,
 372                                        R10, R10_H,
 373                                        R11, R11_H,
 374                                        R13, R13_H,
 375                                        R14, R14_H);
 376 
 377 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
 378 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
 379                                      RSI, RSI_H,
 380                                      RCX, RCX_H,
 381                                      RBX, RBX_H,
 382                                      R8,  R8_H,
 383                                      R9,  R9_H,
 384                                      R10, R10_H,
 385                                      R11, R11_H,
 386                                      R13, R13_H,
 387                                      R14, R14_H);
 388 
 389 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
 390 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
 391 
 392 // Class for all long registers (excluding RCX and RSP)
 393 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
 394                                    RDI, RDI_H,
 395                                    RSI, RSI_H,
 396                                    RAX, RAX_H,
 397                                    RDX, RDX_H,
 398                                    RBX, RBX_H,
 399                                    R8,  R8_H,
 400                                    R9,  R9_H,
 401                                    R10, R10_H,
 402                                    R11, R11_H,
 403                                    R13, R13_H,
 404                                    R14, R14_H);
 405 
 406 // Class for all long registers (excluding RCX, RSP, and RBP)
 407 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
 408                                  RSI, RSI_H,
 409                                  RAX, RAX_H,
 410                                  RDX, RDX_H,
 411                                  RBX, RBX_H,
 412                                  R8,  R8_H,
 413                                  R9,  R9_H,
 414                                  R10, R10_H,
 415                                  R11, R11_H,
 416                                  R13, R13_H,
 417                                  R14, R14_H);
 418 
 419 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
 420 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
 421 
 422 // Singleton class for RAX long register
 423 reg_class long_rax_reg(RAX, RAX_H);
 424 
 425 // Singleton class for RCX long register
 426 reg_class long_rcx_reg(RCX, RCX_H);
 427 
 428 // Singleton class for RDX long register
 429 reg_class long_rdx_reg(RDX, RDX_H);
 430 
 431 // Class for all int registers (excluding RSP)
 432 reg_class int_reg_with_rbp(RAX,
 433                            RDX,
 434                            RBP,
 435                            RDI,
 436                            RSI,
 437                            RCX,
 438                            RBX,
 439                            R8,
 440                            R9,
 441                            R10,
 442                            R11,
 443                            R13,
 444                            R14);
 445 
 446 // Class for all int registers (excluding RSP and RBP)
 447 reg_class int_reg_no_rbp(RAX,
 448                          RDX,
 449                          RDI,
 450                          RSI,
 451                          RCX,
 452                          RBX,
 453                          R8,
 454                          R9,
 455                          R10,
 456                          R11,
 457                          R13,
 458                          R14);
 459 
 460 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
 461 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
 462 
 463 // Class for all int registers (excluding RCX and RSP)
 464 reg_class int_no_rcx_reg_with_rbp(RAX,
 465                                   RDX,
 466                                   RBP,
 467                                   RDI,
 468                                   RSI,
 469                                   RBX,
 470                                   R8,
 471                                   R9,
 472                                   R10,
 473                                   R11,
 474                                   R13,
 475                                   R14);
 476 
 477 // Class for all int registers (excluding RCX, RSP, and RBP)
 478 reg_class int_no_rcx_reg_no_rbp(RAX,
 479                                 RDX,
 480                                 RDI,
 481                                 RSI,
 482                                 RBX,
 483                                 R8,
 484                                 R9,
 485                                 R10,
 486                                 R11,
 487                                 R13,
 488                                 R14);
 489 
 490 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
 491 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
 492 
 493 // Class for all int registers (excluding RAX, RDX, and RSP)
 494 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
 495                                       RDI,
 496                                       RSI,
 497                                       RCX,
 498                                       RBX,
 499                                       R8,
 500                                       R9,
 501                                       R10,
 502                                       R11,
 503                                       R13,
 504                                       R14);
 505 
 506 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
 507 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
 508                                     RSI,
 509                                     RCX,
 510                                     RBX,
 511                                     R8,
 512                                     R9,
 513                                     R10,
 514                                     R11,
 515                                     R13,
 516                                     R14);
 517 
 518 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
 519 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
 520 
 521 // Singleton class for RAX int register
 522 reg_class int_rax_reg(RAX);
 523 
 524 // Singleton class for RBX int register
 525 reg_class int_rbx_reg(RBX);
 526 
 527 // Singleton class for RCX int register
 528 reg_class int_rcx_reg(RCX);
 529 
 530 // Singleton class for RCX int register
 531 reg_class int_rdx_reg(RDX);
 532 
 533 // Singleton class for RCX int register
 534 reg_class int_rdi_reg(RDI);
 535 
 536 // Singleton class for instruction pointer
 537 // reg_class ip_reg(RIP);
 538 
 539 %}
 540 
 541 source_hpp %{
 542 #if INCLUDE_ZGC
 543 #include "gc/z/zBarrierSetAssembler.hpp"
 544 #endif
 545 %}
 546 
 547 //----------SOURCE BLOCK-------------------------------------------------------
 548 // This is a block of C++ code which provides values, functions, and
 549 // definitions necessary in the rest of the architecture description
 550 source %{
 551 #define   RELOC_IMM64    Assembler::imm_operand
 552 #define   RELOC_DISP32   Assembler::disp32_operand
 553 
 554 #define __ _masm.
 555 
 556 static bool generate_vzeroupper(Compile* C) {
 557   return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false;  // Generate vzeroupper
 558 }
 559 
 560 static int clear_avx_size() {
 561   return generate_vzeroupper(Compile::current()) ? 3: 0;  // vzeroupper
 562 }
 563 
 564 // !!!!! Special hack to get all types of calls to specify the byte offset
 565 //       from the start of the call to the point where the return address
 566 //       will point.
 567 int MachCallStaticJavaNode::ret_addr_offset()
 568 {
 569   int offset = 5; // 5 bytes from start of call to where return address points
 570   offset += clear_avx_size();
 571   return offset;
 572 }
 573 
 574 int MachCallDynamicJavaNode::ret_addr_offset()
 575 {
 576   int offset = 15; // 15 bytes from start of call to where return address points
 577   offset += clear_avx_size();
 578   return offset;
 579 }
 580 
 581 int MachCallRuntimeNode::ret_addr_offset() {
 582   int offset = 13; // movq r10,#addr; callq (r10)
 583   offset += clear_avx_size();
 584   return offset;
 585 }
 586 
 587 // Indicate if the safepoint node needs the polling page as an input,
 588 // it does if the polling page is more than disp32 away.
 589 bool SafePointNode::needs_polling_address_input()
 590 {
 591   return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
 592 }
 593 
 594 //
 595 // Compute padding required for nodes which need alignment
 596 //
 597 
 598 // The address of the call instruction needs to be 4-byte aligned to
 599 // ensure that it does not span a cache line so that it can be patched.
 600 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 601 {
 602   current_offset += clear_avx_size(); // skip vzeroupper
 603   current_offset += 1; // skip call opcode byte
 604   return align_up(current_offset, alignment_required()) - current_offset;
 605 }
 606 
 607 // The address of the call instruction needs to be 4-byte aligned to
 608 // ensure that it does not span a cache line so that it can be patched.
 609 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 610 {
 611   current_offset += clear_avx_size(); // skip vzeroupper
 612   current_offset += 11; // skip movq instruction + call opcode byte
 613   return align_up(current_offset, alignment_required()) - current_offset;
 614 }
 615 
 616 // EMIT_RM()
 617 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 618   unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
 619   cbuf.insts()->emit_int8(c);
 620 }
 621 
 622 // EMIT_CC()
 623 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
 624   unsigned char c = (unsigned char) (f1 | f2);
 625   cbuf.insts()->emit_int8(c);
 626 }
 627 
 628 // EMIT_OPCODE()
 629 void emit_opcode(CodeBuffer &cbuf, int code) {
 630   cbuf.insts()->emit_int8((unsigned char) code);
 631 }
 632 
 633 // EMIT_OPCODE() w/ relocation information
 634 void emit_opcode(CodeBuffer &cbuf,
 635                  int code, relocInfo::relocType reloc, int offset, int format)
 636 {
 637   cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
 638   emit_opcode(cbuf, code);
 639 }
 640 
 641 // EMIT_D8()
 642 void emit_d8(CodeBuffer &cbuf, int d8) {
 643   cbuf.insts()->emit_int8((unsigned char) d8);
 644 }
 645 
 646 // EMIT_D16()
 647 void emit_d16(CodeBuffer &cbuf, int d16) {
 648   cbuf.insts()->emit_int16(d16);
 649 }
 650 
 651 // EMIT_D32()
 652 void emit_d32(CodeBuffer &cbuf, int d32) {
 653   cbuf.insts()->emit_int32(d32);
 654 }
 655 
 656 // EMIT_D64()
 657 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
 658   cbuf.insts()->emit_int64(d64);
 659 }
 660 
 661 // emit 32 bit value and construct relocation entry from relocInfo::relocType
 662 void emit_d32_reloc(CodeBuffer& cbuf,
 663                     int d32,
 664                     relocInfo::relocType reloc,
 665                     int format)
 666 {
 667   assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
 668   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 669   cbuf.insts()->emit_int32(d32);
 670 }
 671 
 672 // emit 32 bit value and construct relocation entry from RelocationHolder
 673 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
 674 #ifdef ASSERT
 675   if (rspec.reloc()->type() == relocInfo::oop_type &&
 676       d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
 677     assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
 678     assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
 679   }
 680 #endif
 681   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 682   cbuf.insts()->emit_int32(d32);
 683 }
 684 
 685 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
 686   address next_ip = cbuf.insts_end() + 4;
 687   emit_d32_reloc(cbuf, (int) (addr - next_ip),
 688                  external_word_Relocation::spec(addr),
 689                  RELOC_DISP32);
 690 }
 691 
 692 
 693 // emit 64 bit value and construct relocation entry from relocInfo::relocType
 694 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
 695   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 696   cbuf.insts()->emit_int64(d64);
 697 }
 698 
 699 // emit 64 bit value and construct relocation entry from RelocationHolder
 700 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
 701 #ifdef ASSERT
 702   if (rspec.reloc()->type() == relocInfo::oop_type &&
 703       d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
 704     assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
 705     assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
 706            "cannot embed scavengable oops in code");
 707   }
 708 #endif
 709   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 710   cbuf.insts()->emit_int64(d64);
 711 }
 712 
 713 // Access stack slot for load or store
 714 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
 715 {
 716   emit_opcode(cbuf, opcode);                  // (e.g., FILD   [RSP+src])
 717   if (-0x80 <= disp && disp < 0x80) {
 718     emit_rm(cbuf, 0x01, rm_field, RSP_enc);   // R/M byte
 719     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
 720     emit_d8(cbuf, disp);     // Displacement  // R/M byte
 721   } else {
 722     emit_rm(cbuf, 0x02, rm_field, RSP_enc);   // R/M byte
 723     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
 724     emit_d32(cbuf, disp);     // Displacement // R/M byte
 725   }
 726 }
 727 
 728    // rRegI ereg, memory mem) %{    // emit_reg_mem
 729 void encode_RegMem(CodeBuffer &cbuf,
 730                    int reg,
 731                    int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
 732 {
 733   assert(disp_reloc == relocInfo::none, "cannot have disp");
 734   int regenc = reg & 7;
 735   int baseenc = base & 7;
 736   int indexenc = index & 7;
 737 
 738   // There is no index & no scale, use form without SIB byte
 739   if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
 740     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
 741     if (disp == 0 && base != RBP_enc && base != R13_enc) {
 742       emit_rm(cbuf, 0x0, regenc, baseenc); // *
 743     } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
 744       // If 8-bit displacement, mode 0x1
 745       emit_rm(cbuf, 0x1, regenc, baseenc); // *
 746       emit_d8(cbuf, disp);
 747     } else {
 748       // If 32-bit displacement
 749       if (base == -1) { // Special flag for absolute address
 750         emit_rm(cbuf, 0x0, regenc, 0x5); // *
 751         if (disp_reloc != relocInfo::none) {
 752           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 753         } else {
 754           emit_d32(cbuf, disp);
 755         }
 756       } else {
 757         // Normal base + offset
 758         emit_rm(cbuf, 0x2, regenc, baseenc); // *
 759         if (disp_reloc != relocInfo::none) {
 760           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 761         } else {
 762           emit_d32(cbuf, disp);
 763         }
 764       }
 765     }
 766   } else {
 767     // Else, encode with the SIB byte
 768     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
 769     if (disp == 0 && base != RBP_enc && base != R13_enc) {
 770       // If no displacement
 771       emit_rm(cbuf, 0x0, regenc, 0x4); // *
 772       emit_rm(cbuf, scale, indexenc, baseenc);
 773     } else {
 774       if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
 775         // If 8-bit displacement, mode 0x1
 776         emit_rm(cbuf, 0x1, regenc, 0x4); // *
 777         emit_rm(cbuf, scale, indexenc, baseenc);
 778         emit_d8(cbuf, disp);
 779       } else {
 780         // If 32-bit displacement
 781         if (base == 0x04 ) {
 782           emit_rm(cbuf, 0x2, regenc, 0x4);
 783           emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
 784         } else {
 785           emit_rm(cbuf, 0x2, regenc, 0x4);
 786           emit_rm(cbuf, scale, indexenc, baseenc); // *
 787         }
 788         if (disp_reloc != relocInfo::none) {
 789           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 790         } else {
 791           emit_d32(cbuf, disp);
 792         }
 793       }
 794     }
 795   }
 796 }
 797 
 798 // This could be in MacroAssembler but it's fairly C2 specific
 799 void emit_cmpfp_fixup(MacroAssembler& _masm) {
 800   Label exit;
 801   __ jccb(Assembler::noParity, exit);
 802   __ pushf();
 803   //
 804   // comiss/ucomiss instructions set ZF,PF,CF flags and
 805   // zero OF,AF,SF for NaN values.
 806   // Fixup flags by zeroing ZF,PF so that compare of NaN
 807   // values returns 'less than' result (CF is set).
 808   // Leave the rest of flags unchanged.
 809   //
 810   //    7 6 5 4 3 2 1 0
 811   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
 812   //    0 0 1 0 1 0 1 1   (0x2B)
 813   //
 814   __ andq(Address(rsp, 0), 0xffffff2b);
 815   __ popf();
 816   __ bind(exit);
 817 }
 818 
 819 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
 820   Label done;
 821   __ movl(dst, -1);
 822   __ jcc(Assembler::parity, done);
 823   __ jcc(Assembler::below, done);
 824   __ setb(Assembler::notEqual, dst);
 825   __ movzbl(dst, dst);
 826   __ bind(done);
 827 }
 828 
 829 
 830 //=============================================================================
 831 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 832 
 833 int Compile::ConstantTable::calculate_table_base_offset() const {
 834   return 0;  // absolute addressing, no offset
 835 }
 836 
 837 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 838 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 839   ShouldNotReachHere();
 840 }
 841 
 842 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 843   // Empty encoding
 844 }
 845 
 846 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 847   return 0;
 848 }
 849 
 850 #ifndef PRODUCT
 851 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 852   st->print("# MachConstantBaseNode (empty encoding)");
 853 }
 854 #endif
 855 
 856 
 857 //=============================================================================
 858 #ifndef PRODUCT
 859 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 860   Compile* C = ra_->C;
 861 
 862   int framesize = C->frame_size_in_bytes();
 863   int bangsize = C->bang_size_in_bytes();
 864   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 865   // Remove wordSize for return addr which is already pushed.
 866   framesize -= wordSize;
 867 
 868   if (C->need_stack_bang(bangsize)) {
 869     framesize -= wordSize;
 870     st->print("# stack bang (%d bytes)", bangsize);
 871     st->print("\n\t");
 872     st->print("pushq   rbp\t# Save rbp");
 873     if (PreserveFramePointer) {
 874         st->print("\n\t");
 875         st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
 876     }
 877     if (framesize) {
 878       st->print("\n\t");
 879       st->print("subq    rsp, #%d\t# Create frame",framesize);
 880     }
 881   } else {
 882     st->print("subq    rsp, #%d\t# Create frame",framesize);
 883     st->print("\n\t");
 884     framesize -= wordSize;
 885     st->print("movq    [rsp + #%d], rbp\t# Save rbp",framesize);
 886     if (PreserveFramePointer) {
 887       st->print("\n\t");
 888       st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
 889       if (framesize > 0) {
 890         st->print("\n\t");
 891         st->print("addq    rbp, #%d", framesize);
 892       }
 893     }
 894   }
 895 
 896   if (VerifyStackAtCalls) {
 897     st->print("\n\t");
 898     framesize -= wordSize;
 899     st->print("movq    [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
 900 #ifdef ASSERT
 901     st->print("\n\t");
 902     st->print("# stack alignment check");
 903 #endif
 904   }
 905   st->cr();
 906 }
 907 #endif
 908 
 909 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 910   Compile* C = ra_->C;
 911   MacroAssembler _masm(&cbuf);
 912 
 913   int framesize = C->frame_size_in_bytes();
 914   int bangsize = C->bang_size_in_bytes();
 915 
 916   __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
 917 
 918   C->set_frame_complete(cbuf.insts_size());
 919 
 920   if (C->has_mach_constant_base_node()) {
 921     // NOTE: We set the table base offset here because users might be
 922     // emitted before MachConstantBaseNode.
 923     Compile::ConstantTable& constant_table = C->constant_table();
 924     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 925   }
 926 }
 927 
 928 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 929 {
 930   return MachNode::size(ra_); // too many variables; just compute it
 931                               // the hard way
 932 }
 933 
 934 int MachPrologNode::reloc() const
 935 {
 936   return 0; // a large enough number
 937 }
 938 
 939 //=============================================================================
 940 #ifndef PRODUCT
 941 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 942 {
 943   Compile* C = ra_->C;
 944   if (generate_vzeroupper(C)) {
 945     st->print("vzeroupper");
 946     st->cr(); st->print("\t");
 947   }
 948 
 949   int framesize = C->frame_size_in_bytes();
 950   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 951   // Remove word for return adr already pushed
 952   // and RBP
 953   framesize -= 2*wordSize;
 954 
 955   if (framesize) {
 956     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);
 957     st->print("\t");
 958   }
 959 
 960   st->print_cr("popq   rbp");
 961   if (do_polling() && C->is_method_compilation()) {
 962     st->print("\t");
 963     if (SafepointMechanism::uses_thread_local_poll()) {
 964       st->print_cr("movq   rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
 965                    "testl  rax, [rscratch1]\t"
 966                    "# Safepoint: poll for GC");
 967     } else if (Assembler::is_polling_page_far()) {
 968       st->print_cr("movq   rscratch1, #polling_page_address\n\t"
 969                    "testl  rax, [rscratch1]\t"
 970                    "# Safepoint: poll for GC");
 971     } else {
 972       st->print_cr("testl  rax, [rip + #offset_to_poll_page]\t"
 973                    "# Safepoint: poll for GC");
 974     }
 975   }
 976 }
 977 #endif
 978 
 979 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 980 {
 981   Compile* C = ra_->C;
 982   MacroAssembler _masm(&cbuf);
 983 
 984   if (generate_vzeroupper(C)) {
 985     // Clear upper bits of YMM registers when current compiled code uses
 986     // wide vectors to avoid AVX <-> SSE transition penalty during call.
 987     __ vzeroupper();
 988   }
 989 
 990   int framesize = C->frame_size_in_bytes();
 991   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 992   // Remove word for return adr already pushed
 993   // and RBP
 994   framesize -= 2*wordSize;
 995 
 996   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
 997 
 998   if (framesize) {
 999     emit_opcode(cbuf, Assembler::REX_W);
1000     if (framesize < 0x80) {
1001       emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1002       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1003       emit_d8(cbuf, framesize);
1004     } else {
1005       emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1006       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1007       emit_d32(cbuf, framesize);
1008     }
1009   }
1010 
1011   // popq rbp
1012   emit_opcode(cbuf, 0x58 | RBP_enc);
1013 
1014   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1015     __ reserved_stack_check();
1016   }
1017 
1018   if (do_polling() && C->is_method_compilation()) {
1019     MacroAssembler _masm(&cbuf);
1020     if (SafepointMechanism::uses_thread_local_poll()) {
1021       __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1022       __ relocate(relocInfo::poll_return_type);
1023       __ testl(rax, Address(rscratch1, 0));
1024     } else {
1025       AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1026       if (Assembler::is_polling_page_far()) {
1027         __ lea(rscratch1, polling_page);
1028         __ relocate(relocInfo::poll_return_type);
1029         __ testl(rax, Address(rscratch1, 0));
1030       } else {
1031         __ testl(rax, polling_page);
1032       }
1033     }
1034   }
1035 }
1036 
1037 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1038 {
1039   return MachNode::size(ra_); // too many variables; just compute it
1040                               // the hard way
1041 }
1042 
1043 int MachEpilogNode::reloc() const
1044 {
1045   return 2; // a large enough number
1046 }
1047 
1048 const Pipeline* MachEpilogNode::pipeline() const
1049 {
1050   return MachNode::pipeline_class();
1051 }
1052 
1053 int MachEpilogNode::safepoint_offset() const
1054 {
1055   return 0;
1056 }
1057 
1058 //=============================================================================
1059 
1060 enum RC {
1061   rc_bad,
1062   rc_int,
1063   rc_float,
1064   rc_stack
1065 };
1066 
1067 static enum RC rc_class(OptoReg::Name reg)
1068 {
1069   if( !OptoReg::is_valid(reg)  ) return rc_bad;
1070 
1071   if (OptoReg::is_stack(reg)) return rc_stack;
1072 
1073   VMReg r = OptoReg::as_VMReg(reg);
1074 
1075   if (r->is_Register()) return rc_int;
1076 
1077   assert(r->is_XMMRegister(), "must be");
1078   return rc_float;
1079 }
1080 
1081 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1082 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1083                           int src_hi, int dst_hi, uint ireg, outputStream* st);
1084 
1085 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1086                             int stack_offset, int reg, uint ireg, outputStream* st);
1087 
1088 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1089                                       int dst_offset, uint ireg, outputStream* st) {
1090   if (cbuf) {
1091     MacroAssembler _masm(cbuf);
1092     switch (ireg) {
1093     case Op_VecS:
1094       __ movq(Address(rsp, -8), rax);
1095       __ movl(rax, Address(rsp, src_offset));
1096       __ movl(Address(rsp, dst_offset), rax);
1097       __ movq(rax, Address(rsp, -8));
1098       break;
1099     case Op_VecD:
1100       __ pushq(Address(rsp, src_offset));
1101       __ popq (Address(rsp, dst_offset));
1102       break;
1103     case Op_VecX:
1104       __ pushq(Address(rsp, src_offset));
1105       __ popq (Address(rsp, dst_offset));
1106       __ pushq(Address(rsp, src_offset+8));
1107       __ popq (Address(rsp, dst_offset+8));
1108       break;
1109     case Op_VecY:
1110       __ vmovdqu(Address(rsp, -32), xmm0);
1111       __ vmovdqu(xmm0, Address(rsp, src_offset));
1112       __ vmovdqu(Address(rsp, dst_offset), xmm0);
1113       __ vmovdqu(xmm0, Address(rsp, -32));
1114       break;
1115     case Op_VecZ:
1116       __ evmovdquq(Address(rsp, -64), xmm0, 2);
1117       __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1118       __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1119       __ evmovdquq(xmm0, Address(rsp, -64), 2);
1120       break;
1121     default:
1122       ShouldNotReachHere();
1123     }
1124 #ifndef PRODUCT
1125   } else {
1126     switch (ireg) {
1127     case Op_VecS:
1128       st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1129                 "movl    rax, [rsp + #%d]\n\t"
1130                 "movl    [rsp + #%d], rax\n\t"
1131                 "movq    rax, [rsp - #8]",
1132                 src_offset, dst_offset);
1133       break;
1134     case Op_VecD:
1135       st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1136                 "popq    [rsp + #%d]",
1137                 src_offset, dst_offset);
1138       break;
1139      case Op_VecX:
1140       st->print("pushq   [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1141                 "popq    [rsp + #%d]\n\t"
1142                 "pushq   [rsp + #%d]\n\t"
1143                 "popq    [rsp + #%d]",
1144                 src_offset, dst_offset, src_offset+8, dst_offset+8);
1145       break;
1146     case Op_VecY:
1147       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1148                 "vmovdqu xmm0, [rsp + #%d]\n\t"
1149                 "vmovdqu [rsp + #%d], xmm0\n\t"
1150                 "vmovdqu xmm0, [rsp - #32]",
1151                 src_offset, dst_offset);
1152       break;
1153     case Op_VecZ:
1154       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1155                 "vmovdqu xmm0, [rsp + #%d]\n\t"
1156                 "vmovdqu [rsp + #%d], xmm0\n\t"
1157                 "vmovdqu xmm0, [rsp - #64]",
1158                 src_offset, dst_offset);
1159       break;
1160     default:
1161       ShouldNotReachHere();
1162     }
1163 #endif
1164   }
1165 }
1166 
1167 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1168                                        PhaseRegAlloc* ra_,
1169                                        bool do_size,
1170                                        outputStream* st) const {
1171   assert(cbuf != NULL || st  != NULL, "sanity");
1172   // Get registers to move
1173   OptoReg::Name src_second = ra_->get_reg_second(in(1));
1174   OptoReg::Name src_first = ra_->get_reg_first(in(1));
1175   OptoReg::Name dst_second = ra_->get_reg_second(this);
1176   OptoReg::Name dst_first = ra_->get_reg_first(this);
1177 
1178   enum RC src_second_rc = rc_class(src_second);
1179   enum RC src_first_rc = rc_class(src_first);
1180   enum RC dst_second_rc = rc_class(dst_second);
1181   enum RC dst_first_rc = rc_class(dst_first);
1182 
1183   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1184          "must move at least 1 register" );
1185 
1186   if (src_first == dst_first && src_second == dst_second) {
1187     // Self copy, no move
1188     return 0;
1189   }
1190   if (bottom_type()->isa_vect() != NULL) {
1191     uint ireg = ideal_reg();
1192     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1193     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1194     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1195       // mem -> mem
1196       int src_offset = ra_->reg2offset(src_first);
1197       int dst_offset = ra_->reg2offset(dst_first);
1198       vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1199     } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1200       vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1201     } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1202       int stack_offset = ra_->reg2offset(dst_first);
1203       vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1204     } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1205       int stack_offset = ra_->reg2offset(src_first);
1206       vec_spill_helper(cbuf, false, true,  stack_offset, dst_first, ireg, st);
1207     } else {
1208       ShouldNotReachHere();
1209     }
1210     return 0;
1211   }
1212   if (src_first_rc == rc_stack) {
1213     // mem ->
1214     if (dst_first_rc == rc_stack) {
1215       // mem -> mem
1216       assert(src_second != dst_first, "overlap");
1217       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1218           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1219         // 64-bit
1220         int src_offset = ra_->reg2offset(src_first);
1221         int dst_offset = ra_->reg2offset(dst_first);
1222         if (cbuf) {
1223           MacroAssembler _masm(cbuf);
1224           __ pushq(Address(rsp, src_offset));
1225           __ popq (Address(rsp, dst_offset));
1226 #ifndef PRODUCT
1227         } else {
1228           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1229                     "popq    [rsp + #%d]",
1230                      src_offset, dst_offset);
1231 #endif
1232         }
1233       } else {
1234         // 32-bit
1235         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1236         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1237         // No pushl/popl, so:
1238         int src_offset = ra_->reg2offset(src_first);
1239         int dst_offset = ra_->reg2offset(dst_first);
1240         if (cbuf) {
1241           MacroAssembler _masm(cbuf);
1242           __ movq(Address(rsp, -8), rax);
1243           __ movl(rax, Address(rsp, src_offset));
1244           __ movl(Address(rsp, dst_offset), rax);
1245           __ movq(rax, Address(rsp, -8));
1246 #ifndef PRODUCT
1247         } else {
1248           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1249                     "movl    rax, [rsp + #%d]\n\t"
1250                     "movl    [rsp + #%d], rax\n\t"
1251                     "movq    rax, [rsp - #8]",
1252                      src_offset, dst_offset);
1253 #endif
1254         }
1255       }
1256       return 0;
1257     } else if (dst_first_rc == rc_int) {
1258       // mem -> gpr
1259       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1260           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1261         // 64-bit
1262         int offset = ra_->reg2offset(src_first);
1263         if (cbuf) {
1264           MacroAssembler _masm(cbuf);
1265           __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1266 #ifndef PRODUCT
1267         } else {
1268           st->print("movq    %s, [rsp + #%d]\t# spill",
1269                      Matcher::regName[dst_first],
1270                      offset);
1271 #endif
1272         }
1273       } else {
1274         // 32-bit
1275         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1276         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1277         int offset = ra_->reg2offset(src_first);
1278         if (cbuf) {
1279           MacroAssembler _masm(cbuf);
1280           __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1281 #ifndef PRODUCT
1282         } else {
1283           st->print("movl    %s, [rsp + #%d]\t# spill",
1284                      Matcher::regName[dst_first],
1285                      offset);
1286 #endif
1287         }
1288       }
1289       return 0;
1290     } else if (dst_first_rc == rc_float) {
1291       // mem-> xmm
1292       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1293           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1294         // 64-bit
1295         int offset = ra_->reg2offset(src_first);
1296         if (cbuf) {
1297           MacroAssembler _masm(cbuf);
1298           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1299 #ifndef PRODUCT
1300         } else {
1301           st->print("%s  %s, [rsp + #%d]\t# spill",
1302                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1303                      Matcher::regName[dst_first],
1304                      offset);
1305 #endif
1306         }
1307       } else {
1308         // 32-bit
1309         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1310         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1311         int offset = ra_->reg2offset(src_first);
1312         if (cbuf) {
1313           MacroAssembler _masm(cbuf);
1314           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1315 #ifndef PRODUCT
1316         } else {
1317           st->print("movss   %s, [rsp + #%d]\t# spill",
1318                      Matcher::regName[dst_first],
1319                      offset);
1320 #endif
1321         }
1322       }
1323       return 0;
1324     }
1325   } else if (src_first_rc == rc_int) {
1326     // gpr ->
1327     if (dst_first_rc == rc_stack) {
1328       // gpr -> mem
1329       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1330           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1331         // 64-bit
1332         int offset = ra_->reg2offset(dst_first);
1333         if (cbuf) {
1334           MacroAssembler _masm(cbuf);
1335           __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1336 #ifndef PRODUCT
1337         } else {
1338           st->print("movq    [rsp + #%d], %s\t# spill",
1339                      offset,
1340                      Matcher::regName[src_first]);
1341 #endif
1342         }
1343       } else {
1344         // 32-bit
1345         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1346         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1347         int offset = ra_->reg2offset(dst_first);
1348         if (cbuf) {
1349           MacroAssembler _masm(cbuf);
1350           __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1351 #ifndef PRODUCT
1352         } else {
1353           st->print("movl    [rsp + #%d], %s\t# spill",
1354                      offset,
1355                      Matcher::regName[src_first]);
1356 #endif
1357         }
1358       }
1359       return 0;
1360     } else if (dst_first_rc == rc_int) {
1361       // gpr -> gpr
1362       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1363           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1364         // 64-bit
1365         if (cbuf) {
1366           MacroAssembler _masm(cbuf);
1367           __ movq(as_Register(Matcher::_regEncode[dst_first]),
1368                   as_Register(Matcher::_regEncode[src_first]));
1369 #ifndef PRODUCT
1370         } else {
1371           st->print("movq    %s, %s\t# spill",
1372                      Matcher::regName[dst_first],
1373                      Matcher::regName[src_first]);
1374 #endif
1375         }
1376         return 0;
1377       } else {
1378         // 32-bit
1379         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1380         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1381         if (cbuf) {
1382           MacroAssembler _masm(cbuf);
1383           __ movl(as_Register(Matcher::_regEncode[dst_first]),
1384                   as_Register(Matcher::_regEncode[src_first]));
1385 #ifndef PRODUCT
1386         } else {
1387           st->print("movl    %s, %s\t# spill",
1388                      Matcher::regName[dst_first],
1389                      Matcher::regName[src_first]);
1390 #endif
1391         }
1392         return 0;
1393       }
1394     } else if (dst_first_rc == rc_float) {
1395       // gpr -> xmm
1396       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1397           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1398         // 64-bit
1399         if (cbuf) {
1400           MacroAssembler _masm(cbuf);
1401           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1402 #ifndef PRODUCT
1403         } else {
1404           st->print("movdq   %s, %s\t# spill",
1405                      Matcher::regName[dst_first],
1406                      Matcher::regName[src_first]);
1407 #endif
1408         }
1409       } else {
1410         // 32-bit
1411         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1412         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1413         if (cbuf) {
1414           MacroAssembler _masm(cbuf);
1415           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1416 #ifndef PRODUCT
1417         } else {
1418           st->print("movdl   %s, %s\t# spill",
1419                      Matcher::regName[dst_first],
1420                      Matcher::regName[src_first]);
1421 #endif
1422         }
1423       }
1424       return 0;
1425     }
1426   } else if (src_first_rc == rc_float) {
1427     // xmm ->
1428     if (dst_first_rc == rc_stack) {
1429       // xmm -> mem
1430       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1431           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1432         // 64-bit
1433         int offset = ra_->reg2offset(dst_first);
1434         if (cbuf) {
1435           MacroAssembler _masm(cbuf);
1436           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438         } else {
1439           st->print("movsd   [rsp + #%d], %s\t# spill",
1440                      offset,
1441                      Matcher::regName[src_first]);
1442 #endif
1443         }
1444       } else {
1445         // 32-bit
1446         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1447         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1448         int offset = ra_->reg2offset(dst_first);
1449         if (cbuf) {
1450           MacroAssembler _masm(cbuf);
1451           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1452 #ifndef PRODUCT
1453         } else {
1454           st->print("movss   [rsp + #%d], %s\t# spill",
1455                      offset,
1456                      Matcher::regName[src_first]);
1457 #endif
1458         }
1459       }
1460       return 0;
1461     } else if (dst_first_rc == rc_int) {
1462       // xmm -> gpr
1463       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1464           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1465         // 64-bit
1466         if (cbuf) {
1467           MacroAssembler _masm(cbuf);
1468           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1469 #ifndef PRODUCT
1470         } else {
1471           st->print("movdq   %s, %s\t# spill",
1472                      Matcher::regName[dst_first],
1473                      Matcher::regName[src_first]);
1474 #endif
1475         }
1476       } else {
1477         // 32-bit
1478         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1479         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1480         if (cbuf) {
1481           MacroAssembler _masm(cbuf);
1482           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1483 #ifndef PRODUCT
1484         } else {
1485           st->print("movdl   %s, %s\t# spill",
1486                      Matcher::regName[dst_first],
1487                      Matcher::regName[src_first]);
1488 #endif
1489         }
1490       }
1491       return 0;
1492     } else if (dst_first_rc == rc_float) {
1493       // xmm -> xmm
1494       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1495           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1496         // 64-bit
1497         if (cbuf) {
1498           MacroAssembler _masm(cbuf);
1499           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1500 #ifndef PRODUCT
1501         } else {
1502           st->print("%s  %s, %s\t# spill",
1503                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1504                      Matcher::regName[dst_first],
1505                      Matcher::regName[src_first]);
1506 #endif
1507         }
1508       } else {
1509         // 32-bit
1510         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1511         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1512         if (cbuf) {
1513           MacroAssembler _masm(cbuf);
1514           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1515 #ifndef PRODUCT
1516         } else {
1517           st->print("%s  %s, %s\t# spill",
1518                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1519                      Matcher::regName[dst_first],
1520                      Matcher::regName[src_first]);
1521 #endif
1522         }
1523       }
1524       return 0;
1525     }
1526   }
1527 
1528   assert(0," foo ");
1529   Unimplemented();
1530   return 0;
1531 }
1532 
1533 #ifndef PRODUCT
1534 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1535   implementation(NULL, ra_, false, st);
1536 }
1537 #endif
1538 
1539 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1540   implementation(&cbuf, ra_, false, NULL);
1541 }
1542 
1543 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1544   return MachNode::size(ra_);
1545 }
1546 
1547 //=============================================================================
1548 #ifndef PRODUCT
1549 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1550 {
1551   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1552   int reg = ra_->get_reg_first(this);
1553   st->print("leaq    %s, [rsp + #%d]\t# box lock",
1554             Matcher::regName[reg], offset);
1555 }
1556 #endif
1557 
1558 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1559 {
1560   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1561   int reg = ra_->get_encode(this);
1562   if (offset >= 0x80) {
1563     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1564     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
1565     emit_rm(cbuf, 0x2, reg & 7, 0x04);
1566     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1567     emit_d32(cbuf, offset);
1568   } else {
1569     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1570     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
1571     emit_rm(cbuf, 0x1, reg & 7, 0x04);
1572     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1573     emit_d8(cbuf, offset);
1574   }
1575 }
1576 
1577 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1578 {
1579   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1580   return (offset < 0x80) ? 5 : 8; // REX
1581 }
1582 
1583 //=============================================================================
1584 #ifndef PRODUCT
1585 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1586 {
1587   if (UseCompressedClassPointers) {
1588     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1589     st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1590     st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");
1591   } else {
1592     st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1593                  "# Inline cache check");
1594   }
1595   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
1596   st->print_cr("\tnop\t# nops to align entry point");
1597 }
1598 #endif
1599 
1600 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1601 {
1602   MacroAssembler masm(&cbuf);
1603   uint insts_size = cbuf.insts_size();
1604   if (UseCompressedClassPointers) {
1605     masm.load_klass(rscratch1, j_rarg0);
1606     masm.cmpptr(rax, rscratch1);
1607   } else {
1608     masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1609   }
1610 
1611   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1612 
1613   /* WARNING these NOPs are critical so that verified entry point is properly
1614      4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1615   int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1616   if (OptoBreakpoint) {
1617     // Leave space for int3
1618     nops_cnt -= 1;
1619   }
1620   nops_cnt &= 0x3; // Do not add nops if code is aligned.
1621   if (nops_cnt > 0)
1622     masm.nop(nops_cnt);
1623 }
1624 
1625 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1626 {
1627   return MachNode::size(ra_); // too many variables; just compute it
1628                               // the hard way
1629 }
1630 
1631 
1632 //=============================================================================
1633 
1634 int Matcher::regnum_to_fpu_offset(int regnum)
1635 {
1636   return regnum - 32; // The FP registers are in the second chunk
1637 }
1638 
1639 // This is UltraSparc specific, true just means we have fast l2f conversion
1640 const bool Matcher::convL2FSupported(void) {
1641   return true;
1642 }
1643 
1644 // Is this branch offset short enough that a short branch can be used?
1645 //
1646 // NOTE: If the platform does not provide any short branch variants, then
1647 //       this method should return false for offset 0.
1648 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1649   // The passed offset is relative to address of the branch.
1650   // On 86 a branch displacement is calculated relative to address
1651   // of a next instruction.
1652   offset -= br_size;
1653 
1654   // the short version of jmpConUCF2 contains multiple branches,
1655   // making the reach slightly less
1656   if (rule == jmpConUCF2_rule)
1657     return (-126 <= offset && offset <= 125);
1658   return (-128 <= offset && offset <= 127);
1659 }
1660 
1661 const bool Matcher::isSimpleConstant64(jlong value) {
1662   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1663   //return value == (int) value;  // Cf. storeImmL and immL32.
1664 
1665   // Probably always true, even if a temp register is required.
1666   return true;
1667 }
1668 
1669 // The ecx parameter to rep stosq for the ClearArray node is in words.
1670 const bool Matcher::init_array_count_is_in_bytes = false;
1671 
1672 // No additional cost for CMOVL.
1673 const int Matcher::long_cmove_cost() { return 0; }
1674 
1675 // No CMOVF/CMOVD with SSE2
1676 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1677 
1678 // Does the CPU require late expand (see block.cpp for description of late expand)?
1679 const bool Matcher::require_postalloc_expand = false;
1680 
1681 // Do we need to mask the count passed to shift instructions or does
1682 // the cpu only look at the lower 5/6 bits anyway?
1683 const bool Matcher::need_masked_shift_count = false;
1684 
1685 bool Matcher::narrow_oop_use_complex_address() {
1686   assert(UseCompressedOops, "only for compressed oops code");
1687   return (LogMinObjAlignmentInBytes <= 3);
1688 }
1689 
1690 bool Matcher::narrow_klass_use_complex_address() {
1691   assert(UseCompressedClassPointers, "only for compressed klass code");
1692   return (LogKlassAlignmentInBytes <= 3);
1693 }
1694 
1695 bool Matcher::const_oop_prefer_decode() {
1696   // Prefer ConN+DecodeN over ConP.
1697   return true;
1698 }
1699 
1700 bool Matcher::const_klass_prefer_decode() {
1701   // TODO: Either support matching DecodeNKlass (heap-based) in operand
1702   //       or condisider the following:
1703   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1704   //return Universe::narrow_klass_base() == NULL;
1705   return true;
1706 }
1707 
1708 // Is it better to copy float constants, or load them directly from
1709 // memory?  Intel can load a float constant from a direct address,
1710 // requiring no extra registers.  Most RISCs will have to materialize
1711 // an address into a register first, so they would do better to copy
1712 // the constant from stack.
1713 const bool Matcher::rematerialize_float_constants = true; // XXX
1714 
1715 // If CPU can load and store mis-aligned doubles directly then no
1716 // fixup is needed.  Else we split the double into 2 integer pieces
1717 // and move it piece-by-piece.  Only happens when passing doubles into
1718 // C code as the Java calling convention forces doubles to be aligned.
1719 const bool Matcher::misaligned_doubles_ok = true;
1720 
1721 // No-op on amd64
1722 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1723 
1724 // Advertise here if the CPU requires explicit rounding operations to
1725 // implement the UseStrictFP mode.
1726 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1727 
1728 // Are floats conerted to double when stored to stack during deoptimization?
1729 // On x64 it is stored without convertion so we can use normal access.
1730 bool Matcher::float_in_double() { return false; }
1731 
1732 // Do ints take an entire long register or just half?
1733 const bool Matcher::int_in_long = true;
1734 
1735 // Return whether or not this register is ever used as an argument.
1736 // This function is used on startup to build the trampoline stubs in
1737 // generateOptoStub.  Registers not mentioned will be killed by the VM
1738 // call in the trampoline, and arguments in those registers not be
1739 // available to the callee.
1740 bool Matcher::can_be_java_arg(int reg)
1741 {
1742   return
1743     reg ==  RDI_num || reg == RDI_H_num ||
1744     reg ==  RSI_num || reg == RSI_H_num ||
1745     reg ==  RDX_num || reg == RDX_H_num ||
1746     reg ==  RCX_num || reg == RCX_H_num ||
1747     reg ==   R8_num || reg ==  R8_H_num ||
1748     reg ==   R9_num || reg ==  R9_H_num ||
1749     reg ==  R12_num || reg == R12_H_num ||
1750     reg == XMM0_num || reg == XMM0b_num ||
1751     reg == XMM1_num || reg == XMM1b_num ||
1752     reg == XMM2_num || reg == XMM2b_num ||
1753     reg == XMM3_num || reg == XMM3b_num ||
1754     reg == XMM4_num || reg == XMM4b_num ||
1755     reg == XMM5_num || reg == XMM5b_num ||
1756     reg == XMM6_num || reg == XMM6b_num ||
1757     reg == XMM7_num || reg == XMM7b_num;
1758 }
1759 
1760 bool Matcher::is_spillable_arg(int reg)
1761 {
1762   return can_be_java_arg(reg);
1763 }
1764 
1765 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1766   // In 64 bit mode a code which use multiply when
1767   // devisor is constant is faster than hardware
1768   // DIV instruction (it uses MulHiL).
1769   return false;
1770 }
1771 
1772 // Register for DIVI projection of divmodI
1773 RegMask Matcher::divI_proj_mask() {
1774   return INT_RAX_REG_mask();
1775 }
1776 
1777 // Register for MODI projection of divmodI
1778 RegMask Matcher::modI_proj_mask() {
1779   return INT_RDX_REG_mask();
1780 }
1781 
1782 // Register for DIVL projection of divmodL
1783 RegMask Matcher::divL_proj_mask() {
1784   return LONG_RAX_REG_mask();
1785 }
1786 
1787 // Register for MODL projection of divmodL
1788 RegMask Matcher::modL_proj_mask() {
1789   return LONG_RDX_REG_mask();
1790 }
1791 
1792 // Register for saving SP into on method handle invokes. Not used on x86_64.
1793 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1794     return NO_REG_mask();
1795 }
1796 
1797 %}
1798 
1799 //----------ENCODING BLOCK-----------------------------------------------------
1800 // This block specifies the encoding classes used by the compiler to
1801 // output byte streams.  Encoding classes are parameterized macros
1802 // used by Machine Instruction Nodes in order to generate the bit
1803 // encoding of the instruction.  Operands specify their base encoding
1804 // interface with the interface keyword.  There are currently
1805 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1806 // COND_INTER.  REG_INTER causes an operand to generate a function
1807 // which returns its register number when queried.  CONST_INTER causes
1808 // an operand to generate a function which returns the value of the
1809 // constant when queried.  MEMORY_INTER causes an operand to generate
1810 // four functions which return the Base Register, the Index Register,
1811 // the Scale Value, and the Offset Value of the operand when queried.
1812 // COND_INTER causes an operand to generate six functions which return
1813 // the encoding code (ie - encoding bits for the instruction)
1814 // associated with each basic boolean condition for a conditional
1815 // instruction.
1816 //
1817 // Instructions specify two basic values for encoding.  Again, a
1818 // function is available to check if the constant displacement is an
1819 // oop. They use the ins_encode keyword to specify their encoding
1820 // classes (which must be a sequence of enc_class names, and their
1821 // parameters, specified in the encoding block), and they use the
1822 // opcode keyword to specify, in order, their primary, secondary, and
1823 // tertiary opcode.  Only the opcode sections which a particular
1824 // instruction needs for encoding need to be specified.
1825 encode %{
1826   // Build emit functions for each basic byte or larger field in the
1827   // intel encoding scheme (opcode, rm, sib, immediate), and call them
1828   // from C++ code in the enc_class source block.  Emit functions will
1829   // live in the main source block for now.  In future, we can
1830   // generalize this by adding a syntax that specifies the sizes of
1831   // fields in an order, so that the adlc can build the emit functions
1832   // automagically
1833 
1834   // Emit primary opcode
1835   enc_class OpcP
1836   %{
1837     emit_opcode(cbuf, $primary);
1838   %}
1839 
1840   // Emit secondary opcode
1841   enc_class OpcS
1842   %{
1843     emit_opcode(cbuf, $secondary);
1844   %}
1845 
1846   // Emit tertiary opcode
1847   enc_class OpcT
1848   %{
1849     emit_opcode(cbuf, $tertiary);
1850   %}
1851 
1852   // Emit opcode directly
1853   enc_class Opcode(immI d8)
1854   %{
1855     emit_opcode(cbuf, $d8$$constant);
1856   %}
1857 
1858   // Emit size prefix
1859   enc_class SizePrefix
1860   %{
1861     emit_opcode(cbuf, 0x66);
1862   %}
1863 
1864   enc_class reg(rRegI reg)
1865   %{
1866     emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1867   %}
1868 
1869   enc_class reg_reg(rRegI dst, rRegI src)
1870   %{
1871     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1872   %}
1873 
1874   enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1875   %{
1876     emit_opcode(cbuf, $opcode$$constant);
1877     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1878   %}
1879 
1880   enc_class cdql_enc(no_rax_rdx_RegI div)
1881   %{
1882     // Full implementation of Java idiv and irem; checks for
1883     // special case as described in JVM spec., p.243 & p.271.
1884     //
1885     //         normal case                           special case
1886     //
1887     // input : rax: dividend                         min_int
1888     //         reg: divisor                          -1
1889     //
1890     // output: rax: quotient  (= rax idiv reg)       min_int
1891     //         rdx: remainder (= rax irem reg)       0
1892     //
1893     //  Code sequnce:
1894     //
1895     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax
1896     //    5:   75 07/08                jne    e <normal>
1897     //    7:   33 d2                   xor    %edx,%edx
1898     //  [div >= 8 -> offset + 1]
1899     //  [REX_B]
1900     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div
1901     //    c:   74 03/04                je     11 <done>
1902     // 000000000000000e <normal>:
1903     //    e:   99                      cltd
1904     //  [div >= 8 -> offset + 1]
1905     //  [REX_B]
1906     //    f:   f7 f9                   idiv   $div
1907     // 0000000000000011 <done>:
1908 
1909     // cmp    $0x80000000,%eax
1910     emit_opcode(cbuf, 0x3d);
1911     emit_d8(cbuf, 0x00);
1912     emit_d8(cbuf, 0x00);
1913     emit_d8(cbuf, 0x00);
1914     emit_d8(cbuf, 0x80);
1915 
1916     // jne    e <normal>
1917     emit_opcode(cbuf, 0x75);
1918     emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1919 
1920     // xor    %edx,%edx
1921     emit_opcode(cbuf, 0x33);
1922     emit_d8(cbuf, 0xD2);
1923 
1924     // cmp    $0xffffffffffffffff,%ecx
1925     if ($div$$reg >= 8) {
1926       emit_opcode(cbuf, Assembler::REX_B);
1927     }
1928     emit_opcode(cbuf, 0x83);
1929     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1930     emit_d8(cbuf, 0xFF);
1931 
1932     // je     11 <done>
1933     emit_opcode(cbuf, 0x74);
1934     emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1935 
1936     // <normal>
1937     // cltd
1938     emit_opcode(cbuf, 0x99);
1939 
1940     // idivl (note: must be emitted by the user of this rule)
1941     // <done>
1942   %}
1943 
1944   enc_class cdqq_enc(no_rax_rdx_RegL div)
1945   %{
1946     // Full implementation of Java ldiv and lrem; checks for
1947     // special case as described in JVM spec., p.243 & p.271.
1948     //
1949     //         normal case                           special case
1950     //
1951     // input : rax: dividend                         min_long
1952     //         reg: divisor                          -1
1953     //
1954     // output: rax: quotient  (= rax idiv reg)       min_long
1955     //         rdx: remainder (= rax irem reg)       0
1956     //
1957     //  Code sequnce:
1958     //
1959     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx
1960     //    7:   00 00 80
1961     //    a:   48 39 d0                cmp    %rdx,%rax
1962     //    d:   75 08                   jne    17 <normal>
1963     //    f:   33 d2                   xor    %edx,%edx
1964     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div
1965     //   15:   74 05                   je     1c <done>
1966     // 0000000000000017 <normal>:
1967     //   17:   48 99                   cqto
1968     //   19:   48 f7 f9                idiv   $div
1969     // 000000000000001c <done>:
1970 
1971     // mov    $0x8000000000000000,%rdx
1972     emit_opcode(cbuf, Assembler::REX_W);
1973     emit_opcode(cbuf, 0xBA);
1974     emit_d8(cbuf, 0x00);
1975     emit_d8(cbuf, 0x00);
1976     emit_d8(cbuf, 0x00);
1977     emit_d8(cbuf, 0x00);
1978     emit_d8(cbuf, 0x00);
1979     emit_d8(cbuf, 0x00);
1980     emit_d8(cbuf, 0x00);
1981     emit_d8(cbuf, 0x80);
1982 
1983     // cmp    %rdx,%rax
1984     emit_opcode(cbuf, Assembler::REX_W);
1985     emit_opcode(cbuf, 0x39);
1986     emit_d8(cbuf, 0xD0);
1987 
1988     // jne    17 <normal>
1989     emit_opcode(cbuf, 0x75);
1990     emit_d8(cbuf, 0x08);
1991 
1992     // xor    %edx,%edx
1993     emit_opcode(cbuf, 0x33);
1994     emit_d8(cbuf, 0xD2);
1995 
1996     // cmp    $0xffffffffffffffff,$div
1997     emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1998     emit_opcode(cbuf, 0x83);
1999     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2000     emit_d8(cbuf, 0xFF);
2001 
2002     // je     1e <done>
2003     emit_opcode(cbuf, 0x74);
2004     emit_d8(cbuf, 0x05);
2005 
2006     // <normal>
2007     // cqto
2008     emit_opcode(cbuf, Assembler::REX_W);
2009     emit_opcode(cbuf, 0x99);
2010 
2011     // idivq (note: must be emitted by the user of this rule)
2012     // <done>
2013   %}
2014 
2015   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2016   enc_class OpcSE(immI imm)
2017   %{
2018     // Emit primary opcode and set sign-extend bit
2019     // Check for 8-bit immediate, and set sign extend bit in opcode
2020     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2021       emit_opcode(cbuf, $primary | 0x02);
2022     } else {
2023       // 32-bit immediate
2024       emit_opcode(cbuf, $primary);
2025     }
2026   %}
2027 
2028   enc_class OpcSErm(rRegI dst, immI imm)
2029   %{
2030     // OpcSEr/m
2031     int dstenc = $dst$$reg;
2032     if (dstenc >= 8) {
2033       emit_opcode(cbuf, Assembler::REX_B);
2034       dstenc -= 8;
2035     }
2036     // Emit primary opcode and set sign-extend bit
2037     // Check for 8-bit immediate, and set sign extend bit in opcode
2038     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2039       emit_opcode(cbuf, $primary | 0x02);
2040     } else {
2041       // 32-bit immediate
2042       emit_opcode(cbuf, $primary);
2043     }
2044     // Emit r/m byte with secondary opcode, after primary opcode.
2045     emit_rm(cbuf, 0x3, $secondary, dstenc);
2046   %}
2047 
2048   enc_class OpcSErm_wide(rRegL dst, immI imm)
2049   %{
2050     // OpcSEr/m
2051     int dstenc = $dst$$reg;
2052     if (dstenc < 8) {
2053       emit_opcode(cbuf, Assembler::REX_W);
2054     } else {
2055       emit_opcode(cbuf, Assembler::REX_WB);
2056       dstenc -= 8;
2057     }
2058     // Emit primary opcode and set sign-extend bit
2059     // Check for 8-bit immediate, and set sign extend bit in opcode
2060     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2061       emit_opcode(cbuf, $primary | 0x02);
2062     } else {
2063       // 32-bit immediate
2064       emit_opcode(cbuf, $primary);
2065     }
2066     // Emit r/m byte with secondary opcode, after primary opcode.
2067     emit_rm(cbuf, 0x3, $secondary, dstenc);
2068   %}
2069 
2070   enc_class Con8or32(immI imm)
2071   %{
2072     // Check for 8-bit immediate, and set sign extend bit in opcode
2073     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2074       $$$emit8$imm$$constant;
2075     } else {
2076       // 32-bit immediate
2077       $$$emit32$imm$$constant;
2078     }
2079   %}
2080 
2081   enc_class opc2_reg(rRegI dst)
2082   %{
2083     // BSWAP
2084     emit_cc(cbuf, $secondary, $dst$$reg);
2085   %}
2086 
2087   enc_class opc3_reg(rRegI dst)
2088   %{
2089     // BSWAP
2090     emit_cc(cbuf, $tertiary, $dst$$reg);
2091   %}
2092 
2093   enc_class reg_opc(rRegI div)
2094   %{
2095     // INC, DEC, IDIV, IMOD, JMP indirect, ...
2096     emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2097   %}
2098 
2099   enc_class enc_cmov(cmpOp cop)
2100   %{
2101     // CMOV
2102     $$$emit8$primary;
2103     emit_cc(cbuf, $secondary, $cop$$cmpcode);
2104   %}
2105 
2106   enc_class enc_PartialSubtypeCheck()
2107   %{
2108     Register Rrdi = as_Register(RDI_enc); // result register
2109     Register Rrax = as_Register(RAX_enc); // super class
2110     Register Rrcx = as_Register(RCX_enc); // killed
2111     Register Rrsi = as_Register(RSI_enc); // sub class
2112     Label miss;
2113     const bool set_cond_codes = true;
2114 
2115     MacroAssembler _masm(&cbuf);
2116     __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2117                                      NULL, &miss,
2118                                      /*set_cond_codes:*/ true);
2119     if ($primary) {
2120       __ xorptr(Rrdi, Rrdi);
2121     }
2122     __ bind(miss);
2123   %}
2124 
2125   enc_class clear_avx %{
2126     debug_only(int off0 = cbuf.insts_size());
2127     if (generate_vzeroupper(Compile::current())) {
2128       // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2129       // Clear upper bits of YMM registers when current compiled code uses
2130       // wide vectors to avoid AVX <-> SSE transition penalty during call.
2131       MacroAssembler _masm(&cbuf);
2132       __ vzeroupper();
2133     }
2134     debug_only(int off1 = cbuf.insts_size());
2135     assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2136   %}
2137 
2138   enc_class Java_To_Runtime(method meth) %{
2139     // No relocation needed
2140     MacroAssembler _masm(&cbuf);
2141     __ mov64(r10, (int64_t) $meth$$method);
2142     __ call(r10);
2143   %}
2144 
2145   enc_class Java_To_Interpreter(method meth)
2146   %{
2147     // CALL Java_To_Interpreter
2148     // This is the instruction starting address for relocation info.
2149     cbuf.set_insts_mark();
2150     $$$emit8$primary;
2151     // CALL directly to the runtime
2152     emit_d32_reloc(cbuf,
2153                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2154                    runtime_call_Relocation::spec(),
2155                    RELOC_DISP32);
2156   %}
2157 
2158   enc_class Java_Static_Call(method meth)
2159   %{
2160     // JAVA STATIC CALL
2161     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
2162     // determine who we intended to call.
2163     cbuf.set_insts_mark();
2164     $$$emit8$primary;
2165 
2166     if (!_method) {
2167       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2168                      runtime_call_Relocation::spec(),
2169                      RELOC_DISP32);
2170     } else {
2171       int method_index = resolved_method_index(cbuf);
2172       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2173                                                   : static_call_Relocation::spec(method_index);
2174       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2175                      rspec, RELOC_DISP32);
2176       // Emit stubs for static call.
2177       address mark = cbuf.insts_mark();
2178       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2179       if (stub == NULL) {
2180         ciEnv::current()->record_failure("CodeCache is full");
2181         return;
2182       }
2183 #if INCLUDE_AOT
2184       CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2185 #endif
2186     }
2187   %}
2188 
2189   enc_class Java_Dynamic_Call(method meth) %{
2190     MacroAssembler _masm(&cbuf);
2191     __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2192   %}
2193 
2194   enc_class Java_Compiled_Call(method meth)
2195   %{
2196     // JAVA COMPILED CALL
2197     int disp = in_bytes(Method:: from_compiled_offset());
2198 
2199     // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2200     // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2201 
2202     // callq *disp(%rax)
2203     cbuf.set_insts_mark();
2204     $$$emit8$primary;
2205     if (disp < 0x80) {
2206       emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2207       emit_d8(cbuf, disp); // Displacement
2208     } else {
2209       emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2210       emit_d32(cbuf, disp); // Displacement
2211     }
2212   %}
2213 
2214   enc_class reg_opc_imm(rRegI dst, immI8 shift)
2215   %{
2216     // SAL, SAR, SHR
2217     int dstenc = $dst$$reg;
2218     if (dstenc >= 8) {
2219       emit_opcode(cbuf, Assembler::REX_B);
2220       dstenc -= 8;
2221     }
2222     $$$emit8$primary;
2223     emit_rm(cbuf, 0x3, $secondary, dstenc);
2224     $$$emit8$shift$$constant;
2225   %}
2226 
2227   enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2228   %{
2229     // SAL, SAR, SHR
2230     int dstenc = $dst$$reg;
2231     if (dstenc < 8) {
2232       emit_opcode(cbuf, Assembler::REX_W);
2233     } else {
2234       emit_opcode(cbuf, Assembler::REX_WB);
2235       dstenc -= 8;
2236     }
2237     $$$emit8$primary;
2238     emit_rm(cbuf, 0x3, $secondary, dstenc);
2239     $$$emit8$shift$$constant;
2240   %}
2241 
2242   enc_class load_immI(rRegI dst, immI src)
2243   %{
2244     int dstenc = $dst$$reg;
2245     if (dstenc >= 8) {
2246       emit_opcode(cbuf, Assembler::REX_B);
2247       dstenc -= 8;
2248     }
2249     emit_opcode(cbuf, 0xB8 | dstenc);
2250     $$$emit32$src$$constant;
2251   %}
2252 
2253   enc_class load_immL(rRegL dst, immL src)
2254   %{
2255     int dstenc = $dst$$reg;
2256     if (dstenc < 8) {
2257       emit_opcode(cbuf, Assembler::REX_W);
2258     } else {
2259       emit_opcode(cbuf, Assembler::REX_WB);
2260       dstenc -= 8;
2261     }
2262     emit_opcode(cbuf, 0xB8 | dstenc);
2263     emit_d64(cbuf, $src$$constant);
2264   %}
2265 
2266   enc_class load_immUL32(rRegL dst, immUL32 src)
2267   %{
2268     // same as load_immI, but this time we care about zeroes in the high word
2269     int dstenc = $dst$$reg;
2270     if (dstenc >= 8) {
2271       emit_opcode(cbuf, Assembler::REX_B);
2272       dstenc -= 8;
2273     }
2274     emit_opcode(cbuf, 0xB8 | dstenc);
2275     $$$emit32$src$$constant;
2276   %}
2277 
2278   enc_class load_immL32(rRegL dst, immL32 src)
2279   %{
2280     int dstenc = $dst$$reg;
2281     if (dstenc < 8) {
2282       emit_opcode(cbuf, Assembler::REX_W);
2283     } else {
2284       emit_opcode(cbuf, Assembler::REX_WB);
2285       dstenc -= 8;
2286     }
2287     emit_opcode(cbuf, 0xC7);
2288     emit_rm(cbuf, 0x03, 0x00, dstenc);
2289     $$$emit32$src$$constant;
2290   %}
2291 
2292   enc_class load_immP31(rRegP dst, immP32 src)
2293   %{
2294     // same as load_immI, but this time we care about zeroes in the high word
2295     int dstenc = $dst$$reg;
2296     if (dstenc >= 8) {
2297       emit_opcode(cbuf, Assembler::REX_B);
2298       dstenc -= 8;
2299     }
2300     emit_opcode(cbuf, 0xB8 | dstenc);
2301     $$$emit32$src$$constant;
2302   %}
2303 
2304   enc_class load_immP(rRegP dst, immP src)
2305   %{
2306     int dstenc = $dst$$reg;
2307     if (dstenc < 8) {
2308       emit_opcode(cbuf, Assembler::REX_W);
2309     } else {
2310       emit_opcode(cbuf, Assembler::REX_WB);
2311       dstenc -= 8;
2312     }
2313     emit_opcode(cbuf, 0xB8 | dstenc);
2314     // This next line should be generated from ADLC
2315     if ($src->constant_reloc() != relocInfo::none) {
2316       emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2317     } else {
2318       emit_d64(cbuf, $src$$constant);
2319     }
2320   %}
2321 
2322   enc_class Con32(immI src)
2323   %{
2324     // Output immediate
2325     $$$emit32$src$$constant;
2326   %}
2327 
2328   enc_class Con32F_as_bits(immF src)
2329   %{
2330     // Output Float immediate bits
2331     jfloat jf = $src$$constant;
2332     jint jf_as_bits = jint_cast(jf);
2333     emit_d32(cbuf, jf_as_bits);
2334   %}
2335 
2336   enc_class Con16(immI src)
2337   %{
2338     // Output immediate
2339     $$$emit16$src$$constant;
2340   %}
2341 
2342   // How is this different from Con32??? XXX
2343   enc_class Con_d32(immI src)
2344   %{
2345     emit_d32(cbuf,$src$$constant);
2346   %}
2347 
2348   enc_class conmemref (rRegP t1) %{    // Con32(storeImmI)
2349     // Output immediate memory reference
2350     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2351     emit_d32(cbuf, 0x00);
2352   %}
2353 
2354   enc_class lock_prefix()
2355   %{
2356     if (os::is_MP()) {
2357       emit_opcode(cbuf, 0xF0); // lock
2358     }
2359   %}
2360 
2361   enc_class REX_mem(memory mem)
2362   %{
2363     if ($mem$$base >= 8) {
2364       if ($mem$$index < 8) {
2365         emit_opcode(cbuf, Assembler::REX_B);
2366       } else {
2367         emit_opcode(cbuf, Assembler::REX_XB);
2368       }
2369     } else {
2370       if ($mem$$index >= 8) {
2371         emit_opcode(cbuf, Assembler::REX_X);
2372       }
2373     }
2374   %}
2375 
2376   enc_class REX_mem_wide(memory mem)
2377   %{
2378     if ($mem$$base >= 8) {
2379       if ($mem$$index < 8) {
2380         emit_opcode(cbuf, Assembler::REX_WB);
2381       } else {
2382         emit_opcode(cbuf, Assembler::REX_WXB);
2383       }
2384     } else {
2385       if ($mem$$index < 8) {
2386         emit_opcode(cbuf, Assembler::REX_W);
2387       } else {
2388         emit_opcode(cbuf, Assembler::REX_WX);
2389       }
2390     }
2391   %}
2392 
2393   // for byte regs
2394   enc_class REX_breg(rRegI reg)
2395   %{
2396     if ($reg$$reg >= 4) {
2397       emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2398     }
2399   %}
2400 
2401   // for byte regs
2402   enc_class REX_reg_breg(rRegI dst, rRegI src)
2403   %{
2404     if ($dst$$reg < 8) {
2405       if ($src$$reg >= 4) {
2406         emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2407       }
2408     } else {
2409       if ($src$$reg < 8) {
2410         emit_opcode(cbuf, Assembler::REX_R);
2411       } else {
2412         emit_opcode(cbuf, Assembler::REX_RB);
2413       }
2414     }
2415   %}
2416 
2417   // for byte regs
2418   enc_class REX_breg_mem(rRegI reg, memory mem)
2419   %{
2420     if ($reg$$reg < 8) {
2421       if ($mem$$base < 8) {
2422         if ($mem$$index >= 8) {
2423           emit_opcode(cbuf, Assembler::REX_X);
2424         } else if ($reg$$reg >= 4) {
2425           emit_opcode(cbuf, Assembler::REX);
2426         }
2427       } else {
2428         if ($mem$$index < 8) {
2429           emit_opcode(cbuf, Assembler::REX_B);
2430         } else {
2431           emit_opcode(cbuf, Assembler::REX_XB);
2432         }
2433       }
2434     } else {
2435       if ($mem$$base < 8) {
2436         if ($mem$$index < 8) {
2437           emit_opcode(cbuf, Assembler::REX_R);
2438         } else {
2439           emit_opcode(cbuf, Assembler::REX_RX);
2440         }
2441       } else {
2442         if ($mem$$index < 8) {
2443           emit_opcode(cbuf, Assembler::REX_RB);
2444         } else {
2445           emit_opcode(cbuf, Assembler::REX_RXB);
2446         }
2447       }
2448     }
2449   %}
2450 
2451   enc_class REX_reg(rRegI reg)
2452   %{
2453     if ($reg$$reg >= 8) {
2454       emit_opcode(cbuf, Assembler::REX_B);
2455     }
2456   %}
2457 
2458   enc_class REX_reg_wide(rRegI reg)
2459   %{
2460     if ($reg$$reg < 8) {
2461       emit_opcode(cbuf, Assembler::REX_W);
2462     } else {
2463       emit_opcode(cbuf, Assembler::REX_WB);
2464     }
2465   %}
2466 
2467   enc_class REX_reg_reg(rRegI dst, rRegI src)
2468   %{
2469     if ($dst$$reg < 8) {
2470       if ($src$$reg >= 8) {
2471         emit_opcode(cbuf, Assembler::REX_B);
2472       }
2473     } else {
2474       if ($src$$reg < 8) {
2475         emit_opcode(cbuf, Assembler::REX_R);
2476       } else {
2477         emit_opcode(cbuf, Assembler::REX_RB);
2478       }
2479     }
2480   %}
2481 
2482   enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2483   %{
2484     if ($dst$$reg < 8) {
2485       if ($src$$reg < 8) {
2486         emit_opcode(cbuf, Assembler::REX_W);
2487       } else {
2488         emit_opcode(cbuf, Assembler::REX_WB);
2489       }
2490     } else {
2491       if ($src$$reg < 8) {
2492         emit_opcode(cbuf, Assembler::REX_WR);
2493       } else {
2494         emit_opcode(cbuf, Assembler::REX_WRB);
2495       }
2496     }
2497   %}
2498 
2499   enc_class REX_reg_mem(rRegI reg, memory mem)
2500   %{
2501     if ($reg$$reg < 8) {
2502       if ($mem$$base < 8) {
2503         if ($mem$$index >= 8) {
2504           emit_opcode(cbuf, Assembler::REX_X);
2505         }
2506       } else {
2507         if ($mem$$index < 8) {
2508           emit_opcode(cbuf, Assembler::REX_B);
2509         } else {
2510           emit_opcode(cbuf, Assembler::REX_XB);
2511         }
2512       }
2513     } else {
2514       if ($mem$$base < 8) {
2515         if ($mem$$index < 8) {
2516           emit_opcode(cbuf, Assembler::REX_R);
2517         } else {
2518           emit_opcode(cbuf, Assembler::REX_RX);
2519         }
2520       } else {
2521         if ($mem$$index < 8) {
2522           emit_opcode(cbuf, Assembler::REX_RB);
2523         } else {
2524           emit_opcode(cbuf, Assembler::REX_RXB);
2525         }
2526       }
2527     }
2528   %}
2529 
2530   enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2531   %{
2532     if ($reg$$reg < 8) {
2533       if ($mem$$base < 8) {
2534         if ($mem$$index < 8) {
2535           emit_opcode(cbuf, Assembler::REX_W);
2536         } else {
2537           emit_opcode(cbuf, Assembler::REX_WX);
2538         }
2539       } else {
2540         if ($mem$$index < 8) {
2541           emit_opcode(cbuf, Assembler::REX_WB);
2542         } else {
2543           emit_opcode(cbuf, Assembler::REX_WXB);
2544         }
2545       }
2546     } else {
2547       if ($mem$$base < 8) {
2548         if ($mem$$index < 8) {
2549           emit_opcode(cbuf, Assembler::REX_WR);
2550         } else {
2551           emit_opcode(cbuf, Assembler::REX_WRX);
2552         }
2553       } else {
2554         if ($mem$$index < 8) {
2555           emit_opcode(cbuf, Assembler::REX_WRB);
2556         } else {
2557           emit_opcode(cbuf, Assembler::REX_WRXB);
2558         }
2559       }
2560     }
2561   %}
2562 
2563   enc_class reg_mem(rRegI ereg, memory mem)
2564   %{
2565     // High registers handle in encode_RegMem
2566     int reg = $ereg$$reg;
2567     int base = $mem$$base;
2568     int index = $mem$$index;
2569     int scale = $mem$$scale;
2570     int disp = $mem$$disp;
2571     relocInfo::relocType disp_reloc = $mem->disp_reloc();
2572 
2573     encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2574   %}
2575 
2576   enc_class RM_opc_mem(immI rm_opcode, memory mem)
2577   %{
2578     int rm_byte_opcode = $rm_opcode$$constant;
2579 
2580     // High registers handle in encode_RegMem
2581     int base = $mem$$base;
2582     int index = $mem$$index;
2583     int scale = $mem$$scale;
2584     int displace = $mem$$disp;
2585 
2586     relocInfo::relocType disp_reloc = $mem->disp_reloc();       // disp-as-oop when
2587                                             // working with static
2588                                             // globals
2589     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2590                   disp_reloc);
2591   %}
2592 
2593   enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2594   %{
2595     int reg_encoding = $dst$$reg;
2596     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
2597     int index        = 0x04;            // 0x04 indicates no index
2598     int scale        = 0x00;            // 0x00 indicates no scale
2599     int displace     = $src1$$constant; // 0x00 indicates no displacement
2600     relocInfo::relocType disp_reloc = relocInfo::none;
2601     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2602                   disp_reloc);
2603   %}
2604 
2605   enc_class neg_reg(rRegI dst)
2606   %{
2607     int dstenc = $dst$$reg;
2608     if (dstenc >= 8) {
2609       emit_opcode(cbuf, Assembler::REX_B);
2610       dstenc -= 8;
2611     }
2612     // NEG $dst
2613     emit_opcode(cbuf, 0xF7);
2614     emit_rm(cbuf, 0x3, 0x03, dstenc);
2615   %}
2616 
2617   enc_class neg_reg_wide(rRegI dst)
2618   %{
2619     int dstenc = $dst$$reg;
2620     if (dstenc < 8) {
2621       emit_opcode(cbuf, Assembler::REX_W);
2622     } else {
2623       emit_opcode(cbuf, Assembler::REX_WB);
2624       dstenc -= 8;
2625     }
2626     // NEG $dst
2627     emit_opcode(cbuf, 0xF7);
2628     emit_rm(cbuf, 0x3, 0x03, dstenc);
2629   %}
2630 
2631   enc_class setLT_reg(rRegI dst)
2632   %{
2633     int dstenc = $dst$$reg;
2634     if (dstenc >= 8) {
2635       emit_opcode(cbuf, Assembler::REX_B);
2636       dstenc -= 8;
2637     } else if (dstenc >= 4) {
2638       emit_opcode(cbuf, Assembler::REX);
2639     }
2640     // SETLT $dst
2641     emit_opcode(cbuf, 0x0F);
2642     emit_opcode(cbuf, 0x9C);
2643     emit_rm(cbuf, 0x3, 0x0, dstenc);
2644   %}
2645 
2646   enc_class setNZ_reg(rRegI dst)
2647   %{
2648     int dstenc = $dst$$reg;
2649     if (dstenc >= 8) {
2650       emit_opcode(cbuf, Assembler::REX_B);
2651       dstenc -= 8;
2652     } else if (dstenc >= 4) {
2653       emit_opcode(cbuf, Assembler::REX);
2654     }
2655     // SETNZ $dst
2656     emit_opcode(cbuf, 0x0F);
2657     emit_opcode(cbuf, 0x95);
2658     emit_rm(cbuf, 0x3, 0x0, dstenc);
2659   %}
2660 
2661 
2662   // Compare the lonogs and set -1, 0, or 1 into dst
2663   enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2664   %{
2665     int src1enc = $src1$$reg;
2666     int src2enc = $src2$$reg;
2667     int dstenc = $dst$$reg;
2668 
2669     // cmpq $src1, $src2
2670     if (src1enc < 8) {
2671       if (src2enc < 8) {
2672         emit_opcode(cbuf, Assembler::REX_W);
2673       } else {
2674         emit_opcode(cbuf, Assembler::REX_WB);
2675       }
2676     } else {
2677       if (src2enc < 8) {
2678         emit_opcode(cbuf, Assembler::REX_WR);
2679       } else {
2680         emit_opcode(cbuf, Assembler::REX_WRB);
2681       }
2682     }
2683     emit_opcode(cbuf, 0x3B);
2684     emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2685 
2686     // movl $dst, -1
2687     if (dstenc >= 8) {
2688       emit_opcode(cbuf, Assembler::REX_B);
2689     }
2690     emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2691     emit_d32(cbuf, -1);
2692 
2693     // jl,s done
2694     emit_opcode(cbuf, 0x7C);
2695     emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2696 
2697     // setne $dst
2698     if (dstenc >= 4) {
2699       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2700     }
2701     emit_opcode(cbuf, 0x0F);
2702     emit_opcode(cbuf, 0x95);
2703     emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2704 
2705     // movzbl $dst, $dst
2706     if (dstenc >= 4) {
2707       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2708     }
2709     emit_opcode(cbuf, 0x0F);
2710     emit_opcode(cbuf, 0xB6);
2711     emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2712   %}
2713 
2714   enc_class Push_ResultXD(regD dst) %{
2715     MacroAssembler _masm(&cbuf);
2716     __ fstp_d(Address(rsp, 0));
2717     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2718     __ addptr(rsp, 8);
2719   %}
2720 
2721   enc_class Push_SrcXD(regD src) %{
2722     MacroAssembler _masm(&cbuf);
2723     __ subptr(rsp, 8);
2724     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2725     __ fld_d(Address(rsp, 0));
2726   %}
2727 
2728 
2729   enc_class enc_rethrow()
2730   %{
2731     cbuf.set_insts_mark();
2732     emit_opcode(cbuf, 0xE9); // jmp entry
2733     emit_d32_reloc(cbuf,
2734                    (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2735                    runtime_call_Relocation::spec(),
2736                    RELOC_DISP32);
2737   %}
2738 
2739 %}
2740 
2741 
2742 
2743 //----------FRAME--------------------------------------------------------------
2744 // Definition of frame structure and management information.
2745 //
2746 //  S T A C K   L A Y O U T    Allocators stack-slot number
2747 //                             |   (to get allocators register number
2748 //  G  Owned by    |        |  v    add OptoReg::stack0())
2749 //  r   CALLER     |        |
2750 //  o     |        +--------+      pad to even-align allocators stack-slot
2751 //  w     V        |  pad0  |        numbers; owned by CALLER
2752 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
2753 //  h     ^        |   in   |  5
2754 //        |        |  args  |  4   Holes in incoming args owned by SELF
2755 //  |     |        |        |  3
2756 //  |     |        +--------+
2757 //  V     |        | old out|      Empty on Intel, window on Sparc
2758 //        |    old |preserve|      Must be even aligned.
2759 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
2760 //        |        |   in   |  3   area for Intel ret address
2761 //     Owned by    |preserve|      Empty on Sparc.
2762 //       SELF      +--------+
2763 //        |        |  pad2  |  2   pad to align old SP
2764 //        |        +--------+  1
2765 //        |        | locks  |  0
2766 //        |        +--------+----> OptoReg::stack0(), even aligned
2767 //        |        |  pad1  | 11   pad to align new SP
2768 //        |        +--------+
2769 //        |        |        | 10
2770 //        |        | spills |  9   spills
2771 //        V        |        |  8   (pad0 slot for callee)
2772 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
2773 //        ^        |  out   |  7
2774 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
2775 //     Owned by    +--------+
2776 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
2777 //        |    new |preserve|      Must be even-aligned.
2778 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
2779 //        |        |        |
2780 //
2781 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
2782 //         known from SELF's arguments and the Java calling convention.
2783 //         Region 6-7 is determined per call site.
2784 // Note 2: If the calling convention leaves holes in the incoming argument
2785 //         area, those holes are owned by SELF.  Holes in the outgoing area
2786 //         are owned by the CALLEE.  Holes should not be nessecary in the
2787 //         incoming area, as the Java calling convention is completely under
2788 //         the control of the AD file.  Doubles can be sorted and packed to
2789 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
2790 //         varargs C calling conventions.
2791 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
2792 //         even aligned with pad0 as needed.
2793 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
2794 //         region 6-11 is even aligned; it may be padded out more so that
2795 //         the region from SP to FP meets the minimum stack alignment.
2796 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2797 //         alignment.  Region 11, pad1, may be dynamically extended so that
2798 //         SP meets the minimum alignment.
2799 
2800 frame
2801 %{
2802   // What direction does stack grow in (assumed to be same for C & Java)
2803   stack_direction(TOWARDS_LOW);
2804 
2805   // These three registers define part of the calling convention
2806   // between compiled code and the interpreter.
2807   inline_cache_reg(RAX);                // Inline Cache Register
2808   interpreter_method_oop_reg(RBX);      // Method Oop Register when
2809                                         // calling interpreter
2810 
2811   // Optional: name the operand used by cisc-spilling to access
2812   // [stack_pointer + offset]
2813   cisc_spilling_operand_name(indOffset32);
2814 
2815   // Number of stack slots consumed by locking an object
2816   sync_stack_slots(2);
2817 
2818   // Compiled code's Frame Pointer
2819   frame_pointer(RSP);
2820 
2821   // Interpreter stores its frame pointer in a register which is
2822   // stored to the stack by I2CAdaptors.
2823   // I2CAdaptors convert from interpreted java to compiled java.
2824   interpreter_frame_pointer(RBP);
2825 
2826   // Stack alignment requirement
2827   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2828 
2829   // Number of stack slots between incoming argument block and the start of
2830   // a new frame.  The PROLOG must add this many slots to the stack.  The
2831   // EPILOG must remove this many slots.  amd64 needs two slots for
2832   // return address.
2833   in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2834 
2835   // Number of outgoing stack slots killed above the out_preserve_stack_slots
2836   // for calls to C.  Supports the var-args backing area for register parms.
2837   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2838 
2839   // The after-PROLOG location of the return address.  Location of
2840   // return address specifies a type (REG or STACK) and a number
2841   // representing the register number (i.e. - use a register name) or
2842   // stack slot.
2843   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2844   // Otherwise, it is above the locks and verification slot and alignment word
2845   return_addr(STACK - 2 +
2846               align_up((Compile::current()->in_preserve_stack_slots() +
2847                         Compile::current()->fixed_slots()),
2848                        stack_alignment_in_slots()));
2849 
2850   // Body of function which returns an integer array locating
2851   // arguments either in registers or in stack slots.  Passed an array
2852   // of ideal registers called "sig" and a "length" count.  Stack-slot
2853   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2854   // arguments for a CALLEE.  Incoming stack arguments are
2855   // automatically biased by the preserve_stack_slots field above.
2856 
2857   calling_convention
2858   %{
2859     // No difference between ingoing/outgoing just pass false
2860     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2861   %}
2862 
2863   c_calling_convention
2864   %{
2865     // This is obviously always outgoing
2866     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2867   %}
2868 
2869   // Location of compiled Java return values.  Same as C for now.
2870   return_value
2871   %{
2872     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2873            "only return normal values");
2874 
2875     static const int lo[Op_RegL + 1] = {
2876       0,
2877       0,
2878       RAX_num,  // Op_RegN
2879       RAX_num,  // Op_RegI
2880       RAX_num,  // Op_RegP
2881       XMM0_num, // Op_RegF
2882       XMM0_num, // Op_RegD
2883       RAX_num   // Op_RegL
2884     };
2885     static const int hi[Op_RegL + 1] = {
2886       0,
2887       0,
2888       OptoReg::Bad, // Op_RegN
2889       OptoReg::Bad, // Op_RegI
2890       RAX_H_num,    // Op_RegP
2891       OptoReg::Bad, // Op_RegF
2892       XMM0b_num,    // Op_RegD
2893       RAX_H_num     // Op_RegL
2894     };
2895     // Excluded flags and vector registers.
2896     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2897     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2898   %}
2899 %}
2900 
2901 //----------ATTRIBUTES---------------------------------------------------------
2902 //----------Operand Attributes-------------------------------------------------
2903 op_attrib op_cost(0);        // Required cost attribute
2904 
2905 //----------Instruction Attributes---------------------------------------------
2906 ins_attrib ins_cost(100);       // Required cost attribute
2907 ins_attrib ins_size(8);         // Required size attribute (in bits)
2908 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2909                                 // a non-matching short branch variant
2910                                 // of some long branch?
2911 ins_attrib ins_alignment(1);    // Required alignment attribute (must
2912                                 // be a power of 2) specifies the
2913                                 // alignment that some part of the
2914                                 // instruction (not necessarily the
2915                                 // start) requires.  If > 1, a
2916                                 // compute_padding() function must be
2917                                 // provided for the instruction
2918 
2919 //----------OPERANDS-----------------------------------------------------------
2920 // Operand definitions must precede instruction definitions for correct parsing
2921 // in the ADLC because operands constitute user defined types which are used in
2922 // instruction definitions.
2923 
2924 //----------Simple Operands----------------------------------------------------
2925 // Immediate Operands
2926 // Integer Immediate
2927 operand immI()
2928 %{
2929   match(ConI);
2930 
2931   op_cost(10);
2932   format %{ %}
2933   interface(CONST_INTER);
2934 %}
2935 
2936 // Constant for test vs zero
2937 operand immI0()
2938 %{
2939   predicate(n->get_int() == 0);
2940   match(ConI);
2941 
2942   op_cost(0);
2943   format %{ %}
2944   interface(CONST_INTER);
2945 %}
2946 
2947 // Constant for increment
2948 operand immI1()
2949 %{
2950   predicate(n->get_int() == 1);
2951   match(ConI);
2952 
2953   op_cost(0);
2954   format %{ %}
2955   interface(CONST_INTER);
2956 %}
2957 
2958 // Constant for decrement
2959 operand immI_M1()
2960 %{
2961   predicate(n->get_int() == -1);
2962   match(ConI);
2963 
2964   op_cost(0);
2965   format %{ %}
2966   interface(CONST_INTER);
2967 %}
2968 
2969 // Valid scale values for addressing modes
2970 operand immI2()
2971 %{
2972   predicate(0 <= n->get_int() && (n->get_int() <= 3));
2973   match(ConI);
2974 
2975   format %{ %}
2976   interface(CONST_INTER);
2977 %}
2978 
2979 operand immI8()
2980 %{
2981   predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2982   match(ConI);
2983 
2984   op_cost(5);
2985   format %{ %}
2986   interface(CONST_INTER);
2987 %}
2988 
2989 operand immU8()
2990 %{
2991   predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2992   match(ConI);
2993 
2994   op_cost(5);
2995   format %{ %}
2996   interface(CONST_INTER);
2997 %}
2998 
2999 operand immI16()
3000 %{
3001   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3002   match(ConI);
3003 
3004   op_cost(10);
3005   format %{ %}
3006   interface(CONST_INTER);
3007 %}
3008 
3009 // Int Immediate non-negative
3010 operand immU31()
3011 %{
3012   predicate(n->get_int() >= 0);
3013   match(ConI);
3014 
3015   op_cost(0);
3016   format %{ %}
3017   interface(CONST_INTER);
3018 %}
3019 
3020 // Constant for long shifts
3021 operand immI_32()
3022 %{
3023   predicate( n->get_int() == 32 );
3024   match(ConI);
3025 
3026   op_cost(0);
3027   format %{ %}
3028   interface(CONST_INTER);
3029 %}
3030 
3031 // Constant for long shifts
3032 operand immI_64()
3033 %{
3034   predicate( n->get_int() == 64 );
3035   match(ConI);
3036 
3037   op_cost(0);
3038   format %{ %}
3039   interface(CONST_INTER);
3040 %}
3041 
3042 // Pointer Immediate
3043 operand immP()
3044 %{
3045   match(ConP);
3046 
3047   op_cost(10);
3048   format %{ %}
3049   interface(CONST_INTER);
3050 %}
3051 
3052 // NULL Pointer Immediate
3053 operand immP0()
3054 %{
3055   predicate(n->get_ptr() == 0);
3056   match(ConP);
3057 
3058   op_cost(5);
3059   format %{ %}
3060   interface(CONST_INTER);
3061 %}
3062 
3063 // Pointer Immediate
3064 operand immN() %{
3065   match(ConN);
3066 
3067   op_cost(10);
3068   format %{ %}
3069   interface(CONST_INTER);
3070 %}
3071 
3072 operand immNKlass() %{
3073   match(ConNKlass);
3074 
3075   op_cost(10);
3076   format %{ %}
3077   interface(CONST_INTER);
3078 %}
3079 
3080 // NULL Pointer Immediate
3081 operand immN0() %{
3082   predicate(n->get_narrowcon() == 0);
3083   match(ConN);
3084 
3085   op_cost(5);
3086   format %{ %}
3087   interface(CONST_INTER);
3088 %}
3089 
3090 operand immP31()
3091 %{
3092   predicate(n->as_Type()->type()->reloc() == relocInfo::none
3093             && (n->get_ptr() >> 31) == 0);
3094   match(ConP);
3095 
3096   op_cost(5);
3097   format %{ %}
3098   interface(CONST_INTER);
3099 %}
3100 
3101 
3102 // Long Immediate
3103 operand immL()
3104 %{
3105   match(ConL);
3106 
3107   op_cost(20);
3108   format %{ %}
3109   interface(CONST_INTER);
3110 %}
3111 
3112 // Long Immediate 8-bit
3113 operand immL8()
3114 %{
3115   predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3116   match(ConL);
3117 
3118   op_cost(5);
3119   format %{ %}
3120   interface(CONST_INTER);
3121 %}
3122 
3123 // Long Immediate 32-bit unsigned
3124 operand immUL32()
3125 %{
3126   predicate(n->get_long() == (unsigned int) (n->get_long()));
3127   match(ConL);
3128 
3129   op_cost(10);
3130   format %{ %}
3131   interface(CONST_INTER);
3132 %}
3133 
3134 // Long Immediate 32-bit signed
3135 operand immL32()
3136 %{
3137   predicate(n->get_long() == (int) (n->get_long()));
3138   match(ConL);
3139 
3140   op_cost(15);
3141   format %{ %}
3142   interface(CONST_INTER);
3143 %}
3144 
3145 // Long Immediate zero
3146 operand immL0()
3147 %{
3148   predicate(n->get_long() == 0L);
3149   match(ConL);
3150 
3151   op_cost(10);
3152   format %{ %}
3153   interface(CONST_INTER);
3154 %}
3155 
3156 // Constant for increment
3157 operand immL1()
3158 %{
3159   predicate(n->get_long() == 1);
3160   match(ConL);
3161 
3162   format %{ %}
3163   interface(CONST_INTER);
3164 %}
3165 
3166 // Constant for decrement
3167 operand immL_M1()
3168 %{
3169   predicate(n->get_long() == -1);
3170   match(ConL);
3171 
3172   format %{ %}
3173   interface(CONST_INTER);
3174 %}
3175 
3176 // Long Immediate: the value 10
3177 operand immL10()
3178 %{
3179   predicate(n->get_long() == 10);
3180   match(ConL);
3181 
3182   format %{ %}
3183   interface(CONST_INTER);
3184 %}
3185 
3186 // Long immediate from 0 to 127.
3187 // Used for a shorter form of long mul by 10.
3188 operand immL_127()
3189 %{
3190   predicate(0 <= n->get_long() && n->get_long() < 0x80);
3191   match(ConL);
3192 
3193   op_cost(10);
3194   format %{ %}
3195   interface(CONST_INTER);
3196 %}
3197 
3198 // Long Immediate: low 32-bit mask
3199 operand immL_32bits()
3200 %{
3201   predicate(n->get_long() == 0xFFFFFFFFL);
3202   match(ConL);
3203   op_cost(20);
3204 
3205   format %{ %}
3206   interface(CONST_INTER);
3207 %}
3208 
3209 // Float Immediate zero
3210 operand immF0()
3211 %{
3212   predicate(jint_cast(n->getf()) == 0);
3213   match(ConF);
3214 
3215   op_cost(5);
3216   format %{ %}
3217   interface(CONST_INTER);
3218 %}
3219 
3220 // Float Immediate
3221 operand immF()
3222 %{
3223   match(ConF);
3224 
3225   op_cost(15);
3226   format %{ %}
3227   interface(CONST_INTER);
3228 %}
3229 
3230 // Double Immediate zero
3231 operand immD0()
3232 %{
3233   predicate(jlong_cast(n->getd()) == 0);
3234   match(ConD);
3235 
3236   op_cost(5);
3237   format %{ %}
3238   interface(CONST_INTER);
3239 %}
3240 
3241 // Double Immediate
3242 operand immD()
3243 %{
3244   match(ConD);
3245 
3246   op_cost(15);
3247   format %{ %}
3248   interface(CONST_INTER);
3249 %}
3250 
3251 // Immediates for special shifts (sign extend)
3252 
3253 // Constants for increment
3254 operand immI_16()
3255 %{
3256   predicate(n->get_int() == 16);
3257   match(ConI);
3258 
3259   format %{ %}
3260   interface(CONST_INTER);
3261 %}
3262 
3263 operand immI_24()
3264 %{
3265   predicate(n->get_int() == 24);
3266   match(ConI);
3267 
3268   format %{ %}
3269   interface(CONST_INTER);
3270 %}
3271 
3272 // Constant for byte-wide masking
3273 operand immI_255()
3274 %{
3275   predicate(n->get_int() == 255);
3276   match(ConI);
3277 
3278   format %{ %}
3279   interface(CONST_INTER);
3280 %}
3281 
3282 // Constant for short-wide masking
3283 operand immI_65535()
3284 %{
3285   predicate(n->get_int() == 65535);
3286   match(ConI);
3287 
3288   format %{ %}
3289   interface(CONST_INTER);
3290 %}
3291 
3292 // Constant for byte-wide masking
3293 operand immL_255()
3294 %{
3295   predicate(n->get_long() == 255);
3296   match(ConL);
3297 
3298   format %{ %}
3299   interface(CONST_INTER);
3300 %}
3301 
3302 // Constant for short-wide masking
3303 operand immL_65535()
3304 %{
3305   predicate(n->get_long() == 65535);
3306   match(ConL);
3307 
3308   format %{ %}
3309   interface(CONST_INTER);
3310 %}
3311 
3312 // Register Operands
3313 // Integer Register
3314 operand rRegI()
3315 %{
3316   constraint(ALLOC_IN_RC(int_reg));
3317   match(RegI);
3318 
3319   match(rax_RegI);
3320   match(rbx_RegI);
3321   match(rcx_RegI);
3322   match(rdx_RegI);
3323   match(rdi_RegI);
3324 
3325   format %{ %}
3326   interface(REG_INTER);
3327 %}
3328 
3329 // Special Registers
3330 operand rax_RegI()
3331 %{
3332   constraint(ALLOC_IN_RC(int_rax_reg));
3333   match(RegI);
3334   match(rRegI);
3335 
3336   format %{ "RAX" %}
3337   interface(REG_INTER);
3338 %}
3339 
3340 // Special Registers
3341 operand rbx_RegI()
3342 %{
3343   constraint(ALLOC_IN_RC(int_rbx_reg));
3344   match(RegI);
3345   match(rRegI);
3346 
3347   format %{ "RBX" %}
3348   interface(REG_INTER);
3349 %}
3350 
3351 operand rcx_RegI()
3352 %{
3353   constraint(ALLOC_IN_RC(int_rcx_reg));
3354   match(RegI);
3355   match(rRegI);
3356 
3357   format %{ "RCX" %}
3358   interface(REG_INTER);
3359 %}
3360 
3361 operand rdx_RegI()
3362 %{
3363   constraint(ALLOC_IN_RC(int_rdx_reg));
3364   match(RegI);
3365   match(rRegI);
3366 
3367   format %{ "RDX" %}
3368   interface(REG_INTER);
3369 %}
3370 
3371 operand rdi_RegI()
3372 %{
3373   constraint(ALLOC_IN_RC(int_rdi_reg));
3374   match(RegI);
3375   match(rRegI);
3376 
3377   format %{ "RDI" %}
3378   interface(REG_INTER);
3379 %}
3380 
3381 operand no_rcx_RegI()
3382 %{
3383   constraint(ALLOC_IN_RC(int_no_rcx_reg));
3384   match(RegI);
3385   match(rax_RegI);
3386   match(rbx_RegI);
3387   match(rdx_RegI);
3388   match(rdi_RegI);
3389 
3390   format %{ %}
3391   interface(REG_INTER);
3392 %}
3393 
3394 operand no_rax_rdx_RegI()
3395 %{
3396   constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3397   match(RegI);
3398   match(rbx_RegI);
3399   match(rcx_RegI);
3400   match(rdi_RegI);
3401 
3402   format %{ %}
3403   interface(REG_INTER);
3404 %}
3405 
3406 // Pointer Register
3407 operand any_RegP()
3408 %{
3409   constraint(ALLOC_IN_RC(any_reg));
3410   match(RegP);
3411   match(rax_RegP);
3412   match(rbx_RegP);
3413   match(rdi_RegP);
3414   match(rsi_RegP);
3415   match(rbp_RegP);
3416   match(r15_RegP);
3417   match(rRegP);
3418 
3419   format %{ %}
3420   interface(REG_INTER);
3421 %}
3422 
3423 operand rRegP()
3424 %{
3425   constraint(ALLOC_IN_RC(ptr_reg));
3426   match(RegP);
3427   match(rax_RegP);
3428   match(rbx_RegP);
3429   match(rdi_RegP);
3430   match(rsi_RegP);
3431   match(rbp_RegP);  // See Q&A below about
3432   match(r15_RegP);  // r15_RegP and rbp_RegP.
3433 
3434   format %{ %}
3435   interface(REG_INTER);
3436 %}
3437 
3438 operand rRegN() %{
3439   constraint(ALLOC_IN_RC(int_reg));
3440   match(RegN);
3441 
3442   format %{ %}
3443   interface(REG_INTER);
3444 %}
3445 
3446 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3447 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3448 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3449 // The output of an instruction is controlled by the allocator, which respects
3450 // register class masks, not match rules.  Unless an instruction mentions
3451 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3452 // by the allocator as an input.
3453 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3454 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3455 // result, RBP is not included in the output of the instruction either.
3456 
3457 operand no_rax_RegP()
3458 %{
3459   constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3460   match(RegP);
3461   match(rbx_RegP);
3462   match(rsi_RegP);
3463   match(rdi_RegP);
3464 
3465   format %{ %}
3466   interface(REG_INTER);
3467 %}
3468 
3469 // This operand is not allowed to use RBP even if
3470 // RBP is not used to hold the frame pointer.
3471 operand no_rbp_RegP()
3472 %{
3473   constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3474   match(RegP);
3475   match(rbx_RegP);
3476   match(rsi_RegP);
3477   match(rdi_RegP);
3478 
3479   format %{ %}
3480   interface(REG_INTER);
3481 %}
3482 
3483 operand no_rax_rbx_RegP()
3484 %{
3485   constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3486   match(RegP);
3487   match(rsi_RegP);
3488   match(rdi_RegP);
3489 
3490   format %{ %}
3491   interface(REG_INTER);
3492 %}
3493 
3494 // Special Registers
3495 // Return a pointer value
3496 operand rax_RegP()
3497 %{
3498   constraint(ALLOC_IN_RC(ptr_rax_reg));
3499   match(RegP);
3500   match(rRegP);
3501 
3502   format %{ %}
3503   interface(REG_INTER);
3504 %}
3505 
3506 // Special Registers
3507 // Return a compressed pointer value
3508 operand rax_RegN()
3509 %{
3510   constraint(ALLOC_IN_RC(int_rax_reg));
3511   match(RegN);
3512   match(rRegN);
3513 
3514   format %{ %}
3515   interface(REG_INTER);
3516 %}
3517 
3518 // Used in AtomicAdd
3519 operand rbx_RegP()
3520 %{
3521   constraint(ALLOC_IN_RC(ptr_rbx_reg));
3522   match(RegP);
3523   match(rRegP);
3524 
3525   format %{ %}
3526   interface(REG_INTER);
3527 %}
3528 
3529 operand rsi_RegP()
3530 %{
3531   constraint(ALLOC_IN_RC(ptr_rsi_reg));
3532   match(RegP);
3533   match(rRegP);
3534 
3535   format %{ %}
3536   interface(REG_INTER);
3537 %}
3538 
3539 // Used in rep stosq
3540 operand rdi_RegP()
3541 %{
3542   constraint(ALLOC_IN_RC(ptr_rdi_reg));
3543   match(RegP);
3544   match(rRegP);
3545 
3546   format %{ %}
3547   interface(REG_INTER);
3548 %}
3549 
3550 operand r15_RegP()
3551 %{
3552   constraint(ALLOC_IN_RC(ptr_r15_reg));
3553   match(RegP);
3554   match(rRegP);
3555 
3556   format %{ %}
3557   interface(REG_INTER);
3558 %}
3559 
3560 operand rex_RegP()
3561 %{
3562   constraint(ALLOC_IN_RC(ptr_rex_reg));
3563   match(RegP);
3564   match(rRegP);
3565 
3566   format %{ %}
3567   interface(REG_INTER);
3568 %}
3569 
3570 operand rRegL()
3571 %{
3572   constraint(ALLOC_IN_RC(long_reg));
3573   match(RegL);
3574   match(rax_RegL);
3575   match(rdx_RegL);
3576 
3577   format %{ %}
3578   interface(REG_INTER);
3579 %}
3580 
3581 // Special Registers
3582 operand no_rax_rdx_RegL()
3583 %{
3584   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3585   match(RegL);
3586   match(rRegL);
3587 
3588   format %{ %}
3589   interface(REG_INTER);
3590 %}
3591 
3592 operand no_rax_RegL()
3593 %{
3594   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3595   match(RegL);
3596   match(rRegL);
3597   match(rdx_RegL);
3598 
3599   format %{ %}
3600   interface(REG_INTER);
3601 %}
3602 
3603 operand no_rcx_RegL()
3604 %{
3605   constraint(ALLOC_IN_RC(long_no_rcx_reg));
3606   match(RegL);
3607   match(rRegL);
3608 
3609   format %{ %}
3610   interface(REG_INTER);
3611 %}
3612 
3613 operand rax_RegL()
3614 %{
3615   constraint(ALLOC_IN_RC(long_rax_reg));
3616   match(RegL);
3617   match(rRegL);
3618 
3619   format %{ "RAX" %}
3620   interface(REG_INTER);
3621 %}
3622 
3623 operand rcx_RegL()
3624 %{
3625   constraint(ALLOC_IN_RC(long_rcx_reg));
3626   match(RegL);
3627   match(rRegL);
3628 
3629   format %{ %}
3630   interface(REG_INTER);
3631 %}
3632 
3633 operand rdx_RegL()
3634 %{
3635   constraint(ALLOC_IN_RC(long_rdx_reg));
3636   match(RegL);
3637   match(rRegL);
3638 
3639   format %{ %}
3640   interface(REG_INTER);
3641 %}
3642 
3643 // Flags register, used as output of compare instructions
3644 operand rFlagsReg()
3645 %{
3646   constraint(ALLOC_IN_RC(int_flags));
3647   match(RegFlags);
3648 
3649   format %{ "RFLAGS" %}
3650   interface(REG_INTER);
3651 %}
3652 
3653 // Flags register, used as output of FLOATING POINT compare instructions
3654 operand rFlagsRegU()
3655 %{
3656   constraint(ALLOC_IN_RC(int_flags));
3657   match(RegFlags);
3658 
3659   format %{ "RFLAGS_U" %}
3660   interface(REG_INTER);
3661 %}
3662 
3663 operand rFlagsRegUCF() %{
3664   constraint(ALLOC_IN_RC(int_flags));
3665   match(RegFlags);
3666   predicate(false);
3667 
3668   format %{ "RFLAGS_U_CF" %}
3669   interface(REG_INTER);
3670 %}
3671 
3672 // Float register operands
3673 operand regF() %{
3674    constraint(ALLOC_IN_RC(float_reg));
3675    match(RegF);
3676 
3677    format %{ %}
3678    interface(REG_INTER);
3679 %}
3680 
3681 // Float register operands
3682 operand vlRegF() %{
3683    constraint(ALLOC_IN_RC(float_reg_vl));
3684    match(RegF);
3685 
3686    format %{ %}
3687    interface(REG_INTER);
3688 %}
3689 
3690 // Double register operands
3691 operand regD() %{
3692    constraint(ALLOC_IN_RC(double_reg));
3693    match(RegD);
3694 
3695    format %{ %}
3696    interface(REG_INTER);
3697 %}
3698 
3699 // Double register operands
3700 operand vlRegD() %{
3701    constraint(ALLOC_IN_RC(double_reg_vl));
3702    match(RegD);
3703 
3704    format %{ %}
3705    interface(REG_INTER);
3706 %}
3707 
3708 // Vectors
3709 operand vecS() %{
3710   constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3711   match(VecS);
3712 
3713   format %{ %}
3714   interface(REG_INTER);
3715 %}
3716 
3717 // Vectors
3718 operand legVecS() %{
3719   constraint(ALLOC_IN_RC(vectors_reg_legacy));
3720   match(VecS);
3721 
3722   format %{ %}
3723   interface(REG_INTER);
3724 %}
3725 
3726 operand vecD() %{
3727   constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3728   match(VecD);
3729 
3730   format %{ %}
3731   interface(REG_INTER);
3732 %}
3733 
3734 operand legVecD() %{
3735   constraint(ALLOC_IN_RC(vectord_reg_legacy));
3736   match(VecD);
3737 
3738   format %{ %}
3739   interface(REG_INTER);
3740 %}
3741 
3742 operand vecX() %{
3743   constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3744   match(VecX);
3745 
3746   format %{ %}
3747   interface(REG_INTER);
3748 %}
3749 
3750 operand legVecX() %{
3751   constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3752   match(VecX);
3753 
3754   format %{ %}
3755   interface(REG_INTER);
3756 %}
3757 
3758 operand vecY() %{
3759   constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3760   match(VecY);
3761 
3762   format %{ %}
3763   interface(REG_INTER);
3764 %}
3765 
3766 operand legVecY() %{
3767   constraint(ALLOC_IN_RC(vectory_reg_legacy));
3768   match(VecY);
3769 
3770   format %{ %}
3771   interface(REG_INTER);
3772 %}
3773 
3774 //----------Memory Operands----------------------------------------------------
3775 // Direct Memory Operand
3776 // operand direct(immP addr)
3777 // %{
3778 //   match(addr);
3779 
3780 //   format %{ "[$addr]" %}
3781 //   interface(MEMORY_INTER) %{
3782 //     base(0xFFFFFFFF);
3783 //     index(0x4);
3784 //     scale(0x0);
3785 //     disp($addr);
3786 //   %}
3787 // %}
3788 
3789 // Indirect Memory Operand
3790 operand indirect(any_RegP reg)
3791 %{
3792   constraint(ALLOC_IN_RC(ptr_reg));
3793   match(reg);
3794 
3795   format %{ "[$reg]" %}
3796   interface(MEMORY_INTER) %{
3797     base($reg);
3798     index(0x4);
3799     scale(0x0);
3800     disp(0x0);
3801   %}
3802 %}
3803 
3804 // Indirect Memory Plus Short Offset Operand
3805 operand indOffset8(any_RegP reg, immL8 off)
3806 %{
3807   constraint(ALLOC_IN_RC(ptr_reg));
3808   match(AddP reg off);
3809 
3810   format %{ "[$reg + $off (8-bit)]" %}
3811   interface(MEMORY_INTER) %{
3812     base($reg);
3813     index(0x4);
3814     scale(0x0);
3815     disp($off);
3816   %}
3817 %}
3818 
3819 // Indirect Memory Plus Long Offset Operand
3820 operand indOffset32(any_RegP reg, immL32 off)
3821 %{
3822   constraint(ALLOC_IN_RC(ptr_reg));
3823   match(AddP reg off);
3824 
3825   format %{ "[$reg + $off (32-bit)]" %}
3826   interface(MEMORY_INTER) %{
3827     base($reg);
3828     index(0x4);
3829     scale(0x0);
3830     disp($off);
3831   %}
3832 %}
3833 
3834 // Indirect Memory Plus Index Register Plus Offset Operand
3835 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3836 %{
3837   constraint(ALLOC_IN_RC(ptr_reg));
3838   match(AddP (AddP reg lreg) off);
3839 
3840   op_cost(10);
3841   format %{"[$reg + $off + $lreg]" %}
3842   interface(MEMORY_INTER) %{
3843     base($reg);
3844     index($lreg);
3845     scale(0x0);
3846     disp($off);
3847   %}
3848 %}
3849 
3850 // Indirect Memory Plus Index Register Plus Offset Operand
3851 operand indIndex(any_RegP reg, rRegL lreg)
3852 %{
3853   constraint(ALLOC_IN_RC(ptr_reg));
3854   match(AddP reg lreg);
3855 
3856   op_cost(10);
3857   format %{"[$reg + $lreg]" %}
3858   interface(MEMORY_INTER) %{
3859     base($reg);
3860     index($lreg);
3861     scale(0x0);
3862     disp(0x0);
3863   %}
3864 %}
3865 
3866 // Indirect Memory Times Scale Plus Index Register
3867 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3868 %{
3869   constraint(ALLOC_IN_RC(ptr_reg));
3870   match(AddP reg (LShiftL lreg scale));
3871 
3872   op_cost(10);
3873   format %{"[$reg + $lreg << $scale]" %}
3874   interface(MEMORY_INTER) %{
3875     base($reg);
3876     index($lreg);
3877     scale($scale);
3878     disp(0x0);
3879   %}
3880 %}
3881 
3882 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3883 %{
3884   constraint(ALLOC_IN_RC(ptr_reg));
3885   predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3886   match(AddP reg (LShiftL (ConvI2L idx) scale));
3887 
3888   op_cost(10);
3889   format %{"[$reg + pos $idx << $scale]" %}
3890   interface(MEMORY_INTER) %{
3891     base($reg);
3892     index($idx);
3893     scale($scale);
3894     disp(0x0);
3895   %}
3896 %}
3897 
3898 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3899 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3900 %{
3901   constraint(ALLOC_IN_RC(ptr_reg));
3902   match(AddP (AddP reg (LShiftL lreg scale)) off);
3903 
3904   op_cost(10);
3905   format %{"[$reg + $off + $lreg << $scale]" %}
3906   interface(MEMORY_INTER) %{
3907     base($reg);
3908     index($lreg);
3909     scale($scale);
3910     disp($off);
3911   %}
3912 %}
3913 
3914 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3915 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3916 %{
3917   constraint(ALLOC_IN_RC(ptr_reg));
3918   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3919   match(AddP (AddP reg (ConvI2L idx)) off);
3920 
3921   op_cost(10);
3922   format %{"[$reg + $off + $idx]" %}
3923   interface(MEMORY_INTER) %{
3924     base($reg);
3925     index($idx);
3926     scale(0x0);
3927     disp($off);
3928   %}
3929 %}
3930 
3931 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3932 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3933 %{
3934   constraint(ALLOC_IN_RC(ptr_reg));
3935   predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3936   match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3937 
3938   op_cost(10);
3939   format %{"[$reg + $off + $idx << $scale]" %}
3940   interface(MEMORY_INTER) %{
3941     base($reg);
3942     index($idx);
3943     scale($scale);
3944     disp($off);
3945   %}
3946 %}
3947 
3948 // Indirect Narrow Oop Plus Offset Operand
3949 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3950 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3951 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3952   predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3953   constraint(ALLOC_IN_RC(ptr_reg));
3954   match(AddP (DecodeN reg) off);
3955 
3956   op_cost(10);
3957   format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3958   interface(MEMORY_INTER) %{
3959     base(0xc); // R12
3960     index($reg);
3961     scale(0x3);
3962     disp($off);
3963   %}
3964 %}
3965 
3966 // Indirect Memory Operand
3967 operand indirectNarrow(rRegN reg)
3968 %{
3969   predicate(Universe::narrow_oop_shift() == 0);
3970   constraint(ALLOC_IN_RC(ptr_reg));
3971   match(DecodeN reg);
3972 
3973   format %{ "[$reg]" %}
3974   interface(MEMORY_INTER) %{
3975     base($reg);
3976     index(0x4);
3977     scale(0x0);
3978     disp(0x0);
3979   %}
3980 %}
3981 
3982 // Indirect Memory Plus Short Offset Operand
3983 operand indOffset8Narrow(rRegN reg, immL8 off)
3984 %{
3985   predicate(Universe::narrow_oop_shift() == 0);
3986   constraint(ALLOC_IN_RC(ptr_reg));
3987   match(AddP (DecodeN reg) off);
3988 
3989   format %{ "[$reg + $off (8-bit)]" %}
3990   interface(MEMORY_INTER) %{
3991     base($reg);
3992     index(0x4);
3993     scale(0x0);
3994     disp($off);
3995   %}
3996 %}
3997 
3998 // Indirect Memory Plus Long Offset Operand
3999 operand indOffset32Narrow(rRegN reg, immL32 off)
4000 %{
4001   predicate(Universe::narrow_oop_shift() == 0);
4002   constraint(ALLOC_IN_RC(ptr_reg));
4003   match(AddP (DecodeN reg) off);
4004 
4005   format %{ "[$reg + $off (32-bit)]" %}
4006   interface(MEMORY_INTER) %{
4007     base($reg);
4008     index(0x4);
4009     scale(0x0);
4010     disp($off);
4011   %}
4012 %}
4013 
4014 // Indirect Memory Plus Index Register Plus Offset Operand
4015 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4016 %{
4017   predicate(Universe::narrow_oop_shift() == 0);
4018   constraint(ALLOC_IN_RC(ptr_reg));
4019   match(AddP (AddP (DecodeN reg) lreg) off);
4020 
4021   op_cost(10);
4022   format %{"[$reg + $off + $lreg]" %}
4023   interface(MEMORY_INTER) %{
4024     base($reg);
4025     index($lreg);
4026     scale(0x0);
4027     disp($off);
4028   %}
4029 %}
4030 
4031 // Indirect Memory Plus Index Register Plus Offset Operand
4032 operand indIndexNarrow(rRegN reg, rRegL lreg)
4033 %{
4034   predicate(Universe::narrow_oop_shift() == 0);
4035   constraint(ALLOC_IN_RC(ptr_reg));
4036   match(AddP (DecodeN reg) lreg);
4037 
4038   op_cost(10);
4039   format %{"[$reg + $lreg]" %}
4040   interface(MEMORY_INTER) %{
4041     base($reg);
4042     index($lreg);
4043     scale(0x0);
4044     disp(0x0);
4045   %}
4046 %}
4047 
4048 // Indirect Memory Times Scale Plus Index Register
4049 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4050 %{
4051   predicate(Universe::narrow_oop_shift() == 0);
4052   constraint(ALLOC_IN_RC(ptr_reg));
4053   match(AddP (DecodeN reg) (LShiftL lreg scale));
4054 
4055   op_cost(10);
4056   format %{"[$reg + $lreg << $scale]" %}
4057   interface(MEMORY_INTER) %{
4058     base($reg);
4059     index($lreg);
4060     scale($scale);
4061     disp(0x0);
4062   %}
4063 %}
4064 
4065 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4066 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4067 %{
4068   predicate(Universe::narrow_oop_shift() == 0);
4069   constraint(ALLOC_IN_RC(ptr_reg));
4070   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4071 
4072   op_cost(10);
4073   format %{"[$reg + $off + $lreg << $scale]" %}
4074   interface(MEMORY_INTER) %{
4075     base($reg);
4076     index($lreg);
4077     scale($scale);
4078     disp($off);
4079   %}
4080 %}
4081 
4082 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4083 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4084 %{
4085   constraint(ALLOC_IN_RC(ptr_reg));
4086   predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4087   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4088 
4089   op_cost(10);
4090   format %{"[$reg + $off + $idx]" %}
4091   interface(MEMORY_INTER) %{
4092     base($reg);
4093     index($idx);
4094     scale(0x0);
4095     disp($off);
4096   %}
4097 %}
4098 
4099 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4100 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4101 %{
4102   constraint(ALLOC_IN_RC(ptr_reg));
4103   predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4104   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4105 
4106   op_cost(10);
4107   format %{"[$reg + $off + $idx << $scale]" %}
4108   interface(MEMORY_INTER) %{
4109     base($reg);
4110     index($idx);
4111     scale($scale);
4112     disp($off);
4113   %}
4114 %}
4115 
4116 //----------Special Memory Operands--------------------------------------------
4117 // Stack Slot Operand - This operand is used for loading and storing temporary
4118 //                      values on the stack where a match requires a value to
4119 //                      flow through memory.
4120 operand stackSlotP(sRegP reg)
4121 %{
4122   constraint(ALLOC_IN_RC(stack_slots));
4123   // No match rule because this operand is only generated in matching
4124 
4125   format %{ "[$reg]" %}
4126   interface(MEMORY_INTER) %{
4127     base(0x4);   // RSP
4128     index(0x4);  // No Index
4129     scale(0x0);  // No Scale
4130     disp($reg);  // Stack Offset
4131   %}
4132 %}
4133 
4134 operand stackSlotI(sRegI reg)
4135 %{
4136   constraint(ALLOC_IN_RC(stack_slots));
4137   // No match rule because this operand is only generated in matching
4138 
4139   format %{ "[$reg]" %}
4140   interface(MEMORY_INTER) %{
4141     base(0x4);   // RSP
4142     index(0x4);  // No Index
4143     scale(0x0);  // No Scale
4144     disp($reg);  // Stack Offset
4145   %}
4146 %}
4147 
4148 operand stackSlotF(sRegF reg)
4149 %{
4150   constraint(ALLOC_IN_RC(stack_slots));
4151   // No match rule because this operand is only generated in matching
4152 
4153   format %{ "[$reg]" %}
4154   interface(MEMORY_INTER) %{
4155     base(0x4);   // RSP
4156     index(0x4);  // No Index
4157     scale(0x0);  // No Scale
4158     disp($reg);  // Stack Offset
4159   %}
4160 %}
4161 
4162 operand stackSlotD(sRegD reg)
4163 %{
4164   constraint(ALLOC_IN_RC(stack_slots));
4165   // No match rule because this operand is only generated in matching
4166 
4167   format %{ "[$reg]" %}
4168   interface(MEMORY_INTER) %{
4169     base(0x4);   // RSP
4170     index(0x4);  // No Index
4171     scale(0x0);  // No Scale
4172     disp($reg);  // Stack Offset
4173   %}
4174 %}
4175 operand stackSlotL(sRegL reg)
4176 %{
4177   constraint(ALLOC_IN_RC(stack_slots));
4178   // No match rule because this operand is only generated in matching
4179 
4180   format %{ "[$reg]" %}
4181   interface(MEMORY_INTER) %{
4182     base(0x4);   // RSP
4183     index(0x4);  // No Index
4184     scale(0x0);  // No Scale
4185     disp($reg);  // Stack Offset
4186   %}
4187 %}
4188 
4189 //----------Conditional Branch Operands----------------------------------------
4190 // Comparison Op  - This is the operation of the comparison, and is limited to
4191 //                  the following set of codes:
4192 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4193 //
4194 // Other attributes of the comparison, such as unsignedness, are specified
4195 // by the comparison instruction that sets a condition code flags register.
4196 // That result is represented by a flags operand whose subtype is appropriate
4197 // to the unsignedness (etc.) of the comparison.
4198 //
4199 // Later, the instruction which matches both the Comparison Op (a Bool) and
4200 // the flags (produced by the Cmp) specifies the coding of the comparison op
4201 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4202 
4203 // Comparision Code
4204 operand cmpOp()
4205 %{
4206   match(Bool);
4207 
4208   format %{ "" %}
4209   interface(COND_INTER) %{
4210     equal(0x4, "e");
4211     not_equal(0x5, "ne");
4212     less(0xC, "l");
4213     greater_equal(0xD, "ge");
4214     less_equal(0xE, "le");
4215     greater(0xF, "g");
4216     overflow(0x0, "o");
4217     no_overflow(0x1, "no");
4218   %}
4219 %}
4220 
4221 // Comparison Code, unsigned compare.  Used by FP also, with
4222 // C2 (unordered) turned into GT or LT already.  The other bits
4223 // C0 and C3 are turned into Carry & Zero flags.
4224 operand cmpOpU()
4225 %{
4226   match(Bool);
4227 
4228   format %{ "" %}
4229   interface(COND_INTER) %{
4230     equal(0x4, "e");
4231     not_equal(0x5, "ne");
4232     less(0x2, "b");
4233     greater_equal(0x3, "nb");
4234     less_equal(0x6, "be");
4235     greater(0x7, "nbe");
4236     overflow(0x0, "o");
4237     no_overflow(0x1, "no");
4238   %}
4239 %}
4240 
4241 
4242 // Floating comparisons that don't require any fixup for the unordered case
4243 operand cmpOpUCF() %{
4244   match(Bool);
4245   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4246             n->as_Bool()->_test._test == BoolTest::ge ||
4247             n->as_Bool()->_test._test == BoolTest::le ||
4248             n->as_Bool()->_test._test == BoolTest::gt);
4249   format %{ "" %}
4250   interface(COND_INTER) %{
4251     equal(0x4, "e");
4252     not_equal(0x5, "ne");
4253     less(0x2, "b");
4254     greater_equal(0x3, "nb");
4255     less_equal(0x6, "be");
4256     greater(0x7, "nbe");
4257     overflow(0x0, "o");
4258     no_overflow(0x1, "no");
4259   %}
4260 %}
4261 
4262 
4263 // Floating comparisons that can be fixed up with extra conditional jumps
4264 operand cmpOpUCF2() %{
4265   match(Bool);
4266   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4267             n->as_Bool()->_test._test == BoolTest::eq);
4268   format %{ "" %}
4269   interface(COND_INTER) %{
4270     equal(0x4, "e");
4271     not_equal(0x5, "ne");
4272     less(0x2, "b");
4273     greater_equal(0x3, "nb");
4274     less_equal(0x6, "be");
4275     greater(0x7, "nbe");
4276     overflow(0x0, "o");
4277     no_overflow(0x1, "no");
4278   %}
4279 %}
4280 
4281 // Operands for bound floating pointer register arguments
4282 operand rxmm0() %{
4283   constraint(ALLOC_IN_RC(xmm0_reg));  match(VecX);
4284   predicate((UseSSE > 0) && (UseAVX<= 2));  format%{%}  interface(REG_INTER);
4285 %}
4286 operand rxmm1() %{
4287   constraint(ALLOC_IN_RC(xmm1_reg));  match(VecX);
4288   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4289 %}
4290 operand rxmm2() %{
4291   constraint(ALLOC_IN_RC(xmm2_reg));  match(VecX);
4292   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4293 %}
4294 operand rxmm3() %{
4295   constraint(ALLOC_IN_RC(xmm3_reg));  match(VecX);
4296   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4297 %}
4298 operand rxmm4() %{
4299   constraint(ALLOC_IN_RC(xmm4_reg));  match(VecX);
4300   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4301 %}
4302 operand rxmm5() %{
4303   constraint(ALLOC_IN_RC(xmm5_reg));  match(VecX);
4304   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4305 %}
4306 operand rxmm6() %{
4307   constraint(ALLOC_IN_RC(xmm6_reg));  match(VecX);
4308   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4309 %}
4310 operand rxmm7() %{
4311   constraint(ALLOC_IN_RC(xmm7_reg));  match(VecX);
4312   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4313 %}
4314 operand rxmm8() %{
4315   constraint(ALLOC_IN_RC(xmm8_reg));  match(VecX);
4316   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4317 %}
4318 operand rxmm9() %{
4319   constraint(ALLOC_IN_RC(xmm9_reg));  match(VecX);
4320   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4321 %}
4322 operand rxmm10() %{
4323   constraint(ALLOC_IN_RC(xmm10_reg));  match(VecX);
4324   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4325 %}
4326 operand rxmm11() %{
4327   constraint(ALLOC_IN_RC(xmm11_reg));  match(VecX);
4328   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4329 %}
4330 operand rxmm12() %{
4331   constraint(ALLOC_IN_RC(xmm12_reg));  match(VecX);
4332   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4333 %}
4334 operand rxmm13() %{
4335   constraint(ALLOC_IN_RC(xmm13_reg));  match(VecX);
4336   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4337 %}
4338 operand rxmm14() %{
4339   constraint(ALLOC_IN_RC(xmm14_reg));  match(VecX);
4340   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4341 %}
4342 operand rxmm15() %{
4343   constraint(ALLOC_IN_RC(xmm15_reg));  match(VecX);
4344   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4345 %}
4346 operand rxmm16() %{
4347   constraint(ALLOC_IN_RC(xmm16_reg));  match(VecX);
4348   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4349 %}
4350 operand rxmm17() %{
4351   constraint(ALLOC_IN_RC(xmm17_reg));  match(VecX);
4352   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4353 %}
4354 operand rxmm18() %{
4355   constraint(ALLOC_IN_RC(xmm18_reg));  match(VecX);
4356   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4357 %}
4358 operand rxmm19() %{
4359   constraint(ALLOC_IN_RC(xmm19_reg));  match(VecX);
4360   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4361 %}
4362 operand rxmm20() %{
4363   constraint(ALLOC_IN_RC(xmm20_reg));  match(VecX);
4364   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4365 %}
4366 operand rxmm21() %{
4367   constraint(ALLOC_IN_RC(xmm21_reg));  match(VecX);
4368   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4369 %}
4370 operand rxmm22() %{
4371   constraint(ALLOC_IN_RC(xmm22_reg));  match(VecX);
4372   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4373 %}
4374 operand rxmm23() %{
4375   constraint(ALLOC_IN_RC(xmm23_reg));  match(VecX);
4376   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4377 %}
4378 operand rxmm24() %{
4379   constraint(ALLOC_IN_RC(xmm24_reg));  match(VecX);
4380   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4381 %}
4382 operand rxmm25() %{
4383   constraint(ALLOC_IN_RC(xmm25_reg));  match(VecX);
4384   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4385 %}
4386 operand rxmm26() %{
4387   constraint(ALLOC_IN_RC(xmm26_reg));  match(VecX);
4388   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4389 %}
4390 operand rxmm27() %{
4391   constraint(ALLOC_IN_RC(xmm27_reg));  match(VecX);
4392   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4393 %}
4394 operand rxmm28() %{
4395   constraint(ALLOC_IN_RC(xmm28_reg));  match(VecX);
4396   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4397 %}
4398 operand rxmm29() %{
4399   constraint(ALLOC_IN_RC(xmm29_reg));  match(VecX);
4400   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4401 %}
4402 operand rxmm30() %{
4403   constraint(ALLOC_IN_RC(xmm30_reg));  match(VecX);
4404   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4405 %}
4406 operand rxmm31() %{
4407   constraint(ALLOC_IN_RC(xmm31_reg));  match(VecX);
4408   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4409 %}
4410 
4411 //----------OPERAND CLASSES----------------------------------------------------
4412 // Operand Classes are groups of operands that are used as to simplify
4413 // instruction definitions by not requiring the AD writer to specify separate
4414 // instructions for every form of operand when the instruction accepts
4415 // multiple operand types with the same basic encoding and format.  The classic
4416 // case of this is memory operands.
4417 
4418 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4419                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4420                indCompressedOopOffset,
4421                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4422                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4423                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4424 
4425 //----------PIPELINE-----------------------------------------------------------
4426 // Rules which define the behavior of the target architectures pipeline.
4427 pipeline %{
4428 
4429 //----------ATTRIBUTES---------------------------------------------------------
4430 attributes %{
4431   variable_size_instructions;        // Fixed size instructions
4432   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
4433   instruction_unit_size = 1;         // An instruction is 1 bytes long
4434   instruction_fetch_unit_size = 16;  // The processor fetches one line
4435   instruction_fetch_units = 1;       // of 16 bytes
4436 
4437   // List of nop instructions
4438   nops( MachNop );
4439 %}
4440 
4441 //----------RESOURCES----------------------------------------------------------
4442 // Resources are the functional units available to the machine
4443 
4444 // Generic P2/P3 pipeline
4445 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4446 // 3 instructions decoded per cycle.
4447 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4448 // 3 ALU op, only ALU0 handles mul instructions.
4449 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4450            MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4451            BR, FPU,
4452            ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4453 
4454 //----------PIPELINE DESCRIPTION-----------------------------------------------
4455 // Pipeline Description specifies the stages in the machine's pipeline
4456 
4457 // Generic P2/P3 pipeline
4458 pipe_desc(S0, S1, S2, S3, S4, S5);
4459 
4460 //----------PIPELINE CLASSES---------------------------------------------------
4461 // Pipeline Classes describe the stages in which input and output are
4462 // referenced by the hardware pipeline.
4463 
4464 // Naming convention: ialu or fpu
4465 // Then: _reg
4466 // Then: _reg if there is a 2nd register
4467 // Then: _long if it's a pair of instructions implementing a long
4468 // Then: _fat if it requires the big decoder
4469 //   Or: _mem if it requires the big decoder and a memory unit.
4470 
4471 // Integer ALU reg operation
4472 pipe_class ialu_reg(rRegI dst)
4473 %{
4474     single_instruction;
4475     dst    : S4(write);
4476     dst    : S3(read);
4477     DECODE : S0;        // any decoder
4478     ALU    : S3;        // any alu
4479 %}
4480 
4481 // Long ALU reg operation
4482 pipe_class ialu_reg_long(rRegL dst)
4483 %{
4484     instruction_count(2);
4485     dst    : S4(write);
4486     dst    : S3(read);
4487     DECODE : S0(2);     // any 2 decoders
4488     ALU    : S3(2);     // both alus
4489 %}
4490 
4491 // Integer ALU reg operation using big decoder
4492 pipe_class ialu_reg_fat(rRegI dst)
4493 %{
4494     single_instruction;
4495     dst    : S4(write);
4496     dst    : S3(read);
4497     D0     : S0;        // big decoder only
4498     ALU    : S3;        // any alu
4499 %}
4500 
4501 // Long ALU reg operation using big decoder
4502 pipe_class ialu_reg_long_fat(rRegL dst)
4503 %{
4504     instruction_count(2);
4505     dst    : S4(write);
4506     dst    : S3(read);
4507     D0     : S0(2);     // big decoder only; twice
4508     ALU    : S3(2);     // any 2 alus
4509 %}
4510 
4511 // Integer ALU reg-reg operation
4512 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4513 %{
4514     single_instruction;
4515     dst    : S4(write);
4516     src    : S3(read);
4517     DECODE : S0;        // any decoder
4518     ALU    : S3;        // any alu
4519 %}
4520 
4521 // Long ALU reg-reg operation
4522 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4523 %{
4524     instruction_count(2);
4525     dst    : S4(write);
4526     src    : S3(read);
4527     DECODE : S0(2);     // any 2 decoders
4528     ALU    : S3(2);     // both alus
4529 %}
4530 
4531 // Integer ALU reg-reg operation
4532 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4533 %{
4534     single_instruction;
4535     dst    : S4(write);
4536     src    : S3(read);
4537     D0     : S0;        // big decoder only
4538     ALU    : S3;        // any alu
4539 %}
4540 
4541 // Long ALU reg-reg operation
4542 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4543 %{
4544     instruction_count(2);
4545     dst    : S4(write);
4546     src    : S3(read);
4547     D0     : S0(2);     // big decoder only; twice
4548     ALU    : S3(2);     // both alus
4549 %}
4550 
4551 // Integer ALU reg-mem operation
4552 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4553 %{
4554     single_instruction;
4555     dst    : S5(write);
4556     mem    : S3(read);
4557     D0     : S0;        // big decoder only
4558     ALU    : S4;        // any alu
4559     MEM    : S3;        // any mem
4560 %}
4561 
4562 // Integer mem operation (prefetch)
4563 pipe_class ialu_mem(memory mem)
4564 %{
4565     single_instruction;
4566     mem    : S3(read);
4567     D0     : S0;        // big decoder only
4568     MEM    : S3;        // any mem
4569 %}
4570 
4571 // Integer Store to Memory
4572 pipe_class ialu_mem_reg(memory mem, rRegI src)
4573 %{
4574     single_instruction;
4575     mem    : S3(read);
4576     src    : S5(read);
4577     D0     : S0;        // big decoder only
4578     ALU    : S4;        // any alu
4579     MEM    : S3;
4580 %}
4581 
4582 // // Long Store to Memory
4583 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4584 // %{
4585 //     instruction_count(2);
4586 //     mem    : S3(read);
4587 //     src    : S5(read);
4588 //     D0     : S0(2);          // big decoder only; twice
4589 //     ALU    : S4(2);     // any 2 alus
4590 //     MEM    : S3(2);  // Both mems
4591 // %}
4592 
4593 // Integer Store to Memory
4594 pipe_class ialu_mem_imm(memory mem)
4595 %{
4596     single_instruction;
4597     mem    : S3(read);
4598     D0     : S0;        // big decoder only
4599     ALU    : S4;        // any alu
4600     MEM    : S3;
4601 %}
4602 
4603 // Integer ALU0 reg-reg operation
4604 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4605 %{
4606     single_instruction;
4607     dst    : S4(write);
4608     src    : S3(read);
4609     D0     : S0;        // Big decoder only
4610     ALU0   : S3;        // only alu0
4611 %}
4612 
4613 // Integer ALU0 reg-mem operation
4614 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4615 %{
4616     single_instruction;
4617     dst    : S5(write);
4618     mem    : S3(read);
4619     D0     : S0;        // big decoder only
4620     ALU0   : S4;        // ALU0 only
4621     MEM    : S3;        // any mem
4622 %}
4623 
4624 // Integer ALU reg-reg operation
4625 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4626 %{
4627     single_instruction;
4628     cr     : S4(write);
4629     src1   : S3(read);
4630     src2   : S3(read);
4631     DECODE : S0;        // any decoder
4632     ALU    : S3;        // any alu
4633 %}
4634 
4635 // Integer ALU reg-imm operation
4636 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4637 %{
4638     single_instruction;
4639     cr     : S4(write);
4640     src1   : S3(read);
4641     DECODE : S0;        // any decoder
4642     ALU    : S3;        // any alu
4643 %}
4644 
4645 // Integer ALU reg-mem operation
4646 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4647 %{
4648     single_instruction;
4649     cr     : S4(write);
4650     src1   : S3(read);
4651     src2   : S3(read);
4652     D0     : S0;        // big decoder only
4653     ALU    : S4;        // any alu
4654     MEM    : S3;
4655 %}
4656 
4657 // Conditional move reg-reg
4658 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4659 %{
4660     instruction_count(4);
4661     y      : S4(read);
4662     q      : S3(read);
4663     p      : S3(read);
4664     DECODE : S0(4);     // any decoder
4665 %}
4666 
4667 // Conditional move reg-reg
4668 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4669 %{
4670     single_instruction;
4671     dst    : S4(write);
4672     src    : S3(read);
4673     cr     : S3(read);
4674     DECODE : S0;        // any decoder
4675 %}
4676 
4677 // Conditional move reg-mem
4678 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4679 %{
4680     single_instruction;
4681     dst    : S4(write);
4682     src    : S3(read);
4683     cr     : S3(read);
4684     DECODE : S0;        // any decoder
4685     MEM    : S3;
4686 %}
4687 
4688 // Conditional move reg-reg long
4689 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4690 %{
4691     single_instruction;
4692     dst    : S4(write);
4693     src    : S3(read);
4694     cr     : S3(read);
4695     DECODE : S0(2);     // any 2 decoders
4696 %}
4697 
4698 // XXX
4699 // // Conditional move double reg-reg
4700 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4701 // %{
4702 //     single_instruction;
4703 //     dst    : S4(write);
4704 //     src    : S3(read);
4705 //     cr     : S3(read);
4706 //     DECODE : S0;     // any decoder
4707 // %}
4708 
4709 // Float reg-reg operation
4710 pipe_class fpu_reg(regD dst)
4711 %{
4712     instruction_count(2);
4713     dst    : S3(read);
4714     DECODE : S0(2);     // any 2 decoders
4715     FPU    : S3;
4716 %}
4717 
4718 // Float reg-reg operation
4719 pipe_class fpu_reg_reg(regD dst, regD src)
4720 %{
4721     instruction_count(2);
4722     dst    : S4(write);
4723     src    : S3(read);
4724     DECODE : S0(2);     // any 2 decoders
4725     FPU    : S3;
4726 %}
4727 
4728 // Float reg-reg operation
4729 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4730 %{
4731     instruction_count(3);
4732     dst    : S4(write);
4733     src1   : S3(read);
4734     src2   : S3(read);
4735     DECODE : S0(3);     // any 3 decoders
4736     FPU    : S3(2);
4737 %}
4738 
4739 // Float reg-reg operation
4740 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4741 %{
4742     instruction_count(4);
4743     dst    : S4(write);
4744     src1   : S3(read);
4745     src2   : S3(read);
4746     src3   : S3(read);
4747     DECODE : S0(4);     // any 3 decoders
4748     FPU    : S3(2);
4749 %}
4750 
4751 // Float reg-reg operation
4752 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4753 %{
4754     instruction_count(4);
4755     dst    : S4(write);
4756     src1   : S3(read);
4757     src2   : S3(read);
4758     src3   : S3(read);
4759     DECODE : S1(3);     // any 3 decoders
4760     D0     : S0;        // Big decoder only
4761     FPU    : S3(2);
4762     MEM    : S3;
4763 %}
4764 
4765 // Float reg-mem operation
4766 pipe_class fpu_reg_mem(regD dst, memory mem)
4767 %{
4768     instruction_count(2);
4769     dst    : S5(write);
4770     mem    : S3(read);
4771     D0     : S0;        // big decoder only
4772     DECODE : S1;        // any decoder for FPU POP
4773     FPU    : S4;
4774     MEM    : S3;        // any mem
4775 %}
4776 
4777 // Float reg-mem operation
4778 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4779 %{
4780     instruction_count(3);
4781     dst    : S5(write);
4782     src1   : S3(read);
4783     mem    : S3(read);
4784     D0     : S0;        // big decoder only
4785     DECODE : S1(2);     // any decoder for FPU POP
4786     FPU    : S4;
4787     MEM    : S3;        // any mem
4788 %}
4789 
4790 // Float mem-reg operation
4791 pipe_class fpu_mem_reg(memory mem, regD src)
4792 %{
4793     instruction_count(2);
4794     src    : S5(read);
4795     mem    : S3(read);
4796     DECODE : S0;        // any decoder for FPU PUSH
4797     D0     : S1;        // big decoder only
4798     FPU    : S4;
4799     MEM    : S3;        // any mem
4800 %}
4801 
4802 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4803 %{
4804     instruction_count(3);
4805     src1   : S3(read);
4806     src2   : S3(read);
4807     mem    : S3(read);
4808     DECODE : S0(2);     // any decoder for FPU PUSH
4809     D0     : S1;        // big decoder only
4810     FPU    : S4;
4811     MEM    : S3;        // any mem
4812 %}
4813 
4814 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4815 %{
4816     instruction_count(3);
4817     src1   : S3(read);
4818     src2   : S3(read);
4819     mem    : S4(read);
4820     DECODE : S0;        // any decoder for FPU PUSH
4821     D0     : S0(2);     // big decoder only
4822     FPU    : S4;
4823     MEM    : S3(2);     // any mem
4824 %}
4825 
4826 pipe_class fpu_mem_mem(memory dst, memory src1)
4827 %{
4828     instruction_count(2);
4829     src1   : S3(read);
4830     dst    : S4(read);
4831     D0     : S0(2);     // big decoder only
4832     MEM    : S3(2);     // any mem
4833 %}
4834 
4835 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4836 %{
4837     instruction_count(3);
4838     src1   : S3(read);
4839     src2   : S3(read);
4840     dst    : S4(read);
4841     D0     : S0(3);     // big decoder only
4842     FPU    : S4;
4843     MEM    : S3(3);     // any mem
4844 %}
4845 
4846 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4847 %{
4848     instruction_count(3);
4849     src1   : S4(read);
4850     mem    : S4(read);
4851     DECODE : S0;        // any decoder for FPU PUSH
4852     D0     : S0(2);     // big decoder only
4853     FPU    : S4;
4854     MEM    : S3(2);     // any mem
4855 %}
4856 
4857 // Float load constant
4858 pipe_class fpu_reg_con(regD dst)
4859 %{
4860     instruction_count(2);
4861     dst    : S5(write);
4862     D0     : S0;        // big decoder only for the load
4863     DECODE : S1;        // any decoder for FPU POP
4864     FPU    : S4;
4865     MEM    : S3;        // any mem
4866 %}
4867 
4868 // Float load constant
4869 pipe_class fpu_reg_reg_con(regD dst, regD src)
4870 %{
4871     instruction_count(3);
4872     dst    : S5(write);
4873     src    : S3(read);
4874     D0     : S0;        // big decoder only for the load
4875     DECODE : S1(2);     // any decoder for FPU POP
4876     FPU    : S4;
4877     MEM    : S3;        // any mem
4878 %}
4879 
4880 // UnConditional branch
4881 pipe_class pipe_jmp(label labl)
4882 %{
4883     single_instruction;
4884     BR   : S3;
4885 %}
4886 
4887 // Conditional branch
4888 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4889 %{
4890     single_instruction;
4891     cr    : S1(read);
4892     BR    : S3;
4893 %}
4894 
4895 // Allocation idiom
4896 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4897 %{
4898     instruction_count(1); force_serialization;
4899     fixed_latency(6);
4900     heap_ptr : S3(read);
4901     DECODE   : S0(3);
4902     D0       : S2;
4903     MEM      : S3;
4904     ALU      : S3(2);
4905     dst      : S5(write);
4906     BR       : S5;
4907 %}
4908 
4909 // Generic big/slow expanded idiom
4910 pipe_class pipe_slow()
4911 %{
4912     instruction_count(10); multiple_bundles; force_serialization;
4913     fixed_latency(100);
4914     D0  : S0(2);
4915     MEM : S3(2);
4916 %}
4917 
4918 // The real do-nothing guy
4919 pipe_class empty()
4920 %{
4921     instruction_count(0);
4922 %}
4923 
4924 // Define the class for the Nop node
4925 define
4926 %{
4927    MachNop = empty;
4928 %}
4929 
4930 %}
4931 
4932 //----------INSTRUCTIONS-------------------------------------------------------
4933 //
4934 // match      -- States which machine-independent subtree may be replaced
4935 //               by this instruction.
4936 // ins_cost   -- The estimated cost of this instruction is used by instruction
4937 //               selection to identify a minimum cost tree of machine
4938 //               instructions that matches a tree of machine-independent
4939 //               instructions.
4940 // format     -- A string providing the disassembly for this instruction.
4941 //               The value of an instruction's operand may be inserted
4942 //               by referring to it with a '$' prefix.
4943 // opcode     -- Three instruction opcodes may be provided.  These are referred
4944 //               to within an encode class as $primary, $secondary, and $tertiary
4945 //               rrspectively.  The primary opcode is commonly used to
4946 //               indicate the type of machine instruction, while secondary
4947 //               and tertiary are often used for prefix options or addressing
4948 //               modes.
4949 // ins_encode -- A list of encode classes with parameters. The encode class
4950 //               name must have been defined in an 'enc_class' specification
4951 //               in the encode section of the architecture description.
4952 
4953 
4954 //----------Load/Store/Move Instructions---------------------------------------
4955 //----------Load Instructions--------------------------------------------------
4956 
4957 // Load Byte (8 bit signed)
4958 instruct loadB(rRegI dst, memory mem)
4959 %{
4960   match(Set dst (LoadB mem));
4961 
4962   ins_cost(125);
4963   format %{ "movsbl  $dst, $mem\t# byte" %}
4964 
4965   ins_encode %{
4966     __ movsbl($dst$$Register, $mem$$Address);
4967   %}
4968 
4969   ins_pipe(ialu_reg_mem);
4970 %}
4971 
4972 // Load Byte (8 bit signed) into Long Register
4973 instruct loadB2L(rRegL dst, memory mem)
4974 %{
4975   match(Set dst (ConvI2L (LoadB mem)));
4976 
4977   ins_cost(125);
4978   format %{ "movsbq  $dst, $mem\t# byte -> long" %}
4979 
4980   ins_encode %{
4981     __ movsbq($dst$$Register, $mem$$Address);
4982   %}
4983 
4984   ins_pipe(ialu_reg_mem);
4985 %}
4986 
4987 // Load Unsigned Byte (8 bit UNsigned)
4988 instruct loadUB(rRegI dst, memory mem)
4989 %{
4990   match(Set dst (LoadUB mem));
4991 
4992   ins_cost(125);
4993   format %{ "movzbl  $dst, $mem\t# ubyte" %}
4994 
4995   ins_encode %{
4996     __ movzbl($dst$$Register, $mem$$Address);
4997   %}
4998 
4999   ins_pipe(ialu_reg_mem);
5000 %}
5001 
5002 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5003 instruct loadUB2L(rRegL dst, memory mem)
5004 %{
5005   match(Set dst (ConvI2L (LoadUB mem)));
5006 
5007   ins_cost(125);
5008   format %{ "movzbq  $dst, $mem\t# ubyte -> long" %}
5009 
5010   ins_encode %{
5011     __ movzbq($dst$$Register, $mem$$Address);
5012   %}
5013 
5014   ins_pipe(ialu_reg_mem);
5015 %}
5016 
5017 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5018 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5019   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5020   effect(KILL cr);
5021 
5022   format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5023             "andl    $dst, right_n_bits($mask, 8)" %}
5024   ins_encode %{
5025     Register Rdst = $dst$$Register;
5026     __ movzbq(Rdst, $mem$$Address);
5027     __ andl(Rdst, $mask$$constant & right_n_bits(8));
5028   %}
5029   ins_pipe(ialu_reg_mem);
5030 %}
5031 
5032 // Load Short (16 bit signed)
5033 instruct loadS(rRegI dst, memory mem)
5034 %{
5035   match(Set dst (LoadS mem));
5036 
5037   ins_cost(125);
5038   format %{ "movswl $dst, $mem\t# short" %}
5039 
5040   ins_encode %{
5041     __ movswl($dst$$Register, $mem$$Address);
5042   %}
5043 
5044   ins_pipe(ialu_reg_mem);
5045 %}
5046 
5047 // Load Short (16 bit signed) to Byte (8 bit signed)
5048 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5049   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5050 
5051   ins_cost(125);
5052   format %{ "movsbl $dst, $mem\t# short -> byte" %}
5053   ins_encode %{
5054     __ movsbl($dst$$Register, $mem$$Address);
5055   %}
5056   ins_pipe(ialu_reg_mem);
5057 %}
5058 
5059 // Load Short (16 bit signed) into Long Register
5060 instruct loadS2L(rRegL dst, memory mem)
5061 %{
5062   match(Set dst (ConvI2L (LoadS mem)));
5063 
5064   ins_cost(125);
5065   format %{ "movswq $dst, $mem\t# short -> long" %}
5066 
5067   ins_encode %{
5068     __ movswq($dst$$Register, $mem$$Address);
5069   %}
5070 
5071   ins_pipe(ialu_reg_mem);
5072 %}
5073 
5074 // Load Unsigned Short/Char (16 bit UNsigned)
5075 instruct loadUS(rRegI dst, memory mem)
5076 %{
5077   match(Set dst (LoadUS mem));
5078 
5079   ins_cost(125);
5080   format %{ "movzwl  $dst, $mem\t# ushort/char" %}
5081 
5082   ins_encode %{
5083     __ movzwl($dst$$Register, $mem$$Address);
5084   %}
5085 
5086   ins_pipe(ialu_reg_mem);
5087 %}
5088 
5089 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5090 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5091   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5092 
5093   ins_cost(125);
5094   format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5095   ins_encode %{
5096     __ movsbl($dst$$Register, $mem$$Address);
5097   %}
5098   ins_pipe(ialu_reg_mem);
5099 %}
5100 
5101 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5102 instruct loadUS2L(rRegL dst, memory mem)
5103 %{
5104   match(Set dst (ConvI2L (LoadUS mem)));
5105 
5106   ins_cost(125);
5107   format %{ "movzwq  $dst, $mem\t# ushort/char -> long" %}
5108 
5109   ins_encode %{
5110     __ movzwq($dst$$Register, $mem$$Address);
5111   %}
5112 
5113   ins_pipe(ialu_reg_mem);
5114 %}
5115 
5116 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5117 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5118   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5119 
5120   format %{ "movzbq  $dst, $mem\t# ushort/char & 0xFF -> long" %}
5121   ins_encode %{
5122     __ movzbq($dst$$Register, $mem$$Address);
5123   %}
5124   ins_pipe(ialu_reg_mem);
5125 %}
5126 
5127 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5128 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5129   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5130   effect(KILL cr);
5131 
5132   format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5133             "andl    $dst, right_n_bits($mask, 16)" %}
5134   ins_encode %{
5135     Register Rdst = $dst$$Register;
5136     __ movzwq(Rdst, $mem$$Address);
5137     __ andl(Rdst, $mask$$constant & right_n_bits(16));
5138   %}
5139   ins_pipe(ialu_reg_mem);
5140 %}
5141 
5142 // Load Integer
5143 instruct loadI(rRegI dst, memory mem)
5144 %{
5145   match(Set dst (LoadI mem));
5146 
5147   ins_cost(125);
5148   format %{ "movl    $dst, $mem\t# int" %}
5149 
5150   ins_encode %{
5151     __ movl($dst$$Register, $mem$$Address);
5152   %}
5153 
5154   ins_pipe(ialu_reg_mem);
5155 %}
5156 
5157 // Load Integer (32 bit signed) to Byte (8 bit signed)
5158 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5159   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5160 
5161   ins_cost(125);
5162   format %{ "movsbl  $dst, $mem\t# int -> byte" %}
5163   ins_encode %{
5164     __ movsbl($dst$$Register, $mem$$Address);
5165   %}
5166   ins_pipe(ialu_reg_mem);
5167 %}
5168 
5169 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5170 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5171   match(Set dst (AndI (LoadI mem) mask));
5172 
5173   ins_cost(125);
5174   format %{ "movzbl  $dst, $mem\t# int -> ubyte" %}
5175   ins_encode %{
5176     __ movzbl($dst$$Register, $mem$$Address);
5177   %}
5178   ins_pipe(ialu_reg_mem);
5179 %}
5180 
5181 // Load Integer (32 bit signed) to Short (16 bit signed)
5182 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5183   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5184 
5185   ins_cost(125);
5186   format %{ "movswl  $dst, $mem\t# int -> short" %}
5187   ins_encode %{
5188     __ movswl($dst$$Register, $mem$$Address);
5189   %}
5190   ins_pipe(ialu_reg_mem);
5191 %}
5192 
5193 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5194 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5195   match(Set dst (AndI (LoadI mem) mask));
5196 
5197   ins_cost(125);
5198   format %{ "movzwl  $dst, $mem\t# int -> ushort/char" %}
5199   ins_encode %{
5200     __ movzwl($dst$$Register, $mem$$Address);
5201   %}
5202   ins_pipe(ialu_reg_mem);
5203 %}
5204 
5205 // Load Integer into Long Register
5206 instruct loadI2L(rRegL dst, memory mem)
5207 %{
5208   match(Set dst (ConvI2L (LoadI mem)));
5209 
5210   ins_cost(125);
5211   format %{ "movslq  $dst, $mem\t# int -> long" %}
5212 
5213   ins_encode %{
5214     __ movslq($dst$$Register, $mem$$Address);
5215   %}
5216 
5217   ins_pipe(ialu_reg_mem);
5218 %}
5219 
5220 // Load Integer with mask 0xFF into Long Register
5221 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5222   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5223 
5224   format %{ "movzbq  $dst, $mem\t# int & 0xFF -> long" %}
5225   ins_encode %{
5226     __ movzbq($dst$$Register, $mem$$Address);
5227   %}
5228   ins_pipe(ialu_reg_mem);
5229 %}
5230 
5231 // Load Integer with mask 0xFFFF into Long Register
5232 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5233   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5234 
5235   format %{ "movzwq  $dst, $mem\t# int & 0xFFFF -> long" %}
5236   ins_encode %{
5237     __ movzwq($dst$$Register, $mem$$Address);
5238   %}
5239   ins_pipe(ialu_reg_mem);
5240 %}
5241 
5242 // Load Integer with a 31-bit mask into Long Register
5243 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5244   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5245   effect(KILL cr);
5246 
5247   format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
5248             "andl    $dst, $mask" %}
5249   ins_encode %{
5250     Register Rdst = $dst$$Register;
5251     __ movl(Rdst, $mem$$Address);
5252     __ andl(Rdst, $mask$$constant);
5253   %}
5254   ins_pipe(ialu_reg_mem);
5255 %}
5256 
5257 // Load Unsigned Integer into Long Register
5258 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5259 %{
5260   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5261 
5262   ins_cost(125);
5263   format %{ "movl    $dst, $mem\t# uint -> long" %}
5264 
5265   ins_encode %{
5266     __ movl($dst$$Register, $mem$$Address);
5267   %}
5268 
5269   ins_pipe(ialu_reg_mem);
5270 %}
5271 
5272 // Load Long
5273 instruct loadL(rRegL dst, memory mem)
5274 %{
5275   match(Set dst (LoadL mem));
5276 
5277   ins_cost(125);
5278   format %{ "movq    $dst, $mem\t# long" %}
5279 
5280   ins_encode %{
5281     __ movq($dst$$Register, $mem$$Address);
5282   %}
5283 
5284   ins_pipe(ialu_reg_mem); // XXX
5285 %}
5286 
5287 // Load Range
5288 instruct loadRange(rRegI dst, memory mem)
5289 %{
5290   match(Set dst (LoadRange mem));
5291 
5292   ins_cost(125); // XXX
5293   format %{ "movl    $dst, $mem\t# range" %}
5294   opcode(0x8B);
5295   ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5296   ins_pipe(ialu_reg_mem);
5297 %}
5298 
5299 // Load Pointer
5300 instruct loadP(rRegP dst, memory mem)
5301 %{
5302   match(Set dst (LoadP mem));
5303 
5304   ins_cost(125); // XXX
5305   format %{ "movq    $dst, $mem\t# ptr" %}
5306   opcode(0x8B);
5307   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5308   ins_pipe(ialu_reg_mem); // XXX
5309 %}
5310 
5311 // Load Compressed Pointer
5312 instruct loadN(rRegN dst, memory mem)
5313 %{
5314    match(Set dst (LoadN mem));
5315 
5316    ins_cost(125); // XXX
5317    format %{ "movl    $dst, $mem\t# compressed ptr" %}
5318    ins_encode %{
5319      __ movl($dst$$Register, $mem$$Address);
5320    %}
5321    ins_pipe(ialu_reg_mem); // XXX
5322 %}
5323 
5324 
5325 // Load Klass Pointer
5326 instruct loadKlass(rRegP dst, memory mem)
5327 %{
5328   match(Set dst (LoadKlass mem));
5329 
5330   ins_cost(125); // XXX
5331   format %{ "movq    $dst, $mem\t# class" %}
5332   opcode(0x8B);
5333   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5334   ins_pipe(ialu_reg_mem); // XXX
5335 %}
5336 
5337 // Load narrow Klass Pointer
5338 instruct loadNKlass(rRegN dst, memory mem)
5339 %{
5340   match(Set dst (LoadNKlass mem));
5341 
5342   ins_cost(125); // XXX
5343   format %{ "movl    $dst, $mem\t# compressed klass ptr" %}
5344   ins_encode %{
5345     __ movl($dst$$Register, $mem$$Address);
5346   %}
5347   ins_pipe(ialu_reg_mem); // XXX
5348 %}
5349 
5350 // Load Float
5351 instruct loadF(regF dst, memory mem)
5352 %{
5353   match(Set dst (LoadF mem));
5354 
5355   ins_cost(145); // XXX
5356   format %{ "movss   $dst, $mem\t# float" %}
5357   ins_encode %{
5358     __ movflt($dst$$XMMRegister, $mem$$Address);
5359   %}
5360   ins_pipe(pipe_slow); // XXX
5361 %}
5362 
5363 // Load Float
5364 instruct MoveF2VL(vlRegF dst, regF src) %{
5365   match(Set dst src);
5366   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5367   ins_encode %{
5368     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5369   %}
5370   ins_pipe( fpu_reg_reg );
5371 %}
5372 
5373 // Load Float
5374 instruct MoveVL2F(regF dst, vlRegF src) %{
5375   match(Set dst src);
5376   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5377   ins_encode %{
5378     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5379   %}
5380   ins_pipe( fpu_reg_reg );
5381 %}
5382 
5383 // Load Double
5384 instruct loadD_partial(regD dst, memory mem)
5385 %{
5386   predicate(!UseXmmLoadAndClearUpper);
5387   match(Set dst (LoadD mem));
5388 
5389   ins_cost(145); // XXX
5390   format %{ "movlpd  $dst, $mem\t# double" %}
5391   ins_encode %{
5392     __ movdbl($dst$$XMMRegister, $mem$$Address);
5393   %}
5394   ins_pipe(pipe_slow); // XXX
5395 %}
5396 
5397 instruct loadD(regD dst, memory mem)
5398 %{
5399   predicate(UseXmmLoadAndClearUpper);
5400   match(Set dst (LoadD mem));
5401 
5402   ins_cost(145); // XXX
5403   format %{ "movsd   $dst, $mem\t# double" %}
5404   ins_encode %{
5405     __ movdbl($dst$$XMMRegister, $mem$$Address);
5406   %}
5407   ins_pipe(pipe_slow); // XXX
5408 %}
5409 
5410 // Load Double
5411 instruct MoveD2VL(vlRegD dst, regD src) %{
5412   match(Set dst src);
5413   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5414   ins_encode %{
5415     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5416   %}
5417   ins_pipe( fpu_reg_reg );
5418 %}
5419 
5420 // Load Double
5421 instruct MoveVL2D(regD dst, vlRegD src) %{
5422   match(Set dst src);
5423   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5424   ins_encode %{
5425     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5426   %}
5427   ins_pipe( fpu_reg_reg );
5428 %}
5429 
5430 // Load Effective Address
5431 instruct leaP8(rRegP dst, indOffset8 mem)
5432 %{
5433   match(Set dst mem);
5434 
5435   ins_cost(110); // XXX
5436   format %{ "leaq    $dst, $mem\t# ptr 8" %}
5437   opcode(0x8D);
5438   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5439   ins_pipe(ialu_reg_reg_fat);
5440 %}
5441 
5442 instruct leaP32(rRegP dst, indOffset32 mem)
5443 %{
5444   match(Set dst mem);
5445 
5446   ins_cost(110);
5447   format %{ "leaq    $dst, $mem\t# ptr 32" %}
5448   opcode(0x8D);
5449   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5450   ins_pipe(ialu_reg_reg_fat);
5451 %}
5452 
5453 // instruct leaPIdx(rRegP dst, indIndex mem)
5454 // %{
5455 //   match(Set dst mem);
5456 
5457 //   ins_cost(110);
5458 //   format %{ "leaq    $dst, $mem\t# ptr idx" %}
5459 //   opcode(0x8D);
5460 //   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5461 //   ins_pipe(ialu_reg_reg_fat);
5462 // %}
5463 
5464 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5465 %{
5466   match(Set dst mem);
5467 
5468   ins_cost(110);
5469   format %{ "leaq    $dst, $mem\t# ptr idxoff" %}
5470   opcode(0x8D);
5471   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5472   ins_pipe(ialu_reg_reg_fat);
5473 %}
5474 
5475 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5476 %{
5477   match(Set dst mem);
5478 
5479   ins_cost(110);
5480   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
5481   opcode(0x8D);
5482   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5483   ins_pipe(ialu_reg_reg_fat);
5484 %}
5485 
5486 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5487 %{
5488   match(Set dst mem);
5489 
5490   ins_cost(110);
5491   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
5492   opcode(0x8D);
5493   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5494   ins_pipe(ialu_reg_reg_fat);
5495 %}
5496 
5497 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5498 %{
5499   match(Set dst mem);
5500 
5501   ins_cost(110);
5502   format %{ "leaq    $dst, $mem\t# ptr idxscaleoff" %}
5503   opcode(0x8D);
5504   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5505   ins_pipe(ialu_reg_reg_fat);
5506 %}
5507 
5508 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5509 %{
5510   match(Set dst mem);
5511 
5512   ins_cost(110);
5513   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
5514   opcode(0x8D);
5515   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5516   ins_pipe(ialu_reg_reg_fat);
5517 %}
5518 
5519 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5520 %{
5521   match(Set dst mem);
5522 
5523   ins_cost(110);
5524   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoff" %}
5525   opcode(0x8D);
5526   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5527   ins_pipe(ialu_reg_reg_fat);
5528 %}
5529 
5530 // Load Effective Address which uses Narrow (32-bits) oop
5531 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5532 %{
5533   predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5534   match(Set dst mem);
5535 
5536   ins_cost(110);
5537   format %{ "leaq    $dst, $mem\t# ptr compressedoopoff32" %}
5538   opcode(0x8D);
5539   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5540   ins_pipe(ialu_reg_reg_fat);
5541 %}
5542 
5543 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5544 %{
5545   predicate(Universe::narrow_oop_shift() == 0);
5546   match(Set dst mem);
5547 
5548   ins_cost(110); // XXX
5549   format %{ "leaq    $dst, $mem\t# ptr off8narrow" %}
5550   opcode(0x8D);
5551   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5552   ins_pipe(ialu_reg_reg_fat);
5553 %}
5554 
5555 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5556 %{
5557   predicate(Universe::narrow_oop_shift() == 0);
5558   match(Set dst mem);
5559 
5560   ins_cost(110);
5561   format %{ "leaq    $dst, $mem\t# ptr off32narrow" %}
5562   opcode(0x8D);
5563   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5564   ins_pipe(ialu_reg_reg_fat);
5565 %}
5566 
5567 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5568 %{
5569   predicate(Universe::narrow_oop_shift() == 0);
5570   match(Set dst mem);
5571 
5572   ins_cost(110);
5573   format %{ "leaq    $dst, $mem\t# ptr idxoffnarrow" %}
5574   opcode(0x8D);
5575   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5576   ins_pipe(ialu_reg_reg_fat);
5577 %}
5578 
5579 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5580 %{
5581   predicate(Universe::narrow_oop_shift() == 0);
5582   match(Set dst mem);
5583 
5584   ins_cost(110);
5585   format %{ "leaq    $dst, $mem\t# ptr idxscalenarrow" %}
5586   opcode(0x8D);
5587   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5588   ins_pipe(ialu_reg_reg_fat);
5589 %}
5590 
5591 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5592 %{
5593   predicate(Universe::narrow_oop_shift() == 0);
5594   match(Set dst mem);
5595 
5596   ins_cost(110);
5597   format %{ "leaq    $dst, $mem\t# ptr idxscaleoffnarrow" %}
5598   opcode(0x8D);
5599   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5600   ins_pipe(ialu_reg_reg_fat);
5601 %}
5602 
5603 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5604 %{
5605   predicate(Universe::narrow_oop_shift() == 0);
5606   match(Set dst mem);
5607 
5608   ins_cost(110);
5609   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
5610   opcode(0x8D);
5611   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5612   ins_pipe(ialu_reg_reg_fat);
5613 %}
5614 
5615 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5616 %{
5617   predicate(Universe::narrow_oop_shift() == 0);
5618   match(Set dst mem);
5619 
5620   ins_cost(110);
5621   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5622   opcode(0x8D);
5623   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5624   ins_pipe(ialu_reg_reg_fat);
5625 %}
5626 
5627 instruct loadConI(rRegI dst, immI src)
5628 %{
5629   match(Set dst src);
5630 
5631   format %{ "movl    $dst, $src\t# int" %}
5632   ins_encode(load_immI(dst, src));
5633   ins_pipe(ialu_reg_fat); // XXX
5634 %}
5635 
5636 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5637 %{
5638   match(Set dst src);
5639   effect(KILL cr);
5640 
5641   ins_cost(50);
5642   format %{ "xorl    $dst, $dst\t# int" %}
5643   opcode(0x33); /* + rd */
5644   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5645   ins_pipe(ialu_reg);
5646 %}
5647 
5648 instruct loadConL(rRegL dst, immL src)
5649 %{
5650   match(Set dst src);
5651 
5652   ins_cost(150);
5653   format %{ "movq    $dst, $src\t# long" %}
5654   ins_encode(load_immL(dst, src));
5655   ins_pipe(ialu_reg);
5656 %}
5657 
5658 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5659 %{
5660   match(Set dst src);
5661   effect(KILL cr);
5662 
5663   ins_cost(50);
5664   format %{ "xorl    $dst, $dst\t# long" %}
5665   opcode(0x33); /* + rd */
5666   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5667   ins_pipe(ialu_reg); // XXX
5668 %}
5669 
5670 instruct loadConUL32(rRegL dst, immUL32 src)
5671 %{
5672   match(Set dst src);
5673 
5674   ins_cost(60);
5675   format %{ "movl    $dst, $src\t# long (unsigned 32-bit)" %}
5676   ins_encode(load_immUL32(dst, src));
5677   ins_pipe(ialu_reg);
5678 %}
5679 
5680 instruct loadConL32(rRegL dst, immL32 src)
5681 %{
5682   match(Set dst src);
5683 
5684   ins_cost(70);
5685   format %{ "movq    $dst, $src\t# long (32-bit)" %}
5686   ins_encode(load_immL32(dst, src));
5687   ins_pipe(ialu_reg);
5688 %}
5689 
5690 instruct loadConP(rRegP dst, immP con) %{
5691   match(Set dst con);
5692 
5693   format %{ "movq    $dst, $con\t# ptr" %}
5694   ins_encode(load_immP(dst, con));
5695   ins_pipe(ialu_reg_fat); // XXX
5696 %}
5697 
5698 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5699 %{
5700   match(Set dst src);
5701   effect(KILL cr);
5702 
5703   ins_cost(50);
5704   format %{ "xorl    $dst, $dst\t# ptr" %}
5705   opcode(0x33); /* + rd */
5706   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5707   ins_pipe(ialu_reg);
5708 %}
5709 
5710 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5711 %{
5712   match(Set dst src);
5713   effect(KILL cr);
5714 
5715   ins_cost(60);
5716   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
5717   ins_encode(load_immP31(dst, src));
5718   ins_pipe(ialu_reg);
5719 %}
5720 
5721 instruct loadConF(regF dst, immF con) %{
5722   match(Set dst con);
5723   ins_cost(125);
5724   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5725   ins_encode %{
5726     __ movflt($dst$$XMMRegister, $constantaddress($con));
5727   %}
5728   ins_pipe(pipe_slow);
5729 %}
5730 
5731 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5732   match(Set dst src);
5733   effect(KILL cr);
5734   format %{ "xorq    $dst, $src\t# compressed NULL ptr" %}
5735   ins_encode %{
5736     __ xorq($dst$$Register, $dst$$Register);
5737   %}
5738   ins_pipe(ialu_reg);
5739 %}
5740 
5741 instruct loadConN(rRegN dst, immN src) %{
5742   match(Set dst src);
5743 
5744   ins_cost(125);
5745   format %{ "movl    $dst, $src\t# compressed ptr" %}
5746   ins_encode %{
5747     address con = (address)$src$$constant;
5748     if (con == NULL) {
5749       ShouldNotReachHere();
5750     } else {
5751       __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5752     }
5753   %}
5754   ins_pipe(ialu_reg_fat); // XXX
5755 %}
5756 
5757 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5758   match(Set dst src);
5759 
5760   ins_cost(125);
5761   format %{ "movl    $dst, $src\t# compressed klass ptr" %}
5762   ins_encode %{
5763     address con = (address)$src$$constant;
5764     if (con == NULL) {
5765       ShouldNotReachHere();
5766     } else {
5767       __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5768     }
5769   %}
5770   ins_pipe(ialu_reg_fat); // XXX
5771 %}
5772 
5773 instruct loadConF0(regF dst, immF0 src)
5774 %{
5775   match(Set dst src);
5776   ins_cost(100);
5777 
5778   format %{ "xorps   $dst, $dst\t# float 0.0" %}
5779   ins_encode %{
5780     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5781   %}
5782   ins_pipe(pipe_slow);
5783 %}
5784 
5785 // Use the same format since predicate() can not be used here.
5786 instruct loadConD(regD dst, immD con) %{
5787   match(Set dst con);
5788   ins_cost(125);
5789   format %{ "movsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5790   ins_encode %{
5791     __ movdbl($dst$$XMMRegister, $constantaddress($con));
5792   %}
5793   ins_pipe(pipe_slow);
5794 %}
5795 
5796 instruct loadConD0(regD dst, immD0 src)
5797 %{
5798   match(Set dst src);
5799   ins_cost(100);
5800 
5801   format %{ "xorpd   $dst, $dst\t# double 0.0" %}
5802   ins_encode %{
5803     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5804   %}
5805   ins_pipe(pipe_slow);
5806 %}
5807 
5808 instruct loadSSI(rRegI dst, stackSlotI src)
5809 %{
5810   match(Set dst src);
5811 
5812   ins_cost(125);
5813   format %{ "movl    $dst, $src\t# int stk" %}
5814   opcode(0x8B);
5815   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5816   ins_pipe(ialu_reg_mem);
5817 %}
5818 
5819 instruct loadSSL(rRegL dst, stackSlotL src)
5820 %{
5821   match(Set dst src);
5822 
5823   ins_cost(125);
5824   format %{ "movq    $dst, $src\t# long stk" %}
5825   opcode(0x8B);
5826   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5827   ins_pipe(ialu_reg_mem);
5828 %}
5829 
5830 instruct loadSSP(rRegP dst, stackSlotP src)
5831 %{
5832   match(Set dst src);
5833 
5834   ins_cost(125);
5835   format %{ "movq    $dst, $src\t# ptr stk" %}
5836   opcode(0x8B);
5837   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5838   ins_pipe(ialu_reg_mem);
5839 %}
5840 
5841 instruct loadSSF(regF dst, stackSlotF src)
5842 %{
5843   match(Set dst src);
5844 
5845   ins_cost(125);
5846   format %{ "movss   $dst, $src\t# float stk" %}
5847   ins_encode %{
5848     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5849   %}
5850   ins_pipe(pipe_slow); // XXX
5851 %}
5852 
5853 // Use the same format since predicate() can not be used here.
5854 instruct loadSSD(regD dst, stackSlotD src)
5855 %{
5856   match(Set dst src);
5857 
5858   ins_cost(125);
5859   format %{ "movsd   $dst, $src\t# double stk" %}
5860   ins_encode  %{
5861     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5862   %}
5863   ins_pipe(pipe_slow); // XXX
5864 %}
5865 
5866 // Prefetch instructions for allocation.
5867 // Must be safe to execute with invalid address (cannot fault).
5868 
5869 instruct prefetchAlloc( memory mem ) %{
5870   predicate(AllocatePrefetchInstr==3);
5871   match(PrefetchAllocation mem);
5872   ins_cost(125);
5873 
5874   format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5875   ins_encode %{
5876     __ prefetchw($mem$$Address);
5877   %}
5878   ins_pipe(ialu_mem);
5879 %}
5880 
5881 instruct prefetchAllocNTA( memory mem ) %{
5882   predicate(AllocatePrefetchInstr==0);
5883   match(PrefetchAllocation mem);
5884   ins_cost(125);
5885 
5886   format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5887   ins_encode %{
5888     __ prefetchnta($mem$$Address);
5889   %}
5890   ins_pipe(ialu_mem);
5891 %}
5892 
5893 instruct prefetchAllocT0( memory mem ) %{
5894   predicate(AllocatePrefetchInstr==1);
5895   match(PrefetchAllocation mem);
5896   ins_cost(125);
5897 
5898   format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5899   ins_encode %{
5900     __ prefetcht0($mem$$Address);
5901   %}
5902   ins_pipe(ialu_mem);
5903 %}
5904 
5905 instruct prefetchAllocT2( memory mem ) %{
5906   predicate(AllocatePrefetchInstr==2);
5907   match(PrefetchAllocation mem);
5908   ins_cost(125);
5909 
5910   format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5911   ins_encode %{
5912     __ prefetcht2($mem$$Address);
5913   %}
5914   ins_pipe(ialu_mem);
5915 %}
5916 
5917 //----------Store Instructions-------------------------------------------------
5918 
5919 // Store Byte
5920 instruct storeB(memory mem, rRegI src)
5921 %{
5922   match(Set mem (StoreB mem src));
5923 
5924   ins_cost(125); // XXX
5925   format %{ "movb    $mem, $src\t# byte" %}
5926   opcode(0x88);
5927   ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5928   ins_pipe(ialu_mem_reg);
5929 %}
5930 
5931 // Store Char/Short
5932 instruct storeC(memory mem, rRegI src)
5933 %{
5934   match(Set mem (StoreC mem src));
5935 
5936   ins_cost(125); // XXX
5937   format %{ "movw    $mem, $src\t# char/short" %}
5938   opcode(0x89);
5939   ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5940   ins_pipe(ialu_mem_reg);
5941 %}
5942 
5943 // Store Integer
5944 instruct storeI(memory mem, rRegI src)
5945 %{
5946   match(Set mem (StoreI mem src));
5947 
5948   ins_cost(125); // XXX
5949   format %{ "movl    $mem, $src\t# int" %}
5950   opcode(0x89);
5951   ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5952   ins_pipe(ialu_mem_reg);
5953 %}
5954 
5955 // Store Long
5956 instruct storeL(memory mem, rRegL src)
5957 %{
5958   match(Set mem (StoreL mem src));
5959 
5960   ins_cost(125); // XXX
5961   format %{ "movq    $mem, $src\t# long" %}
5962   opcode(0x89);
5963   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5964   ins_pipe(ialu_mem_reg); // XXX
5965 %}
5966 
5967 // Store Pointer
5968 instruct storeP(memory mem, any_RegP src)
5969 %{
5970   match(Set mem (StoreP mem src));
5971 
5972   ins_cost(125); // XXX
5973   format %{ "movq    $mem, $src\t# ptr" %}
5974   opcode(0x89);
5975   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5976   ins_pipe(ialu_mem_reg);
5977 %}
5978 
5979 instruct storeImmP0(memory mem, immP0 zero)
5980 %{
5981   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5982   match(Set mem (StoreP mem zero));
5983 
5984   ins_cost(125); // XXX
5985   format %{ "movq    $mem, R12\t# ptr (R12_heapbase==0)" %}
5986   ins_encode %{
5987     __ movq($mem$$Address, r12);
5988   %}
5989   ins_pipe(ialu_mem_reg);
5990 %}
5991 
5992 // Store NULL Pointer, mark word, or other simple pointer constant.
5993 instruct storeImmP(memory mem, immP31 src)
5994 %{
5995   match(Set mem (StoreP mem src));
5996 
5997   ins_cost(150); // XXX
5998   format %{ "movq    $mem, $src\t# ptr" %}
5999   opcode(0xC7); /* C7 /0 */
6000   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6001   ins_pipe(ialu_mem_imm);
6002 %}
6003 
6004 // Store Compressed Pointer
6005 instruct storeN(memory mem, rRegN src)
6006 %{
6007   match(Set mem (StoreN mem src));
6008 
6009   ins_cost(125); // XXX
6010   format %{ "movl    $mem, $src\t# compressed ptr" %}
6011   ins_encode %{
6012     __ movl($mem$$Address, $src$$Register);
6013   %}
6014   ins_pipe(ialu_mem_reg);
6015 %}
6016 
6017 instruct storeNKlass(memory mem, rRegN src)
6018 %{
6019   match(Set mem (StoreNKlass mem src));
6020 
6021   ins_cost(125); // XXX
6022   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
6023   ins_encode %{
6024     __ movl($mem$$Address, $src$$Register);
6025   %}
6026   ins_pipe(ialu_mem_reg);
6027 %}
6028 
6029 instruct storeImmN0(memory mem, immN0 zero)
6030 %{
6031   predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6032   match(Set mem (StoreN mem zero));
6033 
6034   ins_cost(125); // XXX
6035   format %{ "movl    $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6036   ins_encode %{
6037     __ movl($mem$$Address, r12);
6038   %}
6039   ins_pipe(ialu_mem_reg);
6040 %}
6041 
6042 instruct storeImmN(memory mem, immN src)
6043 %{
6044   match(Set mem (StoreN mem src));
6045 
6046   ins_cost(150); // XXX
6047   format %{ "movl    $mem, $src\t# compressed ptr" %}
6048   ins_encode %{
6049     address con = (address)$src$$constant;
6050     if (con == NULL) {
6051       __ movl($mem$$Address, (int32_t)0);
6052     } else {
6053       __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6054     }
6055   %}
6056   ins_pipe(ialu_mem_imm);
6057 %}
6058 
6059 instruct storeImmNKlass(memory mem, immNKlass src)
6060 %{
6061   match(Set mem (StoreNKlass mem src));
6062 
6063   ins_cost(150); // XXX
6064   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
6065   ins_encode %{
6066     __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6067   %}
6068   ins_pipe(ialu_mem_imm);
6069 %}
6070 
6071 // Store Integer Immediate
6072 instruct storeImmI0(memory mem, immI0 zero)
6073 %{
6074   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6075   match(Set mem (StoreI mem zero));
6076 
6077   ins_cost(125); // XXX
6078   format %{ "movl    $mem, R12\t# int (R12_heapbase==0)" %}
6079   ins_encode %{
6080     __ movl($mem$$Address, r12);
6081   %}
6082   ins_pipe(ialu_mem_reg);
6083 %}
6084 
6085 instruct storeImmI(memory mem, immI src)
6086 %{
6087   match(Set mem (StoreI mem src));
6088 
6089   ins_cost(150);
6090   format %{ "movl    $mem, $src\t# int" %}
6091   opcode(0xC7); /* C7 /0 */
6092   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6093   ins_pipe(ialu_mem_imm);
6094 %}
6095 
6096 // Store Long Immediate
6097 instruct storeImmL0(memory mem, immL0 zero)
6098 %{
6099   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6100   match(Set mem (StoreL mem zero));
6101 
6102   ins_cost(125); // XXX
6103   format %{ "movq    $mem, R12\t# long (R12_heapbase==0)" %}
6104   ins_encode %{
6105     __ movq($mem$$Address, r12);
6106   %}
6107   ins_pipe(ialu_mem_reg);
6108 %}
6109 
6110 instruct storeImmL(memory mem, immL32 src)
6111 %{
6112   match(Set mem (StoreL mem src));
6113 
6114   ins_cost(150);
6115   format %{ "movq    $mem, $src\t# long" %}
6116   opcode(0xC7); /* C7 /0 */
6117   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6118   ins_pipe(ialu_mem_imm);
6119 %}
6120 
6121 // Store Short/Char Immediate
6122 instruct storeImmC0(memory mem, immI0 zero)
6123 %{
6124   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6125   match(Set mem (StoreC mem zero));
6126 
6127   ins_cost(125); // XXX
6128   format %{ "movw    $mem, R12\t# short/char (R12_heapbase==0)" %}
6129   ins_encode %{
6130     __ movw($mem$$Address, r12);
6131   %}
6132   ins_pipe(ialu_mem_reg);
6133 %}
6134 
6135 instruct storeImmI16(memory mem, immI16 src)
6136 %{
6137   predicate(UseStoreImmI16);
6138   match(Set mem (StoreC mem src));
6139 
6140   ins_cost(150);
6141   format %{ "movw    $mem, $src\t# short/char" %}
6142   opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6143   ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6144   ins_pipe(ialu_mem_imm);
6145 %}
6146 
6147 // Store Byte Immediate
6148 instruct storeImmB0(memory mem, immI0 zero)
6149 %{
6150   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6151   match(Set mem (StoreB mem zero));
6152 
6153   ins_cost(125); // XXX
6154   format %{ "movb    $mem, R12\t# short/char (R12_heapbase==0)" %}
6155   ins_encode %{
6156     __ movb($mem$$Address, r12);
6157   %}
6158   ins_pipe(ialu_mem_reg);
6159 %}
6160 
6161 instruct storeImmB(memory mem, immI8 src)
6162 %{
6163   match(Set mem (StoreB mem src));
6164 
6165   ins_cost(150); // XXX
6166   format %{ "movb    $mem, $src\t# byte" %}
6167   opcode(0xC6); /* C6 /0 */
6168   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6169   ins_pipe(ialu_mem_imm);
6170 %}
6171 
6172 // Store CMS card-mark Immediate
6173 instruct storeImmCM0_reg(memory mem, immI0 zero)
6174 %{
6175   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6176   match(Set mem (StoreCM mem zero));
6177 
6178   ins_cost(125); // XXX
6179   format %{ "movb    $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6180   ins_encode %{
6181     __ movb($mem$$Address, r12);
6182   %}
6183   ins_pipe(ialu_mem_reg);
6184 %}
6185 
6186 instruct storeImmCM0(memory mem, immI0 src)
6187 %{
6188   match(Set mem (StoreCM mem src));
6189 
6190   ins_cost(150); // XXX
6191   format %{ "movb    $mem, $src\t# CMS card-mark byte 0" %}
6192   opcode(0xC6); /* C6 /0 */
6193   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6194   ins_pipe(ialu_mem_imm);
6195 %}
6196 
6197 // Store Float
6198 instruct storeF(memory mem, regF src)
6199 %{
6200   match(Set mem (StoreF mem src));
6201 
6202   ins_cost(95); // XXX
6203   format %{ "movss   $mem, $src\t# float" %}
6204   ins_encode %{
6205     __ movflt($mem$$Address, $src$$XMMRegister);
6206   %}
6207   ins_pipe(pipe_slow); // XXX
6208 %}
6209 
6210 // Store immediate Float value (it is faster than store from XMM register)
6211 instruct storeF0(memory mem, immF0 zero)
6212 %{
6213   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6214   match(Set mem (StoreF mem zero));
6215 
6216   ins_cost(25); // XXX
6217   format %{ "movl    $mem, R12\t# float 0. (R12_heapbase==0)" %}
6218   ins_encode %{
6219     __ movl($mem$$Address, r12);
6220   %}
6221   ins_pipe(ialu_mem_reg);
6222 %}
6223 
6224 instruct storeF_imm(memory mem, immF src)
6225 %{
6226   match(Set mem (StoreF mem src));
6227 
6228   ins_cost(50);
6229   format %{ "movl    $mem, $src\t# float" %}
6230   opcode(0xC7); /* C7 /0 */
6231   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6232   ins_pipe(ialu_mem_imm);
6233 %}
6234 
6235 // Store Double
6236 instruct storeD(memory mem, regD src)
6237 %{
6238   match(Set mem (StoreD mem src));
6239 
6240   ins_cost(95); // XXX
6241   format %{ "movsd   $mem, $src\t# double" %}
6242   ins_encode %{
6243     __ movdbl($mem$$Address, $src$$XMMRegister);
6244   %}
6245   ins_pipe(pipe_slow); // XXX
6246 %}
6247 
6248 // Store immediate double 0.0 (it is faster than store from XMM register)
6249 instruct storeD0_imm(memory mem, immD0 src)
6250 %{
6251   predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6252   match(Set mem (StoreD mem src));
6253 
6254   ins_cost(50);
6255   format %{ "movq    $mem, $src\t# double 0." %}
6256   opcode(0xC7); /* C7 /0 */
6257   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6258   ins_pipe(ialu_mem_imm);
6259 %}
6260 
6261 instruct storeD0(memory mem, immD0 zero)
6262 %{
6263   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6264   match(Set mem (StoreD mem zero));
6265 
6266   ins_cost(25); // XXX
6267   format %{ "movq    $mem, R12\t# double 0. (R12_heapbase==0)" %}
6268   ins_encode %{
6269     __ movq($mem$$Address, r12);
6270   %}
6271   ins_pipe(ialu_mem_reg);
6272 %}
6273 
6274 instruct storeSSI(stackSlotI dst, rRegI src)
6275 %{
6276   match(Set dst src);
6277 
6278   ins_cost(100);
6279   format %{ "movl    $dst, $src\t# int stk" %}
6280   opcode(0x89);
6281   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6282   ins_pipe( ialu_mem_reg );
6283 %}
6284 
6285 instruct storeSSL(stackSlotL dst, rRegL src)
6286 %{
6287   match(Set dst src);
6288 
6289   ins_cost(100);
6290   format %{ "movq    $dst, $src\t# long stk" %}
6291   opcode(0x89);
6292   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6293   ins_pipe(ialu_mem_reg);
6294 %}
6295 
6296 instruct storeSSP(stackSlotP dst, rRegP src)
6297 %{
6298   match(Set dst src);
6299 
6300   ins_cost(100);
6301   format %{ "movq    $dst, $src\t# ptr stk" %}
6302   opcode(0x89);
6303   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6304   ins_pipe(ialu_mem_reg);
6305 %}
6306 
6307 instruct storeSSF(stackSlotF dst, regF src)
6308 %{
6309   match(Set dst src);
6310 
6311   ins_cost(95); // XXX
6312   format %{ "movss   $dst, $src\t# float stk" %}
6313   ins_encode %{
6314     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6315   %}
6316   ins_pipe(pipe_slow); // XXX
6317 %}
6318 
6319 instruct storeSSD(stackSlotD dst, regD src)
6320 %{
6321   match(Set dst src);
6322 
6323   ins_cost(95); // XXX
6324   format %{ "movsd   $dst, $src\t# double stk" %}
6325   ins_encode %{
6326     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6327   %}
6328   ins_pipe(pipe_slow); // XXX
6329 %}
6330 
6331 //----------BSWAP Instructions-------------------------------------------------
6332 instruct bytes_reverse_int(rRegI dst) %{
6333   match(Set dst (ReverseBytesI dst));
6334 
6335   format %{ "bswapl  $dst" %}
6336   opcode(0x0F, 0xC8);  /*Opcode 0F /C8 */
6337   ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6338   ins_pipe( ialu_reg );
6339 %}
6340 
6341 instruct bytes_reverse_long(rRegL dst) %{
6342   match(Set dst (ReverseBytesL dst));
6343 
6344   format %{ "bswapq  $dst" %}
6345   opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6346   ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6347   ins_pipe( ialu_reg);
6348 %}
6349 
6350 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6351   match(Set dst (ReverseBytesUS dst));
6352   effect(KILL cr);
6353 
6354   format %{ "bswapl  $dst\n\t"
6355             "shrl    $dst,16\n\t" %}
6356   ins_encode %{
6357     __ bswapl($dst$$Register);
6358     __ shrl($dst$$Register, 16);
6359   %}
6360   ins_pipe( ialu_reg );
6361 %}
6362 
6363 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6364   match(Set dst (ReverseBytesS dst));
6365   effect(KILL cr);
6366 
6367   format %{ "bswapl  $dst\n\t"
6368             "sar     $dst,16\n\t" %}
6369   ins_encode %{
6370     __ bswapl($dst$$Register);
6371     __ sarl($dst$$Register, 16);
6372   %}
6373   ins_pipe( ialu_reg );
6374 %}
6375 
6376 //---------- Zeros Count Instructions ------------------------------------------
6377 
6378 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6379   predicate(UseCountLeadingZerosInstruction);
6380   match(Set dst (CountLeadingZerosI src));
6381   effect(KILL cr);
6382 
6383   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
6384   ins_encode %{
6385     __ lzcntl($dst$$Register, $src$$Register);
6386   %}
6387   ins_pipe(ialu_reg);
6388 %}
6389 
6390 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6391   predicate(!UseCountLeadingZerosInstruction);
6392   match(Set dst (CountLeadingZerosI src));
6393   effect(KILL cr);
6394 
6395   format %{ "bsrl    $dst, $src\t# count leading zeros (int)\n\t"
6396             "jnz     skip\n\t"
6397             "movl    $dst, -1\n"
6398       "skip:\n\t"
6399             "negl    $dst\n\t"
6400             "addl    $dst, 31" %}
6401   ins_encode %{
6402     Register Rdst = $dst$$Register;
6403     Register Rsrc = $src$$Register;
6404     Label skip;
6405     __ bsrl(Rdst, Rsrc);
6406     __ jccb(Assembler::notZero, skip);
6407     __ movl(Rdst, -1);
6408     __ bind(skip);
6409     __ negl(Rdst);
6410     __ addl(Rdst, BitsPerInt - 1);
6411   %}
6412   ins_pipe(ialu_reg);
6413 %}
6414 
6415 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6416   predicate(UseCountLeadingZerosInstruction);
6417   match(Set dst (CountLeadingZerosL src));
6418   effect(KILL cr);
6419 
6420   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
6421   ins_encode %{
6422     __ lzcntq($dst$$Register, $src$$Register);
6423   %}
6424   ins_pipe(ialu_reg);
6425 %}
6426 
6427 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6428   predicate(!UseCountLeadingZerosInstruction);
6429   match(Set dst (CountLeadingZerosL src));
6430   effect(KILL cr);
6431 
6432   format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
6433             "jnz     skip\n\t"
6434             "movl    $dst, -1\n"
6435       "skip:\n\t"
6436             "negl    $dst\n\t"
6437             "addl    $dst, 63" %}
6438   ins_encode %{
6439     Register Rdst = $dst$$Register;
6440     Register Rsrc = $src$$Register;
6441     Label skip;
6442     __ bsrq(Rdst, Rsrc);
6443     __ jccb(Assembler::notZero, skip);
6444     __ movl(Rdst, -1);
6445     __ bind(skip);
6446     __ negl(Rdst);
6447     __ addl(Rdst, BitsPerLong - 1);
6448   %}
6449   ins_pipe(ialu_reg);
6450 %}
6451 
6452 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6453   predicate(UseCountTrailingZerosInstruction);
6454   match(Set dst (CountTrailingZerosI src));
6455   effect(KILL cr);
6456 
6457   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
6458   ins_encode %{
6459     __ tzcntl($dst$$Register, $src$$Register);
6460   %}
6461   ins_pipe(ialu_reg);
6462 %}
6463 
6464 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6465   predicate(!UseCountTrailingZerosInstruction);
6466   match(Set dst (CountTrailingZerosI src));
6467   effect(KILL cr);
6468 
6469   format %{ "bsfl    $dst, $src\t# count trailing zeros (int)\n\t"
6470             "jnz     done\n\t"
6471             "movl    $dst, 32\n"
6472       "done:" %}
6473   ins_encode %{
6474     Register Rdst = $dst$$Register;
6475     Label done;
6476     __ bsfl(Rdst, $src$$Register);
6477     __ jccb(Assembler::notZero, done);
6478     __ movl(Rdst, BitsPerInt);
6479     __ bind(done);
6480   %}
6481   ins_pipe(ialu_reg);
6482 %}
6483 
6484 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6485   predicate(UseCountTrailingZerosInstruction);
6486   match(Set dst (CountTrailingZerosL src));
6487   effect(KILL cr);
6488 
6489   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
6490   ins_encode %{
6491     __ tzcntq($dst$$Register, $src$$Register);
6492   %}
6493   ins_pipe(ialu_reg);
6494 %}
6495 
6496 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6497   predicate(!UseCountTrailingZerosInstruction);
6498   match(Set dst (CountTrailingZerosL src));
6499   effect(KILL cr);
6500 
6501   format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
6502             "jnz     done\n\t"
6503             "movl    $dst, 64\n"
6504       "done:" %}
6505   ins_encode %{
6506     Register Rdst = $dst$$Register;
6507     Label done;
6508     __ bsfq(Rdst, $src$$Register);
6509     __ jccb(Assembler::notZero, done);
6510     __ movl(Rdst, BitsPerLong);
6511     __ bind(done);
6512   %}
6513   ins_pipe(ialu_reg);
6514 %}
6515 
6516 
6517 //---------- Population Count Instructions -------------------------------------
6518 
6519 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6520   predicate(UsePopCountInstruction);
6521   match(Set dst (PopCountI src));
6522   effect(KILL cr);
6523 
6524   format %{ "popcnt  $dst, $src" %}
6525   ins_encode %{
6526     __ popcntl($dst$$Register, $src$$Register);
6527   %}
6528   ins_pipe(ialu_reg);
6529 %}
6530 
6531 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6532   predicate(UsePopCountInstruction);
6533   match(Set dst (PopCountI (LoadI mem)));
6534   effect(KILL cr);
6535 
6536   format %{ "popcnt  $dst, $mem" %}
6537   ins_encode %{
6538     __ popcntl($dst$$Register, $mem$$Address);
6539   %}
6540   ins_pipe(ialu_reg);
6541 %}
6542 
6543 // Note: Long.bitCount(long) returns an int.
6544 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6545   predicate(UsePopCountInstruction);
6546   match(Set dst (PopCountL src));
6547   effect(KILL cr);
6548 
6549   format %{ "popcnt  $dst, $src" %}
6550   ins_encode %{
6551     __ popcntq($dst$$Register, $src$$Register);
6552   %}
6553   ins_pipe(ialu_reg);
6554 %}
6555 
6556 // Note: Long.bitCount(long) returns an int.
6557 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6558   predicate(UsePopCountInstruction);
6559   match(Set dst (PopCountL (LoadL mem)));
6560   effect(KILL cr);
6561 
6562   format %{ "popcnt  $dst, $mem" %}
6563   ins_encode %{
6564     __ popcntq($dst$$Register, $mem$$Address);
6565   %}
6566   ins_pipe(ialu_reg);
6567 %}
6568 
6569 
6570 //----------MemBar Instructions-----------------------------------------------
6571 // Memory barrier flavors
6572 
6573 instruct membar_acquire()
6574 %{
6575   match(MemBarAcquire);
6576   match(LoadFence);
6577   ins_cost(0);
6578 
6579   size(0);
6580   format %{ "MEMBAR-acquire ! (empty encoding)" %}
6581   ins_encode();
6582   ins_pipe(empty);
6583 %}
6584 
6585 instruct membar_acquire_lock()
6586 %{
6587   match(MemBarAcquireLock);
6588   ins_cost(0);
6589 
6590   size(0);
6591   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6592   ins_encode();
6593   ins_pipe(empty);
6594 %}
6595 
6596 instruct membar_release()
6597 %{
6598   match(MemBarRelease);
6599   match(StoreFence);
6600   ins_cost(0);
6601 
6602   size(0);
6603   format %{ "MEMBAR-release ! (empty encoding)" %}
6604   ins_encode();
6605   ins_pipe(empty);
6606 %}
6607 
6608 instruct membar_release_lock()
6609 %{
6610   match(MemBarReleaseLock);
6611   ins_cost(0);
6612 
6613   size(0);
6614   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6615   ins_encode();
6616   ins_pipe(empty);
6617 %}
6618 
6619 instruct membar_volatile(rFlagsReg cr) %{
6620   match(MemBarVolatile);
6621   effect(KILL cr);
6622   ins_cost(400);
6623 
6624   format %{
6625     $$template
6626     if (os::is_MP()) {
6627       $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6628     } else {
6629       $$emit$$"MEMBAR-volatile ! (empty encoding)"
6630     }
6631   %}
6632   ins_encode %{
6633     __ membar(Assembler::StoreLoad);
6634   %}
6635   ins_pipe(pipe_slow);
6636 %}
6637 
6638 instruct unnecessary_membar_volatile()
6639 %{
6640   match(MemBarVolatile);
6641   predicate(Matcher::post_store_load_barrier(n));
6642   ins_cost(0);
6643 
6644   size(0);
6645   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6646   ins_encode();
6647   ins_pipe(empty);
6648 %}
6649 
6650 instruct membar_storestore() %{
6651   match(MemBarStoreStore);
6652   ins_cost(0);
6653 
6654   size(0);
6655   format %{ "MEMBAR-storestore (empty encoding)" %}
6656   ins_encode( );
6657   ins_pipe(empty);
6658 %}
6659 
6660 //----------Move Instructions--------------------------------------------------
6661 
6662 instruct castX2P(rRegP dst, rRegL src)
6663 %{
6664   match(Set dst (CastX2P src));
6665 
6666   format %{ "movq    $dst, $src\t# long->ptr" %}
6667   ins_encode %{
6668     if ($dst$$reg != $src$$reg) {
6669       __ movptr($dst$$Register, $src$$Register);
6670     }
6671   %}
6672   ins_pipe(ialu_reg_reg); // XXX
6673 %}
6674 
6675 instruct castP2X(rRegL dst, rRegP src)
6676 %{
6677   match(Set dst (CastP2X src));
6678 
6679   format %{ "movq    $dst, $src\t# ptr -> long" %}
6680   ins_encode %{
6681     if ($dst$$reg != $src$$reg) {
6682       __ movptr($dst$$Register, $src$$Register);
6683     }
6684   %}
6685   ins_pipe(ialu_reg_reg); // XXX
6686 %}
6687 
6688 // Convert oop into int for vectors alignment masking
6689 instruct convP2I(rRegI dst, rRegP src)
6690 %{
6691   match(Set dst (ConvL2I (CastP2X src)));
6692 
6693   format %{ "movl    $dst, $src\t# ptr -> int" %}
6694   ins_encode %{
6695     __ movl($dst$$Register, $src$$Register);
6696   %}
6697   ins_pipe(ialu_reg_reg); // XXX
6698 %}
6699 
6700 // Convert compressed oop into int for vectors alignment masking
6701 // in case of 32bit oops (heap < 4Gb).
6702 instruct convN2I(rRegI dst, rRegN src)
6703 %{
6704   predicate(Universe::narrow_oop_shift() == 0);
6705   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6706 
6707   format %{ "movl    $dst, $src\t# compressed ptr -> int" %}
6708   ins_encode %{
6709     __ movl($dst$$Register, $src$$Register);
6710   %}
6711   ins_pipe(ialu_reg_reg); // XXX
6712 %}
6713 
6714 // Convert oop pointer into compressed form
6715 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6716   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6717   match(Set dst (EncodeP src));
6718   effect(KILL cr);
6719   format %{ "encode_heap_oop $dst,$src" %}
6720   ins_encode %{
6721     Register s = $src$$Register;
6722     Register d = $dst$$Register;
6723     if (s != d) {
6724       __ movq(d, s);
6725     }
6726     __ encode_heap_oop(d);
6727   %}
6728   ins_pipe(ialu_reg_long);
6729 %}
6730 
6731 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6732   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6733   match(Set dst (EncodeP src));
6734   effect(KILL cr);
6735   format %{ "encode_heap_oop_not_null $dst,$src" %}
6736   ins_encode %{
6737     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6738   %}
6739   ins_pipe(ialu_reg_long);
6740 %}
6741 
6742 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6743   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6744             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6745   match(Set dst (DecodeN src));
6746   effect(KILL cr);
6747   format %{ "decode_heap_oop $dst,$src" %}
6748   ins_encode %{
6749     Register s = $src$$Register;
6750     Register d = $dst$$Register;
6751     if (s != d) {
6752       __ movq(d, s);
6753     }
6754     __ decode_heap_oop(d);
6755   %}
6756   ins_pipe(ialu_reg_long);
6757 %}
6758 
6759 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6760   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6761             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6762   match(Set dst (DecodeN src));
6763   effect(KILL cr);
6764   format %{ "decode_heap_oop_not_null $dst,$src" %}
6765   ins_encode %{
6766     Register s = $src$$Register;
6767     Register d = $dst$$Register;
6768     if (s != d) {
6769       __ decode_heap_oop_not_null(d, s);
6770     } else {
6771       __ decode_heap_oop_not_null(d);
6772     }
6773   %}
6774   ins_pipe(ialu_reg_long);
6775 %}
6776 
6777 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6778   match(Set dst (EncodePKlass src));
6779   effect(KILL cr);
6780   format %{ "encode_klass_not_null $dst,$src" %}
6781   ins_encode %{
6782     __ encode_klass_not_null($dst$$Register, $src$$Register);
6783   %}
6784   ins_pipe(ialu_reg_long);
6785 %}
6786 
6787 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6788   match(Set dst (DecodeNKlass src));
6789   effect(KILL cr);
6790   format %{ "decode_klass_not_null $dst,$src" %}
6791   ins_encode %{
6792     Register s = $src$$Register;
6793     Register d = $dst$$Register;
6794     if (s != d) {
6795       __ decode_klass_not_null(d, s);
6796     } else {
6797       __ decode_klass_not_null(d);
6798     }
6799   %}
6800   ins_pipe(ialu_reg_long);
6801 %}
6802 
6803 
6804 //----------Conditional Move---------------------------------------------------
6805 // Jump
6806 // dummy instruction for generating temp registers
6807 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6808   match(Jump (LShiftL switch_val shift));
6809   ins_cost(350);
6810   predicate(false);
6811   effect(TEMP dest);
6812 
6813   format %{ "leaq    $dest, [$constantaddress]\n\t"
6814             "jmp     [$dest + $switch_val << $shift]\n\t" %}
6815   ins_encode %{
6816     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6817     // to do that and the compiler is using that register as one it can allocate.
6818     // So we build it all by hand.
6819     // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6820     // ArrayAddress dispatch(table, index);
6821     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6822     __ lea($dest$$Register, $constantaddress);
6823     __ jmp(dispatch);
6824   %}
6825   ins_pipe(pipe_jmp);
6826 %}
6827 
6828 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6829   match(Jump (AddL (LShiftL switch_val shift) offset));
6830   ins_cost(350);
6831   effect(TEMP dest);
6832 
6833   format %{ "leaq    $dest, [$constantaddress]\n\t"
6834             "jmp     [$dest + $switch_val << $shift + $offset]\n\t" %}
6835   ins_encode %{
6836     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6837     // to do that and the compiler is using that register as one it can allocate.
6838     // So we build it all by hand.
6839     // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6840     // ArrayAddress dispatch(table, index);
6841     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6842     __ lea($dest$$Register, $constantaddress);
6843     __ jmp(dispatch);
6844   %}
6845   ins_pipe(pipe_jmp);
6846 %}
6847 
6848 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6849   match(Jump switch_val);
6850   ins_cost(350);
6851   effect(TEMP dest);
6852 
6853   format %{ "leaq    $dest, [$constantaddress]\n\t"
6854             "jmp     [$dest + $switch_val]\n\t" %}
6855   ins_encode %{
6856     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6857     // to do that and the compiler is using that register as one it can allocate.
6858     // So we build it all by hand.
6859     // Address index(noreg, switch_reg, Address::times_1);
6860     // ArrayAddress dispatch(table, index);
6861     Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6862     __ lea($dest$$Register, $constantaddress);
6863     __ jmp(dispatch);
6864   %}
6865   ins_pipe(pipe_jmp);
6866 %}
6867 
6868 // Conditional move
6869 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6870 %{
6871   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6872 
6873   ins_cost(200); // XXX
6874   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6875   opcode(0x0F, 0x40);
6876   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6877   ins_pipe(pipe_cmov_reg);
6878 %}
6879 
6880 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6881   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6882 
6883   ins_cost(200); // XXX
6884   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6885   opcode(0x0F, 0x40);
6886   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6887   ins_pipe(pipe_cmov_reg);
6888 %}
6889 
6890 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6891   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6892   ins_cost(200);
6893   expand %{
6894     cmovI_regU(cop, cr, dst, src);
6895   %}
6896 %}
6897 
6898 // Conditional move
6899 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6900   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6901 
6902   ins_cost(250); // XXX
6903   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6904   opcode(0x0F, 0x40);
6905   ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6906   ins_pipe(pipe_cmov_mem);
6907 %}
6908 
6909 // Conditional move
6910 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6911 %{
6912   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6913 
6914   ins_cost(250); // XXX
6915   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6916   opcode(0x0F, 0x40);
6917   ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6918   ins_pipe(pipe_cmov_mem);
6919 %}
6920 
6921 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6922   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6923   ins_cost(250);
6924   expand %{
6925     cmovI_memU(cop, cr, dst, src);
6926   %}
6927 %}
6928 
6929 // Conditional move
6930 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6931 %{
6932   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6933 
6934   ins_cost(200); // XXX
6935   format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6936   opcode(0x0F, 0x40);
6937   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6938   ins_pipe(pipe_cmov_reg);
6939 %}
6940 
6941 // Conditional move
6942 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6943 %{
6944   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6945 
6946   ins_cost(200); // XXX
6947   format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6948   opcode(0x0F, 0x40);
6949   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6950   ins_pipe(pipe_cmov_reg);
6951 %}
6952 
6953 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6954   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6955   ins_cost(200);
6956   expand %{
6957     cmovN_regU(cop, cr, dst, src);
6958   %}
6959 %}
6960 
6961 // Conditional move
6962 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6963 %{
6964   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6965 
6966   ins_cost(200); // XXX
6967   format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6968   opcode(0x0F, 0x40);
6969   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6970   ins_pipe(pipe_cmov_reg);  // XXX
6971 %}
6972 
6973 // Conditional move
6974 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6975 %{
6976   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6977 
6978   ins_cost(200); // XXX
6979   format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6980   opcode(0x0F, 0x40);
6981   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6982   ins_pipe(pipe_cmov_reg); // XXX
6983 %}
6984 
6985 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6986   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6987   ins_cost(200);
6988   expand %{
6989     cmovP_regU(cop, cr, dst, src);
6990   %}
6991 %}
6992 
6993 // DISABLED: Requires the ADLC to emit a bottom_type call that
6994 // correctly meets the two pointer arguments; one is an incoming
6995 // register but the other is a memory operand.  ALSO appears to
6996 // be buggy with implicit null checks.
6997 //
6998 //// Conditional move
6999 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7000 //%{
7001 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7002 //  ins_cost(250);
7003 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7004 //  opcode(0x0F,0x40);
7005 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7006 //  ins_pipe( pipe_cmov_mem );
7007 //%}
7008 //
7009 //// Conditional move
7010 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7011 //%{
7012 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7013 //  ins_cost(250);
7014 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7015 //  opcode(0x0F,0x40);
7016 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7017 //  ins_pipe( pipe_cmov_mem );
7018 //%}
7019 
7020 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7021 %{
7022   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7023 
7024   ins_cost(200); // XXX
7025   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7026   opcode(0x0F, 0x40);
7027   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7028   ins_pipe(pipe_cmov_reg);  // XXX
7029 %}
7030 
7031 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7032 %{
7033   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7034 
7035   ins_cost(200); // XXX
7036   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7037   opcode(0x0F, 0x40);
7038   ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7039   ins_pipe(pipe_cmov_mem);  // XXX
7040 %}
7041 
7042 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7043 %{
7044   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7045 
7046   ins_cost(200); // XXX
7047   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7048   opcode(0x0F, 0x40);
7049   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7050   ins_pipe(pipe_cmov_reg); // XXX
7051 %}
7052 
7053 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7054   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7055   ins_cost(200);
7056   expand %{
7057     cmovL_regU(cop, cr, dst, src);
7058   %}
7059 %}
7060 
7061 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7062 %{
7063   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7064 
7065   ins_cost(200); // XXX
7066   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7067   opcode(0x0F, 0x40);
7068   ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7069   ins_pipe(pipe_cmov_mem); // XXX
7070 %}
7071 
7072 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7073   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7074   ins_cost(200);
7075   expand %{
7076     cmovL_memU(cop, cr, dst, src);
7077   %}
7078 %}
7079 
7080 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7081 %{
7082   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7083 
7084   ins_cost(200); // XXX
7085   format %{ "jn$cop    skip\t# signed cmove float\n\t"
7086             "movss     $dst, $src\n"
7087     "skip:" %}
7088   ins_encode %{
7089     Label Lskip;
7090     // Invert sense of branch from sense of CMOV
7091     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7092     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7093     __ bind(Lskip);
7094   %}
7095   ins_pipe(pipe_slow);
7096 %}
7097 
7098 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7099 // %{
7100 //   match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7101 
7102 //   ins_cost(200); // XXX
7103 //   format %{ "jn$cop    skip\t# signed cmove float\n\t"
7104 //             "movss     $dst, $src\n"
7105 //     "skip:" %}
7106 //   ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7107 //   ins_pipe(pipe_slow);
7108 // %}
7109 
7110 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7111 %{
7112   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7113 
7114   ins_cost(200); // XXX
7115   format %{ "jn$cop    skip\t# unsigned cmove float\n\t"
7116             "movss     $dst, $src\n"
7117     "skip:" %}
7118   ins_encode %{
7119     Label Lskip;
7120     // Invert sense of branch from sense of CMOV
7121     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7122     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7123     __ bind(Lskip);
7124   %}
7125   ins_pipe(pipe_slow);
7126 %}
7127 
7128 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7129   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7130   ins_cost(200);
7131   expand %{
7132     cmovF_regU(cop, cr, dst, src);
7133   %}
7134 %}
7135 
7136 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7137 %{
7138   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7139 
7140   ins_cost(200); // XXX
7141   format %{ "jn$cop    skip\t# signed cmove double\n\t"
7142             "movsd     $dst, $src\n"
7143     "skip:" %}
7144   ins_encode %{
7145     Label Lskip;
7146     // Invert sense of branch from sense of CMOV
7147     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7148     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7149     __ bind(Lskip);
7150   %}
7151   ins_pipe(pipe_slow);
7152 %}
7153 
7154 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7155 %{
7156   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7157 
7158   ins_cost(200); // XXX
7159   format %{ "jn$cop    skip\t# unsigned cmove double\n\t"
7160             "movsd     $dst, $src\n"
7161     "skip:" %}
7162   ins_encode %{
7163     Label Lskip;
7164     // Invert sense of branch from sense of CMOV
7165     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7166     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7167     __ bind(Lskip);
7168   %}
7169   ins_pipe(pipe_slow);
7170 %}
7171 
7172 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7173   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7174   ins_cost(200);
7175   expand %{
7176     cmovD_regU(cop, cr, dst, src);
7177   %}
7178 %}
7179 
7180 //----------Arithmetic Instructions--------------------------------------------
7181 //----------Addition Instructions----------------------------------------------
7182 
7183 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7184 %{
7185   match(Set dst (AddI dst src));
7186   effect(KILL cr);
7187 
7188   format %{ "addl    $dst, $src\t# int" %}
7189   opcode(0x03);
7190   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7191   ins_pipe(ialu_reg_reg);
7192 %}
7193 
7194 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7195 %{
7196   match(Set dst (AddI dst src));
7197   effect(KILL cr);
7198 
7199   format %{ "addl    $dst, $src\t# int" %}
7200   opcode(0x81, 0x00); /* /0 id */
7201   ins_encode(OpcSErm(dst, src), Con8or32(src));
7202   ins_pipe( ialu_reg );
7203 %}
7204 
7205 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7206 %{
7207   match(Set dst (AddI dst (LoadI src)));
7208   effect(KILL cr);
7209 
7210   ins_cost(125); // XXX
7211   format %{ "addl    $dst, $src\t# int" %}
7212   opcode(0x03);
7213   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7214   ins_pipe(ialu_reg_mem);
7215 %}
7216 
7217 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7218 %{
7219   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7220   effect(KILL cr);
7221 
7222   ins_cost(150); // XXX
7223   format %{ "addl    $dst, $src\t# int" %}
7224   opcode(0x01); /* Opcode 01 /r */
7225   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7226   ins_pipe(ialu_mem_reg);
7227 %}
7228 
7229 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7230 %{
7231   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7232   effect(KILL cr);
7233 
7234   ins_cost(125); // XXX
7235   format %{ "addl    $dst, $src\t# int" %}
7236   opcode(0x81); /* Opcode 81 /0 id */
7237   ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7238   ins_pipe(ialu_mem_imm);
7239 %}
7240 
7241 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7242 %{
7243   predicate(UseIncDec);
7244   match(Set dst (AddI dst src));
7245   effect(KILL cr);
7246 
7247   format %{ "incl    $dst\t# int" %}
7248   opcode(0xFF, 0x00); // FF /0
7249   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7250   ins_pipe(ialu_reg);
7251 %}
7252 
7253 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7254 %{
7255   predicate(UseIncDec);
7256   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7257   effect(KILL cr);
7258 
7259   ins_cost(125); // XXX
7260   format %{ "incl    $dst\t# int" %}
7261   opcode(0xFF); /* Opcode FF /0 */
7262   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7263   ins_pipe(ialu_mem_imm);
7264 %}
7265 
7266 // XXX why does that use AddI
7267 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7268 %{
7269   predicate(UseIncDec);
7270   match(Set dst (AddI dst src));
7271   effect(KILL cr);
7272 
7273   format %{ "decl    $dst\t# int" %}
7274   opcode(0xFF, 0x01); // FF /1
7275   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7276   ins_pipe(ialu_reg);
7277 %}
7278 
7279 // XXX why does that use AddI
7280 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7281 %{
7282   predicate(UseIncDec);
7283   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7284   effect(KILL cr);
7285 
7286   ins_cost(125); // XXX
7287   format %{ "decl    $dst\t# int" %}
7288   opcode(0xFF); /* Opcode FF /1 */
7289   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7290   ins_pipe(ialu_mem_imm);
7291 %}
7292 
7293 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7294 %{
7295   match(Set dst (AddI src0 src1));
7296 
7297   ins_cost(110);
7298   format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7299   opcode(0x8D); /* 0x8D /r */
7300   ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7301   ins_pipe(ialu_reg_reg);
7302 %}
7303 
7304 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7305 %{
7306   match(Set dst (AddL dst src));
7307   effect(KILL cr);
7308 
7309   format %{ "addq    $dst, $src\t# long" %}
7310   opcode(0x03);
7311   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7312   ins_pipe(ialu_reg_reg);
7313 %}
7314 
7315 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7316 %{
7317   match(Set dst (AddL dst src));
7318   effect(KILL cr);
7319 
7320   format %{ "addq    $dst, $src\t# long" %}
7321   opcode(0x81, 0x00); /* /0 id */
7322   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7323   ins_pipe( ialu_reg );
7324 %}
7325 
7326 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7327 %{
7328   match(Set dst (AddL dst (LoadL src)));
7329   effect(KILL cr);
7330 
7331   ins_cost(125); // XXX
7332   format %{ "addq    $dst, $src\t# long" %}
7333   opcode(0x03);
7334   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7335   ins_pipe(ialu_reg_mem);
7336 %}
7337 
7338 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7339 %{
7340   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7341   effect(KILL cr);
7342 
7343   ins_cost(150); // XXX
7344   format %{ "addq    $dst, $src\t# long" %}
7345   opcode(0x01); /* Opcode 01 /r */
7346   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7347   ins_pipe(ialu_mem_reg);
7348 %}
7349 
7350 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7351 %{
7352   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7353   effect(KILL cr);
7354 
7355   ins_cost(125); // XXX
7356   format %{ "addq    $dst, $src\t# long" %}
7357   opcode(0x81); /* Opcode 81 /0 id */
7358   ins_encode(REX_mem_wide(dst),
7359              OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7360   ins_pipe(ialu_mem_imm);
7361 %}
7362 
7363 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7364 %{
7365   predicate(UseIncDec);
7366   match(Set dst (AddL dst src));
7367   effect(KILL cr);
7368 
7369   format %{ "incq    $dst\t# long" %}
7370   opcode(0xFF, 0x00); // FF /0
7371   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7372   ins_pipe(ialu_reg);
7373 %}
7374 
7375 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7376 %{
7377   predicate(UseIncDec);
7378   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7379   effect(KILL cr);
7380 
7381   ins_cost(125); // XXX
7382   format %{ "incq    $dst\t# long" %}
7383   opcode(0xFF); /* Opcode FF /0 */
7384   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7385   ins_pipe(ialu_mem_imm);
7386 %}
7387 
7388 // XXX why does that use AddL
7389 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7390 %{
7391   predicate(UseIncDec);
7392   match(Set dst (AddL dst src));
7393   effect(KILL cr);
7394 
7395   format %{ "decq    $dst\t# long" %}
7396   opcode(0xFF, 0x01); // FF /1
7397   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7398   ins_pipe(ialu_reg);
7399 %}
7400 
7401 // XXX why does that use AddL
7402 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7403 %{
7404   predicate(UseIncDec);
7405   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7406   effect(KILL cr);
7407 
7408   ins_cost(125); // XXX
7409   format %{ "decq    $dst\t# long" %}
7410   opcode(0xFF); /* Opcode FF /1 */
7411   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7412   ins_pipe(ialu_mem_imm);
7413 %}
7414 
7415 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7416 %{
7417   match(Set dst (AddL src0 src1));
7418 
7419   ins_cost(110);
7420   format %{ "leaq    $dst, [$src0 + $src1]\t# long" %}
7421   opcode(0x8D); /* 0x8D /r */
7422   ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7423   ins_pipe(ialu_reg_reg);
7424 %}
7425 
7426 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7427 %{
7428   match(Set dst (AddP dst src));
7429   effect(KILL cr);
7430 
7431   format %{ "addq    $dst, $src\t# ptr" %}
7432   opcode(0x03);
7433   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7434   ins_pipe(ialu_reg_reg);
7435 %}
7436 
7437 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7438 %{
7439   match(Set dst (AddP dst src));
7440   effect(KILL cr);
7441 
7442   format %{ "addq    $dst, $src\t# ptr" %}
7443   opcode(0x81, 0x00); /* /0 id */
7444   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7445   ins_pipe( ialu_reg );
7446 %}
7447 
7448 // XXX addP mem ops ????
7449 
7450 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7451 %{
7452   match(Set dst (AddP src0 src1));
7453 
7454   ins_cost(110);
7455   format %{ "leaq    $dst, [$src0 + $src1]\t# ptr" %}
7456   opcode(0x8D); /* 0x8D /r */
7457   ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7458   ins_pipe(ialu_reg_reg);
7459 %}
7460 
7461 instruct checkCastPP(rRegP dst)
7462 %{
7463   match(Set dst (CheckCastPP dst));
7464 
7465   size(0);
7466   format %{ "# checkcastPP of $dst" %}
7467   ins_encode(/* empty encoding */);
7468   ins_pipe(empty);
7469 %}
7470 
7471 instruct castPP(rRegP dst)
7472 %{
7473   match(Set dst (CastPP dst));
7474 
7475   size(0);
7476   format %{ "# castPP of $dst" %}
7477   ins_encode(/* empty encoding */);
7478   ins_pipe(empty);
7479 %}
7480 
7481 instruct castII(rRegI dst)
7482 %{
7483   match(Set dst (CastII dst));
7484 
7485   size(0);
7486   format %{ "# castII of $dst" %}
7487   ins_encode(/* empty encoding */);
7488   ins_cost(0);
7489   ins_pipe(empty);
7490 %}
7491 
7492 // LoadP-locked same as a regular LoadP when used with compare-swap
7493 instruct loadPLocked(rRegP dst, memory mem)
7494 %{
7495   match(Set dst (LoadPLocked mem));
7496 
7497   ins_cost(125); // XXX
7498   format %{ "movq    $dst, $mem\t# ptr locked" %}
7499   opcode(0x8B);
7500   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7501   ins_pipe(ialu_reg_mem); // XXX
7502 %}
7503 
7504 // Conditional-store of the updated heap-top.
7505 // Used during allocation of the shared heap.
7506 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
7507 
7508 instruct storePConditional(memory heap_top_ptr,
7509                            rax_RegP oldval, rRegP newval,
7510                            rFlagsReg cr)
7511 %{
7512   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7513 
7514   format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7515             "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7516   opcode(0x0F, 0xB1);
7517   ins_encode(lock_prefix,
7518              REX_reg_mem_wide(newval, heap_top_ptr),
7519              OpcP, OpcS,
7520              reg_mem(newval, heap_top_ptr));
7521   ins_pipe(pipe_cmpxchg);
7522 %}
7523 
7524 // Conditional-store of an int value.
7525 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
7526 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7527 %{
7528   match(Set cr (StoreIConditional mem (Binary oldval newval)));
7529   effect(KILL oldval);
7530 
7531   format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7532   opcode(0x0F, 0xB1);
7533   ins_encode(lock_prefix,
7534              REX_reg_mem(newval, mem),
7535              OpcP, OpcS,
7536              reg_mem(newval, mem));
7537   ins_pipe(pipe_cmpxchg);
7538 %}
7539 
7540 // Conditional-store of a long value.
7541 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
7542 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7543 %{
7544   match(Set cr (StoreLConditional mem (Binary oldval newval)));
7545   effect(KILL oldval);
7546 
7547   format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7548   opcode(0x0F, 0xB1);
7549   ins_encode(lock_prefix,
7550              REX_reg_mem_wide(newval, mem),
7551              OpcP, OpcS,
7552              reg_mem(newval, mem));
7553   ins_pipe(pipe_cmpxchg);
7554 %}
7555 
7556 
7557 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7558 instruct compareAndSwapP(rRegI res,
7559                          memory mem_ptr,
7560                          rax_RegP oldval, rRegP newval,
7561                          rFlagsReg cr)
7562 %{
7563   predicate(VM_Version::supports_cx8());
7564   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7565   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7566   effect(KILL cr, KILL oldval);
7567 
7568   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7569             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7570             "sete    $res\n\t"
7571             "movzbl  $res, $res" %}
7572   opcode(0x0F, 0xB1);
7573   ins_encode(lock_prefix,
7574              REX_reg_mem_wide(newval, mem_ptr),
7575              OpcP, OpcS,
7576              reg_mem(newval, mem_ptr),
7577              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7578              REX_reg_breg(res, res), // movzbl
7579              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7580   ins_pipe( pipe_cmpxchg );
7581 %}
7582 
7583 instruct compareAndSwapL(rRegI res,
7584                          memory mem_ptr,
7585                          rax_RegL oldval, rRegL newval,
7586                          rFlagsReg cr)
7587 %{
7588   predicate(VM_Version::supports_cx8());
7589   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7590   match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7591   effect(KILL cr, KILL oldval);
7592 
7593   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7594             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7595             "sete    $res\n\t"
7596             "movzbl  $res, $res" %}
7597   opcode(0x0F, 0xB1);
7598   ins_encode(lock_prefix,
7599              REX_reg_mem_wide(newval, mem_ptr),
7600              OpcP, OpcS,
7601              reg_mem(newval, mem_ptr),
7602              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7603              REX_reg_breg(res, res), // movzbl
7604              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7605   ins_pipe( pipe_cmpxchg );
7606 %}
7607 
7608 instruct compareAndSwapI(rRegI res,
7609                          memory mem_ptr,
7610                          rax_RegI oldval, rRegI newval,
7611                          rFlagsReg cr)
7612 %{
7613   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7614   match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7615   effect(KILL cr, KILL oldval);
7616 
7617   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7618             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7619             "sete    $res\n\t"
7620             "movzbl  $res, $res" %}
7621   opcode(0x0F, 0xB1);
7622   ins_encode(lock_prefix,
7623              REX_reg_mem(newval, mem_ptr),
7624              OpcP, OpcS,
7625              reg_mem(newval, mem_ptr),
7626              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7627              REX_reg_breg(res, res), // movzbl
7628              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7629   ins_pipe( pipe_cmpxchg );
7630 %}
7631 
7632 instruct compareAndSwapB(rRegI res,
7633                          memory mem_ptr,
7634                          rax_RegI oldval, rRegI newval,
7635                          rFlagsReg cr)
7636 %{
7637   match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7638   match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7639   effect(KILL cr, KILL oldval);
7640 
7641   format %{ "cmpxchgb $mem_ptr,$newval\t# "
7642             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7643             "sete    $res\n\t"
7644             "movzbl  $res, $res" %}
7645   opcode(0x0F, 0xB0);
7646   ins_encode(lock_prefix,
7647              REX_breg_mem(newval, mem_ptr),
7648              OpcP, OpcS,
7649              reg_mem(newval, mem_ptr),
7650              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7651              REX_reg_breg(res, res), // movzbl
7652              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7653   ins_pipe( pipe_cmpxchg );
7654 %}
7655 
7656 instruct compareAndSwapS(rRegI res,
7657                          memory mem_ptr,
7658                          rax_RegI oldval, rRegI newval,
7659                          rFlagsReg cr)
7660 %{
7661   match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7662   match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7663   effect(KILL cr, KILL oldval);
7664 
7665   format %{ "cmpxchgw $mem_ptr,$newval\t# "
7666             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7667             "sete    $res\n\t"
7668             "movzbl  $res, $res" %}
7669   opcode(0x0F, 0xB1);
7670   ins_encode(lock_prefix,
7671              SizePrefix,
7672              REX_reg_mem(newval, mem_ptr),
7673              OpcP, OpcS,
7674              reg_mem(newval, mem_ptr),
7675              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7676              REX_reg_breg(res, res), // movzbl
7677              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7678   ins_pipe( pipe_cmpxchg );
7679 %}
7680 
7681 instruct compareAndSwapN(rRegI res,
7682                           memory mem_ptr,
7683                           rax_RegN oldval, rRegN newval,
7684                           rFlagsReg cr) %{
7685   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7686   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7687   effect(KILL cr, KILL oldval);
7688 
7689   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7690             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7691             "sete    $res\n\t"
7692             "movzbl  $res, $res" %}
7693   opcode(0x0F, 0xB1);
7694   ins_encode(lock_prefix,
7695              REX_reg_mem(newval, mem_ptr),
7696              OpcP, OpcS,
7697              reg_mem(newval, mem_ptr),
7698              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7699              REX_reg_breg(res, res), // movzbl
7700              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7701   ins_pipe( pipe_cmpxchg );
7702 %}
7703 
7704 instruct compareAndExchangeB(
7705                          memory mem_ptr,
7706                          rax_RegI oldval, rRegI newval,
7707                          rFlagsReg cr)
7708 %{
7709   match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7710   effect(KILL cr);
7711 
7712   format %{ "cmpxchgb $mem_ptr,$newval\t# "
7713             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7714   opcode(0x0F, 0xB0);
7715   ins_encode(lock_prefix,
7716              REX_breg_mem(newval, mem_ptr),
7717              OpcP, OpcS,
7718              reg_mem(newval, mem_ptr) // lock cmpxchg
7719              );
7720   ins_pipe( pipe_cmpxchg );
7721 %}
7722 
7723 instruct compareAndExchangeS(
7724                          memory mem_ptr,
7725                          rax_RegI oldval, rRegI newval,
7726                          rFlagsReg cr)
7727 %{
7728   match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7729   effect(KILL cr);
7730 
7731   format %{ "cmpxchgw $mem_ptr,$newval\t# "
7732             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7733   opcode(0x0F, 0xB1);
7734   ins_encode(lock_prefix,
7735              SizePrefix,
7736              REX_reg_mem(newval, mem_ptr),
7737              OpcP, OpcS,
7738              reg_mem(newval, mem_ptr) // lock cmpxchg
7739              );
7740   ins_pipe( pipe_cmpxchg );
7741 %}
7742 
7743 instruct compareAndExchangeI(
7744                          memory mem_ptr,
7745                          rax_RegI oldval, rRegI newval,
7746                          rFlagsReg cr)
7747 %{
7748   match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7749   effect(KILL cr);
7750 
7751   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7752             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7753   opcode(0x0F, 0xB1);
7754   ins_encode(lock_prefix,
7755              REX_reg_mem(newval, mem_ptr),
7756              OpcP, OpcS,
7757              reg_mem(newval, mem_ptr) // lock cmpxchg
7758              );
7759   ins_pipe( pipe_cmpxchg );
7760 %}
7761 
7762 instruct compareAndExchangeL(
7763                          memory mem_ptr,
7764                          rax_RegL oldval, rRegL newval,
7765                          rFlagsReg cr)
7766 %{
7767   predicate(VM_Version::supports_cx8());
7768   match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7769   effect(KILL cr);
7770 
7771   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7772             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7773   opcode(0x0F, 0xB1);
7774   ins_encode(lock_prefix,
7775              REX_reg_mem_wide(newval, mem_ptr),
7776              OpcP, OpcS,
7777              reg_mem(newval, mem_ptr)  // lock cmpxchg
7778             );
7779   ins_pipe( pipe_cmpxchg );
7780 %}
7781 
7782 instruct compareAndExchangeN(
7783                           memory mem_ptr,
7784                           rax_RegN oldval, rRegN newval,
7785                           rFlagsReg cr) %{
7786   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7787   effect(KILL cr);
7788 
7789   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7790             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7791   opcode(0x0F, 0xB1);
7792   ins_encode(lock_prefix,
7793              REX_reg_mem(newval, mem_ptr),
7794              OpcP, OpcS,
7795              reg_mem(newval, mem_ptr)  // lock cmpxchg
7796           );
7797   ins_pipe( pipe_cmpxchg );
7798 %}
7799 
7800 instruct compareAndExchangeP(
7801                          memory mem_ptr,
7802                          rax_RegP oldval, rRegP newval,
7803                          rFlagsReg cr)
7804 %{
7805   predicate(VM_Version::supports_cx8());
7806   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7807   effect(KILL cr);
7808 
7809   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7810             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7811   opcode(0x0F, 0xB1);
7812   ins_encode(lock_prefix,
7813              REX_reg_mem_wide(newval, mem_ptr),
7814              OpcP, OpcS,
7815              reg_mem(newval, mem_ptr)  // lock cmpxchg
7816           );
7817   ins_pipe( pipe_cmpxchg );
7818 %}
7819 
7820 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7821   predicate(n->as_LoadStore()->result_not_used());
7822   match(Set dummy (GetAndAddB mem add));
7823   effect(KILL cr);
7824   format %{ "ADDB  [$mem],$add" %}
7825   ins_encode %{
7826     if (os::is_MP()) { __ lock(); }
7827     __ addb($mem$$Address, $add$$constant);
7828   %}
7829   ins_pipe( pipe_cmpxchg );
7830 %}
7831 
7832 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7833   match(Set newval (GetAndAddB mem newval));
7834   effect(KILL cr);
7835   format %{ "XADDB  [$mem],$newval" %}
7836   ins_encode %{
7837     if (os::is_MP()) { __ lock(); }
7838     __ xaddb($mem$$Address, $newval$$Register);
7839   %}
7840   ins_pipe( pipe_cmpxchg );
7841 %}
7842 
7843 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7844   predicate(n->as_LoadStore()->result_not_used());
7845   match(Set dummy (GetAndAddS mem add));
7846   effect(KILL cr);
7847   format %{ "ADDW  [$mem],$add" %}
7848   ins_encode %{
7849     if (os::is_MP()) { __ lock(); }
7850     __ addw($mem$$Address, $add$$constant);
7851   %}
7852   ins_pipe( pipe_cmpxchg );
7853 %}
7854 
7855 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
7856   match(Set newval (GetAndAddS mem newval));
7857   effect(KILL cr);
7858   format %{ "XADDW  [$mem],$newval" %}
7859   ins_encode %{
7860     if (os::is_MP()) { __ lock(); }
7861     __ xaddw($mem$$Address, $newval$$Register);
7862   %}
7863   ins_pipe( pipe_cmpxchg );
7864 %}
7865 
7866 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7867   predicate(n->as_LoadStore()->result_not_used());
7868   match(Set dummy (GetAndAddI mem add));
7869   effect(KILL cr);
7870   format %{ "ADDL  [$mem],$add" %}
7871   ins_encode %{
7872     if (os::is_MP()) { __ lock(); }
7873     __ addl($mem$$Address, $add$$constant);
7874   %}
7875   ins_pipe( pipe_cmpxchg );
7876 %}
7877 
7878 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7879   match(Set newval (GetAndAddI mem newval));
7880   effect(KILL cr);
7881   format %{ "XADDL  [$mem],$newval" %}
7882   ins_encode %{
7883     if (os::is_MP()) { __ lock(); }
7884     __ xaddl($mem$$Address, $newval$$Register);
7885   %}
7886   ins_pipe( pipe_cmpxchg );
7887 %}
7888 
7889 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7890   predicate(n->as_LoadStore()->result_not_used());
7891   match(Set dummy (GetAndAddL mem add));
7892   effect(KILL cr);
7893   format %{ "ADDQ  [$mem],$add" %}
7894   ins_encode %{
7895     if (os::is_MP()) { __ lock(); }
7896     __ addq($mem$$Address, $add$$constant);
7897   %}
7898   ins_pipe( pipe_cmpxchg );
7899 %}
7900 
7901 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7902   match(Set newval (GetAndAddL mem newval));
7903   effect(KILL cr);
7904   format %{ "XADDQ  [$mem],$newval" %}
7905   ins_encode %{
7906     if (os::is_MP()) { __ lock(); }
7907     __ xaddq($mem$$Address, $newval$$Register);
7908   %}
7909   ins_pipe( pipe_cmpxchg );
7910 %}
7911 
7912 instruct xchgB( memory mem, rRegI newval) %{
7913   match(Set newval (GetAndSetB mem newval));
7914   format %{ "XCHGB  $newval,[$mem]" %}
7915   ins_encode %{
7916     __ xchgb($newval$$Register, $mem$$Address);
7917   %}
7918   ins_pipe( pipe_cmpxchg );
7919 %}
7920 
7921 instruct xchgS( memory mem, rRegI newval) %{
7922   match(Set newval (GetAndSetS mem newval));
7923   format %{ "XCHGW  $newval,[$mem]" %}
7924   ins_encode %{
7925     __ xchgw($newval$$Register, $mem$$Address);
7926   %}
7927   ins_pipe( pipe_cmpxchg );
7928 %}
7929 
7930 instruct xchgI( memory mem, rRegI newval) %{
7931   match(Set newval (GetAndSetI mem newval));
7932   format %{ "XCHGL  $newval,[$mem]" %}
7933   ins_encode %{
7934     __ xchgl($newval$$Register, $mem$$Address);
7935   %}
7936   ins_pipe( pipe_cmpxchg );
7937 %}
7938 
7939 instruct xchgL( memory mem, rRegL newval) %{
7940   match(Set newval (GetAndSetL mem newval));
7941   format %{ "XCHGL  $newval,[$mem]" %}
7942   ins_encode %{
7943     __ xchgq($newval$$Register, $mem$$Address);
7944   %}
7945   ins_pipe( pipe_cmpxchg );
7946 %}
7947 
7948 instruct xchgP( memory mem, rRegP newval) %{
7949   match(Set newval (GetAndSetP mem newval));
7950   format %{ "XCHGQ  $newval,[$mem]" %}
7951   ins_encode %{
7952     __ xchgq($newval$$Register, $mem$$Address);
7953   %}
7954   ins_pipe( pipe_cmpxchg );
7955 %}
7956 
7957 instruct xchgN( memory mem, rRegN newval) %{
7958   match(Set newval (GetAndSetN mem newval));
7959   format %{ "XCHGL  $newval,$mem]" %}
7960   ins_encode %{
7961     __ xchgl($newval$$Register, $mem$$Address);
7962   %}
7963   ins_pipe( pipe_cmpxchg );
7964 %}
7965 
7966 //----------Subtraction Instructions-------------------------------------------
7967 
7968 // Integer Subtraction Instructions
7969 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7970 %{
7971   match(Set dst (SubI dst src));
7972   effect(KILL cr);
7973 
7974   format %{ "subl    $dst, $src\t# int" %}
7975   opcode(0x2B);
7976   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7977   ins_pipe(ialu_reg_reg);
7978 %}
7979 
7980 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7981 %{
7982   match(Set dst (SubI dst src));
7983   effect(KILL cr);
7984 
7985   format %{ "subl    $dst, $src\t# int" %}
7986   opcode(0x81, 0x05);  /* Opcode 81 /5 */
7987   ins_encode(OpcSErm(dst, src), Con8or32(src));
7988   ins_pipe(ialu_reg);
7989 %}
7990 
7991 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7992 %{
7993   match(Set dst (SubI dst (LoadI src)));
7994   effect(KILL cr);
7995 
7996   ins_cost(125);
7997   format %{ "subl    $dst, $src\t# int" %}
7998   opcode(0x2B);
7999   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8000   ins_pipe(ialu_reg_mem);
8001 %}
8002 
8003 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8004 %{
8005   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8006   effect(KILL cr);
8007 
8008   ins_cost(150);
8009   format %{ "subl    $dst, $src\t# int" %}
8010   opcode(0x29); /* Opcode 29 /r */
8011   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8012   ins_pipe(ialu_mem_reg);
8013 %}
8014 
8015 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8016 %{
8017   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8018   effect(KILL cr);
8019 
8020   ins_cost(125); // XXX
8021   format %{ "subl    $dst, $src\t# int" %}
8022   opcode(0x81); /* Opcode 81 /5 id */
8023   ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8024   ins_pipe(ialu_mem_imm);
8025 %}
8026 
8027 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8028 %{
8029   match(Set dst (SubL dst src));
8030   effect(KILL cr);
8031 
8032   format %{ "subq    $dst, $src\t# long" %}
8033   opcode(0x2B);
8034   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8035   ins_pipe(ialu_reg_reg);
8036 %}
8037 
8038 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8039 %{
8040   match(Set dst (SubL dst src));
8041   effect(KILL cr);
8042 
8043   format %{ "subq    $dst, $src\t# long" %}
8044   opcode(0x81, 0x05);  /* Opcode 81 /5 */
8045   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8046   ins_pipe(ialu_reg);
8047 %}
8048 
8049 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8050 %{
8051   match(Set dst (SubL dst (LoadL src)));
8052   effect(KILL cr);
8053 
8054   ins_cost(125);
8055   format %{ "subq    $dst, $src\t# long" %}
8056   opcode(0x2B);
8057   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8058   ins_pipe(ialu_reg_mem);
8059 %}
8060 
8061 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8062 %{
8063   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8064   effect(KILL cr);
8065 
8066   ins_cost(150);
8067   format %{ "subq    $dst, $src\t# long" %}
8068   opcode(0x29); /* Opcode 29 /r */
8069   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8070   ins_pipe(ialu_mem_reg);
8071 %}
8072 
8073 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8074 %{
8075   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8076   effect(KILL cr);
8077 
8078   ins_cost(125); // XXX
8079   format %{ "subq    $dst, $src\t# long" %}
8080   opcode(0x81); /* Opcode 81 /5 id */
8081   ins_encode(REX_mem_wide(dst),
8082              OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8083   ins_pipe(ialu_mem_imm);
8084 %}
8085 
8086 // Subtract from a pointer
8087 // XXX hmpf???
8088 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8089 %{
8090   match(Set dst (AddP dst (SubI zero src)));
8091   effect(KILL cr);
8092 
8093   format %{ "subq    $dst, $src\t# ptr - int" %}
8094   opcode(0x2B);
8095   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8096   ins_pipe(ialu_reg_reg);
8097 %}
8098 
8099 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8100 %{
8101   match(Set dst (SubI zero dst));
8102   effect(KILL cr);
8103 
8104   format %{ "negl    $dst\t# int" %}
8105   opcode(0xF7, 0x03);  // Opcode F7 /3
8106   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8107   ins_pipe(ialu_reg);
8108 %}
8109 
8110 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8111 %{
8112   match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8113   effect(KILL cr);
8114 
8115   format %{ "negl    $dst\t# int" %}
8116   opcode(0xF7, 0x03);  // Opcode F7 /3
8117   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8118   ins_pipe(ialu_reg);
8119 %}
8120 
8121 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8122 %{
8123   match(Set dst (SubL zero dst));
8124   effect(KILL cr);
8125 
8126   format %{ "negq    $dst\t# long" %}
8127   opcode(0xF7, 0x03);  // Opcode F7 /3
8128   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8129   ins_pipe(ialu_reg);
8130 %}
8131 
8132 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8133 %{
8134   match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8135   effect(KILL cr);
8136 
8137   format %{ "negq    $dst\t# long" %}
8138   opcode(0xF7, 0x03);  // Opcode F7 /3
8139   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8140   ins_pipe(ialu_reg);
8141 %}
8142 
8143 //----------Multiplication/Division Instructions-------------------------------
8144 // Integer Multiplication Instructions
8145 // Multiply Register
8146 
8147 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8148 %{
8149   match(Set dst (MulI dst src));
8150   effect(KILL cr);
8151 
8152   ins_cost(300);
8153   format %{ "imull   $dst, $src\t# int" %}
8154   opcode(0x0F, 0xAF);
8155   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8156   ins_pipe(ialu_reg_reg_alu0);
8157 %}
8158 
8159 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8160 %{
8161   match(Set dst (MulI src imm));
8162   effect(KILL cr);
8163 
8164   ins_cost(300);
8165   format %{ "imull   $dst, $src, $imm\t# int" %}
8166   opcode(0x69); /* 69 /r id */
8167   ins_encode(REX_reg_reg(dst, src),
8168              OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8169   ins_pipe(ialu_reg_reg_alu0);
8170 %}
8171 
8172 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8173 %{
8174   match(Set dst (MulI dst (LoadI src)));
8175   effect(KILL cr);
8176 
8177   ins_cost(350);
8178   format %{ "imull   $dst, $src\t# int" %}
8179   opcode(0x0F, 0xAF);
8180   ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8181   ins_pipe(ialu_reg_mem_alu0);
8182 %}
8183 
8184 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8185 %{
8186   match(Set dst (MulI (LoadI src) imm));
8187   effect(KILL cr);
8188 
8189   ins_cost(300);
8190   format %{ "imull   $dst, $src, $imm\t# int" %}
8191   opcode(0x69); /* 69 /r id */
8192   ins_encode(REX_reg_mem(dst, src),
8193              OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8194   ins_pipe(ialu_reg_mem_alu0);
8195 %}
8196 
8197 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8198 %{
8199   match(Set dst (MulL dst src));
8200   effect(KILL cr);
8201 
8202   ins_cost(300);
8203   format %{ "imulq   $dst, $src\t# long" %}
8204   opcode(0x0F, 0xAF);
8205   ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8206   ins_pipe(ialu_reg_reg_alu0);
8207 %}
8208 
8209 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8210 %{
8211   match(Set dst (MulL src imm));
8212   effect(KILL cr);
8213 
8214   ins_cost(300);
8215   format %{ "imulq   $dst, $src, $imm\t# long" %}
8216   opcode(0x69); /* 69 /r id */
8217   ins_encode(REX_reg_reg_wide(dst, src),
8218              OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8219   ins_pipe(ialu_reg_reg_alu0);
8220 %}
8221 
8222 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8223 %{
8224   match(Set dst (MulL dst (LoadL src)));
8225   effect(KILL cr);
8226 
8227   ins_cost(350);
8228   format %{ "imulq   $dst, $src\t# long" %}
8229   opcode(0x0F, 0xAF);
8230   ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8231   ins_pipe(ialu_reg_mem_alu0);
8232 %}
8233 
8234 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8235 %{
8236   match(Set dst (MulL (LoadL src) imm));
8237   effect(KILL cr);
8238 
8239   ins_cost(300);
8240   format %{ "imulq   $dst, $src, $imm\t# long" %}
8241   opcode(0x69); /* 69 /r id */
8242   ins_encode(REX_reg_mem_wide(dst, src),
8243              OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8244   ins_pipe(ialu_reg_mem_alu0);
8245 %}
8246 
8247 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8248 %{
8249   match(Set dst (MulHiL src rax));
8250   effect(USE_KILL rax, KILL cr);
8251 
8252   ins_cost(300);
8253   format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
8254   opcode(0xF7, 0x5); /* Opcode F7 /5 */
8255   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8256   ins_pipe(ialu_reg_reg_alu0);
8257 %}
8258 
8259 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8260                    rFlagsReg cr)
8261 %{
8262   match(Set rax (DivI rax div));
8263   effect(KILL rdx, KILL cr);
8264 
8265   ins_cost(30*100+10*100); // XXX
8266   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
8267             "jne,s   normal\n\t"
8268             "xorl    rdx, rdx\n\t"
8269             "cmpl    $div, -1\n\t"
8270             "je,s    done\n"
8271     "normal: cdql\n\t"
8272             "idivl   $div\n"
8273     "done:"        %}
8274   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8275   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8276   ins_pipe(ialu_reg_reg_alu0);
8277 %}
8278 
8279 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8280                    rFlagsReg cr)
8281 %{
8282   match(Set rax (DivL rax div));
8283   effect(KILL rdx, KILL cr);
8284 
8285   ins_cost(30*100+10*100); // XXX
8286   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
8287             "cmpq    rax, rdx\n\t"
8288             "jne,s   normal\n\t"
8289             "xorl    rdx, rdx\n\t"
8290             "cmpq    $div, -1\n\t"
8291             "je,s    done\n"
8292     "normal: cdqq\n\t"
8293             "idivq   $div\n"
8294     "done:"        %}
8295   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8296   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8297   ins_pipe(ialu_reg_reg_alu0);
8298 %}
8299 
8300 // Integer DIVMOD with Register, both quotient and mod results
8301 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8302                              rFlagsReg cr)
8303 %{
8304   match(DivModI rax div);
8305   effect(KILL cr);
8306 
8307   ins_cost(30*100+10*100); // XXX
8308   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
8309             "jne,s   normal\n\t"
8310             "xorl    rdx, rdx\n\t"
8311             "cmpl    $div, -1\n\t"
8312             "je,s    done\n"
8313     "normal: cdql\n\t"
8314             "idivl   $div\n"
8315     "done:"        %}
8316   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8317   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8318   ins_pipe(pipe_slow);
8319 %}
8320 
8321 // Long DIVMOD with Register, both quotient and mod results
8322 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8323                              rFlagsReg cr)
8324 %{
8325   match(DivModL rax div);
8326   effect(KILL cr);
8327 
8328   ins_cost(30*100+10*100); // XXX
8329   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
8330             "cmpq    rax, rdx\n\t"
8331             "jne,s   normal\n\t"
8332             "xorl    rdx, rdx\n\t"
8333             "cmpq    $div, -1\n\t"
8334             "je,s    done\n"
8335     "normal: cdqq\n\t"
8336             "idivq   $div\n"
8337     "done:"        %}
8338   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8339   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8340   ins_pipe(pipe_slow);
8341 %}
8342 
8343 //----------- DivL-By-Constant-Expansions--------------------------------------
8344 // DivI cases are handled by the compiler
8345 
8346 // Magic constant, reciprocal of 10
8347 instruct loadConL_0x6666666666666667(rRegL dst)
8348 %{
8349   effect(DEF dst);
8350 
8351   format %{ "movq    $dst, #0x666666666666667\t# Used in div-by-10" %}
8352   ins_encode(load_immL(dst, 0x6666666666666667));
8353   ins_pipe(ialu_reg);
8354 %}
8355 
8356 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8357 %{
8358   effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8359 
8360   format %{ "imulq   rdx:rax, rax, $src\t# Used in div-by-10" %}
8361   opcode(0xF7, 0x5); /* Opcode F7 /5 */
8362   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8363   ins_pipe(ialu_reg_reg_alu0);
8364 %}
8365 
8366 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8367 %{
8368   effect(USE_DEF dst, KILL cr);
8369 
8370   format %{ "sarq    $dst, #63\t# Used in div-by-10" %}
8371   opcode(0xC1, 0x7); /* C1 /7 ib */
8372   ins_encode(reg_opc_imm_wide(dst, 0x3F));
8373   ins_pipe(ialu_reg);
8374 %}
8375 
8376 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8377 %{
8378   effect(USE_DEF dst, KILL cr);
8379 
8380   format %{ "sarq    $dst, #2\t# Used in div-by-10" %}
8381   opcode(0xC1, 0x7); /* C1 /7 ib */
8382   ins_encode(reg_opc_imm_wide(dst, 0x2));
8383   ins_pipe(ialu_reg);
8384 %}
8385 
8386 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8387 %{
8388   match(Set dst (DivL src div));
8389 
8390   ins_cost((5+8)*100);
8391   expand %{
8392     rax_RegL rax;                     // Killed temp
8393     rFlagsReg cr;                     // Killed
8394     loadConL_0x6666666666666667(rax); // movq  rax, 0x6666666666666667
8395     mul_hi(dst, src, rax, cr);        // mulq  rdx:rax <= rax * $src
8396     sarL_rReg_63(src, cr);            // sarq  src, 63
8397     sarL_rReg_2(dst, cr);             // sarq  rdx, 2
8398     subL_rReg(dst, src, cr);          // subl  rdx, src
8399   %}
8400 %}
8401 
8402 //-----------------------------------------------------------------------------
8403 
8404 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8405                    rFlagsReg cr)
8406 %{
8407   match(Set rdx (ModI rax div));
8408   effect(KILL rax, KILL cr);
8409 
8410   ins_cost(300); // XXX
8411   format %{ "cmpl    rax, 0x80000000\t# irem\n\t"
8412             "jne,s   normal\n\t"
8413             "xorl    rdx, rdx\n\t"
8414             "cmpl    $div, -1\n\t"
8415             "je,s    done\n"
8416     "normal: cdql\n\t"
8417             "idivl   $div\n"
8418     "done:"        %}
8419   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8420   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8421   ins_pipe(ialu_reg_reg_alu0);
8422 %}
8423 
8424 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8425                    rFlagsReg cr)
8426 %{
8427   match(Set rdx (ModL rax div));
8428   effect(KILL rax, KILL cr);
8429 
8430   ins_cost(300); // XXX
8431   format %{ "movq    rdx, 0x8000000000000000\t# lrem\n\t"
8432             "cmpq    rax, rdx\n\t"
8433             "jne,s   normal\n\t"
8434             "xorl    rdx, rdx\n\t"
8435             "cmpq    $div, -1\n\t"
8436             "je,s    done\n"
8437     "normal: cdqq\n\t"
8438             "idivq   $div\n"
8439     "done:"        %}
8440   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8441   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8442   ins_pipe(ialu_reg_reg_alu0);
8443 %}
8444 
8445 // Integer Shift Instructions
8446 // Shift Left by one
8447 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8448 %{
8449   match(Set dst (LShiftI dst shift));
8450   effect(KILL cr);
8451 
8452   format %{ "sall    $dst, $shift" %}
8453   opcode(0xD1, 0x4); /* D1 /4 */
8454   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8455   ins_pipe(ialu_reg);
8456 %}
8457 
8458 // Shift Left by one
8459 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8460 %{
8461   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8462   effect(KILL cr);
8463 
8464   format %{ "sall    $dst, $shift\t" %}
8465   opcode(0xD1, 0x4); /* D1 /4 */
8466   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8467   ins_pipe(ialu_mem_imm);
8468 %}
8469 
8470 // Shift Left by 8-bit immediate
8471 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8472 %{
8473   match(Set dst (LShiftI dst shift));
8474   effect(KILL cr);
8475 
8476   format %{ "sall    $dst, $shift" %}
8477   opcode(0xC1, 0x4); /* C1 /4 ib */
8478   ins_encode(reg_opc_imm(dst, shift));
8479   ins_pipe(ialu_reg);
8480 %}
8481 
8482 // Shift Left by 8-bit immediate
8483 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8484 %{
8485   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8486   effect(KILL cr);
8487 
8488   format %{ "sall    $dst, $shift" %}
8489   opcode(0xC1, 0x4); /* C1 /4 ib */
8490   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8491   ins_pipe(ialu_mem_imm);
8492 %}
8493 
8494 // Shift Left by variable
8495 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8496 %{
8497   match(Set dst (LShiftI dst shift));
8498   effect(KILL cr);
8499 
8500   format %{ "sall    $dst, $shift" %}
8501   opcode(0xD3, 0x4); /* D3 /4 */
8502   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8503   ins_pipe(ialu_reg_reg);
8504 %}
8505 
8506 // Shift Left by variable
8507 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8508 %{
8509   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8510   effect(KILL cr);
8511 
8512   format %{ "sall    $dst, $shift" %}
8513   opcode(0xD3, 0x4); /* D3 /4 */
8514   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8515   ins_pipe(ialu_mem_reg);
8516 %}
8517 
8518 // Arithmetic shift right by one
8519 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8520 %{
8521   match(Set dst (RShiftI dst shift));
8522   effect(KILL cr);
8523 
8524   format %{ "sarl    $dst, $shift" %}
8525   opcode(0xD1, 0x7); /* D1 /7 */
8526   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8527   ins_pipe(ialu_reg);
8528 %}
8529 
8530 // Arithmetic shift right by one
8531 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8532 %{
8533   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8534   effect(KILL cr);
8535 
8536   format %{ "sarl    $dst, $shift" %}
8537   opcode(0xD1, 0x7); /* D1 /7 */
8538   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8539   ins_pipe(ialu_mem_imm);
8540 %}
8541 
8542 // Arithmetic Shift Right by 8-bit immediate
8543 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8544 %{
8545   match(Set dst (RShiftI dst shift));
8546   effect(KILL cr);
8547 
8548   format %{ "sarl    $dst, $shift" %}
8549   opcode(0xC1, 0x7); /* C1 /7 ib */
8550   ins_encode(reg_opc_imm(dst, shift));
8551   ins_pipe(ialu_mem_imm);
8552 %}
8553 
8554 // Arithmetic Shift Right by 8-bit immediate
8555 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8556 %{
8557   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8558   effect(KILL cr);
8559 
8560   format %{ "sarl    $dst, $shift" %}
8561   opcode(0xC1, 0x7); /* C1 /7 ib */
8562   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8563   ins_pipe(ialu_mem_imm);
8564 %}
8565 
8566 // Arithmetic Shift Right by variable
8567 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8568 %{
8569   match(Set dst (RShiftI dst shift));
8570   effect(KILL cr);
8571 
8572   format %{ "sarl    $dst, $shift" %}
8573   opcode(0xD3, 0x7); /* D3 /7 */
8574   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8575   ins_pipe(ialu_reg_reg);
8576 %}
8577 
8578 // Arithmetic Shift Right by variable
8579 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8580 %{
8581   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8582   effect(KILL cr);
8583 
8584   format %{ "sarl    $dst, $shift" %}
8585   opcode(0xD3, 0x7); /* D3 /7 */
8586   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8587   ins_pipe(ialu_mem_reg);
8588 %}
8589 
8590 // Logical shift right by one
8591 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8592 %{
8593   match(Set dst (URShiftI dst shift));
8594   effect(KILL cr);
8595 
8596   format %{ "shrl    $dst, $shift" %}
8597   opcode(0xD1, 0x5); /* D1 /5 */
8598   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8599   ins_pipe(ialu_reg);
8600 %}
8601 
8602 // Logical shift right by one
8603 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8604 %{
8605   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8606   effect(KILL cr);
8607 
8608   format %{ "shrl    $dst, $shift" %}
8609   opcode(0xD1, 0x5); /* D1 /5 */
8610   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8611   ins_pipe(ialu_mem_imm);
8612 %}
8613 
8614 // Logical Shift Right by 8-bit immediate
8615 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8616 %{
8617   match(Set dst (URShiftI dst shift));
8618   effect(KILL cr);
8619 
8620   format %{ "shrl    $dst, $shift" %}
8621   opcode(0xC1, 0x5); /* C1 /5 ib */
8622   ins_encode(reg_opc_imm(dst, shift));
8623   ins_pipe(ialu_reg);
8624 %}
8625 
8626 // Logical Shift Right by 8-bit immediate
8627 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8628 %{
8629   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8630   effect(KILL cr);
8631 
8632   format %{ "shrl    $dst, $shift" %}
8633   opcode(0xC1, 0x5); /* C1 /5 ib */
8634   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8635   ins_pipe(ialu_mem_imm);
8636 %}
8637 
8638 // Logical Shift Right by variable
8639 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8640 %{
8641   match(Set dst (URShiftI dst shift));
8642   effect(KILL cr);
8643 
8644   format %{ "shrl    $dst, $shift" %}
8645   opcode(0xD3, 0x5); /* D3 /5 */
8646   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8647   ins_pipe(ialu_reg_reg);
8648 %}
8649 
8650 // Logical Shift Right by variable
8651 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8652 %{
8653   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8654   effect(KILL cr);
8655 
8656   format %{ "shrl    $dst, $shift" %}
8657   opcode(0xD3, 0x5); /* D3 /5 */
8658   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8659   ins_pipe(ialu_mem_reg);
8660 %}
8661 
8662 // Long Shift Instructions
8663 // Shift Left by one
8664 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8665 %{
8666   match(Set dst (LShiftL dst shift));
8667   effect(KILL cr);
8668 
8669   format %{ "salq    $dst, $shift" %}
8670   opcode(0xD1, 0x4); /* D1 /4 */
8671   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8672   ins_pipe(ialu_reg);
8673 %}
8674 
8675 // Shift Left by one
8676 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8677 %{
8678   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8679   effect(KILL cr);
8680 
8681   format %{ "salq    $dst, $shift" %}
8682   opcode(0xD1, 0x4); /* D1 /4 */
8683   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8684   ins_pipe(ialu_mem_imm);
8685 %}
8686 
8687 // Shift Left by 8-bit immediate
8688 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8689 %{
8690   match(Set dst (LShiftL dst shift));
8691   effect(KILL cr);
8692 
8693   format %{ "salq    $dst, $shift" %}
8694   opcode(0xC1, 0x4); /* C1 /4 ib */
8695   ins_encode(reg_opc_imm_wide(dst, shift));
8696   ins_pipe(ialu_reg);
8697 %}
8698 
8699 // Shift Left by 8-bit immediate
8700 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8701 %{
8702   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8703   effect(KILL cr);
8704 
8705   format %{ "salq    $dst, $shift" %}
8706   opcode(0xC1, 0x4); /* C1 /4 ib */
8707   ins_encode(REX_mem_wide(dst), OpcP,
8708              RM_opc_mem(secondary, dst), Con8or32(shift));
8709   ins_pipe(ialu_mem_imm);
8710 %}
8711 
8712 // Shift Left by variable
8713 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8714 %{
8715   match(Set dst (LShiftL dst shift));
8716   effect(KILL cr);
8717 
8718   format %{ "salq    $dst, $shift" %}
8719   opcode(0xD3, 0x4); /* D3 /4 */
8720   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8721   ins_pipe(ialu_reg_reg);
8722 %}
8723 
8724 // Shift Left by variable
8725 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8726 %{
8727   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8728   effect(KILL cr);
8729 
8730   format %{ "salq    $dst, $shift" %}
8731   opcode(0xD3, 0x4); /* D3 /4 */
8732   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8733   ins_pipe(ialu_mem_reg);
8734 %}
8735 
8736 // Arithmetic shift right by one
8737 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8738 %{
8739   match(Set dst (RShiftL dst shift));
8740   effect(KILL cr);
8741 
8742   format %{ "sarq    $dst, $shift" %}
8743   opcode(0xD1, 0x7); /* D1 /7 */
8744   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8745   ins_pipe(ialu_reg);
8746 %}
8747 
8748 // Arithmetic shift right by one
8749 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8750 %{
8751   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8752   effect(KILL cr);
8753 
8754   format %{ "sarq    $dst, $shift" %}
8755   opcode(0xD1, 0x7); /* D1 /7 */
8756   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8757   ins_pipe(ialu_mem_imm);
8758 %}
8759 
8760 // Arithmetic Shift Right by 8-bit immediate
8761 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8762 %{
8763   match(Set dst (RShiftL dst shift));
8764   effect(KILL cr);
8765 
8766   format %{ "sarq    $dst, $shift" %}
8767   opcode(0xC1, 0x7); /* C1 /7 ib */
8768   ins_encode(reg_opc_imm_wide(dst, shift));
8769   ins_pipe(ialu_mem_imm);
8770 %}
8771 
8772 // Arithmetic Shift Right by 8-bit immediate
8773 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8774 %{
8775   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8776   effect(KILL cr);
8777 
8778   format %{ "sarq    $dst, $shift" %}
8779   opcode(0xC1, 0x7); /* C1 /7 ib */
8780   ins_encode(REX_mem_wide(dst), OpcP,
8781              RM_opc_mem(secondary, dst), Con8or32(shift));
8782   ins_pipe(ialu_mem_imm);
8783 %}
8784 
8785 // Arithmetic Shift Right by variable
8786 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8787 %{
8788   match(Set dst (RShiftL dst shift));
8789   effect(KILL cr);
8790 
8791   format %{ "sarq    $dst, $shift" %}
8792   opcode(0xD3, 0x7); /* D3 /7 */
8793   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8794   ins_pipe(ialu_reg_reg);
8795 %}
8796 
8797 // Arithmetic Shift Right by variable
8798 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8799 %{
8800   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8801   effect(KILL cr);
8802 
8803   format %{ "sarq    $dst, $shift" %}
8804   opcode(0xD3, 0x7); /* D3 /7 */
8805   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8806   ins_pipe(ialu_mem_reg);
8807 %}
8808 
8809 // Logical shift right by one
8810 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8811 %{
8812   match(Set dst (URShiftL dst shift));
8813   effect(KILL cr);
8814 
8815   format %{ "shrq    $dst, $shift" %}
8816   opcode(0xD1, 0x5); /* D1 /5 */
8817   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8818   ins_pipe(ialu_reg);
8819 %}
8820 
8821 // Logical shift right by one
8822 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8823 %{
8824   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8825   effect(KILL cr);
8826 
8827   format %{ "shrq    $dst, $shift" %}
8828   opcode(0xD1, 0x5); /* D1 /5 */
8829   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8830   ins_pipe(ialu_mem_imm);
8831 %}
8832 
8833 // Logical Shift Right by 8-bit immediate
8834 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8835 %{
8836   match(Set dst (URShiftL dst shift));
8837   effect(KILL cr);
8838 
8839   format %{ "shrq    $dst, $shift" %}
8840   opcode(0xC1, 0x5); /* C1 /5 ib */
8841   ins_encode(reg_opc_imm_wide(dst, shift));
8842   ins_pipe(ialu_reg);
8843 %}
8844 
8845 
8846 // Logical Shift Right by 8-bit immediate
8847 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8848 %{
8849   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8850   effect(KILL cr);
8851 
8852   format %{ "shrq    $dst, $shift" %}
8853   opcode(0xC1, 0x5); /* C1 /5 ib */
8854   ins_encode(REX_mem_wide(dst), OpcP,
8855              RM_opc_mem(secondary, dst), Con8or32(shift));
8856   ins_pipe(ialu_mem_imm);
8857 %}
8858 
8859 // Logical Shift Right by variable
8860 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8861 %{
8862   match(Set dst (URShiftL dst shift));
8863   effect(KILL cr);
8864 
8865   format %{ "shrq    $dst, $shift" %}
8866   opcode(0xD3, 0x5); /* D3 /5 */
8867   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8868   ins_pipe(ialu_reg_reg);
8869 %}
8870 
8871 // Logical Shift Right by variable
8872 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8873 %{
8874   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8875   effect(KILL cr);
8876 
8877   format %{ "shrq    $dst, $shift" %}
8878   opcode(0xD3, 0x5); /* D3 /5 */
8879   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8880   ins_pipe(ialu_mem_reg);
8881 %}
8882 
8883 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8884 // This idiom is used by the compiler for the i2b bytecode.
8885 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8886 %{
8887   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8888 
8889   format %{ "movsbl  $dst, $src\t# i2b" %}
8890   opcode(0x0F, 0xBE);
8891   ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8892   ins_pipe(ialu_reg_reg);
8893 %}
8894 
8895 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8896 // This idiom is used by the compiler the i2s bytecode.
8897 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8898 %{
8899   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8900 
8901   format %{ "movswl  $dst, $src\t# i2s" %}
8902   opcode(0x0F, 0xBF);
8903   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8904   ins_pipe(ialu_reg_reg);
8905 %}
8906 
8907 // ROL/ROR instructions
8908 
8909 // ROL expand
8910 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8911   effect(KILL cr, USE_DEF dst);
8912 
8913   format %{ "roll    $dst" %}
8914   opcode(0xD1, 0x0); /* Opcode  D1 /0 */
8915   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8916   ins_pipe(ialu_reg);
8917 %}
8918 
8919 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8920   effect(USE_DEF dst, USE shift, KILL cr);
8921 
8922   format %{ "roll    $dst, $shift" %}
8923   opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8924   ins_encode( reg_opc_imm(dst, shift) );
8925   ins_pipe(ialu_reg);
8926 %}
8927 
8928 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8929 %{
8930   effect(USE_DEF dst, USE shift, KILL cr);
8931 
8932   format %{ "roll    $dst, $shift" %}
8933   opcode(0xD3, 0x0); /* Opcode D3 /0 */
8934   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8935   ins_pipe(ialu_reg_reg);
8936 %}
8937 // end of ROL expand
8938 
8939 // Rotate Left by one
8940 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8941 %{
8942   match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8943 
8944   expand %{
8945     rolI_rReg_imm1(dst, cr);
8946   %}
8947 %}
8948 
8949 // Rotate Left by 8-bit immediate
8950 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8951 %{
8952   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8953   match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8954 
8955   expand %{
8956     rolI_rReg_imm8(dst, lshift, cr);
8957   %}
8958 %}
8959 
8960 // Rotate Left by variable
8961 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8962 %{
8963   match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8964 
8965   expand %{
8966     rolI_rReg_CL(dst, shift, cr);
8967   %}
8968 %}
8969 
8970 // Rotate Left by variable
8971 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8972 %{
8973   match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8974 
8975   expand %{
8976     rolI_rReg_CL(dst, shift, cr);
8977   %}
8978 %}
8979 
8980 // ROR expand
8981 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8982 %{
8983   effect(USE_DEF dst, KILL cr);
8984 
8985   format %{ "rorl    $dst" %}
8986   opcode(0xD1, 0x1); /* D1 /1 */
8987   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8988   ins_pipe(ialu_reg);
8989 %}
8990 
8991 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8992 %{
8993   effect(USE_DEF dst, USE shift, KILL cr);
8994 
8995   format %{ "rorl    $dst, $shift" %}
8996   opcode(0xC1, 0x1); /* C1 /1 ib */
8997   ins_encode(reg_opc_imm(dst, shift));
8998   ins_pipe(ialu_reg);
8999 %}
9000 
9001 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9002 %{
9003   effect(USE_DEF dst, USE shift, KILL cr);
9004 
9005   format %{ "rorl    $dst, $shift" %}
9006   opcode(0xD3, 0x1); /* D3 /1 */
9007   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9008   ins_pipe(ialu_reg_reg);
9009 %}
9010 // end of ROR expand
9011 
9012 // Rotate Right by one
9013 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9014 %{
9015   match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9016 
9017   expand %{
9018     rorI_rReg_imm1(dst, cr);
9019   %}
9020 %}
9021 
9022 // Rotate Right by 8-bit immediate
9023 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9024 %{
9025   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9026   match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9027 
9028   expand %{
9029     rorI_rReg_imm8(dst, rshift, cr);
9030   %}
9031 %}
9032 
9033 // Rotate Right by variable
9034 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9035 %{
9036   match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9037 
9038   expand %{
9039     rorI_rReg_CL(dst, shift, cr);
9040   %}
9041 %}
9042 
9043 // Rotate Right by variable
9044 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9045 %{
9046   match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9047 
9048   expand %{
9049     rorI_rReg_CL(dst, shift, cr);
9050   %}
9051 %}
9052 
9053 // for long rotate
9054 // ROL expand
9055 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9056   effect(USE_DEF dst, KILL cr);
9057 
9058   format %{ "rolq    $dst" %}
9059   opcode(0xD1, 0x0); /* Opcode  D1 /0 */
9060   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9061   ins_pipe(ialu_reg);
9062 %}
9063 
9064 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9065   effect(USE_DEF dst, USE shift, KILL cr);
9066 
9067   format %{ "rolq    $dst, $shift" %}
9068   opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9069   ins_encode( reg_opc_imm_wide(dst, shift) );
9070   ins_pipe(ialu_reg);
9071 %}
9072 
9073 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9074 %{
9075   effect(USE_DEF dst, USE shift, KILL cr);
9076 
9077   format %{ "rolq    $dst, $shift" %}
9078   opcode(0xD3, 0x0); /* Opcode D3 /0 */
9079   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9080   ins_pipe(ialu_reg_reg);
9081 %}
9082 // end of ROL expand
9083 
9084 // Rotate Left by one
9085 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9086 %{
9087   match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9088 
9089   expand %{
9090     rolL_rReg_imm1(dst, cr);
9091   %}
9092 %}
9093 
9094 // Rotate Left by 8-bit immediate
9095 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9096 %{
9097   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9098   match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9099 
9100   expand %{
9101     rolL_rReg_imm8(dst, lshift, cr);
9102   %}
9103 %}
9104 
9105 // Rotate Left by variable
9106 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9107 %{
9108   match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9109 
9110   expand %{
9111     rolL_rReg_CL(dst, shift, cr);
9112   %}
9113 %}
9114 
9115 // Rotate Left by variable
9116 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9117 %{
9118   match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9119 
9120   expand %{
9121     rolL_rReg_CL(dst, shift, cr);
9122   %}
9123 %}
9124 
9125 // ROR expand
9126 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9127 %{
9128   effect(USE_DEF dst, KILL cr);
9129 
9130   format %{ "rorq    $dst" %}
9131   opcode(0xD1, 0x1); /* D1 /1 */
9132   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9133   ins_pipe(ialu_reg);
9134 %}
9135 
9136 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9137 %{
9138   effect(USE_DEF dst, USE shift, KILL cr);
9139 
9140   format %{ "rorq    $dst, $shift" %}
9141   opcode(0xC1, 0x1); /* C1 /1 ib */
9142   ins_encode(reg_opc_imm_wide(dst, shift));
9143   ins_pipe(ialu_reg);
9144 %}
9145 
9146 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9147 %{
9148   effect(USE_DEF dst, USE shift, KILL cr);
9149 
9150   format %{ "rorq    $dst, $shift" %}
9151   opcode(0xD3, 0x1); /* D3 /1 */
9152   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9153   ins_pipe(ialu_reg_reg);
9154 %}
9155 // end of ROR expand
9156 
9157 // Rotate Right by one
9158 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9159 %{
9160   match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9161 
9162   expand %{
9163     rorL_rReg_imm1(dst, cr);
9164   %}
9165 %}
9166 
9167 // Rotate Right by 8-bit immediate
9168 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9169 %{
9170   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9171   match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9172 
9173   expand %{
9174     rorL_rReg_imm8(dst, rshift, cr);
9175   %}
9176 %}
9177 
9178 // Rotate Right by variable
9179 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9180 %{
9181   match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9182 
9183   expand %{
9184     rorL_rReg_CL(dst, shift, cr);
9185   %}
9186 %}
9187 
9188 // Rotate Right by variable
9189 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9190 %{
9191   match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9192 
9193   expand %{
9194     rorL_rReg_CL(dst, shift, cr);
9195   %}
9196 %}
9197 
9198 // Logical Instructions
9199 
9200 // Integer Logical Instructions
9201 
9202 // And Instructions
9203 // And Register with Register
9204 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9205 %{
9206   match(Set dst (AndI dst src));
9207   effect(KILL cr);
9208 
9209   format %{ "andl    $dst, $src\t# int" %}
9210   opcode(0x23);
9211   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9212   ins_pipe(ialu_reg_reg);
9213 %}
9214 
9215 // And Register with Immediate 255
9216 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9217 %{
9218   match(Set dst (AndI dst src));
9219 
9220   format %{ "movzbl  $dst, $dst\t# int & 0xFF" %}
9221   opcode(0x0F, 0xB6);
9222   ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9223   ins_pipe(ialu_reg);
9224 %}
9225 
9226 // And Register with Immediate 255 and promote to long
9227 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9228 %{
9229   match(Set dst (ConvI2L (AndI src mask)));
9230 
9231   format %{ "movzbl  $dst, $src\t# int & 0xFF -> long" %}
9232   opcode(0x0F, 0xB6);
9233   ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9234   ins_pipe(ialu_reg);
9235 %}
9236 
9237 // And Register with Immediate 65535
9238 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9239 %{
9240   match(Set dst (AndI dst src));
9241 
9242   format %{ "movzwl  $dst, $dst\t# int & 0xFFFF" %}
9243   opcode(0x0F, 0xB7);
9244   ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9245   ins_pipe(ialu_reg);
9246 %}
9247 
9248 // And Register with Immediate 65535 and promote to long
9249 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9250 %{
9251   match(Set dst (ConvI2L (AndI src mask)));
9252 
9253   format %{ "movzwl  $dst, $src\t# int & 0xFFFF -> long" %}
9254   opcode(0x0F, 0xB7);
9255   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9256   ins_pipe(ialu_reg);
9257 %}
9258 
9259 // And Register with Immediate
9260 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9261 %{
9262   match(Set dst (AndI dst src));
9263   effect(KILL cr);
9264 
9265   format %{ "andl    $dst, $src\t# int" %}
9266   opcode(0x81, 0x04); /* Opcode 81 /4 */
9267   ins_encode(OpcSErm(dst, src), Con8or32(src));
9268   ins_pipe(ialu_reg);
9269 %}
9270 
9271 // And Register with Memory
9272 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9273 %{
9274   match(Set dst (AndI dst (LoadI src)));
9275   effect(KILL cr);
9276 
9277   ins_cost(125);
9278   format %{ "andl    $dst, $src\t# int" %}
9279   opcode(0x23);
9280   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9281   ins_pipe(ialu_reg_mem);
9282 %}
9283 
9284 // And Memory with Register
9285 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9286 %{
9287   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9288   effect(KILL cr);
9289 
9290   ins_cost(150);
9291   format %{ "andl    $dst, $src\t# int" %}
9292   opcode(0x21); /* Opcode 21 /r */
9293   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9294   ins_pipe(ialu_mem_reg);
9295 %}
9296 
9297 // And Memory with Immediate
9298 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9299 %{
9300   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9301   effect(KILL cr);
9302 
9303   ins_cost(125);
9304   format %{ "andl    $dst, $src\t# int" %}
9305   opcode(0x81, 0x4); /* Opcode 81 /4 id */
9306   ins_encode(REX_mem(dst), OpcSE(src),
9307              RM_opc_mem(secondary, dst), Con8or32(src));
9308   ins_pipe(ialu_mem_imm);
9309 %}
9310 
9311 // BMI1 instructions
9312 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9313   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9314   predicate(UseBMI1Instructions);
9315   effect(KILL cr);
9316 
9317   ins_cost(125);
9318   format %{ "andnl  $dst, $src1, $src2" %}
9319 
9320   ins_encode %{
9321     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9322   %}
9323   ins_pipe(ialu_reg_mem);
9324 %}
9325 
9326 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9327   match(Set dst (AndI (XorI src1 minus_1) src2));
9328   predicate(UseBMI1Instructions);
9329   effect(KILL cr);
9330 
9331   format %{ "andnl  $dst, $src1, $src2" %}
9332 
9333   ins_encode %{
9334     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9335   %}
9336   ins_pipe(ialu_reg);
9337 %}
9338 
9339 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9340   match(Set dst (AndI (SubI imm_zero src) src));
9341   predicate(UseBMI1Instructions);
9342   effect(KILL cr);
9343 
9344   format %{ "blsil  $dst, $src" %}
9345 
9346   ins_encode %{
9347     __ blsil($dst$$Register, $src$$Register);
9348   %}
9349   ins_pipe(ialu_reg);
9350 %}
9351 
9352 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9353   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9354   predicate(UseBMI1Instructions);
9355   effect(KILL cr);
9356 
9357   ins_cost(125);
9358   format %{ "blsil  $dst, $src" %}
9359 
9360   ins_encode %{
9361     __ blsil($dst$$Register, $src$$Address);
9362   %}
9363   ins_pipe(ialu_reg_mem);
9364 %}
9365 
9366 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9367 %{
9368   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9369   predicate(UseBMI1Instructions);
9370   effect(KILL cr);
9371 
9372   ins_cost(125);
9373   format %{ "blsmskl $dst, $src" %}
9374 
9375   ins_encode %{
9376     __ blsmskl($dst$$Register, $src$$Address);
9377   %}
9378   ins_pipe(ialu_reg_mem);
9379 %}
9380 
9381 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9382 %{
9383   match(Set dst (XorI (AddI src minus_1) src));
9384   predicate(UseBMI1Instructions);
9385   effect(KILL cr);
9386 
9387   format %{ "blsmskl $dst, $src" %}
9388 
9389   ins_encode %{
9390     __ blsmskl($dst$$Register, $src$$Register);
9391   %}
9392 
9393   ins_pipe(ialu_reg);
9394 %}
9395 
9396 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9397 %{
9398   match(Set dst (AndI (AddI src minus_1) src) );
9399   predicate(UseBMI1Instructions);
9400   effect(KILL cr);
9401 
9402   format %{ "blsrl  $dst, $src" %}
9403 
9404   ins_encode %{
9405     __ blsrl($dst$$Register, $src$$Register);
9406   %}
9407 
9408   ins_pipe(ialu_reg_mem);
9409 %}
9410 
9411 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9412 %{
9413   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9414   predicate(UseBMI1Instructions);
9415   effect(KILL cr);
9416 
9417   ins_cost(125);
9418   format %{ "blsrl  $dst, $src" %}
9419 
9420   ins_encode %{
9421     __ blsrl($dst$$Register, $src$$Address);
9422   %}
9423 
9424   ins_pipe(ialu_reg);
9425 %}
9426 
9427 // Or Instructions
9428 // Or Register with Register
9429 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9430 %{
9431   match(Set dst (OrI dst src));
9432   effect(KILL cr);
9433 
9434   format %{ "orl     $dst, $src\t# int" %}
9435   opcode(0x0B);
9436   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9437   ins_pipe(ialu_reg_reg);
9438 %}
9439 
9440 // Or Register with Immediate
9441 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9442 %{
9443   match(Set dst (OrI dst src));
9444   effect(KILL cr);
9445 
9446   format %{ "orl     $dst, $src\t# int" %}
9447   opcode(0x81, 0x01); /* Opcode 81 /1 id */
9448   ins_encode(OpcSErm(dst, src), Con8or32(src));
9449   ins_pipe(ialu_reg);
9450 %}
9451 
9452 // Or Register with Memory
9453 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9454 %{
9455   match(Set dst (OrI dst (LoadI src)));
9456   effect(KILL cr);
9457 
9458   ins_cost(125);
9459   format %{ "orl     $dst, $src\t# int" %}
9460   opcode(0x0B);
9461   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9462   ins_pipe(ialu_reg_mem);
9463 %}
9464 
9465 // Or Memory with Register
9466 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9467 %{
9468   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9469   effect(KILL cr);
9470 
9471   ins_cost(150);
9472   format %{ "orl     $dst, $src\t# int" %}
9473   opcode(0x09); /* Opcode 09 /r */
9474   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9475   ins_pipe(ialu_mem_reg);
9476 %}
9477 
9478 // Or Memory with Immediate
9479 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9480 %{
9481   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9482   effect(KILL cr);
9483 
9484   ins_cost(125);
9485   format %{ "orl     $dst, $src\t# int" %}
9486   opcode(0x81, 0x1); /* Opcode 81 /1 id */
9487   ins_encode(REX_mem(dst), OpcSE(src),
9488              RM_opc_mem(secondary, dst), Con8or32(src));
9489   ins_pipe(ialu_mem_imm);
9490 %}
9491 
9492 // Xor Instructions
9493 // Xor Register with Register
9494 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9495 %{
9496   match(Set dst (XorI dst src));
9497   effect(KILL cr);
9498 
9499   format %{ "xorl    $dst, $src\t# int" %}
9500   opcode(0x33);
9501   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9502   ins_pipe(ialu_reg_reg);
9503 %}
9504 
9505 // Xor Register with Immediate -1
9506 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9507   match(Set dst (XorI dst imm));
9508 
9509   format %{ "not    $dst" %}
9510   ins_encode %{
9511      __ notl($dst$$Register);
9512   %}
9513   ins_pipe(ialu_reg);
9514 %}
9515 
9516 // Xor Register with Immediate
9517 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9518 %{
9519   match(Set dst (XorI dst src));
9520   effect(KILL cr);
9521 
9522   format %{ "xorl    $dst, $src\t# int" %}
9523   opcode(0x81, 0x06); /* Opcode 81 /6 id */
9524   ins_encode(OpcSErm(dst, src), Con8or32(src));
9525   ins_pipe(ialu_reg);
9526 %}
9527 
9528 // Xor Register with Memory
9529 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9530 %{
9531   match(Set dst (XorI dst (LoadI src)));
9532   effect(KILL cr);
9533 
9534   ins_cost(125);
9535   format %{ "xorl    $dst, $src\t# int" %}
9536   opcode(0x33);
9537   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9538   ins_pipe(ialu_reg_mem);
9539 %}
9540 
9541 // Xor Memory with Register
9542 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9543 %{
9544   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9545   effect(KILL cr);
9546 
9547   ins_cost(150);
9548   format %{ "xorl    $dst, $src\t# int" %}
9549   opcode(0x31); /* Opcode 31 /r */
9550   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9551   ins_pipe(ialu_mem_reg);
9552 %}
9553 
9554 // Xor Memory with Immediate
9555 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9556 %{
9557   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9558   effect(KILL cr);
9559 
9560   ins_cost(125);
9561   format %{ "xorl    $dst, $src\t# int" %}
9562   opcode(0x81, 0x6); /* Opcode 81 /6 id */
9563   ins_encode(REX_mem(dst), OpcSE(src),
9564              RM_opc_mem(secondary, dst), Con8or32(src));
9565   ins_pipe(ialu_mem_imm);
9566 %}
9567 
9568 
9569 // Long Logical Instructions
9570 
9571 // And Instructions
9572 // And Register with Register
9573 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9574 %{
9575   match(Set dst (AndL dst src));
9576   effect(KILL cr);
9577 
9578   format %{ "andq    $dst, $src\t# long" %}
9579   opcode(0x23);
9580   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9581   ins_pipe(ialu_reg_reg);
9582 %}
9583 
9584 // And Register with Immediate 255
9585 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9586 %{
9587   match(Set dst (AndL dst src));
9588 
9589   format %{ "movzbq  $dst, $dst\t# long & 0xFF" %}
9590   opcode(0x0F, 0xB6);
9591   ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9592   ins_pipe(ialu_reg);
9593 %}
9594 
9595 // And Register with Immediate 65535
9596 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9597 %{
9598   match(Set dst (AndL dst src));
9599 
9600   format %{ "movzwq  $dst, $dst\t# long & 0xFFFF" %}
9601   opcode(0x0F, 0xB7);
9602   ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9603   ins_pipe(ialu_reg);
9604 %}
9605 
9606 // And Register with Immediate
9607 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9608 %{
9609   match(Set dst (AndL dst src));
9610   effect(KILL cr);
9611 
9612   format %{ "andq    $dst, $src\t# long" %}
9613   opcode(0x81, 0x04); /* Opcode 81 /4 */
9614   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9615   ins_pipe(ialu_reg);
9616 %}
9617 
9618 // And Register with Memory
9619 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9620 %{
9621   match(Set dst (AndL dst (LoadL src)));
9622   effect(KILL cr);
9623 
9624   ins_cost(125);
9625   format %{ "andq    $dst, $src\t# long" %}
9626   opcode(0x23);
9627   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9628   ins_pipe(ialu_reg_mem);
9629 %}
9630 
9631 // And Memory with Register
9632 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9633 %{
9634   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9635   effect(KILL cr);
9636 
9637   ins_cost(150);
9638   format %{ "andq    $dst, $src\t# long" %}
9639   opcode(0x21); /* Opcode 21 /r */
9640   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9641   ins_pipe(ialu_mem_reg);
9642 %}
9643 
9644 // And Memory with Immediate
9645 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9646 %{
9647   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9648   effect(KILL cr);
9649 
9650   ins_cost(125);
9651   format %{ "andq    $dst, $src\t# long" %}
9652   opcode(0x81, 0x4); /* Opcode 81 /4 id */
9653   ins_encode(REX_mem_wide(dst), OpcSE(src),
9654              RM_opc_mem(secondary, dst), Con8or32(src));
9655   ins_pipe(ialu_mem_imm);
9656 %}
9657 
9658 // BMI1 instructions
9659 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9660   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9661   predicate(UseBMI1Instructions);
9662   effect(KILL cr);
9663 
9664   ins_cost(125);
9665   format %{ "andnq  $dst, $src1, $src2" %}
9666 
9667   ins_encode %{
9668     __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9669   %}
9670   ins_pipe(ialu_reg_mem);
9671 %}
9672 
9673 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9674   match(Set dst (AndL (XorL src1 minus_1) src2));
9675   predicate(UseBMI1Instructions);
9676   effect(KILL cr);
9677 
9678   format %{ "andnq  $dst, $src1, $src2" %}
9679 
9680   ins_encode %{
9681   __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9682   %}
9683   ins_pipe(ialu_reg_mem);
9684 %}
9685 
9686 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9687   match(Set dst (AndL (SubL imm_zero src) src));
9688   predicate(UseBMI1Instructions);
9689   effect(KILL cr);
9690 
9691   format %{ "blsiq  $dst, $src" %}
9692 
9693   ins_encode %{
9694     __ blsiq($dst$$Register, $src$$Register);
9695   %}
9696   ins_pipe(ialu_reg);
9697 %}
9698 
9699 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9700   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9701   predicate(UseBMI1Instructions);
9702   effect(KILL cr);
9703 
9704   ins_cost(125);
9705   format %{ "blsiq  $dst, $src" %}
9706 
9707   ins_encode %{
9708     __ blsiq($dst$$Register, $src$$Address);
9709   %}
9710   ins_pipe(ialu_reg_mem);
9711 %}
9712 
9713 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9714 %{
9715   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9716   predicate(UseBMI1Instructions);
9717   effect(KILL cr);
9718 
9719   ins_cost(125);
9720   format %{ "blsmskq $dst, $src" %}
9721 
9722   ins_encode %{
9723     __ blsmskq($dst$$Register, $src$$Address);
9724   %}
9725   ins_pipe(ialu_reg_mem);
9726 %}
9727 
9728 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9729 %{
9730   match(Set dst (XorL (AddL src minus_1) src));
9731   predicate(UseBMI1Instructions);
9732   effect(KILL cr);
9733 
9734   format %{ "blsmskq $dst, $src" %}
9735 
9736   ins_encode %{
9737     __ blsmskq($dst$$Register, $src$$Register);
9738   %}
9739 
9740   ins_pipe(ialu_reg);
9741 %}
9742 
9743 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9744 %{
9745   match(Set dst (AndL (AddL src minus_1) src) );
9746   predicate(UseBMI1Instructions);
9747   effect(KILL cr);
9748 
9749   format %{ "blsrq  $dst, $src" %}
9750 
9751   ins_encode %{
9752     __ blsrq($dst$$Register, $src$$Register);
9753   %}
9754 
9755   ins_pipe(ialu_reg);
9756 %}
9757 
9758 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9759 %{
9760   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9761   predicate(UseBMI1Instructions);
9762   effect(KILL cr);
9763 
9764   ins_cost(125);
9765   format %{ "blsrq  $dst, $src" %}
9766 
9767   ins_encode %{
9768     __ blsrq($dst$$Register, $src$$Address);
9769   %}
9770 
9771   ins_pipe(ialu_reg);
9772 %}
9773 
9774 // Or Instructions
9775 // Or Register with Register
9776 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9777 %{
9778   match(Set dst (OrL dst src));
9779   effect(KILL cr);
9780 
9781   format %{ "orq     $dst, $src\t# long" %}
9782   opcode(0x0B);
9783   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9784   ins_pipe(ialu_reg_reg);
9785 %}
9786 
9787 // Use any_RegP to match R15 (TLS register) without spilling.
9788 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9789   match(Set dst (OrL dst (CastP2X src)));
9790   effect(KILL cr);
9791 
9792   format %{ "orq     $dst, $src\t# long" %}
9793   opcode(0x0B);
9794   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9795   ins_pipe(ialu_reg_reg);
9796 %}
9797 
9798 
9799 // Or Register with Immediate
9800 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9801 %{
9802   match(Set dst (OrL dst src));
9803   effect(KILL cr);
9804 
9805   format %{ "orq     $dst, $src\t# long" %}
9806   opcode(0x81, 0x01); /* Opcode 81 /1 id */
9807   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9808   ins_pipe(ialu_reg);
9809 %}
9810 
9811 // Or Register with Memory
9812 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9813 %{
9814   match(Set dst (OrL dst (LoadL src)));
9815   effect(KILL cr);
9816 
9817   ins_cost(125);
9818   format %{ "orq     $dst, $src\t# long" %}
9819   opcode(0x0B);
9820   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9821   ins_pipe(ialu_reg_mem);
9822 %}
9823 
9824 // Or Memory with Register
9825 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9826 %{
9827   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9828   effect(KILL cr);
9829 
9830   ins_cost(150);
9831   format %{ "orq     $dst, $src\t# long" %}
9832   opcode(0x09); /* Opcode 09 /r */
9833   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9834   ins_pipe(ialu_mem_reg);
9835 %}
9836 
9837 // Or Memory with Immediate
9838 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9839 %{
9840   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9841   effect(KILL cr);
9842 
9843   ins_cost(125);
9844   format %{ "orq     $dst, $src\t# long" %}
9845   opcode(0x81, 0x1); /* Opcode 81 /1 id */
9846   ins_encode(REX_mem_wide(dst), OpcSE(src),
9847              RM_opc_mem(secondary, dst), Con8or32(src));
9848   ins_pipe(ialu_mem_imm);
9849 %}
9850 
9851 // Xor Instructions
9852 // Xor Register with Register
9853 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9854 %{
9855   match(Set dst (XorL dst src));
9856   effect(KILL cr);
9857 
9858   format %{ "xorq    $dst, $src\t# long" %}
9859   opcode(0x33);
9860   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9861   ins_pipe(ialu_reg_reg);
9862 %}
9863 
9864 // Xor Register with Immediate -1
9865 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9866   match(Set dst (XorL dst imm));
9867 
9868   format %{ "notq   $dst" %}
9869   ins_encode %{
9870      __ notq($dst$$Register);
9871   %}
9872   ins_pipe(ialu_reg);
9873 %}
9874 
9875 // Xor Register with Immediate
9876 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9877 %{
9878   match(Set dst (XorL dst src));
9879   effect(KILL cr);
9880 
9881   format %{ "xorq    $dst, $src\t# long" %}
9882   opcode(0x81, 0x06); /* Opcode 81 /6 id */
9883   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9884   ins_pipe(ialu_reg);
9885 %}
9886 
9887 // Xor Register with Memory
9888 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9889 %{
9890   match(Set dst (XorL dst (LoadL src)));
9891   effect(KILL cr);
9892 
9893   ins_cost(125);
9894   format %{ "xorq    $dst, $src\t# long" %}
9895   opcode(0x33);
9896   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9897   ins_pipe(ialu_reg_mem);
9898 %}
9899 
9900 // Xor Memory with Register
9901 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9902 %{
9903   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9904   effect(KILL cr);
9905 
9906   ins_cost(150);
9907   format %{ "xorq    $dst, $src\t# long" %}
9908   opcode(0x31); /* Opcode 31 /r */
9909   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9910   ins_pipe(ialu_mem_reg);
9911 %}
9912 
9913 // Xor Memory with Immediate
9914 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9915 %{
9916   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9917   effect(KILL cr);
9918 
9919   ins_cost(125);
9920   format %{ "xorq    $dst, $src\t# long" %}
9921   opcode(0x81, 0x6); /* Opcode 81 /6 id */
9922   ins_encode(REX_mem_wide(dst), OpcSE(src),
9923              RM_opc_mem(secondary, dst), Con8or32(src));
9924   ins_pipe(ialu_mem_imm);
9925 %}
9926 
9927 // Convert Int to Boolean
9928 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9929 %{
9930   match(Set dst (Conv2B src));
9931   effect(KILL cr);
9932 
9933   format %{ "testl   $src, $src\t# ci2b\n\t"
9934             "setnz   $dst\n\t"
9935             "movzbl  $dst, $dst" %}
9936   ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9937              setNZ_reg(dst),
9938              REX_reg_breg(dst, dst), // movzbl
9939              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9940   ins_pipe(pipe_slow); // XXX
9941 %}
9942 
9943 // Convert Pointer to Boolean
9944 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9945 %{
9946   match(Set dst (Conv2B src));
9947   effect(KILL cr);
9948 
9949   format %{ "testq   $src, $src\t# cp2b\n\t"
9950             "setnz   $dst\n\t"
9951             "movzbl  $dst, $dst" %}
9952   ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9953              setNZ_reg(dst),
9954              REX_reg_breg(dst, dst), // movzbl
9955              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9956   ins_pipe(pipe_slow); // XXX
9957 %}
9958 
9959 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9960 %{
9961   match(Set dst (CmpLTMask p q));
9962   effect(KILL cr);
9963 
9964   ins_cost(400);
9965   format %{ "cmpl    $p, $q\t# cmpLTMask\n\t"
9966             "setlt   $dst\n\t"
9967             "movzbl  $dst, $dst\n\t"
9968             "negl    $dst" %}
9969   ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9970              setLT_reg(dst),
9971              REX_reg_breg(dst, dst), // movzbl
9972              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9973              neg_reg(dst));
9974   ins_pipe(pipe_slow);
9975 %}
9976 
9977 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9978 %{
9979   match(Set dst (CmpLTMask dst zero));
9980   effect(KILL cr);
9981 
9982   ins_cost(100);
9983   format %{ "sarl    $dst, #31\t# cmpLTMask0" %}
9984   ins_encode %{
9985   __ sarl($dst$$Register, 31);
9986   %}
9987   ins_pipe(ialu_reg);
9988 %}
9989 
9990 /* Better to save a register than avoid a branch */
9991 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9992 %{
9993   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9994   effect(KILL cr);
9995   ins_cost(300);
9996   format %{ "subl   $p,$q\t# cadd_cmpLTMask\n\t"
9997             "jge    done\n\t"
9998             "addl   $p,$y\n"
9999             "done:  " %}
10000   ins_encode %{
10001     Register Rp = $p$$Register;
10002     Register Rq = $q$$Register;
10003     Register Ry = $y$$Register;
10004     Label done;
10005     __ subl(Rp, Rq);
10006     __ jccb(Assembler::greaterEqual, done);
10007     __ addl(Rp, Ry);
10008     __ bind(done);
10009   %}
10010   ins_pipe(pipe_cmplt);
10011 %}
10012 
10013 /* Better to save a register than avoid a branch */
10014 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10015 %{
10016   match(Set y (AndI (CmpLTMask p q) y));
10017   effect(KILL cr);
10018 
10019   ins_cost(300);
10020 
10021   format %{ "cmpl     $p, $q\t# and_cmpLTMask\n\t"
10022             "jlt      done\n\t"
10023             "xorl     $y, $y\n"
10024             "done:  " %}
10025   ins_encode %{
10026     Register Rp = $p$$Register;
10027     Register Rq = $q$$Register;
10028     Register Ry = $y$$Register;
10029     Label done;
10030     __ cmpl(Rp, Rq);
10031     __ jccb(Assembler::less, done);
10032     __ xorl(Ry, Ry);
10033     __ bind(done);
10034   %}
10035   ins_pipe(pipe_cmplt);
10036 %}
10037 
10038 
10039 //---------- FP Instructions------------------------------------------------
10040 
10041 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10042 %{
10043   match(Set cr (CmpF src1 src2));
10044 
10045   ins_cost(145);
10046   format %{ "ucomiss $src1, $src2\n\t"
10047             "jnp,s   exit\n\t"
10048             "pushfq\t# saw NaN, set CF\n\t"
10049             "andq    [rsp], #0xffffff2b\n\t"
10050             "popfq\n"
10051     "exit:" %}
10052   ins_encode %{
10053     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10054     emit_cmpfp_fixup(_masm);
10055   %}
10056   ins_pipe(pipe_slow);
10057 %}
10058 
10059 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10060   match(Set cr (CmpF src1 src2));
10061 
10062   ins_cost(100);
10063   format %{ "ucomiss $src1, $src2" %}
10064   ins_encode %{
10065     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10066   %}
10067   ins_pipe(pipe_slow);
10068 %}
10069 
10070 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10071 %{
10072   match(Set cr (CmpF src1 (LoadF src2)));
10073 
10074   ins_cost(145);
10075   format %{ "ucomiss $src1, $src2\n\t"
10076             "jnp,s   exit\n\t"
10077             "pushfq\t# saw NaN, set CF\n\t"
10078             "andq    [rsp], #0xffffff2b\n\t"
10079             "popfq\n"
10080     "exit:" %}
10081   ins_encode %{
10082     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10083     emit_cmpfp_fixup(_masm);
10084   %}
10085   ins_pipe(pipe_slow);
10086 %}
10087 
10088 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10089   match(Set cr (CmpF src1 (LoadF src2)));
10090 
10091   ins_cost(100);
10092   format %{ "ucomiss $src1, $src2" %}
10093   ins_encode %{
10094     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10095   %}
10096   ins_pipe(pipe_slow);
10097 %}
10098 
10099 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10100   match(Set cr (CmpF src con));
10101 
10102   ins_cost(145);
10103   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10104             "jnp,s   exit\n\t"
10105             "pushfq\t# saw NaN, set CF\n\t"
10106             "andq    [rsp], #0xffffff2b\n\t"
10107             "popfq\n"
10108     "exit:" %}
10109   ins_encode %{
10110     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10111     emit_cmpfp_fixup(_masm);
10112   %}
10113   ins_pipe(pipe_slow);
10114 %}
10115 
10116 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10117   match(Set cr (CmpF src con));
10118   ins_cost(100);
10119   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10120   ins_encode %{
10121     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10122   %}
10123   ins_pipe(pipe_slow);
10124 %}
10125 
10126 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10127 %{
10128   match(Set cr (CmpD src1 src2));
10129 
10130   ins_cost(145);
10131   format %{ "ucomisd $src1, $src2\n\t"
10132             "jnp,s   exit\n\t"
10133             "pushfq\t# saw NaN, set CF\n\t"
10134             "andq    [rsp], #0xffffff2b\n\t"
10135             "popfq\n"
10136     "exit:" %}
10137   ins_encode %{
10138     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10139     emit_cmpfp_fixup(_masm);
10140   %}
10141   ins_pipe(pipe_slow);
10142 %}
10143 
10144 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10145   match(Set cr (CmpD src1 src2));
10146 
10147   ins_cost(100);
10148   format %{ "ucomisd $src1, $src2 test" %}
10149   ins_encode %{
10150     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10151   %}
10152   ins_pipe(pipe_slow);
10153 %}
10154 
10155 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10156 %{
10157   match(Set cr (CmpD src1 (LoadD src2)));
10158 
10159   ins_cost(145);
10160   format %{ "ucomisd $src1, $src2\n\t"
10161             "jnp,s   exit\n\t"
10162             "pushfq\t# saw NaN, set CF\n\t"
10163             "andq    [rsp], #0xffffff2b\n\t"
10164             "popfq\n"
10165     "exit:" %}
10166   ins_encode %{
10167     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10168     emit_cmpfp_fixup(_masm);
10169   %}
10170   ins_pipe(pipe_slow);
10171 %}
10172 
10173 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10174   match(Set cr (CmpD src1 (LoadD src2)));
10175 
10176   ins_cost(100);
10177   format %{ "ucomisd $src1, $src2" %}
10178   ins_encode %{
10179     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10180   %}
10181   ins_pipe(pipe_slow);
10182 %}
10183 
10184 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10185   match(Set cr (CmpD src con));
10186 
10187   ins_cost(145);
10188   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10189             "jnp,s   exit\n\t"
10190             "pushfq\t# saw NaN, set CF\n\t"
10191             "andq    [rsp], #0xffffff2b\n\t"
10192             "popfq\n"
10193     "exit:" %}
10194   ins_encode %{
10195     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10196     emit_cmpfp_fixup(_masm);
10197   %}
10198   ins_pipe(pipe_slow);
10199 %}
10200 
10201 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10202   match(Set cr (CmpD src con));
10203   ins_cost(100);
10204   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10205   ins_encode %{
10206     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10207   %}
10208   ins_pipe(pipe_slow);
10209 %}
10210 
10211 // Compare into -1,0,1
10212 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10213 %{
10214   match(Set dst (CmpF3 src1 src2));
10215   effect(KILL cr);
10216 
10217   ins_cost(275);
10218   format %{ "ucomiss $src1, $src2\n\t"
10219             "movl    $dst, #-1\n\t"
10220             "jp,s    done\n\t"
10221             "jb,s    done\n\t"
10222             "setne   $dst\n\t"
10223             "movzbl  $dst, $dst\n"
10224     "done:" %}
10225   ins_encode %{
10226     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10227     emit_cmpfp3(_masm, $dst$$Register);
10228   %}
10229   ins_pipe(pipe_slow);
10230 %}
10231 
10232 // Compare into -1,0,1
10233 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10234 %{
10235   match(Set dst (CmpF3 src1 (LoadF src2)));
10236   effect(KILL cr);
10237 
10238   ins_cost(275);
10239   format %{ "ucomiss $src1, $src2\n\t"
10240             "movl    $dst, #-1\n\t"
10241             "jp,s    done\n\t"
10242             "jb,s    done\n\t"
10243             "setne   $dst\n\t"
10244             "movzbl  $dst, $dst\n"
10245     "done:" %}
10246   ins_encode %{
10247     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10248     emit_cmpfp3(_masm, $dst$$Register);
10249   %}
10250   ins_pipe(pipe_slow);
10251 %}
10252 
10253 // Compare into -1,0,1
10254 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10255   match(Set dst (CmpF3 src con));
10256   effect(KILL cr);
10257 
10258   ins_cost(275);
10259   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10260             "movl    $dst, #-1\n\t"
10261             "jp,s    done\n\t"
10262             "jb,s    done\n\t"
10263             "setne   $dst\n\t"
10264             "movzbl  $dst, $dst\n"
10265     "done:" %}
10266   ins_encode %{
10267     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10268     emit_cmpfp3(_masm, $dst$$Register);
10269   %}
10270   ins_pipe(pipe_slow);
10271 %}
10272 
10273 // Compare into -1,0,1
10274 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10275 %{
10276   match(Set dst (CmpD3 src1 src2));
10277   effect(KILL cr);
10278 
10279   ins_cost(275);
10280   format %{ "ucomisd $src1, $src2\n\t"
10281             "movl    $dst, #-1\n\t"
10282             "jp,s    done\n\t"
10283             "jb,s    done\n\t"
10284             "setne   $dst\n\t"
10285             "movzbl  $dst, $dst\n"
10286     "done:" %}
10287   ins_encode %{
10288     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10289     emit_cmpfp3(_masm, $dst$$Register);
10290   %}
10291   ins_pipe(pipe_slow);
10292 %}
10293 
10294 // Compare into -1,0,1
10295 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10296 %{
10297   match(Set dst (CmpD3 src1 (LoadD src2)));
10298   effect(KILL cr);
10299 
10300   ins_cost(275);
10301   format %{ "ucomisd $src1, $src2\n\t"
10302             "movl    $dst, #-1\n\t"
10303             "jp,s    done\n\t"
10304             "jb,s    done\n\t"
10305             "setne   $dst\n\t"
10306             "movzbl  $dst, $dst\n"
10307     "done:" %}
10308   ins_encode %{
10309     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10310     emit_cmpfp3(_masm, $dst$$Register);
10311   %}
10312   ins_pipe(pipe_slow);
10313 %}
10314 
10315 // Compare into -1,0,1
10316 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10317   match(Set dst (CmpD3 src con));
10318   effect(KILL cr);
10319 
10320   ins_cost(275);
10321   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10322             "movl    $dst, #-1\n\t"
10323             "jp,s    done\n\t"
10324             "jb,s    done\n\t"
10325             "setne   $dst\n\t"
10326             "movzbl  $dst, $dst\n"
10327     "done:" %}
10328   ins_encode %{
10329     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10330     emit_cmpfp3(_masm, $dst$$Register);
10331   %}
10332   ins_pipe(pipe_slow);
10333 %}
10334 
10335 //----------Arithmetic Conversion Instructions---------------------------------
10336 
10337 instruct roundFloat_nop(regF dst)
10338 %{
10339   match(Set dst (RoundFloat dst));
10340 
10341   ins_cost(0);
10342   ins_encode();
10343   ins_pipe(empty);
10344 %}
10345 
10346 instruct roundDouble_nop(regD dst)
10347 %{
10348   match(Set dst (RoundDouble dst));
10349 
10350   ins_cost(0);
10351   ins_encode();
10352   ins_pipe(empty);
10353 %}
10354 
10355 instruct convF2D_reg_reg(regD dst, regF src)
10356 %{
10357   match(Set dst (ConvF2D src));
10358 
10359   format %{ "cvtss2sd $dst, $src" %}
10360   ins_encode %{
10361     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10362   %}
10363   ins_pipe(pipe_slow); // XXX
10364 %}
10365 
10366 instruct convF2D_reg_mem(regD dst, memory src)
10367 %{
10368   match(Set dst (ConvF2D (LoadF src)));
10369 
10370   format %{ "cvtss2sd $dst, $src" %}
10371   ins_encode %{
10372     __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10373   %}
10374   ins_pipe(pipe_slow); // XXX
10375 %}
10376 
10377 instruct convD2F_reg_reg(regF dst, regD src)
10378 %{
10379   match(Set dst (ConvD2F src));
10380 
10381   format %{ "cvtsd2ss $dst, $src" %}
10382   ins_encode %{
10383     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10384   %}
10385   ins_pipe(pipe_slow); // XXX
10386 %}
10387 
10388 instruct convD2F_reg_mem(regF dst, memory src)
10389 %{
10390   match(Set dst (ConvD2F (LoadD src)));
10391 
10392   format %{ "cvtsd2ss $dst, $src" %}
10393   ins_encode %{
10394     __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10395   %}
10396   ins_pipe(pipe_slow); // XXX
10397 %}
10398 
10399 // XXX do mem variants
10400 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10401 %{
10402   match(Set dst (ConvF2I src));
10403   effect(KILL cr);
10404 
10405   format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10406             "cmpl    $dst, #0x80000000\n\t"
10407             "jne,s   done\n\t"
10408             "subq    rsp, #8\n\t"
10409             "movss   [rsp], $src\n\t"
10410             "call    f2i_fixup\n\t"
10411             "popq    $dst\n"
10412     "done:   "%}
10413   ins_encode %{
10414     Label done;
10415     __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10416     __ cmpl($dst$$Register, 0x80000000);
10417     __ jccb(Assembler::notEqual, done);
10418     __ subptr(rsp, 8);
10419     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10420     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10421     __ pop($dst$$Register);
10422     __ bind(done);
10423   %}
10424   ins_pipe(pipe_slow);
10425 %}
10426 
10427 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10428 %{
10429   match(Set dst (ConvF2L src));
10430   effect(KILL cr);
10431 
10432   format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10433             "cmpq    $dst, [0x8000000000000000]\n\t"
10434             "jne,s   done\n\t"
10435             "subq    rsp, #8\n\t"
10436             "movss   [rsp], $src\n\t"
10437             "call    f2l_fixup\n\t"
10438             "popq    $dst\n"
10439     "done:   "%}
10440   ins_encode %{
10441     Label done;
10442     __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10443     __ cmp64($dst$$Register,
10444              ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10445     __ jccb(Assembler::notEqual, done);
10446     __ subptr(rsp, 8);
10447     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10448     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10449     __ pop($dst$$Register);
10450     __ bind(done);
10451   %}
10452   ins_pipe(pipe_slow);
10453 %}
10454 
10455 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10456 %{
10457   match(Set dst (ConvD2I src));
10458   effect(KILL cr);
10459 
10460   format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10461             "cmpl    $dst, #0x80000000\n\t"
10462             "jne,s   done\n\t"
10463             "subq    rsp, #8\n\t"
10464             "movsd   [rsp], $src\n\t"
10465             "call    d2i_fixup\n\t"
10466             "popq    $dst\n"
10467     "done:   "%}
10468   ins_encode %{
10469     Label done;
10470     __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10471     __ cmpl($dst$$Register, 0x80000000);
10472     __ jccb(Assembler::notEqual, done);
10473     __ subptr(rsp, 8);
10474     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10475     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10476     __ pop($dst$$Register);
10477     __ bind(done);
10478   %}
10479   ins_pipe(pipe_slow);
10480 %}
10481 
10482 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10483 %{
10484   match(Set dst (ConvD2L src));
10485   effect(KILL cr);
10486 
10487   format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10488             "cmpq    $dst, [0x8000000000000000]\n\t"
10489             "jne,s   done\n\t"
10490             "subq    rsp, #8\n\t"
10491             "movsd   [rsp], $src\n\t"
10492             "call    d2l_fixup\n\t"
10493             "popq    $dst\n"
10494     "done:   "%}
10495   ins_encode %{
10496     Label done;
10497     __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10498     __ cmp64($dst$$Register,
10499              ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10500     __ jccb(Assembler::notEqual, done);
10501     __ subptr(rsp, 8);
10502     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10503     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10504     __ pop($dst$$Register);
10505     __ bind(done);
10506   %}
10507   ins_pipe(pipe_slow);
10508 %}
10509 
10510 instruct convI2F_reg_reg(regF dst, rRegI src)
10511 %{
10512   predicate(!UseXmmI2F);
10513   match(Set dst (ConvI2F src));
10514 
10515   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10516   ins_encode %{
10517     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10518   %}
10519   ins_pipe(pipe_slow); // XXX
10520 %}
10521 
10522 instruct convI2F_reg_mem(regF dst, memory src)
10523 %{
10524   match(Set dst (ConvI2F (LoadI src)));
10525 
10526   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10527   ins_encode %{
10528     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10529   %}
10530   ins_pipe(pipe_slow); // XXX
10531 %}
10532 
10533 instruct convI2D_reg_reg(regD dst, rRegI src)
10534 %{
10535   predicate(!UseXmmI2D);
10536   match(Set dst (ConvI2D src));
10537 
10538   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10539   ins_encode %{
10540     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10541   %}
10542   ins_pipe(pipe_slow); // XXX
10543 %}
10544 
10545 instruct convI2D_reg_mem(regD dst, memory src)
10546 %{
10547   match(Set dst (ConvI2D (LoadI src)));
10548 
10549   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10550   ins_encode %{
10551     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10552   %}
10553   ins_pipe(pipe_slow); // XXX
10554 %}
10555 
10556 instruct convXI2F_reg(regF dst, rRegI src)
10557 %{
10558   predicate(UseXmmI2F);
10559   match(Set dst (ConvI2F src));
10560 
10561   format %{ "movdl $dst, $src\n\t"
10562             "cvtdq2psl $dst, $dst\t# i2f" %}
10563   ins_encode %{
10564     __ movdl($dst$$XMMRegister, $src$$Register);
10565     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10566   %}
10567   ins_pipe(pipe_slow); // XXX
10568 %}
10569 
10570 instruct convXI2D_reg(regD dst, rRegI src)
10571 %{
10572   predicate(UseXmmI2D);
10573   match(Set dst (ConvI2D src));
10574 
10575   format %{ "movdl $dst, $src\n\t"
10576             "cvtdq2pdl $dst, $dst\t# i2d" %}
10577   ins_encode %{
10578     __ movdl($dst$$XMMRegister, $src$$Register);
10579     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10580   %}
10581   ins_pipe(pipe_slow); // XXX
10582 %}
10583 
10584 instruct convL2F_reg_reg(regF dst, rRegL src)
10585 %{
10586   match(Set dst (ConvL2F src));
10587 
10588   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10589   ins_encode %{
10590     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10591   %}
10592   ins_pipe(pipe_slow); // XXX
10593 %}
10594 
10595 instruct convL2F_reg_mem(regF dst, memory src)
10596 %{
10597   match(Set dst (ConvL2F (LoadL src)));
10598 
10599   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10600   ins_encode %{
10601     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10602   %}
10603   ins_pipe(pipe_slow); // XXX
10604 %}
10605 
10606 instruct convL2D_reg_reg(regD dst, rRegL src)
10607 %{
10608   match(Set dst (ConvL2D src));
10609 
10610   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10611   ins_encode %{
10612     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10613   %}
10614   ins_pipe(pipe_slow); // XXX
10615 %}
10616 
10617 instruct convL2D_reg_mem(regD dst, memory src)
10618 %{
10619   match(Set dst (ConvL2D (LoadL src)));
10620 
10621   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10622   ins_encode %{
10623     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10624   %}
10625   ins_pipe(pipe_slow); // XXX
10626 %}
10627 
10628 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10629 %{
10630   match(Set dst (ConvI2L src));
10631 
10632   ins_cost(125);
10633   format %{ "movslq  $dst, $src\t# i2l" %}
10634   ins_encode %{
10635     __ movslq($dst$$Register, $src$$Register);
10636   %}
10637   ins_pipe(ialu_reg_reg);
10638 %}
10639 
10640 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10641 // %{
10642 //   match(Set dst (ConvI2L src));
10643 // //   predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10644 // //             _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10645 //   predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10646 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10647 //             ((const TypeNode*) n)->type()->is_long()->_lo ==
10648 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10649 
10650 //   format %{ "movl    $dst, $src\t# unsigned i2l" %}
10651 //   ins_encode(enc_copy(dst, src));
10652 // //   opcode(0x63); // needs REX.W
10653 // //   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10654 //   ins_pipe(ialu_reg_reg);
10655 // %}
10656 
10657 // Zero-extend convert int to long
10658 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10659 %{
10660   match(Set dst (AndL (ConvI2L src) mask));
10661 
10662   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10663   ins_encode %{
10664     if ($dst$$reg != $src$$reg) {
10665       __ movl($dst$$Register, $src$$Register);
10666     }
10667   %}
10668   ins_pipe(ialu_reg_reg);
10669 %}
10670 
10671 // Zero-extend convert int to long
10672 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10673 %{
10674   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10675 
10676   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10677   ins_encode %{
10678     __ movl($dst$$Register, $src$$Address);
10679   %}
10680   ins_pipe(ialu_reg_mem);
10681 %}
10682 
10683 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10684 %{
10685   match(Set dst (AndL src mask));
10686 
10687   format %{ "movl    $dst, $src\t# zero-extend long" %}
10688   ins_encode %{
10689     __ movl($dst$$Register, $src$$Register);
10690   %}
10691   ins_pipe(ialu_reg_reg);
10692 %}
10693 
10694 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10695 %{
10696   match(Set dst (ConvL2I src));
10697 
10698   format %{ "movl    $dst, $src\t# l2i" %}
10699   ins_encode %{
10700     __ movl($dst$$Register, $src$$Register);
10701   %}
10702   ins_pipe(ialu_reg_reg);
10703 %}
10704 
10705 
10706 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10707   match(Set dst (MoveF2I src));
10708   effect(DEF dst, USE src);
10709 
10710   ins_cost(125);
10711   format %{ "movl    $dst, $src\t# MoveF2I_stack_reg" %}
10712   ins_encode %{
10713     __ movl($dst$$Register, Address(rsp, $src$$disp));
10714   %}
10715   ins_pipe(ialu_reg_mem);
10716 %}
10717 
10718 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10719   match(Set dst (MoveI2F src));
10720   effect(DEF dst, USE src);
10721 
10722   ins_cost(125);
10723   format %{ "movss   $dst, $src\t# MoveI2F_stack_reg" %}
10724   ins_encode %{
10725     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10726   %}
10727   ins_pipe(pipe_slow);
10728 %}
10729 
10730 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10731   match(Set dst (MoveD2L src));
10732   effect(DEF dst, USE src);
10733 
10734   ins_cost(125);
10735   format %{ "movq    $dst, $src\t# MoveD2L_stack_reg" %}
10736   ins_encode %{
10737     __ movq($dst$$Register, Address(rsp, $src$$disp));
10738   %}
10739   ins_pipe(ialu_reg_mem);
10740 %}
10741 
10742 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10743   predicate(!UseXmmLoadAndClearUpper);
10744   match(Set dst (MoveL2D src));
10745   effect(DEF dst, USE src);
10746 
10747   ins_cost(125);
10748   format %{ "movlpd  $dst, $src\t# MoveL2D_stack_reg" %}
10749   ins_encode %{
10750     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10751   %}
10752   ins_pipe(pipe_slow);
10753 %}
10754 
10755 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10756   predicate(UseXmmLoadAndClearUpper);
10757   match(Set dst (MoveL2D src));
10758   effect(DEF dst, USE src);
10759 
10760   ins_cost(125);
10761   format %{ "movsd   $dst, $src\t# MoveL2D_stack_reg" %}
10762   ins_encode %{
10763     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10764   %}
10765   ins_pipe(pipe_slow);
10766 %}
10767 
10768 
10769 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10770   match(Set dst (MoveF2I src));
10771   effect(DEF dst, USE src);
10772 
10773   ins_cost(95); // XXX
10774   format %{ "movss   $dst, $src\t# MoveF2I_reg_stack" %}
10775   ins_encode %{
10776     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10777   %}
10778   ins_pipe(pipe_slow);
10779 %}
10780 
10781 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10782   match(Set dst (MoveI2F src));
10783   effect(DEF dst, USE src);
10784 
10785   ins_cost(100);
10786   format %{ "movl    $dst, $src\t# MoveI2F_reg_stack" %}
10787   ins_encode %{
10788     __ movl(Address(rsp, $dst$$disp), $src$$Register);
10789   %}
10790   ins_pipe( ialu_mem_reg );
10791 %}
10792 
10793 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10794   match(Set dst (MoveD2L src));
10795   effect(DEF dst, USE src);
10796 
10797   ins_cost(95); // XXX
10798   format %{ "movsd   $dst, $src\t# MoveL2D_reg_stack" %}
10799   ins_encode %{
10800     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10801   %}
10802   ins_pipe(pipe_slow);
10803 %}
10804 
10805 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10806   match(Set dst (MoveL2D src));
10807   effect(DEF dst, USE src);
10808 
10809   ins_cost(100);
10810   format %{ "movq    $dst, $src\t# MoveL2D_reg_stack" %}
10811   ins_encode %{
10812     __ movq(Address(rsp, $dst$$disp), $src$$Register);
10813   %}
10814   ins_pipe(ialu_mem_reg);
10815 %}
10816 
10817 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10818   match(Set dst (MoveF2I src));
10819   effect(DEF dst, USE src);
10820   ins_cost(85);
10821   format %{ "movd    $dst,$src\t# MoveF2I" %}
10822   ins_encode %{
10823     __ movdl($dst$$Register, $src$$XMMRegister);
10824   %}
10825   ins_pipe( pipe_slow );
10826 %}
10827 
10828 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10829   match(Set dst (MoveD2L src));
10830   effect(DEF dst, USE src);
10831   ins_cost(85);
10832   format %{ "movd    $dst,$src\t# MoveD2L" %}
10833   ins_encode %{
10834     __ movdq($dst$$Register, $src$$XMMRegister);
10835   %}
10836   ins_pipe( pipe_slow );
10837 %}
10838 
10839 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10840   match(Set dst (MoveI2F src));
10841   effect(DEF dst, USE src);
10842   ins_cost(100);
10843   format %{ "movd    $dst,$src\t# MoveI2F" %}
10844   ins_encode %{
10845     __ movdl($dst$$XMMRegister, $src$$Register);
10846   %}
10847   ins_pipe( pipe_slow );
10848 %}
10849 
10850 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10851   match(Set dst (MoveL2D src));
10852   effect(DEF dst, USE src);
10853   ins_cost(100);
10854   format %{ "movd    $dst,$src\t# MoveL2D" %}
10855   ins_encode %{
10856      __ movdq($dst$$XMMRegister, $src$$Register);
10857   %}
10858   ins_pipe( pipe_slow );
10859 %}
10860 
10861 
10862 // =======================================================================
10863 // fast clearing of an array
10864 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10865                   Universe dummy, rFlagsReg cr)
10866 %{
10867   predicate(!((ClearArrayNode*)n)->is_large());
10868   match(Set dummy (ClearArray cnt base));
10869   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10870 
10871   format %{ $$template
10872     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
10873     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
10874     $$emit$$"jg      LARGE\n\t"
10875     $$emit$$"dec     rcx\n\t"
10876     $$emit$$"js      DONE\t# Zero length\n\t"
10877     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
10878     $$emit$$"dec     rcx\n\t"
10879     $$emit$$"jge     LOOP\n\t"
10880     $$emit$$"jmp     DONE\n\t"
10881     $$emit$$"# LARGE:\n\t"
10882     if (UseFastStosb) {
10883        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
10884        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
10885     } else if (UseXMMForObjInit) {
10886        $$emit$$"mov     rdi,rax\n\t"
10887        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
10888        $$emit$$"jmpq    L_zero_64_bytes\n\t"
10889        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10890        $$emit$$"vmovdqu ymm0,(rax)\n\t"
10891        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10892        $$emit$$"add     0x40,rax\n\t"
10893        $$emit$$"# L_zero_64_bytes:\n\t"
10894        $$emit$$"sub     0x8,rcx\n\t"
10895        $$emit$$"jge     L_loop\n\t"
10896        $$emit$$"add     0x4,rcx\n\t"
10897        $$emit$$"jl      L_tail\n\t"
10898        $$emit$$"vmovdqu ymm0,(rax)\n\t"
10899        $$emit$$"add     0x20,rax\n\t"
10900        $$emit$$"sub     0x4,rcx\n\t"
10901        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10902        $$emit$$"add     0x4,rcx\n\t"
10903        $$emit$$"jle     L_end\n\t"
10904        $$emit$$"dec     rcx\n\t"
10905        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10906        $$emit$$"vmovq   xmm0,(rax)\n\t"
10907        $$emit$$"add     0x8,rax\n\t"
10908        $$emit$$"dec     rcx\n\t"
10909        $$emit$$"jge     L_sloop\n\t"
10910        $$emit$$"# L_end:\n\t"
10911     } else {
10912        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
10913     }
10914     $$emit$$"# DONE"
10915   %}
10916   ins_encode %{
10917     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10918                  $tmp$$XMMRegister, false);
10919   %}
10920   ins_pipe(pipe_slow);
10921 %}
10922 
10923 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero, 
10924                         Universe dummy, rFlagsReg cr)
10925 %{
10926   predicate(((ClearArrayNode*)n)->is_large());
10927   match(Set dummy (ClearArray cnt base));
10928   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10929 
10930   format %{ $$template
10931     if (UseFastStosb) {
10932        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
10933        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
10934        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
10935     } else if (UseXMMForObjInit) {
10936        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
10937        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
10938        $$emit$$"jmpq    L_zero_64_bytes\n\t"
10939        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10940        $$emit$$"vmovdqu ymm0,(rax)\n\t"
10941        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10942        $$emit$$"add     0x40,rax\n\t"
10943        $$emit$$"# L_zero_64_bytes:\n\t"
10944        $$emit$$"sub     0x8,rcx\n\t"
10945        $$emit$$"jge     L_loop\n\t"
10946        $$emit$$"add     0x4,rcx\n\t"
10947        $$emit$$"jl      L_tail\n\t"
10948        $$emit$$"vmovdqu ymm0,(rax)\n\t"
10949        $$emit$$"add     0x20,rax\n\t"
10950        $$emit$$"sub     0x4,rcx\n\t"
10951        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10952        $$emit$$"add     0x4,rcx\n\t"
10953        $$emit$$"jle     L_end\n\t"
10954        $$emit$$"dec     rcx\n\t"
10955        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10956        $$emit$$"vmovq   xmm0,(rax)\n\t"
10957        $$emit$$"add     0x8,rax\n\t"
10958        $$emit$$"dec     rcx\n\t"
10959        $$emit$$"jge     L_sloop\n\t"
10960        $$emit$$"# L_end:\n\t"
10961     } else {
10962        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
10963        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
10964     }
10965   %}
10966   ins_encode %{
10967     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, 
10968                  $tmp$$XMMRegister, true);
10969   %}
10970   ins_pipe(pipe_slow);
10971 %}
10972 
10973 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10974                          rax_RegI result, legVecS tmp1, rFlagsReg cr)
10975 %{
10976   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10977   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10978   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10979 
10980   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
10981   ins_encode %{
10982     __ string_compare($str1$$Register, $str2$$Register,
10983                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
10984                       $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10985   %}
10986   ins_pipe( pipe_slow );
10987 %}
10988 
10989 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10990                          rax_RegI result, legVecS tmp1, rFlagsReg cr)
10991 %{
10992   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10993   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10994   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10995 
10996   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
10997   ins_encode %{
10998     __ string_compare($str1$$Register, $str2$$Register,
10999                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11000                       $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11001   %}
11002   ins_pipe( pipe_slow );
11003 %}
11004 
11005 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11006                           rax_RegI result, legVecS tmp1, rFlagsReg cr)
11007 %{
11008   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11009   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11010   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11011 
11012   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11013   ins_encode %{
11014     __ string_compare($str1$$Register, $str2$$Register,
11015                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11016                       $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11017   %}
11018   ins_pipe( pipe_slow );
11019 %}
11020 
11021 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11022                           rax_RegI result, legVecS tmp1, rFlagsReg cr)
11023 %{
11024   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11025   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11026   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11027 
11028   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11029   ins_encode %{
11030     __ string_compare($str2$$Register, $str1$$Register,
11031                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11032                       $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11033   %}
11034   ins_pipe( pipe_slow );
11035 %}
11036 
11037 // fast search of substring with known size.
11038 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11039                              rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11040 %{
11041   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11042   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11043   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11044 
11045   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11046   ins_encode %{
11047     int icnt2 = (int)$int_cnt2$$constant;
11048     if (icnt2 >= 16) {
11049       // IndexOf for constant substrings with size >= 16 elements
11050       // which don't need to be loaded through stack.
11051       __ string_indexofC8($str1$$Register, $str2$$Register,
11052                           $cnt1$$Register, $cnt2$$Register,
11053                           icnt2, $result$$Register,
11054                           $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11055     } else {
11056       // Small strings are loaded through stack if they cross page boundary.
11057       __ string_indexof($str1$$Register, $str2$$Register,
11058                         $cnt1$$Register, $cnt2$$Register,
11059                         icnt2, $result$$Register,
11060                         $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11061     }
11062   %}
11063   ins_pipe( pipe_slow );
11064 %}
11065 
11066 // fast search of substring with known size.
11067 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11068                              rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11069 %{
11070   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11071   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11072   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11073 
11074   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11075   ins_encode %{
11076     int icnt2 = (int)$int_cnt2$$constant;
11077     if (icnt2 >= 8) {
11078       // IndexOf for constant substrings with size >= 8 elements
11079       // which don't need to be loaded through stack.
11080       __ string_indexofC8($str1$$Register, $str2$$Register,
11081                           $cnt1$$Register, $cnt2$$Register,
11082                           icnt2, $result$$Register,
11083                           $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11084     } else {
11085       // Small strings are loaded through stack if they cross page boundary.
11086       __ string_indexof($str1$$Register, $str2$$Register,
11087                         $cnt1$$Register, $cnt2$$Register,
11088                         icnt2, $result$$Register,
11089                         $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11090     }
11091   %}
11092   ins_pipe( pipe_slow );
11093 %}
11094 
11095 // fast search of substring with known size.
11096 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11097                              rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11098 %{
11099   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11100   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11101   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11102 
11103   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11104   ins_encode %{
11105     int icnt2 = (int)$int_cnt2$$constant;
11106     if (icnt2 >= 8) {
11107       // IndexOf for constant substrings with size >= 8 elements
11108       // which don't need to be loaded through stack.
11109       __ string_indexofC8($str1$$Register, $str2$$Register,
11110                           $cnt1$$Register, $cnt2$$Register,
11111                           icnt2, $result$$Register,
11112                           $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11113     } else {
11114       // Small strings are loaded through stack if they cross page boundary.
11115       __ string_indexof($str1$$Register, $str2$$Register,
11116                         $cnt1$$Register, $cnt2$$Register,
11117                         icnt2, $result$$Register,
11118                         $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11119     }
11120   %}
11121   ins_pipe( pipe_slow );
11122 %}
11123 
11124 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11125                          rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11126 %{
11127   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11128   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11129   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11130 
11131   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11132   ins_encode %{
11133     __ string_indexof($str1$$Register, $str2$$Register,
11134                       $cnt1$$Register, $cnt2$$Register,
11135                       (-1), $result$$Register,
11136                       $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11137   %}
11138   ins_pipe( pipe_slow );
11139 %}
11140 
11141 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11142                          rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11143 %{
11144   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11145   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11146   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11147 
11148   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11149   ins_encode %{
11150     __ string_indexof($str1$$Register, $str2$$Register,
11151                       $cnt1$$Register, $cnt2$$Register,
11152                       (-1), $result$$Register,
11153                       $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11154   %}
11155   ins_pipe( pipe_slow );
11156 %}
11157 
11158 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11159                          rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11160 %{
11161   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11162   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11163   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11164 
11165   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11166   ins_encode %{
11167     __ string_indexof($str1$$Register, $str2$$Register,
11168                       $cnt1$$Register, $cnt2$$Register,
11169                       (-1), $result$$Register,
11170                       $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11171   %}
11172   ins_pipe( pipe_slow );
11173 %}
11174 
11175 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11176                               rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11177 %{
11178   predicate(UseSSE42Intrinsics);
11179   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11180   effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11181   format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11182   ins_encode %{
11183     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11184                            $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11185   %}
11186   ins_pipe( pipe_slow );
11187 %}
11188 
11189 // fast string equals
11190 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11191                        legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11192 %{
11193   match(Set result (StrEquals (Binary str1 str2) cnt));
11194   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11195 
11196   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11197   ins_encode %{
11198     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11199                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11200                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11201   %}
11202   ins_pipe( pipe_slow );
11203 %}
11204 
11205 // fast array equals
11206 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11207                        legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11208 %{
11209   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11210   match(Set result (AryEq ary1 ary2));
11211   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11212 
11213   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11214   ins_encode %{
11215     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11216                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11217                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11218   %}
11219   ins_pipe( pipe_slow );
11220 %}
11221 
11222 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11223                       legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11224 %{
11225   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11226   match(Set result (AryEq ary1 ary2));
11227   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11228 
11229   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11230   ins_encode %{
11231     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11232                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11233                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11234   %}
11235   ins_pipe( pipe_slow );
11236 %}
11237 
11238 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11239                       legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11240 %{
11241   match(Set result (HasNegatives ary1 len));
11242   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11243 
11244   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11245   ins_encode %{
11246     __ has_negatives($ary1$$Register, $len$$Register,
11247                      $result$$Register, $tmp3$$Register,
11248                      $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11249   %}
11250   ins_pipe( pipe_slow );
11251 %}
11252 
11253 // fast char[] to byte[] compression
11254 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11255                          rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11256   match(Set result (StrCompressedCopy src (Binary dst len)));
11257   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11258 
11259   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11260   ins_encode %{
11261     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11262                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11263                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11264   %}
11265   ins_pipe( pipe_slow );
11266 %}
11267 
11268 // fast byte[] to char[] inflation
11269 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11270                         legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11271   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11272   effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11273 
11274   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11275   ins_encode %{
11276     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11277                           $tmp1$$XMMRegister, $tmp2$$Register);
11278   %}
11279   ins_pipe( pipe_slow );
11280 %}
11281 
11282 // encode char[] to byte[] in ISO_8859_1
11283 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11284                           legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11285                           rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11286   match(Set result (EncodeISOArray src (Binary dst len)));
11287   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11288 
11289   format %{ "Encode array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11290   ins_encode %{
11291     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11292                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11293                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11294   %}
11295   ins_pipe( pipe_slow );
11296 %}
11297 
11298 //----------Overflow Math Instructions-----------------------------------------
11299 
11300 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11301 %{
11302   match(Set cr (OverflowAddI op1 op2));
11303   effect(DEF cr, USE_KILL op1, USE op2);
11304 
11305   format %{ "addl    $op1, $op2\t# overflow check int" %}
11306 
11307   ins_encode %{
11308     __ addl($op1$$Register, $op2$$Register);
11309   %}
11310   ins_pipe(ialu_reg_reg);
11311 %}
11312 
11313 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11314 %{
11315   match(Set cr (OverflowAddI op1 op2));
11316   effect(DEF cr, USE_KILL op1, USE op2);
11317 
11318   format %{ "addl    $op1, $op2\t# overflow check int" %}
11319 
11320   ins_encode %{
11321     __ addl($op1$$Register, $op2$$constant);
11322   %}
11323   ins_pipe(ialu_reg_reg);
11324 %}
11325 
11326 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11327 %{
11328   match(Set cr (OverflowAddL op1 op2));
11329   effect(DEF cr, USE_KILL op1, USE op2);
11330 
11331   format %{ "addq    $op1, $op2\t# overflow check long" %}
11332   ins_encode %{
11333     __ addq($op1$$Register, $op2$$Register);
11334   %}
11335   ins_pipe(ialu_reg_reg);
11336 %}
11337 
11338 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11339 %{
11340   match(Set cr (OverflowAddL op1 op2));
11341   effect(DEF cr, USE_KILL op1, USE op2);
11342 
11343   format %{ "addq    $op1, $op2\t# overflow check long" %}
11344   ins_encode %{
11345     __ addq($op1$$Register, $op2$$constant);
11346   %}
11347   ins_pipe(ialu_reg_reg);
11348 %}
11349 
11350 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11351 %{
11352   match(Set cr (OverflowSubI op1 op2));
11353 
11354   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11355   ins_encode %{
11356     __ cmpl($op1$$Register, $op2$$Register);
11357   %}
11358   ins_pipe(ialu_reg_reg);
11359 %}
11360 
11361 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11362 %{
11363   match(Set cr (OverflowSubI op1 op2));
11364 
11365   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11366   ins_encode %{
11367     __ cmpl($op1$$Register, $op2$$constant);
11368   %}
11369   ins_pipe(ialu_reg_reg);
11370 %}
11371 
11372 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11373 %{
11374   match(Set cr (OverflowSubL op1 op2));
11375 
11376   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11377   ins_encode %{
11378     __ cmpq($op1$$Register, $op2$$Register);
11379   %}
11380   ins_pipe(ialu_reg_reg);
11381 %}
11382 
11383 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11384 %{
11385   match(Set cr (OverflowSubL op1 op2));
11386 
11387   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11388   ins_encode %{
11389     __ cmpq($op1$$Register, $op2$$constant);
11390   %}
11391   ins_pipe(ialu_reg_reg);
11392 %}
11393 
11394 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11395 %{
11396   match(Set cr (OverflowSubI zero op2));
11397   effect(DEF cr, USE_KILL op2);
11398 
11399   format %{ "negl    $op2\t# overflow check int" %}
11400   ins_encode %{
11401     __ negl($op2$$Register);
11402   %}
11403   ins_pipe(ialu_reg_reg);
11404 %}
11405 
11406 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11407 %{
11408   match(Set cr (OverflowSubL zero op2));
11409   effect(DEF cr, USE_KILL op2);
11410 
11411   format %{ "negq    $op2\t# overflow check long" %}
11412   ins_encode %{
11413     __ negq($op2$$Register);
11414   %}
11415   ins_pipe(ialu_reg_reg);
11416 %}
11417 
11418 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11419 %{
11420   match(Set cr (OverflowMulI op1 op2));
11421   effect(DEF cr, USE_KILL op1, USE op2);
11422 
11423   format %{ "imull    $op1, $op2\t# overflow check int" %}
11424   ins_encode %{
11425     __ imull($op1$$Register, $op2$$Register);
11426   %}
11427   ins_pipe(ialu_reg_reg_alu0);
11428 %}
11429 
11430 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11431 %{
11432   match(Set cr (OverflowMulI op1 op2));
11433   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11434 
11435   format %{ "imull    $tmp, $op1, $op2\t# overflow check int" %}
11436   ins_encode %{
11437     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11438   %}
11439   ins_pipe(ialu_reg_reg_alu0);
11440 %}
11441 
11442 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11443 %{
11444   match(Set cr (OverflowMulL op1 op2));
11445   effect(DEF cr, USE_KILL op1, USE op2);
11446 
11447   format %{ "imulq    $op1, $op2\t# overflow check long" %}
11448   ins_encode %{
11449     __ imulq($op1$$Register, $op2$$Register);
11450   %}
11451   ins_pipe(ialu_reg_reg_alu0);
11452 %}
11453 
11454 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11455 %{
11456   match(Set cr (OverflowMulL op1 op2));
11457   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11458 
11459   format %{ "imulq    $tmp, $op1, $op2\t# overflow check long" %}
11460   ins_encode %{
11461     __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11462   %}
11463   ins_pipe(ialu_reg_reg_alu0);
11464 %}
11465 
11466 
11467 //----------Control Flow Instructions------------------------------------------
11468 // Signed compare Instructions
11469 
11470 // XXX more variants!!
11471 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11472 %{
11473   match(Set cr (CmpI op1 op2));
11474   effect(DEF cr, USE op1, USE op2);
11475 
11476   format %{ "cmpl    $op1, $op2" %}
11477   opcode(0x3B);  /* Opcode 3B /r */
11478   ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11479   ins_pipe(ialu_cr_reg_reg);
11480 %}
11481 
11482 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11483 %{
11484   match(Set cr (CmpI op1 op2));
11485 
11486   format %{ "cmpl    $op1, $op2" %}
11487   opcode(0x81, 0x07); /* Opcode 81 /7 */
11488   ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11489   ins_pipe(ialu_cr_reg_imm);
11490 %}
11491 
11492 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11493 %{
11494   match(Set cr (CmpI op1 (LoadI op2)));
11495 
11496   ins_cost(500); // XXX
11497   format %{ "cmpl    $op1, $op2" %}
11498   opcode(0x3B); /* Opcode 3B /r */
11499   ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11500   ins_pipe(ialu_cr_reg_mem);
11501 %}
11502 
11503 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11504 %{
11505   match(Set cr (CmpI src zero));
11506 
11507   format %{ "testl   $src, $src" %}
11508   opcode(0x85);
11509   ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11510   ins_pipe(ialu_cr_reg_imm);
11511 %}
11512 
11513 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11514 %{
11515   match(Set cr (CmpI (AndI src con) zero));
11516 
11517   format %{ "testl   $src, $con" %}
11518   opcode(0xF7, 0x00);
11519   ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11520   ins_pipe(ialu_cr_reg_imm);
11521 %}
11522 
11523 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11524 %{
11525   match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11526 
11527   format %{ "testl   $src, $mem" %}
11528   opcode(0x85);
11529   ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11530   ins_pipe(ialu_cr_reg_mem);
11531 %}
11532 
11533 // Unsigned compare Instructions; really, same as signed except they
11534 // produce an rFlagsRegU instead of rFlagsReg.
11535 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11536 %{
11537   match(Set cr (CmpU op1 op2));
11538 
11539   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11540   opcode(0x3B); /* Opcode 3B /r */
11541   ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11542   ins_pipe(ialu_cr_reg_reg);
11543 %}
11544 
11545 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11546 %{
11547   match(Set cr (CmpU op1 op2));
11548 
11549   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11550   opcode(0x81,0x07); /* Opcode 81 /7 */
11551   ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11552   ins_pipe(ialu_cr_reg_imm);
11553 %}
11554 
11555 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11556 %{
11557   match(Set cr (CmpU op1 (LoadI op2)));
11558 
11559   ins_cost(500); // XXX
11560   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11561   opcode(0x3B); /* Opcode 3B /r */
11562   ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11563   ins_pipe(ialu_cr_reg_mem);
11564 %}
11565 
11566 // // // Cisc-spilled version of cmpU_rReg
11567 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11568 // //%{
11569 // //  match(Set cr (CmpU (LoadI op1) op2));
11570 // //
11571 // //  format %{ "CMPu   $op1,$op2" %}
11572 // //  ins_cost(500);
11573 // //  opcode(0x39);  /* Opcode 39 /r */
11574 // //  ins_encode( OpcP, reg_mem( op1, op2) );
11575 // //%}
11576 
11577 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11578 %{
11579   match(Set cr (CmpU src zero));
11580 
11581   format %{ "testl  $src, $src\t# unsigned" %}
11582   opcode(0x85);
11583   ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11584   ins_pipe(ialu_cr_reg_imm);
11585 %}
11586 
11587 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11588 %{
11589   match(Set cr (CmpP op1 op2));
11590 
11591   format %{ "cmpq    $op1, $op2\t# ptr" %}
11592   opcode(0x3B); /* Opcode 3B /r */
11593   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11594   ins_pipe(ialu_cr_reg_reg);
11595 %}
11596 
11597 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11598 %{
11599   match(Set cr (CmpP op1 (LoadP op2)));
11600 
11601   ins_cost(500); // XXX
11602   format %{ "cmpq    $op1, $op2\t# ptr" %}
11603   opcode(0x3B); /* Opcode 3B /r */
11604   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11605   ins_pipe(ialu_cr_reg_mem);
11606 %}
11607 
11608 // // // Cisc-spilled version of cmpP_rReg
11609 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11610 // //%{
11611 // //  match(Set cr (CmpP (LoadP op1) op2));
11612 // //
11613 // //  format %{ "CMPu   $op1,$op2" %}
11614 // //  ins_cost(500);
11615 // //  opcode(0x39);  /* Opcode 39 /r */
11616 // //  ins_encode( OpcP, reg_mem( op1, op2) );
11617 // //%}
11618 
11619 // XXX this is generalized by compP_rReg_mem???
11620 // Compare raw pointer (used in out-of-heap check).
11621 // Only works because non-oop pointers must be raw pointers
11622 // and raw pointers have no anti-dependencies.
11623 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11624 %{
11625   predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11626   match(Set cr (CmpP op1 (LoadP op2)));
11627 
11628   format %{ "cmpq    $op1, $op2\t# raw ptr" %}
11629   opcode(0x3B); /* Opcode 3B /r */
11630   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11631   ins_pipe(ialu_cr_reg_mem);
11632 %}
11633 
11634 // This will generate a signed flags result. This should be OK since
11635 // any compare to a zero should be eq/neq.
11636 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11637 %{
11638   match(Set cr (CmpP src zero));
11639 
11640   format %{ "testq   $src, $src\t# ptr" %}
11641   opcode(0x85);
11642   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11643   ins_pipe(ialu_cr_reg_imm);
11644 %}
11645 
11646 // This will generate a signed flags result. This should be OK since
11647 // any compare to a zero should be eq/neq.
11648 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11649 %{
11650   predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11651   match(Set cr (CmpP (LoadP op) zero));
11652 
11653   ins_cost(500); // XXX
11654   format %{ "testq   $op, 0xffffffffffffffff\t# ptr" %}
11655   opcode(0xF7); /* Opcode F7 /0 */
11656   ins_encode(REX_mem_wide(op),
11657              OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11658   ins_pipe(ialu_cr_reg_imm);
11659 %}
11660 
11661 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11662 %{
11663   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11664   match(Set cr (CmpP (LoadP mem) zero));
11665 
11666   format %{ "cmpq    R12, $mem\t# ptr (R12_heapbase==0)" %}
11667   ins_encode %{
11668     __ cmpq(r12, $mem$$Address);
11669   %}
11670   ins_pipe(ialu_cr_reg_mem);
11671 %}
11672 
11673 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11674 %{
11675   match(Set cr (CmpN op1 op2));
11676 
11677   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
11678   ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11679   ins_pipe(ialu_cr_reg_reg);
11680 %}
11681 
11682 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11683 %{
11684   match(Set cr (CmpN src (LoadN mem)));
11685 
11686   format %{ "cmpl    $src, $mem\t# compressed ptr" %}
11687   ins_encode %{
11688     __ cmpl($src$$Register, $mem$$Address);
11689   %}
11690   ins_pipe(ialu_cr_reg_mem);
11691 %}
11692 
11693 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11694   match(Set cr (CmpN op1 op2));
11695 
11696   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
11697   ins_encode %{
11698     __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11699   %}
11700   ins_pipe(ialu_cr_reg_imm);
11701 %}
11702 
11703 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11704 %{
11705   match(Set cr (CmpN src (LoadN mem)));
11706 
11707   format %{ "cmpl    $mem, $src\t# compressed ptr" %}
11708   ins_encode %{
11709     __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11710   %}
11711   ins_pipe(ialu_cr_reg_mem);
11712 %}
11713 
11714 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11715   match(Set cr (CmpN op1 op2));
11716 
11717   format %{ "cmpl    $op1, $op2\t# compressed klass ptr" %}
11718   ins_encode %{
11719     __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11720   %}
11721   ins_pipe(ialu_cr_reg_imm);
11722 %}
11723 
11724 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11725 %{
11726   match(Set cr (CmpN src (LoadNKlass mem)));
11727 
11728   format %{ "cmpl    $mem, $src\t# compressed klass ptr" %}
11729   ins_encode %{
11730     __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11731   %}
11732   ins_pipe(ialu_cr_reg_mem);
11733 %}
11734 
11735 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11736   match(Set cr (CmpN src zero));
11737 
11738   format %{ "testl   $src, $src\t# compressed ptr" %}
11739   ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11740   ins_pipe(ialu_cr_reg_imm);
11741 %}
11742 
11743 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11744 %{
11745   predicate(Universe::narrow_oop_base() != NULL);
11746   match(Set cr (CmpN (LoadN mem) zero));
11747 
11748   ins_cost(500); // XXX
11749   format %{ "testl   $mem, 0xffffffff\t# compressed ptr" %}
11750   ins_encode %{
11751     __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11752   %}
11753   ins_pipe(ialu_cr_reg_mem);
11754 %}
11755 
11756 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11757 %{
11758   predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11759   match(Set cr (CmpN (LoadN mem) zero));
11760 
11761   format %{ "cmpl    R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11762   ins_encode %{
11763     __ cmpl(r12, $mem$$Address);
11764   %}
11765   ins_pipe(ialu_cr_reg_mem);
11766 %}
11767 
11768 // Yanked all unsigned pointer compare operations.
11769 // Pointer compares are done with CmpP which is already unsigned.
11770 
11771 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11772 %{
11773   match(Set cr (CmpL op1 op2));
11774 
11775   format %{ "cmpq    $op1, $op2" %}
11776   opcode(0x3B);  /* Opcode 3B /r */
11777   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11778   ins_pipe(ialu_cr_reg_reg);
11779 %}
11780 
11781 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11782 %{
11783   match(Set cr (CmpL op1 op2));
11784 
11785   format %{ "cmpq    $op1, $op2" %}
11786   opcode(0x81, 0x07); /* Opcode 81 /7 */
11787   ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11788   ins_pipe(ialu_cr_reg_imm);
11789 %}
11790 
11791 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11792 %{
11793   match(Set cr (CmpL op1 (LoadL op2)));
11794 
11795   format %{ "cmpq    $op1, $op2" %}
11796   opcode(0x3B); /* Opcode 3B /r */
11797   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11798   ins_pipe(ialu_cr_reg_mem);
11799 %}
11800 
11801 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11802 %{
11803   match(Set cr (CmpL src zero));
11804 
11805   format %{ "testq   $src, $src" %}
11806   opcode(0x85);
11807   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11808   ins_pipe(ialu_cr_reg_imm);
11809 %}
11810 
11811 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11812 %{
11813   match(Set cr (CmpL (AndL src con) zero));
11814 
11815   format %{ "testq   $src, $con\t# long" %}
11816   opcode(0xF7, 0x00);
11817   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11818   ins_pipe(ialu_cr_reg_imm);
11819 %}
11820 
11821 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11822 %{
11823   match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11824 
11825   format %{ "testq   $src, $mem" %}
11826   opcode(0x85);
11827   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11828   ins_pipe(ialu_cr_reg_mem);
11829 %}
11830 
11831 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11832 %{
11833   match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11834 
11835   format %{ "testq   $src, $mem" %}
11836   opcode(0x85);
11837   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11838   ins_pipe(ialu_cr_reg_mem);
11839 %}
11840 
11841 // Manifest a CmpL result in an integer register.  Very painful.
11842 // This is the test to avoid.
11843 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11844 %{
11845   match(Set dst (CmpL3 src1 src2));
11846   effect(KILL flags);
11847 
11848   ins_cost(275); // XXX
11849   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
11850             "movl    $dst, -1\n\t"
11851             "jl,s    done\n\t"
11852             "setne   $dst\n\t"
11853             "movzbl  $dst, $dst\n\t"
11854     "done:" %}
11855   ins_encode(cmpl3_flag(src1, src2, dst));
11856   ins_pipe(pipe_slow);
11857 %}
11858 
11859 // Unsigned long compare Instructions; really, same as signed long except they
11860 // produce an rFlagsRegU instead of rFlagsReg.
11861 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11862 %{
11863   match(Set cr (CmpUL op1 op2));
11864 
11865   format %{ "cmpq    $op1, $op2\t# unsigned" %}
11866   opcode(0x3B);  /* Opcode 3B /r */
11867   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11868   ins_pipe(ialu_cr_reg_reg);
11869 %}
11870 
11871 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
11872 %{
11873   match(Set cr (CmpUL op1 op2));
11874 
11875   format %{ "cmpq    $op1, $op2\t# unsigned" %}
11876   opcode(0x81, 0x07); /* Opcode 81 /7 */
11877   ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11878   ins_pipe(ialu_cr_reg_imm);
11879 %}
11880 
11881 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11882 %{
11883   match(Set cr (CmpUL op1 (LoadL op2)));
11884 
11885   format %{ "cmpq    $op1, $op2\t# unsigned" %}
11886   opcode(0x3B); /* Opcode 3B /r */
11887   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11888   ins_pipe(ialu_cr_reg_mem);
11889 %}
11890 
11891 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11892 %{
11893   match(Set cr (CmpUL src zero));
11894 
11895   format %{ "testq   $src, $src\t# unsigned" %}
11896   opcode(0x85);
11897   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11898   ins_pipe(ialu_cr_reg_imm);
11899 %}
11900 
11901 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
11902 %{
11903   match(Set cr (CmpI (LoadB mem) imm));
11904 
11905   ins_cost(125);
11906   format %{ "cmpb    $mem, $imm" %}
11907   ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11908   ins_pipe(ialu_cr_reg_mem);
11909 %}
11910 
11911 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
11912 %{
11913   match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
11914 
11915   ins_cost(125);
11916   format %{ "testb   $mem, $imm" %}
11917   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11918   ins_pipe(ialu_cr_reg_mem);
11919 %}
11920 
11921 //----------Max and Min--------------------------------------------------------
11922 // Min Instructions
11923 
11924 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11925 %{
11926   effect(USE_DEF dst, USE src, USE cr);
11927 
11928   format %{ "cmovlgt $dst, $src\t# min" %}
11929   opcode(0x0F, 0x4F);
11930   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11931   ins_pipe(pipe_cmov_reg);
11932 %}
11933 
11934 
11935 instruct minI_rReg(rRegI dst, rRegI src)
11936 %{
11937   match(Set dst (MinI dst src));
11938 
11939   ins_cost(200);
11940   expand %{
11941     rFlagsReg cr;
11942     compI_rReg(cr, dst, src);
11943     cmovI_reg_g(dst, src, cr);
11944   %}
11945 %}
11946 
11947 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11948 %{
11949   effect(USE_DEF dst, USE src, USE cr);
11950 
11951   format %{ "cmovllt $dst, $src\t# max" %}
11952   opcode(0x0F, 0x4C);
11953   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11954   ins_pipe(pipe_cmov_reg);
11955 %}
11956 
11957 
11958 instruct maxI_rReg(rRegI dst, rRegI src)
11959 %{
11960   match(Set dst (MaxI dst src));
11961 
11962   ins_cost(200);
11963   expand %{
11964     rFlagsReg cr;
11965     compI_rReg(cr, dst, src);
11966     cmovI_reg_l(dst, src, cr);
11967   %}
11968 %}
11969 
11970 // ============================================================================
11971 // Branch Instructions
11972 
11973 // Jump Direct - Label defines a relative address from JMP+1
11974 instruct jmpDir(label labl)
11975 %{
11976   match(Goto);
11977   effect(USE labl);
11978 
11979   ins_cost(300);
11980   format %{ "jmp     $labl" %}
11981   size(5);
11982   ins_encode %{
11983     Label* L = $labl$$label;
11984     __ jmp(*L, false); // Always long jump
11985   %}
11986   ins_pipe(pipe_jmp);
11987 %}
11988 
11989 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11990 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11991 %{
11992   match(If cop cr);
11993   effect(USE labl);
11994 
11995   ins_cost(300);
11996   format %{ "j$cop     $labl" %}
11997   size(6);
11998   ins_encode %{
11999     Label* L = $labl$$label;
12000     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12001   %}
12002   ins_pipe(pipe_jcc);
12003 %}
12004 
12005 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12006 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12007 %{
12008   predicate(!n->has_vector_mask_set());
12009   match(CountedLoopEnd cop cr);
12010   effect(USE labl);
12011 
12012   ins_cost(300);
12013   format %{ "j$cop     $labl\t# loop end" %}
12014   size(6);
12015   ins_encode %{
12016     Label* L = $labl$$label;
12017     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12018   %}
12019   ins_pipe(pipe_jcc);
12020 %}
12021 
12022 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12023 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12024   predicate(!n->has_vector_mask_set());
12025   match(CountedLoopEnd cop cmp);
12026   effect(USE labl);
12027 
12028   ins_cost(300);
12029   format %{ "j$cop,u   $labl\t# loop end" %}
12030   size(6);
12031   ins_encode %{
12032     Label* L = $labl$$label;
12033     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12034   %}
12035   ins_pipe(pipe_jcc);
12036 %}
12037 
12038 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12039   predicate(!n->has_vector_mask_set());
12040   match(CountedLoopEnd cop cmp);
12041   effect(USE labl);
12042 
12043   ins_cost(200);
12044   format %{ "j$cop,u   $labl\t# loop end" %}
12045   size(6);
12046   ins_encode %{
12047     Label* L = $labl$$label;
12048     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12049   %}
12050   ins_pipe(pipe_jcc);
12051 %}
12052 
12053 // mask version
12054 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12055 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12056 %{
12057   predicate(n->has_vector_mask_set());
12058   match(CountedLoopEnd cop cr);
12059   effect(USE labl);
12060 
12061   ins_cost(400);
12062   format %{ "j$cop     $labl\t# loop end\n\t"
12063             "restorevectmask \t# vector mask restore for loops" %}
12064   size(10);
12065   ins_encode %{
12066     Label* L = $labl$$label;
12067     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12068     __ restorevectmask();
12069   %}
12070   ins_pipe(pipe_jcc);
12071 %}
12072 
12073 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12074 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12075   predicate(n->has_vector_mask_set());
12076   match(CountedLoopEnd cop cmp);
12077   effect(USE labl);
12078 
12079   ins_cost(400);
12080   format %{ "j$cop,u   $labl\t# loop end\n\t"
12081             "restorevectmask \t# vector mask restore for loops" %}
12082   size(10);
12083   ins_encode %{
12084     Label* L = $labl$$label;
12085     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12086     __ restorevectmask();
12087   %}
12088   ins_pipe(pipe_jcc);
12089 %}
12090 
12091 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12092   predicate(n->has_vector_mask_set());
12093   match(CountedLoopEnd cop cmp);
12094   effect(USE labl);
12095 
12096   ins_cost(300);
12097   format %{ "j$cop,u   $labl\t# loop end\n\t"
12098             "restorevectmask \t# vector mask restore for loops" %}
12099   size(10);
12100   ins_encode %{
12101     Label* L = $labl$$label;
12102     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12103     __ restorevectmask();
12104   %}
12105   ins_pipe(pipe_jcc);
12106 %}
12107 
12108 // Jump Direct Conditional - using unsigned comparison
12109 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12110   match(If cop cmp);
12111   effect(USE labl);
12112 
12113   ins_cost(300);
12114   format %{ "j$cop,u  $labl" %}
12115   size(6);
12116   ins_encode %{
12117     Label* L = $labl$$label;
12118     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12119   %}
12120   ins_pipe(pipe_jcc);
12121 %}
12122 
12123 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12124   match(If cop cmp);
12125   effect(USE labl);
12126 
12127   ins_cost(200);
12128   format %{ "j$cop,u  $labl" %}
12129   size(6);
12130   ins_encode %{
12131     Label* L = $labl$$label;
12132     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12133   %}
12134   ins_pipe(pipe_jcc);
12135 %}
12136 
12137 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12138   match(If cop cmp);
12139   effect(USE labl);
12140 
12141   ins_cost(200);
12142   format %{ $$template
12143     if ($cop$$cmpcode == Assembler::notEqual) {
12144       $$emit$$"jp,u   $labl\n\t"
12145       $$emit$$"j$cop,u   $labl"
12146     } else {
12147       $$emit$$"jp,u   done\n\t"
12148       $$emit$$"j$cop,u   $labl\n\t"
12149       $$emit$$"done:"
12150     }
12151   %}
12152   ins_encode %{
12153     Label* l = $labl$$label;
12154     if ($cop$$cmpcode == Assembler::notEqual) {
12155       __ jcc(Assembler::parity, *l, false);
12156       __ jcc(Assembler::notEqual, *l, false);
12157     } else if ($cop$$cmpcode == Assembler::equal) {
12158       Label done;
12159       __ jccb(Assembler::parity, done);
12160       __ jcc(Assembler::equal, *l, false);
12161       __ bind(done);
12162     } else {
12163        ShouldNotReachHere();
12164     }
12165   %}
12166   ins_pipe(pipe_jcc);
12167 %}
12168 
12169 // ============================================================================
12170 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary
12171 // superklass array for an instance of the superklass.  Set a hidden
12172 // internal cache on a hit (cache is checked with exposed code in
12173 // gen_subtype_check()).  Return NZ for a miss or zero for a hit.  The
12174 // encoding ALSO sets flags.
12175 
12176 instruct partialSubtypeCheck(rdi_RegP result,
12177                              rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12178                              rFlagsReg cr)
12179 %{
12180   match(Set result (PartialSubtypeCheck sub super));
12181   effect(KILL rcx, KILL cr);
12182 
12183   ins_cost(1100);  // slightly larger than the next version
12184   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12185             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12186             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12187             "repne   scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12188             "jne,s   miss\t\t# Missed: rdi not-zero\n\t"
12189             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12190             "xorq    $result, $result\t\t Hit: rdi zero\n\t"
12191     "miss:\t" %}
12192 
12193   opcode(0x1); // Force a XOR of RDI
12194   ins_encode(enc_PartialSubtypeCheck());
12195   ins_pipe(pipe_slow);
12196 %}
12197 
12198 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12199                                      rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12200                                      immP0 zero,
12201                                      rdi_RegP result)
12202 %{
12203   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12204   effect(KILL rcx, KILL result);
12205 
12206   ins_cost(1000);
12207   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12208             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12209             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12210             "repne   scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12211             "jne,s   miss\t\t# Missed: flags nz\n\t"
12212             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12213     "miss:\t" %}
12214 
12215   opcode(0x0); // No need to XOR RDI
12216   ins_encode(enc_PartialSubtypeCheck());
12217   ins_pipe(pipe_slow);
12218 %}
12219 
12220 // ============================================================================
12221 // Branch Instructions -- short offset versions
12222 //
12223 // These instructions are used to replace jumps of a long offset (the default
12224 // match) with jumps of a shorter offset.  These instructions are all tagged
12225 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12226 // match rules in general matching.  Instead, the ADLC generates a conversion
12227 // method in the MachNode which can be used to do in-place replacement of the
12228 // long variant with the shorter variant.  The compiler will determine if a
12229 // branch can be taken by the is_short_branch_offset() predicate in the machine
12230 // specific code section of the file.
12231 
12232 // Jump Direct - Label defines a relative address from JMP+1
12233 instruct jmpDir_short(label labl) %{
12234   match(Goto);
12235   effect(USE labl);
12236 
12237   ins_cost(300);
12238   format %{ "jmp,s   $labl" %}
12239   size(2);
12240   ins_encode %{
12241     Label* L = $labl$$label;
12242     __ jmpb(*L);
12243   %}
12244   ins_pipe(pipe_jmp);
12245   ins_short_branch(1);
12246 %}
12247 
12248 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12249 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12250   match(If cop cr);
12251   effect(USE labl);
12252 
12253   ins_cost(300);
12254   format %{ "j$cop,s   $labl" %}
12255   size(2);
12256   ins_encode %{
12257     Label* L = $labl$$label;
12258     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12259   %}
12260   ins_pipe(pipe_jcc);
12261   ins_short_branch(1);
12262 %}
12263 
12264 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12265 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12266   match(CountedLoopEnd cop cr);
12267   effect(USE labl);
12268 
12269   ins_cost(300);
12270   format %{ "j$cop,s   $labl\t# loop end" %}
12271   size(2);
12272   ins_encode %{
12273     Label* L = $labl$$label;
12274     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12275   %}
12276   ins_pipe(pipe_jcc);
12277   ins_short_branch(1);
12278 %}
12279 
12280 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12281 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12282   match(CountedLoopEnd cop cmp);
12283   effect(USE labl);
12284 
12285   ins_cost(300);
12286   format %{ "j$cop,us  $labl\t# loop end" %}
12287   size(2);
12288   ins_encode %{
12289     Label* L = $labl$$label;
12290     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12291   %}
12292   ins_pipe(pipe_jcc);
12293   ins_short_branch(1);
12294 %}
12295 
12296 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12297   match(CountedLoopEnd cop cmp);
12298   effect(USE labl);
12299 
12300   ins_cost(300);
12301   format %{ "j$cop,us  $labl\t# loop end" %}
12302   size(2);
12303   ins_encode %{
12304     Label* L = $labl$$label;
12305     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12306   %}
12307   ins_pipe(pipe_jcc);
12308   ins_short_branch(1);
12309 %}
12310 
12311 // Jump Direct Conditional - using unsigned comparison
12312 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12313   match(If cop cmp);
12314   effect(USE labl);
12315 
12316   ins_cost(300);
12317   format %{ "j$cop,us  $labl" %}
12318   size(2);
12319   ins_encode %{
12320     Label* L = $labl$$label;
12321     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12322   %}
12323   ins_pipe(pipe_jcc);
12324   ins_short_branch(1);
12325 %}
12326 
12327 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12328   match(If cop cmp);
12329   effect(USE labl);
12330 
12331   ins_cost(300);
12332   format %{ "j$cop,us  $labl" %}
12333   size(2);
12334   ins_encode %{
12335     Label* L = $labl$$label;
12336     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12337   %}
12338   ins_pipe(pipe_jcc);
12339   ins_short_branch(1);
12340 %}
12341 
12342 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12343   match(If cop cmp);
12344   effect(USE labl);
12345 
12346   ins_cost(300);
12347   format %{ $$template
12348     if ($cop$$cmpcode == Assembler::notEqual) {
12349       $$emit$$"jp,u,s   $labl\n\t"
12350       $$emit$$"j$cop,u,s   $labl"
12351     } else {
12352       $$emit$$"jp,u,s   done\n\t"
12353       $$emit$$"j$cop,u,s  $labl\n\t"
12354       $$emit$$"done:"
12355     }
12356   %}
12357   size(4);
12358   ins_encode %{
12359     Label* l = $labl$$label;
12360     if ($cop$$cmpcode == Assembler::notEqual) {
12361       __ jccb(Assembler::parity, *l);
12362       __ jccb(Assembler::notEqual, *l);
12363     } else if ($cop$$cmpcode == Assembler::equal) {
12364       Label done;
12365       __ jccb(Assembler::parity, done);
12366       __ jccb(Assembler::equal, *l);
12367       __ bind(done);
12368     } else {
12369        ShouldNotReachHere();
12370     }
12371   %}
12372   ins_pipe(pipe_jcc);
12373   ins_short_branch(1);
12374 %}
12375 
12376 // ============================================================================
12377 // inlined locking and unlocking
12378 
12379 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12380   predicate(Compile::current()->use_rtm());
12381   match(Set cr (FastLock object box));
12382   effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12383   ins_cost(300);
12384   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12385   ins_encode %{
12386     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12387                  $scr$$Register, $cx1$$Register, $cx2$$Register,
12388                  _counters, _rtm_counters, _stack_rtm_counters,
12389                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12390                  true, ra_->C->profile_rtm());
12391   %}
12392   ins_pipe(pipe_slow);
12393 %}
12394 
12395 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12396   predicate(!Compile::current()->use_rtm());
12397   match(Set cr (FastLock object box));
12398   effect(TEMP tmp, TEMP scr, USE_KILL box);
12399   ins_cost(300);
12400   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12401   ins_encode %{
12402     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12403                  $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12404   %}
12405   ins_pipe(pipe_slow);
12406 %}
12407 
12408 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12409   match(Set cr (FastUnlock object box));
12410   effect(TEMP tmp, USE_KILL box);
12411   ins_cost(300);
12412   format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12413   ins_encode %{
12414     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12415   %}
12416   ins_pipe(pipe_slow);
12417 %}
12418 
12419 
12420 // ============================================================================
12421 // Safepoint Instructions
12422 instruct safePoint_poll(rFlagsReg cr)
12423 %{
12424   predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12425   match(SafePoint);
12426   effect(KILL cr);
12427 
12428   format %{ "testl  rax, [rip + #offset_to_poll_page]\t"
12429             "# Safepoint: poll for GC" %}
12430   ins_cost(125);
12431   ins_encode %{
12432     AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12433     __ testl(rax, addr);
12434   %}
12435   ins_pipe(ialu_reg_mem);
12436 %}
12437 
12438 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12439 %{
12440   predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12441   match(SafePoint poll);
12442   effect(KILL cr, USE poll);
12443 
12444   format %{ "testl  rax, [$poll]\t"
12445             "# Safepoint: poll for GC" %}
12446   ins_cost(125);
12447   ins_encode %{
12448     __ relocate(relocInfo::poll_type);
12449     __ testl(rax, Address($poll$$Register, 0));
12450   %}
12451   ins_pipe(ialu_reg_mem);
12452 %}
12453 
12454 instruct safePoint_poll_tls(rFlagsReg cr, rex_RegP poll)
12455 %{
12456   predicate(SafepointMechanism::uses_thread_local_poll());
12457   match(SafePoint poll);
12458   effect(KILL cr, USE poll);
12459 
12460   format %{ "testl  rax, [$poll]\t"
12461             "# Safepoint: poll for GC" %}
12462   ins_cost(125);
12463   size(3); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12464   ins_encode %{
12465     __ relocate(relocInfo::poll_type);
12466     address pre_pc = __ pc();
12467     __ testl(rax, Address($poll$$Register, 0));
12468     address post_pc = __ pc();
12469     guarantee(pre_pc[0] == 0x41 && pre_pc[1] == 0x85, "must emit #rex test-ax [reg]");
12470   %}
12471   ins_pipe(ialu_reg_mem);
12472 %}
12473 
12474 // ============================================================================
12475 // Procedure Call/Return Instructions
12476 // Call Java Static Instruction
12477 // Note: If this code changes, the corresponding ret_addr_offset() and
12478 //       compute_padding() functions will have to be adjusted.
12479 instruct CallStaticJavaDirect(method meth) %{
12480   match(CallStaticJava);
12481   effect(USE meth);
12482 
12483   ins_cost(300);
12484   format %{ "call,static " %}
12485   opcode(0xE8); /* E8 cd */
12486   ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12487   ins_pipe(pipe_slow);
12488   ins_alignment(4);
12489 %}
12490 
12491 // Call Java Dynamic Instruction
12492 // Note: If this code changes, the corresponding ret_addr_offset() and
12493 //       compute_padding() functions will have to be adjusted.
12494 instruct CallDynamicJavaDirect(method meth)
12495 %{
12496   match(CallDynamicJava);
12497   effect(USE meth);
12498 
12499   ins_cost(300);
12500   format %{ "movq    rax, #Universe::non_oop_word()\n\t"
12501             "call,dynamic " %}
12502   ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12503   ins_pipe(pipe_slow);
12504   ins_alignment(4);
12505 %}
12506 
12507 // Call Runtime Instruction
12508 instruct CallRuntimeDirect(method meth)
12509 %{
12510   match(CallRuntime);
12511   effect(USE meth);
12512 
12513   ins_cost(300);
12514   format %{ "call,runtime " %}
12515   ins_encode(clear_avx, Java_To_Runtime(meth));
12516   ins_pipe(pipe_slow);
12517 %}
12518 
12519 // Call runtime without safepoint
12520 instruct CallLeafDirect(method meth)
12521 %{
12522   match(CallLeaf);
12523   effect(USE meth);
12524 
12525   ins_cost(300);
12526   format %{ "call_leaf,runtime " %}
12527   ins_encode(clear_avx, Java_To_Runtime(meth));
12528   ins_pipe(pipe_slow);
12529 %}
12530 
12531 // Call runtime without safepoint
12532 instruct CallLeafNoFPDirect(method meth)
12533 %{
12534   match(CallLeafNoFP);
12535   effect(USE meth);
12536 
12537   ins_cost(300);
12538   format %{ "call_leaf_nofp,runtime " %}
12539   ins_encode(clear_avx, Java_To_Runtime(meth));
12540   ins_pipe(pipe_slow);
12541 %}
12542 
12543 // Return Instruction
12544 // Remove the return address & jump to it.
12545 // Notice: We always emit a nop after a ret to make sure there is room
12546 // for safepoint patching
12547 instruct Ret()
12548 %{
12549   match(Return);
12550 
12551   format %{ "ret" %}
12552   opcode(0xC3);
12553   ins_encode(OpcP);
12554   ins_pipe(pipe_jmp);
12555 %}
12556 
12557 // Tail Call; Jump from runtime stub to Java code.
12558 // Also known as an 'interprocedural jump'.
12559 // Target of jump will eventually return to caller.
12560 // TailJump below removes the return address.
12561 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12562 %{
12563   match(TailCall jump_target method_oop);
12564 
12565   ins_cost(300);
12566   format %{ "jmp     $jump_target\t# rbx holds method oop" %}
12567   opcode(0xFF, 0x4); /* Opcode FF /4 */
12568   ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12569   ins_pipe(pipe_jmp);
12570 %}
12571 
12572 // Tail Jump; remove the return address; jump to target.
12573 // TailCall above leaves the return address around.
12574 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12575 %{
12576   match(TailJump jump_target ex_oop);
12577 
12578   ins_cost(300);
12579   format %{ "popq    rdx\t# pop return address\n\t"
12580             "jmp     $jump_target" %}
12581   opcode(0xFF, 0x4); /* Opcode FF /4 */
12582   ins_encode(Opcode(0x5a), // popq rdx
12583              REX_reg(jump_target), OpcP, reg_opc(jump_target));
12584   ins_pipe(pipe_jmp);
12585 %}
12586 
12587 // Create exception oop: created by stack-crawling runtime code.
12588 // Created exception is now available to this handler, and is setup
12589 // just prior to jumping to this handler.  No code emitted.
12590 instruct CreateException(rax_RegP ex_oop)
12591 %{
12592   match(Set ex_oop (CreateEx));
12593 
12594   size(0);
12595   // use the following format syntax
12596   format %{ "# exception oop is in rax; no code emitted" %}
12597   ins_encode();
12598   ins_pipe(empty);
12599 %}
12600 
12601 // Rethrow exception:
12602 // The exception oop will come in the first argument position.
12603 // Then JUMP (not call) to the rethrow stub code.
12604 instruct RethrowException()
12605 %{
12606   match(Rethrow);
12607 
12608   // use the following format syntax
12609   format %{ "jmp     rethrow_stub" %}
12610   ins_encode(enc_rethrow);
12611   ins_pipe(pipe_jmp);
12612 %}
12613 
12614 //
12615 // Execute ZGC load barrier (strong) slow path
12616 //
12617 
12618 // When running without XMM regs
12619 instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12620 
12621   match(Set dst (LoadBarrierSlowReg mem));
12622   predicate(MaxVectorSize < 16);
12623 
12624   effect(DEF dst, KILL cr);
12625 
12626   format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12627   ins_encode %{
12628 #if INCLUDE_ZGC
12629     Register d = $dst$$Register;
12630     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12631 
12632     assert(d != r12, "Can't be R12!");
12633     assert(d != r15, "Can't be R15!");
12634     assert(d != rsp, "Can't be RSP!");
12635 
12636     __ lea(d, $mem$$Address);
12637     __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12638 #else
12639     ShouldNotReachHere();
12640 #endif
12641   %}
12642   ins_pipe(pipe_slow);
12643 %}
12644 
12645 // For XMM and YMM enabled processors
12646 instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12647                                      rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12648                                      rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12649                                      rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12650                                      rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12651 
12652   match(Set dst (LoadBarrierSlowReg mem));
12653   predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12654 
12655   effect(DEF dst, KILL cr,
12656          KILL x0, KILL x1, KILL x2, KILL x3,
12657          KILL x4, KILL x5, KILL x6, KILL x7,
12658          KILL x8, KILL x9, KILL x10, KILL x11,
12659          KILL x12, KILL x13, KILL x14, KILL x15);
12660 
12661   format %{"LoadBarrierSlowRegXmm $dst, $mem" %}
12662   ins_encode %{
12663 #if INCLUDE_ZGC
12664     Register d = $dst$$Register;
12665     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12666 
12667     assert(d != r12, "Can't be R12!");
12668     assert(d != r15, "Can't be R15!");
12669     assert(d != rsp, "Can't be RSP!");
12670 
12671     __ lea(d, $mem$$Address);
12672     __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12673 #else
12674     ShouldNotReachHere();
12675 #endif
12676   %}
12677   ins_pipe(pipe_slow);
12678 %}
12679 
12680 // For ZMM enabled processors
12681 instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12682                                rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12683                                rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12684                                rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12685                                rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12686                                rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12687                                rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12688                                rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12689                                rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12690 
12691   match(Set dst (LoadBarrierSlowReg mem));
12692   predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12693 
12694   effect(DEF dst, KILL cr,
12695          KILL x0, KILL x1, KILL x2, KILL x3,
12696          KILL x4, KILL x5, KILL x6, KILL x7,
12697          KILL x8, KILL x9, KILL x10, KILL x11,
12698          KILL x12, KILL x13, KILL x14, KILL x15,
12699          KILL x16, KILL x17, KILL x18, KILL x19,
12700          KILL x20, KILL x21, KILL x22, KILL x23,
12701          KILL x24, KILL x25, KILL x26, KILL x27,
12702          KILL x28, KILL x29, KILL x30, KILL x31);
12703 
12704   format %{"LoadBarrierSlowRegZmm $dst, $mem" %}
12705   ins_encode %{
12706 #if INCLUDE_ZGC
12707     Register d = $dst$$Register;
12708     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12709 
12710     assert(d != r12, "Can't be R12!");
12711     assert(d != r15, "Can't be R15!");
12712     assert(d != rsp, "Can't be RSP!");
12713 
12714     __ lea(d, $mem$$Address);
12715     __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12716 #else
12717     ShouldNotReachHere();
12718 #endif
12719   %}
12720   ins_pipe(pipe_slow);
12721 %}
12722 
12723 //
12724 // Execute ZGC load barrier (weak) slow path
12725 //
12726 
12727 // When running without XMM regs
12728 instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12729 
12730   match(Set dst (LoadBarrierSlowReg mem));
12731   predicate(MaxVectorSize < 16);
12732 
12733   effect(DEF dst, KILL cr);
12734 
12735   format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12736   ins_encode %{
12737 #if INCLUDE_ZGC
12738     Register d = $dst$$Register;
12739     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12740 
12741     assert(d != r12, "Can't be R12!");
12742     assert(d != r15, "Can't be R15!");
12743     assert(d != rsp, "Can't be RSP!");
12744 
12745     __ lea(d, $mem$$Address);
12746     __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12747 #else
12748     ShouldNotReachHere();
12749 #endif
12750   %}
12751   ins_pipe(pipe_slow);
12752 %}
12753 
12754 // For XMM and YMM enabled processors
12755 instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12756                                          rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12757                                          rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12758                                          rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12759                                          rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12760 
12761   match(Set dst (LoadBarrierWeakSlowReg mem));
12762   predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12763 
12764   effect(DEF dst, KILL cr,
12765          KILL x0, KILL x1, KILL x2, KILL x3,
12766          KILL x4, KILL x5, KILL x6, KILL x7,
12767          KILL x8, KILL x9, KILL x10, KILL x11,
12768          KILL x12, KILL x13, KILL x14, KILL x15);
12769 
12770   format %{"LoadBarrierWeakSlowRegXmm $dst, $mem" %}
12771   ins_encode %{
12772 #if INCLUDE_ZGC
12773     Register d = $dst$$Register;
12774     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12775 
12776     assert(d != r12, "Can't be R12!");
12777     assert(d != r15, "Can't be R15!");
12778     assert(d != rsp, "Can't be RSP!");
12779 
12780     __ lea(d,$mem$$Address);
12781     __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12782 #else
12783     ShouldNotReachHere();
12784 #endif
12785   %}
12786   ins_pipe(pipe_slow);
12787 %}
12788 
12789 // For ZMM enabled processors
12790 instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12791                                    rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12792                                    rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12793                                    rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12794                                    rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12795                                    rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12796                                    rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12797                                    rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12798                                    rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12799 
12800   match(Set dst (LoadBarrierWeakSlowReg mem));
12801   predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12802 
12803   effect(DEF dst, KILL cr,
12804          KILL x0, KILL x1, KILL x2, KILL x3,
12805          KILL x4, KILL x5, KILL x6, KILL x7,
12806          KILL x8, KILL x9, KILL x10, KILL x11,
12807          KILL x12, KILL x13, KILL x14, KILL x15,
12808          KILL x16, KILL x17, KILL x18, KILL x19,
12809          KILL x20, KILL x21, KILL x22, KILL x23,
12810          KILL x24, KILL x25, KILL x26, KILL x27,
12811          KILL x28, KILL x29, KILL x30, KILL x31);
12812 
12813   format %{"LoadBarrierWeakSlowRegZmm $dst, $mem" %}
12814   ins_encode %{
12815 #if INCLUDE_ZGC
12816     Register d = $dst$$Register;
12817     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12818 
12819     assert(d != r12, "Can't be R12!");
12820     assert(d != r15, "Can't be R15!");
12821     assert(d != rsp, "Can't be RSP!");
12822 
12823     __ lea(d,$mem$$Address);
12824     __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12825 #else
12826     ShouldNotReachHere();
12827 #endif
12828   %}
12829   ins_pipe(pipe_slow);
12830 %}
12831 
12832 // ============================================================================
12833 // This name is KNOWN by the ADLC and cannot be changed.
12834 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12835 // for this guy.
12836 instruct tlsLoadP(r15_RegP dst) %{
12837   match(Set dst (ThreadLocal));
12838   effect(DEF dst);
12839 
12840   size(0);
12841   format %{ "# TLS is in R15" %}
12842   ins_encode( /*empty encoding*/ );
12843   ins_pipe(ialu_reg_reg);
12844 %}
12845 
12846 
12847 //----------PEEPHOLE RULES-----------------------------------------------------
12848 // These must follow all instruction definitions as they use the names
12849 // defined in the instructions definitions.
12850 //
12851 // peepmatch ( root_instr_name [preceding_instruction]* );
12852 //
12853 // peepconstraint %{
12854 // (instruction_number.operand_name relational_op instruction_number.operand_name
12855 //  [, ...] );
12856 // // instruction numbers are zero-based using left to right order in peepmatch
12857 //
12858 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
12859 // // provide an instruction_number.operand_name for each operand that appears
12860 // // in the replacement instruction's match rule
12861 //
12862 // ---------VM FLAGS---------------------------------------------------------
12863 //
12864 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12865 //
12866 // Each peephole rule is given an identifying number starting with zero and
12867 // increasing by one in the order seen by the parser.  An individual peephole
12868 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12869 // on the command-line.
12870 //
12871 // ---------CURRENT LIMITATIONS----------------------------------------------
12872 //
12873 // Only match adjacent instructions in same basic block
12874 // Only equality constraints
12875 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12876 // Only one replacement instruction
12877 //
12878 // ---------EXAMPLE----------------------------------------------------------
12879 //
12880 // // pertinent parts of existing instructions in architecture description
12881 // instruct movI(rRegI dst, rRegI src)
12882 // %{
12883 //   match(Set dst (CopyI src));
12884 // %}
12885 //
12886 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12887 // %{
12888 //   match(Set dst (AddI dst src));
12889 //   effect(KILL cr);
12890 // %}
12891 //
12892 // // Change (inc mov) to lea
12893 // peephole %{
12894 //   // increment preceeded by register-register move
12895 //   peepmatch ( incI_rReg movI );
12896 //   // require that the destination register of the increment
12897 //   // match the destination register of the move
12898 //   peepconstraint ( 0.dst == 1.dst );
12899 //   // construct a replacement instruction that sets
12900 //   // the destination to ( move's source register + one )
12901 //   peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12902 // %}
12903 //
12904 
12905 // Implementation no longer uses movX instructions since
12906 // machine-independent system no longer uses CopyX nodes.
12907 //
12908 // peephole
12909 // %{
12910 //   peepmatch (incI_rReg movI);
12911 //   peepconstraint (0.dst == 1.dst);
12912 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12913 // %}
12914 
12915 // peephole
12916 // %{
12917 //   peepmatch (decI_rReg movI);
12918 //   peepconstraint (0.dst == 1.dst);
12919 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12920 // %}
12921 
12922 // peephole
12923 // %{
12924 //   peepmatch (addI_rReg_imm movI);
12925 //   peepconstraint (0.dst == 1.dst);
12926 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12927 // %}
12928 
12929 // peephole
12930 // %{
12931 //   peepmatch (incL_rReg movL);
12932 //   peepconstraint (0.dst == 1.dst);
12933 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12934 // %}
12935 
12936 // peephole
12937 // %{
12938 //   peepmatch (decL_rReg movL);
12939 //   peepconstraint (0.dst == 1.dst);
12940 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12941 // %}
12942 
12943 // peephole
12944 // %{
12945 //   peepmatch (addL_rReg_imm movL);
12946 //   peepconstraint (0.dst == 1.dst);
12947 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12948 // %}
12949 
12950 // peephole
12951 // %{
12952 //   peepmatch (addP_rReg_imm movP);
12953 //   peepconstraint (0.dst == 1.dst);
12954 //   peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12955 // %}
12956 
12957 // // Change load of spilled value to only a spill
12958 // instruct storeI(memory mem, rRegI src)
12959 // %{
12960 //   match(Set mem (StoreI mem src));
12961 // %}
12962 //
12963 // instruct loadI(rRegI dst, memory mem)
12964 // %{
12965 //   match(Set dst (LoadI mem));
12966 // %}
12967 //
12968 
12969 peephole
12970 %{
12971   peepmatch (loadI storeI);
12972   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12973   peepreplace (storeI(1.mem 1.mem 1.src));
12974 %}
12975 
12976 peephole
12977 %{
12978   peepmatch (loadL storeL);
12979   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12980   peepreplace (storeL(1.mem 1.mem 1.src));
12981 %}
12982 
12983 //----------SMARTSPILL RULES---------------------------------------------------
12984 // These must follow all instruction definitions as they use the names
12985 // defined in the instructions definitions.