1 //
   2 // Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
   6 // under the terms of the GNU General Public License version 2 only, as
   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
  17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // AMD64 Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 
  32 register %{
  33 //----------Architecture Description Register Definitions----------------------
  34 // General Registers
  35 // "reg_def"  name ( register save type, C convention save type,
  36 //                   ideal register type, encoding );
  37 // Register Save Types:
  38 //
  39 // NS  = No-Save:       The register allocator assumes that these registers
  40 //                      can be used without saving upon entry to the method, &
  41 //                      that they do not need to be saved at call sites.
  42 //
  43 // SOC = Save-On-Call:  The register allocator assumes that these registers
  44 //                      can be used without saving upon entry to the method,
  45 //                      but that they must be saved at call sites.
  46 //
  47 // SOE = Save-On-Entry: The register allocator assumes that these registers
  48 //                      must be saved before using them upon entry to the
  49 //                      method, but they do not need to be saved at call
  50 //                      sites.
  51 //
  52 // AS  = Always-Save:   The register allocator assumes that these registers
  53 //                      must be saved before using them upon entry to the
  54 //                      method, & that they must be saved at call sites.
  55 //
  56 // Ideal Register Type is used to determine how to save & restore a
  57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  59 //
  60 // The encoding number is the actual bit-pattern placed into the opcodes.
  61 
  62 // General Registers
  63 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when
  64 // used as byte registers)
  65 
  66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
  67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
  68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
  69 
  70 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
  71 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
  72 
  73 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
  74 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
  75 
  76 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
  77 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
  78 
  79 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
  80 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
  81 
  82 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
  83 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
  84 
  85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
  86 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
  87 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
  88 
  89 #ifdef _WIN64
  90 
  91 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
  92 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
  93 
  94 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
  95 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
  96 
  97 #else
  98 
  99 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
 100 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
 101 
 102 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
 103 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
 104 
 105 #endif
 106 
 107 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
 108 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
 109 
 110 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
 111 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
 112 
 113 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
 115 
 116 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
 118 
 119 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
 121 
 122 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
 124 
 125 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
 127 
 128 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
 130 
 131 
 132 // Floating Point Registers
 133 
 134 // Specify priority of register selection within phases of register
 135 // allocation.  Highest priority is first.  A useful heuristic is to
 136 // give registers a low priority when they are required by machine
 137 // instructions, like EAX and EDX on I486, and choose no-save registers
 138 // before save-on-call, & save-on-call before save-on-entry.  Registers
 139 // which participate in fixed calling sequences should come last.
 140 // Registers which are used as pairs must fall on an even boundary.
 141 
 142 alloc_class chunk0(R10,         R10_H,
 143                    R11,         R11_H,
 144                    R8,          R8_H,
 145                    R9,          R9_H,
 146                    R12,         R12_H,
 147                    RCX,         RCX_H,
 148                    RBX,         RBX_H,
 149                    RDI,         RDI_H,
 150                    RDX,         RDX_H,
 151                    RSI,         RSI_H,
 152                    RAX,         RAX_H,
 153                    RBP,         RBP_H,
 154                    R13,         R13_H,
 155                    R14,         R14_H,
 156                    R15,         R15_H,
 157                    RSP,         RSP_H);
 158 
 159 
 160 //----------Architecture Description Register Classes--------------------------
 161 // Several register classes are automatically defined based upon information in
 162 // this architecture description.
 163 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
 164 // 2) reg_class compiler_method_oop_reg    ( /* as def'd in frame section */ )
 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 167 //
 168 
 169 // Empty register class.
 170 reg_class no_reg();
 171 
 172 // Class for all pointer registers (including RSP and RBP)
 173 reg_class any_reg_with_rbp(RAX, RAX_H,
 174                            RDX, RDX_H,
 175                            RBP, RBP_H,
 176                            RDI, RDI_H,
 177                            RSI, RSI_H,
 178                            RCX, RCX_H,
 179                            RBX, RBX_H,
 180                            RSP, RSP_H,
 181                            R8,  R8_H,
 182                            R9,  R9_H,
 183                            R10, R10_H,
 184                            R11, R11_H,
 185                            R12, R12_H,
 186                            R13, R13_H,
 187                            R14, R14_H,
 188                            R15, R15_H);
 189 
 190 // Class for all pointer registers (including RSP, but excluding RBP)
 191 reg_class any_reg_no_rbp(RAX, RAX_H,
 192                          RDX, RDX_H,
 193                          RDI, RDI_H,
 194                          RSI, RSI_H,
 195                          RCX, RCX_H,
 196                          RBX, RBX_H,
 197                          RSP, RSP_H,
 198                          R8,  R8_H,
 199                          R9,  R9_H,
 200                          R10, R10_H,
 201                          R11, R11_H,
 202                          R12, R12_H,
 203                          R13, R13_H,
 204                          R14, R14_H,
 205                          R15, R15_H);
 206 
 207 // Dynamic register class that selects at runtime between register classes
 208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
 209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
 210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
 211 
 212 // Class for all pointer registers (excluding RSP)
 213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
 214                            RDX, RDX_H,
 215                            RBP, RBP_H,
 216                            RDI, RDI_H,
 217                            RSI, RSI_H,
 218                            RCX, RCX_H,
 219                            RBX, RBX_H,
 220                            R8,  R8_H,
 221                            R9,  R9_H,
 222                            R10, R10_H,
 223                            R11, R11_H,
 224                            R13, R13_H,
 225                            R14, R14_H);
 226 
 227 // Class for all pointer registers (excluding RSP and RBP)
 228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
 229                          RDX, RDX_H,
 230                          RDI, RDI_H,
 231                          RSI, RSI_H,
 232                          RCX, RCX_H,
 233                          RBX, RBX_H,
 234                          R8,  R8_H,
 235                          R9,  R9_H,
 236                          R10, R10_H,
 237                          R11, R11_H,
 238                          R13, R13_H,
 239                          R14, R14_H);
 240 
 241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
 242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
 243 
 244 // Class for all pointer registers (excluding RAX and RSP)
 245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
 246                                   RBP, RBP_H,
 247                                   RDI, RDI_H,
 248                                   RSI, RSI_H,
 249                                   RCX, RCX_H,
 250                                   RBX, RBX_H,
 251                                   R8,  R8_H,
 252                                   R9,  R9_H,
 253                                   R10, R10_H,
 254                                   R11, R11_H,
 255                                   R13, R13_H,
 256                                   R14, R14_H);
 257 
 258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
 259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
 260                                 RDI, RDI_H,
 261                                 RSI, RSI_H,
 262                                 RCX, RCX_H,
 263                                 RBX, RBX_H,
 264                                 R8,  R8_H,
 265                                 R9,  R9_H,
 266                                 R10, R10_H,
 267                                 R11, R11_H,
 268                                 R13, R13_H,
 269                                 R14, R14_H);
 270 
 271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
 272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
 273 
 274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
 275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
 276                                       RBP, RBP_H,
 277                                       RDI, RDI_H,
 278                                       RSI, RSI_H,
 279                                       RCX, RCX_H,
 280                                       R8,  R8_H,
 281                                       R9,  R9_H,
 282                                       R10, R10_H,
 283                                       R11, R11_H,
 284                                       R13, R13_H,
 285                                       R14, R14_H);
 286 
 287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
 288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
 289                                     RDI, RDI_H,
 290                                     RSI, RSI_H,
 291                                     RCX, RCX_H,
 292                                     R8,  R8_H,
 293                                     R9,  R9_H,
 294                                     R10, R10_H,
 295                                     R11, R11_H,
 296                                     R13, R13_H,
 297                                     R14, R14_H);
 298 
 299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
 300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
 301 
 302 // Singleton class for RAX pointer register
 303 reg_class ptr_rax_reg(RAX, RAX_H);
 304 
 305 // Singleton class for RBX pointer register
 306 reg_class ptr_rbx_reg(RBX, RBX_H);
 307 
 308 // Singleton class for RSI pointer register
 309 reg_class ptr_rsi_reg(RSI, RSI_H);
 310 
 311 // Singleton class for RDI pointer register
 312 reg_class ptr_rdi_reg(RDI, RDI_H);
 313 
 314 // Singleton class for stack pointer
 315 reg_class ptr_rsp_reg(RSP, RSP_H);
 316 
 317 // Singleton class for TLS pointer
 318 reg_class ptr_r15_reg(R15, R15_H);
 319 
 320 // The registers which can be used for
 321 // a thread local safepoint poll
 322 // * R12 is reserved for heap base
 323 // * R13 cannot be encoded for addressing without an offset byte
 324 // * R15 is reserved for the JavaThread
 325 reg_class ptr_rex_reg(R8,  R8_H,
 326                       R9,  R9_H,
 327                       R10, R10_H,
 328                       R11, R11_H,
 329                       R14, R14_H);
 330 
 331 
 332 // Class for all long registers (excluding RSP)
 333 reg_class long_reg_with_rbp(RAX, RAX_H,
 334                             RDX, RDX_H,
 335                             RBP, RBP_H,
 336                             RDI, RDI_H,
 337                             RSI, RSI_H,
 338                             RCX, RCX_H,
 339                             RBX, RBX_H,
 340                             R8,  R8_H,
 341                             R9,  R9_H,
 342                             R10, R10_H,
 343                             R11, R11_H,
 344                             R13, R13_H,
 345                             R14, R14_H);
 346 
 347 // Class for all long registers (excluding RSP and RBP)
 348 reg_class long_reg_no_rbp(RAX, RAX_H,
 349                           RDX, RDX_H,
 350                           RDI, RDI_H,
 351                           RSI, RSI_H,
 352                           RCX, RCX_H,
 353                           RBX, RBX_H,
 354                           R8,  R8_H,
 355                           R9,  R9_H,
 356                           R10, R10_H,
 357                           R11, R11_H,
 358                           R13, R13_H,
 359                           R14, R14_H);
 360 
 361 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
 362 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
 363 
 364 // Class for all long registers (excluding RAX, RDX and RSP)
 365 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
 366                                        RDI, RDI_H,
 367                                        RSI, RSI_H,
 368                                        RCX, RCX_H,
 369                                        RBX, RBX_H,
 370                                        R8,  R8_H,
 371                                        R9,  R9_H,
 372                                        R10, R10_H,
 373                                        R11, R11_H,
 374                                        R13, R13_H,
 375                                        R14, R14_H);
 376 
 377 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
 378 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
 379                                      RSI, RSI_H,
 380                                      RCX, RCX_H,
 381                                      RBX, RBX_H,
 382                                      R8,  R8_H,
 383                                      R9,  R9_H,
 384                                      R10, R10_H,
 385                                      R11, R11_H,
 386                                      R13, R13_H,
 387                                      R14, R14_H);
 388 
 389 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
 390 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
 391 
 392 // Class for all long registers (excluding RCX and RSP)
 393 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
 394                                    RDI, RDI_H,
 395                                    RSI, RSI_H,
 396                                    RAX, RAX_H,
 397                                    RDX, RDX_H,
 398                                    RBX, RBX_H,
 399                                    R8,  R8_H,
 400                                    R9,  R9_H,
 401                                    R10, R10_H,
 402                                    R11, R11_H,
 403                                    R13, R13_H,
 404                                    R14, R14_H);
 405 
 406 // Class for all long registers (excluding RCX, RSP, and RBP)
 407 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
 408                                  RSI, RSI_H,
 409                                  RAX, RAX_H,
 410                                  RDX, RDX_H,
 411                                  RBX, RBX_H,
 412                                  R8,  R8_H,
 413                                  R9,  R9_H,
 414                                  R10, R10_H,
 415                                  R11, R11_H,
 416                                  R13, R13_H,
 417                                  R14, R14_H);
 418 
 419 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
 420 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
 421 
 422 // Singleton class for RAX long register
 423 reg_class long_rax_reg(RAX, RAX_H);
 424 
 425 // Singleton class for RCX long register
 426 reg_class long_rcx_reg(RCX, RCX_H);
 427 
 428 // Singleton class for RDX long register
 429 reg_class long_rdx_reg(RDX, RDX_H);
 430 
 431 // Class for all int registers (excluding RSP)
 432 reg_class int_reg_with_rbp(RAX,
 433                            RDX,
 434                            RBP,
 435                            RDI,
 436                            RSI,
 437                            RCX,
 438                            RBX,
 439                            R8,
 440                            R9,
 441                            R10,
 442                            R11,
 443                            R13,
 444                            R14);
 445 
 446 // Class for all int registers (excluding RSP and RBP)
 447 reg_class int_reg_no_rbp(RAX,
 448                          RDX,
 449                          RDI,
 450                          RSI,
 451                          RCX,
 452                          RBX,
 453                          R8,
 454                          R9,
 455                          R10,
 456                          R11,
 457                          R13,
 458                          R14);
 459 
 460 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
 461 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
 462 
 463 // Class for all int registers (excluding RCX and RSP)
 464 reg_class int_no_rcx_reg_with_rbp(RAX,
 465                                   RDX,
 466                                   RBP,
 467                                   RDI,
 468                                   RSI,
 469                                   RBX,
 470                                   R8,
 471                                   R9,
 472                                   R10,
 473                                   R11,
 474                                   R13,
 475                                   R14);
 476 
 477 // Class for all int registers (excluding RCX, RSP, and RBP)
 478 reg_class int_no_rcx_reg_no_rbp(RAX,
 479                                 RDX,
 480                                 RDI,
 481                                 RSI,
 482                                 RBX,
 483                                 R8,
 484                                 R9,
 485                                 R10,
 486                                 R11,
 487                                 R13,
 488                                 R14);
 489 
 490 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
 491 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
 492 
 493 // Class for all int registers (excluding RAX, RDX, and RSP)
 494 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
 495                                       RDI,
 496                                       RSI,
 497                                       RCX,
 498                                       RBX,
 499                                       R8,
 500                                       R9,
 501                                       R10,
 502                                       R11,
 503                                       R13,
 504                                       R14);
 505 
 506 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
 507 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
 508                                     RSI,
 509                                     RCX,
 510                                     RBX,
 511                                     R8,
 512                                     R9,
 513                                     R10,
 514                                     R11,
 515                                     R13,
 516                                     R14);
 517 
 518 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
 519 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
 520 
 521 // Singleton class for RAX int register
 522 reg_class int_rax_reg(RAX);
 523 
 524 // Singleton class for RBX int register
 525 reg_class int_rbx_reg(RBX);
 526 
 527 // Singleton class for RCX int register
 528 reg_class int_rcx_reg(RCX);
 529 
 530 // Singleton class for RCX int register
 531 reg_class int_rdx_reg(RDX);
 532 
 533 // Singleton class for RCX int register
 534 reg_class int_rdi_reg(RDI);
 535 
 536 // Singleton class for instruction pointer
 537 // reg_class ip_reg(RIP);
 538 
 539 %}
 540 
 541 source_hpp %{
 542 #if INCLUDE_ZGC
 543 #include "gc/z/zBarrierSetAssembler.hpp"
 544 #endif
 545 #if INCLUDE_SHENANDOAHGC
 546 #include "gc/shenandoah/shenandoahBrooksPointer.hpp"
 547 #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp"
 548 #else
 549 // This is normally available through shenandoah_globals.hpp, but if Shenandoah
 550 // compilation is disabled, there is no such header. Fake the constants for predicates
 551 // to work. This workaround would be removed as we backport more stuff, including
 552 // the split shenandoah_x86_64.ad.
 553 #define ShenandoahCASBarrier false
 554 #endif
 555 %}
 556 
 557 //----------SOURCE BLOCK-------------------------------------------------------
 558 // This is a block of C++ code which provides values, functions, and
 559 // definitions necessary in the rest of the architecture description
 560 source %{
 561 #define   RELOC_IMM64    Assembler::imm_operand
 562 #define   RELOC_DISP32   Assembler::disp32_operand
 563 
 564 #define __ _masm.
 565 
 566 static bool generate_vzeroupper(Compile* C) {
 567   return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false;  // Generate vzeroupper
 568 }
 569 
 570 static int clear_avx_size() {
 571   return generate_vzeroupper(Compile::current()) ? 3: 0;  // vzeroupper
 572 }
 573 
 574 // !!!!! Special hack to get all types of calls to specify the byte offset
 575 //       from the start of the call to the point where the return address
 576 //       will point.
 577 int MachCallStaticJavaNode::ret_addr_offset()
 578 {
 579   int offset = 5; // 5 bytes from start of call to where return address points
 580   offset += clear_avx_size();
 581   return offset;
 582 }
 583 
 584 int MachCallDynamicJavaNode::ret_addr_offset()
 585 {
 586   int offset = 15; // 15 bytes from start of call to where return address points
 587   offset += clear_avx_size();
 588   return offset;
 589 }
 590 
 591 int MachCallRuntimeNode::ret_addr_offset() {
 592   int offset = 13; // movq r10,#addr; callq (r10)
 593   offset += clear_avx_size();
 594   return offset;
 595 }
 596 
 597 // Indicate if the safepoint node needs the polling page as an input,
 598 // it does if the polling page is more than disp32 away.
 599 bool SafePointNode::needs_polling_address_input()
 600 {
 601   return SafepointMechanism::uses_thread_local_poll() || Assembler::is_polling_page_far();
 602 }
 603 
 604 //
 605 // Compute padding required for nodes which need alignment
 606 //
 607 
 608 // The address of the call instruction needs to be 4-byte aligned to
 609 // ensure that it does not span a cache line so that it can be patched.
 610 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
 611 {
 612   current_offset += clear_avx_size(); // skip vzeroupper
 613   current_offset += 1; // skip call opcode byte
 614   return align_up(current_offset, alignment_required()) - current_offset;
 615 }
 616 
 617 // The address of the call instruction needs to be 4-byte aligned to
 618 // ensure that it does not span a cache line so that it can be patched.
 619 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
 620 {
 621   current_offset += clear_avx_size(); // skip vzeroupper
 622   current_offset += 11; // skip movq instruction + call opcode byte
 623   return align_up(current_offset, alignment_required()) - current_offset;
 624 }
 625 
 626 // EMIT_RM()
 627 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
 628   unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
 629   cbuf.insts()->emit_int8(c);
 630 }
 631 
 632 // EMIT_CC()
 633 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
 634   unsigned char c = (unsigned char) (f1 | f2);
 635   cbuf.insts()->emit_int8(c);
 636 }
 637 
 638 // EMIT_OPCODE()
 639 void emit_opcode(CodeBuffer &cbuf, int code) {
 640   cbuf.insts()->emit_int8((unsigned char) code);
 641 }
 642 
 643 // EMIT_OPCODE() w/ relocation information
 644 void emit_opcode(CodeBuffer &cbuf,
 645                  int code, relocInfo::relocType reloc, int offset, int format)
 646 {
 647   cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
 648   emit_opcode(cbuf, code);
 649 }
 650 
 651 // EMIT_D8()
 652 void emit_d8(CodeBuffer &cbuf, int d8) {
 653   cbuf.insts()->emit_int8((unsigned char) d8);
 654 }
 655 
 656 // EMIT_D16()
 657 void emit_d16(CodeBuffer &cbuf, int d16) {
 658   cbuf.insts()->emit_int16(d16);
 659 }
 660 
 661 // EMIT_D32()
 662 void emit_d32(CodeBuffer &cbuf, int d32) {
 663   cbuf.insts()->emit_int32(d32);
 664 }
 665 
 666 // EMIT_D64()
 667 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
 668   cbuf.insts()->emit_int64(d64);
 669 }
 670 
 671 // emit 32 bit value and construct relocation entry from relocInfo::relocType
 672 void emit_d32_reloc(CodeBuffer& cbuf,
 673                     int d32,
 674                     relocInfo::relocType reloc,
 675                     int format)
 676 {
 677   assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
 678   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 679   cbuf.insts()->emit_int32(d32);
 680 }
 681 
 682 // emit 32 bit value and construct relocation entry from RelocationHolder
 683 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
 684 #ifdef ASSERT
 685   if (rspec.reloc()->type() == relocInfo::oop_type &&
 686       d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
 687     assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
 688     assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop((intptr_t)d32))), "cannot embed scavengable oops in code");
 689   }
 690 #endif
 691   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 692   cbuf.insts()->emit_int32(d32);
 693 }
 694 
 695 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
 696   address next_ip = cbuf.insts_end() + 4;
 697   emit_d32_reloc(cbuf, (int) (addr - next_ip),
 698                  external_word_Relocation::spec(addr),
 699                  RELOC_DISP32);
 700 }
 701 
 702 
 703 // emit 64 bit value and construct relocation entry from relocInfo::relocType
 704 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
 705   cbuf.relocate(cbuf.insts_mark(), reloc, format);
 706   cbuf.insts()->emit_int64(d64);
 707 }
 708 
 709 // emit 64 bit value and construct relocation entry from RelocationHolder
 710 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
 711 #ifdef ASSERT
 712   if (rspec.reloc()->type() == relocInfo::oop_type &&
 713       d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
 714     assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
 715     assert(oopDesc::is_oop(cast_to_oop(d64)) && (ScavengeRootsInCode || !Universe::heap()->is_scavengable(cast_to_oop(d64))),
 716            "cannot embed scavengable oops in code");
 717   }
 718 #endif
 719   cbuf.relocate(cbuf.insts_mark(), rspec, format);
 720   cbuf.insts()->emit_int64(d64);
 721 }
 722 
 723 // Access stack slot for load or store
 724 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
 725 {
 726   emit_opcode(cbuf, opcode);                  // (e.g., FILD   [RSP+src])
 727   if (-0x80 <= disp && disp < 0x80) {
 728     emit_rm(cbuf, 0x01, rm_field, RSP_enc);   // R/M byte
 729     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
 730     emit_d8(cbuf, disp);     // Displacement  // R/M byte
 731   } else {
 732     emit_rm(cbuf, 0x02, rm_field, RSP_enc);   // R/M byte
 733     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
 734     emit_d32(cbuf, disp);     // Displacement // R/M byte
 735   }
 736 }
 737 
 738    // rRegI ereg, memory mem) %{    // emit_reg_mem
 739 void encode_RegMem(CodeBuffer &cbuf,
 740                    int reg,
 741                    int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
 742 {
 743   assert(disp_reloc == relocInfo::none, "cannot have disp");
 744   int regenc = reg & 7;
 745   int baseenc = base & 7;
 746   int indexenc = index & 7;
 747 
 748   // There is no index & no scale, use form without SIB byte
 749   if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
 750     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
 751     if (disp == 0 && base != RBP_enc && base != R13_enc) {
 752       emit_rm(cbuf, 0x0, regenc, baseenc); // *
 753     } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
 754       // If 8-bit displacement, mode 0x1
 755       emit_rm(cbuf, 0x1, regenc, baseenc); // *
 756       emit_d8(cbuf, disp);
 757     } else {
 758       // If 32-bit displacement
 759       if (base == -1) { // Special flag for absolute address
 760         emit_rm(cbuf, 0x0, regenc, 0x5); // *
 761         if (disp_reloc != relocInfo::none) {
 762           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 763         } else {
 764           emit_d32(cbuf, disp);
 765         }
 766       } else {
 767         // Normal base + offset
 768         emit_rm(cbuf, 0x2, regenc, baseenc); // *
 769         if (disp_reloc != relocInfo::none) {
 770           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 771         } else {
 772           emit_d32(cbuf, disp);
 773         }
 774       }
 775     }
 776   } else {
 777     // Else, encode with the SIB byte
 778     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
 779     if (disp == 0 && base != RBP_enc && base != R13_enc) {
 780       // If no displacement
 781       emit_rm(cbuf, 0x0, regenc, 0x4); // *
 782       emit_rm(cbuf, scale, indexenc, baseenc);
 783     } else {
 784       if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
 785         // If 8-bit displacement, mode 0x1
 786         emit_rm(cbuf, 0x1, regenc, 0x4); // *
 787         emit_rm(cbuf, scale, indexenc, baseenc);
 788         emit_d8(cbuf, disp);
 789       } else {
 790         // If 32-bit displacement
 791         if (base == 0x04 ) {
 792           emit_rm(cbuf, 0x2, regenc, 0x4);
 793           emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
 794         } else {
 795           emit_rm(cbuf, 0x2, regenc, 0x4);
 796           emit_rm(cbuf, scale, indexenc, baseenc); // *
 797         }
 798         if (disp_reloc != relocInfo::none) {
 799           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
 800         } else {
 801           emit_d32(cbuf, disp);
 802         }
 803       }
 804     }
 805   }
 806 }
 807 
 808 // This could be in MacroAssembler but it's fairly C2 specific
 809 void emit_cmpfp_fixup(MacroAssembler& _masm) {
 810   Label exit;
 811   __ jccb(Assembler::noParity, exit);
 812   __ pushf();
 813   //
 814   // comiss/ucomiss instructions set ZF,PF,CF flags and
 815   // zero OF,AF,SF for NaN values.
 816   // Fixup flags by zeroing ZF,PF so that compare of NaN
 817   // values returns 'less than' result (CF is set).
 818   // Leave the rest of flags unchanged.
 819   //
 820   //    7 6 5 4 3 2 1 0
 821   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
 822   //    0 0 1 0 1 0 1 1   (0x2B)
 823   //
 824   __ andq(Address(rsp, 0), 0xffffff2b);
 825   __ popf();
 826   __ bind(exit);
 827 }
 828 
 829 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
 830   Label done;
 831   __ movl(dst, -1);
 832   __ jcc(Assembler::parity, done);
 833   __ jcc(Assembler::below, done);
 834   __ setb(Assembler::notEqual, dst);
 835   __ movzbl(dst, dst);
 836   __ bind(done);
 837 }
 838 
 839 
 840 //=============================================================================
 841 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 842 
 843 int Compile::ConstantTable::calculate_table_base_offset() const {
 844   return 0;  // absolute addressing, no offset
 845 }
 846 
 847 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 848 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 849   ShouldNotReachHere();
 850 }
 851 
 852 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 853   // Empty encoding
 854 }
 855 
 856 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 857   return 0;
 858 }
 859 
 860 #ifndef PRODUCT
 861 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 862   st->print("# MachConstantBaseNode (empty encoding)");
 863 }
 864 #endif
 865 
 866 
 867 //=============================================================================
 868 #ifndef PRODUCT
 869 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 870   Compile* C = ra_->C;
 871 
 872   int framesize = C->frame_size_in_bytes();
 873   int bangsize = C->bang_size_in_bytes();
 874   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 875   // Remove wordSize for return addr which is already pushed.
 876   framesize -= wordSize;
 877 
 878   if (C->need_stack_bang(bangsize)) {
 879     framesize -= wordSize;
 880     st->print("# stack bang (%d bytes)", bangsize);
 881     st->print("\n\t");
 882     st->print("pushq   rbp\t# Save rbp");
 883     if (PreserveFramePointer) {
 884         st->print("\n\t");
 885         st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
 886     }
 887     if (framesize) {
 888       st->print("\n\t");
 889       st->print("subq    rsp, #%d\t# Create frame",framesize);
 890     }
 891   } else {
 892     st->print("subq    rsp, #%d\t# Create frame",framesize);
 893     st->print("\n\t");
 894     framesize -= wordSize;
 895     st->print("movq    [rsp + #%d], rbp\t# Save rbp",framesize);
 896     if (PreserveFramePointer) {
 897       st->print("\n\t");
 898       st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
 899       if (framesize > 0) {
 900         st->print("\n\t");
 901         st->print("addq    rbp, #%d", framesize);
 902       }
 903     }
 904   }
 905 
 906   if (VerifyStackAtCalls) {
 907     st->print("\n\t");
 908     framesize -= wordSize;
 909     st->print("movq    [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
 910 #ifdef ASSERT
 911     st->print("\n\t");
 912     st->print("# stack alignment check");
 913 #endif
 914   }
 915   st->cr();
 916 }
 917 #endif
 918 
 919 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 920   Compile* C = ra_->C;
 921   MacroAssembler _masm(&cbuf);
 922 
 923   int framesize = C->frame_size_in_bytes();
 924   int bangsize = C->bang_size_in_bytes();
 925 
 926   __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
 927 
 928   C->set_frame_complete(cbuf.insts_size());
 929 
 930   if (C->has_mach_constant_base_node()) {
 931     // NOTE: We set the table base offset here because users might be
 932     // emitted before MachConstantBaseNode.
 933     Compile::ConstantTable& constant_table = C->constant_table();
 934     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 935   }
 936 }
 937 
 938 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
 939 {
 940   return MachNode::size(ra_); // too many variables; just compute it
 941                               // the hard way
 942 }
 943 
 944 int MachPrologNode::reloc() const
 945 {
 946   return 0; // a large enough number
 947 }
 948 
 949 //=============================================================================
 950 #ifndef PRODUCT
 951 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 952 {
 953   Compile* C = ra_->C;
 954   if (generate_vzeroupper(C)) {
 955     st->print("vzeroupper");
 956     st->cr(); st->print("\t");
 957   }
 958 
 959   int framesize = C->frame_size_in_bytes();
 960   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 961   // Remove word for return adr already pushed
 962   // and RBP
 963   framesize -= 2*wordSize;
 964 
 965   if (framesize) {
 966     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);
 967     st->print("\t");
 968   }
 969 
 970   st->print_cr("popq   rbp");
 971   if (do_polling() && C->is_method_compilation()) {
 972     st->print("\t");
 973     if (SafepointMechanism::uses_thread_local_poll()) {
 974       st->print_cr("movq   rscratch1, poll_offset[r15_thread] #polling_page_address\n\t"
 975                    "testl  rax, [rscratch1]\t"
 976                    "# Safepoint: poll for GC");
 977     } else if (Assembler::is_polling_page_far()) {
 978       st->print_cr("movq   rscratch1, #polling_page_address\n\t"
 979                    "testl  rax, [rscratch1]\t"
 980                    "# Safepoint: poll for GC");
 981     } else {
 982       st->print_cr("testl  rax, [rip + #offset_to_poll_page]\t"
 983                    "# Safepoint: poll for GC");
 984     }
 985   }
 986 }
 987 #endif
 988 
 989 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 990 {
 991   Compile* C = ra_->C;
 992   MacroAssembler _masm(&cbuf);
 993 
 994   if (generate_vzeroupper(C)) {
 995     // Clear upper bits of YMM registers when current compiled code uses
 996     // wide vectors to avoid AVX <-> SSE transition penalty during call.
 997     __ vzeroupper();
 998   }
 999 
1000   int framesize = C->frame_size_in_bytes();
1001   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1002   // Remove word for return adr already pushed
1003   // and RBP
1004   framesize -= 2*wordSize;
1005 
1006   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1007 
1008   if (framesize) {
1009     emit_opcode(cbuf, Assembler::REX_W);
1010     if (framesize < 0x80) {
1011       emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1012       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1013       emit_d8(cbuf, framesize);
1014     } else {
1015       emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1016       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1017       emit_d32(cbuf, framesize);
1018     }
1019   }
1020 
1021   // popq rbp
1022   emit_opcode(cbuf, 0x58 | RBP_enc);
1023 
1024   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1025     __ reserved_stack_check();
1026   }
1027 
1028   if (do_polling() && C->is_method_compilation()) {
1029     MacroAssembler _masm(&cbuf);
1030     if (SafepointMechanism::uses_thread_local_poll()) {
1031       __ movq(rscratch1, Address(r15_thread, Thread::polling_page_offset()));
1032       __ relocate(relocInfo::poll_return_type);
1033       __ testl(rax, Address(rscratch1, 0));
1034     } else {
1035       AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
1036       if (Assembler::is_polling_page_far()) {
1037         __ lea(rscratch1, polling_page);
1038         __ relocate(relocInfo::poll_return_type);
1039         __ testl(rax, Address(rscratch1, 0));
1040       } else {
1041         __ testl(rax, polling_page);
1042       }
1043     }
1044   }
1045 }
1046 
1047 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1048 {
1049   return MachNode::size(ra_); // too many variables; just compute it
1050                               // the hard way
1051 }
1052 
1053 int MachEpilogNode::reloc() const
1054 {
1055   return 2; // a large enough number
1056 }
1057 
1058 const Pipeline* MachEpilogNode::pipeline() const
1059 {
1060   return MachNode::pipeline_class();
1061 }
1062 
1063 int MachEpilogNode::safepoint_offset() const
1064 {
1065   return 0;
1066 }
1067 
1068 //=============================================================================
1069 
1070 enum RC {
1071   rc_bad,
1072   rc_int,
1073   rc_float,
1074   rc_stack
1075 };
1076 
1077 static enum RC rc_class(OptoReg::Name reg)
1078 {
1079   if( !OptoReg::is_valid(reg)  ) return rc_bad;
1080 
1081   if (OptoReg::is_stack(reg)) return rc_stack;
1082 
1083   VMReg r = OptoReg::as_VMReg(reg);
1084 
1085   if (r->is_Register()) return rc_int;
1086 
1087   assert(r->is_XMMRegister(), "must be");
1088   return rc_float;
1089 }
1090 
1091 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1092 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1093                           int src_hi, int dst_hi, uint ireg, outputStream* st);
1094 
1095 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1096                             int stack_offset, int reg, uint ireg, outputStream* st);
1097 
1098 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1099                                       int dst_offset, uint ireg, outputStream* st) {
1100   if (cbuf) {
1101     MacroAssembler _masm(cbuf);
1102     switch (ireg) {
1103     case Op_VecS:
1104       __ movq(Address(rsp, -8), rax);
1105       __ movl(rax, Address(rsp, src_offset));
1106       __ movl(Address(rsp, dst_offset), rax);
1107       __ movq(rax, Address(rsp, -8));
1108       break;
1109     case Op_VecD:
1110       __ pushq(Address(rsp, src_offset));
1111       __ popq (Address(rsp, dst_offset));
1112       break;
1113     case Op_VecX:
1114       __ pushq(Address(rsp, src_offset));
1115       __ popq (Address(rsp, dst_offset));
1116       __ pushq(Address(rsp, src_offset+8));
1117       __ popq (Address(rsp, dst_offset+8));
1118       break;
1119     case Op_VecY:
1120       __ vmovdqu(Address(rsp, -32), xmm0);
1121       __ vmovdqu(xmm0, Address(rsp, src_offset));
1122       __ vmovdqu(Address(rsp, dst_offset), xmm0);
1123       __ vmovdqu(xmm0, Address(rsp, -32));
1124       break;
1125     case Op_VecZ:
1126       __ evmovdquq(Address(rsp, -64), xmm0, 2);
1127       __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1128       __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1129       __ evmovdquq(xmm0, Address(rsp, -64), 2);
1130       break;
1131     default:
1132       ShouldNotReachHere();
1133     }
1134 #ifndef PRODUCT
1135   } else {
1136     switch (ireg) {
1137     case Op_VecS:
1138       st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1139                 "movl    rax, [rsp + #%d]\n\t"
1140                 "movl    [rsp + #%d], rax\n\t"
1141                 "movq    rax, [rsp - #8]",
1142                 src_offset, dst_offset);
1143       break;
1144     case Op_VecD:
1145       st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1146                 "popq    [rsp + #%d]",
1147                 src_offset, dst_offset);
1148       break;
1149      case Op_VecX:
1150       st->print("pushq   [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1151                 "popq    [rsp + #%d]\n\t"
1152                 "pushq   [rsp + #%d]\n\t"
1153                 "popq    [rsp + #%d]",
1154                 src_offset, dst_offset, src_offset+8, dst_offset+8);
1155       break;
1156     case Op_VecY:
1157       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1158                 "vmovdqu xmm0, [rsp + #%d]\n\t"
1159                 "vmovdqu [rsp + #%d], xmm0\n\t"
1160                 "vmovdqu xmm0, [rsp - #32]",
1161                 src_offset, dst_offset);
1162       break;
1163     case Op_VecZ:
1164       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1165                 "vmovdqu xmm0, [rsp + #%d]\n\t"
1166                 "vmovdqu [rsp + #%d], xmm0\n\t"
1167                 "vmovdqu xmm0, [rsp - #64]",
1168                 src_offset, dst_offset);
1169       break;
1170     default:
1171       ShouldNotReachHere();
1172     }
1173 #endif
1174   }
1175 }
1176 
1177 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1178                                        PhaseRegAlloc* ra_,
1179                                        bool do_size,
1180                                        outputStream* st) const {
1181   assert(cbuf != NULL || st  != NULL, "sanity");
1182   // Get registers to move
1183   OptoReg::Name src_second = ra_->get_reg_second(in(1));
1184   OptoReg::Name src_first = ra_->get_reg_first(in(1));
1185   OptoReg::Name dst_second = ra_->get_reg_second(this);
1186   OptoReg::Name dst_first = ra_->get_reg_first(this);
1187 
1188   enum RC src_second_rc = rc_class(src_second);
1189   enum RC src_first_rc = rc_class(src_first);
1190   enum RC dst_second_rc = rc_class(dst_second);
1191   enum RC dst_first_rc = rc_class(dst_first);
1192 
1193   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1194          "must move at least 1 register" );
1195 
1196   if (src_first == dst_first && src_second == dst_second) {
1197     // Self copy, no move
1198     return 0;
1199   }
1200   if (bottom_type()->isa_vect() != NULL) {
1201     uint ireg = ideal_reg();
1202     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1203     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1204     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1205       // mem -> mem
1206       int src_offset = ra_->reg2offset(src_first);
1207       int dst_offset = ra_->reg2offset(dst_first);
1208       vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1209     } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1210       vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1211     } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1212       int stack_offset = ra_->reg2offset(dst_first);
1213       vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1214     } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1215       int stack_offset = ra_->reg2offset(src_first);
1216       vec_spill_helper(cbuf, false, true,  stack_offset, dst_first, ireg, st);
1217     } else {
1218       ShouldNotReachHere();
1219     }
1220     return 0;
1221   }
1222   if (src_first_rc == rc_stack) {
1223     // mem ->
1224     if (dst_first_rc == rc_stack) {
1225       // mem -> mem
1226       assert(src_second != dst_first, "overlap");
1227       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1228           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1229         // 64-bit
1230         int src_offset = ra_->reg2offset(src_first);
1231         int dst_offset = ra_->reg2offset(dst_first);
1232         if (cbuf) {
1233           MacroAssembler _masm(cbuf);
1234           __ pushq(Address(rsp, src_offset));
1235           __ popq (Address(rsp, dst_offset));
1236 #ifndef PRODUCT
1237         } else {
1238           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1239                     "popq    [rsp + #%d]",
1240                      src_offset, dst_offset);
1241 #endif
1242         }
1243       } else {
1244         // 32-bit
1245         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1246         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1247         // No pushl/popl, so:
1248         int src_offset = ra_->reg2offset(src_first);
1249         int dst_offset = ra_->reg2offset(dst_first);
1250         if (cbuf) {
1251           MacroAssembler _masm(cbuf);
1252           __ movq(Address(rsp, -8), rax);
1253           __ movl(rax, Address(rsp, src_offset));
1254           __ movl(Address(rsp, dst_offset), rax);
1255           __ movq(rax, Address(rsp, -8));
1256 #ifndef PRODUCT
1257         } else {
1258           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1259                     "movl    rax, [rsp + #%d]\n\t"
1260                     "movl    [rsp + #%d], rax\n\t"
1261                     "movq    rax, [rsp - #8]",
1262                      src_offset, dst_offset);
1263 #endif
1264         }
1265       }
1266       return 0;
1267     } else if (dst_first_rc == rc_int) {
1268       // mem -> gpr
1269       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1270           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1271         // 64-bit
1272         int offset = ra_->reg2offset(src_first);
1273         if (cbuf) {
1274           MacroAssembler _masm(cbuf);
1275           __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1276 #ifndef PRODUCT
1277         } else {
1278           st->print("movq    %s, [rsp + #%d]\t# spill",
1279                      Matcher::regName[dst_first],
1280                      offset);
1281 #endif
1282         }
1283       } else {
1284         // 32-bit
1285         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1286         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1287         int offset = ra_->reg2offset(src_first);
1288         if (cbuf) {
1289           MacroAssembler _masm(cbuf);
1290           __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1291 #ifndef PRODUCT
1292         } else {
1293           st->print("movl    %s, [rsp + #%d]\t# spill",
1294                      Matcher::regName[dst_first],
1295                      offset);
1296 #endif
1297         }
1298       }
1299       return 0;
1300     } else if (dst_first_rc == rc_float) {
1301       // mem-> xmm
1302       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1303           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1304         // 64-bit
1305         int offset = ra_->reg2offset(src_first);
1306         if (cbuf) {
1307           MacroAssembler _masm(cbuf);
1308           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1309 #ifndef PRODUCT
1310         } else {
1311           st->print("%s  %s, [rsp + #%d]\t# spill",
1312                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1313                      Matcher::regName[dst_first],
1314                      offset);
1315 #endif
1316         }
1317       } else {
1318         // 32-bit
1319         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1320         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1321         int offset = ra_->reg2offset(src_first);
1322         if (cbuf) {
1323           MacroAssembler _masm(cbuf);
1324           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1325 #ifndef PRODUCT
1326         } else {
1327           st->print("movss   %s, [rsp + #%d]\t# spill",
1328                      Matcher::regName[dst_first],
1329                      offset);
1330 #endif
1331         }
1332       }
1333       return 0;
1334     }
1335   } else if (src_first_rc == rc_int) {
1336     // gpr ->
1337     if (dst_first_rc == rc_stack) {
1338       // gpr -> mem
1339       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1340           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1341         // 64-bit
1342         int offset = ra_->reg2offset(dst_first);
1343         if (cbuf) {
1344           MacroAssembler _masm(cbuf);
1345           __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1346 #ifndef PRODUCT
1347         } else {
1348           st->print("movq    [rsp + #%d], %s\t# spill",
1349                      offset,
1350                      Matcher::regName[src_first]);
1351 #endif
1352         }
1353       } else {
1354         // 32-bit
1355         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1356         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1357         int offset = ra_->reg2offset(dst_first);
1358         if (cbuf) {
1359           MacroAssembler _masm(cbuf);
1360           __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1361 #ifndef PRODUCT
1362         } else {
1363           st->print("movl    [rsp + #%d], %s\t# spill",
1364                      offset,
1365                      Matcher::regName[src_first]);
1366 #endif
1367         }
1368       }
1369       return 0;
1370     } else if (dst_first_rc == rc_int) {
1371       // gpr -> gpr
1372       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1373           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1374         // 64-bit
1375         if (cbuf) {
1376           MacroAssembler _masm(cbuf);
1377           __ movq(as_Register(Matcher::_regEncode[dst_first]),
1378                   as_Register(Matcher::_regEncode[src_first]));
1379 #ifndef PRODUCT
1380         } else {
1381           st->print("movq    %s, %s\t# spill",
1382                      Matcher::regName[dst_first],
1383                      Matcher::regName[src_first]);
1384 #endif
1385         }
1386         return 0;
1387       } else {
1388         // 32-bit
1389         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1390         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1391         if (cbuf) {
1392           MacroAssembler _masm(cbuf);
1393           __ movl(as_Register(Matcher::_regEncode[dst_first]),
1394                   as_Register(Matcher::_regEncode[src_first]));
1395 #ifndef PRODUCT
1396         } else {
1397           st->print("movl    %s, %s\t# spill",
1398                      Matcher::regName[dst_first],
1399                      Matcher::regName[src_first]);
1400 #endif
1401         }
1402         return 0;
1403       }
1404     } else if (dst_first_rc == rc_float) {
1405       // gpr -> xmm
1406       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1407           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1408         // 64-bit
1409         if (cbuf) {
1410           MacroAssembler _masm(cbuf);
1411           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1412 #ifndef PRODUCT
1413         } else {
1414           st->print("movdq   %s, %s\t# spill",
1415                      Matcher::regName[dst_first],
1416                      Matcher::regName[src_first]);
1417 #endif
1418         }
1419       } else {
1420         // 32-bit
1421         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1422         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1423         if (cbuf) {
1424           MacroAssembler _masm(cbuf);
1425           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1426 #ifndef PRODUCT
1427         } else {
1428           st->print("movdl   %s, %s\t# spill",
1429                      Matcher::regName[dst_first],
1430                      Matcher::regName[src_first]);
1431 #endif
1432         }
1433       }
1434       return 0;
1435     }
1436   } else if (src_first_rc == rc_float) {
1437     // xmm ->
1438     if (dst_first_rc == rc_stack) {
1439       // xmm -> mem
1440       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1441           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1442         // 64-bit
1443         int offset = ra_->reg2offset(dst_first);
1444         if (cbuf) {
1445           MacroAssembler _masm(cbuf);
1446           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1447 #ifndef PRODUCT
1448         } else {
1449           st->print("movsd   [rsp + #%d], %s\t# spill",
1450                      offset,
1451                      Matcher::regName[src_first]);
1452 #endif
1453         }
1454       } else {
1455         // 32-bit
1456         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1457         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1458         int offset = ra_->reg2offset(dst_first);
1459         if (cbuf) {
1460           MacroAssembler _masm(cbuf);
1461           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1462 #ifndef PRODUCT
1463         } else {
1464           st->print("movss   [rsp + #%d], %s\t# spill",
1465                      offset,
1466                      Matcher::regName[src_first]);
1467 #endif
1468         }
1469       }
1470       return 0;
1471     } else if (dst_first_rc == rc_int) {
1472       // xmm -> gpr
1473       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1474           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1475         // 64-bit
1476         if (cbuf) {
1477           MacroAssembler _masm(cbuf);
1478           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1479 #ifndef PRODUCT
1480         } else {
1481           st->print("movdq   %s, %s\t# spill",
1482                      Matcher::regName[dst_first],
1483                      Matcher::regName[src_first]);
1484 #endif
1485         }
1486       } else {
1487         // 32-bit
1488         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1489         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1490         if (cbuf) {
1491           MacroAssembler _masm(cbuf);
1492           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1493 #ifndef PRODUCT
1494         } else {
1495           st->print("movdl   %s, %s\t# spill",
1496                      Matcher::regName[dst_first],
1497                      Matcher::regName[src_first]);
1498 #endif
1499         }
1500       }
1501       return 0;
1502     } else if (dst_first_rc == rc_float) {
1503       // xmm -> xmm
1504       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1505           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1506         // 64-bit
1507         if (cbuf) {
1508           MacroAssembler _masm(cbuf);
1509           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1510 #ifndef PRODUCT
1511         } else {
1512           st->print("%s  %s, %s\t# spill",
1513                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1514                      Matcher::regName[dst_first],
1515                      Matcher::regName[src_first]);
1516 #endif
1517         }
1518       } else {
1519         // 32-bit
1520         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1521         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1522         if (cbuf) {
1523           MacroAssembler _masm(cbuf);
1524           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1525 #ifndef PRODUCT
1526         } else {
1527           st->print("%s  %s, %s\t# spill",
1528                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1529                      Matcher::regName[dst_first],
1530                      Matcher::regName[src_first]);
1531 #endif
1532         }
1533       }
1534       return 0;
1535     }
1536   }
1537 
1538   assert(0," foo ");
1539   Unimplemented();
1540   return 0;
1541 }
1542 
1543 #ifndef PRODUCT
1544 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1545   implementation(NULL, ra_, false, st);
1546 }
1547 #endif
1548 
1549 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1550   implementation(&cbuf, ra_, false, NULL);
1551 }
1552 
1553 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1554   return MachNode::size(ra_);
1555 }
1556 
1557 //=============================================================================
1558 #ifndef PRODUCT
1559 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1560 {
1561   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1562   int reg = ra_->get_reg_first(this);
1563   st->print("leaq    %s, [rsp + #%d]\t# box lock",
1564             Matcher::regName[reg], offset);
1565 }
1566 #endif
1567 
1568 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1569 {
1570   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1571   int reg = ra_->get_encode(this);
1572   if (offset >= 0x80) {
1573     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1574     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
1575     emit_rm(cbuf, 0x2, reg & 7, 0x04);
1576     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1577     emit_d32(cbuf, offset);
1578   } else {
1579     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1580     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
1581     emit_rm(cbuf, 0x1, reg & 7, 0x04);
1582     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1583     emit_d8(cbuf, offset);
1584   }
1585 }
1586 
1587 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1588 {
1589   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1590   return (offset < 0x80) ? 5 : 8; // REX
1591 }
1592 
1593 //=============================================================================
1594 #ifndef PRODUCT
1595 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1596 {
1597   if (UseCompressedClassPointers) {
1598     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1599     st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1600     st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");
1601   } else {
1602     st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1603                  "# Inline cache check");
1604   }
1605   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
1606   st->print_cr("\tnop\t# nops to align entry point");
1607 }
1608 #endif
1609 
1610 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1611 {
1612   MacroAssembler masm(&cbuf);
1613   uint insts_size = cbuf.insts_size();
1614   if (UseCompressedClassPointers) {
1615     masm.load_klass(rscratch1, j_rarg0);
1616     masm.cmpptr(rax, rscratch1);
1617   } else {
1618     masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1619   }
1620 
1621   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1622 
1623   /* WARNING these NOPs are critical so that verified entry point is properly
1624      4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1625   int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1626   if (OptoBreakpoint) {
1627     // Leave space for int3
1628     nops_cnt -= 1;
1629   }
1630   nops_cnt &= 0x3; // Do not add nops if code is aligned.
1631   if (nops_cnt > 0)
1632     masm.nop(nops_cnt);
1633 }
1634 
1635 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1636 {
1637   return MachNode::size(ra_); // too many variables; just compute it
1638                               // the hard way
1639 }
1640 
1641 
1642 //=============================================================================
1643 
1644 int Matcher::regnum_to_fpu_offset(int regnum)
1645 {
1646   return regnum - 32; // The FP registers are in the second chunk
1647 }
1648 
1649 // This is UltraSparc specific, true just means we have fast l2f conversion
1650 const bool Matcher::convL2FSupported(void) {
1651   return true;
1652 }
1653 
1654 // Is this branch offset short enough that a short branch can be used?
1655 //
1656 // NOTE: If the platform does not provide any short branch variants, then
1657 //       this method should return false for offset 0.
1658 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1659   // The passed offset is relative to address of the branch.
1660   // On 86 a branch displacement is calculated relative to address
1661   // of a next instruction.
1662   offset -= br_size;
1663 
1664   // the short version of jmpConUCF2 contains multiple branches,
1665   // making the reach slightly less
1666   if (rule == jmpConUCF2_rule)
1667     return (-126 <= offset && offset <= 125);
1668   return (-128 <= offset && offset <= 127);
1669 }
1670 
1671 const bool Matcher::isSimpleConstant64(jlong value) {
1672   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1673   //return value == (int) value;  // Cf. storeImmL and immL32.
1674 
1675   // Probably always true, even if a temp register is required.
1676   return true;
1677 }
1678 
1679 // The ecx parameter to rep stosq for the ClearArray node is in words.
1680 const bool Matcher::init_array_count_is_in_bytes = false;
1681 
1682 // No additional cost for CMOVL.
1683 const int Matcher::long_cmove_cost() { return 0; }
1684 
1685 // No CMOVF/CMOVD with SSE2
1686 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1687 
1688 // Does the CPU require late expand (see block.cpp for description of late expand)?
1689 const bool Matcher::require_postalloc_expand = false;
1690 
1691 // Do we need to mask the count passed to shift instructions or does
1692 // the cpu only look at the lower 5/6 bits anyway?
1693 const bool Matcher::need_masked_shift_count = false;
1694 
1695 bool Matcher::narrow_oop_use_complex_address() {
1696   assert(UseCompressedOops, "only for compressed oops code");
1697   return (LogMinObjAlignmentInBytes <= 3);
1698 }
1699 
1700 bool Matcher::narrow_klass_use_complex_address() {
1701   assert(UseCompressedClassPointers, "only for compressed klass code");
1702   return (LogKlassAlignmentInBytes <= 3);
1703 }
1704 
1705 bool Matcher::const_oop_prefer_decode() {
1706   // Prefer ConN+DecodeN over ConP.
1707   return true;
1708 }
1709 
1710 bool Matcher::const_klass_prefer_decode() {
1711   // TODO: Either support matching DecodeNKlass (heap-based) in operand
1712   //       or condisider the following:
1713   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1714   //return Universe::narrow_klass_base() == NULL;
1715   return true;
1716 }
1717 
1718 // Is it better to copy float constants, or load them directly from
1719 // memory?  Intel can load a float constant from a direct address,
1720 // requiring no extra registers.  Most RISCs will have to materialize
1721 // an address into a register first, so they would do better to copy
1722 // the constant from stack.
1723 const bool Matcher::rematerialize_float_constants = true; // XXX
1724 
1725 // If CPU can load and store mis-aligned doubles directly then no
1726 // fixup is needed.  Else we split the double into 2 integer pieces
1727 // and move it piece-by-piece.  Only happens when passing doubles into
1728 // C code as the Java calling convention forces doubles to be aligned.
1729 const bool Matcher::misaligned_doubles_ok = true;
1730 
1731 // No-op on amd64
1732 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1733 
1734 // Advertise here if the CPU requires explicit rounding operations to
1735 // implement the UseStrictFP mode.
1736 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1737 
1738 // Are floats conerted to double when stored to stack during deoptimization?
1739 // On x64 it is stored without convertion so we can use normal access.
1740 bool Matcher::float_in_double() { return false; }
1741 
1742 // Do ints take an entire long register or just half?
1743 const bool Matcher::int_in_long = true;
1744 
1745 // Return whether or not this register is ever used as an argument.
1746 // This function is used on startup to build the trampoline stubs in
1747 // generateOptoStub.  Registers not mentioned will be killed by the VM
1748 // call in the trampoline, and arguments in those registers not be
1749 // available to the callee.
1750 bool Matcher::can_be_java_arg(int reg)
1751 {
1752   return
1753     reg ==  RDI_num || reg == RDI_H_num ||
1754     reg ==  RSI_num || reg == RSI_H_num ||
1755     reg ==  RDX_num || reg == RDX_H_num ||
1756     reg ==  RCX_num || reg == RCX_H_num ||
1757     reg ==   R8_num || reg ==  R8_H_num ||
1758     reg ==   R9_num || reg ==  R9_H_num ||
1759     reg ==  R12_num || reg == R12_H_num ||
1760     reg == XMM0_num || reg == XMM0b_num ||
1761     reg == XMM1_num || reg == XMM1b_num ||
1762     reg == XMM2_num || reg == XMM2b_num ||
1763     reg == XMM3_num || reg == XMM3b_num ||
1764     reg == XMM4_num || reg == XMM4b_num ||
1765     reg == XMM5_num || reg == XMM5b_num ||
1766     reg == XMM6_num || reg == XMM6b_num ||
1767     reg == XMM7_num || reg == XMM7b_num;
1768 }
1769 
1770 bool Matcher::is_spillable_arg(int reg)
1771 {
1772   return can_be_java_arg(reg);
1773 }
1774 
1775 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1776   // In 64 bit mode a code which use multiply when
1777   // devisor is constant is faster than hardware
1778   // DIV instruction (it uses MulHiL).
1779   return false;
1780 }
1781 
1782 // Register for DIVI projection of divmodI
1783 RegMask Matcher::divI_proj_mask() {
1784   return INT_RAX_REG_mask();
1785 }
1786 
1787 // Register for MODI projection of divmodI
1788 RegMask Matcher::modI_proj_mask() {
1789   return INT_RDX_REG_mask();
1790 }
1791 
1792 // Register for DIVL projection of divmodL
1793 RegMask Matcher::divL_proj_mask() {
1794   return LONG_RAX_REG_mask();
1795 }
1796 
1797 // Register for MODL projection of divmodL
1798 RegMask Matcher::modL_proj_mask() {
1799   return LONG_RDX_REG_mask();
1800 }
1801 
1802 // Register for saving SP into on method handle invokes. Not used on x86_64.
1803 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1804     return NO_REG_mask();
1805 }
1806 
1807 %}
1808 
1809 //----------ENCODING BLOCK-----------------------------------------------------
1810 // This block specifies the encoding classes used by the compiler to
1811 // output byte streams.  Encoding classes are parameterized macros
1812 // used by Machine Instruction Nodes in order to generate the bit
1813 // encoding of the instruction.  Operands specify their base encoding
1814 // interface with the interface keyword.  There are currently
1815 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1816 // COND_INTER.  REG_INTER causes an operand to generate a function
1817 // which returns its register number when queried.  CONST_INTER causes
1818 // an operand to generate a function which returns the value of the
1819 // constant when queried.  MEMORY_INTER causes an operand to generate
1820 // four functions which return the Base Register, the Index Register,
1821 // the Scale Value, and the Offset Value of the operand when queried.
1822 // COND_INTER causes an operand to generate six functions which return
1823 // the encoding code (ie - encoding bits for the instruction)
1824 // associated with each basic boolean condition for a conditional
1825 // instruction.
1826 //
1827 // Instructions specify two basic values for encoding.  Again, a
1828 // function is available to check if the constant displacement is an
1829 // oop. They use the ins_encode keyword to specify their encoding
1830 // classes (which must be a sequence of enc_class names, and their
1831 // parameters, specified in the encoding block), and they use the
1832 // opcode keyword to specify, in order, their primary, secondary, and
1833 // tertiary opcode.  Only the opcode sections which a particular
1834 // instruction needs for encoding need to be specified.
1835 encode %{
1836   // Build emit functions for each basic byte or larger field in the
1837   // intel encoding scheme (opcode, rm, sib, immediate), and call them
1838   // from C++ code in the enc_class source block.  Emit functions will
1839   // live in the main source block for now.  In future, we can
1840   // generalize this by adding a syntax that specifies the sizes of
1841   // fields in an order, so that the adlc can build the emit functions
1842   // automagically
1843 
1844   // Emit primary opcode
1845   enc_class OpcP
1846   %{
1847     emit_opcode(cbuf, $primary);
1848   %}
1849 
1850   // Emit secondary opcode
1851   enc_class OpcS
1852   %{
1853     emit_opcode(cbuf, $secondary);
1854   %}
1855 
1856   // Emit tertiary opcode
1857   enc_class OpcT
1858   %{
1859     emit_opcode(cbuf, $tertiary);
1860   %}
1861 
1862   // Emit opcode directly
1863   enc_class Opcode(immI d8)
1864   %{
1865     emit_opcode(cbuf, $d8$$constant);
1866   %}
1867 
1868   // Emit size prefix
1869   enc_class SizePrefix
1870   %{
1871     emit_opcode(cbuf, 0x66);
1872   %}
1873 
1874   enc_class reg(rRegI reg)
1875   %{
1876     emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1877   %}
1878 
1879   enc_class reg_reg(rRegI dst, rRegI src)
1880   %{
1881     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1882   %}
1883 
1884   enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1885   %{
1886     emit_opcode(cbuf, $opcode$$constant);
1887     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1888   %}
1889 
1890   enc_class cdql_enc(no_rax_rdx_RegI div)
1891   %{
1892     // Full implementation of Java idiv and irem; checks for
1893     // special case as described in JVM spec., p.243 & p.271.
1894     //
1895     //         normal case                           special case
1896     //
1897     // input : rax: dividend                         min_int
1898     //         reg: divisor                          -1
1899     //
1900     // output: rax: quotient  (= rax idiv reg)       min_int
1901     //         rdx: remainder (= rax irem reg)       0
1902     //
1903     //  Code sequnce:
1904     //
1905     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax
1906     //    5:   75 07/08                jne    e <normal>
1907     //    7:   33 d2                   xor    %edx,%edx
1908     //  [div >= 8 -> offset + 1]
1909     //  [REX_B]
1910     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div
1911     //    c:   74 03/04                je     11 <done>
1912     // 000000000000000e <normal>:
1913     //    e:   99                      cltd
1914     //  [div >= 8 -> offset + 1]
1915     //  [REX_B]
1916     //    f:   f7 f9                   idiv   $div
1917     // 0000000000000011 <done>:
1918 
1919     // cmp    $0x80000000,%eax
1920     emit_opcode(cbuf, 0x3d);
1921     emit_d8(cbuf, 0x00);
1922     emit_d8(cbuf, 0x00);
1923     emit_d8(cbuf, 0x00);
1924     emit_d8(cbuf, 0x80);
1925 
1926     // jne    e <normal>
1927     emit_opcode(cbuf, 0x75);
1928     emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1929 
1930     // xor    %edx,%edx
1931     emit_opcode(cbuf, 0x33);
1932     emit_d8(cbuf, 0xD2);
1933 
1934     // cmp    $0xffffffffffffffff,%ecx
1935     if ($div$$reg >= 8) {
1936       emit_opcode(cbuf, Assembler::REX_B);
1937     }
1938     emit_opcode(cbuf, 0x83);
1939     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1940     emit_d8(cbuf, 0xFF);
1941 
1942     // je     11 <done>
1943     emit_opcode(cbuf, 0x74);
1944     emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1945 
1946     // <normal>
1947     // cltd
1948     emit_opcode(cbuf, 0x99);
1949 
1950     // idivl (note: must be emitted by the user of this rule)
1951     // <done>
1952   %}
1953 
1954   enc_class cdqq_enc(no_rax_rdx_RegL div)
1955   %{
1956     // Full implementation of Java ldiv and lrem; checks for
1957     // special case as described in JVM spec., p.243 & p.271.
1958     //
1959     //         normal case                           special case
1960     //
1961     // input : rax: dividend                         min_long
1962     //         reg: divisor                          -1
1963     //
1964     // output: rax: quotient  (= rax idiv reg)       min_long
1965     //         rdx: remainder (= rax irem reg)       0
1966     //
1967     //  Code sequnce:
1968     //
1969     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx
1970     //    7:   00 00 80
1971     //    a:   48 39 d0                cmp    %rdx,%rax
1972     //    d:   75 08                   jne    17 <normal>
1973     //    f:   33 d2                   xor    %edx,%edx
1974     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div
1975     //   15:   74 05                   je     1c <done>
1976     // 0000000000000017 <normal>:
1977     //   17:   48 99                   cqto
1978     //   19:   48 f7 f9                idiv   $div
1979     // 000000000000001c <done>:
1980 
1981     // mov    $0x8000000000000000,%rdx
1982     emit_opcode(cbuf, Assembler::REX_W);
1983     emit_opcode(cbuf, 0xBA);
1984     emit_d8(cbuf, 0x00);
1985     emit_d8(cbuf, 0x00);
1986     emit_d8(cbuf, 0x00);
1987     emit_d8(cbuf, 0x00);
1988     emit_d8(cbuf, 0x00);
1989     emit_d8(cbuf, 0x00);
1990     emit_d8(cbuf, 0x00);
1991     emit_d8(cbuf, 0x80);
1992 
1993     // cmp    %rdx,%rax
1994     emit_opcode(cbuf, Assembler::REX_W);
1995     emit_opcode(cbuf, 0x39);
1996     emit_d8(cbuf, 0xD0);
1997 
1998     // jne    17 <normal>
1999     emit_opcode(cbuf, 0x75);
2000     emit_d8(cbuf, 0x08);
2001 
2002     // xor    %edx,%edx
2003     emit_opcode(cbuf, 0x33);
2004     emit_d8(cbuf, 0xD2);
2005 
2006     // cmp    $0xffffffffffffffff,$div
2007     emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2008     emit_opcode(cbuf, 0x83);
2009     emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2010     emit_d8(cbuf, 0xFF);
2011 
2012     // je     1e <done>
2013     emit_opcode(cbuf, 0x74);
2014     emit_d8(cbuf, 0x05);
2015 
2016     // <normal>
2017     // cqto
2018     emit_opcode(cbuf, Assembler::REX_W);
2019     emit_opcode(cbuf, 0x99);
2020 
2021     // idivq (note: must be emitted by the user of this rule)
2022     // <done>
2023   %}
2024 
2025   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2026   enc_class OpcSE(immI imm)
2027   %{
2028     // Emit primary opcode and set sign-extend bit
2029     // Check for 8-bit immediate, and set sign extend bit in opcode
2030     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2031       emit_opcode(cbuf, $primary | 0x02);
2032     } else {
2033       // 32-bit immediate
2034       emit_opcode(cbuf, $primary);
2035     }
2036   %}
2037 
2038   enc_class OpcSErm(rRegI dst, immI imm)
2039   %{
2040     // OpcSEr/m
2041     int dstenc = $dst$$reg;
2042     if (dstenc >= 8) {
2043       emit_opcode(cbuf, Assembler::REX_B);
2044       dstenc -= 8;
2045     }
2046     // Emit primary opcode and set sign-extend bit
2047     // Check for 8-bit immediate, and set sign extend bit in opcode
2048     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2049       emit_opcode(cbuf, $primary | 0x02);
2050     } else {
2051       // 32-bit immediate
2052       emit_opcode(cbuf, $primary);
2053     }
2054     // Emit r/m byte with secondary opcode, after primary opcode.
2055     emit_rm(cbuf, 0x3, $secondary, dstenc);
2056   %}
2057 
2058   enc_class OpcSErm_wide(rRegL dst, immI imm)
2059   %{
2060     // OpcSEr/m
2061     int dstenc = $dst$$reg;
2062     if (dstenc < 8) {
2063       emit_opcode(cbuf, Assembler::REX_W);
2064     } else {
2065       emit_opcode(cbuf, Assembler::REX_WB);
2066       dstenc -= 8;
2067     }
2068     // Emit primary opcode and set sign-extend bit
2069     // Check for 8-bit immediate, and set sign extend bit in opcode
2070     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2071       emit_opcode(cbuf, $primary | 0x02);
2072     } else {
2073       // 32-bit immediate
2074       emit_opcode(cbuf, $primary);
2075     }
2076     // Emit r/m byte with secondary opcode, after primary opcode.
2077     emit_rm(cbuf, 0x3, $secondary, dstenc);
2078   %}
2079 
2080   enc_class Con8or32(immI imm)
2081   %{
2082     // Check for 8-bit immediate, and set sign extend bit in opcode
2083     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2084       $$$emit8$imm$$constant;
2085     } else {
2086       // 32-bit immediate
2087       $$$emit32$imm$$constant;
2088     }
2089   %}
2090 
2091   enc_class opc2_reg(rRegI dst)
2092   %{
2093     // BSWAP
2094     emit_cc(cbuf, $secondary, $dst$$reg);
2095   %}
2096 
2097   enc_class opc3_reg(rRegI dst)
2098   %{
2099     // BSWAP
2100     emit_cc(cbuf, $tertiary, $dst$$reg);
2101   %}
2102 
2103   enc_class reg_opc(rRegI div)
2104   %{
2105     // INC, DEC, IDIV, IMOD, JMP indirect, ...
2106     emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2107   %}
2108 
2109   enc_class enc_cmov(cmpOp cop)
2110   %{
2111     // CMOV
2112     $$$emit8$primary;
2113     emit_cc(cbuf, $secondary, $cop$$cmpcode);
2114   %}
2115 
2116   enc_class enc_PartialSubtypeCheck()
2117   %{
2118     Register Rrdi = as_Register(RDI_enc); // result register
2119     Register Rrax = as_Register(RAX_enc); // super class
2120     Register Rrcx = as_Register(RCX_enc); // killed
2121     Register Rrsi = as_Register(RSI_enc); // sub class
2122     Label miss;
2123     const bool set_cond_codes = true;
2124 
2125     MacroAssembler _masm(&cbuf);
2126     __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2127                                      NULL, &miss,
2128                                      /*set_cond_codes:*/ true);
2129     if ($primary) {
2130       __ xorptr(Rrdi, Rrdi);
2131     }
2132     __ bind(miss);
2133   %}
2134 
2135   enc_class clear_avx %{
2136     debug_only(int off0 = cbuf.insts_size());
2137     if (generate_vzeroupper(Compile::current())) {
2138       // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2139       // Clear upper bits of YMM registers when current compiled code uses
2140       // wide vectors to avoid AVX <-> SSE transition penalty during call.
2141       MacroAssembler _masm(&cbuf);
2142       __ vzeroupper();
2143     }
2144     debug_only(int off1 = cbuf.insts_size());
2145     assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2146   %}
2147 
2148   enc_class Java_To_Runtime(method meth) %{
2149     // No relocation needed
2150     MacroAssembler _masm(&cbuf);
2151     __ mov64(r10, (int64_t) $meth$$method);
2152     __ call(r10);
2153   %}
2154 
2155   enc_class Java_To_Interpreter(method meth)
2156   %{
2157     // CALL Java_To_Interpreter
2158     // This is the instruction starting address for relocation info.
2159     cbuf.set_insts_mark();
2160     $$$emit8$primary;
2161     // CALL directly to the runtime
2162     emit_d32_reloc(cbuf,
2163                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2164                    runtime_call_Relocation::spec(),
2165                    RELOC_DISP32);
2166   %}
2167 
2168   enc_class Java_Static_Call(method meth)
2169   %{
2170     // JAVA STATIC CALL
2171     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
2172     // determine who we intended to call.
2173     cbuf.set_insts_mark();
2174     $$$emit8$primary;
2175 
2176     if (!_method) {
2177       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2178                      runtime_call_Relocation::spec(),
2179                      RELOC_DISP32);
2180     } else {
2181       int method_index = resolved_method_index(cbuf);
2182       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2183                                                   : static_call_Relocation::spec(method_index);
2184       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2185                      rspec, RELOC_DISP32);
2186       // Emit stubs for static call.
2187       address mark = cbuf.insts_mark();
2188       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2189       if (stub == NULL) {
2190         ciEnv::current()->record_failure("CodeCache is full");
2191         return;
2192       }
2193 #if INCLUDE_AOT
2194       CompiledStaticCall::emit_to_aot_stub(cbuf, mark);
2195 #endif
2196     }
2197   %}
2198 
2199   enc_class Java_Dynamic_Call(method meth) %{
2200     MacroAssembler _masm(&cbuf);
2201     __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2202   %}
2203 
2204   enc_class Java_Compiled_Call(method meth)
2205   %{
2206     // JAVA COMPILED CALL
2207     int disp = in_bytes(Method:: from_compiled_offset());
2208 
2209     // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2210     // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2211 
2212     // callq *disp(%rax)
2213     cbuf.set_insts_mark();
2214     $$$emit8$primary;
2215     if (disp < 0x80) {
2216       emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2217       emit_d8(cbuf, disp); // Displacement
2218     } else {
2219       emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2220       emit_d32(cbuf, disp); // Displacement
2221     }
2222   %}
2223 
2224   enc_class reg_opc_imm(rRegI dst, immI8 shift)
2225   %{
2226     // SAL, SAR, SHR
2227     int dstenc = $dst$$reg;
2228     if (dstenc >= 8) {
2229       emit_opcode(cbuf, Assembler::REX_B);
2230       dstenc -= 8;
2231     }
2232     $$$emit8$primary;
2233     emit_rm(cbuf, 0x3, $secondary, dstenc);
2234     $$$emit8$shift$$constant;
2235   %}
2236 
2237   enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2238   %{
2239     // SAL, SAR, SHR
2240     int dstenc = $dst$$reg;
2241     if (dstenc < 8) {
2242       emit_opcode(cbuf, Assembler::REX_W);
2243     } else {
2244       emit_opcode(cbuf, Assembler::REX_WB);
2245       dstenc -= 8;
2246     }
2247     $$$emit8$primary;
2248     emit_rm(cbuf, 0x3, $secondary, dstenc);
2249     $$$emit8$shift$$constant;
2250   %}
2251 
2252   enc_class load_immI(rRegI dst, immI src)
2253   %{
2254     int dstenc = $dst$$reg;
2255     if (dstenc >= 8) {
2256       emit_opcode(cbuf, Assembler::REX_B);
2257       dstenc -= 8;
2258     }
2259     emit_opcode(cbuf, 0xB8 | dstenc);
2260     $$$emit32$src$$constant;
2261   %}
2262 
2263   enc_class load_immL(rRegL dst, immL src)
2264   %{
2265     int dstenc = $dst$$reg;
2266     if (dstenc < 8) {
2267       emit_opcode(cbuf, Assembler::REX_W);
2268     } else {
2269       emit_opcode(cbuf, Assembler::REX_WB);
2270       dstenc -= 8;
2271     }
2272     emit_opcode(cbuf, 0xB8 | dstenc);
2273     emit_d64(cbuf, $src$$constant);
2274   %}
2275 
2276   enc_class load_immUL32(rRegL dst, immUL32 src)
2277   %{
2278     // same as load_immI, but this time we care about zeroes in the high word
2279     int dstenc = $dst$$reg;
2280     if (dstenc >= 8) {
2281       emit_opcode(cbuf, Assembler::REX_B);
2282       dstenc -= 8;
2283     }
2284     emit_opcode(cbuf, 0xB8 | dstenc);
2285     $$$emit32$src$$constant;
2286   %}
2287 
2288   enc_class load_immL32(rRegL dst, immL32 src)
2289   %{
2290     int dstenc = $dst$$reg;
2291     if (dstenc < 8) {
2292       emit_opcode(cbuf, Assembler::REX_W);
2293     } else {
2294       emit_opcode(cbuf, Assembler::REX_WB);
2295       dstenc -= 8;
2296     }
2297     emit_opcode(cbuf, 0xC7);
2298     emit_rm(cbuf, 0x03, 0x00, dstenc);
2299     $$$emit32$src$$constant;
2300   %}
2301 
2302   enc_class load_immP31(rRegP dst, immP32 src)
2303   %{
2304     // same as load_immI, but this time we care about zeroes in the high word
2305     int dstenc = $dst$$reg;
2306     if (dstenc >= 8) {
2307       emit_opcode(cbuf, Assembler::REX_B);
2308       dstenc -= 8;
2309     }
2310     emit_opcode(cbuf, 0xB8 | dstenc);
2311     $$$emit32$src$$constant;
2312   %}
2313 
2314   enc_class load_immP(rRegP dst, immP src)
2315   %{
2316     int dstenc = $dst$$reg;
2317     if (dstenc < 8) {
2318       emit_opcode(cbuf, Assembler::REX_W);
2319     } else {
2320       emit_opcode(cbuf, Assembler::REX_WB);
2321       dstenc -= 8;
2322     }
2323     emit_opcode(cbuf, 0xB8 | dstenc);
2324     // This next line should be generated from ADLC
2325     if ($src->constant_reloc() != relocInfo::none) {
2326       emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2327     } else {
2328       emit_d64(cbuf, $src$$constant);
2329     }
2330   %}
2331 
2332   enc_class Con32(immI src)
2333   %{
2334     // Output immediate
2335     $$$emit32$src$$constant;
2336   %}
2337 
2338   enc_class Con32F_as_bits(immF src)
2339   %{
2340     // Output Float immediate bits
2341     jfloat jf = $src$$constant;
2342     jint jf_as_bits = jint_cast(jf);
2343     emit_d32(cbuf, jf_as_bits);
2344   %}
2345 
2346   enc_class Con16(immI src)
2347   %{
2348     // Output immediate
2349     $$$emit16$src$$constant;
2350   %}
2351 
2352   // How is this different from Con32??? XXX
2353   enc_class Con_d32(immI src)
2354   %{
2355     emit_d32(cbuf,$src$$constant);
2356   %}
2357 
2358   enc_class conmemref (rRegP t1) %{    // Con32(storeImmI)
2359     // Output immediate memory reference
2360     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2361     emit_d32(cbuf, 0x00);
2362   %}
2363 
2364   enc_class lock_prefix()
2365   %{
2366     if (os::is_MP()) {
2367       emit_opcode(cbuf, 0xF0); // lock
2368     }
2369   %}
2370 
2371   enc_class REX_mem(memory mem)
2372   %{
2373     if ($mem$$base >= 8) {
2374       if ($mem$$index < 8) {
2375         emit_opcode(cbuf, Assembler::REX_B);
2376       } else {
2377         emit_opcode(cbuf, Assembler::REX_XB);
2378       }
2379     } else {
2380       if ($mem$$index >= 8) {
2381         emit_opcode(cbuf, Assembler::REX_X);
2382       }
2383     }
2384   %}
2385 
2386   enc_class REX_mem_wide(memory mem)
2387   %{
2388     if ($mem$$base >= 8) {
2389       if ($mem$$index < 8) {
2390         emit_opcode(cbuf, Assembler::REX_WB);
2391       } else {
2392         emit_opcode(cbuf, Assembler::REX_WXB);
2393       }
2394     } else {
2395       if ($mem$$index < 8) {
2396         emit_opcode(cbuf, Assembler::REX_W);
2397       } else {
2398         emit_opcode(cbuf, Assembler::REX_WX);
2399       }
2400     }
2401   %}
2402 
2403   // for byte regs
2404   enc_class REX_breg(rRegI reg)
2405   %{
2406     if ($reg$$reg >= 4) {
2407       emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2408     }
2409   %}
2410 
2411   // for byte regs
2412   enc_class REX_reg_breg(rRegI dst, rRegI src)
2413   %{
2414     if ($dst$$reg < 8) {
2415       if ($src$$reg >= 4) {
2416         emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2417       }
2418     } else {
2419       if ($src$$reg < 8) {
2420         emit_opcode(cbuf, Assembler::REX_R);
2421       } else {
2422         emit_opcode(cbuf, Assembler::REX_RB);
2423       }
2424     }
2425   %}
2426 
2427   // for byte regs
2428   enc_class REX_breg_mem(rRegI reg, memory mem)
2429   %{
2430     if ($reg$$reg < 8) {
2431       if ($mem$$base < 8) {
2432         if ($mem$$index >= 8) {
2433           emit_opcode(cbuf, Assembler::REX_X);
2434         } else if ($reg$$reg >= 4) {
2435           emit_opcode(cbuf, Assembler::REX);
2436         }
2437       } else {
2438         if ($mem$$index < 8) {
2439           emit_opcode(cbuf, Assembler::REX_B);
2440         } else {
2441           emit_opcode(cbuf, Assembler::REX_XB);
2442         }
2443       }
2444     } else {
2445       if ($mem$$base < 8) {
2446         if ($mem$$index < 8) {
2447           emit_opcode(cbuf, Assembler::REX_R);
2448         } else {
2449           emit_opcode(cbuf, Assembler::REX_RX);
2450         }
2451       } else {
2452         if ($mem$$index < 8) {
2453           emit_opcode(cbuf, Assembler::REX_RB);
2454         } else {
2455           emit_opcode(cbuf, Assembler::REX_RXB);
2456         }
2457       }
2458     }
2459   %}
2460 
2461   enc_class REX_reg(rRegI reg)
2462   %{
2463     if ($reg$$reg >= 8) {
2464       emit_opcode(cbuf, Assembler::REX_B);
2465     }
2466   %}
2467 
2468   enc_class REX_reg_wide(rRegI reg)
2469   %{
2470     if ($reg$$reg < 8) {
2471       emit_opcode(cbuf, Assembler::REX_W);
2472     } else {
2473       emit_opcode(cbuf, Assembler::REX_WB);
2474     }
2475   %}
2476 
2477   enc_class REX_reg_reg(rRegI dst, rRegI src)
2478   %{
2479     if ($dst$$reg < 8) {
2480       if ($src$$reg >= 8) {
2481         emit_opcode(cbuf, Assembler::REX_B);
2482       }
2483     } else {
2484       if ($src$$reg < 8) {
2485         emit_opcode(cbuf, Assembler::REX_R);
2486       } else {
2487         emit_opcode(cbuf, Assembler::REX_RB);
2488       }
2489     }
2490   %}
2491 
2492   enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2493   %{
2494     if ($dst$$reg < 8) {
2495       if ($src$$reg < 8) {
2496         emit_opcode(cbuf, Assembler::REX_W);
2497       } else {
2498         emit_opcode(cbuf, Assembler::REX_WB);
2499       }
2500     } else {
2501       if ($src$$reg < 8) {
2502         emit_opcode(cbuf, Assembler::REX_WR);
2503       } else {
2504         emit_opcode(cbuf, Assembler::REX_WRB);
2505       }
2506     }
2507   %}
2508 
2509   enc_class REX_reg_mem(rRegI reg, memory mem)
2510   %{
2511     if ($reg$$reg < 8) {
2512       if ($mem$$base < 8) {
2513         if ($mem$$index >= 8) {
2514           emit_opcode(cbuf, Assembler::REX_X);
2515         }
2516       } else {
2517         if ($mem$$index < 8) {
2518           emit_opcode(cbuf, Assembler::REX_B);
2519         } else {
2520           emit_opcode(cbuf, Assembler::REX_XB);
2521         }
2522       }
2523     } else {
2524       if ($mem$$base < 8) {
2525         if ($mem$$index < 8) {
2526           emit_opcode(cbuf, Assembler::REX_R);
2527         } else {
2528           emit_opcode(cbuf, Assembler::REX_RX);
2529         }
2530       } else {
2531         if ($mem$$index < 8) {
2532           emit_opcode(cbuf, Assembler::REX_RB);
2533         } else {
2534           emit_opcode(cbuf, Assembler::REX_RXB);
2535         }
2536       }
2537     }
2538   %}
2539 
2540   enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2541   %{
2542     if ($reg$$reg < 8) {
2543       if ($mem$$base < 8) {
2544         if ($mem$$index < 8) {
2545           emit_opcode(cbuf, Assembler::REX_W);
2546         } else {
2547           emit_opcode(cbuf, Assembler::REX_WX);
2548         }
2549       } else {
2550         if ($mem$$index < 8) {
2551           emit_opcode(cbuf, Assembler::REX_WB);
2552         } else {
2553           emit_opcode(cbuf, Assembler::REX_WXB);
2554         }
2555       }
2556     } else {
2557       if ($mem$$base < 8) {
2558         if ($mem$$index < 8) {
2559           emit_opcode(cbuf, Assembler::REX_WR);
2560         } else {
2561           emit_opcode(cbuf, Assembler::REX_WRX);
2562         }
2563       } else {
2564         if ($mem$$index < 8) {
2565           emit_opcode(cbuf, Assembler::REX_WRB);
2566         } else {
2567           emit_opcode(cbuf, Assembler::REX_WRXB);
2568         }
2569       }
2570     }
2571   %}
2572 
2573   enc_class reg_mem(rRegI ereg, memory mem)
2574   %{
2575     // High registers handle in encode_RegMem
2576     int reg = $ereg$$reg;
2577     int base = $mem$$base;
2578     int index = $mem$$index;
2579     int scale = $mem$$scale;
2580     int disp = $mem$$disp;
2581     relocInfo::relocType disp_reloc = $mem->disp_reloc();
2582 
2583     encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2584   %}
2585 
2586   enc_class RM_opc_mem(immI rm_opcode, memory mem)
2587   %{
2588     int rm_byte_opcode = $rm_opcode$$constant;
2589 
2590     // High registers handle in encode_RegMem
2591     int base = $mem$$base;
2592     int index = $mem$$index;
2593     int scale = $mem$$scale;
2594     int displace = $mem$$disp;
2595 
2596     relocInfo::relocType disp_reloc = $mem->disp_reloc();       // disp-as-oop when
2597                                             // working with static
2598                                             // globals
2599     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2600                   disp_reloc);
2601   %}
2602 
2603   enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2604   %{
2605     int reg_encoding = $dst$$reg;
2606     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
2607     int index        = 0x04;            // 0x04 indicates no index
2608     int scale        = 0x00;            // 0x00 indicates no scale
2609     int displace     = $src1$$constant; // 0x00 indicates no displacement
2610     relocInfo::relocType disp_reloc = relocInfo::none;
2611     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2612                   disp_reloc);
2613   %}
2614 
2615   enc_class neg_reg(rRegI dst)
2616   %{
2617     int dstenc = $dst$$reg;
2618     if (dstenc >= 8) {
2619       emit_opcode(cbuf, Assembler::REX_B);
2620       dstenc -= 8;
2621     }
2622     // NEG $dst
2623     emit_opcode(cbuf, 0xF7);
2624     emit_rm(cbuf, 0x3, 0x03, dstenc);
2625   %}
2626 
2627   enc_class neg_reg_wide(rRegI dst)
2628   %{
2629     int dstenc = $dst$$reg;
2630     if (dstenc < 8) {
2631       emit_opcode(cbuf, Assembler::REX_W);
2632     } else {
2633       emit_opcode(cbuf, Assembler::REX_WB);
2634       dstenc -= 8;
2635     }
2636     // NEG $dst
2637     emit_opcode(cbuf, 0xF7);
2638     emit_rm(cbuf, 0x3, 0x03, dstenc);
2639   %}
2640 
2641   enc_class setLT_reg(rRegI dst)
2642   %{
2643     int dstenc = $dst$$reg;
2644     if (dstenc >= 8) {
2645       emit_opcode(cbuf, Assembler::REX_B);
2646       dstenc -= 8;
2647     } else if (dstenc >= 4) {
2648       emit_opcode(cbuf, Assembler::REX);
2649     }
2650     // SETLT $dst
2651     emit_opcode(cbuf, 0x0F);
2652     emit_opcode(cbuf, 0x9C);
2653     emit_rm(cbuf, 0x3, 0x0, dstenc);
2654   %}
2655 
2656   enc_class setNZ_reg(rRegI dst)
2657   %{
2658     int dstenc = $dst$$reg;
2659     if (dstenc >= 8) {
2660       emit_opcode(cbuf, Assembler::REX_B);
2661       dstenc -= 8;
2662     } else if (dstenc >= 4) {
2663       emit_opcode(cbuf, Assembler::REX);
2664     }
2665     // SETNZ $dst
2666     emit_opcode(cbuf, 0x0F);
2667     emit_opcode(cbuf, 0x95);
2668     emit_rm(cbuf, 0x3, 0x0, dstenc);
2669   %}
2670 
2671 
2672   // Compare the lonogs and set -1, 0, or 1 into dst
2673   enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2674   %{
2675     int src1enc = $src1$$reg;
2676     int src2enc = $src2$$reg;
2677     int dstenc = $dst$$reg;
2678 
2679     // cmpq $src1, $src2
2680     if (src1enc < 8) {
2681       if (src2enc < 8) {
2682         emit_opcode(cbuf, Assembler::REX_W);
2683       } else {
2684         emit_opcode(cbuf, Assembler::REX_WB);
2685       }
2686     } else {
2687       if (src2enc < 8) {
2688         emit_opcode(cbuf, Assembler::REX_WR);
2689       } else {
2690         emit_opcode(cbuf, Assembler::REX_WRB);
2691       }
2692     }
2693     emit_opcode(cbuf, 0x3B);
2694     emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2695 
2696     // movl $dst, -1
2697     if (dstenc >= 8) {
2698       emit_opcode(cbuf, Assembler::REX_B);
2699     }
2700     emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2701     emit_d32(cbuf, -1);
2702 
2703     // jl,s done
2704     emit_opcode(cbuf, 0x7C);
2705     emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2706 
2707     // setne $dst
2708     if (dstenc >= 4) {
2709       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2710     }
2711     emit_opcode(cbuf, 0x0F);
2712     emit_opcode(cbuf, 0x95);
2713     emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2714 
2715     // movzbl $dst, $dst
2716     if (dstenc >= 4) {
2717       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2718     }
2719     emit_opcode(cbuf, 0x0F);
2720     emit_opcode(cbuf, 0xB6);
2721     emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2722   %}
2723 
2724   enc_class Push_ResultXD(regD dst) %{
2725     MacroAssembler _masm(&cbuf);
2726     __ fstp_d(Address(rsp, 0));
2727     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2728     __ addptr(rsp, 8);
2729   %}
2730 
2731   enc_class Push_SrcXD(regD src) %{
2732     MacroAssembler _masm(&cbuf);
2733     __ subptr(rsp, 8);
2734     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2735     __ fld_d(Address(rsp, 0));
2736   %}
2737 
2738 
2739   enc_class enc_rethrow()
2740   %{
2741     cbuf.set_insts_mark();
2742     emit_opcode(cbuf, 0xE9); // jmp entry
2743     emit_d32_reloc(cbuf,
2744                    (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2745                    runtime_call_Relocation::spec(),
2746                    RELOC_DISP32);
2747   %}
2748 
2749 %}
2750 
2751 
2752 
2753 //----------FRAME--------------------------------------------------------------
2754 // Definition of frame structure and management information.
2755 //
2756 //  S T A C K   L A Y O U T    Allocators stack-slot number
2757 //                             |   (to get allocators register number
2758 //  G  Owned by    |        |  v    add OptoReg::stack0())
2759 //  r   CALLER     |        |
2760 //  o     |        +--------+      pad to even-align allocators stack-slot
2761 //  w     V        |  pad0  |        numbers; owned by CALLER
2762 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
2763 //  h     ^        |   in   |  5
2764 //        |        |  args  |  4   Holes in incoming args owned by SELF
2765 //  |     |        |        |  3
2766 //  |     |        +--------+
2767 //  V     |        | old out|      Empty on Intel, window on Sparc
2768 //        |    old |preserve|      Must be even aligned.
2769 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
2770 //        |        |   in   |  3   area for Intel ret address
2771 //     Owned by    |preserve|      Empty on Sparc.
2772 //       SELF      +--------+
2773 //        |        |  pad2  |  2   pad to align old SP
2774 //        |        +--------+  1
2775 //        |        | locks  |  0
2776 //        |        +--------+----> OptoReg::stack0(), even aligned
2777 //        |        |  pad1  | 11   pad to align new SP
2778 //        |        +--------+
2779 //        |        |        | 10
2780 //        |        | spills |  9   spills
2781 //        V        |        |  8   (pad0 slot for callee)
2782 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
2783 //        ^        |  out   |  7
2784 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
2785 //     Owned by    +--------+
2786 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
2787 //        |    new |preserve|      Must be even-aligned.
2788 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
2789 //        |        |        |
2790 //
2791 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
2792 //         known from SELF's arguments and the Java calling convention.
2793 //         Region 6-7 is determined per call site.
2794 // Note 2: If the calling convention leaves holes in the incoming argument
2795 //         area, those holes are owned by SELF.  Holes in the outgoing area
2796 //         are owned by the CALLEE.  Holes should not be nessecary in the
2797 //         incoming area, as the Java calling convention is completely under
2798 //         the control of the AD file.  Doubles can be sorted and packed to
2799 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
2800 //         varargs C calling conventions.
2801 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
2802 //         even aligned with pad0 as needed.
2803 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
2804 //         region 6-11 is even aligned; it may be padded out more so that
2805 //         the region from SP to FP meets the minimum stack alignment.
2806 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2807 //         alignment.  Region 11, pad1, may be dynamically extended so that
2808 //         SP meets the minimum alignment.
2809 
2810 frame
2811 %{
2812   // What direction does stack grow in (assumed to be same for C & Java)
2813   stack_direction(TOWARDS_LOW);
2814 
2815   // These three registers define part of the calling convention
2816   // between compiled code and the interpreter.
2817   inline_cache_reg(RAX);                // Inline Cache Register
2818   interpreter_method_oop_reg(RBX);      // Method Oop Register when
2819                                         // calling interpreter
2820 
2821   // Optional: name the operand used by cisc-spilling to access
2822   // [stack_pointer + offset]
2823   cisc_spilling_operand_name(indOffset32);
2824 
2825   // Number of stack slots consumed by locking an object
2826   sync_stack_slots(2);
2827 
2828   // Compiled code's Frame Pointer
2829   frame_pointer(RSP);
2830 
2831   // Interpreter stores its frame pointer in a register which is
2832   // stored to the stack by I2CAdaptors.
2833   // I2CAdaptors convert from interpreted java to compiled java.
2834   interpreter_frame_pointer(RBP);
2835 
2836   // Stack alignment requirement
2837   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2838 
2839   // Number of stack slots between incoming argument block and the start of
2840   // a new frame.  The PROLOG must add this many slots to the stack.  The
2841   // EPILOG must remove this many slots.  amd64 needs two slots for
2842   // return address.
2843   in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2844 
2845   // Number of outgoing stack slots killed above the out_preserve_stack_slots
2846   // for calls to C.  Supports the var-args backing area for register parms.
2847   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2848 
2849   // The after-PROLOG location of the return address.  Location of
2850   // return address specifies a type (REG or STACK) and a number
2851   // representing the register number (i.e. - use a register name) or
2852   // stack slot.
2853   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2854   // Otherwise, it is above the locks and verification slot and alignment word
2855   return_addr(STACK - 2 +
2856               align_up((Compile::current()->in_preserve_stack_slots() +
2857                         Compile::current()->fixed_slots()),
2858                        stack_alignment_in_slots()));
2859 
2860   // Body of function which returns an integer array locating
2861   // arguments either in registers or in stack slots.  Passed an array
2862   // of ideal registers called "sig" and a "length" count.  Stack-slot
2863   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2864   // arguments for a CALLEE.  Incoming stack arguments are
2865   // automatically biased by the preserve_stack_slots field above.
2866 
2867   calling_convention
2868   %{
2869     // No difference between ingoing/outgoing just pass false
2870     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2871   %}
2872 
2873   c_calling_convention
2874   %{
2875     // This is obviously always outgoing
2876     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2877   %}
2878 
2879   // Location of compiled Java return values.  Same as C for now.
2880   return_value
2881   %{
2882     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2883            "only return normal values");
2884 
2885     static const int lo[Op_RegL + 1] = {
2886       0,
2887       0,
2888       RAX_num,  // Op_RegN
2889       RAX_num,  // Op_RegI
2890       RAX_num,  // Op_RegP
2891       XMM0_num, // Op_RegF
2892       XMM0_num, // Op_RegD
2893       RAX_num   // Op_RegL
2894     };
2895     static const int hi[Op_RegL + 1] = {
2896       0,
2897       0,
2898       OptoReg::Bad, // Op_RegN
2899       OptoReg::Bad, // Op_RegI
2900       RAX_H_num,    // Op_RegP
2901       OptoReg::Bad, // Op_RegF
2902       XMM0b_num,    // Op_RegD
2903       RAX_H_num     // Op_RegL
2904     };
2905     // Excluded flags and vector registers.
2906     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2907     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2908   %}
2909 %}
2910 
2911 //----------ATTRIBUTES---------------------------------------------------------
2912 //----------Operand Attributes-------------------------------------------------
2913 op_attrib op_cost(0);        // Required cost attribute
2914 
2915 //----------Instruction Attributes---------------------------------------------
2916 ins_attrib ins_cost(100);       // Required cost attribute
2917 ins_attrib ins_size(8);         // Required size attribute (in bits)
2918 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2919                                 // a non-matching short branch variant
2920                                 // of some long branch?
2921 ins_attrib ins_alignment(1);    // Required alignment attribute (must
2922                                 // be a power of 2) specifies the
2923                                 // alignment that some part of the
2924                                 // instruction (not necessarily the
2925                                 // start) requires.  If > 1, a
2926                                 // compute_padding() function must be
2927                                 // provided for the instruction
2928 
2929 //----------OPERANDS-----------------------------------------------------------
2930 // Operand definitions must precede instruction definitions for correct parsing
2931 // in the ADLC because operands constitute user defined types which are used in
2932 // instruction definitions.
2933 
2934 //----------Simple Operands----------------------------------------------------
2935 // Immediate Operands
2936 // Integer Immediate
2937 operand immI()
2938 %{
2939   match(ConI);
2940 
2941   op_cost(10);
2942   format %{ %}
2943   interface(CONST_INTER);
2944 %}
2945 
2946 // Constant for test vs zero
2947 operand immI0()
2948 %{
2949   predicate(n->get_int() == 0);
2950   match(ConI);
2951 
2952   op_cost(0);
2953   format %{ %}
2954   interface(CONST_INTER);
2955 %}
2956 
2957 // Constant for increment
2958 operand immI1()
2959 %{
2960   predicate(n->get_int() == 1);
2961   match(ConI);
2962 
2963   op_cost(0);
2964   format %{ %}
2965   interface(CONST_INTER);
2966 %}
2967 
2968 // Constant for decrement
2969 operand immI_M1()
2970 %{
2971   predicate(n->get_int() == -1);
2972   match(ConI);
2973 
2974   op_cost(0);
2975   format %{ %}
2976   interface(CONST_INTER);
2977 %}
2978 
2979 // Valid scale values for addressing modes
2980 operand immI2()
2981 %{
2982   predicate(0 <= n->get_int() && (n->get_int() <= 3));
2983   match(ConI);
2984 
2985   format %{ %}
2986   interface(CONST_INTER);
2987 %}
2988 
2989 operand immI8()
2990 %{
2991   predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2992   match(ConI);
2993 
2994   op_cost(5);
2995   format %{ %}
2996   interface(CONST_INTER);
2997 %}
2998 
2999 operand immU8()
3000 %{
3001   predicate((0 <= n->get_int()) && (n->get_int() <= 255));
3002   match(ConI);
3003 
3004   op_cost(5);
3005   format %{ %}
3006   interface(CONST_INTER);
3007 %}
3008 
3009 operand immI16()
3010 %{
3011   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3012   match(ConI);
3013 
3014   op_cost(10);
3015   format %{ %}
3016   interface(CONST_INTER);
3017 %}
3018 
3019 // Int Immediate non-negative
3020 operand immU31()
3021 %{
3022   predicate(n->get_int() >= 0);
3023   match(ConI);
3024 
3025   op_cost(0);
3026   format %{ %}
3027   interface(CONST_INTER);
3028 %}
3029 
3030 // Constant for long shifts
3031 operand immI_32()
3032 %{
3033   predicate( n->get_int() == 32 );
3034   match(ConI);
3035 
3036   op_cost(0);
3037   format %{ %}
3038   interface(CONST_INTER);
3039 %}
3040 
3041 // Constant for long shifts
3042 operand immI_64()
3043 %{
3044   predicate( n->get_int() == 64 );
3045   match(ConI);
3046 
3047   op_cost(0);
3048   format %{ %}
3049   interface(CONST_INTER);
3050 %}
3051 
3052 // Pointer Immediate
3053 operand immP()
3054 %{
3055   match(ConP);
3056 
3057   op_cost(10);
3058   format %{ %}
3059   interface(CONST_INTER);
3060 %}
3061 
3062 // NULL Pointer Immediate
3063 operand immP0()
3064 %{
3065   predicate(n->get_ptr() == 0);
3066   match(ConP);
3067 
3068   op_cost(5);
3069   format %{ %}
3070   interface(CONST_INTER);
3071 %}
3072 
3073 // Pointer Immediate
3074 operand immN() %{
3075   match(ConN);
3076 
3077   op_cost(10);
3078   format %{ %}
3079   interface(CONST_INTER);
3080 %}
3081 
3082 operand immNKlass() %{
3083   match(ConNKlass);
3084 
3085   op_cost(10);
3086   format %{ %}
3087   interface(CONST_INTER);
3088 %}
3089 
3090 // NULL Pointer Immediate
3091 operand immN0() %{
3092   predicate(n->get_narrowcon() == 0);
3093   match(ConN);
3094 
3095   op_cost(5);
3096   format %{ %}
3097   interface(CONST_INTER);
3098 %}
3099 
3100 operand immP31()
3101 %{
3102   predicate(n->as_Type()->type()->reloc() == relocInfo::none
3103             && (n->get_ptr() >> 31) == 0);
3104   match(ConP);
3105 
3106   op_cost(5);
3107   format %{ %}
3108   interface(CONST_INTER);
3109 %}
3110 
3111 
3112 // Long Immediate
3113 operand immL()
3114 %{
3115   match(ConL);
3116 
3117   op_cost(20);
3118   format %{ %}
3119   interface(CONST_INTER);
3120 %}
3121 
3122 // Long Immediate 8-bit
3123 operand immL8()
3124 %{
3125   predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3126   match(ConL);
3127 
3128   op_cost(5);
3129   format %{ %}
3130   interface(CONST_INTER);
3131 %}
3132 
3133 // Long Immediate 32-bit unsigned
3134 operand immUL32()
3135 %{
3136   predicate(n->get_long() == (unsigned int) (n->get_long()));
3137   match(ConL);
3138 
3139   op_cost(10);
3140   format %{ %}
3141   interface(CONST_INTER);
3142 %}
3143 
3144 // Long Immediate 32-bit signed
3145 operand immL32()
3146 %{
3147   predicate(n->get_long() == (int) (n->get_long()));
3148   match(ConL);
3149 
3150   op_cost(15);
3151   format %{ %}
3152   interface(CONST_INTER);
3153 %}
3154 
3155 // Long Immediate zero
3156 operand immL0()
3157 %{
3158   predicate(n->get_long() == 0L);
3159   match(ConL);
3160 
3161   op_cost(10);
3162   format %{ %}
3163   interface(CONST_INTER);
3164 %}
3165 
3166 // Constant for increment
3167 operand immL1()
3168 %{
3169   predicate(n->get_long() == 1);
3170   match(ConL);
3171 
3172   format %{ %}
3173   interface(CONST_INTER);
3174 %}
3175 
3176 // Constant for decrement
3177 operand immL_M1()
3178 %{
3179   predicate(n->get_long() == -1);
3180   match(ConL);
3181 
3182   format %{ %}
3183   interface(CONST_INTER);
3184 %}
3185 
3186 // Long Immediate: the value 10
3187 operand immL10()
3188 %{
3189   predicate(n->get_long() == 10);
3190   match(ConL);
3191 
3192   format %{ %}
3193   interface(CONST_INTER);
3194 %}
3195 
3196 // Long immediate from 0 to 127.
3197 // Used for a shorter form of long mul by 10.
3198 operand immL_127()
3199 %{
3200   predicate(0 <= n->get_long() && n->get_long() < 0x80);
3201   match(ConL);
3202 
3203   op_cost(10);
3204   format %{ %}
3205   interface(CONST_INTER);
3206 %}
3207 
3208 // Long Immediate: low 32-bit mask
3209 operand immL_32bits()
3210 %{
3211   predicate(n->get_long() == 0xFFFFFFFFL);
3212   match(ConL);
3213   op_cost(20);
3214 
3215   format %{ %}
3216   interface(CONST_INTER);
3217 %}
3218 
3219 // Float Immediate zero
3220 operand immF0()
3221 %{
3222   predicate(jint_cast(n->getf()) == 0);
3223   match(ConF);
3224 
3225   op_cost(5);
3226   format %{ %}
3227   interface(CONST_INTER);
3228 %}
3229 
3230 // Float Immediate
3231 operand immF()
3232 %{
3233   match(ConF);
3234 
3235   op_cost(15);
3236   format %{ %}
3237   interface(CONST_INTER);
3238 %}
3239 
3240 // Double Immediate zero
3241 operand immD0()
3242 %{
3243   predicate(jlong_cast(n->getd()) == 0);
3244   match(ConD);
3245 
3246   op_cost(5);
3247   format %{ %}
3248   interface(CONST_INTER);
3249 %}
3250 
3251 // Double Immediate
3252 operand immD()
3253 %{
3254   match(ConD);
3255 
3256   op_cost(15);
3257   format %{ %}
3258   interface(CONST_INTER);
3259 %}
3260 
3261 // Immediates for special shifts (sign extend)
3262 
3263 // Constants for increment
3264 operand immI_16()
3265 %{
3266   predicate(n->get_int() == 16);
3267   match(ConI);
3268 
3269   format %{ %}
3270   interface(CONST_INTER);
3271 %}
3272 
3273 operand immI_24()
3274 %{
3275   predicate(n->get_int() == 24);
3276   match(ConI);
3277 
3278   format %{ %}
3279   interface(CONST_INTER);
3280 %}
3281 
3282 // Constant for byte-wide masking
3283 operand immI_255()
3284 %{
3285   predicate(n->get_int() == 255);
3286   match(ConI);
3287 
3288   format %{ %}
3289   interface(CONST_INTER);
3290 %}
3291 
3292 // Constant for short-wide masking
3293 operand immI_65535()
3294 %{
3295   predicate(n->get_int() == 65535);
3296   match(ConI);
3297 
3298   format %{ %}
3299   interface(CONST_INTER);
3300 %}
3301 
3302 // Constant for byte-wide masking
3303 operand immL_255()
3304 %{
3305   predicate(n->get_long() == 255);
3306   match(ConL);
3307 
3308   format %{ %}
3309   interface(CONST_INTER);
3310 %}
3311 
3312 // Constant for short-wide masking
3313 operand immL_65535()
3314 %{
3315   predicate(n->get_long() == 65535);
3316   match(ConL);
3317 
3318   format %{ %}
3319   interface(CONST_INTER);
3320 %}
3321 
3322 // Register Operands
3323 // Integer Register
3324 operand rRegI()
3325 %{
3326   constraint(ALLOC_IN_RC(int_reg));
3327   match(RegI);
3328 
3329   match(rax_RegI);
3330   match(rbx_RegI);
3331   match(rcx_RegI);
3332   match(rdx_RegI);
3333   match(rdi_RegI);
3334 
3335   format %{ %}
3336   interface(REG_INTER);
3337 %}
3338 
3339 // Special Registers
3340 operand rax_RegI()
3341 %{
3342   constraint(ALLOC_IN_RC(int_rax_reg));
3343   match(RegI);
3344   match(rRegI);
3345 
3346   format %{ "RAX" %}
3347   interface(REG_INTER);
3348 %}
3349 
3350 // Special Registers
3351 operand rbx_RegI()
3352 %{
3353   constraint(ALLOC_IN_RC(int_rbx_reg));
3354   match(RegI);
3355   match(rRegI);
3356 
3357   format %{ "RBX" %}
3358   interface(REG_INTER);
3359 %}
3360 
3361 operand rcx_RegI()
3362 %{
3363   constraint(ALLOC_IN_RC(int_rcx_reg));
3364   match(RegI);
3365   match(rRegI);
3366 
3367   format %{ "RCX" %}
3368   interface(REG_INTER);
3369 %}
3370 
3371 operand rdx_RegI()
3372 %{
3373   constraint(ALLOC_IN_RC(int_rdx_reg));
3374   match(RegI);
3375   match(rRegI);
3376 
3377   format %{ "RDX" %}
3378   interface(REG_INTER);
3379 %}
3380 
3381 operand rdi_RegI()
3382 %{
3383   constraint(ALLOC_IN_RC(int_rdi_reg));
3384   match(RegI);
3385   match(rRegI);
3386 
3387   format %{ "RDI" %}
3388   interface(REG_INTER);
3389 %}
3390 
3391 operand no_rcx_RegI()
3392 %{
3393   constraint(ALLOC_IN_RC(int_no_rcx_reg));
3394   match(RegI);
3395   match(rax_RegI);
3396   match(rbx_RegI);
3397   match(rdx_RegI);
3398   match(rdi_RegI);
3399 
3400   format %{ %}
3401   interface(REG_INTER);
3402 %}
3403 
3404 operand no_rax_rdx_RegI()
3405 %{
3406   constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3407   match(RegI);
3408   match(rbx_RegI);
3409   match(rcx_RegI);
3410   match(rdi_RegI);
3411 
3412   format %{ %}
3413   interface(REG_INTER);
3414 %}
3415 
3416 // Pointer Register
3417 operand any_RegP()
3418 %{
3419   constraint(ALLOC_IN_RC(any_reg));
3420   match(RegP);
3421   match(rax_RegP);
3422   match(rbx_RegP);
3423   match(rdi_RegP);
3424   match(rsi_RegP);
3425   match(rbp_RegP);
3426   match(r15_RegP);
3427   match(rRegP);
3428 
3429   format %{ %}
3430   interface(REG_INTER);
3431 %}
3432 
3433 operand rRegP()
3434 %{
3435   constraint(ALLOC_IN_RC(ptr_reg));
3436   match(RegP);
3437   match(rax_RegP);
3438   match(rbx_RegP);
3439   match(rdi_RegP);
3440   match(rsi_RegP);
3441   match(rbp_RegP);  // See Q&A below about
3442   match(r15_RegP);  // r15_RegP and rbp_RegP.
3443 
3444   format %{ %}
3445   interface(REG_INTER);
3446 %}
3447 
3448 operand rRegN() %{
3449   constraint(ALLOC_IN_RC(int_reg));
3450   match(RegN);
3451 
3452   format %{ %}
3453   interface(REG_INTER);
3454 %}
3455 
3456 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3457 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3458 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3459 // The output of an instruction is controlled by the allocator, which respects
3460 // register class masks, not match rules.  Unless an instruction mentions
3461 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3462 // by the allocator as an input.
3463 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3464 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3465 // result, RBP is not included in the output of the instruction either.
3466 
3467 operand no_rax_RegP()
3468 %{
3469   constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3470   match(RegP);
3471   match(rbx_RegP);
3472   match(rsi_RegP);
3473   match(rdi_RegP);
3474 
3475   format %{ %}
3476   interface(REG_INTER);
3477 %}
3478 
3479 // This operand is not allowed to use RBP even if
3480 // RBP is not used to hold the frame pointer.
3481 operand no_rbp_RegP()
3482 %{
3483   constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3484   match(RegP);
3485   match(rbx_RegP);
3486   match(rsi_RegP);
3487   match(rdi_RegP);
3488 
3489   format %{ %}
3490   interface(REG_INTER);
3491 %}
3492 
3493 operand no_rax_rbx_RegP()
3494 %{
3495   constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3496   match(RegP);
3497   match(rsi_RegP);
3498   match(rdi_RegP);
3499 
3500   format %{ %}
3501   interface(REG_INTER);
3502 %}
3503 
3504 // Special Registers
3505 // Return a pointer value
3506 operand rax_RegP()
3507 %{
3508   constraint(ALLOC_IN_RC(ptr_rax_reg));
3509   match(RegP);
3510   match(rRegP);
3511 
3512   format %{ %}
3513   interface(REG_INTER);
3514 %}
3515 
3516 // Special Registers
3517 // Return a compressed pointer value
3518 operand rax_RegN()
3519 %{
3520   constraint(ALLOC_IN_RC(int_rax_reg));
3521   match(RegN);
3522   match(rRegN);
3523 
3524   format %{ %}
3525   interface(REG_INTER);
3526 %}
3527 
3528 // Used in AtomicAdd
3529 operand rbx_RegP()
3530 %{
3531   constraint(ALLOC_IN_RC(ptr_rbx_reg));
3532   match(RegP);
3533   match(rRegP);
3534 
3535   format %{ %}
3536   interface(REG_INTER);
3537 %}
3538 
3539 operand rsi_RegP()
3540 %{
3541   constraint(ALLOC_IN_RC(ptr_rsi_reg));
3542   match(RegP);
3543   match(rRegP);
3544 
3545   format %{ %}
3546   interface(REG_INTER);
3547 %}
3548 
3549 // Used in rep stosq
3550 operand rdi_RegP()
3551 %{
3552   constraint(ALLOC_IN_RC(ptr_rdi_reg));
3553   match(RegP);
3554   match(rRegP);
3555 
3556   format %{ %}
3557   interface(REG_INTER);
3558 %}
3559 
3560 operand r15_RegP()
3561 %{
3562   constraint(ALLOC_IN_RC(ptr_r15_reg));
3563   match(RegP);
3564   match(rRegP);
3565 
3566   format %{ %}
3567   interface(REG_INTER);
3568 %}
3569 
3570 operand rex_RegP()
3571 %{
3572   constraint(ALLOC_IN_RC(ptr_rex_reg));
3573   match(RegP);
3574   match(rRegP);
3575 
3576   format %{ %}
3577   interface(REG_INTER);
3578 %}
3579 
3580 operand rRegL()
3581 %{
3582   constraint(ALLOC_IN_RC(long_reg));
3583   match(RegL);
3584   match(rax_RegL);
3585   match(rdx_RegL);
3586 
3587   format %{ %}
3588   interface(REG_INTER);
3589 %}
3590 
3591 // Special Registers
3592 operand no_rax_rdx_RegL()
3593 %{
3594   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3595   match(RegL);
3596   match(rRegL);
3597 
3598   format %{ %}
3599   interface(REG_INTER);
3600 %}
3601 
3602 operand no_rax_RegL()
3603 %{
3604   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3605   match(RegL);
3606   match(rRegL);
3607   match(rdx_RegL);
3608 
3609   format %{ %}
3610   interface(REG_INTER);
3611 %}
3612 
3613 operand no_rcx_RegL()
3614 %{
3615   constraint(ALLOC_IN_RC(long_no_rcx_reg));
3616   match(RegL);
3617   match(rRegL);
3618 
3619   format %{ %}
3620   interface(REG_INTER);
3621 %}
3622 
3623 operand rax_RegL()
3624 %{
3625   constraint(ALLOC_IN_RC(long_rax_reg));
3626   match(RegL);
3627   match(rRegL);
3628 
3629   format %{ "RAX" %}
3630   interface(REG_INTER);
3631 %}
3632 
3633 operand rcx_RegL()
3634 %{
3635   constraint(ALLOC_IN_RC(long_rcx_reg));
3636   match(RegL);
3637   match(rRegL);
3638 
3639   format %{ %}
3640   interface(REG_INTER);
3641 %}
3642 
3643 operand rdx_RegL()
3644 %{
3645   constraint(ALLOC_IN_RC(long_rdx_reg));
3646   match(RegL);
3647   match(rRegL);
3648 
3649   format %{ %}
3650   interface(REG_INTER);
3651 %}
3652 
3653 // Flags register, used as output of compare instructions
3654 operand rFlagsReg()
3655 %{
3656   constraint(ALLOC_IN_RC(int_flags));
3657   match(RegFlags);
3658 
3659   format %{ "RFLAGS" %}
3660   interface(REG_INTER);
3661 %}
3662 
3663 // Flags register, used as output of FLOATING POINT compare instructions
3664 operand rFlagsRegU()
3665 %{
3666   constraint(ALLOC_IN_RC(int_flags));
3667   match(RegFlags);
3668 
3669   format %{ "RFLAGS_U" %}
3670   interface(REG_INTER);
3671 %}
3672 
3673 operand rFlagsRegUCF() %{
3674   constraint(ALLOC_IN_RC(int_flags));
3675   match(RegFlags);
3676   predicate(false);
3677 
3678   format %{ "RFLAGS_U_CF" %}
3679   interface(REG_INTER);
3680 %}
3681 
3682 // Float register operands
3683 operand regF() %{
3684    constraint(ALLOC_IN_RC(float_reg));
3685    match(RegF);
3686 
3687    format %{ %}
3688    interface(REG_INTER);
3689 %}
3690 
3691 // Float register operands
3692 operand vlRegF() %{
3693    constraint(ALLOC_IN_RC(float_reg_vl));
3694    match(RegF);
3695 
3696    format %{ %}
3697    interface(REG_INTER);
3698 %}
3699 
3700 // Double register operands
3701 operand regD() %{
3702    constraint(ALLOC_IN_RC(double_reg));
3703    match(RegD);
3704 
3705    format %{ %}
3706    interface(REG_INTER);
3707 %}
3708 
3709 // Double register operands
3710 operand vlRegD() %{
3711    constraint(ALLOC_IN_RC(double_reg_vl));
3712    match(RegD);
3713 
3714    format %{ %}
3715    interface(REG_INTER);
3716 %}
3717 
3718 // Vectors
3719 operand vecS() %{
3720   constraint(ALLOC_IN_RC(vectors_reg_vlbwdq));
3721   match(VecS);
3722 
3723   format %{ %}
3724   interface(REG_INTER);
3725 %}
3726 
3727 // Vectors
3728 operand legVecS() %{
3729   constraint(ALLOC_IN_RC(vectors_reg_legacy));
3730   match(VecS);
3731 
3732   format %{ %}
3733   interface(REG_INTER);
3734 %}
3735 
3736 operand vecD() %{
3737   constraint(ALLOC_IN_RC(vectord_reg_vlbwdq));
3738   match(VecD);
3739 
3740   format %{ %}
3741   interface(REG_INTER);
3742 %}
3743 
3744 operand legVecD() %{
3745   constraint(ALLOC_IN_RC(vectord_reg_legacy));
3746   match(VecD);
3747 
3748   format %{ %}
3749   interface(REG_INTER);
3750 %}
3751 
3752 operand vecX() %{
3753   constraint(ALLOC_IN_RC(vectorx_reg_vlbwdq));
3754   match(VecX);
3755 
3756   format %{ %}
3757   interface(REG_INTER);
3758 %}
3759 
3760 operand legVecX() %{
3761   constraint(ALLOC_IN_RC(vectorx_reg_legacy));
3762   match(VecX);
3763 
3764   format %{ %}
3765   interface(REG_INTER);
3766 %}
3767 
3768 operand vecY() %{
3769   constraint(ALLOC_IN_RC(vectory_reg_vlbwdq));
3770   match(VecY);
3771 
3772   format %{ %}
3773   interface(REG_INTER);
3774 %}
3775 
3776 operand legVecY() %{
3777   constraint(ALLOC_IN_RC(vectory_reg_legacy));
3778   match(VecY);
3779 
3780   format %{ %}
3781   interface(REG_INTER);
3782 %}
3783 
3784 //----------Memory Operands----------------------------------------------------
3785 // Direct Memory Operand
3786 // operand direct(immP addr)
3787 // %{
3788 //   match(addr);
3789 
3790 //   format %{ "[$addr]" %}
3791 //   interface(MEMORY_INTER) %{
3792 //     base(0xFFFFFFFF);
3793 //     index(0x4);
3794 //     scale(0x0);
3795 //     disp($addr);
3796 //   %}
3797 // %}
3798 
3799 // Indirect Memory Operand
3800 operand indirect(any_RegP reg)
3801 %{
3802   constraint(ALLOC_IN_RC(ptr_reg));
3803   match(reg);
3804 
3805   format %{ "[$reg]" %}
3806   interface(MEMORY_INTER) %{
3807     base($reg);
3808     index(0x4);
3809     scale(0x0);
3810     disp(0x0);
3811   %}
3812 %}
3813 
3814 // Indirect Memory Plus Short Offset Operand
3815 operand indOffset8(any_RegP reg, immL8 off)
3816 %{
3817   constraint(ALLOC_IN_RC(ptr_reg));
3818   match(AddP reg off);
3819 
3820   format %{ "[$reg + $off (8-bit)]" %}
3821   interface(MEMORY_INTER) %{
3822     base($reg);
3823     index(0x4);
3824     scale(0x0);
3825     disp($off);
3826   %}
3827 %}
3828 
3829 // Indirect Memory Plus Long Offset Operand
3830 operand indOffset32(any_RegP reg, immL32 off)
3831 %{
3832   constraint(ALLOC_IN_RC(ptr_reg));
3833   match(AddP reg off);
3834 
3835   format %{ "[$reg + $off (32-bit)]" %}
3836   interface(MEMORY_INTER) %{
3837     base($reg);
3838     index(0x4);
3839     scale(0x0);
3840     disp($off);
3841   %}
3842 %}
3843 
3844 // Indirect Memory Plus Index Register Plus Offset Operand
3845 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3846 %{
3847   constraint(ALLOC_IN_RC(ptr_reg));
3848   match(AddP (AddP reg lreg) off);
3849 
3850   op_cost(10);
3851   format %{"[$reg + $off + $lreg]" %}
3852   interface(MEMORY_INTER) %{
3853     base($reg);
3854     index($lreg);
3855     scale(0x0);
3856     disp($off);
3857   %}
3858 %}
3859 
3860 // Indirect Memory Plus Index Register Plus Offset Operand
3861 operand indIndex(any_RegP reg, rRegL lreg)
3862 %{
3863   constraint(ALLOC_IN_RC(ptr_reg));
3864   match(AddP reg lreg);
3865 
3866   op_cost(10);
3867   format %{"[$reg + $lreg]" %}
3868   interface(MEMORY_INTER) %{
3869     base($reg);
3870     index($lreg);
3871     scale(0x0);
3872     disp(0x0);
3873   %}
3874 %}
3875 
3876 // Indirect Memory Times Scale Plus Index Register
3877 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3878 %{
3879   constraint(ALLOC_IN_RC(ptr_reg));
3880   match(AddP reg (LShiftL lreg scale));
3881 
3882   op_cost(10);
3883   format %{"[$reg + $lreg << $scale]" %}
3884   interface(MEMORY_INTER) %{
3885     base($reg);
3886     index($lreg);
3887     scale($scale);
3888     disp(0x0);
3889   %}
3890 %}
3891 
3892 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3893 %{
3894   constraint(ALLOC_IN_RC(ptr_reg));
3895   predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3896   match(AddP reg (LShiftL (ConvI2L idx) scale));
3897 
3898   op_cost(10);
3899   format %{"[$reg + pos $idx << $scale]" %}
3900   interface(MEMORY_INTER) %{
3901     base($reg);
3902     index($idx);
3903     scale($scale);
3904     disp(0x0);
3905   %}
3906 %}
3907 
3908 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3909 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3910 %{
3911   constraint(ALLOC_IN_RC(ptr_reg));
3912   match(AddP (AddP reg (LShiftL lreg scale)) off);
3913 
3914   op_cost(10);
3915   format %{"[$reg + $off + $lreg << $scale]" %}
3916   interface(MEMORY_INTER) %{
3917     base($reg);
3918     index($lreg);
3919     scale($scale);
3920     disp($off);
3921   %}
3922 %}
3923 
3924 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3925 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3926 %{
3927   constraint(ALLOC_IN_RC(ptr_reg));
3928   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3929   match(AddP (AddP reg (ConvI2L idx)) off);
3930 
3931   op_cost(10);
3932   format %{"[$reg + $off + $idx]" %}
3933   interface(MEMORY_INTER) %{
3934     base($reg);
3935     index($idx);
3936     scale(0x0);
3937     disp($off);
3938   %}
3939 %}
3940 
3941 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3942 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3943 %{
3944   constraint(ALLOC_IN_RC(ptr_reg));
3945   predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3946   match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3947 
3948   op_cost(10);
3949   format %{"[$reg + $off + $idx << $scale]" %}
3950   interface(MEMORY_INTER) %{
3951     base($reg);
3952     index($idx);
3953     scale($scale);
3954     disp($off);
3955   %}
3956 %}
3957 
3958 // Indirect Narrow Oop Plus Offset Operand
3959 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3960 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3961 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3962   predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3963   constraint(ALLOC_IN_RC(ptr_reg));
3964   match(AddP (DecodeN reg) off);
3965 
3966   op_cost(10);
3967   format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3968   interface(MEMORY_INTER) %{
3969     base(0xc); // R12
3970     index($reg);
3971     scale(0x3);
3972     disp($off);
3973   %}
3974 %}
3975 
3976 // Indirect Memory Operand
3977 operand indirectNarrow(rRegN reg)
3978 %{
3979   predicate(Universe::narrow_oop_shift() == 0);
3980   constraint(ALLOC_IN_RC(ptr_reg));
3981   match(DecodeN reg);
3982 
3983   format %{ "[$reg]" %}
3984   interface(MEMORY_INTER) %{
3985     base($reg);
3986     index(0x4);
3987     scale(0x0);
3988     disp(0x0);
3989   %}
3990 %}
3991 
3992 // Indirect Memory Plus Short Offset Operand
3993 operand indOffset8Narrow(rRegN reg, immL8 off)
3994 %{
3995   predicate(Universe::narrow_oop_shift() == 0);
3996   constraint(ALLOC_IN_RC(ptr_reg));
3997   match(AddP (DecodeN reg) off);
3998 
3999   format %{ "[$reg + $off (8-bit)]" %}
4000   interface(MEMORY_INTER) %{
4001     base($reg);
4002     index(0x4);
4003     scale(0x0);
4004     disp($off);
4005   %}
4006 %}
4007 
4008 // Indirect Memory Plus Long Offset Operand
4009 operand indOffset32Narrow(rRegN reg, immL32 off)
4010 %{
4011   predicate(Universe::narrow_oop_shift() == 0);
4012   constraint(ALLOC_IN_RC(ptr_reg));
4013   match(AddP (DecodeN reg) off);
4014 
4015   format %{ "[$reg + $off (32-bit)]" %}
4016   interface(MEMORY_INTER) %{
4017     base($reg);
4018     index(0x4);
4019     scale(0x0);
4020     disp($off);
4021   %}
4022 %}
4023 
4024 // Indirect Memory Plus Index Register Plus Offset Operand
4025 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4026 %{
4027   predicate(Universe::narrow_oop_shift() == 0);
4028   constraint(ALLOC_IN_RC(ptr_reg));
4029   match(AddP (AddP (DecodeN reg) lreg) off);
4030 
4031   op_cost(10);
4032   format %{"[$reg + $off + $lreg]" %}
4033   interface(MEMORY_INTER) %{
4034     base($reg);
4035     index($lreg);
4036     scale(0x0);
4037     disp($off);
4038   %}
4039 %}
4040 
4041 // Indirect Memory Plus Index Register Plus Offset Operand
4042 operand indIndexNarrow(rRegN reg, rRegL lreg)
4043 %{
4044   predicate(Universe::narrow_oop_shift() == 0);
4045   constraint(ALLOC_IN_RC(ptr_reg));
4046   match(AddP (DecodeN reg) lreg);
4047 
4048   op_cost(10);
4049   format %{"[$reg + $lreg]" %}
4050   interface(MEMORY_INTER) %{
4051     base($reg);
4052     index($lreg);
4053     scale(0x0);
4054     disp(0x0);
4055   %}
4056 %}
4057 
4058 // Indirect Memory Times Scale Plus Index Register
4059 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4060 %{
4061   predicate(Universe::narrow_oop_shift() == 0);
4062   constraint(ALLOC_IN_RC(ptr_reg));
4063   match(AddP (DecodeN reg) (LShiftL lreg scale));
4064 
4065   op_cost(10);
4066   format %{"[$reg + $lreg << $scale]" %}
4067   interface(MEMORY_INTER) %{
4068     base($reg);
4069     index($lreg);
4070     scale($scale);
4071     disp(0x0);
4072   %}
4073 %}
4074 
4075 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4076 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4077 %{
4078   predicate(Universe::narrow_oop_shift() == 0);
4079   constraint(ALLOC_IN_RC(ptr_reg));
4080   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4081 
4082   op_cost(10);
4083   format %{"[$reg + $off + $lreg << $scale]" %}
4084   interface(MEMORY_INTER) %{
4085     base($reg);
4086     index($lreg);
4087     scale($scale);
4088     disp($off);
4089   %}
4090 %}
4091 
4092 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4093 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4094 %{
4095   constraint(ALLOC_IN_RC(ptr_reg));
4096   predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4097   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4098 
4099   op_cost(10);
4100   format %{"[$reg + $off + $idx]" %}
4101   interface(MEMORY_INTER) %{
4102     base($reg);
4103     index($idx);
4104     scale(0x0);
4105     disp($off);
4106   %}
4107 %}
4108 
4109 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4110 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4111 %{
4112   constraint(ALLOC_IN_RC(ptr_reg));
4113   predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4114   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4115 
4116   op_cost(10);
4117   format %{"[$reg + $off + $idx << $scale]" %}
4118   interface(MEMORY_INTER) %{
4119     base($reg);
4120     index($idx);
4121     scale($scale);
4122     disp($off);
4123   %}
4124 %}
4125 
4126 //----------Special Memory Operands--------------------------------------------
4127 // Stack Slot Operand - This operand is used for loading and storing temporary
4128 //                      values on the stack where a match requires a value to
4129 //                      flow through memory.
4130 operand stackSlotP(sRegP reg)
4131 %{
4132   constraint(ALLOC_IN_RC(stack_slots));
4133   // No match rule because this operand is only generated in matching
4134 
4135   format %{ "[$reg]" %}
4136   interface(MEMORY_INTER) %{
4137     base(0x4);   // RSP
4138     index(0x4);  // No Index
4139     scale(0x0);  // No Scale
4140     disp($reg);  // Stack Offset
4141   %}
4142 %}
4143 
4144 operand stackSlotI(sRegI reg)
4145 %{
4146   constraint(ALLOC_IN_RC(stack_slots));
4147   // No match rule because this operand is only generated in matching
4148 
4149   format %{ "[$reg]" %}
4150   interface(MEMORY_INTER) %{
4151     base(0x4);   // RSP
4152     index(0x4);  // No Index
4153     scale(0x0);  // No Scale
4154     disp($reg);  // Stack Offset
4155   %}
4156 %}
4157 
4158 operand stackSlotF(sRegF reg)
4159 %{
4160   constraint(ALLOC_IN_RC(stack_slots));
4161   // No match rule because this operand is only generated in matching
4162 
4163   format %{ "[$reg]" %}
4164   interface(MEMORY_INTER) %{
4165     base(0x4);   // RSP
4166     index(0x4);  // No Index
4167     scale(0x0);  // No Scale
4168     disp($reg);  // Stack Offset
4169   %}
4170 %}
4171 
4172 operand stackSlotD(sRegD reg)
4173 %{
4174   constraint(ALLOC_IN_RC(stack_slots));
4175   // No match rule because this operand is only generated in matching
4176 
4177   format %{ "[$reg]" %}
4178   interface(MEMORY_INTER) %{
4179     base(0x4);   // RSP
4180     index(0x4);  // No Index
4181     scale(0x0);  // No Scale
4182     disp($reg);  // Stack Offset
4183   %}
4184 %}
4185 operand stackSlotL(sRegL reg)
4186 %{
4187   constraint(ALLOC_IN_RC(stack_slots));
4188   // No match rule because this operand is only generated in matching
4189 
4190   format %{ "[$reg]" %}
4191   interface(MEMORY_INTER) %{
4192     base(0x4);   // RSP
4193     index(0x4);  // No Index
4194     scale(0x0);  // No Scale
4195     disp($reg);  // Stack Offset
4196   %}
4197 %}
4198 
4199 //----------Conditional Branch Operands----------------------------------------
4200 // Comparison Op  - This is the operation of the comparison, and is limited to
4201 //                  the following set of codes:
4202 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4203 //
4204 // Other attributes of the comparison, such as unsignedness, are specified
4205 // by the comparison instruction that sets a condition code flags register.
4206 // That result is represented by a flags operand whose subtype is appropriate
4207 // to the unsignedness (etc.) of the comparison.
4208 //
4209 // Later, the instruction which matches both the Comparison Op (a Bool) and
4210 // the flags (produced by the Cmp) specifies the coding of the comparison op
4211 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4212 
4213 // Comparision Code
4214 operand cmpOp()
4215 %{
4216   match(Bool);
4217 
4218   format %{ "" %}
4219   interface(COND_INTER) %{
4220     equal(0x4, "e");
4221     not_equal(0x5, "ne");
4222     less(0xC, "l");
4223     greater_equal(0xD, "ge");
4224     less_equal(0xE, "le");
4225     greater(0xF, "g");
4226     overflow(0x0, "o");
4227     no_overflow(0x1, "no");
4228   %}
4229 %}
4230 
4231 // Comparison Code, unsigned compare.  Used by FP also, with
4232 // C2 (unordered) turned into GT or LT already.  The other bits
4233 // C0 and C3 are turned into Carry & Zero flags.
4234 operand cmpOpU()
4235 %{
4236   match(Bool);
4237 
4238   format %{ "" %}
4239   interface(COND_INTER) %{
4240     equal(0x4, "e");
4241     not_equal(0x5, "ne");
4242     less(0x2, "b");
4243     greater_equal(0x3, "nb");
4244     less_equal(0x6, "be");
4245     greater(0x7, "nbe");
4246     overflow(0x0, "o");
4247     no_overflow(0x1, "no");
4248   %}
4249 %}
4250 
4251 
4252 // Floating comparisons that don't require any fixup for the unordered case
4253 operand cmpOpUCF() %{
4254   match(Bool);
4255   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4256             n->as_Bool()->_test._test == BoolTest::ge ||
4257             n->as_Bool()->_test._test == BoolTest::le ||
4258             n->as_Bool()->_test._test == BoolTest::gt);
4259   format %{ "" %}
4260   interface(COND_INTER) %{
4261     equal(0x4, "e");
4262     not_equal(0x5, "ne");
4263     less(0x2, "b");
4264     greater_equal(0x3, "nb");
4265     less_equal(0x6, "be");
4266     greater(0x7, "nbe");
4267     overflow(0x0, "o");
4268     no_overflow(0x1, "no");
4269   %}
4270 %}
4271 
4272 
4273 // Floating comparisons that can be fixed up with extra conditional jumps
4274 operand cmpOpUCF2() %{
4275   match(Bool);
4276   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4277             n->as_Bool()->_test._test == BoolTest::eq);
4278   format %{ "" %}
4279   interface(COND_INTER) %{
4280     equal(0x4, "e");
4281     not_equal(0x5, "ne");
4282     less(0x2, "b");
4283     greater_equal(0x3, "nb");
4284     less_equal(0x6, "be");
4285     greater(0x7, "nbe");
4286     overflow(0x0, "o");
4287     no_overflow(0x1, "no");
4288   %}
4289 %}
4290 
4291 // Operands for bound floating pointer register arguments
4292 operand rxmm0() %{
4293   constraint(ALLOC_IN_RC(xmm0_reg));  match(VecX);
4294   predicate((UseSSE > 0) && (UseAVX<= 2));  format%{%}  interface(REG_INTER);
4295 %}
4296 operand rxmm1() %{
4297   constraint(ALLOC_IN_RC(xmm1_reg));  match(VecX);
4298   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4299 %}
4300 operand rxmm2() %{
4301   constraint(ALLOC_IN_RC(xmm2_reg));  match(VecX);
4302   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4303 %}
4304 operand rxmm3() %{
4305   constraint(ALLOC_IN_RC(xmm3_reg));  match(VecX);
4306   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4307 %}
4308 operand rxmm4() %{
4309   constraint(ALLOC_IN_RC(xmm4_reg));  match(VecX);
4310   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4311 %}
4312 operand rxmm5() %{
4313   constraint(ALLOC_IN_RC(xmm5_reg));  match(VecX);
4314   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4315 %}
4316 operand rxmm6() %{
4317   constraint(ALLOC_IN_RC(xmm6_reg));  match(VecX);
4318   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4319 %}
4320 operand rxmm7() %{
4321   constraint(ALLOC_IN_RC(xmm7_reg));  match(VecX);
4322   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4323 %}
4324 operand rxmm8() %{
4325   constraint(ALLOC_IN_RC(xmm8_reg));  match(VecX);
4326   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4327 %}
4328 operand rxmm9() %{
4329   constraint(ALLOC_IN_RC(xmm9_reg));  match(VecX);
4330   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4331 %}
4332 operand rxmm10() %{
4333   constraint(ALLOC_IN_RC(xmm10_reg));  match(VecX);
4334   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4335 %}
4336 operand rxmm11() %{
4337   constraint(ALLOC_IN_RC(xmm11_reg));  match(VecX);
4338   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4339 %}
4340 operand rxmm12() %{
4341   constraint(ALLOC_IN_RC(xmm12_reg));  match(VecX);
4342   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4343 %}
4344 operand rxmm13() %{
4345   constraint(ALLOC_IN_RC(xmm13_reg));  match(VecX);
4346   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4347 %}
4348 operand rxmm14() %{
4349   constraint(ALLOC_IN_RC(xmm14_reg));  match(VecX);
4350   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4351 %}
4352 operand rxmm15() %{
4353   constraint(ALLOC_IN_RC(xmm15_reg));  match(VecX);
4354   predicate((UseSSE > 0) && (UseAVX <= 2));  format%{%}  interface(REG_INTER);
4355 %}
4356 operand rxmm16() %{
4357   constraint(ALLOC_IN_RC(xmm16_reg));  match(VecX);
4358   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4359 %}
4360 operand rxmm17() %{
4361   constraint(ALLOC_IN_RC(xmm17_reg));  match(VecX);
4362   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4363 %}
4364 operand rxmm18() %{
4365   constraint(ALLOC_IN_RC(xmm18_reg));  match(VecX);
4366   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4367 %}
4368 operand rxmm19() %{
4369   constraint(ALLOC_IN_RC(xmm19_reg));  match(VecX);
4370   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4371 %}
4372 operand rxmm20() %{
4373   constraint(ALLOC_IN_RC(xmm20_reg));  match(VecX);
4374   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4375 %}
4376 operand rxmm21() %{
4377   constraint(ALLOC_IN_RC(xmm21_reg));  match(VecX);
4378   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4379 %}
4380 operand rxmm22() %{
4381   constraint(ALLOC_IN_RC(xmm22_reg));  match(VecX);
4382   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4383 %}
4384 operand rxmm23() %{
4385   constraint(ALLOC_IN_RC(xmm23_reg));  match(VecX);
4386   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4387 %}
4388 operand rxmm24() %{
4389   constraint(ALLOC_IN_RC(xmm24_reg));  match(VecX);
4390   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4391 %}
4392 operand rxmm25() %{
4393   constraint(ALLOC_IN_RC(xmm25_reg));  match(VecX);
4394   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4395 %}
4396 operand rxmm26() %{
4397   constraint(ALLOC_IN_RC(xmm26_reg));  match(VecX);
4398   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4399 %}
4400 operand rxmm27() %{
4401   constraint(ALLOC_IN_RC(xmm27_reg));  match(VecX);
4402   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4403 %}
4404 operand rxmm28() %{
4405   constraint(ALLOC_IN_RC(xmm28_reg));  match(VecX);
4406   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4407 %}
4408 operand rxmm29() %{
4409   constraint(ALLOC_IN_RC(xmm29_reg));  match(VecX);
4410   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4411 %}
4412 operand rxmm30() %{
4413   constraint(ALLOC_IN_RC(xmm30_reg));  match(VecX);
4414   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4415 %}
4416 operand rxmm31() %{
4417   constraint(ALLOC_IN_RC(xmm31_reg));  match(VecX);
4418   predicate(UseAVX == 3);  format%{%}  interface(REG_INTER);
4419 %}
4420 
4421 //----------OPERAND CLASSES----------------------------------------------------
4422 // Operand Classes are groups of operands that are used as to simplify
4423 // instruction definitions by not requiring the AD writer to specify separate
4424 // instructions for every form of operand when the instruction accepts
4425 // multiple operand types with the same basic encoding and format.  The classic
4426 // case of this is memory operands.
4427 
4428 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4429                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4430                indCompressedOopOffset,
4431                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4432                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4433                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4434 
4435 //----------PIPELINE-----------------------------------------------------------
4436 // Rules which define the behavior of the target architectures pipeline.
4437 pipeline %{
4438 
4439 //----------ATTRIBUTES---------------------------------------------------------
4440 attributes %{
4441   variable_size_instructions;        // Fixed size instructions
4442   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
4443   instruction_unit_size = 1;         // An instruction is 1 bytes long
4444   instruction_fetch_unit_size = 16;  // The processor fetches one line
4445   instruction_fetch_units = 1;       // of 16 bytes
4446 
4447   // List of nop instructions
4448   nops( MachNop );
4449 %}
4450 
4451 //----------RESOURCES----------------------------------------------------------
4452 // Resources are the functional units available to the machine
4453 
4454 // Generic P2/P3 pipeline
4455 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4456 // 3 instructions decoded per cycle.
4457 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4458 // 3 ALU op, only ALU0 handles mul instructions.
4459 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4460            MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4461            BR, FPU,
4462            ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4463 
4464 //----------PIPELINE DESCRIPTION-----------------------------------------------
4465 // Pipeline Description specifies the stages in the machine's pipeline
4466 
4467 // Generic P2/P3 pipeline
4468 pipe_desc(S0, S1, S2, S3, S4, S5);
4469 
4470 //----------PIPELINE CLASSES---------------------------------------------------
4471 // Pipeline Classes describe the stages in which input and output are
4472 // referenced by the hardware pipeline.
4473 
4474 // Naming convention: ialu or fpu
4475 // Then: _reg
4476 // Then: _reg if there is a 2nd register
4477 // Then: _long if it's a pair of instructions implementing a long
4478 // Then: _fat if it requires the big decoder
4479 //   Or: _mem if it requires the big decoder and a memory unit.
4480 
4481 // Integer ALU reg operation
4482 pipe_class ialu_reg(rRegI dst)
4483 %{
4484     single_instruction;
4485     dst    : S4(write);
4486     dst    : S3(read);
4487     DECODE : S0;        // any decoder
4488     ALU    : S3;        // any alu
4489 %}
4490 
4491 // Long ALU reg operation
4492 pipe_class ialu_reg_long(rRegL dst)
4493 %{
4494     instruction_count(2);
4495     dst    : S4(write);
4496     dst    : S3(read);
4497     DECODE : S0(2);     // any 2 decoders
4498     ALU    : S3(2);     // both alus
4499 %}
4500 
4501 // Integer ALU reg operation using big decoder
4502 pipe_class ialu_reg_fat(rRegI dst)
4503 %{
4504     single_instruction;
4505     dst    : S4(write);
4506     dst    : S3(read);
4507     D0     : S0;        // big decoder only
4508     ALU    : S3;        // any alu
4509 %}
4510 
4511 // Long ALU reg operation using big decoder
4512 pipe_class ialu_reg_long_fat(rRegL dst)
4513 %{
4514     instruction_count(2);
4515     dst    : S4(write);
4516     dst    : S3(read);
4517     D0     : S0(2);     // big decoder only; twice
4518     ALU    : S3(2);     // any 2 alus
4519 %}
4520 
4521 // Integer ALU reg-reg operation
4522 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4523 %{
4524     single_instruction;
4525     dst    : S4(write);
4526     src    : S3(read);
4527     DECODE : S0;        // any decoder
4528     ALU    : S3;        // any alu
4529 %}
4530 
4531 // Long ALU reg-reg operation
4532 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4533 %{
4534     instruction_count(2);
4535     dst    : S4(write);
4536     src    : S3(read);
4537     DECODE : S0(2);     // any 2 decoders
4538     ALU    : S3(2);     // both alus
4539 %}
4540 
4541 // Integer ALU reg-reg operation
4542 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4543 %{
4544     single_instruction;
4545     dst    : S4(write);
4546     src    : S3(read);
4547     D0     : S0;        // big decoder only
4548     ALU    : S3;        // any alu
4549 %}
4550 
4551 // Long ALU reg-reg operation
4552 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4553 %{
4554     instruction_count(2);
4555     dst    : S4(write);
4556     src    : S3(read);
4557     D0     : S0(2);     // big decoder only; twice
4558     ALU    : S3(2);     // both alus
4559 %}
4560 
4561 // Integer ALU reg-mem operation
4562 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4563 %{
4564     single_instruction;
4565     dst    : S5(write);
4566     mem    : S3(read);
4567     D0     : S0;        // big decoder only
4568     ALU    : S4;        // any alu
4569     MEM    : S3;        // any mem
4570 %}
4571 
4572 // Integer mem operation (prefetch)
4573 pipe_class ialu_mem(memory mem)
4574 %{
4575     single_instruction;
4576     mem    : S3(read);
4577     D0     : S0;        // big decoder only
4578     MEM    : S3;        // any mem
4579 %}
4580 
4581 // Integer Store to Memory
4582 pipe_class ialu_mem_reg(memory mem, rRegI src)
4583 %{
4584     single_instruction;
4585     mem    : S3(read);
4586     src    : S5(read);
4587     D0     : S0;        // big decoder only
4588     ALU    : S4;        // any alu
4589     MEM    : S3;
4590 %}
4591 
4592 // // Long Store to Memory
4593 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4594 // %{
4595 //     instruction_count(2);
4596 //     mem    : S3(read);
4597 //     src    : S5(read);
4598 //     D0     : S0(2);          // big decoder only; twice
4599 //     ALU    : S4(2);     // any 2 alus
4600 //     MEM    : S3(2);  // Both mems
4601 // %}
4602 
4603 // Integer Store to Memory
4604 pipe_class ialu_mem_imm(memory mem)
4605 %{
4606     single_instruction;
4607     mem    : S3(read);
4608     D0     : S0;        // big decoder only
4609     ALU    : S4;        // any alu
4610     MEM    : S3;
4611 %}
4612 
4613 // Integer ALU0 reg-reg operation
4614 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4615 %{
4616     single_instruction;
4617     dst    : S4(write);
4618     src    : S3(read);
4619     D0     : S0;        // Big decoder only
4620     ALU0   : S3;        // only alu0
4621 %}
4622 
4623 // Integer ALU0 reg-mem operation
4624 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4625 %{
4626     single_instruction;
4627     dst    : S5(write);
4628     mem    : S3(read);
4629     D0     : S0;        // big decoder only
4630     ALU0   : S4;        // ALU0 only
4631     MEM    : S3;        // any mem
4632 %}
4633 
4634 // Integer ALU reg-reg operation
4635 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4636 %{
4637     single_instruction;
4638     cr     : S4(write);
4639     src1   : S3(read);
4640     src2   : S3(read);
4641     DECODE : S0;        // any decoder
4642     ALU    : S3;        // any alu
4643 %}
4644 
4645 // Integer ALU reg-imm operation
4646 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4647 %{
4648     single_instruction;
4649     cr     : S4(write);
4650     src1   : S3(read);
4651     DECODE : S0;        // any decoder
4652     ALU    : S3;        // any alu
4653 %}
4654 
4655 // Integer ALU reg-mem operation
4656 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4657 %{
4658     single_instruction;
4659     cr     : S4(write);
4660     src1   : S3(read);
4661     src2   : S3(read);
4662     D0     : S0;        // big decoder only
4663     ALU    : S4;        // any alu
4664     MEM    : S3;
4665 %}
4666 
4667 // Conditional move reg-reg
4668 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4669 %{
4670     instruction_count(4);
4671     y      : S4(read);
4672     q      : S3(read);
4673     p      : S3(read);
4674     DECODE : S0(4);     // any decoder
4675 %}
4676 
4677 // Conditional move reg-reg
4678 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4679 %{
4680     single_instruction;
4681     dst    : S4(write);
4682     src    : S3(read);
4683     cr     : S3(read);
4684     DECODE : S0;        // any decoder
4685 %}
4686 
4687 // Conditional move reg-mem
4688 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4689 %{
4690     single_instruction;
4691     dst    : S4(write);
4692     src    : S3(read);
4693     cr     : S3(read);
4694     DECODE : S0;        // any decoder
4695     MEM    : S3;
4696 %}
4697 
4698 // Conditional move reg-reg long
4699 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4700 %{
4701     single_instruction;
4702     dst    : S4(write);
4703     src    : S3(read);
4704     cr     : S3(read);
4705     DECODE : S0(2);     // any 2 decoders
4706 %}
4707 
4708 // XXX
4709 // // Conditional move double reg-reg
4710 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4711 // %{
4712 //     single_instruction;
4713 //     dst    : S4(write);
4714 //     src    : S3(read);
4715 //     cr     : S3(read);
4716 //     DECODE : S0;     // any decoder
4717 // %}
4718 
4719 // Float reg-reg operation
4720 pipe_class fpu_reg(regD dst)
4721 %{
4722     instruction_count(2);
4723     dst    : S3(read);
4724     DECODE : S0(2);     // any 2 decoders
4725     FPU    : S3;
4726 %}
4727 
4728 // Float reg-reg operation
4729 pipe_class fpu_reg_reg(regD dst, regD src)
4730 %{
4731     instruction_count(2);
4732     dst    : S4(write);
4733     src    : S3(read);
4734     DECODE : S0(2);     // any 2 decoders
4735     FPU    : S3;
4736 %}
4737 
4738 // Float reg-reg operation
4739 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4740 %{
4741     instruction_count(3);
4742     dst    : S4(write);
4743     src1   : S3(read);
4744     src2   : S3(read);
4745     DECODE : S0(3);     // any 3 decoders
4746     FPU    : S3(2);
4747 %}
4748 
4749 // Float reg-reg operation
4750 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4751 %{
4752     instruction_count(4);
4753     dst    : S4(write);
4754     src1   : S3(read);
4755     src2   : S3(read);
4756     src3   : S3(read);
4757     DECODE : S0(4);     // any 3 decoders
4758     FPU    : S3(2);
4759 %}
4760 
4761 // Float reg-reg operation
4762 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4763 %{
4764     instruction_count(4);
4765     dst    : S4(write);
4766     src1   : S3(read);
4767     src2   : S3(read);
4768     src3   : S3(read);
4769     DECODE : S1(3);     // any 3 decoders
4770     D0     : S0;        // Big decoder only
4771     FPU    : S3(2);
4772     MEM    : S3;
4773 %}
4774 
4775 // Float reg-mem operation
4776 pipe_class fpu_reg_mem(regD dst, memory mem)
4777 %{
4778     instruction_count(2);
4779     dst    : S5(write);
4780     mem    : S3(read);
4781     D0     : S0;        // big decoder only
4782     DECODE : S1;        // any decoder for FPU POP
4783     FPU    : S4;
4784     MEM    : S3;        // any mem
4785 %}
4786 
4787 // Float reg-mem operation
4788 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4789 %{
4790     instruction_count(3);
4791     dst    : S5(write);
4792     src1   : S3(read);
4793     mem    : S3(read);
4794     D0     : S0;        // big decoder only
4795     DECODE : S1(2);     // any decoder for FPU POP
4796     FPU    : S4;
4797     MEM    : S3;        // any mem
4798 %}
4799 
4800 // Float mem-reg operation
4801 pipe_class fpu_mem_reg(memory mem, regD src)
4802 %{
4803     instruction_count(2);
4804     src    : S5(read);
4805     mem    : S3(read);
4806     DECODE : S0;        // any decoder for FPU PUSH
4807     D0     : S1;        // big decoder only
4808     FPU    : S4;
4809     MEM    : S3;        // any mem
4810 %}
4811 
4812 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4813 %{
4814     instruction_count(3);
4815     src1   : S3(read);
4816     src2   : S3(read);
4817     mem    : S3(read);
4818     DECODE : S0(2);     // any decoder for FPU PUSH
4819     D0     : S1;        // big decoder only
4820     FPU    : S4;
4821     MEM    : S3;        // any mem
4822 %}
4823 
4824 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4825 %{
4826     instruction_count(3);
4827     src1   : S3(read);
4828     src2   : S3(read);
4829     mem    : S4(read);
4830     DECODE : S0;        // any decoder for FPU PUSH
4831     D0     : S0(2);     // big decoder only
4832     FPU    : S4;
4833     MEM    : S3(2);     // any mem
4834 %}
4835 
4836 pipe_class fpu_mem_mem(memory dst, memory src1)
4837 %{
4838     instruction_count(2);
4839     src1   : S3(read);
4840     dst    : S4(read);
4841     D0     : S0(2);     // big decoder only
4842     MEM    : S3(2);     // any mem
4843 %}
4844 
4845 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4846 %{
4847     instruction_count(3);
4848     src1   : S3(read);
4849     src2   : S3(read);
4850     dst    : S4(read);
4851     D0     : S0(3);     // big decoder only
4852     FPU    : S4;
4853     MEM    : S3(3);     // any mem
4854 %}
4855 
4856 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4857 %{
4858     instruction_count(3);
4859     src1   : S4(read);
4860     mem    : S4(read);
4861     DECODE : S0;        // any decoder for FPU PUSH
4862     D0     : S0(2);     // big decoder only
4863     FPU    : S4;
4864     MEM    : S3(2);     // any mem
4865 %}
4866 
4867 // Float load constant
4868 pipe_class fpu_reg_con(regD dst)
4869 %{
4870     instruction_count(2);
4871     dst    : S5(write);
4872     D0     : S0;        // big decoder only for the load
4873     DECODE : S1;        // any decoder for FPU POP
4874     FPU    : S4;
4875     MEM    : S3;        // any mem
4876 %}
4877 
4878 // Float load constant
4879 pipe_class fpu_reg_reg_con(regD dst, regD src)
4880 %{
4881     instruction_count(3);
4882     dst    : S5(write);
4883     src    : S3(read);
4884     D0     : S0;        // big decoder only for the load
4885     DECODE : S1(2);     // any decoder for FPU POP
4886     FPU    : S4;
4887     MEM    : S3;        // any mem
4888 %}
4889 
4890 // UnConditional branch
4891 pipe_class pipe_jmp(label labl)
4892 %{
4893     single_instruction;
4894     BR   : S3;
4895 %}
4896 
4897 // Conditional branch
4898 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4899 %{
4900     single_instruction;
4901     cr    : S1(read);
4902     BR    : S3;
4903 %}
4904 
4905 // Allocation idiom
4906 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4907 %{
4908     instruction_count(1); force_serialization;
4909     fixed_latency(6);
4910     heap_ptr : S3(read);
4911     DECODE   : S0(3);
4912     D0       : S2;
4913     MEM      : S3;
4914     ALU      : S3(2);
4915     dst      : S5(write);
4916     BR       : S5;
4917 %}
4918 
4919 // Generic big/slow expanded idiom
4920 pipe_class pipe_slow()
4921 %{
4922     instruction_count(10); multiple_bundles; force_serialization;
4923     fixed_latency(100);
4924     D0  : S0(2);
4925     MEM : S3(2);
4926 %}
4927 
4928 // The real do-nothing guy
4929 pipe_class empty()
4930 %{
4931     instruction_count(0);
4932 %}
4933 
4934 // Define the class for the Nop node
4935 define
4936 %{
4937    MachNop = empty;
4938 %}
4939 
4940 %}
4941 
4942 //----------INSTRUCTIONS-------------------------------------------------------
4943 //
4944 // match      -- States which machine-independent subtree may be replaced
4945 //               by this instruction.
4946 // ins_cost   -- The estimated cost of this instruction is used by instruction
4947 //               selection to identify a minimum cost tree of machine
4948 //               instructions that matches a tree of machine-independent
4949 //               instructions.
4950 // format     -- A string providing the disassembly for this instruction.
4951 //               The value of an instruction's operand may be inserted
4952 //               by referring to it with a '$' prefix.
4953 // opcode     -- Three instruction opcodes may be provided.  These are referred
4954 //               to within an encode class as $primary, $secondary, and $tertiary
4955 //               rrspectively.  The primary opcode is commonly used to
4956 //               indicate the type of machine instruction, while secondary
4957 //               and tertiary are often used for prefix options or addressing
4958 //               modes.
4959 // ins_encode -- A list of encode classes with parameters. The encode class
4960 //               name must have been defined in an 'enc_class' specification
4961 //               in the encode section of the architecture description.
4962 
4963 
4964 //----------Load/Store/Move Instructions---------------------------------------
4965 //----------Load Instructions--------------------------------------------------
4966 
4967 // Load Byte (8 bit signed)
4968 instruct loadB(rRegI dst, memory mem)
4969 %{
4970   match(Set dst (LoadB mem));
4971 
4972   ins_cost(125);
4973   format %{ "movsbl  $dst, $mem\t# byte" %}
4974 
4975   ins_encode %{
4976     __ movsbl($dst$$Register, $mem$$Address);
4977   %}
4978 
4979   ins_pipe(ialu_reg_mem);
4980 %}
4981 
4982 // Load Byte (8 bit signed) into Long Register
4983 instruct loadB2L(rRegL dst, memory mem)
4984 %{
4985   match(Set dst (ConvI2L (LoadB mem)));
4986 
4987   ins_cost(125);
4988   format %{ "movsbq  $dst, $mem\t# byte -> long" %}
4989 
4990   ins_encode %{
4991     __ movsbq($dst$$Register, $mem$$Address);
4992   %}
4993 
4994   ins_pipe(ialu_reg_mem);
4995 %}
4996 
4997 // Load Unsigned Byte (8 bit UNsigned)
4998 instruct loadUB(rRegI dst, memory mem)
4999 %{
5000   match(Set dst (LoadUB mem));
5001 
5002   ins_cost(125);
5003   format %{ "movzbl  $dst, $mem\t# ubyte" %}
5004 
5005   ins_encode %{
5006     __ movzbl($dst$$Register, $mem$$Address);
5007   %}
5008 
5009   ins_pipe(ialu_reg_mem);
5010 %}
5011 
5012 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5013 instruct loadUB2L(rRegL dst, memory mem)
5014 %{
5015   match(Set dst (ConvI2L (LoadUB mem)));
5016 
5017   ins_cost(125);
5018   format %{ "movzbq  $dst, $mem\t# ubyte -> long" %}
5019 
5020   ins_encode %{
5021     __ movzbq($dst$$Register, $mem$$Address);
5022   %}
5023 
5024   ins_pipe(ialu_reg_mem);
5025 %}
5026 
5027 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5028 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5029   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5030   effect(KILL cr);
5031 
5032   format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
5033             "andl    $dst, right_n_bits($mask, 8)" %}
5034   ins_encode %{
5035     Register Rdst = $dst$$Register;
5036     __ movzbq(Rdst, $mem$$Address);
5037     __ andl(Rdst, $mask$$constant & right_n_bits(8));
5038   %}
5039   ins_pipe(ialu_reg_mem);
5040 %}
5041 
5042 // Load Short (16 bit signed)
5043 instruct loadS(rRegI dst, memory mem)
5044 %{
5045   match(Set dst (LoadS mem));
5046 
5047   ins_cost(125);
5048   format %{ "movswl $dst, $mem\t# short" %}
5049 
5050   ins_encode %{
5051     __ movswl($dst$$Register, $mem$$Address);
5052   %}
5053 
5054   ins_pipe(ialu_reg_mem);
5055 %}
5056 
5057 // Load Short (16 bit signed) to Byte (8 bit signed)
5058 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5059   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5060 
5061   ins_cost(125);
5062   format %{ "movsbl $dst, $mem\t# short -> byte" %}
5063   ins_encode %{
5064     __ movsbl($dst$$Register, $mem$$Address);
5065   %}
5066   ins_pipe(ialu_reg_mem);
5067 %}
5068 
5069 // Load Short (16 bit signed) into Long Register
5070 instruct loadS2L(rRegL dst, memory mem)
5071 %{
5072   match(Set dst (ConvI2L (LoadS mem)));
5073 
5074   ins_cost(125);
5075   format %{ "movswq $dst, $mem\t# short -> long" %}
5076 
5077   ins_encode %{
5078     __ movswq($dst$$Register, $mem$$Address);
5079   %}
5080 
5081   ins_pipe(ialu_reg_mem);
5082 %}
5083 
5084 // Load Unsigned Short/Char (16 bit UNsigned)
5085 instruct loadUS(rRegI dst, memory mem)
5086 %{
5087   match(Set dst (LoadUS mem));
5088 
5089   ins_cost(125);
5090   format %{ "movzwl  $dst, $mem\t# ushort/char" %}
5091 
5092   ins_encode %{
5093     __ movzwl($dst$$Register, $mem$$Address);
5094   %}
5095 
5096   ins_pipe(ialu_reg_mem);
5097 %}
5098 
5099 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5100 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5101   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5102 
5103   ins_cost(125);
5104   format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5105   ins_encode %{
5106     __ movsbl($dst$$Register, $mem$$Address);
5107   %}
5108   ins_pipe(ialu_reg_mem);
5109 %}
5110 
5111 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5112 instruct loadUS2L(rRegL dst, memory mem)
5113 %{
5114   match(Set dst (ConvI2L (LoadUS mem)));
5115 
5116   ins_cost(125);
5117   format %{ "movzwq  $dst, $mem\t# ushort/char -> long" %}
5118 
5119   ins_encode %{
5120     __ movzwq($dst$$Register, $mem$$Address);
5121   %}
5122 
5123   ins_pipe(ialu_reg_mem);
5124 %}
5125 
5126 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5127 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5128   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5129 
5130   format %{ "movzbq  $dst, $mem\t# ushort/char & 0xFF -> long" %}
5131   ins_encode %{
5132     __ movzbq($dst$$Register, $mem$$Address);
5133   %}
5134   ins_pipe(ialu_reg_mem);
5135 %}
5136 
5137 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5138 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5139   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5140   effect(KILL cr);
5141 
5142   format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5143             "andl    $dst, right_n_bits($mask, 16)" %}
5144   ins_encode %{
5145     Register Rdst = $dst$$Register;
5146     __ movzwq(Rdst, $mem$$Address);
5147     __ andl(Rdst, $mask$$constant & right_n_bits(16));
5148   %}
5149   ins_pipe(ialu_reg_mem);
5150 %}
5151 
5152 // Load Integer
5153 instruct loadI(rRegI dst, memory mem)
5154 %{
5155   match(Set dst (LoadI mem));
5156 
5157   ins_cost(125);
5158   format %{ "movl    $dst, $mem\t# int" %}
5159 
5160   ins_encode %{
5161     __ movl($dst$$Register, $mem$$Address);
5162   %}
5163 
5164   ins_pipe(ialu_reg_mem);
5165 %}
5166 
5167 // Load Integer (32 bit signed) to Byte (8 bit signed)
5168 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5169   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5170 
5171   ins_cost(125);
5172   format %{ "movsbl  $dst, $mem\t# int -> byte" %}
5173   ins_encode %{
5174     __ movsbl($dst$$Register, $mem$$Address);
5175   %}
5176   ins_pipe(ialu_reg_mem);
5177 %}
5178 
5179 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5180 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5181   match(Set dst (AndI (LoadI mem) mask));
5182 
5183   ins_cost(125);
5184   format %{ "movzbl  $dst, $mem\t# int -> ubyte" %}
5185   ins_encode %{
5186     __ movzbl($dst$$Register, $mem$$Address);
5187   %}
5188   ins_pipe(ialu_reg_mem);
5189 %}
5190 
5191 // Load Integer (32 bit signed) to Short (16 bit signed)
5192 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5193   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5194 
5195   ins_cost(125);
5196   format %{ "movswl  $dst, $mem\t# int -> short" %}
5197   ins_encode %{
5198     __ movswl($dst$$Register, $mem$$Address);
5199   %}
5200   ins_pipe(ialu_reg_mem);
5201 %}
5202 
5203 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5204 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5205   match(Set dst (AndI (LoadI mem) mask));
5206 
5207   ins_cost(125);
5208   format %{ "movzwl  $dst, $mem\t# int -> ushort/char" %}
5209   ins_encode %{
5210     __ movzwl($dst$$Register, $mem$$Address);
5211   %}
5212   ins_pipe(ialu_reg_mem);
5213 %}
5214 
5215 // Load Integer into Long Register
5216 instruct loadI2L(rRegL dst, memory mem)
5217 %{
5218   match(Set dst (ConvI2L (LoadI mem)));
5219 
5220   ins_cost(125);
5221   format %{ "movslq  $dst, $mem\t# int -> long" %}
5222 
5223   ins_encode %{
5224     __ movslq($dst$$Register, $mem$$Address);
5225   %}
5226 
5227   ins_pipe(ialu_reg_mem);
5228 %}
5229 
5230 // Load Integer with mask 0xFF into Long Register
5231 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5232   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5233 
5234   format %{ "movzbq  $dst, $mem\t# int & 0xFF -> long" %}
5235   ins_encode %{
5236     __ movzbq($dst$$Register, $mem$$Address);
5237   %}
5238   ins_pipe(ialu_reg_mem);
5239 %}
5240 
5241 // Load Integer with mask 0xFFFF into Long Register
5242 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5243   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5244 
5245   format %{ "movzwq  $dst, $mem\t# int & 0xFFFF -> long" %}
5246   ins_encode %{
5247     __ movzwq($dst$$Register, $mem$$Address);
5248   %}
5249   ins_pipe(ialu_reg_mem);
5250 %}
5251 
5252 // Load Integer with a 31-bit mask into Long Register
5253 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5254   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5255   effect(KILL cr);
5256 
5257   format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
5258             "andl    $dst, $mask" %}
5259   ins_encode %{
5260     Register Rdst = $dst$$Register;
5261     __ movl(Rdst, $mem$$Address);
5262     __ andl(Rdst, $mask$$constant);
5263   %}
5264   ins_pipe(ialu_reg_mem);
5265 %}
5266 
5267 // Load Unsigned Integer into Long Register
5268 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5269 %{
5270   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5271 
5272   ins_cost(125);
5273   format %{ "movl    $dst, $mem\t# uint -> long" %}
5274 
5275   ins_encode %{
5276     __ movl($dst$$Register, $mem$$Address);
5277   %}
5278 
5279   ins_pipe(ialu_reg_mem);
5280 %}
5281 
5282 // Load Long
5283 instruct loadL(rRegL dst, memory mem)
5284 %{
5285   match(Set dst (LoadL mem));
5286 
5287   ins_cost(125);
5288   format %{ "movq    $dst, $mem\t# long" %}
5289 
5290   ins_encode %{
5291     __ movq($dst$$Register, $mem$$Address);
5292   %}
5293 
5294   ins_pipe(ialu_reg_mem); // XXX
5295 %}
5296 
5297 // Load Range
5298 instruct loadRange(rRegI dst, memory mem)
5299 %{
5300   match(Set dst (LoadRange mem));
5301 
5302   ins_cost(125); // XXX
5303   format %{ "movl    $dst, $mem\t# range" %}
5304   opcode(0x8B);
5305   ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5306   ins_pipe(ialu_reg_mem);
5307 %}
5308 
5309 // Load Pointer
5310 instruct loadP(rRegP dst, memory mem)
5311 %{
5312   match(Set dst (LoadP mem));
5313 
5314   ins_cost(125); // XXX
5315   format %{ "movq    $dst, $mem\t# ptr" %}
5316   opcode(0x8B);
5317   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5318   ins_pipe(ialu_reg_mem); // XXX
5319 %}
5320 
5321 // Load Compressed Pointer
5322 instruct loadN(rRegN dst, memory mem)
5323 %{
5324    match(Set dst (LoadN mem));
5325 
5326    ins_cost(125); // XXX
5327    format %{ "movl    $dst, $mem\t# compressed ptr" %}
5328    ins_encode %{
5329      __ movl($dst$$Register, $mem$$Address);
5330    %}
5331    ins_pipe(ialu_reg_mem); // XXX
5332 %}
5333 
5334 
5335 // Load Klass Pointer
5336 instruct loadKlass(rRegP dst, memory mem)
5337 %{
5338   match(Set dst (LoadKlass mem));
5339 
5340   ins_cost(125); // XXX
5341   format %{ "movq    $dst, $mem\t# class" %}
5342   opcode(0x8B);
5343   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5344   ins_pipe(ialu_reg_mem); // XXX
5345 %}
5346 
5347 // Load narrow Klass Pointer
5348 instruct loadNKlass(rRegN dst, memory mem)
5349 %{
5350   match(Set dst (LoadNKlass mem));
5351 
5352   ins_cost(125); // XXX
5353   format %{ "movl    $dst, $mem\t# compressed klass ptr" %}
5354   ins_encode %{
5355     __ movl($dst$$Register, $mem$$Address);
5356   %}
5357   ins_pipe(ialu_reg_mem); // XXX
5358 %}
5359 
5360 // Load Float
5361 instruct loadF(regF dst, memory mem)
5362 %{
5363   match(Set dst (LoadF mem));
5364 
5365   ins_cost(145); // XXX
5366   format %{ "movss   $dst, $mem\t# float" %}
5367   ins_encode %{
5368     __ movflt($dst$$XMMRegister, $mem$$Address);
5369   %}
5370   ins_pipe(pipe_slow); // XXX
5371 %}
5372 
5373 // Load Float
5374 instruct MoveF2VL(vlRegF dst, regF src) %{
5375   match(Set dst src);
5376   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5377   ins_encode %{
5378     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5379   %}
5380   ins_pipe( fpu_reg_reg );
5381 %}
5382 
5383 // Load Float
5384 instruct MoveVL2F(regF dst, vlRegF src) %{
5385   match(Set dst src);
5386   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
5387   ins_encode %{
5388     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
5389   %}
5390   ins_pipe( fpu_reg_reg );
5391 %}
5392 
5393 // Load Double
5394 instruct loadD_partial(regD dst, memory mem)
5395 %{
5396   predicate(!UseXmmLoadAndClearUpper);
5397   match(Set dst (LoadD mem));
5398 
5399   ins_cost(145); // XXX
5400   format %{ "movlpd  $dst, $mem\t# double" %}
5401   ins_encode %{
5402     __ movdbl($dst$$XMMRegister, $mem$$Address);
5403   %}
5404   ins_pipe(pipe_slow); // XXX
5405 %}
5406 
5407 instruct loadD(regD dst, memory mem)
5408 %{
5409   predicate(UseXmmLoadAndClearUpper);
5410   match(Set dst (LoadD mem));
5411 
5412   ins_cost(145); // XXX
5413   format %{ "movsd   $dst, $mem\t# double" %}
5414   ins_encode %{
5415     __ movdbl($dst$$XMMRegister, $mem$$Address);
5416   %}
5417   ins_pipe(pipe_slow); // XXX
5418 %}
5419 
5420 // Load Double
5421 instruct MoveD2VL(vlRegD dst, regD src) %{
5422   match(Set dst src);
5423   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5424   ins_encode %{
5425     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5426   %}
5427   ins_pipe( fpu_reg_reg );
5428 %}
5429 
5430 // Load Double
5431 instruct MoveVL2D(regD dst, vlRegD src) %{
5432   match(Set dst src);
5433   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
5434   ins_encode %{
5435     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
5436   %}
5437   ins_pipe( fpu_reg_reg );
5438 %}
5439 
5440 // Load Effective Address
5441 instruct leaP8(rRegP dst, indOffset8 mem)
5442 %{
5443   match(Set dst mem);
5444 
5445   ins_cost(110); // XXX
5446   format %{ "leaq    $dst, $mem\t# ptr 8" %}
5447   opcode(0x8D);
5448   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5449   ins_pipe(ialu_reg_reg_fat);
5450 %}
5451 
5452 instruct leaP32(rRegP dst, indOffset32 mem)
5453 %{
5454   match(Set dst mem);
5455 
5456   ins_cost(110);
5457   format %{ "leaq    $dst, $mem\t# ptr 32" %}
5458   opcode(0x8D);
5459   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5460   ins_pipe(ialu_reg_reg_fat);
5461 %}
5462 
5463 // instruct leaPIdx(rRegP dst, indIndex mem)
5464 // %{
5465 //   match(Set dst mem);
5466 
5467 //   ins_cost(110);
5468 //   format %{ "leaq    $dst, $mem\t# ptr idx" %}
5469 //   opcode(0x8D);
5470 //   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5471 //   ins_pipe(ialu_reg_reg_fat);
5472 // %}
5473 
5474 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5475 %{
5476   match(Set dst mem);
5477 
5478   ins_cost(110);
5479   format %{ "leaq    $dst, $mem\t# ptr idxoff" %}
5480   opcode(0x8D);
5481   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5482   ins_pipe(ialu_reg_reg_fat);
5483 %}
5484 
5485 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5486 %{
5487   match(Set dst mem);
5488 
5489   ins_cost(110);
5490   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
5491   opcode(0x8D);
5492   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5493   ins_pipe(ialu_reg_reg_fat);
5494 %}
5495 
5496 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5497 %{
5498   match(Set dst mem);
5499 
5500   ins_cost(110);
5501   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
5502   opcode(0x8D);
5503   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5504   ins_pipe(ialu_reg_reg_fat);
5505 %}
5506 
5507 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5508 %{
5509   match(Set dst mem);
5510 
5511   ins_cost(110);
5512   format %{ "leaq    $dst, $mem\t# ptr idxscaleoff" %}
5513   opcode(0x8D);
5514   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5515   ins_pipe(ialu_reg_reg_fat);
5516 %}
5517 
5518 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5519 %{
5520   match(Set dst mem);
5521 
5522   ins_cost(110);
5523   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
5524   opcode(0x8D);
5525   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5526   ins_pipe(ialu_reg_reg_fat);
5527 %}
5528 
5529 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5530 %{
5531   match(Set dst mem);
5532 
5533   ins_cost(110);
5534   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoff" %}
5535   opcode(0x8D);
5536   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5537   ins_pipe(ialu_reg_reg_fat);
5538 %}
5539 
5540 // Load Effective Address which uses Narrow (32-bits) oop
5541 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5542 %{
5543   predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5544   match(Set dst mem);
5545 
5546   ins_cost(110);
5547   format %{ "leaq    $dst, $mem\t# ptr compressedoopoff32" %}
5548   opcode(0x8D);
5549   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5550   ins_pipe(ialu_reg_reg_fat);
5551 %}
5552 
5553 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5554 %{
5555   predicate(Universe::narrow_oop_shift() == 0);
5556   match(Set dst mem);
5557 
5558   ins_cost(110); // XXX
5559   format %{ "leaq    $dst, $mem\t# ptr off8narrow" %}
5560   opcode(0x8D);
5561   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5562   ins_pipe(ialu_reg_reg_fat);
5563 %}
5564 
5565 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5566 %{
5567   predicate(Universe::narrow_oop_shift() == 0);
5568   match(Set dst mem);
5569 
5570   ins_cost(110);
5571   format %{ "leaq    $dst, $mem\t# ptr off32narrow" %}
5572   opcode(0x8D);
5573   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5574   ins_pipe(ialu_reg_reg_fat);
5575 %}
5576 
5577 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5578 %{
5579   predicate(Universe::narrow_oop_shift() == 0);
5580   match(Set dst mem);
5581 
5582   ins_cost(110);
5583   format %{ "leaq    $dst, $mem\t# ptr idxoffnarrow" %}
5584   opcode(0x8D);
5585   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5586   ins_pipe(ialu_reg_reg_fat);
5587 %}
5588 
5589 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5590 %{
5591   predicate(Universe::narrow_oop_shift() == 0);
5592   match(Set dst mem);
5593 
5594   ins_cost(110);
5595   format %{ "leaq    $dst, $mem\t# ptr idxscalenarrow" %}
5596   opcode(0x8D);
5597   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5598   ins_pipe(ialu_reg_reg_fat);
5599 %}
5600 
5601 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5602 %{
5603   predicate(Universe::narrow_oop_shift() == 0);
5604   match(Set dst mem);
5605 
5606   ins_cost(110);
5607   format %{ "leaq    $dst, $mem\t# ptr idxscaleoffnarrow" %}
5608   opcode(0x8D);
5609   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5610   ins_pipe(ialu_reg_reg_fat);
5611 %}
5612 
5613 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5614 %{
5615   predicate(Universe::narrow_oop_shift() == 0);
5616   match(Set dst mem);
5617 
5618   ins_cost(110);
5619   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
5620   opcode(0x8D);
5621   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5622   ins_pipe(ialu_reg_reg_fat);
5623 %}
5624 
5625 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5626 %{
5627   predicate(Universe::narrow_oop_shift() == 0);
5628   match(Set dst mem);
5629 
5630   ins_cost(110);
5631   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5632   opcode(0x8D);
5633   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5634   ins_pipe(ialu_reg_reg_fat);
5635 %}
5636 
5637 instruct loadConI(rRegI dst, immI src)
5638 %{
5639   match(Set dst src);
5640 
5641   format %{ "movl    $dst, $src\t# int" %}
5642   ins_encode(load_immI(dst, src));
5643   ins_pipe(ialu_reg_fat); // XXX
5644 %}
5645 
5646 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5647 %{
5648   match(Set dst src);
5649   effect(KILL cr);
5650 
5651   ins_cost(50);
5652   format %{ "xorl    $dst, $dst\t# int" %}
5653   opcode(0x33); /* + rd */
5654   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5655   ins_pipe(ialu_reg);
5656 %}
5657 
5658 instruct loadConL(rRegL dst, immL src)
5659 %{
5660   match(Set dst src);
5661 
5662   ins_cost(150);
5663   format %{ "movq    $dst, $src\t# long" %}
5664   ins_encode(load_immL(dst, src));
5665   ins_pipe(ialu_reg);
5666 %}
5667 
5668 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5669 %{
5670   match(Set dst src);
5671   effect(KILL cr);
5672 
5673   ins_cost(50);
5674   format %{ "xorl    $dst, $dst\t# long" %}
5675   opcode(0x33); /* + rd */
5676   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5677   ins_pipe(ialu_reg); // XXX
5678 %}
5679 
5680 instruct loadConUL32(rRegL dst, immUL32 src)
5681 %{
5682   match(Set dst src);
5683 
5684   ins_cost(60);
5685   format %{ "movl    $dst, $src\t# long (unsigned 32-bit)" %}
5686   ins_encode(load_immUL32(dst, src));
5687   ins_pipe(ialu_reg);
5688 %}
5689 
5690 instruct loadConL32(rRegL dst, immL32 src)
5691 %{
5692   match(Set dst src);
5693 
5694   ins_cost(70);
5695   format %{ "movq    $dst, $src\t# long (32-bit)" %}
5696   ins_encode(load_immL32(dst, src));
5697   ins_pipe(ialu_reg);
5698 %}
5699 
5700 instruct loadConP(rRegP dst, immP con) %{
5701   match(Set dst con);
5702 
5703   format %{ "movq    $dst, $con\t# ptr" %}
5704   ins_encode(load_immP(dst, con));
5705   ins_pipe(ialu_reg_fat); // XXX
5706 %}
5707 
5708 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5709 %{
5710   match(Set dst src);
5711   effect(KILL cr);
5712 
5713   ins_cost(50);
5714   format %{ "xorl    $dst, $dst\t# ptr" %}
5715   opcode(0x33); /* + rd */
5716   ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5717   ins_pipe(ialu_reg);
5718 %}
5719 
5720 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5721 %{
5722   match(Set dst src);
5723   effect(KILL cr);
5724 
5725   ins_cost(60);
5726   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
5727   ins_encode(load_immP31(dst, src));
5728   ins_pipe(ialu_reg);
5729 %}
5730 
5731 instruct loadConF(regF dst, immF con) %{
5732   match(Set dst con);
5733   ins_cost(125);
5734   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5735   ins_encode %{
5736     __ movflt($dst$$XMMRegister, $constantaddress($con));
5737   %}
5738   ins_pipe(pipe_slow);
5739 %}
5740 
5741 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5742   match(Set dst src);
5743   effect(KILL cr);
5744   format %{ "xorq    $dst, $src\t# compressed NULL ptr" %}
5745   ins_encode %{
5746     __ xorq($dst$$Register, $dst$$Register);
5747   %}
5748   ins_pipe(ialu_reg);
5749 %}
5750 
5751 instruct loadConN(rRegN dst, immN src) %{
5752   match(Set dst src);
5753 
5754   ins_cost(125);
5755   format %{ "movl    $dst, $src\t# compressed ptr" %}
5756   ins_encode %{
5757     address con = (address)$src$$constant;
5758     if (con == NULL) {
5759       ShouldNotReachHere();
5760     } else {
5761       __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5762     }
5763   %}
5764   ins_pipe(ialu_reg_fat); // XXX
5765 %}
5766 
5767 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5768   match(Set dst src);
5769 
5770   ins_cost(125);
5771   format %{ "movl    $dst, $src\t# compressed klass ptr" %}
5772   ins_encode %{
5773     address con = (address)$src$$constant;
5774     if (con == NULL) {
5775       ShouldNotReachHere();
5776     } else {
5777       __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5778     }
5779   %}
5780   ins_pipe(ialu_reg_fat); // XXX
5781 %}
5782 
5783 instruct loadConF0(regF dst, immF0 src)
5784 %{
5785   match(Set dst src);
5786   ins_cost(100);
5787 
5788   format %{ "xorps   $dst, $dst\t# float 0.0" %}
5789   ins_encode %{
5790     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5791   %}
5792   ins_pipe(pipe_slow);
5793 %}
5794 
5795 // Use the same format since predicate() can not be used here.
5796 instruct loadConD(regD dst, immD con) %{
5797   match(Set dst con);
5798   ins_cost(125);
5799   format %{ "movsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5800   ins_encode %{
5801     __ movdbl($dst$$XMMRegister, $constantaddress($con));
5802   %}
5803   ins_pipe(pipe_slow);
5804 %}
5805 
5806 instruct loadConD0(regD dst, immD0 src)
5807 %{
5808   match(Set dst src);
5809   ins_cost(100);
5810 
5811   format %{ "xorpd   $dst, $dst\t# double 0.0" %}
5812   ins_encode %{
5813     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5814   %}
5815   ins_pipe(pipe_slow);
5816 %}
5817 
5818 instruct loadSSI(rRegI dst, stackSlotI src)
5819 %{
5820   match(Set dst src);
5821 
5822   ins_cost(125);
5823   format %{ "movl    $dst, $src\t# int stk" %}
5824   opcode(0x8B);
5825   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5826   ins_pipe(ialu_reg_mem);
5827 %}
5828 
5829 instruct loadSSL(rRegL dst, stackSlotL src)
5830 %{
5831   match(Set dst src);
5832 
5833   ins_cost(125);
5834   format %{ "movq    $dst, $src\t# long stk" %}
5835   opcode(0x8B);
5836   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5837   ins_pipe(ialu_reg_mem);
5838 %}
5839 
5840 instruct loadSSP(rRegP dst, stackSlotP src)
5841 %{
5842   match(Set dst src);
5843 
5844   ins_cost(125);
5845   format %{ "movq    $dst, $src\t# ptr stk" %}
5846   opcode(0x8B);
5847   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5848   ins_pipe(ialu_reg_mem);
5849 %}
5850 
5851 instruct loadSSF(regF dst, stackSlotF src)
5852 %{
5853   match(Set dst src);
5854 
5855   ins_cost(125);
5856   format %{ "movss   $dst, $src\t# float stk" %}
5857   ins_encode %{
5858     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5859   %}
5860   ins_pipe(pipe_slow); // XXX
5861 %}
5862 
5863 // Use the same format since predicate() can not be used here.
5864 instruct loadSSD(regD dst, stackSlotD src)
5865 %{
5866   match(Set dst src);
5867 
5868   ins_cost(125);
5869   format %{ "movsd   $dst, $src\t# double stk" %}
5870   ins_encode  %{
5871     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5872   %}
5873   ins_pipe(pipe_slow); // XXX
5874 %}
5875 
5876 // Prefetch instructions for allocation.
5877 // Must be safe to execute with invalid address (cannot fault).
5878 
5879 instruct prefetchAlloc( memory mem ) %{
5880   predicate(AllocatePrefetchInstr==3);
5881   match(PrefetchAllocation mem);
5882   ins_cost(125);
5883 
5884   format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5885   ins_encode %{
5886     __ prefetchw($mem$$Address);
5887   %}
5888   ins_pipe(ialu_mem);
5889 %}
5890 
5891 instruct prefetchAllocNTA( memory mem ) %{
5892   predicate(AllocatePrefetchInstr==0);
5893   match(PrefetchAllocation mem);
5894   ins_cost(125);
5895 
5896   format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5897   ins_encode %{
5898     __ prefetchnta($mem$$Address);
5899   %}
5900   ins_pipe(ialu_mem);
5901 %}
5902 
5903 instruct prefetchAllocT0( memory mem ) %{
5904   predicate(AllocatePrefetchInstr==1);
5905   match(PrefetchAllocation mem);
5906   ins_cost(125);
5907 
5908   format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5909   ins_encode %{
5910     __ prefetcht0($mem$$Address);
5911   %}
5912   ins_pipe(ialu_mem);
5913 %}
5914 
5915 instruct prefetchAllocT2( memory mem ) %{
5916   predicate(AllocatePrefetchInstr==2);
5917   match(PrefetchAllocation mem);
5918   ins_cost(125);
5919 
5920   format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5921   ins_encode %{
5922     __ prefetcht2($mem$$Address);
5923   %}
5924   ins_pipe(ialu_mem);
5925 %}
5926 
5927 //----------Store Instructions-------------------------------------------------
5928 
5929 // Store Byte
5930 instruct storeB(memory mem, rRegI src)
5931 %{
5932   match(Set mem (StoreB mem src));
5933 
5934   ins_cost(125); // XXX
5935   format %{ "movb    $mem, $src\t# byte" %}
5936   opcode(0x88);
5937   ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5938   ins_pipe(ialu_mem_reg);
5939 %}
5940 
5941 // Store Char/Short
5942 instruct storeC(memory mem, rRegI src)
5943 %{
5944   match(Set mem (StoreC mem src));
5945 
5946   ins_cost(125); // XXX
5947   format %{ "movw    $mem, $src\t# char/short" %}
5948   opcode(0x89);
5949   ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5950   ins_pipe(ialu_mem_reg);
5951 %}
5952 
5953 // Store Integer
5954 instruct storeI(memory mem, rRegI src)
5955 %{
5956   match(Set mem (StoreI mem src));
5957 
5958   ins_cost(125); // XXX
5959   format %{ "movl    $mem, $src\t# int" %}
5960   opcode(0x89);
5961   ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5962   ins_pipe(ialu_mem_reg);
5963 %}
5964 
5965 // Store Long
5966 instruct storeL(memory mem, rRegL src)
5967 %{
5968   match(Set mem (StoreL mem src));
5969 
5970   ins_cost(125); // XXX
5971   format %{ "movq    $mem, $src\t# long" %}
5972   opcode(0x89);
5973   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5974   ins_pipe(ialu_mem_reg); // XXX
5975 %}
5976 
5977 // Store Pointer
5978 instruct storeP(memory mem, any_RegP src)
5979 %{
5980   match(Set mem (StoreP mem src));
5981 
5982   ins_cost(125); // XXX
5983   format %{ "movq    $mem, $src\t# ptr" %}
5984   opcode(0x89);
5985   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5986   ins_pipe(ialu_mem_reg);
5987 %}
5988 
5989 instruct storeImmP0(memory mem, immP0 zero)
5990 %{
5991   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5992   match(Set mem (StoreP mem zero));
5993 
5994   ins_cost(125); // XXX
5995   format %{ "movq    $mem, R12\t# ptr (R12_heapbase==0)" %}
5996   ins_encode %{
5997     __ movq($mem$$Address, r12);
5998   %}
5999   ins_pipe(ialu_mem_reg);
6000 %}
6001 
6002 // Store NULL Pointer, mark word, or other simple pointer constant.
6003 instruct storeImmP(memory mem, immP31 src)
6004 %{
6005   match(Set mem (StoreP mem src));
6006 
6007   ins_cost(150); // XXX
6008   format %{ "movq    $mem, $src\t# ptr" %}
6009   opcode(0xC7); /* C7 /0 */
6010   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6011   ins_pipe(ialu_mem_imm);
6012 %}
6013 
6014 // Store Compressed Pointer
6015 instruct storeN(memory mem, rRegN src)
6016 %{
6017   match(Set mem (StoreN mem src));
6018 
6019   ins_cost(125); // XXX
6020   format %{ "movl    $mem, $src\t# compressed ptr" %}
6021   ins_encode %{
6022     __ movl($mem$$Address, $src$$Register);
6023   %}
6024   ins_pipe(ialu_mem_reg);
6025 %}
6026 
6027 instruct storeNKlass(memory mem, rRegN src)
6028 %{
6029   match(Set mem (StoreNKlass mem src));
6030 
6031   ins_cost(125); // XXX
6032   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
6033   ins_encode %{
6034     __ movl($mem$$Address, $src$$Register);
6035   %}
6036   ins_pipe(ialu_mem_reg);
6037 %}
6038 
6039 instruct storeImmN0(memory mem, immN0 zero)
6040 %{
6041   predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
6042   match(Set mem (StoreN mem zero));
6043 
6044   ins_cost(125); // XXX
6045   format %{ "movl    $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6046   ins_encode %{
6047     __ movl($mem$$Address, r12);
6048   %}
6049   ins_pipe(ialu_mem_reg);
6050 %}
6051 
6052 instruct storeImmN(memory mem, immN src)
6053 %{
6054   match(Set mem (StoreN mem src));
6055 
6056   ins_cost(150); // XXX
6057   format %{ "movl    $mem, $src\t# compressed ptr" %}
6058   ins_encode %{
6059     address con = (address)$src$$constant;
6060     if (con == NULL) {
6061       __ movl($mem$$Address, (int32_t)0);
6062     } else {
6063       __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6064     }
6065   %}
6066   ins_pipe(ialu_mem_imm);
6067 %}
6068 
6069 instruct storeImmNKlass(memory mem, immNKlass src)
6070 %{
6071   match(Set mem (StoreNKlass mem src));
6072 
6073   ins_cost(150); // XXX
6074   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
6075   ins_encode %{
6076     __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6077   %}
6078   ins_pipe(ialu_mem_imm);
6079 %}
6080 
6081 // Store Integer Immediate
6082 instruct storeImmI0(memory mem, immI0 zero)
6083 %{
6084   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6085   match(Set mem (StoreI mem zero));
6086 
6087   ins_cost(125); // XXX
6088   format %{ "movl    $mem, R12\t# int (R12_heapbase==0)" %}
6089   ins_encode %{
6090     __ movl($mem$$Address, r12);
6091   %}
6092   ins_pipe(ialu_mem_reg);
6093 %}
6094 
6095 instruct storeImmI(memory mem, immI src)
6096 %{
6097   match(Set mem (StoreI mem src));
6098 
6099   ins_cost(150);
6100   format %{ "movl    $mem, $src\t# int" %}
6101   opcode(0xC7); /* C7 /0 */
6102   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6103   ins_pipe(ialu_mem_imm);
6104 %}
6105 
6106 // Store Long Immediate
6107 instruct storeImmL0(memory mem, immL0 zero)
6108 %{
6109   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6110   match(Set mem (StoreL mem zero));
6111 
6112   ins_cost(125); // XXX
6113   format %{ "movq    $mem, R12\t# long (R12_heapbase==0)" %}
6114   ins_encode %{
6115     __ movq($mem$$Address, r12);
6116   %}
6117   ins_pipe(ialu_mem_reg);
6118 %}
6119 
6120 instruct storeImmL(memory mem, immL32 src)
6121 %{
6122   match(Set mem (StoreL mem src));
6123 
6124   ins_cost(150);
6125   format %{ "movq    $mem, $src\t# long" %}
6126   opcode(0xC7); /* C7 /0 */
6127   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6128   ins_pipe(ialu_mem_imm);
6129 %}
6130 
6131 // Store Short/Char Immediate
6132 instruct storeImmC0(memory mem, immI0 zero)
6133 %{
6134   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6135   match(Set mem (StoreC mem zero));
6136 
6137   ins_cost(125); // XXX
6138   format %{ "movw    $mem, R12\t# short/char (R12_heapbase==0)" %}
6139   ins_encode %{
6140     __ movw($mem$$Address, r12);
6141   %}
6142   ins_pipe(ialu_mem_reg);
6143 %}
6144 
6145 instruct storeImmI16(memory mem, immI16 src)
6146 %{
6147   predicate(UseStoreImmI16);
6148   match(Set mem (StoreC mem src));
6149 
6150   ins_cost(150);
6151   format %{ "movw    $mem, $src\t# short/char" %}
6152   opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6153   ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6154   ins_pipe(ialu_mem_imm);
6155 %}
6156 
6157 // Store Byte Immediate
6158 instruct storeImmB0(memory mem, immI0 zero)
6159 %{
6160   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6161   match(Set mem (StoreB mem zero));
6162 
6163   ins_cost(125); // XXX
6164   format %{ "movb    $mem, R12\t# short/char (R12_heapbase==0)" %}
6165   ins_encode %{
6166     __ movb($mem$$Address, r12);
6167   %}
6168   ins_pipe(ialu_mem_reg);
6169 %}
6170 
6171 instruct storeImmB(memory mem, immI8 src)
6172 %{
6173   match(Set mem (StoreB mem src));
6174 
6175   ins_cost(150); // XXX
6176   format %{ "movb    $mem, $src\t# byte" %}
6177   opcode(0xC6); /* C6 /0 */
6178   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6179   ins_pipe(ialu_mem_imm);
6180 %}
6181 
6182 // Store CMS card-mark Immediate
6183 instruct storeImmCM0_reg(memory mem, immI0 zero)
6184 %{
6185   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6186   match(Set mem (StoreCM mem zero));
6187 
6188   ins_cost(125); // XXX
6189   format %{ "movb    $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6190   ins_encode %{
6191     __ movb($mem$$Address, r12);
6192   %}
6193   ins_pipe(ialu_mem_reg);
6194 %}
6195 
6196 instruct storeImmCM0(memory mem, immI0 src)
6197 %{
6198   match(Set mem (StoreCM mem src));
6199 
6200   ins_cost(150); // XXX
6201   format %{ "movb    $mem, $src\t# CMS card-mark byte 0" %}
6202   opcode(0xC6); /* C6 /0 */
6203   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6204   ins_pipe(ialu_mem_imm);
6205 %}
6206 
6207 // Store Float
6208 instruct storeF(memory mem, regF src)
6209 %{
6210   match(Set mem (StoreF mem src));
6211 
6212   ins_cost(95); // XXX
6213   format %{ "movss   $mem, $src\t# float" %}
6214   ins_encode %{
6215     __ movflt($mem$$Address, $src$$XMMRegister);
6216   %}
6217   ins_pipe(pipe_slow); // XXX
6218 %}
6219 
6220 // Store immediate Float value (it is faster than store from XMM register)
6221 instruct storeF0(memory mem, immF0 zero)
6222 %{
6223   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6224   match(Set mem (StoreF mem zero));
6225 
6226   ins_cost(25); // XXX
6227   format %{ "movl    $mem, R12\t# float 0. (R12_heapbase==0)" %}
6228   ins_encode %{
6229     __ movl($mem$$Address, r12);
6230   %}
6231   ins_pipe(ialu_mem_reg);
6232 %}
6233 
6234 instruct storeF_imm(memory mem, immF src)
6235 %{
6236   match(Set mem (StoreF mem src));
6237 
6238   ins_cost(50);
6239   format %{ "movl    $mem, $src\t# float" %}
6240   opcode(0xC7); /* C7 /0 */
6241   ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6242   ins_pipe(ialu_mem_imm);
6243 %}
6244 
6245 // Store Double
6246 instruct storeD(memory mem, regD src)
6247 %{
6248   match(Set mem (StoreD mem src));
6249 
6250   ins_cost(95); // XXX
6251   format %{ "movsd   $mem, $src\t# double" %}
6252   ins_encode %{
6253     __ movdbl($mem$$Address, $src$$XMMRegister);
6254   %}
6255   ins_pipe(pipe_slow); // XXX
6256 %}
6257 
6258 // Store immediate double 0.0 (it is faster than store from XMM register)
6259 instruct storeD0_imm(memory mem, immD0 src)
6260 %{
6261   predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
6262   match(Set mem (StoreD mem src));
6263 
6264   ins_cost(50);
6265   format %{ "movq    $mem, $src\t# double 0." %}
6266   opcode(0xC7); /* C7 /0 */
6267   ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6268   ins_pipe(ialu_mem_imm);
6269 %}
6270 
6271 instruct storeD0(memory mem, immD0 zero)
6272 %{
6273   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
6274   match(Set mem (StoreD mem zero));
6275 
6276   ins_cost(25); // XXX
6277   format %{ "movq    $mem, R12\t# double 0. (R12_heapbase==0)" %}
6278   ins_encode %{
6279     __ movq($mem$$Address, r12);
6280   %}
6281   ins_pipe(ialu_mem_reg);
6282 %}
6283 
6284 instruct storeSSI(stackSlotI dst, rRegI src)
6285 %{
6286   match(Set dst src);
6287 
6288   ins_cost(100);
6289   format %{ "movl    $dst, $src\t# int stk" %}
6290   opcode(0x89);
6291   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6292   ins_pipe( ialu_mem_reg );
6293 %}
6294 
6295 instruct storeSSL(stackSlotL dst, rRegL src)
6296 %{
6297   match(Set dst src);
6298 
6299   ins_cost(100);
6300   format %{ "movq    $dst, $src\t# long stk" %}
6301   opcode(0x89);
6302   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6303   ins_pipe(ialu_mem_reg);
6304 %}
6305 
6306 instruct storeSSP(stackSlotP dst, rRegP src)
6307 %{
6308   match(Set dst src);
6309 
6310   ins_cost(100);
6311   format %{ "movq    $dst, $src\t# ptr stk" %}
6312   opcode(0x89);
6313   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6314   ins_pipe(ialu_mem_reg);
6315 %}
6316 
6317 instruct storeSSF(stackSlotF dst, regF src)
6318 %{
6319   match(Set dst src);
6320 
6321   ins_cost(95); // XXX
6322   format %{ "movss   $dst, $src\t# float stk" %}
6323   ins_encode %{
6324     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6325   %}
6326   ins_pipe(pipe_slow); // XXX
6327 %}
6328 
6329 instruct storeSSD(stackSlotD dst, regD src)
6330 %{
6331   match(Set dst src);
6332 
6333   ins_cost(95); // XXX
6334   format %{ "movsd   $dst, $src\t# double stk" %}
6335   ins_encode %{
6336     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6337   %}
6338   ins_pipe(pipe_slow); // XXX
6339 %}
6340 
6341 //----------BSWAP Instructions-------------------------------------------------
6342 instruct bytes_reverse_int(rRegI dst) %{
6343   match(Set dst (ReverseBytesI dst));
6344 
6345   format %{ "bswapl  $dst" %}
6346   opcode(0x0F, 0xC8);  /*Opcode 0F /C8 */
6347   ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6348   ins_pipe( ialu_reg );
6349 %}
6350 
6351 instruct bytes_reverse_long(rRegL dst) %{
6352   match(Set dst (ReverseBytesL dst));
6353 
6354   format %{ "bswapq  $dst" %}
6355   opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6356   ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6357   ins_pipe( ialu_reg);
6358 %}
6359 
6360 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6361   match(Set dst (ReverseBytesUS dst));
6362   effect(KILL cr);
6363 
6364   format %{ "bswapl  $dst\n\t"
6365             "shrl    $dst,16\n\t" %}
6366   ins_encode %{
6367     __ bswapl($dst$$Register);
6368     __ shrl($dst$$Register, 16);
6369   %}
6370   ins_pipe( ialu_reg );
6371 %}
6372 
6373 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6374   match(Set dst (ReverseBytesS dst));
6375   effect(KILL cr);
6376 
6377   format %{ "bswapl  $dst\n\t"
6378             "sar     $dst,16\n\t" %}
6379   ins_encode %{
6380     __ bswapl($dst$$Register);
6381     __ sarl($dst$$Register, 16);
6382   %}
6383   ins_pipe( ialu_reg );
6384 %}
6385 
6386 //---------- Zeros Count Instructions ------------------------------------------
6387 
6388 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6389   predicate(UseCountLeadingZerosInstruction);
6390   match(Set dst (CountLeadingZerosI src));
6391   effect(KILL cr);
6392 
6393   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
6394   ins_encode %{
6395     __ lzcntl($dst$$Register, $src$$Register);
6396   %}
6397   ins_pipe(ialu_reg);
6398 %}
6399 
6400 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6401   predicate(!UseCountLeadingZerosInstruction);
6402   match(Set dst (CountLeadingZerosI src));
6403   effect(KILL cr);
6404 
6405   format %{ "bsrl    $dst, $src\t# count leading zeros (int)\n\t"
6406             "jnz     skip\n\t"
6407             "movl    $dst, -1\n"
6408       "skip:\n\t"
6409             "negl    $dst\n\t"
6410             "addl    $dst, 31" %}
6411   ins_encode %{
6412     Register Rdst = $dst$$Register;
6413     Register Rsrc = $src$$Register;
6414     Label skip;
6415     __ bsrl(Rdst, Rsrc);
6416     __ jccb(Assembler::notZero, skip);
6417     __ movl(Rdst, -1);
6418     __ bind(skip);
6419     __ negl(Rdst);
6420     __ addl(Rdst, BitsPerInt - 1);
6421   %}
6422   ins_pipe(ialu_reg);
6423 %}
6424 
6425 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6426   predicate(UseCountLeadingZerosInstruction);
6427   match(Set dst (CountLeadingZerosL src));
6428   effect(KILL cr);
6429 
6430   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
6431   ins_encode %{
6432     __ lzcntq($dst$$Register, $src$$Register);
6433   %}
6434   ins_pipe(ialu_reg);
6435 %}
6436 
6437 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6438   predicate(!UseCountLeadingZerosInstruction);
6439   match(Set dst (CountLeadingZerosL src));
6440   effect(KILL cr);
6441 
6442   format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
6443             "jnz     skip\n\t"
6444             "movl    $dst, -1\n"
6445       "skip:\n\t"
6446             "negl    $dst\n\t"
6447             "addl    $dst, 63" %}
6448   ins_encode %{
6449     Register Rdst = $dst$$Register;
6450     Register Rsrc = $src$$Register;
6451     Label skip;
6452     __ bsrq(Rdst, Rsrc);
6453     __ jccb(Assembler::notZero, skip);
6454     __ movl(Rdst, -1);
6455     __ bind(skip);
6456     __ negl(Rdst);
6457     __ addl(Rdst, BitsPerLong - 1);
6458   %}
6459   ins_pipe(ialu_reg);
6460 %}
6461 
6462 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6463   predicate(UseCountTrailingZerosInstruction);
6464   match(Set dst (CountTrailingZerosI src));
6465   effect(KILL cr);
6466 
6467   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
6468   ins_encode %{
6469     __ tzcntl($dst$$Register, $src$$Register);
6470   %}
6471   ins_pipe(ialu_reg);
6472 %}
6473 
6474 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6475   predicate(!UseCountTrailingZerosInstruction);
6476   match(Set dst (CountTrailingZerosI src));
6477   effect(KILL cr);
6478 
6479   format %{ "bsfl    $dst, $src\t# count trailing zeros (int)\n\t"
6480             "jnz     done\n\t"
6481             "movl    $dst, 32\n"
6482       "done:" %}
6483   ins_encode %{
6484     Register Rdst = $dst$$Register;
6485     Label done;
6486     __ bsfl(Rdst, $src$$Register);
6487     __ jccb(Assembler::notZero, done);
6488     __ movl(Rdst, BitsPerInt);
6489     __ bind(done);
6490   %}
6491   ins_pipe(ialu_reg);
6492 %}
6493 
6494 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6495   predicate(UseCountTrailingZerosInstruction);
6496   match(Set dst (CountTrailingZerosL src));
6497   effect(KILL cr);
6498 
6499   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
6500   ins_encode %{
6501     __ tzcntq($dst$$Register, $src$$Register);
6502   %}
6503   ins_pipe(ialu_reg);
6504 %}
6505 
6506 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6507   predicate(!UseCountTrailingZerosInstruction);
6508   match(Set dst (CountTrailingZerosL src));
6509   effect(KILL cr);
6510 
6511   format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
6512             "jnz     done\n\t"
6513             "movl    $dst, 64\n"
6514       "done:" %}
6515   ins_encode %{
6516     Register Rdst = $dst$$Register;
6517     Label done;
6518     __ bsfq(Rdst, $src$$Register);
6519     __ jccb(Assembler::notZero, done);
6520     __ movl(Rdst, BitsPerLong);
6521     __ bind(done);
6522   %}
6523   ins_pipe(ialu_reg);
6524 %}
6525 
6526 
6527 //---------- Population Count Instructions -------------------------------------
6528 
6529 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6530   predicate(UsePopCountInstruction);
6531   match(Set dst (PopCountI src));
6532   effect(KILL cr);
6533 
6534   format %{ "popcnt  $dst, $src" %}
6535   ins_encode %{
6536     __ popcntl($dst$$Register, $src$$Register);
6537   %}
6538   ins_pipe(ialu_reg);
6539 %}
6540 
6541 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6542   predicate(UsePopCountInstruction);
6543   match(Set dst (PopCountI (LoadI mem)));
6544   effect(KILL cr);
6545 
6546   format %{ "popcnt  $dst, $mem" %}
6547   ins_encode %{
6548     __ popcntl($dst$$Register, $mem$$Address);
6549   %}
6550   ins_pipe(ialu_reg);
6551 %}
6552 
6553 // Note: Long.bitCount(long) returns an int.
6554 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6555   predicate(UsePopCountInstruction);
6556   match(Set dst (PopCountL src));
6557   effect(KILL cr);
6558 
6559   format %{ "popcnt  $dst, $src" %}
6560   ins_encode %{
6561     __ popcntq($dst$$Register, $src$$Register);
6562   %}
6563   ins_pipe(ialu_reg);
6564 %}
6565 
6566 // Note: Long.bitCount(long) returns an int.
6567 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6568   predicate(UsePopCountInstruction);
6569   match(Set dst (PopCountL (LoadL mem)));
6570   effect(KILL cr);
6571 
6572   format %{ "popcnt  $dst, $mem" %}
6573   ins_encode %{
6574     __ popcntq($dst$$Register, $mem$$Address);
6575   %}
6576   ins_pipe(ialu_reg);
6577 %}
6578 
6579 
6580 //----------MemBar Instructions-----------------------------------------------
6581 // Memory barrier flavors
6582 
6583 instruct membar_acquire()
6584 %{
6585   match(MemBarAcquire);
6586   match(LoadFence);
6587   ins_cost(0);
6588 
6589   size(0);
6590   format %{ "MEMBAR-acquire ! (empty encoding)" %}
6591   ins_encode();
6592   ins_pipe(empty);
6593 %}
6594 
6595 instruct membar_acquire_lock()
6596 %{
6597   match(MemBarAcquireLock);
6598   ins_cost(0);
6599 
6600   size(0);
6601   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6602   ins_encode();
6603   ins_pipe(empty);
6604 %}
6605 
6606 instruct membar_release()
6607 %{
6608   match(MemBarRelease);
6609   match(StoreFence);
6610   ins_cost(0);
6611 
6612   size(0);
6613   format %{ "MEMBAR-release ! (empty encoding)" %}
6614   ins_encode();
6615   ins_pipe(empty);
6616 %}
6617 
6618 instruct membar_release_lock()
6619 %{
6620   match(MemBarReleaseLock);
6621   ins_cost(0);
6622 
6623   size(0);
6624   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6625   ins_encode();
6626   ins_pipe(empty);
6627 %}
6628 
6629 instruct membar_volatile(rFlagsReg cr) %{
6630   match(MemBarVolatile);
6631   effect(KILL cr);
6632   ins_cost(400);
6633 
6634   format %{
6635     $$template
6636     if (os::is_MP()) {
6637       $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6638     } else {
6639       $$emit$$"MEMBAR-volatile ! (empty encoding)"
6640     }
6641   %}
6642   ins_encode %{
6643     __ membar(Assembler::StoreLoad);
6644   %}
6645   ins_pipe(pipe_slow);
6646 %}
6647 
6648 instruct unnecessary_membar_volatile()
6649 %{
6650   match(MemBarVolatile);
6651   predicate(Matcher::post_store_load_barrier(n));
6652   ins_cost(0);
6653 
6654   size(0);
6655   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6656   ins_encode();
6657   ins_pipe(empty);
6658 %}
6659 
6660 instruct membar_storestore() %{
6661   match(MemBarStoreStore);
6662   ins_cost(0);
6663 
6664   size(0);
6665   format %{ "MEMBAR-storestore (empty encoding)" %}
6666   ins_encode( );
6667   ins_pipe(empty);
6668 %}
6669 
6670 //----------Move Instructions--------------------------------------------------
6671 
6672 instruct castX2P(rRegP dst, rRegL src)
6673 %{
6674   match(Set dst (CastX2P src));
6675 
6676   format %{ "movq    $dst, $src\t# long->ptr" %}
6677   ins_encode %{
6678     if ($dst$$reg != $src$$reg) {
6679       __ movptr($dst$$Register, $src$$Register);
6680     }
6681   %}
6682   ins_pipe(ialu_reg_reg); // XXX
6683 %}
6684 
6685 instruct castP2X(rRegL dst, rRegP src)
6686 %{
6687   match(Set dst (CastP2X src));
6688 
6689   format %{ "movq    $dst, $src\t# ptr -> long" %}
6690   ins_encode %{
6691     if ($dst$$reg != $src$$reg) {
6692       __ movptr($dst$$Register, $src$$Register);
6693     }
6694   %}
6695   ins_pipe(ialu_reg_reg); // XXX
6696 %}
6697 
6698 // Convert oop into int for vectors alignment masking
6699 instruct convP2I(rRegI dst, rRegP src)
6700 %{
6701   match(Set dst (ConvL2I (CastP2X src)));
6702 
6703   format %{ "movl    $dst, $src\t# ptr -> int" %}
6704   ins_encode %{
6705     __ movl($dst$$Register, $src$$Register);
6706   %}
6707   ins_pipe(ialu_reg_reg); // XXX
6708 %}
6709 
6710 // Convert compressed oop into int for vectors alignment masking
6711 // in case of 32bit oops (heap < 4Gb).
6712 instruct convN2I(rRegI dst, rRegN src)
6713 %{
6714   predicate(Universe::narrow_oop_shift() == 0);
6715   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6716 
6717   format %{ "movl    $dst, $src\t# compressed ptr -> int" %}
6718   ins_encode %{
6719     __ movl($dst$$Register, $src$$Register);
6720   %}
6721   ins_pipe(ialu_reg_reg); // XXX
6722 %}
6723 
6724 instruct shenandoahRB(rRegP dst, rRegP src, rFlagsReg cr) %{
6725   match(Set dst (ShenandoahReadBarrier src));
6726   effect(DEF dst, USE src);
6727   ins_cost(125); // XXX
6728   format %{ "shenandoah_rb $dst, $src" %}
6729   ins_encode %{
6730 #if INCLUDE_SHENANDOAHGC
6731     Register d = $dst$$Register;
6732     Register s = $src$$Register;
6733     __ movptr(d, Address(s, ShenandoahBrooksPointer::byte_offset()));
6734 #else
6735     ShouldNotReachHere();
6736 #endif
6737   %}
6738   ins_pipe(ialu_reg_mem);
6739 %}
6740 
6741 instruct shenandoahRBNarrow(rRegP dst, rRegN src) %{
6742   predicate(UseCompressedOops && (Universe::narrow_oop_shift() == 0));
6743   match(Set dst (ShenandoahReadBarrier (DecodeN src)));
6744   effect(DEF dst, USE src);
6745   ins_cost(125); // XXX
6746   format %{ "shenandoah_rb $dst, $src" %}
6747   ins_encode %{
6748 #if INCLUDE_SHENANDOAHGC
6749     Register d = $dst$$Register;
6750     Register s = $src$$Register;
6751     __ movptr(d, Address(r12, s, Address::times_1, ShenandoahBrooksPointer::byte_offset()));
6752 #else
6753     ShouldNotReachHere();
6754 #endif
6755   %}
6756   ins_pipe(ialu_reg_mem);
6757 %}
6758 
6759 instruct shenandoahRBNarrowShift(rRegP dst, rRegN src) %{
6760   predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
6761   match(Set dst (ShenandoahReadBarrier (DecodeN src)));
6762   effect(DEF dst, USE src);
6763   ins_cost(125); // XXX
6764   format %{ "shenandoah_rb $dst, $src" %}
6765   ins_encode %{
6766 #if INCLUDE_SHENANDOAHGC
6767     Register d = $dst$$Register;
6768     Register s = $src$$Register;
6769     __ movptr(d, Address(r12, s, Address::times_8, ShenandoahBrooksPointer::byte_offset()));
6770 #else
6771     ShouldNotReachHere();
6772 #endif
6773   %}
6774   ins_pipe(ialu_reg_mem);
6775 %}
6776 
6777 // Convert oop pointer into compressed form
6778 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6779   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6780   match(Set dst (EncodeP src));
6781   effect(KILL cr);
6782   format %{ "encode_heap_oop $dst,$src" %}
6783   ins_encode %{
6784     Register s = $src$$Register;
6785     Register d = $dst$$Register;
6786     if (s != d) {
6787       __ movq(d, s);
6788     }
6789     __ encode_heap_oop(d);
6790   %}
6791   ins_pipe(ialu_reg_long);
6792 %}
6793 
6794 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6795   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6796   match(Set dst (EncodeP src));
6797   effect(KILL cr);
6798   format %{ "encode_heap_oop_not_null $dst,$src" %}
6799   ins_encode %{
6800     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6801   %}
6802   ins_pipe(ialu_reg_long);
6803 %}
6804 
6805 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6806   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6807             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6808   match(Set dst (DecodeN src));
6809   effect(KILL cr);
6810   format %{ "decode_heap_oop $dst,$src" %}
6811   ins_encode %{
6812     Register s = $src$$Register;
6813     Register d = $dst$$Register;
6814     if (s != d) {
6815       __ movq(d, s);
6816     }
6817     __ decode_heap_oop(d);
6818   %}
6819   ins_pipe(ialu_reg_long);
6820 %}
6821 
6822 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6823   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6824             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6825   match(Set dst (DecodeN src));
6826   effect(KILL cr);
6827   format %{ "decode_heap_oop_not_null $dst,$src" %}
6828   ins_encode %{
6829     Register s = $src$$Register;
6830     Register d = $dst$$Register;
6831     if (s != d) {
6832       __ decode_heap_oop_not_null(d, s);
6833     } else {
6834       __ decode_heap_oop_not_null(d);
6835     }
6836   %}
6837   ins_pipe(ialu_reg_long);
6838 %}
6839 
6840 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6841   match(Set dst (EncodePKlass src));
6842   effect(KILL cr);
6843   format %{ "encode_klass_not_null $dst,$src" %}
6844   ins_encode %{
6845     __ encode_klass_not_null($dst$$Register, $src$$Register);
6846   %}
6847   ins_pipe(ialu_reg_long);
6848 %}
6849 
6850 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6851   match(Set dst (DecodeNKlass src));
6852   effect(KILL cr);
6853   format %{ "decode_klass_not_null $dst,$src" %}
6854   ins_encode %{
6855     Register s = $src$$Register;
6856     Register d = $dst$$Register;
6857     if (s != d) {
6858       __ decode_klass_not_null(d, s);
6859     } else {
6860       __ decode_klass_not_null(d);
6861     }
6862   %}
6863   ins_pipe(ialu_reg_long);
6864 %}
6865 
6866 
6867 //----------Conditional Move---------------------------------------------------
6868 // Jump
6869 // dummy instruction for generating temp registers
6870 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6871   match(Jump (LShiftL switch_val shift));
6872   ins_cost(350);
6873   predicate(false);
6874   effect(TEMP dest);
6875 
6876   format %{ "leaq    $dest, [$constantaddress]\n\t"
6877             "jmp     [$dest + $switch_val << $shift]\n\t" %}
6878   ins_encode %{
6879     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6880     // to do that and the compiler is using that register as one it can allocate.
6881     // So we build it all by hand.
6882     // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6883     // ArrayAddress dispatch(table, index);
6884     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6885     __ lea($dest$$Register, $constantaddress);
6886     __ jmp(dispatch);
6887   %}
6888   ins_pipe(pipe_jmp);
6889 %}
6890 
6891 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6892   match(Jump (AddL (LShiftL switch_val shift) offset));
6893   ins_cost(350);
6894   effect(TEMP dest);
6895 
6896   format %{ "leaq    $dest, [$constantaddress]\n\t"
6897             "jmp     [$dest + $switch_val << $shift + $offset]\n\t" %}
6898   ins_encode %{
6899     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6900     // to do that and the compiler is using that register as one it can allocate.
6901     // So we build it all by hand.
6902     // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6903     // ArrayAddress dispatch(table, index);
6904     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6905     __ lea($dest$$Register, $constantaddress);
6906     __ jmp(dispatch);
6907   %}
6908   ins_pipe(pipe_jmp);
6909 %}
6910 
6911 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6912   match(Jump switch_val);
6913   ins_cost(350);
6914   effect(TEMP dest);
6915 
6916   format %{ "leaq    $dest, [$constantaddress]\n\t"
6917             "jmp     [$dest + $switch_val]\n\t" %}
6918   ins_encode %{
6919     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6920     // to do that and the compiler is using that register as one it can allocate.
6921     // So we build it all by hand.
6922     // Address index(noreg, switch_reg, Address::times_1);
6923     // ArrayAddress dispatch(table, index);
6924     Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6925     __ lea($dest$$Register, $constantaddress);
6926     __ jmp(dispatch);
6927   %}
6928   ins_pipe(pipe_jmp);
6929 %}
6930 
6931 // Conditional move
6932 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6933 %{
6934   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6935 
6936   ins_cost(200); // XXX
6937   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6938   opcode(0x0F, 0x40);
6939   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6940   ins_pipe(pipe_cmov_reg);
6941 %}
6942 
6943 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6944   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6945 
6946   ins_cost(200); // XXX
6947   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6948   opcode(0x0F, 0x40);
6949   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6950   ins_pipe(pipe_cmov_reg);
6951 %}
6952 
6953 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6954   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6955   ins_cost(200);
6956   expand %{
6957     cmovI_regU(cop, cr, dst, src);
6958   %}
6959 %}
6960 
6961 // Conditional move
6962 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6963   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6964 
6965   ins_cost(250); // XXX
6966   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6967   opcode(0x0F, 0x40);
6968   ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6969   ins_pipe(pipe_cmov_mem);
6970 %}
6971 
6972 // Conditional move
6973 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6974 %{
6975   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6976 
6977   ins_cost(250); // XXX
6978   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6979   opcode(0x0F, 0x40);
6980   ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6981   ins_pipe(pipe_cmov_mem);
6982 %}
6983 
6984 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6985   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6986   ins_cost(250);
6987   expand %{
6988     cmovI_memU(cop, cr, dst, src);
6989   %}
6990 %}
6991 
6992 // Conditional move
6993 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6994 %{
6995   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6996 
6997   ins_cost(200); // XXX
6998   format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6999   opcode(0x0F, 0x40);
7000   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7001   ins_pipe(pipe_cmov_reg);
7002 %}
7003 
7004 // Conditional move
7005 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7006 %{
7007   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7008 
7009   ins_cost(200); // XXX
7010   format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7011   opcode(0x0F, 0x40);
7012   ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7013   ins_pipe(pipe_cmov_reg);
7014 %}
7015 
7016 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7017   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7018   ins_cost(200);
7019   expand %{
7020     cmovN_regU(cop, cr, dst, src);
7021   %}
7022 %}
7023 
7024 // Conditional move
7025 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7026 %{
7027   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7028 
7029   ins_cost(200); // XXX
7030   format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7031   opcode(0x0F, 0x40);
7032   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7033   ins_pipe(pipe_cmov_reg);  // XXX
7034 %}
7035 
7036 // Conditional move
7037 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7038 %{
7039   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7040 
7041   ins_cost(200); // XXX
7042   format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7043   opcode(0x0F, 0x40);
7044   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7045   ins_pipe(pipe_cmov_reg); // XXX
7046 %}
7047 
7048 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7049   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7050   ins_cost(200);
7051   expand %{
7052     cmovP_regU(cop, cr, dst, src);
7053   %}
7054 %}
7055 
7056 // DISABLED: Requires the ADLC to emit a bottom_type call that
7057 // correctly meets the two pointer arguments; one is an incoming
7058 // register but the other is a memory operand.  ALSO appears to
7059 // be buggy with implicit null checks.
7060 //
7061 //// Conditional move
7062 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7063 //%{
7064 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7065 //  ins_cost(250);
7066 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7067 //  opcode(0x0F,0x40);
7068 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7069 //  ins_pipe( pipe_cmov_mem );
7070 //%}
7071 //
7072 //// Conditional move
7073 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7074 //%{
7075 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7076 //  ins_cost(250);
7077 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
7078 //  opcode(0x0F,0x40);
7079 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7080 //  ins_pipe( pipe_cmov_mem );
7081 //%}
7082 
7083 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7084 %{
7085   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7086 
7087   ins_cost(200); // XXX
7088   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7089   opcode(0x0F, 0x40);
7090   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7091   ins_pipe(pipe_cmov_reg);  // XXX
7092 %}
7093 
7094 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7095 %{
7096   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7097 
7098   ins_cost(200); // XXX
7099   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7100   opcode(0x0F, 0x40);
7101   ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7102   ins_pipe(pipe_cmov_mem);  // XXX
7103 %}
7104 
7105 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7106 %{
7107   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7108 
7109   ins_cost(200); // XXX
7110   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7111   opcode(0x0F, 0x40);
7112   ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7113   ins_pipe(pipe_cmov_reg); // XXX
7114 %}
7115 
7116 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7117   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7118   ins_cost(200);
7119   expand %{
7120     cmovL_regU(cop, cr, dst, src);
7121   %}
7122 %}
7123 
7124 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7125 %{
7126   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7127 
7128   ins_cost(200); // XXX
7129   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7130   opcode(0x0F, 0x40);
7131   ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7132   ins_pipe(pipe_cmov_mem); // XXX
7133 %}
7134 
7135 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7136   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7137   ins_cost(200);
7138   expand %{
7139     cmovL_memU(cop, cr, dst, src);
7140   %}
7141 %}
7142 
7143 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7144 %{
7145   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7146 
7147   ins_cost(200); // XXX
7148   format %{ "jn$cop    skip\t# signed cmove float\n\t"
7149             "movss     $dst, $src\n"
7150     "skip:" %}
7151   ins_encode %{
7152     Label Lskip;
7153     // Invert sense of branch from sense of CMOV
7154     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7155     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7156     __ bind(Lskip);
7157   %}
7158   ins_pipe(pipe_slow);
7159 %}
7160 
7161 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7162 // %{
7163 //   match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7164 
7165 //   ins_cost(200); // XXX
7166 //   format %{ "jn$cop    skip\t# signed cmove float\n\t"
7167 //             "movss     $dst, $src\n"
7168 //     "skip:" %}
7169 //   ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7170 //   ins_pipe(pipe_slow);
7171 // %}
7172 
7173 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7174 %{
7175   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7176 
7177   ins_cost(200); // XXX
7178   format %{ "jn$cop    skip\t# unsigned cmove float\n\t"
7179             "movss     $dst, $src\n"
7180     "skip:" %}
7181   ins_encode %{
7182     Label Lskip;
7183     // Invert sense of branch from sense of CMOV
7184     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7185     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7186     __ bind(Lskip);
7187   %}
7188   ins_pipe(pipe_slow);
7189 %}
7190 
7191 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7192   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7193   ins_cost(200);
7194   expand %{
7195     cmovF_regU(cop, cr, dst, src);
7196   %}
7197 %}
7198 
7199 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7200 %{
7201   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7202 
7203   ins_cost(200); // XXX
7204   format %{ "jn$cop    skip\t# signed cmove double\n\t"
7205             "movsd     $dst, $src\n"
7206     "skip:" %}
7207   ins_encode %{
7208     Label Lskip;
7209     // Invert sense of branch from sense of CMOV
7210     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7211     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7212     __ bind(Lskip);
7213   %}
7214   ins_pipe(pipe_slow);
7215 %}
7216 
7217 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7218 %{
7219   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7220 
7221   ins_cost(200); // XXX
7222   format %{ "jn$cop    skip\t# unsigned cmove double\n\t"
7223             "movsd     $dst, $src\n"
7224     "skip:" %}
7225   ins_encode %{
7226     Label Lskip;
7227     // Invert sense of branch from sense of CMOV
7228     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7229     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7230     __ bind(Lskip);
7231   %}
7232   ins_pipe(pipe_slow);
7233 %}
7234 
7235 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7236   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7237   ins_cost(200);
7238   expand %{
7239     cmovD_regU(cop, cr, dst, src);
7240   %}
7241 %}
7242 
7243 //----------Arithmetic Instructions--------------------------------------------
7244 //----------Addition Instructions----------------------------------------------
7245 
7246 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7247 %{
7248   match(Set dst (AddI dst src));
7249   effect(KILL cr);
7250 
7251   format %{ "addl    $dst, $src\t# int" %}
7252   opcode(0x03);
7253   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7254   ins_pipe(ialu_reg_reg);
7255 %}
7256 
7257 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7258 %{
7259   match(Set dst (AddI dst src));
7260   effect(KILL cr);
7261 
7262   format %{ "addl    $dst, $src\t# int" %}
7263   opcode(0x81, 0x00); /* /0 id */
7264   ins_encode(OpcSErm(dst, src), Con8or32(src));
7265   ins_pipe( ialu_reg );
7266 %}
7267 
7268 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7269 %{
7270   match(Set dst (AddI dst (LoadI src)));
7271   effect(KILL cr);
7272 
7273   ins_cost(125); // XXX
7274   format %{ "addl    $dst, $src\t# int" %}
7275   opcode(0x03);
7276   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7277   ins_pipe(ialu_reg_mem);
7278 %}
7279 
7280 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7281 %{
7282   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7283   effect(KILL cr);
7284 
7285   ins_cost(150); // XXX
7286   format %{ "addl    $dst, $src\t# int" %}
7287   opcode(0x01); /* Opcode 01 /r */
7288   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7289   ins_pipe(ialu_mem_reg);
7290 %}
7291 
7292 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7293 %{
7294   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7295   effect(KILL cr);
7296 
7297   ins_cost(125); // XXX
7298   format %{ "addl    $dst, $src\t# int" %}
7299   opcode(0x81); /* Opcode 81 /0 id */
7300   ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7301   ins_pipe(ialu_mem_imm);
7302 %}
7303 
7304 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7305 %{
7306   predicate(UseIncDec);
7307   match(Set dst (AddI dst src));
7308   effect(KILL cr);
7309 
7310   format %{ "incl    $dst\t# int" %}
7311   opcode(0xFF, 0x00); // FF /0
7312   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7313   ins_pipe(ialu_reg);
7314 %}
7315 
7316 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7317 %{
7318   predicate(UseIncDec);
7319   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7320   effect(KILL cr);
7321 
7322   ins_cost(125); // XXX
7323   format %{ "incl    $dst\t# int" %}
7324   opcode(0xFF); /* Opcode FF /0 */
7325   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7326   ins_pipe(ialu_mem_imm);
7327 %}
7328 
7329 // XXX why does that use AddI
7330 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7331 %{
7332   predicate(UseIncDec);
7333   match(Set dst (AddI dst src));
7334   effect(KILL cr);
7335 
7336   format %{ "decl    $dst\t# int" %}
7337   opcode(0xFF, 0x01); // FF /1
7338   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7339   ins_pipe(ialu_reg);
7340 %}
7341 
7342 // XXX why does that use AddI
7343 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7344 %{
7345   predicate(UseIncDec);
7346   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7347   effect(KILL cr);
7348 
7349   ins_cost(125); // XXX
7350   format %{ "decl    $dst\t# int" %}
7351   opcode(0xFF); /* Opcode FF /1 */
7352   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7353   ins_pipe(ialu_mem_imm);
7354 %}
7355 
7356 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7357 %{
7358   match(Set dst (AddI src0 src1));
7359 
7360   ins_cost(110);
7361   format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7362   opcode(0x8D); /* 0x8D /r */
7363   ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7364   ins_pipe(ialu_reg_reg);
7365 %}
7366 
7367 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7368 %{
7369   match(Set dst (AddL dst src));
7370   effect(KILL cr);
7371 
7372   format %{ "addq    $dst, $src\t# long" %}
7373   opcode(0x03);
7374   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7375   ins_pipe(ialu_reg_reg);
7376 %}
7377 
7378 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7379 %{
7380   match(Set dst (AddL dst src));
7381   effect(KILL cr);
7382 
7383   format %{ "addq    $dst, $src\t# long" %}
7384   opcode(0x81, 0x00); /* /0 id */
7385   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7386   ins_pipe( ialu_reg );
7387 %}
7388 
7389 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7390 %{
7391   match(Set dst (AddL dst (LoadL src)));
7392   effect(KILL cr);
7393 
7394   ins_cost(125); // XXX
7395   format %{ "addq    $dst, $src\t# long" %}
7396   opcode(0x03);
7397   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7398   ins_pipe(ialu_reg_mem);
7399 %}
7400 
7401 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7402 %{
7403   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7404   effect(KILL cr);
7405 
7406   ins_cost(150); // XXX
7407   format %{ "addq    $dst, $src\t# long" %}
7408   opcode(0x01); /* Opcode 01 /r */
7409   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7410   ins_pipe(ialu_mem_reg);
7411 %}
7412 
7413 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7414 %{
7415   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7416   effect(KILL cr);
7417 
7418   ins_cost(125); // XXX
7419   format %{ "addq    $dst, $src\t# long" %}
7420   opcode(0x81); /* Opcode 81 /0 id */
7421   ins_encode(REX_mem_wide(dst),
7422              OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7423   ins_pipe(ialu_mem_imm);
7424 %}
7425 
7426 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7427 %{
7428   predicate(UseIncDec);
7429   match(Set dst (AddL dst src));
7430   effect(KILL cr);
7431 
7432   format %{ "incq    $dst\t# long" %}
7433   opcode(0xFF, 0x00); // FF /0
7434   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7435   ins_pipe(ialu_reg);
7436 %}
7437 
7438 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7439 %{
7440   predicate(UseIncDec);
7441   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7442   effect(KILL cr);
7443 
7444   ins_cost(125); // XXX
7445   format %{ "incq    $dst\t# long" %}
7446   opcode(0xFF); /* Opcode FF /0 */
7447   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7448   ins_pipe(ialu_mem_imm);
7449 %}
7450 
7451 // XXX why does that use AddL
7452 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7453 %{
7454   predicate(UseIncDec);
7455   match(Set dst (AddL dst src));
7456   effect(KILL cr);
7457 
7458   format %{ "decq    $dst\t# long" %}
7459   opcode(0xFF, 0x01); // FF /1
7460   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7461   ins_pipe(ialu_reg);
7462 %}
7463 
7464 // XXX why does that use AddL
7465 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7466 %{
7467   predicate(UseIncDec);
7468   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7469   effect(KILL cr);
7470 
7471   ins_cost(125); // XXX
7472   format %{ "decq    $dst\t# long" %}
7473   opcode(0xFF); /* Opcode FF /1 */
7474   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7475   ins_pipe(ialu_mem_imm);
7476 %}
7477 
7478 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7479 %{
7480   match(Set dst (AddL src0 src1));
7481 
7482   ins_cost(110);
7483   format %{ "leaq    $dst, [$src0 + $src1]\t# long" %}
7484   opcode(0x8D); /* 0x8D /r */
7485   ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7486   ins_pipe(ialu_reg_reg);
7487 %}
7488 
7489 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7490 %{
7491   match(Set dst (AddP dst src));
7492   effect(KILL cr);
7493 
7494   format %{ "addq    $dst, $src\t# ptr" %}
7495   opcode(0x03);
7496   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7497   ins_pipe(ialu_reg_reg);
7498 %}
7499 
7500 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7501 %{
7502   match(Set dst (AddP dst src));
7503   effect(KILL cr);
7504 
7505   format %{ "addq    $dst, $src\t# ptr" %}
7506   opcode(0x81, 0x00); /* /0 id */
7507   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7508   ins_pipe( ialu_reg );
7509 %}
7510 
7511 // XXX addP mem ops ????
7512 
7513 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7514 %{
7515   match(Set dst (AddP src0 src1));
7516 
7517   ins_cost(110);
7518   format %{ "leaq    $dst, [$src0 + $src1]\t# ptr" %}
7519   opcode(0x8D); /* 0x8D /r */
7520   ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7521   ins_pipe(ialu_reg_reg);
7522 %}
7523 
7524 instruct checkCastPP(rRegP dst)
7525 %{
7526   match(Set dst (CheckCastPP dst));
7527 
7528   size(0);
7529   format %{ "# checkcastPP of $dst" %}
7530   ins_encode(/* empty encoding */);
7531   ins_pipe(empty);
7532 %}
7533 
7534 instruct castPP(rRegP dst)
7535 %{
7536   match(Set dst (CastPP dst));
7537 
7538   size(0);
7539   format %{ "# castPP of $dst" %}
7540   ins_encode(/* empty encoding */);
7541   ins_pipe(empty);
7542 %}
7543 
7544 instruct castII(rRegI dst)
7545 %{
7546   match(Set dst (CastII dst));
7547 
7548   size(0);
7549   format %{ "# castII of $dst" %}
7550   ins_encode(/* empty encoding */);
7551   ins_cost(0);
7552   ins_pipe(empty);
7553 %}
7554 
7555 // LoadP-locked same as a regular LoadP when used with compare-swap
7556 instruct loadPLocked(rRegP dst, memory mem)
7557 %{
7558   match(Set dst (LoadPLocked mem));
7559 
7560   ins_cost(125); // XXX
7561   format %{ "movq    $dst, $mem\t# ptr locked" %}
7562   opcode(0x8B);
7563   ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7564   ins_pipe(ialu_reg_mem); // XXX
7565 %}
7566 
7567 // Conditional-store of the updated heap-top.
7568 // Used during allocation of the shared heap.
7569 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
7570 
7571 instruct storePConditional(memory heap_top_ptr,
7572                            rax_RegP oldval, rRegP newval,
7573                            rFlagsReg cr)
7574 %{
7575   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7576 
7577   format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7578             "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7579   opcode(0x0F, 0xB1);
7580   ins_encode(lock_prefix,
7581              REX_reg_mem_wide(newval, heap_top_ptr),
7582              OpcP, OpcS,
7583              reg_mem(newval, heap_top_ptr));
7584   ins_pipe(pipe_cmpxchg);
7585 %}
7586 
7587 // Conditional-store of an int value.
7588 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
7589 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7590 %{
7591   match(Set cr (StoreIConditional mem (Binary oldval newval)));
7592   effect(KILL oldval);
7593 
7594   format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7595   opcode(0x0F, 0xB1);
7596   ins_encode(lock_prefix,
7597              REX_reg_mem(newval, mem),
7598              OpcP, OpcS,
7599              reg_mem(newval, mem));
7600   ins_pipe(pipe_cmpxchg);
7601 %}
7602 
7603 // Conditional-store of a long value.
7604 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
7605 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7606 %{
7607   match(Set cr (StoreLConditional mem (Binary oldval newval)));
7608   effect(KILL oldval);
7609 
7610   format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7611   opcode(0x0F, 0xB1);
7612   ins_encode(lock_prefix,
7613              REX_reg_mem_wide(newval, mem),
7614              OpcP, OpcS,
7615              reg_mem(newval, mem));
7616   ins_pipe(pipe_cmpxchg);
7617 %}
7618 
7619 
7620 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7621 instruct compareAndSwapP(rRegI res,
7622                          memory mem_ptr,
7623                          rax_RegP oldval, rRegP newval,
7624                          rFlagsReg cr)
7625 %{
7626   predicate(VM_Version::supports_cx8() && (!UseShenandoahGC || !ShenandoahCASBarrier || n->in(3)->in(1)->bottom_type() == TypePtr::NULL_PTR));
7627   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7628   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7629   effect(KILL cr, KILL oldval);
7630 
7631   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7632             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7633             "sete    $res\n\t"
7634             "movzbl  $res, $res" %}
7635   opcode(0x0F, 0xB1);
7636   ins_encode(lock_prefix,
7637              REX_reg_mem_wide(newval, mem_ptr),
7638              OpcP, OpcS,
7639              reg_mem(newval, mem_ptr),
7640              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7641              REX_reg_breg(res, res), // movzbl
7642              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7643   ins_pipe( pipe_cmpxchg );
7644 %}
7645 
7646 instruct compareAndSwapP_shenandoah(rRegI res,
7647                                     memory mem_ptr,
7648                                     rRegP tmp1, rRegP tmp2,
7649                                     rax_RegP oldval, rRegP newval,
7650                                     rFlagsReg cr)
7651 %{
7652   predicate(VM_Version::supports_cx8() && UseShenandoahGC && ShenandoahCASBarrier && n->in(3)->in(1)->bottom_type() != TypePtr::NULL_PTR);
7653   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7654   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7655   effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval);
7656 
7657   format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7658 
7659   ins_encode %{
7660 #if INCLUDE_SHENANDOAHGC
7661     ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7662             false, // swap
7663             $tmp1$$Register, $tmp2$$Register
7664     );
7665 #else
7666     ShouldNotReachHere();
7667 #endif
7668   %}
7669   ins_pipe( pipe_cmpxchg );
7670 %}
7671 
7672 instruct compareAndSwapL(rRegI res,
7673                          memory mem_ptr,
7674                          rax_RegL oldval, rRegL newval,
7675                          rFlagsReg cr)
7676 %{
7677   predicate(VM_Version::supports_cx8());
7678   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7679   match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7680   effect(KILL cr, KILL oldval);
7681 
7682   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7683             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7684             "sete    $res\n\t"
7685             "movzbl  $res, $res" %}
7686   opcode(0x0F, 0xB1);
7687   ins_encode(lock_prefix,
7688              REX_reg_mem_wide(newval, mem_ptr),
7689              OpcP, OpcS,
7690              reg_mem(newval, mem_ptr),
7691              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7692              REX_reg_breg(res, res), // movzbl
7693              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7694   ins_pipe( pipe_cmpxchg );
7695 %}
7696 
7697 instruct compareAndSwapI(rRegI res,
7698                          memory mem_ptr,
7699                          rax_RegI oldval, rRegI newval,
7700                          rFlagsReg cr)
7701 %{
7702   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7703   match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7704   effect(KILL cr, KILL oldval);
7705 
7706   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7707             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7708             "sete    $res\n\t"
7709             "movzbl  $res, $res" %}
7710   opcode(0x0F, 0xB1);
7711   ins_encode(lock_prefix,
7712              REX_reg_mem(newval, mem_ptr),
7713              OpcP, OpcS,
7714              reg_mem(newval, mem_ptr),
7715              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7716              REX_reg_breg(res, res), // movzbl
7717              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7718   ins_pipe( pipe_cmpxchg );
7719 %}
7720 
7721 instruct compareAndSwapB(rRegI res,
7722                          memory mem_ptr,
7723                          rax_RegI oldval, rRegI newval,
7724                          rFlagsReg cr)
7725 %{
7726   match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7727   match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7728   effect(KILL cr, KILL oldval);
7729 
7730   format %{ "cmpxchgb $mem_ptr,$newval\t# "
7731             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7732             "sete    $res\n\t"
7733             "movzbl  $res, $res" %}
7734   opcode(0x0F, 0xB0);
7735   ins_encode(lock_prefix,
7736              REX_breg_mem(newval, mem_ptr),
7737              OpcP, OpcS,
7738              reg_mem(newval, mem_ptr),
7739              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7740              REX_reg_breg(res, res), // movzbl
7741              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7742   ins_pipe( pipe_cmpxchg );
7743 %}
7744 
7745 instruct compareAndSwapS(rRegI res,
7746                          memory mem_ptr,
7747                          rax_RegI oldval, rRegI newval,
7748                          rFlagsReg cr)
7749 %{
7750   match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7751   match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7752   effect(KILL cr, KILL oldval);
7753 
7754   format %{ "cmpxchgw $mem_ptr,$newval\t# "
7755             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7756             "sete    $res\n\t"
7757             "movzbl  $res, $res" %}
7758   opcode(0x0F, 0xB1);
7759   ins_encode(lock_prefix,
7760              SizePrefix,
7761              REX_reg_mem(newval, mem_ptr),
7762              OpcP, OpcS,
7763              reg_mem(newval, mem_ptr),
7764              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7765              REX_reg_breg(res, res), // movzbl
7766              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7767   ins_pipe( pipe_cmpxchg );
7768 %}
7769 
7770 instruct compareAndSwapN(rRegI res,
7771                           memory mem_ptr,
7772                           rax_RegN oldval, rRegN newval,
7773                           rFlagsReg cr) %{
7774   predicate(!UseShenandoahGC || !ShenandoahCASBarrier || n->in(3)->in(1)->bottom_type() == TypeNarrowOop::NULL_PTR);
7775   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7776   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7777   effect(KILL cr, KILL oldval);
7778 
7779   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7780             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7781             "sete    $res\n\t"
7782             "movzbl  $res, $res" %}
7783   opcode(0x0F, 0xB1);
7784   ins_encode(lock_prefix,
7785              REX_reg_mem(newval, mem_ptr),
7786              OpcP, OpcS,
7787              reg_mem(newval, mem_ptr),
7788              REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7789              REX_reg_breg(res, res), // movzbl
7790              Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7791   ins_pipe( pipe_cmpxchg );
7792 %}
7793 
7794 instruct compareAndSwapN_shenandoah(rRegI res,
7795                                     memory mem_ptr,
7796                                     rRegP tmp1, rRegP tmp2,
7797                                     rax_RegN oldval, rRegN newval,
7798                                     rFlagsReg cr) %{
7799   predicate(UseShenandoahGC && ShenandoahCASBarrier && n->in(3)->in(1)->bottom_type() != TypeNarrowOop::NULL_PTR);
7800   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7801   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7802   effect(TEMP tmp1, TEMP tmp2, KILL cr, KILL oldval);
7803 
7804   format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7805 
7806   ins_encode %{
7807 #if INCLUDE_SHENANDOAHGC
7808     ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, $res$$Register, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7809             false, // swap
7810             $tmp1$$Register, $tmp2$$Register
7811     );
7812 #else
7813     ShouldNotReachHere();
7814 #endif
7815   %}
7816   ins_pipe( pipe_cmpxchg );
7817 %}
7818 
7819 instruct compareAndExchangeB(
7820                          memory mem_ptr,
7821                          rax_RegI oldval, rRegI newval,
7822                          rFlagsReg cr)
7823 %{
7824   match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7825   effect(KILL cr);
7826 
7827   format %{ "cmpxchgb $mem_ptr,$newval\t# "
7828             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7829   opcode(0x0F, 0xB0);
7830   ins_encode(lock_prefix,
7831              REX_breg_mem(newval, mem_ptr),
7832              OpcP, OpcS,
7833              reg_mem(newval, mem_ptr) // lock cmpxchg
7834              );
7835   ins_pipe( pipe_cmpxchg );
7836 %}
7837 
7838 instruct compareAndExchangeS(
7839                          memory mem_ptr,
7840                          rax_RegI oldval, rRegI newval,
7841                          rFlagsReg cr)
7842 %{
7843   match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7844   effect(KILL cr);
7845 
7846   format %{ "cmpxchgw $mem_ptr,$newval\t# "
7847             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7848   opcode(0x0F, 0xB1);
7849   ins_encode(lock_prefix,
7850              SizePrefix,
7851              REX_reg_mem(newval, mem_ptr),
7852              OpcP, OpcS,
7853              reg_mem(newval, mem_ptr) // lock cmpxchg
7854              );
7855   ins_pipe( pipe_cmpxchg );
7856 %}
7857 
7858 instruct compareAndExchangeI(
7859                          memory mem_ptr,
7860                          rax_RegI oldval, rRegI newval,
7861                          rFlagsReg cr)
7862 %{
7863   match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7864   effect(KILL cr);
7865 
7866   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7867             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7868   opcode(0x0F, 0xB1);
7869   ins_encode(lock_prefix,
7870              REX_reg_mem(newval, mem_ptr),
7871              OpcP, OpcS,
7872              reg_mem(newval, mem_ptr) // lock cmpxchg
7873              );
7874   ins_pipe( pipe_cmpxchg );
7875 %}
7876 
7877 instruct compareAndExchangeL(
7878                          memory mem_ptr,
7879                          rax_RegL oldval, rRegL newval,
7880                          rFlagsReg cr)
7881 %{
7882   predicate(VM_Version::supports_cx8());
7883   match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7884   effect(KILL cr);
7885 
7886   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7887             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
7888   opcode(0x0F, 0xB1);
7889   ins_encode(lock_prefix,
7890              REX_reg_mem_wide(newval, mem_ptr),
7891              OpcP, OpcS,
7892              reg_mem(newval, mem_ptr)  // lock cmpxchg
7893             );
7894   ins_pipe( pipe_cmpxchg );
7895 %}
7896 
7897 instruct compareAndExchangeN(
7898                           memory mem_ptr,
7899                           rax_RegN oldval, rRegN newval,
7900                           rFlagsReg cr) %{
7901   predicate(!UseShenandoahGC || !ShenandoahCASBarrier || n->in(3)->in(1)->bottom_type() == TypeNarrowOop::NULL_PTR);
7902   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7903   effect(KILL cr);
7904 
7905   format %{ "cmpxchgl $mem_ptr,$newval\t# "
7906             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7907   opcode(0x0F, 0xB1);
7908   ins_encode(lock_prefix,
7909              REX_reg_mem(newval, mem_ptr),
7910              OpcP, OpcS,
7911              reg_mem(newval, mem_ptr)  // lock cmpxchg
7912           );
7913   ins_pipe( pipe_cmpxchg );
7914 %}
7915 
7916 instruct compareAndExchangeN_shenandoah(memory mem_ptr,
7917                                         rax_RegN oldval, rRegN newval,
7918                                         rRegP tmp1, rRegP tmp2,
7919                                         rFlagsReg cr) %{
7920   predicate(UseShenandoahGC && ShenandoahCASBarrier && n->in(3)->in(1)->bottom_type() != TypeNarrowOop::NULL_PTR);
7921   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7922   effect(TEMP tmp1, TEMP tmp2, KILL cr);
7923 
7924   format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7925 
7926   ins_encode %{
7927 #if INCLUDE_SHENANDOAHGC
7928     ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7929             true, // exchange
7930             $tmp1$$Register, $tmp2$$Register
7931     );
7932 #else
7933     ShouldNotReachHere();
7934 #endif
7935   %}
7936   ins_pipe( pipe_cmpxchg );
7937 %}
7938 
7939 instruct compareAndExchangeP(
7940                          memory mem_ptr,
7941                          rax_RegP oldval, rRegP newval,
7942                          rFlagsReg cr)
7943 %{
7944   predicate(VM_Version::supports_cx8() && (!UseShenandoahGC || ShenandoahCASBarrier || n->in(3)->in(1)->bottom_type() == TypePtr::NULL_PTR));
7945   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7946   effect(KILL cr);
7947 
7948   format %{ "cmpxchgq $mem_ptr,$newval\t# "
7949             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7950   opcode(0x0F, 0xB1);
7951   ins_encode(lock_prefix,
7952              REX_reg_mem_wide(newval, mem_ptr),
7953              OpcP, OpcS,
7954              reg_mem(newval, mem_ptr)  // lock cmpxchg
7955           );
7956   ins_pipe( pipe_cmpxchg );
7957 %}
7958 
7959 instruct compareAndExchangeP_shenandoah(memory mem_ptr,
7960                                         rax_RegP oldval, rRegP newval,
7961                                         rRegP tmp1, rRegP tmp2,
7962                                         rFlagsReg cr)
7963 %{
7964   predicate(VM_Version::supports_cx8() && UseShenandoahGC && ShenandoahCASBarrier && n->in(3)->in(1)->bottom_type() != TypePtr::NULL_PTR);
7965   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7966   effect(KILL cr, TEMP tmp1, TEMP tmp2);
7967   ins_cost(1000);
7968 
7969   format %{ "shenandoah_cas_oop $mem_ptr,$newval" %}
7970 
7971   ins_encode %{
7972 #if INCLUDE_SHENANDOAHGC
7973     ShenandoahBarrierSet::assembler()->cmpxchg_oop(&_masm, NULL, $mem_ptr$$Address, $oldval$$Register, $newval$$Register,
7974             true,  // exchange
7975             $tmp1$$Register, $tmp2$$Register
7976     );
7977 #else
7978     ShouldNotReachHere();
7979 #endif
7980   %}
7981   ins_pipe( pipe_cmpxchg );
7982 %}
7983 
7984 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7985   predicate(n->as_LoadStore()->result_not_used());
7986   match(Set dummy (GetAndAddB mem add));
7987   effect(KILL cr);
7988   format %{ "ADDB  [$mem],$add" %}
7989   ins_encode %{
7990     if (os::is_MP()) { __ lock(); }
7991     __ addb($mem$$Address, $add$$constant);
7992   %}
7993   ins_pipe( pipe_cmpxchg );
7994 %}
7995 
7996 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
7997   match(Set newval (GetAndAddB mem newval));
7998   effect(KILL cr);
7999   format %{ "XADDB  [$mem],$newval" %}
8000   ins_encode %{
8001     if (os::is_MP()) { __ lock(); }
8002     __ xaddb($mem$$Address, $newval$$Register);
8003   %}
8004   ins_pipe( pipe_cmpxchg );
8005 %}
8006 
8007 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8008   predicate(n->as_LoadStore()->result_not_used());
8009   match(Set dummy (GetAndAddS mem add));
8010   effect(KILL cr);
8011   format %{ "ADDW  [$mem],$add" %}
8012   ins_encode %{
8013     if (os::is_MP()) { __ lock(); }
8014     __ addw($mem$$Address, $add$$constant);
8015   %}
8016   ins_pipe( pipe_cmpxchg );
8017 %}
8018 
8019 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
8020   match(Set newval (GetAndAddS mem newval));
8021   effect(KILL cr);
8022   format %{ "XADDW  [$mem],$newval" %}
8023   ins_encode %{
8024     if (os::is_MP()) { __ lock(); }
8025     __ xaddw($mem$$Address, $newval$$Register);
8026   %}
8027   ins_pipe( pipe_cmpxchg );
8028 %}
8029 
8030 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8031   predicate(n->as_LoadStore()->result_not_used());
8032   match(Set dummy (GetAndAddI mem add));
8033   effect(KILL cr);
8034   format %{ "ADDL  [$mem],$add" %}
8035   ins_encode %{
8036     if (os::is_MP()) { __ lock(); }
8037     __ addl($mem$$Address, $add$$constant);
8038   %}
8039   ins_pipe( pipe_cmpxchg );
8040 %}
8041 
8042 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8043   match(Set newval (GetAndAddI mem newval));
8044   effect(KILL cr);
8045   format %{ "XADDL  [$mem],$newval" %}
8046   ins_encode %{
8047     if (os::is_MP()) { __ lock(); }
8048     __ xaddl($mem$$Address, $newval$$Register);
8049   %}
8050   ins_pipe( pipe_cmpxchg );
8051 %}
8052 
8053 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8054   predicate(n->as_LoadStore()->result_not_used());
8055   match(Set dummy (GetAndAddL mem add));
8056   effect(KILL cr);
8057   format %{ "ADDQ  [$mem],$add" %}
8058   ins_encode %{
8059     if (os::is_MP()) { __ lock(); }
8060     __ addq($mem$$Address, $add$$constant);
8061   %}
8062   ins_pipe( pipe_cmpxchg );
8063 %}
8064 
8065 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8066   match(Set newval (GetAndAddL mem newval));
8067   effect(KILL cr);
8068   format %{ "XADDQ  [$mem],$newval" %}
8069   ins_encode %{
8070     if (os::is_MP()) { __ lock(); }
8071     __ xaddq($mem$$Address, $newval$$Register);
8072   %}
8073   ins_pipe( pipe_cmpxchg );
8074 %}
8075 
8076 instruct xchgB( memory mem, rRegI newval) %{
8077   match(Set newval (GetAndSetB mem newval));
8078   format %{ "XCHGB  $newval,[$mem]" %}
8079   ins_encode %{
8080     __ xchgb($newval$$Register, $mem$$Address);
8081   %}
8082   ins_pipe( pipe_cmpxchg );
8083 %}
8084 
8085 instruct xchgS( memory mem, rRegI newval) %{
8086   match(Set newval (GetAndSetS mem newval));
8087   format %{ "XCHGW  $newval,[$mem]" %}
8088   ins_encode %{
8089     __ xchgw($newval$$Register, $mem$$Address);
8090   %}
8091   ins_pipe( pipe_cmpxchg );
8092 %}
8093 
8094 instruct xchgI( memory mem, rRegI newval) %{
8095   match(Set newval (GetAndSetI mem newval));
8096   format %{ "XCHGL  $newval,[$mem]" %}
8097   ins_encode %{
8098     __ xchgl($newval$$Register, $mem$$Address);
8099   %}
8100   ins_pipe( pipe_cmpxchg );
8101 %}
8102 
8103 instruct xchgL( memory mem, rRegL newval) %{
8104   match(Set newval (GetAndSetL mem newval));
8105   format %{ "XCHGL  $newval,[$mem]" %}
8106   ins_encode %{
8107     __ xchgq($newval$$Register, $mem$$Address);
8108   %}
8109   ins_pipe( pipe_cmpxchg );
8110 %}
8111 
8112 instruct xchgP( memory mem, rRegP newval) %{
8113   match(Set newval (GetAndSetP mem newval));
8114   format %{ "XCHGQ  $newval,[$mem]" %}
8115   ins_encode %{
8116     __ xchgq($newval$$Register, $mem$$Address);
8117   %}
8118   ins_pipe( pipe_cmpxchg );
8119 %}
8120 
8121 instruct xchgN( memory mem, rRegN newval) %{
8122   match(Set newval (GetAndSetN mem newval));
8123   format %{ "XCHGL  $newval,$mem]" %}
8124   ins_encode %{
8125     __ xchgl($newval$$Register, $mem$$Address);
8126   %}
8127   ins_pipe( pipe_cmpxchg );
8128 %}
8129 
8130 //----------Subtraction Instructions-------------------------------------------
8131 
8132 // Integer Subtraction Instructions
8133 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8134 %{
8135   match(Set dst (SubI dst src));
8136   effect(KILL cr);
8137 
8138   format %{ "subl    $dst, $src\t# int" %}
8139   opcode(0x2B);
8140   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8141   ins_pipe(ialu_reg_reg);
8142 %}
8143 
8144 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8145 %{
8146   match(Set dst (SubI dst src));
8147   effect(KILL cr);
8148 
8149   format %{ "subl    $dst, $src\t# int" %}
8150   opcode(0x81, 0x05);  /* Opcode 81 /5 */
8151   ins_encode(OpcSErm(dst, src), Con8or32(src));
8152   ins_pipe(ialu_reg);
8153 %}
8154 
8155 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8156 %{
8157   match(Set dst (SubI dst (LoadI src)));
8158   effect(KILL cr);
8159 
8160   ins_cost(125);
8161   format %{ "subl    $dst, $src\t# int" %}
8162   opcode(0x2B);
8163   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8164   ins_pipe(ialu_reg_mem);
8165 %}
8166 
8167 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8168 %{
8169   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8170   effect(KILL cr);
8171 
8172   ins_cost(150);
8173   format %{ "subl    $dst, $src\t# int" %}
8174   opcode(0x29); /* Opcode 29 /r */
8175   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8176   ins_pipe(ialu_mem_reg);
8177 %}
8178 
8179 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8180 %{
8181   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8182   effect(KILL cr);
8183 
8184   ins_cost(125); // XXX
8185   format %{ "subl    $dst, $src\t# int" %}
8186   opcode(0x81); /* Opcode 81 /5 id */
8187   ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8188   ins_pipe(ialu_mem_imm);
8189 %}
8190 
8191 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8192 %{
8193   match(Set dst (SubL dst src));
8194   effect(KILL cr);
8195 
8196   format %{ "subq    $dst, $src\t# long" %}
8197   opcode(0x2B);
8198   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8199   ins_pipe(ialu_reg_reg);
8200 %}
8201 
8202 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8203 %{
8204   match(Set dst (SubL dst src));
8205   effect(KILL cr);
8206 
8207   format %{ "subq    $dst, $src\t# long" %}
8208   opcode(0x81, 0x05);  /* Opcode 81 /5 */
8209   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8210   ins_pipe(ialu_reg);
8211 %}
8212 
8213 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8214 %{
8215   match(Set dst (SubL dst (LoadL src)));
8216   effect(KILL cr);
8217 
8218   ins_cost(125);
8219   format %{ "subq    $dst, $src\t# long" %}
8220   opcode(0x2B);
8221   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8222   ins_pipe(ialu_reg_mem);
8223 %}
8224 
8225 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8226 %{
8227   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8228   effect(KILL cr);
8229 
8230   ins_cost(150);
8231   format %{ "subq    $dst, $src\t# long" %}
8232   opcode(0x29); /* Opcode 29 /r */
8233   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8234   ins_pipe(ialu_mem_reg);
8235 %}
8236 
8237 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8238 %{
8239   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8240   effect(KILL cr);
8241 
8242   ins_cost(125); // XXX
8243   format %{ "subq    $dst, $src\t# long" %}
8244   opcode(0x81); /* Opcode 81 /5 id */
8245   ins_encode(REX_mem_wide(dst),
8246              OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8247   ins_pipe(ialu_mem_imm);
8248 %}
8249 
8250 // Subtract from a pointer
8251 // XXX hmpf???
8252 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8253 %{
8254   match(Set dst (AddP dst (SubI zero src)));
8255   effect(KILL cr);
8256 
8257   format %{ "subq    $dst, $src\t# ptr - int" %}
8258   opcode(0x2B);
8259   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8260   ins_pipe(ialu_reg_reg);
8261 %}
8262 
8263 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8264 %{
8265   match(Set dst (SubI zero dst));
8266   effect(KILL cr);
8267 
8268   format %{ "negl    $dst\t# int" %}
8269   opcode(0xF7, 0x03);  // Opcode F7 /3
8270   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8271   ins_pipe(ialu_reg);
8272 %}
8273 
8274 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8275 %{
8276   match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8277   effect(KILL cr);
8278 
8279   format %{ "negl    $dst\t# int" %}
8280   opcode(0xF7, 0x03);  // Opcode F7 /3
8281   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8282   ins_pipe(ialu_reg);
8283 %}
8284 
8285 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8286 %{
8287   match(Set dst (SubL zero dst));
8288   effect(KILL cr);
8289 
8290   format %{ "negq    $dst\t# long" %}
8291   opcode(0xF7, 0x03);  // Opcode F7 /3
8292   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8293   ins_pipe(ialu_reg);
8294 %}
8295 
8296 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8297 %{
8298   match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8299   effect(KILL cr);
8300 
8301   format %{ "negq    $dst\t# long" %}
8302   opcode(0xF7, 0x03);  // Opcode F7 /3
8303   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8304   ins_pipe(ialu_reg);
8305 %}
8306 
8307 //----------Multiplication/Division Instructions-------------------------------
8308 // Integer Multiplication Instructions
8309 // Multiply Register
8310 
8311 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8312 %{
8313   match(Set dst (MulI dst src));
8314   effect(KILL cr);
8315 
8316   ins_cost(300);
8317   format %{ "imull   $dst, $src\t# int" %}
8318   opcode(0x0F, 0xAF);
8319   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8320   ins_pipe(ialu_reg_reg_alu0);
8321 %}
8322 
8323 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8324 %{
8325   match(Set dst (MulI src imm));
8326   effect(KILL cr);
8327 
8328   ins_cost(300);
8329   format %{ "imull   $dst, $src, $imm\t# int" %}
8330   opcode(0x69); /* 69 /r id */
8331   ins_encode(REX_reg_reg(dst, src),
8332              OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8333   ins_pipe(ialu_reg_reg_alu0);
8334 %}
8335 
8336 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8337 %{
8338   match(Set dst (MulI dst (LoadI src)));
8339   effect(KILL cr);
8340 
8341   ins_cost(350);
8342   format %{ "imull   $dst, $src\t# int" %}
8343   opcode(0x0F, 0xAF);
8344   ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8345   ins_pipe(ialu_reg_mem_alu0);
8346 %}
8347 
8348 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8349 %{
8350   match(Set dst (MulI (LoadI src) imm));
8351   effect(KILL cr);
8352 
8353   ins_cost(300);
8354   format %{ "imull   $dst, $src, $imm\t# int" %}
8355   opcode(0x69); /* 69 /r id */
8356   ins_encode(REX_reg_mem(dst, src),
8357              OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8358   ins_pipe(ialu_reg_mem_alu0);
8359 %}
8360 
8361 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8362 %{
8363   match(Set dst (MulL dst src));
8364   effect(KILL cr);
8365 
8366   ins_cost(300);
8367   format %{ "imulq   $dst, $src\t# long" %}
8368   opcode(0x0F, 0xAF);
8369   ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8370   ins_pipe(ialu_reg_reg_alu0);
8371 %}
8372 
8373 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8374 %{
8375   match(Set dst (MulL src imm));
8376   effect(KILL cr);
8377 
8378   ins_cost(300);
8379   format %{ "imulq   $dst, $src, $imm\t# long" %}
8380   opcode(0x69); /* 69 /r id */
8381   ins_encode(REX_reg_reg_wide(dst, src),
8382              OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8383   ins_pipe(ialu_reg_reg_alu0);
8384 %}
8385 
8386 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8387 %{
8388   match(Set dst (MulL dst (LoadL src)));
8389   effect(KILL cr);
8390 
8391   ins_cost(350);
8392   format %{ "imulq   $dst, $src\t# long" %}
8393   opcode(0x0F, 0xAF);
8394   ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8395   ins_pipe(ialu_reg_mem_alu0);
8396 %}
8397 
8398 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8399 %{
8400   match(Set dst (MulL (LoadL src) imm));
8401   effect(KILL cr);
8402 
8403   ins_cost(300);
8404   format %{ "imulq   $dst, $src, $imm\t# long" %}
8405   opcode(0x69); /* 69 /r id */
8406   ins_encode(REX_reg_mem_wide(dst, src),
8407              OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8408   ins_pipe(ialu_reg_mem_alu0);
8409 %}
8410 
8411 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8412 %{
8413   match(Set dst (MulHiL src rax));
8414   effect(USE_KILL rax, KILL cr);
8415 
8416   ins_cost(300);
8417   format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
8418   opcode(0xF7, 0x5); /* Opcode F7 /5 */
8419   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8420   ins_pipe(ialu_reg_reg_alu0);
8421 %}
8422 
8423 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8424                    rFlagsReg cr)
8425 %{
8426   match(Set rax (DivI rax div));
8427   effect(KILL rdx, KILL cr);
8428 
8429   ins_cost(30*100+10*100); // XXX
8430   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
8431             "jne,s   normal\n\t"
8432             "xorl    rdx, rdx\n\t"
8433             "cmpl    $div, -1\n\t"
8434             "je,s    done\n"
8435     "normal: cdql\n\t"
8436             "idivl   $div\n"
8437     "done:"        %}
8438   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8439   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8440   ins_pipe(ialu_reg_reg_alu0);
8441 %}
8442 
8443 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8444                    rFlagsReg cr)
8445 %{
8446   match(Set rax (DivL rax div));
8447   effect(KILL rdx, KILL cr);
8448 
8449   ins_cost(30*100+10*100); // XXX
8450   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
8451             "cmpq    rax, rdx\n\t"
8452             "jne,s   normal\n\t"
8453             "xorl    rdx, rdx\n\t"
8454             "cmpq    $div, -1\n\t"
8455             "je,s    done\n"
8456     "normal: cdqq\n\t"
8457             "idivq   $div\n"
8458     "done:"        %}
8459   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8460   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8461   ins_pipe(ialu_reg_reg_alu0);
8462 %}
8463 
8464 // Integer DIVMOD with Register, both quotient and mod results
8465 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8466                              rFlagsReg cr)
8467 %{
8468   match(DivModI rax div);
8469   effect(KILL cr);
8470 
8471   ins_cost(30*100+10*100); // XXX
8472   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
8473             "jne,s   normal\n\t"
8474             "xorl    rdx, rdx\n\t"
8475             "cmpl    $div, -1\n\t"
8476             "je,s    done\n"
8477     "normal: cdql\n\t"
8478             "idivl   $div\n"
8479     "done:"        %}
8480   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8481   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8482   ins_pipe(pipe_slow);
8483 %}
8484 
8485 // Long DIVMOD with Register, both quotient and mod results
8486 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8487                              rFlagsReg cr)
8488 %{
8489   match(DivModL rax div);
8490   effect(KILL cr);
8491 
8492   ins_cost(30*100+10*100); // XXX
8493   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
8494             "cmpq    rax, rdx\n\t"
8495             "jne,s   normal\n\t"
8496             "xorl    rdx, rdx\n\t"
8497             "cmpq    $div, -1\n\t"
8498             "je,s    done\n"
8499     "normal: cdqq\n\t"
8500             "idivq   $div\n"
8501     "done:"        %}
8502   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8503   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8504   ins_pipe(pipe_slow);
8505 %}
8506 
8507 //----------- DivL-By-Constant-Expansions--------------------------------------
8508 // DivI cases are handled by the compiler
8509 
8510 // Magic constant, reciprocal of 10
8511 instruct loadConL_0x6666666666666667(rRegL dst)
8512 %{
8513   effect(DEF dst);
8514 
8515   format %{ "movq    $dst, #0x666666666666667\t# Used in div-by-10" %}
8516   ins_encode(load_immL(dst, 0x6666666666666667));
8517   ins_pipe(ialu_reg);
8518 %}
8519 
8520 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8521 %{
8522   effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8523 
8524   format %{ "imulq   rdx:rax, rax, $src\t# Used in div-by-10" %}
8525   opcode(0xF7, 0x5); /* Opcode F7 /5 */
8526   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8527   ins_pipe(ialu_reg_reg_alu0);
8528 %}
8529 
8530 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8531 %{
8532   effect(USE_DEF dst, KILL cr);
8533 
8534   format %{ "sarq    $dst, #63\t# Used in div-by-10" %}
8535   opcode(0xC1, 0x7); /* C1 /7 ib */
8536   ins_encode(reg_opc_imm_wide(dst, 0x3F));
8537   ins_pipe(ialu_reg);
8538 %}
8539 
8540 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8541 %{
8542   effect(USE_DEF dst, KILL cr);
8543 
8544   format %{ "sarq    $dst, #2\t# Used in div-by-10" %}
8545   opcode(0xC1, 0x7); /* C1 /7 ib */
8546   ins_encode(reg_opc_imm_wide(dst, 0x2));
8547   ins_pipe(ialu_reg);
8548 %}
8549 
8550 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8551 %{
8552   match(Set dst (DivL src div));
8553 
8554   ins_cost((5+8)*100);
8555   expand %{
8556     rax_RegL rax;                     // Killed temp
8557     rFlagsReg cr;                     // Killed
8558     loadConL_0x6666666666666667(rax); // movq  rax, 0x6666666666666667
8559     mul_hi(dst, src, rax, cr);        // mulq  rdx:rax <= rax * $src
8560     sarL_rReg_63(src, cr);            // sarq  src, 63
8561     sarL_rReg_2(dst, cr);             // sarq  rdx, 2
8562     subL_rReg(dst, src, cr);          // subl  rdx, src
8563   %}
8564 %}
8565 
8566 //-----------------------------------------------------------------------------
8567 
8568 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8569                    rFlagsReg cr)
8570 %{
8571   match(Set rdx (ModI rax div));
8572   effect(KILL rax, KILL cr);
8573 
8574   ins_cost(300); // XXX
8575   format %{ "cmpl    rax, 0x80000000\t# irem\n\t"
8576             "jne,s   normal\n\t"
8577             "xorl    rdx, rdx\n\t"
8578             "cmpl    $div, -1\n\t"
8579             "je,s    done\n"
8580     "normal: cdql\n\t"
8581             "idivl   $div\n"
8582     "done:"        %}
8583   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8584   ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8585   ins_pipe(ialu_reg_reg_alu0);
8586 %}
8587 
8588 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8589                    rFlagsReg cr)
8590 %{
8591   match(Set rdx (ModL rax div));
8592   effect(KILL rax, KILL cr);
8593 
8594   ins_cost(300); // XXX
8595   format %{ "movq    rdx, 0x8000000000000000\t# lrem\n\t"
8596             "cmpq    rax, rdx\n\t"
8597             "jne,s   normal\n\t"
8598             "xorl    rdx, rdx\n\t"
8599             "cmpq    $div, -1\n\t"
8600             "je,s    done\n"
8601     "normal: cdqq\n\t"
8602             "idivq   $div\n"
8603     "done:"        %}
8604   opcode(0xF7, 0x7);  /* Opcode F7 /7 */
8605   ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8606   ins_pipe(ialu_reg_reg_alu0);
8607 %}
8608 
8609 // Integer Shift Instructions
8610 // Shift Left by one
8611 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8612 %{
8613   match(Set dst (LShiftI dst shift));
8614   effect(KILL cr);
8615 
8616   format %{ "sall    $dst, $shift" %}
8617   opcode(0xD1, 0x4); /* D1 /4 */
8618   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8619   ins_pipe(ialu_reg);
8620 %}
8621 
8622 // Shift Left by one
8623 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8624 %{
8625   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8626   effect(KILL cr);
8627 
8628   format %{ "sall    $dst, $shift\t" %}
8629   opcode(0xD1, 0x4); /* D1 /4 */
8630   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8631   ins_pipe(ialu_mem_imm);
8632 %}
8633 
8634 // Shift Left by 8-bit immediate
8635 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8636 %{
8637   match(Set dst (LShiftI dst shift));
8638   effect(KILL cr);
8639 
8640   format %{ "sall    $dst, $shift" %}
8641   opcode(0xC1, 0x4); /* C1 /4 ib */
8642   ins_encode(reg_opc_imm(dst, shift));
8643   ins_pipe(ialu_reg);
8644 %}
8645 
8646 // Shift Left by 8-bit immediate
8647 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8648 %{
8649   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8650   effect(KILL cr);
8651 
8652   format %{ "sall    $dst, $shift" %}
8653   opcode(0xC1, 0x4); /* C1 /4 ib */
8654   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8655   ins_pipe(ialu_mem_imm);
8656 %}
8657 
8658 // Shift Left by variable
8659 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8660 %{
8661   match(Set dst (LShiftI dst shift));
8662   effect(KILL cr);
8663 
8664   format %{ "sall    $dst, $shift" %}
8665   opcode(0xD3, 0x4); /* D3 /4 */
8666   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8667   ins_pipe(ialu_reg_reg);
8668 %}
8669 
8670 // Shift Left by variable
8671 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8672 %{
8673   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8674   effect(KILL cr);
8675 
8676   format %{ "sall    $dst, $shift" %}
8677   opcode(0xD3, 0x4); /* D3 /4 */
8678   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8679   ins_pipe(ialu_mem_reg);
8680 %}
8681 
8682 // Arithmetic shift right by one
8683 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8684 %{
8685   match(Set dst (RShiftI dst shift));
8686   effect(KILL cr);
8687 
8688   format %{ "sarl    $dst, $shift" %}
8689   opcode(0xD1, 0x7); /* D1 /7 */
8690   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8691   ins_pipe(ialu_reg);
8692 %}
8693 
8694 // Arithmetic shift right by one
8695 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8696 %{
8697   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8698   effect(KILL cr);
8699 
8700   format %{ "sarl    $dst, $shift" %}
8701   opcode(0xD1, 0x7); /* D1 /7 */
8702   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8703   ins_pipe(ialu_mem_imm);
8704 %}
8705 
8706 // Arithmetic Shift Right by 8-bit immediate
8707 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8708 %{
8709   match(Set dst (RShiftI dst shift));
8710   effect(KILL cr);
8711 
8712   format %{ "sarl    $dst, $shift" %}
8713   opcode(0xC1, 0x7); /* C1 /7 ib */
8714   ins_encode(reg_opc_imm(dst, shift));
8715   ins_pipe(ialu_mem_imm);
8716 %}
8717 
8718 // Arithmetic Shift Right by 8-bit immediate
8719 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8720 %{
8721   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8722   effect(KILL cr);
8723 
8724   format %{ "sarl    $dst, $shift" %}
8725   opcode(0xC1, 0x7); /* C1 /7 ib */
8726   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8727   ins_pipe(ialu_mem_imm);
8728 %}
8729 
8730 // Arithmetic Shift Right by variable
8731 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8732 %{
8733   match(Set dst (RShiftI dst shift));
8734   effect(KILL cr);
8735 
8736   format %{ "sarl    $dst, $shift" %}
8737   opcode(0xD3, 0x7); /* D3 /7 */
8738   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8739   ins_pipe(ialu_reg_reg);
8740 %}
8741 
8742 // Arithmetic Shift Right by variable
8743 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8744 %{
8745   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8746   effect(KILL cr);
8747 
8748   format %{ "sarl    $dst, $shift" %}
8749   opcode(0xD3, 0x7); /* D3 /7 */
8750   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8751   ins_pipe(ialu_mem_reg);
8752 %}
8753 
8754 // Logical shift right by one
8755 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8756 %{
8757   match(Set dst (URShiftI dst shift));
8758   effect(KILL cr);
8759 
8760   format %{ "shrl    $dst, $shift" %}
8761   opcode(0xD1, 0x5); /* D1 /5 */
8762   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8763   ins_pipe(ialu_reg);
8764 %}
8765 
8766 // Logical shift right by one
8767 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8768 %{
8769   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8770   effect(KILL cr);
8771 
8772   format %{ "shrl    $dst, $shift" %}
8773   opcode(0xD1, 0x5); /* D1 /5 */
8774   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8775   ins_pipe(ialu_mem_imm);
8776 %}
8777 
8778 // Logical Shift Right by 8-bit immediate
8779 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8780 %{
8781   match(Set dst (URShiftI dst shift));
8782   effect(KILL cr);
8783 
8784   format %{ "shrl    $dst, $shift" %}
8785   opcode(0xC1, 0x5); /* C1 /5 ib */
8786   ins_encode(reg_opc_imm(dst, shift));
8787   ins_pipe(ialu_reg);
8788 %}
8789 
8790 // Logical Shift Right by 8-bit immediate
8791 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8792 %{
8793   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8794   effect(KILL cr);
8795 
8796   format %{ "shrl    $dst, $shift" %}
8797   opcode(0xC1, 0x5); /* C1 /5 ib */
8798   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8799   ins_pipe(ialu_mem_imm);
8800 %}
8801 
8802 // Logical Shift Right by variable
8803 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8804 %{
8805   match(Set dst (URShiftI dst shift));
8806   effect(KILL cr);
8807 
8808   format %{ "shrl    $dst, $shift" %}
8809   opcode(0xD3, 0x5); /* D3 /5 */
8810   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8811   ins_pipe(ialu_reg_reg);
8812 %}
8813 
8814 // Logical Shift Right by variable
8815 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8816 %{
8817   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8818   effect(KILL cr);
8819 
8820   format %{ "shrl    $dst, $shift" %}
8821   opcode(0xD3, 0x5); /* D3 /5 */
8822   ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8823   ins_pipe(ialu_mem_reg);
8824 %}
8825 
8826 // Long Shift Instructions
8827 // Shift Left by one
8828 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8829 %{
8830   match(Set dst (LShiftL dst shift));
8831   effect(KILL cr);
8832 
8833   format %{ "salq    $dst, $shift" %}
8834   opcode(0xD1, 0x4); /* D1 /4 */
8835   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8836   ins_pipe(ialu_reg);
8837 %}
8838 
8839 // Shift Left by one
8840 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8841 %{
8842   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8843   effect(KILL cr);
8844 
8845   format %{ "salq    $dst, $shift" %}
8846   opcode(0xD1, 0x4); /* D1 /4 */
8847   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8848   ins_pipe(ialu_mem_imm);
8849 %}
8850 
8851 // Shift Left by 8-bit immediate
8852 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8853 %{
8854   match(Set dst (LShiftL dst shift));
8855   effect(KILL cr);
8856 
8857   format %{ "salq    $dst, $shift" %}
8858   opcode(0xC1, 0x4); /* C1 /4 ib */
8859   ins_encode(reg_opc_imm_wide(dst, shift));
8860   ins_pipe(ialu_reg);
8861 %}
8862 
8863 // Shift Left by 8-bit immediate
8864 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8865 %{
8866   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8867   effect(KILL cr);
8868 
8869   format %{ "salq    $dst, $shift" %}
8870   opcode(0xC1, 0x4); /* C1 /4 ib */
8871   ins_encode(REX_mem_wide(dst), OpcP,
8872              RM_opc_mem(secondary, dst), Con8or32(shift));
8873   ins_pipe(ialu_mem_imm);
8874 %}
8875 
8876 // Shift Left by variable
8877 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8878 %{
8879   match(Set dst (LShiftL dst shift));
8880   effect(KILL cr);
8881 
8882   format %{ "salq    $dst, $shift" %}
8883   opcode(0xD3, 0x4); /* D3 /4 */
8884   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8885   ins_pipe(ialu_reg_reg);
8886 %}
8887 
8888 // Shift Left by variable
8889 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8890 %{
8891   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8892   effect(KILL cr);
8893 
8894   format %{ "salq    $dst, $shift" %}
8895   opcode(0xD3, 0x4); /* D3 /4 */
8896   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8897   ins_pipe(ialu_mem_reg);
8898 %}
8899 
8900 // Arithmetic shift right by one
8901 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8902 %{
8903   match(Set dst (RShiftL dst shift));
8904   effect(KILL cr);
8905 
8906   format %{ "sarq    $dst, $shift" %}
8907   opcode(0xD1, 0x7); /* D1 /7 */
8908   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8909   ins_pipe(ialu_reg);
8910 %}
8911 
8912 // Arithmetic shift right by one
8913 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8914 %{
8915   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8916   effect(KILL cr);
8917 
8918   format %{ "sarq    $dst, $shift" %}
8919   opcode(0xD1, 0x7); /* D1 /7 */
8920   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8921   ins_pipe(ialu_mem_imm);
8922 %}
8923 
8924 // Arithmetic Shift Right by 8-bit immediate
8925 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8926 %{
8927   match(Set dst (RShiftL dst shift));
8928   effect(KILL cr);
8929 
8930   format %{ "sarq    $dst, $shift" %}
8931   opcode(0xC1, 0x7); /* C1 /7 ib */
8932   ins_encode(reg_opc_imm_wide(dst, shift));
8933   ins_pipe(ialu_mem_imm);
8934 %}
8935 
8936 // Arithmetic Shift Right by 8-bit immediate
8937 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8938 %{
8939   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8940   effect(KILL cr);
8941 
8942   format %{ "sarq    $dst, $shift" %}
8943   opcode(0xC1, 0x7); /* C1 /7 ib */
8944   ins_encode(REX_mem_wide(dst), OpcP,
8945              RM_opc_mem(secondary, dst), Con8or32(shift));
8946   ins_pipe(ialu_mem_imm);
8947 %}
8948 
8949 // Arithmetic Shift Right by variable
8950 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8951 %{
8952   match(Set dst (RShiftL dst shift));
8953   effect(KILL cr);
8954 
8955   format %{ "sarq    $dst, $shift" %}
8956   opcode(0xD3, 0x7); /* D3 /7 */
8957   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8958   ins_pipe(ialu_reg_reg);
8959 %}
8960 
8961 // Arithmetic Shift Right by variable
8962 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8963 %{
8964   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8965   effect(KILL cr);
8966 
8967   format %{ "sarq    $dst, $shift" %}
8968   opcode(0xD3, 0x7); /* D3 /7 */
8969   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8970   ins_pipe(ialu_mem_reg);
8971 %}
8972 
8973 // Logical shift right by one
8974 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8975 %{
8976   match(Set dst (URShiftL dst shift));
8977   effect(KILL cr);
8978 
8979   format %{ "shrq    $dst, $shift" %}
8980   opcode(0xD1, 0x5); /* D1 /5 */
8981   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8982   ins_pipe(ialu_reg);
8983 %}
8984 
8985 // Logical shift right by one
8986 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8987 %{
8988   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8989   effect(KILL cr);
8990 
8991   format %{ "shrq    $dst, $shift" %}
8992   opcode(0xD1, 0x5); /* D1 /5 */
8993   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8994   ins_pipe(ialu_mem_imm);
8995 %}
8996 
8997 // Logical Shift Right by 8-bit immediate
8998 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8999 %{
9000   match(Set dst (URShiftL dst shift));
9001   effect(KILL cr);
9002 
9003   format %{ "shrq    $dst, $shift" %}
9004   opcode(0xC1, 0x5); /* C1 /5 ib */
9005   ins_encode(reg_opc_imm_wide(dst, shift));
9006   ins_pipe(ialu_reg);
9007 %}
9008 
9009 
9010 // Logical Shift Right by 8-bit immediate
9011 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9012 %{
9013   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9014   effect(KILL cr);
9015 
9016   format %{ "shrq    $dst, $shift" %}
9017   opcode(0xC1, 0x5); /* C1 /5 ib */
9018   ins_encode(REX_mem_wide(dst), OpcP,
9019              RM_opc_mem(secondary, dst), Con8or32(shift));
9020   ins_pipe(ialu_mem_imm);
9021 %}
9022 
9023 // Logical Shift Right by variable
9024 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9025 %{
9026   match(Set dst (URShiftL dst shift));
9027   effect(KILL cr);
9028 
9029   format %{ "shrq    $dst, $shift" %}
9030   opcode(0xD3, 0x5); /* D3 /5 */
9031   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9032   ins_pipe(ialu_reg_reg);
9033 %}
9034 
9035 // Logical Shift Right by variable
9036 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9037 %{
9038   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9039   effect(KILL cr);
9040 
9041   format %{ "shrq    $dst, $shift" %}
9042   opcode(0xD3, 0x5); /* D3 /5 */
9043   ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9044   ins_pipe(ialu_mem_reg);
9045 %}
9046 
9047 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9048 // This idiom is used by the compiler for the i2b bytecode.
9049 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9050 %{
9051   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9052 
9053   format %{ "movsbl  $dst, $src\t# i2b" %}
9054   opcode(0x0F, 0xBE);
9055   ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9056   ins_pipe(ialu_reg_reg);
9057 %}
9058 
9059 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9060 // This idiom is used by the compiler the i2s bytecode.
9061 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9062 %{
9063   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9064 
9065   format %{ "movswl  $dst, $src\t# i2s" %}
9066   opcode(0x0F, 0xBF);
9067   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9068   ins_pipe(ialu_reg_reg);
9069 %}
9070 
9071 // ROL/ROR instructions
9072 
9073 // ROL expand
9074 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9075   effect(KILL cr, USE_DEF dst);
9076 
9077   format %{ "roll    $dst" %}
9078   opcode(0xD1, 0x0); /* Opcode  D1 /0 */
9079   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9080   ins_pipe(ialu_reg);
9081 %}
9082 
9083 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9084   effect(USE_DEF dst, USE shift, KILL cr);
9085 
9086   format %{ "roll    $dst, $shift" %}
9087   opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9088   ins_encode( reg_opc_imm(dst, shift) );
9089   ins_pipe(ialu_reg);
9090 %}
9091 
9092 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9093 %{
9094   effect(USE_DEF dst, USE shift, KILL cr);
9095 
9096   format %{ "roll    $dst, $shift" %}
9097   opcode(0xD3, 0x0); /* Opcode D3 /0 */
9098   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9099   ins_pipe(ialu_reg_reg);
9100 %}
9101 // end of ROL expand
9102 
9103 // Rotate Left by one
9104 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9105 %{
9106   match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9107 
9108   expand %{
9109     rolI_rReg_imm1(dst, cr);
9110   %}
9111 %}
9112 
9113 // Rotate Left by 8-bit immediate
9114 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9115 %{
9116   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9117   match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9118 
9119   expand %{
9120     rolI_rReg_imm8(dst, lshift, cr);
9121   %}
9122 %}
9123 
9124 // Rotate Left by variable
9125 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9126 %{
9127   match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9128 
9129   expand %{
9130     rolI_rReg_CL(dst, shift, cr);
9131   %}
9132 %}
9133 
9134 // Rotate Left by variable
9135 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9136 %{
9137   match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9138 
9139   expand %{
9140     rolI_rReg_CL(dst, shift, cr);
9141   %}
9142 %}
9143 
9144 // ROR expand
9145 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9146 %{
9147   effect(USE_DEF dst, KILL cr);
9148 
9149   format %{ "rorl    $dst" %}
9150   opcode(0xD1, 0x1); /* D1 /1 */
9151   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9152   ins_pipe(ialu_reg);
9153 %}
9154 
9155 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9156 %{
9157   effect(USE_DEF dst, USE shift, KILL cr);
9158 
9159   format %{ "rorl    $dst, $shift" %}
9160   opcode(0xC1, 0x1); /* C1 /1 ib */
9161   ins_encode(reg_opc_imm(dst, shift));
9162   ins_pipe(ialu_reg);
9163 %}
9164 
9165 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9166 %{
9167   effect(USE_DEF dst, USE shift, KILL cr);
9168 
9169   format %{ "rorl    $dst, $shift" %}
9170   opcode(0xD3, 0x1); /* D3 /1 */
9171   ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9172   ins_pipe(ialu_reg_reg);
9173 %}
9174 // end of ROR expand
9175 
9176 // Rotate Right by one
9177 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9178 %{
9179   match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9180 
9181   expand %{
9182     rorI_rReg_imm1(dst, cr);
9183   %}
9184 %}
9185 
9186 // Rotate Right by 8-bit immediate
9187 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9188 %{
9189   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9190   match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9191 
9192   expand %{
9193     rorI_rReg_imm8(dst, rshift, cr);
9194   %}
9195 %}
9196 
9197 // Rotate Right by variable
9198 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9199 %{
9200   match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9201 
9202   expand %{
9203     rorI_rReg_CL(dst, shift, cr);
9204   %}
9205 %}
9206 
9207 // Rotate Right by variable
9208 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9209 %{
9210   match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9211 
9212   expand %{
9213     rorI_rReg_CL(dst, shift, cr);
9214   %}
9215 %}
9216 
9217 // for long rotate
9218 // ROL expand
9219 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9220   effect(USE_DEF dst, KILL cr);
9221 
9222   format %{ "rolq    $dst" %}
9223   opcode(0xD1, 0x0); /* Opcode  D1 /0 */
9224   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9225   ins_pipe(ialu_reg);
9226 %}
9227 
9228 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9229   effect(USE_DEF dst, USE shift, KILL cr);
9230 
9231   format %{ "rolq    $dst, $shift" %}
9232   opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9233   ins_encode( reg_opc_imm_wide(dst, shift) );
9234   ins_pipe(ialu_reg);
9235 %}
9236 
9237 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9238 %{
9239   effect(USE_DEF dst, USE shift, KILL cr);
9240 
9241   format %{ "rolq    $dst, $shift" %}
9242   opcode(0xD3, 0x0); /* Opcode D3 /0 */
9243   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9244   ins_pipe(ialu_reg_reg);
9245 %}
9246 // end of ROL expand
9247 
9248 // Rotate Left by one
9249 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9250 %{
9251   match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9252 
9253   expand %{
9254     rolL_rReg_imm1(dst, cr);
9255   %}
9256 %}
9257 
9258 // Rotate Left by 8-bit immediate
9259 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9260 %{
9261   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9262   match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9263 
9264   expand %{
9265     rolL_rReg_imm8(dst, lshift, cr);
9266   %}
9267 %}
9268 
9269 // Rotate Left by variable
9270 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9271 %{
9272   match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9273 
9274   expand %{
9275     rolL_rReg_CL(dst, shift, cr);
9276   %}
9277 %}
9278 
9279 // Rotate Left by variable
9280 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9281 %{
9282   match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9283 
9284   expand %{
9285     rolL_rReg_CL(dst, shift, cr);
9286   %}
9287 %}
9288 
9289 // ROR expand
9290 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9291 %{
9292   effect(USE_DEF dst, KILL cr);
9293 
9294   format %{ "rorq    $dst" %}
9295   opcode(0xD1, 0x1); /* D1 /1 */
9296   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9297   ins_pipe(ialu_reg);
9298 %}
9299 
9300 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9301 %{
9302   effect(USE_DEF dst, USE shift, KILL cr);
9303 
9304   format %{ "rorq    $dst, $shift" %}
9305   opcode(0xC1, 0x1); /* C1 /1 ib */
9306   ins_encode(reg_opc_imm_wide(dst, shift));
9307   ins_pipe(ialu_reg);
9308 %}
9309 
9310 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9311 %{
9312   effect(USE_DEF dst, USE shift, KILL cr);
9313 
9314   format %{ "rorq    $dst, $shift" %}
9315   opcode(0xD3, 0x1); /* D3 /1 */
9316   ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9317   ins_pipe(ialu_reg_reg);
9318 %}
9319 // end of ROR expand
9320 
9321 // Rotate Right by one
9322 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9323 %{
9324   match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9325 
9326   expand %{
9327     rorL_rReg_imm1(dst, cr);
9328   %}
9329 %}
9330 
9331 // Rotate Right by 8-bit immediate
9332 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9333 %{
9334   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9335   match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9336 
9337   expand %{
9338     rorL_rReg_imm8(dst, rshift, cr);
9339   %}
9340 %}
9341 
9342 // Rotate Right by variable
9343 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9344 %{
9345   match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9346 
9347   expand %{
9348     rorL_rReg_CL(dst, shift, cr);
9349   %}
9350 %}
9351 
9352 // Rotate Right by variable
9353 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9354 %{
9355   match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9356 
9357   expand %{
9358     rorL_rReg_CL(dst, shift, cr);
9359   %}
9360 %}
9361 
9362 // Logical Instructions
9363 
9364 // Integer Logical Instructions
9365 
9366 // And Instructions
9367 // And Register with Register
9368 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9369 %{
9370   match(Set dst (AndI dst src));
9371   effect(KILL cr);
9372 
9373   format %{ "andl    $dst, $src\t# int" %}
9374   opcode(0x23);
9375   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9376   ins_pipe(ialu_reg_reg);
9377 %}
9378 
9379 // And Register with Immediate 255
9380 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9381 %{
9382   match(Set dst (AndI dst src));
9383 
9384   format %{ "movzbl  $dst, $dst\t# int & 0xFF" %}
9385   opcode(0x0F, 0xB6);
9386   ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9387   ins_pipe(ialu_reg);
9388 %}
9389 
9390 // And Register with Immediate 255 and promote to long
9391 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9392 %{
9393   match(Set dst (ConvI2L (AndI src mask)));
9394 
9395   format %{ "movzbl  $dst, $src\t# int & 0xFF -> long" %}
9396   opcode(0x0F, 0xB6);
9397   ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9398   ins_pipe(ialu_reg);
9399 %}
9400 
9401 // And Register with Immediate 65535
9402 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9403 %{
9404   match(Set dst (AndI dst src));
9405 
9406   format %{ "movzwl  $dst, $dst\t# int & 0xFFFF" %}
9407   opcode(0x0F, 0xB7);
9408   ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9409   ins_pipe(ialu_reg);
9410 %}
9411 
9412 // And Register with Immediate 65535 and promote to long
9413 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9414 %{
9415   match(Set dst (ConvI2L (AndI src mask)));
9416 
9417   format %{ "movzwl  $dst, $src\t# int & 0xFFFF -> long" %}
9418   opcode(0x0F, 0xB7);
9419   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9420   ins_pipe(ialu_reg);
9421 %}
9422 
9423 // And Register with Immediate
9424 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9425 %{
9426   match(Set dst (AndI dst src));
9427   effect(KILL cr);
9428 
9429   format %{ "andl    $dst, $src\t# int" %}
9430   opcode(0x81, 0x04); /* Opcode 81 /4 */
9431   ins_encode(OpcSErm(dst, src), Con8or32(src));
9432   ins_pipe(ialu_reg);
9433 %}
9434 
9435 // And Register with Memory
9436 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9437 %{
9438   match(Set dst (AndI dst (LoadI src)));
9439   effect(KILL cr);
9440 
9441   ins_cost(125);
9442   format %{ "andl    $dst, $src\t# int" %}
9443   opcode(0x23);
9444   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9445   ins_pipe(ialu_reg_mem);
9446 %}
9447 
9448 // And Memory with Register
9449 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9450 %{
9451   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9452   effect(KILL cr);
9453 
9454   ins_cost(150);
9455   format %{ "andl    $dst, $src\t# int" %}
9456   opcode(0x21); /* Opcode 21 /r */
9457   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9458   ins_pipe(ialu_mem_reg);
9459 %}
9460 
9461 // And Memory with Immediate
9462 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9463 %{
9464   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9465   effect(KILL cr);
9466 
9467   ins_cost(125);
9468   format %{ "andl    $dst, $src\t# int" %}
9469   opcode(0x81, 0x4); /* Opcode 81 /4 id */
9470   ins_encode(REX_mem(dst), OpcSE(src),
9471              RM_opc_mem(secondary, dst), Con8or32(src));
9472   ins_pipe(ialu_mem_imm);
9473 %}
9474 
9475 // BMI1 instructions
9476 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9477   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9478   predicate(UseBMI1Instructions);
9479   effect(KILL cr);
9480 
9481   ins_cost(125);
9482   format %{ "andnl  $dst, $src1, $src2" %}
9483 
9484   ins_encode %{
9485     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9486   %}
9487   ins_pipe(ialu_reg_mem);
9488 %}
9489 
9490 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9491   match(Set dst (AndI (XorI src1 minus_1) src2));
9492   predicate(UseBMI1Instructions);
9493   effect(KILL cr);
9494 
9495   format %{ "andnl  $dst, $src1, $src2" %}
9496 
9497   ins_encode %{
9498     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9499   %}
9500   ins_pipe(ialu_reg);
9501 %}
9502 
9503 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
9504   match(Set dst (AndI (SubI imm_zero src) src));
9505   predicate(UseBMI1Instructions);
9506   effect(KILL cr);
9507 
9508   format %{ "blsil  $dst, $src" %}
9509 
9510   ins_encode %{
9511     __ blsil($dst$$Register, $src$$Register);
9512   %}
9513   ins_pipe(ialu_reg);
9514 %}
9515 
9516 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
9517   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9518   predicate(UseBMI1Instructions);
9519   effect(KILL cr);
9520 
9521   ins_cost(125);
9522   format %{ "blsil  $dst, $src" %}
9523 
9524   ins_encode %{
9525     __ blsil($dst$$Register, $src$$Address);
9526   %}
9527   ins_pipe(ialu_reg_mem);
9528 %}
9529 
9530 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9531 %{
9532   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9533   predicate(UseBMI1Instructions);
9534   effect(KILL cr);
9535 
9536   ins_cost(125);
9537   format %{ "blsmskl $dst, $src" %}
9538 
9539   ins_encode %{
9540     __ blsmskl($dst$$Register, $src$$Address);
9541   %}
9542   ins_pipe(ialu_reg_mem);
9543 %}
9544 
9545 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9546 %{
9547   match(Set dst (XorI (AddI src minus_1) src));
9548   predicate(UseBMI1Instructions);
9549   effect(KILL cr);
9550 
9551   format %{ "blsmskl $dst, $src" %}
9552 
9553   ins_encode %{
9554     __ blsmskl($dst$$Register, $src$$Register);
9555   %}
9556 
9557   ins_pipe(ialu_reg);
9558 %}
9559 
9560 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9561 %{
9562   match(Set dst (AndI (AddI src minus_1) src) );
9563   predicate(UseBMI1Instructions);
9564   effect(KILL cr);
9565 
9566   format %{ "blsrl  $dst, $src" %}
9567 
9568   ins_encode %{
9569     __ blsrl($dst$$Register, $src$$Register);
9570   %}
9571 
9572   ins_pipe(ialu_reg_mem);
9573 %}
9574 
9575 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9576 %{
9577   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9578   predicate(UseBMI1Instructions);
9579   effect(KILL cr);
9580 
9581   ins_cost(125);
9582   format %{ "blsrl  $dst, $src" %}
9583 
9584   ins_encode %{
9585     __ blsrl($dst$$Register, $src$$Address);
9586   %}
9587 
9588   ins_pipe(ialu_reg);
9589 %}
9590 
9591 // Or Instructions
9592 // Or Register with Register
9593 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9594 %{
9595   match(Set dst (OrI dst src));
9596   effect(KILL cr);
9597 
9598   format %{ "orl     $dst, $src\t# int" %}
9599   opcode(0x0B);
9600   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9601   ins_pipe(ialu_reg_reg);
9602 %}
9603 
9604 // Or Register with Immediate
9605 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9606 %{
9607   match(Set dst (OrI dst src));
9608   effect(KILL cr);
9609 
9610   format %{ "orl     $dst, $src\t# int" %}
9611   opcode(0x81, 0x01); /* Opcode 81 /1 id */
9612   ins_encode(OpcSErm(dst, src), Con8or32(src));
9613   ins_pipe(ialu_reg);
9614 %}
9615 
9616 // Or Register with Memory
9617 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9618 %{
9619   match(Set dst (OrI dst (LoadI src)));
9620   effect(KILL cr);
9621 
9622   ins_cost(125);
9623   format %{ "orl     $dst, $src\t# int" %}
9624   opcode(0x0B);
9625   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9626   ins_pipe(ialu_reg_mem);
9627 %}
9628 
9629 // Or Memory with Register
9630 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9631 %{
9632   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9633   effect(KILL cr);
9634 
9635   ins_cost(150);
9636   format %{ "orl     $dst, $src\t# int" %}
9637   opcode(0x09); /* Opcode 09 /r */
9638   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9639   ins_pipe(ialu_mem_reg);
9640 %}
9641 
9642 // Or Memory with Immediate
9643 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9644 %{
9645   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9646   effect(KILL cr);
9647 
9648   ins_cost(125);
9649   format %{ "orl     $dst, $src\t# int" %}
9650   opcode(0x81, 0x1); /* Opcode 81 /1 id */
9651   ins_encode(REX_mem(dst), OpcSE(src),
9652              RM_opc_mem(secondary, dst), Con8or32(src));
9653   ins_pipe(ialu_mem_imm);
9654 %}
9655 
9656 // Xor Instructions
9657 // Xor Register with Register
9658 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9659 %{
9660   match(Set dst (XorI dst src));
9661   effect(KILL cr);
9662 
9663   format %{ "xorl    $dst, $src\t# int" %}
9664   opcode(0x33);
9665   ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9666   ins_pipe(ialu_reg_reg);
9667 %}
9668 
9669 // Xor Register with Immediate -1
9670 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9671   match(Set dst (XorI dst imm));
9672 
9673   format %{ "not    $dst" %}
9674   ins_encode %{
9675      __ notl($dst$$Register);
9676   %}
9677   ins_pipe(ialu_reg);
9678 %}
9679 
9680 // Xor Register with Immediate
9681 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9682 %{
9683   match(Set dst (XorI dst src));
9684   effect(KILL cr);
9685 
9686   format %{ "xorl    $dst, $src\t# int" %}
9687   opcode(0x81, 0x06); /* Opcode 81 /6 id */
9688   ins_encode(OpcSErm(dst, src), Con8or32(src));
9689   ins_pipe(ialu_reg);
9690 %}
9691 
9692 // Xor Register with Memory
9693 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9694 %{
9695   match(Set dst (XorI dst (LoadI src)));
9696   effect(KILL cr);
9697 
9698   ins_cost(125);
9699   format %{ "xorl    $dst, $src\t# int" %}
9700   opcode(0x33);
9701   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9702   ins_pipe(ialu_reg_mem);
9703 %}
9704 
9705 // Xor Memory with Register
9706 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9707 %{
9708   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9709   effect(KILL cr);
9710 
9711   ins_cost(150);
9712   format %{ "xorl    $dst, $src\t# int" %}
9713   opcode(0x31); /* Opcode 31 /r */
9714   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9715   ins_pipe(ialu_mem_reg);
9716 %}
9717 
9718 // Xor Memory with Immediate
9719 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9720 %{
9721   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9722   effect(KILL cr);
9723 
9724   ins_cost(125);
9725   format %{ "xorl    $dst, $src\t# int" %}
9726   opcode(0x81, 0x6); /* Opcode 81 /6 id */
9727   ins_encode(REX_mem(dst), OpcSE(src),
9728              RM_opc_mem(secondary, dst), Con8or32(src));
9729   ins_pipe(ialu_mem_imm);
9730 %}
9731 
9732 
9733 // Long Logical Instructions
9734 
9735 // And Instructions
9736 // And Register with Register
9737 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9738 %{
9739   match(Set dst (AndL dst src));
9740   effect(KILL cr);
9741 
9742   format %{ "andq    $dst, $src\t# long" %}
9743   opcode(0x23);
9744   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9745   ins_pipe(ialu_reg_reg);
9746 %}
9747 
9748 // And Register with Immediate 255
9749 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9750 %{
9751   match(Set dst (AndL dst src));
9752 
9753   format %{ "movzbq  $dst, $dst\t# long & 0xFF" %}
9754   opcode(0x0F, 0xB6);
9755   ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9756   ins_pipe(ialu_reg);
9757 %}
9758 
9759 // And Register with Immediate 65535
9760 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9761 %{
9762   match(Set dst (AndL dst src));
9763 
9764   format %{ "movzwq  $dst, $dst\t# long & 0xFFFF" %}
9765   opcode(0x0F, 0xB7);
9766   ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9767   ins_pipe(ialu_reg);
9768 %}
9769 
9770 // And Register with Immediate
9771 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9772 %{
9773   match(Set dst (AndL dst src));
9774   effect(KILL cr);
9775 
9776   format %{ "andq    $dst, $src\t# long" %}
9777   opcode(0x81, 0x04); /* Opcode 81 /4 */
9778   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9779   ins_pipe(ialu_reg);
9780 %}
9781 
9782 // And Register with Memory
9783 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9784 %{
9785   match(Set dst (AndL dst (LoadL src)));
9786   effect(KILL cr);
9787 
9788   ins_cost(125);
9789   format %{ "andq    $dst, $src\t# long" %}
9790   opcode(0x23);
9791   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9792   ins_pipe(ialu_reg_mem);
9793 %}
9794 
9795 // And Memory with Register
9796 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9797 %{
9798   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9799   effect(KILL cr);
9800 
9801   ins_cost(150);
9802   format %{ "andq    $dst, $src\t# long" %}
9803   opcode(0x21); /* Opcode 21 /r */
9804   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9805   ins_pipe(ialu_mem_reg);
9806 %}
9807 
9808 // And Memory with Immediate
9809 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9810 %{
9811   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9812   effect(KILL cr);
9813 
9814   ins_cost(125);
9815   format %{ "andq    $dst, $src\t# long" %}
9816   opcode(0x81, 0x4); /* Opcode 81 /4 id */
9817   ins_encode(REX_mem_wide(dst), OpcSE(src),
9818              RM_opc_mem(secondary, dst), Con8or32(src));
9819   ins_pipe(ialu_mem_imm);
9820 %}
9821 
9822 // BMI1 instructions
9823 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9824   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9825   predicate(UseBMI1Instructions);
9826   effect(KILL cr);
9827 
9828   ins_cost(125);
9829   format %{ "andnq  $dst, $src1, $src2" %}
9830 
9831   ins_encode %{
9832     __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9833   %}
9834   ins_pipe(ialu_reg_mem);
9835 %}
9836 
9837 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9838   match(Set dst (AndL (XorL src1 minus_1) src2));
9839   predicate(UseBMI1Instructions);
9840   effect(KILL cr);
9841 
9842   format %{ "andnq  $dst, $src1, $src2" %}
9843 
9844   ins_encode %{
9845   __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9846   %}
9847   ins_pipe(ialu_reg_mem);
9848 %}
9849 
9850 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9851   match(Set dst (AndL (SubL imm_zero src) src));
9852   predicate(UseBMI1Instructions);
9853   effect(KILL cr);
9854 
9855   format %{ "blsiq  $dst, $src" %}
9856 
9857   ins_encode %{
9858     __ blsiq($dst$$Register, $src$$Register);
9859   %}
9860   ins_pipe(ialu_reg);
9861 %}
9862 
9863 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9864   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9865   predicate(UseBMI1Instructions);
9866   effect(KILL cr);
9867 
9868   ins_cost(125);
9869   format %{ "blsiq  $dst, $src" %}
9870 
9871   ins_encode %{
9872     __ blsiq($dst$$Register, $src$$Address);
9873   %}
9874   ins_pipe(ialu_reg_mem);
9875 %}
9876 
9877 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9878 %{
9879   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9880   predicate(UseBMI1Instructions);
9881   effect(KILL cr);
9882 
9883   ins_cost(125);
9884   format %{ "blsmskq $dst, $src" %}
9885 
9886   ins_encode %{
9887     __ blsmskq($dst$$Register, $src$$Address);
9888   %}
9889   ins_pipe(ialu_reg_mem);
9890 %}
9891 
9892 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9893 %{
9894   match(Set dst (XorL (AddL src minus_1) src));
9895   predicate(UseBMI1Instructions);
9896   effect(KILL cr);
9897 
9898   format %{ "blsmskq $dst, $src" %}
9899 
9900   ins_encode %{
9901     __ blsmskq($dst$$Register, $src$$Register);
9902   %}
9903 
9904   ins_pipe(ialu_reg);
9905 %}
9906 
9907 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9908 %{
9909   match(Set dst (AndL (AddL src minus_1) src) );
9910   predicate(UseBMI1Instructions);
9911   effect(KILL cr);
9912 
9913   format %{ "blsrq  $dst, $src" %}
9914 
9915   ins_encode %{
9916     __ blsrq($dst$$Register, $src$$Register);
9917   %}
9918 
9919   ins_pipe(ialu_reg);
9920 %}
9921 
9922 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9923 %{
9924   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9925   predicate(UseBMI1Instructions);
9926   effect(KILL cr);
9927 
9928   ins_cost(125);
9929   format %{ "blsrq  $dst, $src" %}
9930 
9931   ins_encode %{
9932     __ blsrq($dst$$Register, $src$$Address);
9933   %}
9934 
9935   ins_pipe(ialu_reg);
9936 %}
9937 
9938 // Or Instructions
9939 // Or Register with Register
9940 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9941 %{
9942   match(Set dst (OrL dst src));
9943   effect(KILL cr);
9944 
9945   format %{ "orq     $dst, $src\t# long" %}
9946   opcode(0x0B);
9947   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9948   ins_pipe(ialu_reg_reg);
9949 %}
9950 
9951 // Use any_RegP to match R15 (TLS register) without spilling.
9952 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9953   match(Set dst (OrL dst (CastP2X src)));
9954   effect(KILL cr);
9955 
9956   format %{ "orq     $dst, $src\t# long" %}
9957   opcode(0x0B);
9958   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9959   ins_pipe(ialu_reg_reg);
9960 %}
9961 
9962 
9963 // Or Register with Immediate
9964 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9965 %{
9966   match(Set dst (OrL dst src));
9967   effect(KILL cr);
9968 
9969   format %{ "orq     $dst, $src\t# long" %}
9970   opcode(0x81, 0x01); /* Opcode 81 /1 id */
9971   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9972   ins_pipe(ialu_reg);
9973 %}
9974 
9975 // Or Register with Memory
9976 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9977 %{
9978   match(Set dst (OrL dst (LoadL src)));
9979   effect(KILL cr);
9980 
9981   ins_cost(125);
9982   format %{ "orq     $dst, $src\t# long" %}
9983   opcode(0x0B);
9984   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9985   ins_pipe(ialu_reg_mem);
9986 %}
9987 
9988 // Or Memory with Register
9989 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9990 %{
9991   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9992   effect(KILL cr);
9993 
9994   ins_cost(150);
9995   format %{ "orq     $dst, $src\t# long" %}
9996   opcode(0x09); /* Opcode 09 /r */
9997   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9998   ins_pipe(ialu_mem_reg);
9999 %}
10000 
10001 // Or Memory with Immediate
10002 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10003 %{
10004   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10005   effect(KILL cr);
10006 
10007   ins_cost(125);
10008   format %{ "orq     $dst, $src\t# long" %}
10009   opcode(0x81, 0x1); /* Opcode 81 /1 id */
10010   ins_encode(REX_mem_wide(dst), OpcSE(src),
10011              RM_opc_mem(secondary, dst), Con8or32(src));
10012   ins_pipe(ialu_mem_imm);
10013 %}
10014 
10015 // Xor Instructions
10016 // Xor Register with Register
10017 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10018 %{
10019   match(Set dst (XorL dst src));
10020   effect(KILL cr);
10021 
10022   format %{ "xorq    $dst, $src\t# long" %}
10023   opcode(0x33);
10024   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
10025   ins_pipe(ialu_reg_reg);
10026 %}
10027 
10028 // Xor Register with Immediate -1
10029 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10030   match(Set dst (XorL dst imm));
10031 
10032   format %{ "notq   $dst" %}
10033   ins_encode %{
10034      __ notq($dst$$Register);
10035   %}
10036   ins_pipe(ialu_reg);
10037 %}
10038 
10039 // Xor Register with Immediate
10040 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10041 %{
10042   match(Set dst (XorL dst src));
10043   effect(KILL cr);
10044 
10045   format %{ "xorq    $dst, $src\t# long" %}
10046   opcode(0x81, 0x06); /* Opcode 81 /6 id */
10047   ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
10048   ins_pipe(ialu_reg);
10049 %}
10050 
10051 // Xor Register with Memory
10052 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10053 %{
10054   match(Set dst (XorL dst (LoadL src)));
10055   effect(KILL cr);
10056 
10057   ins_cost(125);
10058   format %{ "xorq    $dst, $src\t# long" %}
10059   opcode(0x33);
10060   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10061   ins_pipe(ialu_reg_mem);
10062 %}
10063 
10064 // Xor Memory with Register
10065 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10066 %{
10067   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10068   effect(KILL cr);
10069 
10070   ins_cost(150);
10071   format %{ "xorq    $dst, $src\t# long" %}
10072   opcode(0x31); /* Opcode 31 /r */
10073   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10074   ins_pipe(ialu_mem_reg);
10075 %}
10076 
10077 // Xor Memory with Immediate
10078 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10079 %{
10080   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10081   effect(KILL cr);
10082 
10083   ins_cost(125);
10084   format %{ "xorq    $dst, $src\t# long" %}
10085   opcode(0x81, 0x6); /* Opcode 81 /6 id */
10086   ins_encode(REX_mem_wide(dst), OpcSE(src),
10087              RM_opc_mem(secondary, dst), Con8or32(src));
10088   ins_pipe(ialu_mem_imm);
10089 %}
10090 
10091 // Convert Int to Boolean
10092 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10093 %{
10094   match(Set dst (Conv2B src));
10095   effect(KILL cr);
10096 
10097   format %{ "testl   $src, $src\t# ci2b\n\t"
10098             "setnz   $dst\n\t"
10099             "movzbl  $dst, $dst" %}
10100   ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10101              setNZ_reg(dst),
10102              REX_reg_breg(dst, dst), // movzbl
10103              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10104   ins_pipe(pipe_slow); // XXX
10105 %}
10106 
10107 // Convert Pointer to Boolean
10108 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10109 %{
10110   match(Set dst (Conv2B src));
10111   effect(KILL cr);
10112 
10113   format %{ "testq   $src, $src\t# cp2b\n\t"
10114             "setnz   $dst\n\t"
10115             "movzbl  $dst, $dst" %}
10116   ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10117              setNZ_reg(dst),
10118              REX_reg_breg(dst, dst), // movzbl
10119              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10120   ins_pipe(pipe_slow); // XXX
10121 %}
10122 
10123 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10124 %{
10125   match(Set dst (CmpLTMask p q));
10126   effect(KILL cr);
10127 
10128   ins_cost(400);
10129   format %{ "cmpl    $p, $q\t# cmpLTMask\n\t"
10130             "setlt   $dst\n\t"
10131             "movzbl  $dst, $dst\n\t"
10132             "negl    $dst" %}
10133   ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10134              setLT_reg(dst),
10135              REX_reg_breg(dst, dst), // movzbl
10136              Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10137              neg_reg(dst));
10138   ins_pipe(pipe_slow);
10139 %}
10140 
10141 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10142 %{
10143   match(Set dst (CmpLTMask dst zero));
10144   effect(KILL cr);
10145 
10146   ins_cost(100);
10147   format %{ "sarl    $dst, #31\t# cmpLTMask0" %}
10148   ins_encode %{
10149   __ sarl($dst$$Register, 31);
10150   %}
10151   ins_pipe(ialu_reg);
10152 %}
10153 
10154 /* Better to save a register than avoid a branch */
10155 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10156 %{
10157   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10158   effect(KILL cr);
10159   ins_cost(300);
10160   format %{ "subl   $p,$q\t# cadd_cmpLTMask\n\t"
10161             "jge    done\n\t"
10162             "addl   $p,$y\n"
10163             "done:  " %}
10164   ins_encode %{
10165     Register Rp = $p$$Register;
10166     Register Rq = $q$$Register;
10167     Register Ry = $y$$Register;
10168     Label done;
10169     __ subl(Rp, Rq);
10170     __ jccb(Assembler::greaterEqual, done);
10171     __ addl(Rp, Ry);
10172     __ bind(done);
10173   %}
10174   ins_pipe(pipe_cmplt);
10175 %}
10176 
10177 /* Better to save a register than avoid a branch */
10178 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10179 %{
10180   match(Set y (AndI (CmpLTMask p q) y));
10181   effect(KILL cr);
10182 
10183   ins_cost(300);
10184 
10185   format %{ "cmpl     $p, $q\t# and_cmpLTMask\n\t"
10186             "jlt      done\n\t"
10187             "xorl     $y, $y\n"
10188             "done:  " %}
10189   ins_encode %{
10190     Register Rp = $p$$Register;
10191     Register Rq = $q$$Register;
10192     Register Ry = $y$$Register;
10193     Label done;
10194     __ cmpl(Rp, Rq);
10195     __ jccb(Assembler::less, done);
10196     __ xorl(Ry, Ry);
10197     __ bind(done);
10198   %}
10199   ins_pipe(pipe_cmplt);
10200 %}
10201 
10202 
10203 //---------- FP Instructions------------------------------------------------
10204 
10205 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10206 %{
10207   match(Set cr (CmpF src1 src2));
10208 
10209   ins_cost(145);
10210   format %{ "ucomiss $src1, $src2\n\t"
10211             "jnp,s   exit\n\t"
10212             "pushfq\t# saw NaN, set CF\n\t"
10213             "andq    [rsp], #0xffffff2b\n\t"
10214             "popfq\n"
10215     "exit:" %}
10216   ins_encode %{
10217     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10218     emit_cmpfp_fixup(_masm);
10219   %}
10220   ins_pipe(pipe_slow);
10221 %}
10222 
10223 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10224   match(Set cr (CmpF src1 src2));
10225 
10226   ins_cost(100);
10227   format %{ "ucomiss $src1, $src2" %}
10228   ins_encode %{
10229     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10230   %}
10231   ins_pipe(pipe_slow);
10232 %}
10233 
10234 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10235 %{
10236   match(Set cr (CmpF src1 (LoadF src2)));
10237 
10238   ins_cost(145);
10239   format %{ "ucomiss $src1, $src2\n\t"
10240             "jnp,s   exit\n\t"
10241             "pushfq\t# saw NaN, set CF\n\t"
10242             "andq    [rsp], #0xffffff2b\n\t"
10243             "popfq\n"
10244     "exit:" %}
10245   ins_encode %{
10246     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10247     emit_cmpfp_fixup(_masm);
10248   %}
10249   ins_pipe(pipe_slow);
10250 %}
10251 
10252 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10253   match(Set cr (CmpF src1 (LoadF src2)));
10254 
10255   ins_cost(100);
10256   format %{ "ucomiss $src1, $src2" %}
10257   ins_encode %{
10258     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10259   %}
10260   ins_pipe(pipe_slow);
10261 %}
10262 
10263 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10264   match(Set cr (CmpF src con));
10265 
10266   ins_cost(145);
10267   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10268             "jnp,s   exit\n\t"
10269             "pushfq\t# saw NaN, set CF\n\t"
10270             "andq    [rsp], #0xffffff2b\n\t"
10271             "popfq\n"
10272     "exit:" %}
10273   ins_encode %{
10274     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10275     emit_cmpfp_fixup(_masm);
10276   %}
10277   ins_pipe(pipe_slow);
10278 %}
10279 
10280 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10281   match(Set cr (CmpF src con));
10282   ins_cost(100);
10283   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10284   ins_encode %{
10285     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10286   %}
10287   ins_pipe(pipe_slow);
10288 %}
10289 
10290 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10291 %{
10292   match(Set cr (CmpD src1 src2));
10293 
10294   ins_cost(145);
10295   format %{ "ucomisd $src1, $src2\n\t"
10296             "jnp,s   exit\n\t"
10297             "pushfq\t# saw NaN, set CF\n\t"
10298             "andq    [rsp], #0xffffff2b\n\t"
10299             "popfq\n"
10300     "exit:" %}
10301   ins_encode %{
10302     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10303     emit_cmpfp_fixup(_masm);
10304   %}
10305   ins_pipe(pipe_slow);
10306 %}
10307 
10308 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10309   match(Set cr (CmpD src1 src2));
10310 
10311   ins_cost(100);
10312   format %{ "ucomisd $src1, $src2 test" %}
10313   ins_encode %{
10314     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10315   %}
10316   ins_pipe(pipe_slow);
10317 %}
10318 
10319 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10320 %{
10321   match(Set cr (CmpD src1 (LoadD src2)));
10322 
10323   ins_cost(145);
10324   format %{ "ucomisd $src1, $src2\n\t"
10325             "jnp,s   exit\n\t"
10326             "pushfq\t# saw NaN, set CF\n\t"
10327             "andq    [rsp], #0xffffff2b\n\t"
10328             "popfq\n"
10329     "exit:" %}
10330   ins_encode %{
10331     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10332     emit_cmpfp_fixup(_masm);
10333   %}
10334   ins_pipe(pipe_slow);
10335 %}
10336 
10337 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10338   match(Set cr (CmpD src1 (LoadD src2)));
10339 
10340   ins_cost(100);
10341   format %{ "ucomisd $src1, $src2" %}
10342   ins_encode %{
10343     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10344   %}
10345   ins_pipe(pipe_slow);
10346 %}
10347 
10348 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10349   match(Set cr (CmpD src con));
10350 
10351   ins_cost(145);
10352   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10353             "jnp,s   exit\n\t"
10354             "pushfq\t# saw NaN, set CF\n\t"
10355             "andq    [rsp], #0xffffff2b\n\t"
10356             "popfq\n"
10357     "exit:" %}
10358   ins_encode %{
10359     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10360     emit_cmpfp_fixup(_masm);
10361   %}
10362   ins_pipe(pipe_slow);
10363 %}
10364 
10365 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10366   match(Set cr (CmpD src con));
10367   ins_cost(100);
10368   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10369   ins_encode %{
10370     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10371   %}
10372   ins_pipe(pipe_slow);
10373 %}
10374 
10375 // Compare into -1,0,1
10376 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10377 %{
10378   match(Set dst (CmpF3 src1 src2));
10379   effect(KILL cr);
10380 
10381   ins_cost(275);
10382   format %{ "ucomiss $src1, $src2\n\t"
10383             "movl    $dst, #-1\n\t"
10384             "jp,s    done\n\t"
10385             "jb,s    done\n\t"
10386             "setne   $dst\n\t"
10387             "movzbl  $dst, $dst\n"
10388     "done:" %}
10389   ins_encode %{
10390     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10391     emit_cmpfp3(_masm, $dst$$Register);
10392   %}
10393   ins_pipe(pipe_slow);
10394 %}
10395 
10396 // Compare into -1,0,1
10397 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10398 %{
10399   match(Set dst (CmpF3 src1 (LoadF src2)));
10400   effect(KILL cr);
10401 
10402   ins_cost(275);
10403   format %{ "ucomiss $src1, $src2\n\t"
10404             "movl    $dst, #-1\n\t"
10405             "jp,s    done\n\t"
10406             "jb,s    done\n\t"
10407             "setne   $dst\n\t"
10408             "movzbl  $dst, $dst\n"
10409     "done:" %}
10410   ins_encode %{
10411     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10412     emit_cmpfp3(_masm, $dst$$Register);
10413   %}
10414   ins_pipe(pipe_slow);
10415 %}
10416 
10417 // Compare into -1,0,1
10418 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10419   match(Set dst (CmpF3 src con));
10420   effect(KILL cr);
10421 
10422   ins_cost(275);
10423   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10424             "movl    $dst, #-1\n\t"
10425             "jp,s    done\n\t"
10426             "jb,s    done\n\t"
10427             "setne   $dst\n\t"
10428             "movzbl  $dst, $dst\n"
10429     "done:" %}
10430   ins_encode %{
10431     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10432     emit_cmpfp3(_masm, $dst$$Register);
10433   %}
10434   ins_pipe(pipe_slow);
10435 %}
10436 
10437 // Compare into -1,0,1
10438 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10439 %{
10440   match(Set dst (CmpD3 src1 src2));
10441   effect(KILL cr);
10442 
10443   ins_cost(275);
10444   format %{ "ucomisd $src1, $src2\n\t"
10445             "movl    $dst, #-1\n\t"
10446             "jp,s    done\n\t"
10447             "jb,s    done\n\t"
10448             "setne   $dst\n\t"
10449             "movzbl  $dst, $dst\n"
10450     "done:" %}
10451   ins_encode %{
10452     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10453     emit_cmpfp3(_masm, $dst$$Register);
10454   %}
10455   ins_pipe(pipe_slow);
10456 %}
10457 
10458 // Compare into -1,0,1
10459 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10460 %{
10461   match(Set dst (CmpD3 src1 (LoadD src2)));
10462   effect(KILL cr);
10463 
10464   ins_cost(275);
10465   format %{ "ucomisd $src1, $src2\n\t"
10466             "movl    $dst, #-1\n\t"
10467             "jp,s    done\n\t"
10468             "jb,s    done\n\t"
10469             "setne   $dst\n\t"
10470             "movzbl  $dst, $dst\n"
10471     "done:" %}
10472   ins_encode %{
10473     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10474     emit_cmpfp3(_masm, $dst$$Register);
10475   %}
10476   ins_pipe(pipe_slow);
10477 %}
10478 
10479 // Compare into -1,0,1
10480 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10481   match(Set dst (CmpD3 src con));
10482   effect(KILL cr);
10483 
10484   ins_cost(275);
10485   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10486             "movl    $dst, #-1\n\t"
10487             "jp,s    done\n\t"
10488             "jb,s    done\n\t"
10489             "setne   $dst\n\t"
10490             "movzbl  $dst, $dst\n"
10491     "done:" %}
10492   ins_encode %{
10493     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10494     emit_cmpfp3(_masm, $dst$$Register);
10495   %}
10496   ins_pipe(pipe_slow);
10497 %}
10498 
10499 //----------Arithmetic Conversion Instructions---------------------------------
10500 
10501 instruct roundFloat_nop(regF dst)
10502 %{
10503   match(Set dst (RoundFloat dst));
10504 
10505   ins_cost(0);
10506   ins_encode();
10507   ins_pipe(empty);
10508 %}
10509 
10510 instruct roundDouble_nop(regD dst)
10511 %{
10512   match(Set dst (RoundDouble dst));
10513 
10514   ins_cost(0);
10515   ins_encode();
10516   ins_pipe(empty);
10517 %}
10518 
10519 instruct convF2D_reg_reg(regD dst, regF src)
10520 %{
10521   match(Set dst (ConvF2D src));
10522 
10523   format %{ "cvtss2sd $dst, $src" %}
10524   ins_encode %{
10525     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10526   %}
10527   ins_pipe(pipe_slow); // XXX
10528 %}
10529 
10530 instruct convF2D_reg_mem(regD dst, memory src)
10531 %{
10532   match(Set dst (ConvF2D (LoadF src)));
10533 
10534   format %{ "cvtss2sd $dst, $src" %}
10535   ins_encode %{
10536     __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10537   %}
10538   ins_pipe(pipe_slow); // XXX
10539 %}
10540 
10541 instruct convD2F_reg_reg(regF dst, regD src)
10542 %{
10543   match(Set dst (ConvD2F src));
10544 
10545   format %{ "cvtsd2ss $dst, $src" %}
10546   ins_encode %{
10547     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10548   %}
10549   ins_pipe(pipe_slow); // XXX
10550 %}
10551 
10552 instruct convD2F_reg_mem(regF dst, memory src)
10553 %{
10554   match(Set dst (ConvD2F (LoadD src)));
10555 
10556   format %{ "cvtsd2ss $dst, $src" %}
10557   ins_encode %{
10558     __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10559   %}
10560   ins_pipe(pipe_slow); // XXX
10561 %}
10562 
10563 // XXX do mem variants
10564 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10565 %{
10566   match(Set dst (ConvF2I src));
10567   effect(KILL cr);
10568 
10569   format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10570             "cmpl    $dst, #0x80000000\n\t"
10571             "jne,s   done\n\t"
10572             "subq    rsp, #8\n\t"
10573             "movss   [rsp], $src\n\t"
10574             "call    f2i_fixup\n\t"
10575             "popq    $dst\n"
10576     "done:   "%}
10577   ins_encode %{
10578     Label done;
10579     __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10580     __ cmpl($dst$$Register, 0x80000000);
10581     __ jccb(Assembler::notEqual, done);
10582     __ subptr(rsp, 8);
10583     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10584     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10585     __ pop($dst$$Register);
10586     __ bind(done);
10587   %}
10588   ins_pipe(pipe_slow);
10589 %}
10590 
10591 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10592 %{
10593   match(Set dst (ConvF2L src));
10594   effect(KILL cr);
10595 
10596   format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10597             "cmpq    $dst, [0x8000000000000000]\n\t"
10598             "jne,s   done\n\t"
10599             "subq    rsp, #8\n\t"
10600             "movss   [rsp], $src\n\t"
10601             "call    f2l_fixup\n\t"
10602             "popq    $dst\n"
10603     "done:   "%}
10604   ins_encode %{
10605     Label done;
10606     __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10607     __ cmp64($dst$$Register,
10608              ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10609     __ jccb(Assembler::notEqual, done);
10610     __ subptr(rsp, 8);
10611     __ movflt(Address(rsp, 0), $src$$XMMRegister);
10612     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10613     __ pop($dst$$Register);
10614     __ bind(done);
10615   %}
10616   ins_pipe(pipe_slow);
10617 %}
10618 
10619 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10620 %{
10621   match(Set dst (ConvD2I src));
10622   effect(KILL cr);
10623 
10624   format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10625             "cmpl    $dst, #0x80000000\n\t"
10626             "jne,s   done\n\t"
10627             "subq    rsp, #8\n\t"
10628             "movsd   [rsp], $src\n\t"
10629             "call    d2i_fixup\n\t"
10630             "popq    $dst\n"
10631     "done:   "%}
10632   ins_encode %{
10633     Label done;
10634     __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10635     __ cmpl($dst$$Register, 0x80000000);
10636     __ jccb(Assembler::notEqual, done);
10637     __ subptr(rsp, 8);
10638     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10639     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10640     __ pop($dst$$Register);
10641     __ bind(done);
10642   %}
10643   ins_pipe(pipe_slow);
10644 %}
10645 
10646 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10647 %{
10648   match(Set dst (ConvD2L src));
10649   effect(KILL cr);
10650 
10651   format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10652             "cmpq    $dst, [0x8000000000000000]\n\t"
10653             "jne,s   done\n\t"
10654             "subq    rsp, #8\n\t"
10655             "movsd   [rsp], $src\n\t"
10656             "call    d2l_fixup\n\t"
10657             "popq    $dst\n"
10658     "done:   "%}
10659   ins_encode %{
10660     Label done;
10661     __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10662     __ cmp64($dst$$Register,
10663              ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10664     __ jccb(Assembler::notEqual, done);
10665     __ subptr(rsp, 8);
10666     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10667     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10668     __ pop($dst$$Register);
10669     __ bind(done);
10670   %}
10671   ins_pipe(pipe_slow);
10672 %}
10673 
10674 instruct convI2F_reg_reg(regF dst, rRegI src)
10675 %{
10676   predicate(!UseXmmI2F);
10677   match(Set dst (ConvI2F src));
10678 
10679   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10680   ins_encode %{
10681     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10682   %}
10683   ins_pipe(pipe_slow); // XXX
10684 %}
10685 
10686 instruct convI2F_reg_mem(regF dst, memory src)
10687 %{
10688   match(Set dst (ConvI2F (LoadI src)));
10689 
10690   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10691   ins_encode %{
10692     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10693   %}
10694   ins_pipe(pipe_slow); // XXX
10695 %}
10696 
10697 instruct convI2D_reg_reg(regD dst, rRegI src)
10698 %{
10699   predicate(!UseXmmI2D);
10700   match(Set dst (ConvI2D src));
10701 
10702   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10703   ins_encode %{
10704     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10705   %}
10706   ins_pipe(pipe_slow); // XXX
10707 %}
10708 
10709 instruct convI2D_reg_mem(regD dst, memory src)
10710 %{
10711   match(Set dst (ConvI2D (LoadI src)));
10712 
10713   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10714   ins_encode %{
10715     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10716   %}
10717   ins_pipe(pipe_slow); // XXX
10718 %}
10719 
10720 instruct convXI2F_reg(regF dst, rRegI src)
10721 %{
10722   predicate(UseXmmI2F);
10723   match(Set dst (ConvI2F src));
10724 
10725   format %{ "movdl $dst, $src\n\t"
10726             "cvtdq2psl $dst, $dst\t# i2f" %}
10727   ins_encode %{
10728     __ movdl($dst$$XMMRegister, $src$$Register);
10729     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10730   %}
10731   ins_pipe(pipe_slow); // XXX
10732 %}
10733 
10734 instruct convXI2D_reg(regD dst, rRegI src)
10735 %{
10736   predicate(UseXmmI2D);
10737   match(Set dst (ConvI2D src));
10738 
10739   format %{ "movdl $dst, $src\n\t"
10740             "cvtdq2pdl $dst, $dst\t# i2d" %}
10741   ins_encode %{
10742     __ movdl($dst$$XMMRegister, $src$$Register);
10743     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10744   %}
10745   ins_pipe(pipe_slow); // XXX
10746 %}
10747 
10748 instruct convL2F_reg_reg(regF dst, rRegL src)
10749 %{
10750   match(Set dst (ConvL2F src));
10751 
10752   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10753   ins_encode %{
10754     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10755   %}
10756   ins_pipe(pipe_slow); // XXX
10757 %}
10758 
10759 instruct convL2F_reg_mem(regF dst, memory src)
10760 %{
10761   match(Set dst (ConvL2F (LoadL src)));
10762 
10763   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10764   ins_encode %{
10765     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10766   %}
10767   ins_pipe(pipe_slow); // XXX
10768 %}
10769 
10770 instruct convL2D_reg_reg(regD dst, rRegL src)
10771 %{
10772   match(Set dst (ConvL2D src));
10773 
10774   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10775   ins_encode %{
10776     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10777   %}
10778   ins_pipe(pipe_slow); // XXX
10779 %}
10780 
10781 instruct convL2D_reg_mem(regD dst, memory src)
10782 %{
10783   match(Set dst (ConvL2D (LoadL src)));
10784 
10785   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10786   ins_encode %{
10787     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10788   %}
10789   ins_pipe(pipe_slow); // XXX
10790 %}
10791 
10792 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10793 %{
10794   match(Set dst (ConvI2L src));
10795 
10796   ins_cost(125);
10797   format %{ "movslq  $dst, $src\t# i2l" %}
10798   ins_encode %{
10799     __ movslq($dst$$Register, $src$$Register);
10800   %}
10801   ins_pipe(ialu_reg_reg);
10802 %}
10803 
10804 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10805 // %{
10806 //   match(Set dst (ConvI2L src));
10807 // //   predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10808 // //             _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10809 //   predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10810 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10811 //             ((const TypeNode*) n)->type()->is_long()->_lo ==
10812 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10813 
10814 //   format %{ "movl    $dst, $src\t# unsigned i2l" %}
10815 //   ins_encode(enc_copy(dst, src));
10816 // //   opcode(0x63); // needs REX.W
10817 // //   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10818 //   ins_pipe(ialu_reg_reg);
10819 // %}
10820 
10821 // Zero-extend convert int to long
10822 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10823 %{
10824   match(Set dst (AndL (ConvI2L src) mask));
10825 
10826   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10827   ins_encode %{
10828     if ($dst$$reg != $src$$reg) {
10829       __ movl($dst$$Register, $src$$Register);
10830     }
10831   %}
10832   ins_pipe(ialu_reg_reg);
10833 %}
10834 
10835 // Zero-extend convert int to long
10836 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10837 %{
10838   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10839 
10840   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10841   ins_encode %{
10842     __ movl($dst$$Register, $src$$Address);
10843   %}
10844   ins_pipe(ialu_reg_mem);
10845 %}
10846 
10847 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10848 %{
10849   match(Set dst (AndL src mask));
10850 
10851   format %{ "movl    $dst, $src\t# zero-extend long" %}
10852   ins_encode %{
10853     __ movl($dst$$Register, $src$$Register);
10854   %}
10855   ins_pipe(ialu_reg_reg);
10856 %}
10857 
10858 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10859 %{
10860   match(Set dst (ConvL2I src));
10861 
10862   format %{ "movl    $dst, $src\t# l2i" %}
10863   ins_encode %{
10864     __ movl($dst$$Register, $src$$Register);
10865   %}
10866   ins_pipe(ialu_reg_reg);
10867 %}
10868 
10869 
10870 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10871   match(Set dst (MoveF2I src));
10872   effect(DEF dst, USE src);
10873 
10874   ins_cost(125);
10875   format %{ "movl    $dst, $src\t# MoveF2I_stack_reg" %}
10876   ins_encode %{
10877     __ movl($dst$$Register, Address(rsp, $src$$disp));
10878   %}
10879   ins_pipe(ialu_reg_mem);
10880 %}
10881 
10882 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10883   match(Set dst (MoveI2F src));
10884   effect(DEF dst, USE src);
10885 
10886   ins_cost(125);
10887   format %{ "movss   $dst, $src\t# MoveI2F_stack_reg" %}
10888   ins_encode %{
10889     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10890   %}
10891   ins_pipe(pipe_slow);
10892 %}
10893 
10894 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10895   match(Set dst (MoveD2L src));
10896   effect(DEF dst, USE src);
10897 
10898   ins_cost(125);
10899   format %{ "movq    $dst, $src\t# MoveD2L_stack_reg" %}
10900   ins_encode %{
10901     __ movq($dst$$Register, Address(rsp, $src$$disp));
10902   %}
10903   ins_pipe(ialu_reg_mem);
10904 %}
10905 
10906 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10907   predicate(!UseXmmLoadAndClearUpper);
10908   match(Set dst (MoveL2D src));
10909   effect(DEF dst, USE src);
10910 
10911   ins_cost(125);
10912   format %{ "movlpd  $dst, $src\t# MoveL2D_stack_reg" %}
10913   ins_encode %{
10914     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10915   %}
10916   ins_pipe(pipe_slow);
10917 %}
10918 
10919 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10920   predicate(UseXmmLoadAndClearUpper);
10921   match(Set dst (MoveL2D src));
10922   effect(DEF dst, USE src);
10923 
10924   ins_cost(125);
10925   format %{ "movsd   $dst, $src\t# MoveL2D_stack_reg" %}
10926   ins_encode %{
10927     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10928   %}
10929   ins_pipe(pipe_slow);
10930 %}
10931 
10932 
10933 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10934   match(Set dst (MoveF2I src));
10935   effect(DEF dst, USE src);
10936 
10937   ins_cost(95); // XXX
10938   format %{ "movss   $dst, $src\t# MoveF2I_reg_stack" %}
10939   ins_encode %{
10940     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10941   %}
10942   ins_pipe(pipe_slow);
10943 %}
10944 
10945 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10946   match(Set dst (MoveI2F src));
10947   effect(DEF dst, USE src);
10948 
10949   ins_cost(100);
10950   format %{ "movl    $dst, $src\t# MoveI2F_reg_stack" %}
10951   ins_encode %{
10952     __ movl(Address(rsp, $dst$$disp), $src$$Register);
10953   %}
10954   ins_pipe( ialu_mem_reg );
10955 %}
10956 
10957 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10958   match(Set dst (MoveD2L src));
10959   effect(DEF dst, USE src);
10960 
10961   ins_cost(95); // XXX
10962   format %{ "movsd   $dst, $src\t# MoveL2D_reg_stack" %}
10963   ins_encode %{
10964     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10965   %}
10966   ins_pipe(pipe_slow);
10967 %}
10968 
10969 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10970   match(Set dst (MoveL2D src));
10971   effect(DEF dst, USE src);
10972 
10973   ins_cost(100);
10974   format %{ "movq    $dst, $src\t# MoveL2D_reg_stack" %}
10975   ins_encode %{
10976     __ movq(Address(rsp, $dst$$disp), $src$$Register);
10977   %}
10978   ins_pipe(ialu_mem_reg);
10979 %}
10980 
10981 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10982   match(Set dst (MoveF2I src));
10983   effect(DEF dst, USE src);
10984   ins_cost(85);
10985   format %{ "movd    $dst,$src\t# MoveF2I" %}
10986   ins_encode %{
10987     __ movdl($dst$$Register, $src$$XMMRegister);
10988   %}
10989   ins_pipe( pipe_slow );
10990 %}
10991 
10992 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10993   match(Set dst (MoveD2L src));
10994   effect(DEF dst, USE src);
10995   ins_cost(85);
10996   format %{ "movd    $dst,$src\t# MoveD2L" %}
10997   ins_encode %{
10998     __ movdq($dst$$Register, $src$$XMMRegister);
10999   %}
11000   ins_pipe( pipe_slow );
11001 %}
11002 
11003 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11004   match(Set dst (MoveI2F src));
11005   effect(DEF dst, USE src);
11006   ins_cost(100);
11007   format %{ "movd    $dst,$src\t# MoveI2F" %}
11008   ins_encode %{
11009     __ movdl($dst$$XMMRegister, $src$$Register);
11010   %}
11011   ins_pipe( pipe_slow );
11012 %}
11013 
11014 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11015   match(Set dst (MoveL2D src));
11016   effect(DEF dst, USE src);
11017   ins_cost(100);
11018   format %{ "movd    $dst,$src\t# MoveL2D" %}
11019   ins_encode %{
11020      __ movdq($dst$$XMMRegister, $src$$Register);
11021   %}
11022   ins_pipe( pipe_slow );
11023 %}
11024 
11025 
11026 // =======================================================================
11027 // fast clearing of an array
11028 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11029                   Universe dummy, rFlagsReg cr)
11030 %{
11031   predicate(!((ClearArrayNode*)n)->is_large());
11032   match(Set dummy (ClearArray cnt base));
11033   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11034 
11035   format %{ $$template
11036     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11037     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
11038     $$emit$$"jg      LARGE\n\t"
11039     $$emit$$"dec     rcx\n\t"
11040     $$emit$$"js      DONE\t# Zero length\n\t"
11041     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
11042     $$emit$$"dec     rcx\n\t"
11043     $$emit$$"jge     LOOP\n\t"
11044     $$emit$$"jmp     DONE\n\t"
11045     $$emit$$"# LARGE:\n\t"
11046     if (UseFastStosb) {
11047        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11048        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
11049     } else if (UseXMMForObjInit) {
11050        $$emit$$"mov     rdi,rax\n\t"
11051        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11052        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11053        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11054        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11055        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11056        $$emit$$"add     0x40,rax\n\t"
11057        $$emit$$"# L_zero_64_bytes:\n\t"
11058        $$emit$$"sub     0x8,rcx\n\t"
11059        $$emit$$"jge     L_loop\n\t"
11060        $$emit$$"add     0x4,rcx\n\t"
11061        $$emit$$"jl      L_tail\n\t"
11062        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11063        $$emit$$"add     0x20,rax\n\t"
11064        $$emit$$"sub     0x4,rcx\n\t"
11065        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11066        $$emit$$"add     0x4,rcx\n\t"
11067        $$emit$$"jle     L_end\n\t"
11068        $$emit$$"dec     rcx\n\t"
11069        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11070        $$emit$$"vmovq   xmm0,(rax)\n\t"
11071        $$emit$$"add     0x8,rax\n\t"
11072        $$emit$$"dec     rcx\n\t"
11073        $$emit$$"jge     L_sloop\n\t"
11074        $$emit$$"# L_end:\n\t"
11075     } else {
11076        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
11077     }
11078     $$emit$$"# DONE"
11079   %}
11080   ins_encode %{
11081     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11082                  $tmp$$XMMRegister, false);
11083   %}
11084   ins_pipe(pipe_slow);
11085 %}
11086 
11087 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero, 
11088                         Universe dummy, rFlagsReg cr)
11089 %{
11090   predicate(((ClearArrayNode*)n)->is_large());
11091   match(Set dummy (ClearArray cnt base));
11092   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11093 
11094   format %{ $$template
11095     if (UseFastStosb) {
11096        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11097        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11098        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
11099     } else if (UseXMMForObjInit) {
11100        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
11101        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11102        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11103        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11104        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11105        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11106        $$emit$$"add     0x40,rax\n\t"
11107        $$emit$$"# L_zero_64_bytes:\n\t"
11108        $$emit$$"sub     0x8,rcx\n\t"
11109        $$emit$$"jge     L_loop\n\t"
11110        $$emit$$"add     0x4,rcx\n\t"
11111        $$emit$$"jl      L_tail\n\t"
11112        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11113        $$emit$$"add     0x20,rax\n\t"
11114        $$emit$$"sub     0x4,rcx\n\t"
11115        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11116        $$emit$$"add     0x4,rcx\n\t"
11117        $$emit$$"jle     L_end\n\t"
11118        $$emit$$"dec     rcx\n\t"
11119        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11120        $$emit$$"vmovq   xmm0,(rax)\n\t"
11121        $$emit$$"add     0x8,rax\n\t"
11122        $$emit$$"dec     rcx\n\t"
11123        $$emit$$"jge     L_sloop\n\t"
11124        $$emit$$"# L_end:\n\t"
11125     } else {
11126        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11127        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
11128     }
11129   %}
11130   ins_encode %{
11131     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register, 
11132                  $tmp$$XMMRegister, true);
11133   %}
11134   ins_pipe(pipe_slow);
11135 %}
11136 
11137 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11138                          rax_RegI result, legVecS tmp1, rFlagsReg cr)
11139 %{
11140   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11141   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11142   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11143 
11144   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11145   ins_encode %{
11146     __ string_compare($str1$$Register, $str2$$Register,
11147                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11148                       $tmp1$$XMMRegister, StrIntrinsicNode::LL);
11149   %}
11150   ins_pipe( pipe_slow );
11151 %}
11152 
11153 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11154                          rax_RegI result, legVecS tmp1, rFlagsReg cr)
11155 %{
11156   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11157   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11158   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11159 
11160   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11161   ins_encode %{
11162     __ string_compare($str1$$Register, $str2$$Register,
11163                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11164                       $tmp1$$XMMRegister, StrIntrinsicNode::UU);
11165   %}
11166   ins_pipe( pipe_slow );
11167 %}
11168 
11169 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11170                           rax_RegI result, legVecS tmp1, rFlagsReg cr)
11171 %{
11172   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11173   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11174   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11175 
11176   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11177   ins_encode %{
11178     __ string_compare($str1$$Register, $str2$$Register,
11179                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11180                       $tmp1$$XMMRegister, StrIntrinsicNode::LU);
11181   %}
11182   ins_pipe( pipe_slow );
11183 %}
11184 
11185 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11186                           rax_RegI result, legVecS tmp1, rFlagsReg cr)
11187 %{
11188   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11189   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11190   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11191 
11192   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11193   ins_encode %{
11194     __ string_compare($str2$$Register, $str1$$Register,
11195                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11196                       $tmp1$$XMMRegister, StrIntrinsicNode::UL);
11197   %}
11198   ins_pipe( pipe_slow );
11199 %}
11200 
11201 // fast search of substring with known size.
11202 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11203                              rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11204 %{
11205   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11206   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11207   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11208 
11209   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11210   ins_encode %{
11211     int icnt2 = (int)$int_cnt2$$constant;
11212     if (icnt2 >= 16) {
11213       // IndexOf for constant substrings with size >= 16 elements
11214       // which don't need to be loaded through stack.
11215       __ string_indexofC8($str1$$Register, $str2$$Register,
11216                           $cnt1$$Register, $cnt2$$Register,
11217                           icnt2, $result$$Register,
11218                           $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11219     } else {
11220       // Small strings are loaded through stack if they cross page boundary.
11221       __ string_indexof($str1$$Register, $str2$$Register,
11222                         $cnt1$$Register, $cnt2$$Register,
11223                         icnt2, $result$$Register,
11224                         $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11225     }
11226   %}
11227   ins_pipe( pipe_slow );
11228 %}
11229 
11230 // fast search of substring with known size.
11231 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11232                              rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11233 %{
11234   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11235   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11236   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11237 
11238   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11239   ins_encode %{
11240     int icnt2 = (int)$int_cnt2$$constant;
11241     if (icnt2 >= 8) {
11242       // IndexOf for constant substrings with size >= 8 elements
11243       // which don't need to be loaded through stack.
11244       __ string_indexofC8($str1$$Register, $str2$$Register,
11245                           $cnt1$$Register, $cnt2$$Register,
11246                           icnt2, $result$$Register,
11247                           $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11248     } else {
11249       // Small strings are loaded through stack if they cross page boundary.
11250       __ string_indexof($str1$$Register, $str2$$Register,
11251                         $cnt1$$Register, $cnt2$$Register,
11252                         icnt2, $result$$Register,
11253                         $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11254     }
11255   %}
11256   ins_pipe( pipe_slow );
11257 %}
11258 
11259 // fast search of substring with known size.
11260 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11261                              rbx_RegI result, legVecS vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11262 %{
11263   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11264   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11265   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11266 
11267   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $vec, $cnt1, $cnt2, $tmp" %}
11268   ins_encode %{
11269     int icnt2 = (int)$int_cnt2$$constant;
11270     if (icnt2 >= 8) {
11271       // IndexOf for constant substrings with size >= 8 elements
11272       // which don't need to be loaded through stack.
11273       __ string_indexofC8($str1$$Register, $str2$$Register,
11274                           $cnt1$$Register, $cnt2$$Register,
11275                           icnt2, $result$$Register,
11276                           $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11277     } else {
11278       // Small strings are loaded through stack if they cross page boundary.
11279       __ string_indexof($str1$$Register, $str2$$Register,
11280                         $cnt1$$Register, $cnt2$$Register,
11281                         icnt2, $result$$Register,
11282                         $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11283     }
11284   %}
11285   ins_pipe( pipe_slow );
11286 %}
11287 
11288 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11289                          rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11290 %{
11291   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11292   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11293   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11294 
11295   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11296   ins_encode %{
11297     __ string_indexof($str1$$Register, $str2$$Register,
11298                       $cnt1$$Register, $cnt2$$Register,
11299                       (-1), $result$$Register,
11300                       $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11301   %}
11302   ins_pipe( pipe_slow );
11303 %}
11304 
11305 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11306                          rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11307 %{
11308   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11309   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11310   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11311 
11312   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11313   ins_encode %{
11314     __ string_indexof($str1$$Register, $str2$$Register,
11315                       $cnt1$$Register, $cnt2$$Register,
11316                       (-1), $result$$Register,
11317                       $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11318   %}
11319   ins_pipe( pipe_slow );
11320 %}
11321 
11322 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11323                          rbx_RegI result, legVecS vec, rcx_RegI tmp, rFlagsReg cr)
11324 %{
11325   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11326   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11327   effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11328 
11329   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11330   ins_encode %{
11331     __ string_indexof($str1$$Register, $str2$$Register,
11332                       $cnt1$$Register, $cnt2$$Register,
11333                       (-1), $result$$Register,
11334                       $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11335   %}
11336   ins_pipe( pipe_slow );
11337 %}
11338 
11339 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11340                               rbx_RegI result, legVecS vec1, legVecS vec2, legVecS vec3, rcx_RegI tmp, rFlagsReg cr)
11341 %{
11342   predicate(UseSSE42Intrinsics);
11343   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11344   effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11345   format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11346   ins_encode %{
11347     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11348                            $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
11349   %}
11350   ins_pipe( pipe_slow );
11351 %}
11352 
11353 // fast string equals
11354 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11355                        legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11356 %{
11357   match(Set result (StrEquals (Binary str1 str2) cnt));
11358   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11359 
11360   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11361   ins_encode %{
11362     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11363                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11364                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11365   %}
11366   ins_pipe( pipe_slow );
11367 %}
11368 
11369 // fast array equals
11370 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11371                        legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11372 %{
11373   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11374   match(Set result (AryEq ary1 ary2));
11375   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11376 
11377   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11378   ins_encode %{
11379     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11380                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11381                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
11382   %}
11383   ins_pipe( pipe_slow );
11384 %}
11385 
11386 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11387                       legVecS tmp1, legVecS tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11388 %{
11389   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11390   match(Set result (AryEq ary1 ary2));
11391   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11392 
11393   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11394   ins_encode %{
11395     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11396                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11397                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
11398   %}
11399   ins_pipe( pipe_slow );
11400 %}
11401 
11402 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11403                       legVecS tmp1, legVecS tmp2, rbx_RegI tmp3, rFlagsReg cr)
11404 %{
11405   match(Set result (HasNegatives ary1 len));
11406   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11407 
11408   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11409   ins_encode %{
11410     __ has_negatives($ary1$$Register, $len$$Register,
11411                      $result$$Register, $tmp3$$Register,
11412                      $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11413   %}
11414   ins_pipe( pipe_slow );
11415 %}
11416 
11417 // fast char[] to byte[] compression
11418 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11419                          rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11420   match(Set result (StrCompressedCopy src (Binary dst len)));
11421   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11422 
11423   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11424   ins_encode %{
11425     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11426                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11427                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11428   %}
11429   ins_pipe( pipe_slow );
11430 %}
11431 
11432 // fast byte[] to char[] inflation
11433 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11434                         legVecS tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11435   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11436   effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11437 
11438   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11439   ins_encode %{
11440     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11441                           $tmp1$$XMMRegister, $tmp2$$Register);
11442   %}
11443   ins_pipe( pipe_slow );
11444 %}
11445 
11446 // encode char[] to byte[] in ISO_8859_1
11447 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11448                           legVecS tmp1, legVecS tmp2, legVecS tmp3, legVecS tmp4,
11449                           rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11450   match(Set result (EncodeISOArray src (Binary dst len)));
11451   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11452 
11453   format %{ "Encode array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11454   ins_encode %{
11455     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11456                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11457                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11458   %}
11459   ins_pipe( pipe_slow );
11460 %}
11461 
11462 //----------Overflow Math Instructions-----------------------------------------
11463 
11464 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11465 %{
11466   match(Set cr (OverflowAddI op1 op2));
11467   effect(DEF cr, USE_KILL op1, USE op2);
11468 
11469   format %{ "addl    $op1, $op2\t# overflow check int" %}
11470 
11471   ins_encode %{
11472     __ addl($op1$$Register, $op2$$Register);
11473   %}
11474   ins_pipe(ialu_reg_reg);
11475 %}
11476 
11477 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11478 %{
11479   match(Set cr (OverflowAddI op1 op2));
11480   effect(DEF cr, USE_KILL op1, USE op2);
11481 
11482   format %{ "addl    $op1, $op2\t# overflow check int" %}
11483 
11484   ins_encode %{
11485     __ addl($op1$$Register, $op2$$constant);
11486   %}
11487   ins_pipe(ialu_reg_reg);
11488 %}
11489 
11490 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11491 %{
11492   match(Set cr (OverflowAddL op1 op2));
11493   effect(DEF cr, USE_KILL op1, USE op2);
11494 
11495   format %{ "addq    $op1, $op2\t# overflow check long" %}
11496   ins_encode %{
11497     __ addq($op1$$Register, $op2$$Register);
11498   %}
11499   ins_pipe(ialu_reg_reg);
11500 %}
11501 
11502 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11503 %{
11504   match(Set cr (OverflowAddL op1 op2));
11505   effect(DEF cr, USE_KILL op1, USE op2);
11506 
11507   format %{ "addq    $op1, $op2\t# overflow check long" %}
11508   ins_encode %{
11509     __ addq($op1$$Register, $op2$$constant);
11510   %}
11511   ins_pipe(ialu_reg_reg);
11512 %}
11513 
11514 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11515 %{
11516   match(Set cr (OverflowSubI op1 op2));
11517 
11518   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11519   ins_encode %{
11520     __ cmpl($op1$$Register, $op2$$Register);
11521   %}
11522   ins_pipe(ialu_reg_reg);
11523 %}
11524 
11525 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11526 %{
11527   match(Set cr (OverflowSubI op1 op2));
11528 
11529   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11530   ins_encode %{
11531     __ cmpl($op1$$Register, $op2$$constant);
11532   %}
11533   ins_pipe(ialu_reg_reg);
11534 %}
11535 
11536 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11537 %{
11538   match(Set cr (OverflowSubL op1 op2));
11539 
11540   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11541   ins_encode %{
11542     __ cmpq($op1$$Register, $op2$$Register);
11543   %}
11544   ins_pipe(ialu_reg_reg);
11545 %}
11546 
11547 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11548 %{
11549   match(Set cr (OverflowSubL op1 op2));
11550 
11551   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11552   ins_encode %{
11553     __ cmpq($op1$$Register, $op2$$constant);
11554   %}
11555   ins_pipe(ialu_reg_reg);
11556 %}
11557 
11558 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
11559 %{
11560   match(Set cr (OverflowSubI zero op2));
11561   effect(DEF cr, USE_KILL op2);
11562 
11563   format %{ "negl    $op2\t# overflow check int" %}
11564   ins_encode %{
11565     __ negl($op2$$Register);
11566   %}
11567   ins_pipe(ialu_reg_reg);
11568 %}
11569 
11570 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11571 %{
11572   match(Set cr (OverflowSubL zero op2));
11573   effect(DEF cr, USE_KILL op2);
11574 
11575   format %{ "negq    $op2\t# overflow check long" %}
11576   ins_encode %{
11577     __ negq($op2$$Register);
11578   %}
11579   ins_pipe(ialu_reg_reg);
11580 %}
11581 
11582 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11583 %{
11584   match(Set cr (OverflowMulI op1 op2));
11585   effect(DEF cr, USE_KILL op1, USE op2);
11586 
11587   format %{ "imull    $op1, $op2\t# overflow check int" %}
11588   ins_encode %{
11589     __ imull($op1$$Register, $op2$$Register);
11590   %}
11591   ins_pipe(ialu_reg_reg_alu0);
11592 %}
11593 
11594 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11595 %{
11596   match(Set cr (OverflowMulI op1 op2));
11597   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11598 
11599   format %{ "imull    $tmp, $op1, $op2\t# overflow check int" %}
11600   ins_encode %{
11601     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11602   %}
11603   ins_pipe(ialu_reg_reg_alu0);
11604 %}
11605 
11606 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11607 %{
11608   match(Set cr (OverflowMulL op1 op2));
11609   effect(DEF cr, USE_KILL op1, USE op2);
11610 
11611   format %{ "imulq    $op1, $op2\t# overflow check long" %}
11612   ins_encode %{
11613     __ imulq($op1$$Register, $op2$$Register);
11614   %}
11615   ins_pipe(ialu_reg_reg_alu0);
11616 %}
11617 
11618 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11619 %{
11620   match(Set cr (OverflowMulL op1 op2));
11621   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11622 
11623   format %{ "imulq    $tmp, $op1, $op2\t# overflow check long" %}
11624   ins_encode %{
11625     __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11626   %}
11627   ins_pipe(ialu_reg_reg_alu0);
11628 %}
11629 
11630 
11631 //----------Control Flow Instructions------------------------------------------
11632 // Signed compare Instructions
11633 
11634 // XXX more variants!!
11635 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11636 %{
11637   match(Set cr (CmpI op1 op2));
11638   effect(DEF cr, USE op1, USE op2);
11639 
11640   format %{ "cmpl    $op1, $op2" %}
11641   opcode(0x3B);  /* Opcode 3B /r */
11642   ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11643   ins_pipe(ialu_cr_reg_reg);
11644 %}
11645 
11646 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11647 %{
11648   match(Set cr (CmpI op1 op2));
11649 
11650   format %{ "cmpl    $op1, $op2" %}
11651   opcode(0x81, 0x07); /* Opcode 81 /7 */
11652   ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11653   ins_pipe(ialu_cr_reg_imm);
11654 %}
11655 
11656 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11657 %{
11658   match(Set cr (CmpI op1 (LoadI op2)));
11659 
11660   ins_cost(500); // XXX
11661   format %{ "cmpl    $op1, $op2" %}
11662   opcode(0x3B); /* Opcode 3B /r */
11663   ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11664   ins_pipe(ialu_cr_reg_mem);
11665 %}
11666 
11667 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11668 %{
11669   match(Set cr (CmpI src zero));
11670 
11671   format %{ "testl   $src, $src" %}
11672   opcode(0x85);
11673   ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11674   ins_pipe(ialu_cr_reg_imm);
11675 %}
11676 
11677 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11678 %{
11679   match(Set cr (CmpI (AndI src con) zero));
11680 
11681   format %{ "testl   $src, $con" %}
11682   opcode(0xF7, 0x00);
11683   ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11684   ins_pipe(ialu_cr_reg_imm);
11685 %}
11686 
11687 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11688 %{
11689   match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11690 
11691   format %{ "testl   $src, $mem" %}
11692   opcode(0x85);
11693   ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11694   ins_pipe(ialu_cr_reg_mem);
11695 %}
11696 
11697 // Unsigned compare Instructions; really, same as signed except they
11698 // produce an rFlagsRegU instead of rFlagsReg.
11699 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11700 %{
11701   match(Set cr (CmpU op1 op2));
11702 
11703   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11704   opcode(0x3B); /* Opcode 3B /r */
11705   ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11706   ins_pipe(ialu_cr_reg_reg);
11707 %}
11708 
11709 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11710 %{
11711   match(Set cr (CmpU op1 op2));
11712 
11713   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11714   opcode(0x81,0x07); /* Opcode 81 /7 */
11715   ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11716   ins_pipe(ialu_cr_reg_imm);
11717 %}
11718 
11719 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11720 %{
11721   match(Set cr (CmpU op1 (LoadI op2)));
11722 
11723   ins_cost(500); // XXX
11724   format %{ "cmpl    $op1, $op2\t# unsigned" %}
11725   opcode(0x3B); /* Opcode 3B /r */
11726   ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11727   ins_pipe(ialu_cr_reg_mem);
11728 %}
11729 
11730 // // // Cisc-spilled version of cmpU_rReg
11731 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11732 // //%{
11733 // //  match(Set cr (CmpU (LoadI op1) op2));
11734 // //
11735 // //  format %{ "CMPu   $op1,$op2" %}
11736 // //  ins_cost(500);
11737 // //  opcode(0x39);  /* Opcode 39 /r */
11738 // //  ins_encode( OpcP, reg_mem( op1, op2) );
11739 // //%}
11740 
11741 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11742 %{
11743   match(Set cr (CmpU src zero));
11744 
11745   format %{ "testl  $src, $src\t# unsigned" %}
11746   opcode(0x85);
11747   ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11748   ins_pipe(ialu_cr_reg_imm);
11749 %}
11750 
11751 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11752 %{
11753   match(Set cr (CmpP op1 op2));
11754 
11755   format %{ "cmpq    $op1, $op2\t# ptr" %}
11756   opcode(0x3B); /* Opcode 3B /r */
11757   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11758   ins_pipe(ialu_cr_reg_reg);
11759 %}
11760 
11761 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11762 %{
11763   match(Set cr (CmpP op1 (LoadP op2)));
11764 
11765   ins_cost(500); // XXX
11766   format %{ "cmpq    $op1, $op2\t# ptr" %}
11767   opcode(0x3B); /* Opcode 3B /r */
11768   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11769   ins_pipe(ialu_cr_reg_mem);
11770 %}
11771 
11772 // // // Cisc-spilled version of cmpP_rReg
11773 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11774 // //%{
11775 // //  match(Set cr (CmpP (LoadP op1) op2));
11776 // //
11777 // //  format %{ "CMPu   $op1,$op2" %}
11778 // //  ins_cost(500);
11779 // //  opcode(0x39);  /* Opcode 39 /r */
11780 // //  ins_encode( OpcP, reg_mem( op1, op2) );
11781 // //%}
11782 
11783 // XXX this is generalized by compP_rReg_mem???
11784 // Compare raw pointer (used in out-of-heap check).
11785 // Only works because non-oop pointers must be raw pointers
11786 // and raw pointers have no anti-dependencies.
11787 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11788 %{
11789   predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11790   match(Set cr (CmpP op1 (LoadP op2)));
11791 
11792   format %{ "cmpq    $op1, $op2\t# raw ptr" %}
11793   opcode(0x3B); /* Opcode 3B /r */
11794   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11795   ins_pipe(ialu_cr_reg_mem);
11796 %}
11797 
11798 // This will generate a signed flags result. This should be OK since
11799 // any compare to a zero should be eq/neq.
11800 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11801 %{
11802   match(Set cr (CmpP src zero));
11803 
11804   format %{ "testq   $src, $src\t# ptr" %}
11805   opcode(0x85);
11806   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11807   ins_pipe(ialu_cr_reg_imm);
11808 %}
11809 
11810 // This will generate a signed flags result. This should be OK since
11811 // any compare to a zero should be eq/neq.
11812 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11813 %{
11814   predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11815   match(Set cr (CmpP (LoadP op) zero));
11816 
11817   ins_cost(500); // XXX
11818   format %{ "testq   $op, 0xffffffffffffffff\t# ptr" %}
11819   opcode(0xF7); /* Opcode F7 /0 */
11820   ins_encode(REX_mem_wide(op),
11821              OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11822   ins_pipe(ialu_cr_reg_imm);
11823 %}
11824 
11825 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11826 %{
11827   predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11828   match(Set cr (CmpP (LoadP mem) zero));
11829 
11830   format %{ "cmpq    R12, $mem\t# ptr (R12_heapbase==0)" %}
11831   ins_encode %{
11832     __ cmpq(r12, $mem$$Address);
11833   %}
11834   ins_pipe(ialu_cr_reg_mem);
11835 %}
11836 
11837 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11838 %{
11839   match(Set cr (CmpN op1 op2));
11840 
11841   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
11842   ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11843   ins_pipe(ialu_cr_reg_reg);
11844 %}
11845 
11846 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11847 %{
11848   match(Set cr (CmpN src (LoadN mem)));
11849 
11850   format %{ "cmpl    $src, $mem\t# compressed ptr" %}
11851   ins_encode %{
11852     __ cmpl($src$$Register, $mem$$Address);
11853   %}
11854   ins_pipe(ialu_cr_reg_mem);
11855 %}
11856 
11857 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11858   match(Set cr (CmpN op1 op2));
11859 
11860   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
11861   ins_encode %{
11862     __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11863   %}
11864   ins_pipe(ialu_cr_reg_imm);
11865 %}
11866 
11867 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11868 %{
11869   match(Set cr (CmpN src (LoadN mem)));
11870 
11871   format %{ "cmpl    $mem, $src\t# compressed ptr" %}
11872   ins_encode %{
11873     __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11874   %}
11875   ins_pipe(ialu_cr_reg_mem);
11876 %}
11877 
11878 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11879   match(Set cr (CmpN op1 op2));
11880 
11881   format %{ "cmpl    $op1, $op2\t# compressed klass ptr" %}
11882   ins_encode %{
11883     __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11884   %}
11885   ins_pipe(ialu_cr_reg_imm);
11886 %}
11887 
11888 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11889 %{
11890   match(Set cr (CmpN src (LoadNKlass mem)));
11891 
11892   format %{ "cmpl    $mem, $src\t# compressed klass ptr" %}
11893   ins_encode %{
11894     __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11895   %}
11896   ins_pipe(ialu_cr_reg_mem);
11897 %}
11898 
11899 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11900   match(Set cr (CmpN src zero));
11901 
11902   format %{ "testl   $src, $src\t# compressed ptr" %}
11903   ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11904   ins_pipe(ialu_cr_reg_imm);
11905 %}
11906 
11907 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11908 %{
11909   predicate(Universe::narrow_oop_base() != NULL);
11910   match(Set cr (CmpN (LoadN mem) zero));
11911 
11912   ins_cost(500); // XXX
11913   format %{ "testl   $mem, 0xffffffff\t# compressed ptr" %}
11914   ins_encode %{
11915     __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11916   %}
11917   ins_pipe(ialu_cr_reg_mem);
11918 %}
11919 
11920 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11921 %{
11922   predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11923   match(Set cr (CmpN (LoadN mem) zero));
11924 
11925   format %{ "cmpl    R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11926   ins_encode %{
11927     __ cmpl(r12, $mem$$Address);
11928   %}
11929   ins_pipe(ialu_cr_reg_mem);
11930 %}
11931 
11932 // Yanked all unsigned pointer compare operations.
11933 // Pointer compares are done with CmpP which is already unsigned.
11934 
11935 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11936 %{
11937   match(Set cr (CmpL op1 op2));
11938 
11939   format %{ "cmpq    $op1, $op2" %}
11940   opcode(0x3B);  /* Opcode 3B /r */
11941   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11942   ins_pipe(ialu_cr_reg_reg);
11943 %}
11944 
11945 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11946 %{
11947   match(Set cr (CmpL op1 op2));
11948 
11949   format %{ "cmpq    $op1, $op2" %}
11950   opcode(0x81, 0x07); /* Opcode 81 /7 */
11951   ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11952   ins_pipe(ialu_cr_reg_imm);
11953 %}
11954 
11955 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11956 %{
11957   match(Set cr (CmpL op1 (LoadL op2)));
11958 
11959   format %{ "cmpq    $op1, $op2" %}
11960   opcode(0x3B); /* Opcode 3B /r */
11961   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11962   ins_pipe(ialu_cr_reg_mem);
11963 %}
11964 
11965 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11966 %{
11967   match(Set cr (CmpL src zero));
11968 
11969   format %{ "testq   $src, $src" %}
11970   opcode(0x85);
11971   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11972   ins_pipe(ialu_cr_reg_imm);
11973 %}
11974 
11975 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11976 %{
11977   match(Set cr (CmpL (AndL src con) zero));
11978 
11979   format %{ "testq   $src, $con\t# long" %}
11980   opcode(0xF7, 0x00);
11981   ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11982   ins_pipe(ialu_cr_reg_imm);
11983 %}
11984 
11985 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11986 %{
11987   match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11988 
11989   format %{ "testq   $src, $mem" %}
11990   opcode(0x85);
11991   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11992   ins_pipe(ialu_cr_reg_mem);
11993 %}
11994 
11995 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11996 %{
11997   match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11998 
11999   format %{ "testq   $src, $mem" %}
12000   opcode(0x85);
12001   ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
12002   ins_pipe(ialu_cr_reg_mem);
12003 %}
12004 
12005 // Manifest a CmpL result in an integer register.  Very painful.
12006 // This is the test to avoid.
12007 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12008 %{
12009   match(Set dst (CmpL3 src1 src2));
12010   effect(KILL flags);
12011 
12012   ins_cost(275); // XXX
12013   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
12014             "movl    $dst, -1\n\t"
12015             "jl,s    done\n\t"
12016             "setne   $dst\n\t"
12017             "movzbl  $dst, $dst\n\t"
12018     "done:" %}
12019   ins_encode(cmpl3_flag(src1, src2, dst));
12020   ins_pipe(pipe_slow);
12021 %}
12022 
12023 // Unsigned long compare Instructions; really, same as signed long except they
12024 // produce an rFlagsRegU instead of rFlagsReg.
12025 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12026 %{
12027   match(Set cr (CmpUL op1 op2));
12028 
12029   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12030   opcode(0x3B);  /* Opcode 3B /r */
12031   ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
12032   ins_pipe(ialu_cr_reg_reg);
12033 %}
12034 
12035 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12036 %{
12037   match(Set cr (CmpUL op1 op2));
12038 
12039   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12040   opcode(0x81, 0x07); /* Opcode 81 /7 */
12041   ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
12042   ins_pipe(ialu_cr_reg_imm);
12043 %}
12044 
12045 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12046 %{
12047   match(Set cr (CmpUL op1 (LoadL op2)));
12048 
12049   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12050   opcode(0x3B); /* Opcode 3B /r */
12051   ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
12052   ins_pipe(ialu_cr_reg_mem);
12053 %}
12054 
12055 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12056 %{
12057   match(Set cr (CmpUL src zero));
12058 
12059   format %{ "testq   $src, $src\t# unsigned" %}
12060   opcode(0x85);
12061   ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
12062   ins_pipe(ialu_cr_reg_imm);
12063 %}
12064 
12065 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12066 %{
12067   match(Set cr (CmpI (LoadB mem) imm));
12068 
12069   ins_cost(125);
12070   format %{ "cmpb    $mem, $imm" %}
12071   ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12072   ins_pipe(ialu_cr_reg_mem);
12073 %}
12074 
12075 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
12076 %{
12077   match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12078 
12079   ins_cost(125);
12080   format %{ "testb   $mem, $imm" %}
12081   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12082   ins_pipe(ialu_cr_reg_mem);
12083 %}
12084 
12085 //----------Max and Min--------------------------------------------------------
12086 // Min Instructions
12087 
12088 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12089 %{
12090   effect(USE_DEF dst, USE src, USE cr);
12091 
12092   format %{ "cmovlgt $dst, $src\t# min" %}
12093   opcode(0x0F, 0x4F);
12094   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12095   ins_pipe(pipe_cmov_reg);
12096 %}
12097 
12098 
12099 instruct minI_rReg(rRegI dst, rRegI src)
12100 %{
12101   match(Set dst (MinI dst src));
12102 
12103   ins_cost(200);
12104   expand %{
12105     rFlagsReg cr;
12106     compI_rReg(cr, dst, src);
12107     cmovI_reg_g(dst, src, cr);
12108   %}
12109 %}
12110 
12111 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12112 %{
12113   effect(USE_DEF dst, USE src, USE cr);
12114 
12115   format %{ "cmovllt $dst, $src\t# max" %}
12116   opcode(0x0F, 0x4C);
12117   ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
12118   ins_pipe(pipe_cmov_reg);
12119 %}
12120 
12121 
12122 instruct maxI_rReg(rRegI dst, rRegI src)
12123 %{
12124   match(Set dst (MaxI dst src));
12125 
12126   ins_cost(200);
12127   expand %{
12128     rFlagsReg cr;
12129     compI_rReg(cr, dst, src);
12130     cmovI_reg_l(dst, src, cr);
12131   %}
12132 %}
12133 
12134 // ============================================================================
12135 // Branch Instructions
12136 
12137 // Jump Direct - Label defines a relative address from JMP+1
12138 instruct jmpDir(label labl)
12139 %{
12140   match(Goto);
12141   effect(USE labl);
12142 
12143   ins_cost(300);
12144   format %{ "jmp     $labl" %}
12145   size(5);
12146   ins_encode %{
12147     Label* L = $labl$$label;
12148     __ jmp(*L, false); // Always long jump
12149   %}
12150   ins_pipe(pipe_jmp);
12151 %}
12152 
12153 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12154 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12155 %{
12156   match(If cop cr);
12157   effect(USE labl);
12158 
12159   ins_cost(300);
12160   format %{ "j$cop     $labl" %}
12161   size(6);
12162   ins_encode %{
12163     Label* L = $labl$$label;
12164     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12165   %}
12166   ins_pipe(pipe_jcc);
12167 %}
12168 
12169 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12170 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12171 %{
12172   predicate(!n->has_vector_mask_set());
12173   match(CountedLoopEnd cop cr);
12174   effect(USE labl);
12175 
12176   ins_cost(300);
12177   format %{ "j$cop     $labl\t# loop end" %}
12178   size(6);
12179   ins_encode %{
12180     Label* L = $labl$$label;
12181     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12182   %}
12183   ins_pipe(pipe_jcc);
12184 %}
12185 
12186 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12187 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12188   predicate(!n->has_vector_mask_set());
12189   match(CountedLoopEnd cop cmp);
12190   effect(USE labl);
12191 
12192   ins_cost(300);
12193   format %{ "j$cop,u   $labl\t# loop end" %}
12194   size(6);
12195   ins_encode %{
12196     Label* L = $labl$$label;
12197     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12198   %}
12199   ins_pipe(pipe_jcc);
12200 %}
12201 
12202 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12203   predicate(!n->has_vector_mask_set());
12204   match(CountedLoopEnd cop cmp);
12205   effect(USE labl);
12206 
12207   ins_cost(200);
12208   format %{ "j$cop,u   $labl\t# loop end" %}
12209   size(6);
12210   ins_encode %{
12211     Label* L = $labl$$label;
12212     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12213   %}
12214   ins_pipe(pipe_jcc);
12215 %}
12216 
12217 // mask version
12218 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12219 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, rFlagsReg cr, label labl)
12220 %{
12221   predicate(n->has_vector_mask_set());
12222   match(CountedLoopEnd cop cr);
12223   effect(USE labl);
12224 
12225   ins_cost(400);
12226   format %{ "j$cop     $labl\t# loop end\n\t"
12227             "restorevectmask \t# vector mask restore for loops" %}
12228   size(10);
12229   ins_encode %{
12230     Label* L = $labl$$label;
12231     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12232     __ restorevectmask();
12233   %}
12234   ins_pipe(pipe_jcc);
12235 %}
12236 
12237 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12238 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12239   predicate(n->has_vector_mask_set());
12240   match(CountedLoopEnd cop cmp);
12241   effect(USE labl);
12242 
12243   ins_cost(400);
12244   format %{ "j$cop,u   $labl\t# loop end\n\t"
12245             "restorevectmask \t# vector mask restore for loops" %}
12246   size(10);
12247   ins_encode %{
12248     Label* L = $labl$$label;
12249     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12250     __ restorevectmask();
12251   %}
12252   ins_pipe(pipe_jcc);
12253 %}
12254 
12255 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12256   predicate(n->has_vector_mask_set());
12257   match(CountedLoopEnd cop cmp);
12258   effect(USE labl);
12259 
12260   ins_cost(300);
12261   format %{ "j$cop,u   $labl\t# loop end\n\t"
12262             "restorevectmask \t# vector mask restore for loops" %}
12263   size(10);
12264   ins_encode %{
12265     Label* L = $labl$$label;
12266     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12267     __ restorevectmask();
12268   %}
12269   ins_pipe(pipe_jcc);
12270 %}
12271 
12272 // Jump Direct Conditional - using unsigned comparison
12273 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12274   match(If cop cmp);
12275   effect(USE labl);
12276 
12277   ins_cost(300);
12278   format %{ "j$cop,u  $labl" %}
12279   size(6);
12280   ins_encode %{
12281     Label* L = $labl$$label;
12282     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12283   %}
12284   ins_pipe(pipe_jcc);
12285 %}
12286 
12287 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12288   match(If cop cmp);
12289   effect(USE labl);
12290 
12291   ins_cost(200);
12292   format %{ "j$cop,u  $labl" %}
12293   size(6);
12294   ins_encode %{
12295     Label* L = $labl$$label;
12296     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12297   %}
12298   ins_pipe(pipe_jcc);
12299 %}
12300 
12301 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12302   match(If cop cmp);
12303   effect(USE labl);
12304 
12305   ins_cost(200);
12306   format %{ $$template
12307     if ($cop$$cmpcode == Assembler::notEqual) {
12308       $$emit$$"jp,u   $labl\n\t"
12309       $$emit$$"j$cop,u   $labl"
12310     } else {
12311       $$emit$$"jp,u   done\n\t"
12312       $$emit$$"j$cop,u   $labl\n\t"
12313       $$emit$$"done:"
12314     }
12315   %}
12316   ins_encode %{
12317     Label* l = $labl$$label;
12318     if ($cop$$cmpcode == Assembler::notEqual) {
12319       __ jcc(Assembler::parity, *l, false);
12320       __ jcc(Assembler::notEqual, *l, false);
12321     } else if ($cop$$cmpcode == Assembler::equal) {
12322       Label done;
12323       __ jccb(Assembler::parity, done);
12324       __ jcc(Assembler::equal, *l, false);
12325       __ bind(done);
12326     } else {
12327        ShouldNotReachHere();
12328     }
12329   %}
12330   ins_pipe(pipe_jcc);
12331 %}
12332 
12333 // ============================================================================
12334 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary
12335 // superklass array for an instance of the superklass.  Set a hidden
12336 // internal cache on a hit (cache is checked with exposed code in
12337 // gen_subtype_check()).  Return NZ for a miss or zero for a hit.  The
12338 // encoding ALSO sets flags.
12339 
12340 instruct partialSubtypeCheck(rdi_RegP result,
12341                              rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12342                              rFlagsReg cr)
12343 %{
12344   match(Set result (PartialSubtypeCheck sub super));
12345   effect(KILL rcx, KILL cr);
12346 
12347   ins_cost(1100);  // slightly larger than the next version
12348   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12349             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12350             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12351             "repne   scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12352             "jne,s   miss\t\t# Missed: rdi not-zero\n\t"
12353             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12354             "xorq    $result, $result\t\t Hit: rdi zero\n\t"
12355     "miss:\t" %}
12356 
12357   opcode(0x1); // Force a XOR of RDI
12358   ins_encode(enc_PartialSubtypeCheck());
12359   ins_pipe(pipe_slow);
12360 %}
12361 
12362 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12363                                      rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12364                                      immP0 zero,
12365                                      rdi_RegP result)
12366 %{
12367   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12368   effect(KILL rcx, KILL result);
12369 
12370   ins_cost(1000);
12371   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12372             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12373             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12374             "repne   scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12375             "jne,s   miss\t\t# Missed: flags nz\n\t"
12376             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12377     "miss:\t" %}
12378 
12379   opcode(0x0); // No need to XOR RDI
12380   ins_encode(enc_PartialSubtypeCheck());
12381   ins_pipe(pipe_slow);
12382 %}
12383 
12384 // ============================================================================
12385 // Branch Instructions -- short offset versions
12386 //
12387 // These instructions are used to replace jumps of a long offset (the default
12388 // match) with jumps of a shorter offset.  These instructions are all tagged
12389 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12390 // match rules in general matching.  Instead, the ADLC generates a conversion
12391 // method in the MachNode which can be used to do in-place replacement of the
12392 // long variant with the shorter variant.  The compiler will determine if a
12393 // branch can be taken by the is_short_branch_offset() predicate in the machine
12394 // specific code section of the file.
12395 
12396 // Jump Direct - Label defines a relative address from JMP+1
12397 instruct jmpDir_short(label labl) %{
12398   match(Goto);
12399   effect(USE labl);
12400 
12401   ins_cost(300);
12402   format %{ "jmp,s   $labl" %}
12403   size(2);
12404   ins_encode %{
12405     Label* L = $labl$$label;
12406     __ jmpb(*L);
12407   %}
12408   ins_pipe(pipe_jmp);
12409   ins_short_branch(1);
12410 %}
12411 
12412 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12413 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12414   match(If cop cr);
12415   effect(USE labl);
12416 
12417   ins_cost(300);
12418   format %{ "j$cop,s   $labl" %}
12419   size(2);
12420   ins_encode %{
12421     Label* L = $labl$$label;
12422     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12423   %}
12424   ins_pipe(pipe_jcc);
12425   ins_short_branch(1);
12426 %}
12427 
12428 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12429 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12430   match(CountedLoopEnd cop cr);
12431   effect(USE labl);
12432 
12433   ins_cost(300);
12434   format %{ "j$cop,s   $labl\t# loop end" %}
12435   size(2);
12436   ins_encode %{
12437     Label* L = $labl$$label;
12438     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12439   %}
12440   ins_pipe(pipe_jcc);
12441   ins_short_branch(1);
12442 %}
12443 
12444 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12445 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12446   match(CountedLoopEnd cop cmp);
12447   effect(USE labl);
12448 
12449   ins_cost(300);
12450   format %{ "j$cop,us  $labl\t# loop end" %}
12451   size(2);
12452   ins_encode %{
12453     Label* L = $labl$$label;
12454     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12455   %}
12456   ins_pipe(pipe_jcc);
12457   ins_short_branch(1);
12458 %}
12459 
12460 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12461   match(CountedLoopEnd cop cmp);
12462   effect(USE labl);
12463 
12464   ins_cost(300);
12465   format %{ "j$cop,us  $labl\t# loop end" %}
12466   size(2);
12467   ins_encode %{
12468     Label* L = $labl$$label;
12469     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12470   %}
12471   ins_pipe(pipe_jcc);
12472   ins_short_branch(1);
12473 %}
12474 
12475 // Jump Direct Conditional - using unsigned comparison
12476 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12477   match(If cop cmp);
12478   effect(USE labl);
12479 
12480   ins_cost(300);
12481   format %{ "j$cop,us  $labl" %}
12482   size(2);
12483   ins_encode %{
12484     Label* L = $labl$$label;
12485     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12486   %}
12487   ins_pipe(pipe_jcc);
12488   ins_short_branch(1);
12489 %}
12490 
12491 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12492   match(If cop cmp);
12493   effect(USE labl);
12494 
12495   ins_cost(300);
12496   format %{ "j$cop,us  $labl" %}
12497   size(2);
12498   ins_encode %{
12499     Label* L = $labl$$label;
12500     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12501   %}
12502   ins_pipe(pipe_jcc);
12503   ins_short_branch(1);
12504 %}
12505 
12506 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12507   match(If cop cmp);
12508   effect(USE labl);
12509 
12510   ins_cost(300);
12511   format %{ $$template
12512     if ($cop$$cmpcode == Assembler::notEqual) {
12513       $$emit$$"jp,u,s   $labl\n\t"
12514       $$emit$$"j$cop,u,s   $labl"
12515     } else {
12516       $$emit$$"jp,u,s   done\n\t"
12517       $$emit$$"j$cop,u,s  $labl\n\t"
12518       $$emit$$"done:"
12519     }
12520   %}
12521   size(4);
12522   ins_encode %{
12523     Label* l = $labl$$label;
12524     if ($cop$$cmpcode == Assembler::notEqual) {
12525       __ jccb(Assembler::parity, *l);
12526       __ jccb(Assembler::notEqual, *l);
12527     } else if ($cop$$cmpcode == Assembler::equal) {
12528       Label done;
12529       __ jccb(Assembler::parity, done);
12530       __ jccb(Assembler::equal, *l);
12531       __ bind(done);
12532     } else {
12533        ShouldNotReachHere();
12534     }
12535   %}
12536   ins_pipe(pipe_jcc);
12537   ins_short_branch(1);
12538 %}
12539 
12540 // ============================================================================
12541 // inlined locking and unlocking
12542 
12543 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12544   predicate(Compile::current()->use_rtm());
12545   match(Set cr (FastLock object box));
12546   effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12547   ins_cost(300);
12548   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12549   ins_encode %{
12550     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12551                  $scr$$Register, $cx1$$Register, $cx2$$Register,
12552                  _counters, _rtm_counters, _stack_rtm_counters,
12553                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12554                  true, ra_->C->profile_rtm());
12555   %}
12556   ins_pipe(pipe_slow);
12557 %}
12558 
12559 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12560   predicate(!Compile::current()->use_rtm());
12561   match(Set cr (FastLock object box));
12562   effect(TEMP tmp, TEMP scr, USE_KILL box);
12563   ins_cost(300);
12564   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12565   ins_encode %{
12566     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12567                  $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
12568   %}
12569   ins_pipe(pipe_slow);
12570 %}
12571 
12572 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12573   match(Set cr (FastUnlock object box));
12574   effect(TEMP tmp, USE_KILL box);
12575   ins_cost(300);
12576   format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12577   ins_encode %{
12578     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12579   %}
12580   ins_pipe(pipe_slow);
12581 %}
12582 
12583 
12584 // ============================================================================
12585 // Safepoint Instructions
12586 instruct safePoint_poll(rFlagsReg cr)
12587 %{
12588   predicate(!Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12589   match(SafePoint);
12590   effect(KILL cr);
12591 
12592   format %{ "testl  rax, [rip + #offset_to_poll_page]\t"
12593             "# Safepoint: poll for GC" %}
12594   ins_cost(125);
12595   ins_encode %{
12596     AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
12597     __ testl(rax, addr);
12598   %}
12599   ins_pipe(ialu_reg_mem);
12600 %}
12601 
12602 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
12603 %{
12604   predicate(Assembler::is_polling_page_far() && SafepointMechanism::uses_global_page_poll());
12605   match(SafePoint poll);
12606   effect(KILL cr, USE poll);
12607 
12608   format %{ "testl  rax, [$poll]\t"
12609             "# Safepoint: poll for GC" %}
12610   ins_cost(125);
12611   ins_encode %{
12612     __ relocate(relocInfo::poll_type);
12613     __ testl(rax, Address($poll$$Register, 0));
12614   %}
12615   ins_pipe(ialu_reg_mem);
12616 %}
12617 
12618 instruct safePoint_poll_tls(rFlagsReg cr, rex_RegP poll)
12619 %{
12620   predicate(SafepointMechanism::uses_thread_local_poll());
12621   match(SafePoint poll);
12622   effect(KILL cr, USE poll);
12623 
12624   format %{ "testl  rax, [$poll]\t"
12625             "# Safepoint: poll for GC" %}
12626   ins_cost(125);
12627   size(3); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12628   ins_encode %{
12629     __ relocate(relocInfo::poll_type);
12630     address pre_pc = __ pc();
12631     __ testl(rax, Address($poll$$Register, 0));
12632     address post_pc = __ pc();
12633     guarantee(pre_pc[0] == 0x41 && pre_pc[1] == 0x85, "must emit #rex test-ax [reg]");
12634   %}
12635   ins_pipe(ialu_reg_mem);
12636 %}
12637 
12638 // ============================================================================
12639 // Procedure Call/Return Instructions
12640 // Call Java Static Instruction
12641 // Note: If this code changes, the corresponding ret_addr_offset() and
12642 //       compute_padding() functions will have to be adjusted.
12643 instruct CallStaticJavaDirect(method meth) %{
12644   match(CallStaticJava);
12645   effect(USE meth);
12646 
12647   ins_cost(300);
12648   format %{ "call,static " %}
12649   opcode(0xE8); /* E8 cd */
12650   ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12651   ins_pipe(pipe_slow);
12652   ins_alignment(4);
12653 %}
12654 
12655 // Call Java Dynamic Instruction
12656 // Note: If this code changes, the corresponding ret_addr_offset() and
12657 //       compute_padding() functions will have to be adjusted.
12658 instruct CallDynamicJavaDirect(method meth)
12659 %{
12660   match(CallDynamicJava);
12661   effect(USE meth);
12662 
12663   ins_cost(300);
12664   format %{ "movq    rax, #Universe::non_oop_word()\n\t"
12665             "call,dynamic " %}
12666   ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12667   ins_pipe(pipe_slow);
12668   ins_alignment(4);
12669 %}
12670 
12671 // Call Runtime Instruction
12672 instruct CallRuntimeDirect(method meth)
12673 %{
12674   match(CallRuntime);
12675   effect(USE meth);
12676 
12677   ins_cost(300);
12678   format %{ "call,runtime " %}
12679   ins_encode(clear_avx, Java_To_Runtime(meth));
12680   ins_pipe(pipe_slow);
12681 %}
12682 
12683 // Call runtime without safepoint
12684 instruct CallLeafDirect(method meth)
12685 %{
12686   match(CallLeaf);
12687   effect(USE meth);
12688 
12689   ins_cost(300);
12690   format %{ "call_leaf,runtime " %}
12691   ins_encode(clear_avx, Java_To_Runtime(meth));
12692   ins_pipe(pipe_slow);
12693 %}
12694 
12695 // Call runtime without safepoint
12696 instruct CallLeafNoFPDirect(method meth)
12697 %{
12698   match(CallLeafNoFP);
12699   effect(USE meth);
12700 
12701   ins_cost(300);
12702   format %{ "call_leaf_nofp,runtime " %}
12703   ins_encode(clear_avx, Java_To_Runtime(meth));
12704   ins_pipe(pipe_slow);
12705 %}
12706 
12707 // Return Instruction
12708 // Remove the return address & jump to it.
12709 // Notice: We always emit a nop after a ret to make sure there is room
12710 // for safepoint patching
12711 instruct Ret()
12712 %{
12713   match(Return);
12714 
12715   format %{ "ret" %}
12716   opcode(0xC3);
12717   ins_encode(OpcP);
12718   ins_pipe(pipe_jmp);
12719 %}
12720 
12721 // Tail Call; Jump from runtime stub to Java code.
12722 // Also known as an 'interprocedural jump'.
12723 // Target of jump will eventually return to caller.
12724 // TailJump below removes the return address.
12725 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12726 %{
12727   match(TailCall jump_target method_oop);
12728 
12729   ins_cost(300);
12730   format %{ "jmp     $jump_target\t# rbx holds method oop" %}
12731   opcode(0xFF, 0x4); /* Opcode FF /4 */
12732   ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12733   ins_pipe(pipe_jmp);
12734 %}
12735 
12736 // Tail Jump; remove the return address; jump to target.
12737 // TailCall above leaves the return address around.
12738 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12739 %{
12740   match(TailJump jump_target ex_oop);
12741 
12742   ins_cost(300);
12743   format %{ "popq    rdx\t# pop return address\n\t"
12744             "jmp     $jump_target" %}
12745   opcode(0xFF, 0x4); /* Opcode FF /4 */
12746   ins_encode(Opcode(0x5a), // popq rdx
12747              REX_reg(jump_target), OpcP, reg_opc(jump_target));
12748   ins_pipe(pipe_jmp);
12749 %}
12750 
12751 // Create exception oop: created by stack-crawling runtime code.
12752 // Created exception is now available to this handler, and is setup
12753 // just prior to jumping to this handler.  No code emitted.
12754 instruct CreateException(rax_RegP ex_oop)
12755 %{
12756   match(Set ex_oop (CreateEx));
12757 
12758   size(0);
12759   // use the following format syntax
12760   format %{ "# exception oop is in rax; no code emitted" %}
12761   ins_encode();
12762   ins_pipe(empty);
12763 %}
12764 
12765 // Rethrow exception:
12766 // The exception oop will come in the first argument position.
12767 // Then JUMP (not call) to the rethrow stub code.
12768 instruct RethrowException()
12769 %{
12770   match(Rethrow);
12771 
12772   // use the following format syntax
12773   format %{ "jmp     rethrow_stub" %}
12774   ins_encode(enc_rethrow);
12775   ins_pipe(pipe_jmp);
12776 %}
12777 
12778 //
12779 // Execute ZGC load barrier (strong) slow path
12780 //
12781 
12782 // When running without XMM regs
12783 instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12784 
12785   match(Set dst (LoadBarrierSlowReg mem));
12786   predicate(MaxVectorSize < 16);
12787 
12788   effect(DEF dst, KILL cr);
12789 
12790   format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12791   ins_encode %{
12792 #if INCLUDE_ZGC
12793     Register d = $dst$$Register;
12794     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12795 
12796     assert(d != r12, "Can't be R12!");
12797     assert(d != r15, "Can't be R15!");
12798     assert(d != rsp, "Can't be RSP!");
12799 
12800     __ lea(d, $mem$$Address);
12801     __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12802 #else
12803     ShouldNotReachHere();
12804 #endif
12805   %}
12806   ins_pipe(pipe_slow);
12807 %}
12808 
12809 // For XMM and YMM enabled processors
12810 instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12811                                      rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12812                                      rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12813                                      rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12814                                      rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12815 
12816   match(Set dst (LoadBarrierSlowReg mem));
12817   predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12818 
12819   effect(DEF dst, KILL cr,
12820          KILL x0, KILL x1, KILL x2, KILL x3,
12821          KILL x4, KILL x5, KILL x6, KILL x7,
12822          KILL x8, KILL x9, KILL x10, KILL x11,
12823          KILL x12, KILL x13, KILL x14, KILL x15);
12824 
12825   format %{"LoadBarrierSlowRegXmm $dst, $mem" %}
12826   ins_encode %{
12827 #if INCLUDE_ZGC
12828     Register d = $dst$$Register;
12829     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12830 
12831     assert(d != r12, "Can't be R12!");
12832     assert(d != r15, "Can't be R15!");
12833     assert(d != rsp, "Can't be RSP!");
12834 
12835     __ lea(d, $mem$$Address);
12836     __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12837 #else
12838     ShouldNotReachHere();
12839 #endif
12840   %}
12841   ins_pipe(pipe_slow);
12842 %}
12843 
12844 // For ZMM enabled processors
12845 instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12846                                rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12847                                rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12848                                rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12849                                rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12850                                rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12851                                rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12852                                rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12853                                rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12854 
12855   match(Set dst (LoadBarrierSlowReg mem));
12856   predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12857 
12858   effect(DEF dst, KILL cr,
12859          KILL x0, KILL x1, KILL x2, KILL x3,
12860          KILL x4, KILL x5, KILL x6, KILL x7,
12861          KILL x8, KILL x9, KILL x10, KILL x11,
12862          KILL x12, KILL x13, KILL x14, KILL x15,
12863          KILL x16, KILL x17, KILL x18, KILL x19,
12864          KILL x20, KILL x21, KILL x22, KILL x23,
12865          KILL x24, KILL x25, KILL x26, KILL x27,
12866          KILL x28, KILL x29, KILL x30, KILL x31);
12867 
12868   format %{"LoadBarrierSlowRegZmm $dst, $mem" %}
12869   ins_encode %{
12870 #if INCLUDE_ZGC
12871     Register d = $dst$$Register;
12872     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12873 
12874     assert(d != r12, "Can't be R12!");
12875     assert(d != r15, "Can't be R15!");
12876     assert(d != rsp, "Can't be RSP!");
12877 
12878     __ lea(d, $mem$$Address);
12879     __ call(RuntimeAddress(bs->load_barrier_slow_stub(d)));
12880 #else
12881     ShouldNotReachHere();
12882 #endif
12883   %}
12884   ins_pipe(pipe_slow);
12885 %}
12886 
12887 //
12888 // Execute ZGC load barrier (weak) slow path
12889 //
12890 
12891 // When running without XMM regs
12892 instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{
12893 
12894   match(Set dst (LoadBarrierSlowReg mem));
12895   predicate(MaxVectorSize < 16);
12896 
12897   effect(DEF dst, KILL cr);
12898 
12899   format %{"LoadBarrierSlowRegNoVec $dst, $mem" %}
12900   ins_encode %{
12901 #if INCLUDE_ZGC
12902     Register d = $dst$$Register;
12903     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12904 
12905     assert(d != r12, "Can't be R12!");
12906     assert(d != r15, "Can't be R15!");
12907     assert(d != rsp, "Can't be RSP!");
12908 
12909     __ lea(d, $mem$$Address);
12910     __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12911 #else
12912     ShouldNotReachHere();
12913 #endif
12914   %}
12915   ins_pipe(pipe_slow);
12916 %}
12917 
12918 // For XMM and YMM enabled processors
12919 instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr,
12920                                          rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12921                                          rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12922                                          rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12923                                          rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{
12924 
12925   match(Set dst (LoadBarrierWeakSlowReg mem));
12926   predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16));
12927 
12928   effect(DEF dst, KILL cr,
12929          KILL x0, KILL x1, KILL x2, KILL x3,
12930          KILL x4, KILL x5, KILL x6, KILL x7,
12931          KILL x8, KILL x9, KILL x10, KILL x11,
12932          KILL x12, KILL x13, KILL x14, KILL x15);
12933 
12934   format %{"LoadBarrierWeakSlowRegXmm $dst, $mem" %}
12935   ins_encode %{
12936 #if INCLUDE_ZGC
12937     Register d = $dst$$Register;
12938     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12939 
12940     assert(d != r12, "Can't be R12!");
12941     assert(d != r15, "Can't be R15!");
12942     assert(d != rsp, "Can't be RSP!");
12943 
12944     __ lea(d,$mem$$Address);
12945     __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12946 #else
12947     ShouldNotReachHere();
12948 #endif
12949   %}
12950   ins_pipe(pipe_slow);
12951 %}
12952 
12953 // For ZMM enabled processors
12954 instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr,
12955                                    rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3,
12956                                    rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7,
12957                                    rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11,
12958                                    rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15,
12959                                    rxmm16 x16, rxmm17 x17, rxmm18 x18, rxmm19 x19,
12960                                    rxmm20 x20, rxmm21 x21, rxmm22 x22, rxmm23 x23,
12961                                    rxmm24 x24, rxmm25 x25, rxmm26 x26, rxmm27 x27,
12962                                    rxmm28 x28, rxmm29 x29, rxmm30 x30, rxmm31 x31) %{
12963 
12964   match(Set dst (LoadBarrierWeakSlowReg mem));
12965   predicate((UseAVX == 3) && (MaxVectorSize >= 16));
12966 
12967   effect(DEF dst, KILL cr,
12968          KILL x0, KILL x1, KILL x2, KILL x3,
12969          KILL x4, KILL x5, KILL x6, KILL x7,
12970          KILL x8, KILL x9, KILL x10, KILL x11,
12971          KILL x12, KILL x13, KILL x14, KILL x15,
12972          KILL x16, KILL x17, KILL x18, KILL x19,
12973          KILL x20, KILL x21, KILL x22, KILL x23,
12974          KILL x24, KILL x25, KILL x26, KILL x27,
12975          KILL x28, KILL x29, KILL x30, KILL x31);
12976 
12977   format %{"LoadBarrierWeakSlowRegZmm $dst, $mem" %}
12978   ins_encode %{
12979 #if INCLUDE_ZGC
12980     Register d = $dst$$Register;
12981     ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler();
12982 
12983     assert(d != r12, "Can't be R12!");
12984     assert(d != r15, "Can't be R15!");
12985     assert(d != rsp, "Can't be RSP!");
12986 
12987     __ lea(d,$mem$$Address);
12988     __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d)));
12989 #else
12990     ShouldNotReachHere();
12991 #endif
12992   %}
12993   ins_pipe(pipe_slow);
12994 %}
12995 
12996 // ============================================================================
12997 // This name is KNOWN by the ADLC and cannot be changed.
12998 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12999 // for this guy.
13000 instruct tlsLoadP(r15_RegP dst) %{
13001   match(Set dst (ThreadLocal));
13002   effect(DEF dst);
13003 
13004   size(0);
13005   format %{ "# TLS is in R15" %}
13006   ins_encode( /*empty encoding*/ );
13007   ins_pipe(ialu_reg_reg);
13008 %}
13009 
13010 
13011 //----------PEEPHOLE RULES-----------------------------------------------------
13012 // These must follow all instruction definitions as they use the names
13013 // defined in the instructions definitions.
13014 //
13015 // peepmatch ( root_instr_name [preceding_instruction]* );
13016 //
13017 // peepconstraint %{
13018 // (instruction_number.operand_name relational_op instruction_number.operand_name
13019 //  [, ...] );
13020 // // instruction numbers are zero-based using left to right order in peepmatch
13021 //
13022 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
13023 // // provide an instruction_number.operand_name for each operand that appears
13024 // // in the replacement instruction's match rule
13025 //
13026 // ---------VM FLAGS---------------------------------------------------------
13027 //
13028 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13029 //
13030 // Each peephole rule is given an identifying number starting with zero and
13031 // increasing by one in the order seen by the parser.  An individual peephole
13032 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13033 // on the command-line.
13034 //
13035 // ---------CURRENT LIMITATIONS----------------------------------------------
13036 //
13037 // Only match adjacent instructions in same basic block
13038 // Only equality constraints
13039 // Only constraints between operands, not (0.dest_reg == RAX_enc)
13040 // Only one replacement instruction
13041 //
13042 // ---------EXAMPLE----------------------------------------------------------
13043 //
13044 // // pertinent parts of existing instructions in architecture description
13045 // instruct movI(rRegI dst, rRegI src)
13046 // %{
13047 //   match(Set dst (CopyI src));
13048 // %}
13049 //
13050 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
13051 // %{
13052 //   match(Set dst (AddI dst src));
13053 //   effect(KILL cr);
13054 // %}
13055 //
13056 // // Change (inc mov) to lea
13057 // peephole %{
13058 //   // increment preceeded by register-register move
13059 //   peepmatch ( incI_rReg movI );
13060 //   // require that the destination register of the increment
13061 //   // match the destination register of the move
13062 //   peepconstraint ( 0.dst == 1.dst );
13063 //   // construct a replacement instruction that sets
13064 //   // the destination to ( move's source register + one )
13065 //   peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13066 // %}
13067 //
13068 
13069 // Implementation no longer uses movX instructions since
13070 // machine-independent system no longer uses CopyX nodes.
13071 //
13072 // peephole
13073 // %{
13074 //   peepmatch (incI_rReg movI);
13075 //   peepconstraint (0.dst == 1.dst);
13076 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13077 // %}
13078 
13079 // peephole
13080 // %{
13081 //   peepmatch (decI_rReg movI);
13082 //   peepconstraint (0.dst == 1.dst);
13083 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13084 // %}
13085 
13086 // peephole
13087 // %{
13088 //   peepmatch (addI_rReg_imm movI);
13089 //   peepconstraint (0.dst == 1.dst);
13090 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13091 // %}
13092 
13093 // peephole
13094 // %{
13095 //   peepmatch (incL_rReg movL);
13096 //   peepconstraint (0.dst == 1.dst);
13097 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13098 // %}
13099 
13100 // peephole
13101 // %{
13102 //   peepmatch (decL_rReg movL);
13103 //   peepconstraint (0.dst == 1.dst);
13104 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13105 // %}
13106 
13107 // peephole
13108 // %{
13109 //   peepmatch (addL_rReg_imm movL);
13110 //   peepconstraint (0.dst == 1.dst);
13111 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13112 // %}
13113 
13114 // peephole
13115 // %{
13116 //   peepmatch (addP_rReg_imm movP);
13117 //   peepconstraint (0.dst == 1.dst);
13118 //   peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13119 // %}
13120 
13121 // // Change load of spilled value to only a spill
13122 // instruct storeI(memory mem, rRegI src)
13123 // %{
13124 //   match(Set mem (StoreI mem src));
13125 // %}
13126 //
13127 // instruct loadI(rRegI dst, memory mem)
13128 // %{
13129 //   match(Set dst (LoadI mem));
13130 // %}
13131 //
13132 
13133 peephole
13134 %{
13135   peepmatch (loadI storeI);
13136   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13137   peepreplace (storeI(1.mem 1.mem 1.src));
13138 %}
13139 
13140 peephole
13141 %{
13142   peepmatch (loadL storeL);
13143   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13144   peepreplace (storeL(1.mem 1.mem 1.src));
13145 %}
13146 
13147 //----------SMARTSPILL RULES---------------------------------------------------
13148 // These must follow all instruction definitions as they use the names
13149 // defined in the instructions definitions.