1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "memory/allocation.inline.hpp"
  27 #include "memory/resourceArea.hpp"
  28 #include "opto/ad.hpp"
  29 #include "opto/addnode.hpp"
  30 #include "opto/callnode.hpp"
  31 #include "opto/idealGraphPrinter.hpp"
  32 #include "opto/matcher.hpp"
  33 #include "opto/memnode.hpp"
  34 #include "opto/movenode.hpp"
  35 #include "opto/opcodes.hpp"
  36 #include "opto/regmask.hpp"
  37 #include "opto/rootnode.hpp"
  38 #include "opto/runtime.hpp"
  39 #include "opto/type.hpp"
  40 #include "opto/vectornode.hpp"
  41 #include "runtime/os.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "utilities/align.hpp"
  44 #if INCLUDE_ZGC
  45 #include "gc/z/zBarrierSetRuntime.hpp"
  46 #endif // INCLUDE_ZGC
  47 #if INCLUDE_SHENANDOAHGC
  48 #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp"
  49 #endif
  50 
  51 OptoReg::Name OptoReg::c_frame_pointer;
  52 
  53 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
  54 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
  55 RegMask Matcher::STACK_ONLY_mask;
  56 RegMask Matcher::c_frame_ptr_mask;
  57 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
  58 const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
  59 
  60 //---------------------------Matcher-------------------------------------------
  61 Matcher::Matcher()
  62 : PhaseTransform( Phase::Ins_Select ),
  63 #ifdef ASSERT
  64   _old2new_map(C->comp_arena()),
  65   _new2old_map(C->comp_arena()),
  66 #endif
  67   _shared_nodes(C->comp_arena()),
  68   _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
  69   _swallowed(swallowed),
  70   _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
  71   _end_inst_chain_rule(_END_INST_CHAIN_RULE),
  72   _must_clone(must_clone),
  73   _register_save_policy(register_save_policy),
  74   _c_reg_save_policy(c_reg_save_policy),
  75   _register_save_type(register_save_type),
  76   _ruleName(ruleName),
  77   _allocation_started(false),
  78   _states_arena(Chunk::medium_size, mtCompiler),
  79   _visited(&_states_arena),
  80   _shared(&_states_arena),
  81   _dontcare(&_states_arena) {
  82   C->set_matcher(this);
  83 
  84   idealreg2spillmask  [Op_RegI] = NULL;
  85   idealreg2spillmask  [Op_RegN] = NULL;
  86   idealreg2spillmask  [Op_RegL] = NULL;
  87   idealreg2spillmask  [Op_RegF] = NULL;
  88   idealreg2spillmask  [Op_RegD] = NULL;
  89   idealreg2spillmask  [Op_RegP] = NULL;
  90   idealreg2spillmask  [Op_VecS] = NULL;
  91   idealreg2spillmask  [Op_VecD] = NULL;
  92   idealreg2spillmask  [Op_VecX] = NULL;
  93   idealreg2spillmask  [Op_VecY] = NULL;
  94   idealreg2spillmask  [Op_VecZ] = NULL;
  95   idealreg2spillmask  [Op_RegFlags] = NULL;
  96 
  97   idealreg2debugmask  [Op_RegI] = NULL;
  98   idealreg2debugmask  [Op_RegN] = NULL;
  99   idealreg2debugmask  [Op_RegL] = NULL;
 100   idealreg2debugmask  [Op_RegF] = NULL;
 101   idealreg2debugmask  [Op_RegD] = NULL;
 102   idealreg2debugmask  [Op_RegP] = NULL;
 103   idealreg2debugmask  [Op_VecS] = NULL;
 104   idealreg2debugmask  [Op_VecD] = NULL;
 105   idealreg2debugmask  [Op_VecX] = NULL;
 106   idealreg2debugmask  [Op_VecY] = NULL;
 107   idealreg2debugmask  [Op_VecZ] = NULL;
 108   idealreg2debugmask  [Op_RegFlags] = NULL;
 109 
 110   idealreg2mhdebugmask[Op_RegI] = NULL;
 111   idealreg2mhdebugmask[Op_RegN] = NULL;
 112   idealreg2mhdebugmask[Op_RegL] = NULL;
 113   idealreg2mhdebugmask[Op_RegF] = NULL;
 114   idealreg2mhdebugmask[Op_RegD] = NULL;
 115   idealreg2mhdebugmask[Op_RegP] = NULL;
 116   idealreg2mhdebugmask[Op_VecS] = NULL;
 117   idealreg2mhdebugmask[Op_VecD] = NULL;
 118   idealreg2mhdebugmask[Op_VecX] = NULL;
 119   idealreg2mhdebugmask[Op_VecY] = NULL;
 120   idealreg2mhdebugmask[Op_VecZ] = NULL;
 121   idealreg2mhdebugmask[Op_RegFlags] = NULL;
 122 
 123   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
 124 }
 125 
 126 //------------------------------warp_incoming_stk_arg------------------------
 127 // This warps a VMReg into an OptoReg::Name
 128 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
 129   OptoReg::Name warped;
 130   if( reg->is_stack() ) {  // Stack slot argument?
 131     warped = OptoReg::add(_old_SP, reg->reg2stack() );
 132     warped = OptoReg::add(warped, C->out_preserve_stack_slots());
 133     if( warped >= _in_arg_limit )
 134       _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
 135     if (!RegMask::can_represent_arg(warped)) {
 136       // the compiler cannot represent this method's calling sequence
 137       C->record_method_not_compilable("unsupported incoming calling sequence");
 138       return OptoReg::Bad;
 139     }
 140     return warped;
 141   }
 142   return OptoReg::as_OptoReg(reg);
 143 }
 144 
 145 //---------------------------compute_old_SP------------------------------------
 146 OptoReg::Name Compile::compute_old_SP() {
 147   int fixed    = fixed_slots();
 148   int preserve = in_preserve_stack_slots();
 149   return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
 150 }
 151 
 152 
 153 
 154 #ifdef ASSERT
 155 void Matcher::verify_new_nodes_only(Node* xroot) {
 156   // Make sure that the new graph only references new nodes
 157   ResourceMark rm;
 158   Unique_Node_List worklist;
 159   VectorSet visited(Thread::current()->resource_area());
 160   worklist.push(xroot);
 161   while (worklist.size() > 0) {
 162     Node* n = worklist.pop();
 163     visited <<= n->_idx;
 164     assert(C->node_arena()->contains(n), "dead node");
 165     for (uint j = 0; j < n->req(); j++) {
 166       Node* in = n->in(j);
 167       if (in != NULL) {
 168         assert(C->node_arena()->contains(in), "dead node");
 169         if (!visited.test(in->_idx)) {
 170           worklist.push(in);
 171         }
 172       }
 173     }
 174   }
 175 }
 176 #endif
 177 
 178 
 179 //---------------------------match---------------------------------------------
 180 void Matcher::match( ) {
 181   if( MaxLabelRootDepth < 100 ) { // Too small?
 182     assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
 183     MaxLabelRootDepth = 100;
 184   }
 185   // One-time initialization of some register masks.
 186   init_spill_mask( C->root()->in(1) );
 187   _return_addr_mask = return_addr();
 188 #ifdef _LP64
 189   // Pointers take 2 slots in 64-bit land
 190   _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
 191 #endif
 192 
 193   // Map a Java-signature return type into return register-value
 194   // machine registers for 0, 1 and 2 returned values.
 195   const TypeTuple *range = C->tf()->range();
 196   if( range->cnt() > TypeFunc::Parms ) { // If not a void function
 197     // Get ideal-register return type
 198     uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
 199     // Get machine return register
 200     uint sop = C->start()->Opcode();
 201     OptoRegPair regs = return_value(ireg, false);
 202 
 203     // And mask for same
 204     _return_value_mask = RegMask(regs.first());
 205     if( OptoReg::is_valid(regs.second()) )
 206       _return_value_mask.Insert(regs.second());
 207   }
 208 
 209   // ---------------
 210   // Frame Layout
 211 
 212   // Need the method signature to determine the incoming argument types,
 213   // because the types determine which registers the incoming arguments are
 214   // in, and this affects the matched code.
 215   const TypeTuple *domain = C->tf()->domain();
 216   uint             argcnt = domain->cnt() - TypeFunc::Parms;
 217   BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
 218   VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
 219   _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
 220   _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
 221   uint i;
 222   for( i = 0; i<argcnt; i++ ) {
 223     sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
 224   }
 225 
 226   // Pass array of ideal registers and length to USER code (from the AD file)
 227   // that will convert this to an array of register numbers.
 228   const StartNode *start = C->start();
 229   start->calling_convention( sig_bt, vm_parm_regs, argcnt );
 230 #ifdef ASSERT
 231   // Sanity check users' calling convention.  Real handy while trying to
 232   // get the initial port correct.
 233   { for (uint i = 0; i<argcnt; i++) {
 234       if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 235         assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
 236         _parm_regs[i].set_bad();
 237         continue;
 238       }
 239       VMReg parm_reg = vm_parm_regs[i].first();
 240       assert(parm_reg->is_valid(), "invalid arg?");
 241       if (parm_reg->is_reg()) {
 242         OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
 243         assert(can_be_java_arg(opto_parm_reg) ||
 244                C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
 245                opto_parm_reg == inline_cache_reg(),
 246                "parameters in register must be preserved by runtime stubs");
 247       }
 248       for (uint j = 0; j < i; j++) {
 249         assert(parm_reg != vm_parm_regs[j].first(),
 250                "calling conv. must produce distinct regs");
 251       }
 252     }
 253   }
 254 #endif
 255 
 256   // Do some initial frame layout.
 257 
 258   // Compute the old incoming SP (may be called FP) as
 259   //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
 260   _old_SP = C->compute_old_SP();
 261   assert( is_even(_old_SP), "must be even" );
 262 
 263   // Compute highest incoming stack argument as
 264   //   _old_SP + out_preserve_stack_slots + incoming argument size.
 265   _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 266   assert( is_even(_in_arg_limit), "out_preserve must be even" );
 267   for( i = 0; i < argcnt; i++ ) {
 268     // Permit args to have no register
 269     _calling_convention_mask[i].Clear();
 270     if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 271       continue;
 272     }
 273     // calling_convention returns stack arguments as a count of
 274     // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
 275     // the allocators point of view, taking into account all the
 276     // preserve area, locks & pad2.
 277 
 278     OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
 279     if( OptoReg::is_valid(reg1))
 280       _calling_convention_mask[i].Insert(reg1);
 281 
 282     OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
 283     if( OptoReg::is_valid(reg2))
 284       _calling_convention_mask[i].Insert(reg2);
 285 
 286     // Saved biased stack-slot register number
 287     _parm_regs[i].set_pair(reg2, reg1);
 288   }
 289 
 290   // Finally, make sure the incoming arguments take up an even number of
 291   // words, in case the arguments or locals need to contain doubleword stack
 292   // slots.  The rest of the system assumes that stack slot pairs (in
 293   // particular, in the spill area) which look aligned will in fact be
 294   // aligned relative to the stack pointer in the target machine.  Double
 295   // stack slots will always be allocated aligned.
 296   _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
 297 
 298   // Compute highest outgoing stack argument as
 299   //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
 300   _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
 301   assert( is_even(_out_arg_limit), "out_preserve must be even" );
 302 
 303   if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
 304     // the compiler cannot represent this method's calling sequence
 305     C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
 306   }
 307 
 308   if (C->failing())  return;  // bailed out on incoming arg failure
 309 
 310   // ---------------
 311   // Collect roots of matcher trees.  Every node for which
 312   // _shared[_idx] is cleared is guaranteed to not be shared, and thus
 313   // can be a valid interior of some tree.
 314   find_shared( C->root() );
 315   find_shared( C->top() );
 316 
 317   C->print_method(PHASE_BEFORE_MATCHING);
 318 
 319   // Create new ideal node ConP #NULL even if it does exist in old space
 320   // to avoid false sharing if the corresponding mach node is not used.
 321   // The corresponding mach node is only used in rare cases for derived
 322   // pointers.
 323   Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
 324 
 325   // Swap out to old-space; emptying new-space
 326   Arena *old = C->node_arena()->move_contents(C->old_arena());
 327 
 328   // Save debug and profile information for nodes in old space:
 329   _old_node_note_array = C->node_note_array();
 330   if (_old_node_note_array != NULL) {
 331     C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
 332                            (C->comp_arena(), _old_node_note_array->length(),
 333                             0, NULL));
 334   }
 335 
 336   // Pre-size the new_node table to avoid the need for range checks.
 337   grow_new_node_array(C->unique());
 338 
 339   // Reset node counter so MachNodes start with _idx at 0
 340   int live_nodes = C->live_nodes();
 341   C->set_unique(0);
 342   C->reset_dead_node_list();
 343 
 344   // Recursively match trees from old space into new space.
 345   // Correct leaves of new-space Nodes; they point to old-space.
 346   _visited.Clear();             // Clear visit bits for xform call
 347   C->set_cached_top_node(xform( C->top(), live_nodes ));
 348   if (!C->failing()) {
 349     Node* xroot =        xform( C->root(), 1 );
 350     if (xroot == NULL) {
 351       Matcher::soft_match_failure();  // recursive matching process failed
 352       C->record_method_not_compilable("instruction match failed");
 353     } else {
 354       // During matching shared constants were attached to C->root()
 355       // because xroot wasn't available yet, so transfer the uses to
 356       // the xroot.
 357       for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
 358         Node* n = C->root()->fast_out(j);
 359         if (C->node_arena()->contains(n)) {
 360           assert(n->in(0) == C->root(), "should be control user");
 361           n->set_req(0, xroot);
 362           --j;
 363           --jmax;
 364         }
 365       }
 366 
 367       // Generate new mach node for ConP #NULL
 368       assert(new_ideal_null != NULL, "sanity");
 369       _mach_null = match_tree(new_ideal_null);
 370       // Don't set control, it will confuse GCM since there are no uses.
 371       // The control will be set when this node is used first time
 372       // in find_base_for_derived().
 373       assert(_mach_null != NULL, "");
 374 
 375       C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
 376 
 377 #ifdef ASSERT
 378       verify_new_nodes_only(xroot);
 379 #endif
 380     }
 381   }
 382   if (C->top() == NULL || C->root() == NULL) {
 383     C->record_method_not_compilable("graph lost"); // %%% cannot happen?
 384   }
 385   if (C->failing()) {
 386     // delete old;
 387     old->destruct_contents();
 388     return;
 389   }
 390   assert( C->top(), "" );
 391   assert( C->root(), "" );
 392   validate_null_checks();
 393 
 394   // Now smoke old-space
 395   NOT_DEBUG( old->destruct_contents() );
 396 
 397   // ------------------------
 398   // Set up save-on-entry registers
 399   Fixup_Save_On_Entry( );
 400 }
 401 
 402 
 403 //------------------------------Fixup_Save_On_Entry----------------------------
 404 // The stated purpose of this routine is to take care of save-on-entry
 405 // registers.  However, the overall goal of the Match phase is to convert into
 406 // machine-specific instructions which have RegMasks to guide allocation.
 407 // So what this procedure really does is put a valid RegMask on each input
 408 // to the machine-specific variations of all Return, TailCall and Halt
 409 // instructions.  It also adds edgs to define the save-on-entry values (and of
 410 // course gives them a mask).
 411 
 412 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
 413   RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
 414   // Do all the pre-defined register masks
 415   rms[TypeFunc::Control  ] = RegMask::Empty;
 416   rms[TypeFunc::I_O      ] = RegMask::Empty;
 417   rms[TypeFunc::Memory   ] = RegMask::Empty;
 418   rms[TypeFunc::ReturnAdr] = ret_adr;
 419   rms[TypeFunc::FramePtr ] = fp;
 420   return rms;
 421 }
 422 
 423 //---------------------------init_first_stack_mask-----------------------------
 424 // Create the initial stack mask used by values spilling to the stack.
 425 // Disallow any debug info in outgoing argument areas by setting the
 426 // initial mask accordingly.
 427 void Matcher::init_first_stack_mask() {
 428 
 429   // Allocate storage for spill masks as masks for the appropriate load type.
 430   RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
 431 
 432   idealreg2spillmask  [Op_RegN] = &rms[0];
 433   idealreg2spillmask  [Op_RegI] = &rms[1];
 434   idealreg2spillmask  [Op_RegL] = &rms[2];
 435   idealreg2spillmask  [Op_RegF] = &rms[3];
 436   idealreg2spillmask  [Op_RegD] = &rms[4];
 437   idealreg2spillmask  [Op_RegP] = &rms[5];
 438 
 439   idealreg2debugmask  [Op_RegN] = &rms[6];
 440   idealreg2debugmask  [Op_RegI] = &rms[7];
 441   idealreg2debugmask  [Op_RegL] = &rms[8];
 442   idealreg2debugmask  [Op_RegF] = &rms[9];
 443   idealreg2debugmask  [Op_RegD] = &rms[10];
 444   idealreg2debugmask  [Op_RegP] = &rms[11];
 445 
 446   idealreg2mhdebugmask[Op_RegN] = &rms[12];
 447   idealreg2mhdebugmask[Op_RegI] = &rms[13];
 448   idealreg2mhdebugmask[Op_RegL] = &rms[14];
 449   idealreg2mhdebugmask[Op_RegF] = &rms[15];
 450   idealreg2mhdebugmask[Op_RegD] = &rms[16];
 451   idealreg2mhdebugmask[Op_RegP] = &rms[17];
 452 
 453   idealreg2spillmask  [Op_VecS] = &rms[18];
 454   idealreg2spillmask  [Op_VecD] = &rms[19];
 455   idealreg2spillmask  [Op_VecX] = &rms[20];
 456   idealreg2spillmask  [Op_VecY] = &rms[21];
 457   idealreg2spillmask  [Op_VecZ] = &rms[22];
 458 
 459   OptoReg::Name i;
 460 
 461   // At first, start with the empty mask
 462   C->FIRST_STACK_mask().Clear();
 463 
 464   // Add in the incoming argument area
 465   OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 466   for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
 467     C->FIRST_STACK_mask().Insert(i);
 468   }
 469   // Add in all bits past the outgoing argument area
 470   guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
 471             "must be able to represent all call arguments in reg mask");
 472   OptoReg::Name init = _out_arg_limit;
 473   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
 474     C->FIRST_STACK_mask().Insert(i);
 475   }
 476   // Finally, set the "infinite stack" bit.
 477   C->FIRST_STACK_mask().set_AllStack();
 478 
 479   // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
 480   RegMask aligned_stack_mask = C->FIRST_STACK_mask();
 481   // Keep spill masks aligned.
 482   aligned_stack_mask.clear_to_pairs();
 483   assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 484 
 485   *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
 486 #ifdef _LP64
 487   *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
 488    idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
 489    idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
 490 #else
 491    idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
 492 #endif
 493   *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
 494    idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
 495   *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
 496    idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
 497   *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
 498    idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
 499   *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
 500    idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
 501 
 502   if (Matcher::vector_size_supported(T_BYTE,4)) {
 503     *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
 504      idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
 505   }
 506   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 507     // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
 508     // RA guarantees such alignment since it is needed for Double and Long values.
 509     *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
 510      idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
 511   }
 512   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 513     // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
 514     //
 515     // RA can use input arguments stack slots for spills but until RA
 516     // we don't know frame size and offset of input arg stack slots.
 517     //
 518     // Exclude last input arg stack slots to avoid spilling vectors there
 519     // otherwise vector spills could stomp over stack slots in caller frame.
 520     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 521     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
 522       aligned_stack_mask.Remove(in);
 523       in = OptoReg::add(in, -1);
 524     }
 525      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
 526      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 527     *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
 528      idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
 529   }
 530   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 531     // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
 532     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 533     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
 534       aligned_stack_mask.Remove(in);
 535       in = OptoReg::add(in, -1);
 536     }
 537      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
 538      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 539     *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
 540      idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
 541   }
 542   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 543     // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
 544     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 545     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
 546       aligned_stack_mask.Remove(in);
 547       in = OptoReg::add(in, -1);
 548     }
 549      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
 550      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 551     *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
 552      idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
 553   }
 554    if (UseFPUForSpilling) {
 555      // This mask logic assumes that the spill operations are
 556      // symmetric and that the registers involved are the same size.
 557      // On sparc for instance we may have to use 64 bit moves will
 558      // kill 2 registers when used with F0-F31.
 559      idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
 560      idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
 561 #ifdef _LP64
 562      idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
 563      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 564      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 565      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
 566 #else
 567      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
 568 #ifdef ARM
 569      // ARM has support for moving 64bit values between a pair of
 570      // integer registers and a double register
 571      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 572      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 573 #endif
 574 #endif
 575    }
 576 
 577   // Make up debug masks.  Any spill slot plus callee-save registers.
 578   // Caller-save registers are assumed to be trashable by the various
 579   // inline-cache fixup routines.
 580   *idealreg2debugmask  [Op_RegN]= *idealreg2spillmask[Op_RegN];
 581   *idealreg2debugmask  [Op_RegI]= *idealreg2spillmask[Op_RegI];
 582   *idealreg2debugmask  [Op_RegL]= *idealreg2spillmask[Op_RegL];
 583   *idealreg2debugmask  [Op_RegF]= *idealreg2spillmask[Op_RegF];
 584   *idealreg2debugmask  [Op_RegD]= *idealreg2spillmask[Op_RegD];
 585   *idealreg2debugmask  [Op_RegP]= *idealreg2spillmask[Op_RegP];
 586 
 587   *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
 588   *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
 589   *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
 590   *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
 591   *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
 592   *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
 593 
 594   // Prevent stub compilations from attempting to reference
 595   // callee-saved registers from debug info
 596   bool exclude_soe = !Compile::current()->is_method_compilation();
 597 
 598   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 599     // registers the caller has to save do not work
 600     if( _register_save_policy[i] == 'C' ||
 601         _register_save_policy[i] == 'A' ||
 602         (_register_save_policy[i] == 'E' && exclude_soe) ) {
 603       idealreg2debugmask  [Op_RegN]->Remove(i);
 604       idealreg2debugmask  [Op_RegI]->Remove(i); // Exclude save-on-call
 605       idealreg2debugmask  [Op_RegL]->Remove(i); // registers from debug
 606       idealreg2debugmask  [Op_RegF]->Remove(i); // masks
 607       idealreg2debugmask  [Op_RegD]->Remove(i);
 608       idealreg2debugmask  [Op_RegP]->Remove(i);
 609 
 610       idealreg2mhdebugmask[Op_RegN]->Remove(i);
 611       idealreg2mhdebugmask[Op_RegI]->Remove(i);
 612       idealreg2mhdebugmask[Op_RegL]->Remove(i);
 613       idealreg2mhdebugmask[Op_RegF]->Remove(i);
 614       idealreg2mhdebugmask[Op_RegD]->Remove(i);
 615       idealreg2mhdebugmask[Op_RegP]->Remove(i);
 616     }
 617   }
 618 
 619   // Subtract the register we use to save the SP for MethodHandle
 620   // invokes to from the debug mask.
 621   const RegMask save_mask = method_handle_invoke_SP_save_mask();
 622   idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
 623   idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
 624   idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
 625   idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
 626   idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
 627   idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
 628 }
 629 
 630 //---------------------------is_save_on_entry----------------------------------
 631 bool Matcher::is_save_on_entry( int reg ) {
 632   return
 633     _register_save_policy[reg] == 'E' ||
 634     _register_save_policy[reg] == 'A' || // Save-on-entry register?
 635     // Also save argument registers in the trampolining stubs
 636     (C->save_argument_registers() && is_spillable_arg(reg));
 637 }
 638 
 639 //---------------------------Fixup_Save_On_Entry-------------------------------
 640 void Matcher::Fixup_Save_On_Entry( ) {
 641   init_first_stack_mask();
 642 
 643   Node *root = C->root();       // Short name for root
 644   // Count number of save-on-entry registers.
 645   uint soe_cnt = number_of_saved_registers();
 646   uint i;
 647 
 648   // Find the procedure Start Node
 649   StartNode *start = C->start();
 650   assert( start, "Expect a start node" );
 651 
 652   // Save argument registers in the trampolining stubs
 653   if( C->save_argument_registers() )
 654     for( i = 0; i < _last_Mach_Reg; i++ )
 655       if( is_spillable_arg(i) )
 656         soe_cnt++;
 657 
 658   // Input RegMask array shared by all Returns.
 659   // The type for doubles and longs has a count of 2, but
 660   // there is only 1 returned value
 661   uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
 662   RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 663   // Returns have 0 or 1 returned values depending on call signature.
 664   // Return register is specified by return_value in the AD file.
 665   if (ret_edge_cnt > TypeFunc::Parms)
 666     ret_rms[TypeFunc::Parms+0] = _return_value_mask;
 667 
 668   // Input RegMask array shared by all Rethrows.
 669   uint reth_edge_cnt = TypeFunc::Parms+1;
 670   RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 671   // Rethrow takes exception oop only, but in the argument 0 slot.
 672   OptoReg::Name reg = find_receiver(false);
 673   if (reg >= 0) {
 674     reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
 675 #ifdef _LP64
 676     // Need two slots for ptrs in 64-bit land
 677     reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
 678 #endif
 679   }
 680 
 681   // Input RegMask array shared by all TailCalls
 682   uint tail_call_edge_cnt = TypeFunc::Parms+2;
 683   RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 684 
 685   // Input RegMask array shared by all TailJumps
 686   uint tail_jump_edge_cnt = TypeFunc::Parms+2;
 687   RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 688 
 689   // TailCalls have 2 returned values (target & moop), whose masks come
 690   // from the usual MachNode/MachOper mechanism.  Find a sample
 691   // TailCall to extract these masks and put the correct masks into
 692   // the tail_call_rms array.
 693   for( i=1; i < root->req(); i++ ) {
 694     MachReturnNode *m = root->in(i)->as_MachReturn();
 695     if( m->ideal_Opcode() == Op_TailCall ) {
 696       tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 697       tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 698       break;
 699     }
 700   }
 701 
 702   // TailJumps have 2 returned values (target & ex_oop), whose masks come
 703   // from the usual MachNode/MachOper mechanism.  Find a sample
 704   // TailJump to extract these masks and put the correct masks into
 705   // the tail_jump_rms array.
 706   for( i=1; i < root->req(); i++ ) {
 707     MachReturnNode *m = root->in(i)->as_MachReturn();
 708     if( m->ideal_Opcode() == Op_TailJump ) {
 709       tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 710       tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 711       break;
 712     }
 713   }
 714 
 715   // Input RegMask array shared by all Halts
 716   uint halt_edge_cnt = TypeFunc::Parms;
 717   RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 718 
 719   // Capture the return input masks into each exit flavor
 720   for( i=1; i < root->req(); i++ ) {
 721     MachReturnNode *exit = root->in(i)->as_MachReturn();
 722     switch( exit->ideal_Opcode() ) {
 723       case Op_Return   : exit->_in_rms = ret_rms;  break;
 724       case Op_Rethrow  : exit->_in_rms = reth_rms; break;
 725       case Op_TailCall : exit->_in_rms = tail_call_rms; break;
 726       case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
 727       case Op_Halt     : exit->_in_rms = halt_rms; break;
 728       default          : ShouldNotReachHere();
 729     }
 730   }
 731 
 732   // Next unused projection number from Start.
 733   int proj_cnt = C->tf()->domain()->cnt();
 734 
 735   // Do all the save-on-entry registers.  Make projections from Start for
 736   // them, and give them a use at the exit points.  To the allocator, they
 737   // look like incoming register arguments.
 738   for( i = 0; i < _last_Mach_Reg; i++ ) {
 739     if( is_save_on_entry(i) ) {
 740 
 741       // Add the save-on-entry to the mask array
 742       ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
 743       reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
 744       tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
 745       tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
 746       // Halts need the SOE registers, but only in the stack as debug info.
 747       // A just-prior uncommon-trap or deoptimization will use the SOE regs.
 748       halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
 749 
 750       Node *mproj;
 751 
 752       // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
 753       // into a single RegD.
 754       if( (i&1) == 0 &&
 755           _register_save_type[i  ] == Op_RegF &&
 756           _register_save_type[i+1] == Op_RegF &&
 757           is_save_on_entry(i+1) ) {
 758         // Add other bit for double
 759         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 760         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 761         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 762         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 763         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 764         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
 765         proj_cnt += 2;          // Skip 2 for doubles
 766       }
 767       else if( (i&1) == 1 &&    // Else check for high half of double
 768                _register_save_type[i-1] == Op_RegF &&
 769                _register_save_type[i  ] == Op_RegF &&
 770                is_save_on_entry(i-1) ) {
 771         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 772         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 773         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 774         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 775         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 776         mproj = C->top();
 777       }
 778       // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
 779       // into a single RegL.
 780       else if( (i&1) == 0 &&
 781           _register_save_type[i  ] == Op_RegI &&
 782           _register_save_type[i+1] == Op_RegI &&
 783         is_save_on_entry(i+1) ) {
 784         // Add other bit for long
 785         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 786         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 787         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 788         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 789         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 790         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
 791         proj_cnt += 2;          // Skip 2 for longs
 792       }
 793       else if( (i&1) == 1 &&    // Else check for high half of long
 794                _register_save_type[i-1] == Op_RegI &&
 795                _register_save_type[i  ] == Op_RegI &&
 796                is_save_on_entry(i-1) ) {
 797         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 798         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 799         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 800         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 801         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 802         mproj = C->top();
 803       } else {
 804         // Make a projection for it off the Start
 805         mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
 806       }
 807 
 808       ret_edge_cnt ++;
 809       reth_edge_cnt ++;
 810       tail_call_edge_cnt ++;
 811       tail_jump_edge_cnt ++;
 812       halt_edge_cnt ++;
 813 
 814       // Add a use of the SOE register to all exit paths
 815       for( uint j=1; j < root->req(); j++ )
 816         root->in(j)->add_req(mproj);
 817     } // End of if a save-on-entry register
 818   } // End of for all machine registers
 819 }
 820 
 821 //------------------------------init_spill_mask--------------------------------
 822 void Matcher::init_spill_mask( Node *ret ) {
 823   if( idealreg2regmask[Op_RegI] ) return; // One time only init
 824 
 825   OptoReg::c_frame_pointer = c_frame_pointer();
 826   c_frame_ptr_mask = c_frame_pointer();
 827 #ifdef _LP64
 828   // pointers are twice as big
 829   c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
 830 #endif
 831 
 832   // Start at OptoReg::stack0()
 833   STACK_ONLY_mask.Clear();
 834   OptoReg::Name init = OptoReg::stack2reg(0);
 835   // STACK_ONLY_mask is all stack bits
 836   OptoReg::Name i;
 837   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
 838     STACK_ONLY_mask.Insert(i);
 839   // Also set the "infinite stack" bit.
 840   STACK_ONLY_mask.set_AllStack();
 841 
 842   // Copy the register names over into the shared world
 843   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 844     // SharedInfo::regName[i] = regName[i];
 845     // Handy RegMasks per machine register
 846     mreg2regmask[i].Insert(i);
 847   }
 848 
 849   // Grab the Frame Pointer
 850   Node *fp  = ret->in(TypeFunc::FramePtr);
 851   Node *mem = ret->in(TypeFunc::Memory);
 852   const TypePtr* atp = TypePtr::BOTTOM;
 853   // Share frame pointer while making spill ops
 854   set_shared(fp);
 855 
 856   // Compute generic short-offset Loads
 857 #ifdef _LP64
 858   MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 859 #endif
 860   MachNode *spillI  = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
 861   MachNode *spillL  = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
 862   MachNode *spillF  = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
 863   MachNode *spillD  = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
 864   MachNode *spillP  = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 865   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 866          spillD != NULL && spillP != NULL, "");
 867   // Get the ADLC notion of the right regmask, for each basic type.
 868 #ifdef _LP64
 869   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 870 #endif
 871   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 872   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 873   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 874   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 875   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 876 
 877   // Vector regmasks.
 878   if (Matcher::vector_size_supported(T_BYTE,4)) {
 879     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 880     MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 881     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 882   }
 883   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 884     MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 885     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 886   }
 887   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 888     MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
 889     idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
 890   }
 891   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 892     MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
 893     idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
 894   }
 895   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 896     MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
 897     idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
 898   }
 899 }
 900 
 901 #ifdef ASSERT
 902 static void match_alias_type(Compile* C, Node* n, Node* m) {
 903   if (!VerifyAliases)  return;  // do not go looking for trouble by default
 904   const TypePtr* nat = n->adr_type();
 905   const TypePtr* mat = m->adr_type();
 906   int nidx = C->get_alias_index(nat);
 907   int midx = C->get_alias_index(mat);
 908   // Detune the assert for cases like (AndI 0xFF (LoadB p)).
 909   if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
 910     for (uint i = 1; i < n->req(); i++) {
 911       Node* n1 = n->in(i);
 912       const TypePtr* n1at = n1->adr_type();
 913       if (n1at != NULL) {
 914         nat = n1at;
 915         nidx = C->get_alias_index(n1at);
 916       }
 917     }
 918   }
 919   // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
 920   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
 921     switch (n->Opcode()) {
 922     case Op_PrefetchAllocation:
 923       nidx = Compile::AliasIdxRaw;
 924       nat = TypeRawPtr::BOTTOM;
 925       break;
 926     }
 927   }
 928   if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
 929     switch (n->Opcode()) {
 930     case Op_ClearArray:
 931       midx = Compile::AliasIdxRaw;
 932       mat = TypeRawPtr::BOTTOM;
 933       break;
 934     }
 935   }
 936   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
 937     switch (n->Opcode()) {
 938     case Op_Return:
 939     case Op_Rethrow:
 940     case Op_Halt:
 941     case Op_TailCall:
 942     case Op_TailJump:
 943       nidx = Compile::AliasIdxBot;
 944       nat = TypePtr::BOTTOM;
 945       break;
 946     }
 947   }
 948   if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
 949     switch (n->Opcode()) {
 950     case Op_StrComp:
 951     case Op_StrEquals:
 952     case Op_StrIndexOf:
 953     case Op_StrIndexOfChar:
 954     case Op_AryEq:
 955     case Op_HasNegatives:
 956     case Op_MemBarVolatile:
 957     case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
 958     case Op_StrInflatedCopy:
 959     case Op_StrCompressedCopy:
 960     case Op_OnSpinWait:
 961     case Op_EncodeISOArray:
 962       nidx = Compile::AliasIdxTop;
 963       nat = NULL;
 964       break;
 965     }
 966   }
 967   if (nidx != midx) {
 968     if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
 969       tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
 970       n->dump();
 971       m->dump();
 972     }
 973     assert(C->subsume_loads() && C->must_alias(nat, midx),
 974            "must not lose alias info when matching");
 975   }
 976 }
 977 #endif
 978 
 979 //------------------------------xform------------------------------------------
 980 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
 981 // Node in new-space.  Given a new-space Node, recursively walk his children.
 982 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
 983 Node *Matcher::xform( Node *n, int max_stack ) {
 984   // Use one stack to keep both: child's node/state and parent's node/index
 985   MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
 986   mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
 987   while (mstack.is_nonempty()) {
 988     C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
 989     if (C->failing()) return NULL;
 990     n = mstack.node();          // Leave node on stack
 991     Node_State nstate = mstack.state();
 992     if (nstate == Visit) {
 993       mstack.set_state(Post_Visit);
 994       Node *oldn = n;
 995       // Old-space or new-space check
 996       if (!C->node_arena()->contains(n)) {
 997         // Old space!
 998         Node* m;
 999         if (has_new_node(n)) {  // Not yet Label/Reduced
1000           m = new_node(n);
1001         } else {
1002           if (!is_dontcare(n)) { // Matcher can match this guy
1003             // Calls match special.  They match alone with no children.
1004             // Their children, the incoming arguments, match normally.
1005             m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1006             if (C->failing())  return NULL;
1007             if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1008             if (n->is_MemBar()) {
1009               m->as_MachMemBar()->set_adr_type(n->adr_type());
1010             }
1011           } else {                  // Nothing the matcher cares about
1012             if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) {       // Projections?
1013               // Convert to machine-dependent projection
1014               m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1015 #ifdef ASSERT
1016               _new2old_map.map(m->_idx, n);
1017 #endif
1018               if (m->in(0) != NULL) // m might be top
1019                 collect_null_checks(m, n);
1020             } else {                // Else just a regular 'ol guy
1021               m = n->clone();       // So just clone into new-space
1022 #ifdef ASSERT
1023               _new2old_map.map(m->_idx, n);
1024 #endif
1025               // Def-Use edges will be added incrementally as Uses
1026               // of this node are matched.
1027               assert(m->outcnt() == 0, "no Uses of this clone yet");
1028             }
1029           }
1030 
1031           set_new_node(n, m);       // Map old to new
1032           if (_old_node_note_array != NULL) {
1033             Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1034                                                   n->_idx);
1035             C->set_node_notes_at(m->_idx, nn);
1036           }
1037           debug_only(match_alias_type(C, n, m));
1038         }
1039         n = m;    // n is now a new-space node
1040         mstack.set_node(n);
1041       }
1042 
1043       // New space!
1044       if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1045 
1046       int i;
1047       // Put precedence edges on stack first (match them last).
1048       for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1049         Node *m = oldn->in(i);
1050         if (m == NULL) break;
1051         // set -1 to call add_prec() instead of set_req() during Step1
1052         mstack.push(m, Visit, n, -1);
1053       }
1054 
1055       // Handle precedence edges for interior nodes
1056       for (i = n->len()-1; (uint)i >= n->req(); i--) {
1057         Node *m = n->in(i);
1058         if (m == NULL || C->node_arena()->contains(m)) continue;
1059         n->rm_prec(i);
1060         // set -1 to call add_prec() instead of set_req() during Step1
1061         mstack.push(m, Visit, n, -1);
1062       }
1063 
1064       // For constant debug info, I'd rather have unmatched constants.
1065       int cnt = n->req();
1066       JVMState* jvms = n->jvms();
1067       int debug_cnt = jvms ? jvms->debug_start() : cnt;
1068 
1069       // Now do only debug info.  Clone constants rather than matching.
1070       // Constants are represented directly in the debug info without
1071       // the need for executable machine instructions.
1072       // Monitor boxes are also represented directly.
1073       for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1074         Node *m = n->in(i);          // Get input
1075         int op = m->Opcode();
1076         assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1077         if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1078             op == Op_ConF || op == Op_ConD || op == Op_ConL
1079             // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
1080             ) {
1081           m = m->clone();
1082 #ifdef ASSERT
1083           _new2old_map.map(m->_idx, n);
1084 #endif
1085           mstack.push(m, Post_Visit, n, i); // Don't need to visit
1086           mstack.push(m->in(0), Visit, m, 0);
1087         } else {
1088           mstack.push(m, Visit, n, i);
1089         }
1090       }
1091 
1092       // And now walk his children, and convert his inputs to new-space.
1093       for( ; i >= 0; --i ) { // For all normal inputs do
1094         Node *m = n->in(i);  // Get input
1095         if(m != NULL)
1096           mstack.push(m, Visit, n, i);
1097       }
1098 
1099     }
1100     else if (nstate == Post_Visit) {
1101       // Set xformed input
1102       Node *p = mstack.parent();
1103       if (p != NULL) { // root doesn't have parent
1104         int i = (int)mstack.index();
1105         if (i >= 0)
1106           p->set_req(i, n); // required input
1107         else if (i == -1)
1108           p->add_prec(n);   // precedence input
1109         else
1110           ShouldNotReachHere();
1111       }
1112       mstack.pop(); // remove processed node from stack
1113     }
1114     else {
1115       ShouldNotReachHere();
1116     }
1117   } // while (mstack.is_nonempty())
1118   return n; // Return new-space Node
1119 }
1120 
1121 //------------------------------warp_outgoing_stk_arg------------------------
1122 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1123   // Convert outgoing argument location to a pre-biased stack offset
1124   if (reg->is_stack()) {
1125     OptoReg::Name warped = reg->reg2stack();
1126     // Adjust the stack slot offset to be the register number used
1127     // by the allocator.
1128     warped = OptoReg::add(begin_out_arg_area, warped);
1129     // Keep track of the largest numbered stack slot used for an arg.
1130     // Largest used slot per call-site indicates the amount of stack
1131     // that is killed by the call.
1132     if( warped >= out_arg_limit_per_call )
1133       out_arg_limit_per_call = OptoReg::add(warped,1);
1134     if (!RegMask::can_represent_arg(warped)) {
1135       C->record_method_not_compilable("unsupported calling sequence");
1136       return OptoReg::Bad;
1137     }
1138     return warped;
1139   }
1140   return OptoReg::as_OptoReg(reg);
1141 }
1142 
1143 
1144 //------------------------------match_sfpt-------------------------------------
1145 // Helper function to match call instructions.  Calls match special.
1146 // They match alone with no children.  Their children, the incoming
1147 // arguments, match normally.
1148 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1149   MachSafePointNode *msfpt = NULL;
1150   MachCallNode      *mcall = NULL;
1151   uint               cnt;
1152   // Split out case for SafePoint vs Call
1153   CallNode *call;
1154   const TypeTuple *domain;
1155   ciMethod*        method = NULL;
1156   bool             is_method_handle_invoke = false;  // for special kill effects
1157   if( sfpt->is_Call() ) {
1158     call = sfpt->as_Call();
1159     domain = call->tf()->domain();
1160     cnt = domain->cnt();
1161 
1162     // Match just the call, nothing else
1163     MachNode *m = match_tree(call);
1164     if (C->failing())  return NULL;
1165     if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1166 
1167     // Copy data from the Ideal SafePoint to the machine version
1168     mcall = m->as_MachCall();
1169 
1170     mcall->set_tf(         call->tf());
1171     mcall->set_entry_point(call->entry_point());
1172     mcall->set_cnt(        call->cnt());
1173 
1174     if( mcall->is_MachCallJava() ) {
1175       MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
1176       const CallJavaNode *call_java =  call->as_CallJava();
1177       method = call_java->method();
1178       mcall_java->_method = method;
1179       mcall_java->_bci = call_java->_bci;
1180       mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1181       is_method_handle_invoke = call_java->is_method_handle_invoke();
1182       mcall_java->_method_handle_invoke = is_method_handle_invoke;
1183       mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1184       if (is_method_handle_invoke) {
1185         C->set_has_method_handle_invokes(true);
1186       }
1187       if( mcall_java->is_MachCallStaticJava() )
1188         mcall_java->as_MachCallStaticJava()->_name =
1189          call_java->as_CallStaticJava()->_name;
1190       if( mcall_java->is_MachCallDynamicJava() )
1191         mcall_java->as_MachCallDynamicJava()->_vtable_index =
1192          call_java->as_CallDynamicJava()->_vtable_index;
1193     }
1194     else if( mcall->is_MachCallRuntime() ) {
1195       mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1196     }
1197     msfpt = mcall;
1198   }
1199   // This is a non-call safepoint
1200   else {
1201     call = NULL;
1202     domain = NULL;
1203     MachNode *mn = match_tree(sfpt);
1204     if (C->failing())  return NULL;
1205     msfpt = mn->as_MachSafePoint();
1206     cnt = TypeFunc::Parms;
1207   }
1208 
1209   // Advertise the correct memory effects (for anti-dependence computation).
1210   msfpt->set_adr_type(sfpt->adr_type());
1211 
1212   // Allocate a private array of RegMasks.  These RegMasks are not shared.
1213   msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1214   // Empty them all.
1215   memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1216 
1217   // Do all the pre-defined non-Empty register masks
1218   msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1219   msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1220 
1221   // Place first outgoing argument can possibly be put.
1222   OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1223   assert( is_even(begin_out_arg_area), "" );
1224   // Compute max outgoing register number per call site.
1225   OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1226   // Calls to C may hammer extra stack slots above and beyond any arguments.
1227   // These are usually backing store for register arguments for varargs.
1228   if( call != NULL && call->is_CallRuntime() )
1229     out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1230 
1231 
1232   // Do the normal argument list (parameters) register masks
1233   int argcnt = cnt - TypeFunc::Parms;
1234   if( argcnt > 0 ) {          // Skip it all if we have no args
1235     BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1236     VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1237     int i;
1238     for( i = 0; i < argcnt; i++ ) {
1239       sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1240     }
1241     // V-call to pick proper calling convention
1242     call->calling_convention( sig_bt, parm_regs, argcnt );
1243 
1244 #ifdef ASSERT
1245     // Sanity check users' calling convention.  Really handy during
1246     // the initial porting effort.  Fairly expensive otherwise.
1247     { for (int i = 0; i<argcnt; i++) {
1248       if( !parm_regs[i].first()->is_valid() &&
1249           !parm_regs[i].second()->is_valid() ) continue;
1250       VMReg reg1 = parm_regs[i].first();
1251       VMReg reg2 = parm_regs[i].second();
1252       for (int j = 0; j < i; j++) {
1253         if( !parm_regs[j].first()->is_valid() &&
1254             !parm_regs[j].second()->is_valid() ) continue;
1255         VMReg reg3 = parm_regs[j].first();
1256         VMReg reg4 = parm_regs[j].second();
1257         if( !reg1->is_valid() ) {
1258           assert( !reg2->is_valid(), "valid halvsies" );
1259         } else if( !reg3->is_valid() ) {
1260           assert( !reg4->is_valid(), "valid halvsies" );
1261         } else {
1262           assert( reg1 != reg2, "calling conv. must produce distinct regs");
1263           assert( reg1 != reg3, "calling conv. must produce distinct regs");
1264           assert( reg1 != reg4, "calling conv. must produce distinct regs");
1265           assert( reg2 != reg3, "calling conv. must produce distinct regs");
1266           assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1267           assert( reg3 != reg4, "calling conv. must produce distinct regs");
1268         }
1269       }
1270     }
1271     }
1272 #endif
1273 
1274     // Visit each argument.  Compute its outgoing register mask.
1275     // Return results now can have 2 bits returned.
1276     // Compute max over all outgoing arguments both per call-site
1277     // and over the entire method.
1278     for( i = 0; i < argcnt; i++ ) {
1279       // Address of incoming argument mask to fill in
1280       RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1281       if( !parm_regs[i].first()->is_valid() &&
1282           !parm_regs[i].second()->is_valid() ) {
1283         continue;               // Avoid Halves
1284       }
1285       // Grab first register, adjust stack slots and insert in mask.
1286       OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1287       if (OptoReg::is_valid(reg1))
1288         rm->Insert( reg1 );
1289       // Grab second register (if any), adjust stack slots and insert in mask.
1290       OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1291       if (OptoReg::is_valid(reg2))
1292         rm->Insert( reg2 );
1293     } // End of for all arguments
1294 
1295     // Compute number of stack slots needed to restore stack in case of
1296     // Pascal-style argument popping.
1297     mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1298   }
1299 
1300   // Compute the max stack slot killed by any call.  These will not be
1301   // available for debug info, and will be used to adjust FIRST_STACK_mask
1302   // after all call sites have been visited.
1303   if( _out_arg_limit < out_arg_limit_per_call)
1304     _out_arg_limit = out_arg_limit_per_call;
1305 
1306   if (mcall) {
1307     // Kill the outgoing argument area, including any non-argument holes and
1308     // any legacy C-killed slots.  Use Fat-Projections to do the killing.
1309     // Since the max-per-method covers the max-per-call-site and debug info
1310     // is excluded on the max-per-method basis, debug info cannot land in
1311     // this killed area.
1312     uint r_cnt = mcall->tf()->range()->cnt();
1313     MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1314     if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1315       C->record_method_not_compilable("unsupported outgoing calling sequence");
1316     } else {
1317       for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1318         proj->_rout.Insert(OptoReg::Name(i));
1319     }
1320     if (proj->_rout.is_NotEmpty()) {
1321       push_projection(proj);
1322     }
1323   }
1324   // Transfer the safepoint information from the call to the mcall
1325   // Move the JVMState list
1326   msfpt->set_jvms(sfpt->jvms());
1327   for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1328     jvms->set_map(sfpt);
1329   }
1330 
1331   // Debug inputs begin just after the last incoming parameter
1332   assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1333          (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1334 
1335   // Move the OopMap
1336   msfpt->_oop_map = sfpt->_oop_map;
1337 
1338   // Add additional edges.
1339   if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1340     // For these calls we can not add MachConstantBase in expand(), as the
1341     // ins are not complete then.
1342     msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1343     if (msfpt->jvms() &&
1344         msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1345       // We added an edge before jvms, so we must adapt the position of the ins.
1346       msfpt->jvms()->adapt_position(+1);
1347     }
1348   }
1349 
1350   // Registers killed by the call are set in the local scheduling pass
1351   // of Global Code Motion.
1352   return msfpt;
1353 }
1354 
1355 //---------------------------match_tree----------------------------------------
1356 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
1357 // of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
1358 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1359 // a Load's result RegMask for memoization in idealreg2regmask[]
1360 MachNode *Matcher::match_tree( const Node *n ) {
1361   assert( n->Opcode() != Op_Phi, "cannot match" );
1362   assert( !n->is_block_start(), "cannot match" );
1363   // Set the mark for all locally allocated State objects.
1364   // When this call returns, the _states_arena arena will be reset
1365   // freeing all State objects.
1366   ResourceMark rm( &_states_arena );
1367 
1368   LabelRootDepth = 0;
1369 
1370   // StoreNodes require their Memory input to match any LoadNodes
1371   Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1372 #ifdef ASSERT
1373   Node* save_mem_node = _mem_node;
1374   _mem_node = n->is_Store() ? (Node*)n : NULL;
1375 #endif
1376   // State object for root node of match tree
1377   // Allocate it on _states_arena - stack allocation can cause stack overflow.
1378   State *s = new (&_states_arena) State;
1379   s->_kids[0] = NULL;
1380   s->_kids[1] = NULL;
1381   s->_leaf = (Node*)n;
1382   // Label the input tree, allocating labels from top-level arena
1383   Label_Root( n, s, n->in(0), mem );
1384   if (C->failing())  return NULL;
1385 
1386   // The minimum cost match for the whole tree is found at the root State
1387   uint mincost = max_juint;
1388   uint cost = max_juint;
1389   uint i;
1390   for( i = 0; i < NUM_OPERANDS; i++ ) {
1391     if( s->valid(i) &&                // valid entry and
1392         s->_cost[i] < cost &&         // low cost and
1393         s->_rule[i] >= NUM_OPERANDS ) // not an operand
1394       cost = s->_cost[mincost=i];
1395   }
1396   if (mincost == max_juint) {
1397 #ifndef PRODUCT
1398     tty->print("No matching rule for:");
1399     s->dump();
1400 #endif
1401     Matcher::soft_match_failure();
1402     return NULL;
1403   }
1404   // Reduce input tree based upon the state labels to machine Nodes
1405   MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1406 #ifdef ASSERT
1407   _old2new_map.map(n->_idx, m);
1408   _new2old_map.map(m->_idx, (Node*)n);
1409 #endif
1410 
1411   // Add any Matcher-ignored edges
1412   uint cnt = n->req();
1413   uint start = 1;
1414   if( mem != (Node*)1 ) start = MemNode::Memory+1;
1415   if( n->is_AddP() ) {
1416     assert( mem == (Node*)1, "" );
1417     start = AddPNode::Base+1;
1418   }
1419   for( i = start; i < cnt; i++ ) {
1420     if( !n->match_edge(i) ) {
1421       if( i < m->req() )
1422         m->ins_req( i, n->in(i) );
1423       else
1424         m->add_req( n->in(i) );
1425     }
1426   }
1427 
1428   debug_only( _mem_node = save_mem_node; )
1429   return m;
1430 }
1431 
1432 
1433 //------------------------------match_into_reg---------------------------------
1434 // Choose to either match this Node in a register or part of the current
1435 // match tree.  Return true for requiring a register and false for matching
1436 // as part of the current match tree.
1437 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1438 
1439   const Type *t = m->bottom_type();
1440 
1441   if (t->singleton()) {
1442     // Never force constants into registers.  Allow them to match as
1443     // constants or registers.  Copies of the same value will share
1444     // the same register.  See find_shared_node.
1445     return false;
1446   } else {                      // Not a constant
1447     // Stop recursion if they have different Controls.
1448     Node* m_control = m->in(0);
1449     // Control of load's memory can post-dominates load's control.
1450     // So use it since load can't float above its memory.
1451     Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1452     if (control && m_control && control != m_control && control != mem_control) {
1453 
1454       // Actually, we can live with the most conservative control we
1455       // find, if it post-dominates the others.  This allows us to
1456       // pick up load/op/store trees where the load can float a little
1457       // above the store.
1458       Node *x = control;
1459       const uint max_scan = 6;  // Arbitrary scan cutoff
1460       uint j;
1461       for (j=0; j<max_scan; j++) {
1462         if (x->is_Region())     // Bail out at merge points
1463           return true;
1464         x = x->in(0);
1465         if (x == m_control)     // Does 'control' post-dominate
1466           break;                // m->in(0)?  If so, we can use it
1467         if (x == mem_control)   // Does 'control' post-dominate
1468           break;                // mem_control?  If so, we can use it
1469       }
1470       if (j == max_scan)        // No post-domination before scan end?
1471         return true;            // Then break the match tree up
1472     }
1473     if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1474         (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1475       // These are commonly used in address expressions and can
1476       // efficiently fold into them on X64 in some cases.
1477       return false;
1478     }
1479   }
1480 
1481   // Not forceable cloning.  If shared, put it into a register.
1482   return shared;
1483 }
1484 
1485 
1486 //------------------------------Instruction Selection--------------------------
1487 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1488 // ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
1489 // things the Matcher does not match (e.g., Memory), and things with different
1490 // Controls (hence forced into different blocks).  We pass in the Control
1491 // selected for this entire State tree.
1492 
1493 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1494 // Store and the Load must have identical Memories (as well as identical
1495 // pointers).  Since the Matcher does not have anything for Memory (and
1496 // does not handle DAGs), I have to match the Memory input myself.  If the
1497 // Tree root is a Store, I require all Loads to have the identical memory.
1498 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1499   // Since Label_Root is a recursive function, its possible that we might run
1500   // out of stack space.  See bugs 6272980 & 6227033 for more info.
1501   LabelRootDepth++;
1502   if (LabelRootDepth > MaxLabelRootDepth) {
1503     C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1504     return NULL;
1505   }
1506   uint care = 0;                // Edges matcher cares about
1507   uint cnt = n->req();
1508   uint i = 0;
1509 
1510   // Examine children for memory state
1511   // Can only subsume a child into your match-tree if that child's memory state
1512   // is not modified along the path to another input.
1513   // It is unsafe even if the other inputs are separate roots.
1514   Node *input_mem = NULL;
1515   for( i = 1; i < cnt; i++ ) {
1516     if( !n->match_edge(i) ) continue;
1517     Node *m = n->in(i);         // Get ith input
1518     assert( m, "expect non-null children" );
1519     if( m->is_Load() ) {
1520       if( input_mem == NULL ) {
1521         input_mem = m->in(MemNode::Memory);
1522       } else if( input_mem != m->in(MemNode::Memory) ) {
1523         input_mem = NodeSentinel;
1524       }
1525     }
1526   }
1527 
1528   for( i = 1; i < cnt; i++ ){// For my children
1529     if( !n->match_edge(i) ) continue;
1530     Node *m = n->in(i);         // Get ith input
1531     // Allocate states out of a private arena
1532     State *s = new (&_states_arena) State;
1533     svec->_kids[care++] = s;
1534     assert( care <= 2, "binary only for now" );
1535 
1536     // Recursively label the State tree.
1537     s->_kids[0] = NULL;
1538     s->_kids[1] = NULL;
1539     s->_leaf = m;
1540 
1541     // Check for leaves of the State Tree; things that cannot be a part of
1542     // the current tree.  If it finds any, that value is matched as a
1543     // register operand.  If not, then the normal matching is used.
1544     if( match_into_reg(n, m, control, i, is_shared(m)) ||
1545         //
1546         // Stop recursion if this is LoadNode and the root of this tree is a
1547         // StoreNode and the load & store have different memories.
1548         ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1549         // Can NOT include the match of a subtree when its memory state
1550         // is used by any of the other subtrees
1551         (input_mem == NodeSentinel) ) {
1552       // Print when we exclude matching due to different memory states at input-loads
1553       if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1554         && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1555         tty->print_cr("invalid input_mem");
1556       }
1557       // Switch to a register-only opcode; this value must be in a register
1558       // and cannot be subsumed as part of a larger instruction.
1559       s->DFA( m->ideal_reg(), m );
1560 
1561     } else {
1562       // If match tree has no control and we do, adopt it for entire tree
1563       if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1564         control = m->in(0);         // Pick up control
1565       // Else match as a normal part of the match tree.
1566       control = Label_Root(m,s,control,mem);
1567       if (C->failing()) return NULL;
1568     }
1569   }
1570 
1571 
1572   // Call DFA to match this node, and return
1573   svec->DFA( n->Opcode(), n );
1574 
1575 #ifdef ASSERT
1576   uint x;
1577   for( x = 0; x < _LAST_MACH_OPER; x++ )
1578     if( svec->valid(x) )
1579       break;
1580 
1581   if (x >= _LAST_MACH_OPER) {
1582     n->dump();
1583     svec->dump();
1584     assert( false, "bad AD file" );
1585   }
1586 #endif
1587   return control;
1588 }
1589 
1590 
1591 // Con nodes reduced using the same rule can share their MachNode
1592 // which reduces the number of copies of a constant in the final
1593 // program.  The register allocator is free to split uses later to
1594 // split live ranges.
1595 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1596   if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1597 
1598   // See if this Con has already been reduced using this rule.
1599   if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1600   MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1601   if (last != NULL && rule == last->rule()) {
1602     // Don't expect control change for DecodeN
1603     if (leaf->is_DecodeNarrowPtr())
1604       return last;
1605     // Get the new space root.
1606     Node* xroot = new_node(C->root());
1607     if (xroot == NULL) {
1608       // This shouldn't happen give the order of matching.
1609       return NULL;
1610     }
1611 
1612     // Shared constants need to have their control be root so they
1613     // can be scheduled properly.
1614     Node* control = last->in(0);
1615     if (control != xroot) {
1616       if (control == NULL || control == C->root()) {
1617         last->set_req(0, xroot);
1618       } else {
1619         assert(false, "unexpected control");
1620         return NULL;
1621       }
1622     }
1623     return last;
1624   }
1625   return NULL;
1626 }
1627 
1628 
1629 //------------------------------ReduceInst-------------------------------------
1630 // Reduce a State tree (with given Control) into a tree of MachNodes.
1631 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1632 // complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
1633 // Each MachNode has a number of complicated MachOper operands; each
1634 // MachOper also covers a further tree of Ideal Nodes.
1635 
1636 // The root of the Ideal match tree is always an instruction, so we enter
1637 // the recursion here.  After building the MachNode, we need to recurse
1638 // the tree checking for these cases:
1639 // (1) Child is an instruction -
1640 //     Build the instruction (recursively), add it as an edge.
1641 //     Build a simple operand (register) to hold the result of the instruction.
1642 // (2) Child is an interior part of an instruction -
1643 //     Skip over it (do nothing)
1644 // (3) Child is the start of a operand -
1645 //     Build the operand, place it inside the instruction
1646 //     Call ReduceOper.
1647 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1648   assert( rule >= NUM_OPERANDS, "called with operand rule" );
1649 
1650   MachNode* shared_node = find_shared_node(s->_leaf, rule);
1651   if (shared_node != NULL) {
1652     return shared_node;
1653   }
1654 
1655   // Build the object to represent this state & prepare for recursive calls
1656   MachNode *mach = s->MachNodeGenerator(rule);
1657   guarantee(mach != NULL, "Missing MachNode");
1658   mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1659   assert( mach->_opnds[0] != NULL, "Missing result operand" );
1660   Node *leaf = s->_leaf;
1661   // Check for instruction or instruction chain rule
1662   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1663     assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1664            "duplicating node that's already been matched");
1665     // Instruction
1666     mach->add_req( leaf->in(0) ); // Set initial control
1667     // Reduce interior of complex instruction
1668     ReduceInst_Interior( s, rule, mem, mach, 1 );
1669   } else {
1670     // Instruction chain rules are data-dependent on their inputs
1671     mach->add_req(0);             // Set initial control to none
1672     ReduceInst_Chain_Rule( s, rule, mem, mach );
1673   }
1674 
1675   // If a Memory was used, insert a Memory edge
1676   if( mem != (Node*)1 ) {
1677     mach->ins_req(MemNode::Memory,mem);
1678 #ifdef ASSERT
1679     // Verify adr type after matching memory operation
1680     const MachOper* oper = mach->memory_operand();
1681     if (oper != NULL && oper != (MachOper*)-1) {
1682       // It has a unique memory operand.  Find corresponding ideal mem node.
1683       Node* m = NULL;
1684       if (leaf->is_Mem()) {
1685         m = leaf;
1686       } else {
1687         m = _mem_node;
1688         assert(m != NULL && m->is_Mem(), "expecting memory node");
1689       }
1690       const Type* mach_at = mach->adr_type();
1691       // DecodeN node consumed by an address may have different type
1692       // than its input. Don't compare types for such case.
1693       if (m->adr_type() != mach_at &&
1694           (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1695            (m->in(MemNode::Address)->is_AddP() &&
1696             m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1697            (m->in(MemNode::Address)->is_AddP() &&
1698             m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1699             m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1700         mach_at = m->adr_type();
1701       }
1702       if (m->adr_type() != mach_at) {
1703         m->dump();
1704         tty->print_cr("mach:");
1705         mach->dump(1);
1706       }
1707       assert(m->adr_type() == mach_at, "matcher should not change adr type");
1708     }
1709 #endif
1710   }
1711 
1712   // If the _leaf is an AddP, insert the base edge
1713   if (leaf->is_AddP()) {
1714     mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1715   }
1716 
1717   uint number_of_projections_prior = number_of_projections();
1718 
1719   // Perform any 1-to-many expansions required
1720   MachNode *ex = mach->Expand(s, _projection_list, mem);
1721   if (ex != mach) {
1722     assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1723     if( ex->in(1)->is_Con() )
1724       ex->in(1)->set_req(0, C->root());
1725     // Remove old node from the graph
1726     for( uint i=0; i<mach->req(); i++ ) {
1727       mach->set_req(i,NULL);
1728     }
1729 #ifdef ASSERT
1730     _new2old_map.map(ex->_idx, s->_leaf);
1731 #endif
1732   }
1733 
1734   // PhaseChaitin::fixup_spills will sometimes generate spill code
1735   // via the matcher.  By the time, nodes have been wired into the CFG,
1736   // and any further nodes generated by expand rules will be left hanging
1737   // in space, and will not get emitted as output code.  Catch this.
1738   // Also, catch any new register allocation constraints ("projections")
1739   // generated belatedly during spill code generation.
1740   if (_allocation_started) {
1741     guarantee(ex == mach, "no expand rules during spill generation");
1742     guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1743   }
1744 
1745   if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1746     // Record the con for sharing
1747     _shared_nodes.map(leaf->_idx, ex);
1748   }
1749 
1750   return ex;
1751 }
1752 
1753 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1754   for (uint i = n->req(); i < n->len(); i++) {
1755     if (n->in(i) != NULL) {
1756       mach->add_prec(n->in(i));
1757     }
1758   }
1759 }
1760 
1761 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1762   // 'op' is what I am expecting to receive
1763   int op = _leftOp[rule];
1764   // Operand type to catch childs result
1765   // This is what my child will give me.
1766   int opnd_class_instance = s->_rule[op];
1767   // Choose between operand class or not.
1768   // This is what I will receive.
1769   int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1770   // New rule for child.  Chase operand classes to get the actual rule.
1771   int newrule = s->_rule[catch_op];
1772 
1773   if( newrule < NUM_OPERANDS ) {
1774     // Chain from operand or operand class, may be output of shared node
1775     assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1776             "Bad AD file: Instruction chain rule must chain from operand");
1777     // Insert operand into array of operands for this instruction
1778     mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1779 
1780     ReduceOper( s, newrule, mem, mach );
1781   } else {
1782     // Chain from the result of an instruction
1783     assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1784     mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1785     Node *mem1 = (Node*)1;
1786     debug_only(Node *save_mem_node = _mem_node;)
1787     mach->add_req( ReduceInst(s, newrule, mem1) );
1788     debug_only(_mem_node = save_mem_node;)
1789   }
1790   return;
1791 }
1792 
1793 
1794 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1795   handle_precedence_edges(s->_leaf, mach);
1796 
1797   if( s->_leaf->is_Load() ) {
1798     Node *mem2 = s->_leaf->in(MemNode::Memory);
1799     assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1800     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1801     mem = mem2;
1802   }
1803   if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1804     if( mach->in(0) == NULL )
1805       mach->set_req(0, s->_leaf->in(0));
1806   }
1807 
1808   // Now recursively walk the state tree & add operand list.
1809   for( uint i=0; i<2; i++ ) {   // binary tree
1810     State *newstate = s->_kids[i];
1811     if( newstate == NULL ) break;      // Might only have 1 child
1812     // 'op' is what I am expecting to receive
1813     int op;
1814     if( i == 0 ) {
1815       op = _leftOp[rule];
1816     } else {
1817       op = _rightOp[rule];
1818     }
1819     // Operand type to catch childs result
1820     // This is what my child will give me.
1821     int opnd_class_instance = newstate->_rule[op];
1822     // Choose between operand class or not.
1823     // This is what I will receive.
1824     int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1825     // New rule for child.  Chase operand classes to get the actual rule.
1826     int newrule = newstate->_rule[catch_op];
1827 
1828     if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1829       // Operand/operandClass
1830       // Insert operand into array of operands for this instruction
1831       mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1832       ReduceOper( newstate, newrule, mem, mach );
1833 
1834     } else {                    // Child is internal operand or new instruction
1835       if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1836         // internal operand --> call ReduceInst_Interior
1837         // Interior of complex instruction.  Do nothing but recurse.
1838         num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1839       } else {
1840         // instruction --> call build operand(  ) to catch result
1841         //             --> ReduceInst( newrule )
1842         mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1843         Node *mem1 = (Node*)1;
1844         debug_only(Node *save_mem_node = _mem_node;)
1845         mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1846         debug_only(_mem_node = save_mem_node;)
1847       }
1848     }
1849     assert( mach->_opnds[num_opnds-1], "" );
1850   }
1851   return num_opnds;
1852 }
1853 
1854 // This routine walks the interior of possible complex operands.
1855 // At each point we check our children in the match tree:
1856 // (1) No children -
1857 //     We are a leaf; add _leaf field as an input to the MachNode
1858 // (2) Child is an internal operand -
1859 //     Skip over it ( do nothing )
1860 // (3) Child is an instruction -
1861 //     Call ReduceInst recursively and
1862 //     and instruction as an input to the MachNode
1863 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1864   assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1865   State *kid = s->_kids[0];
1866   assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1867 
1868   // Leaf?  And not subsumed?
1869   if( kid == NULL && !_swallowed[rule] ) {
1870     mach->add_req( s->_leaf );  // Add leaf pointer
1871     return;                     // Bail out
1872   }
1873 
1874   if( s->_leaf->is_Load() ) {
1875     assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1876     mem = s->_leaf->in(MemNode::Memory);
1877     debug_only(_mem_node = s->_leaf;)
1878   }
1879 
1880   handle_precedence_edges(s->_leaf, mach);
1881 
1882   if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1883     if( !mach->in(0) )
1884       mach->set_req(0,s->_leaf->in(0));
1885     else {
1886       assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1887     }
1888   }
1889 
1890   for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) {   // binary tree
1891     int newrule;
1892     if( i == 0)
1893       newrule = kid->_rule[_leftOp[rule]];
1894     else
1895       newrule = kid->_rule[_rightOp[rule]];
1896 
1897     if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1898       // Internal operand; recurse but do nothing else
1899       ReduceOper( kid, newrule, mem, mach );
1900 
1901     } else {                    // Child is a new instruction
1902       // Reduce the instruction, and add a direct pointer from this
1903       // machine instruction to the newly reduced one.
1904       Node *mem1 = (Node*)1;
1905       debug_only(Node *save_mem_node = _mem_node;)
1906       mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1907       debug_only(_mem_node = save_mem_node;)
1908     }
1909   }
1910 }
1911 
1912 
1913 // -------------------------------------------------------------------------
1914 // Java-Java calling convention
1915 // (what you use when Java calls Java)
1916 
1917 //------------------------------find_receiver----------------------------------
1918 // For a given signature, return the OptoReg for parameter 0.
1919 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1920   VMRegPair regs;
1921   BasicType sig_bt = T_OBJECT;
1922   calling_convention(&sig_bt, &regs, 1, is_outgoing);
1923   // Return argument 0 register.  In the LP64 build pointers
1924   // take 2 registers, but the VM wants only the 'main' name.
1925   return OptoReg::as_OptoReg(regs.first());
1926 }
1927 
1928 // This function identifies sub-graphs in which a 'load' node is
1929 // input to two different nodes, and such that it can be matched
1930 // with BMI instructions like blsi, blsr, etc.
1931 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1932 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1933 // refers to the same node.
1934 #ifdef X86
1935 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1936 // This is a temporary solution until we make DAGs expressible in ADL.
1937 template<typename ConType>
1938 class FusedPatternMatcher {
1939   Node* _op1_node;
1940   Node* _mop_node;
1941   int _con_op;
1942 
1943   static int match_next(Node* n, int next_op, int next_op_idx) {
1944     if (n->in(1) == NULL || n->in(2) == NULL) {
1945       return -1;
1946     }
1947 
1948     if (next_op_idx == -1) { // n is commutative, try rotations
1949       if (n->in(1)->Opcode() == next_op) {
1950         return 1;
1951       } else if (n->in(2)->Opcode() == next_op) {
1952         return 2;
1953       }
1954     } else {
1955       assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1956       if (n->in(next_op_idx)->Opcode() == next_op) {
1957         return next_op_idx;
1958       }
1959     }
1960     return -1;
1961   }
1962 public:
1963   FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1964     _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1965 
1966   bool match(int op1, int op1_op2_idx,  // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1967              int op2, int op2_con_idx,  // op2 and the index of the op2->con edge, -1 if op2 is commutative
1968              typename ConType::NativeType con_value) {
1969     if (_op1_node->Opcode() != op1) {
1970       return false;
1971     }
1972     if (_mop_node->outcnt() > 2) {
1973       return false;
1974     }
1975     op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1976     if (op1_op2_idx == -1) {
1977       return false;
1978     }
1979     // Memory operation must be the other edge
1980     int op1_mop_idx = (op1_op2_idx & 1) + 1;
1981 
1982     // Check that the mop node is really what we want
1983     if (_op1_node->in(op1_mop_idx) == _mop_node) {
1984       Node *op2_node = _op1_node->in(op1_op2_idx);
1985       if (op2_node->outcnt() > 1) {
1986         return false;
1987       }
1988       assert(op2_node->Opcode() == op2, "Should be");
1989       op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1990       if (op2_con_idx == -1) {
1991         return false;
1992       }
1993       // Memory operation must be the other edge
1994       int op2_mop_idx = (op2_con_idx & 1) + 1;
1995       // Check that the memory operation is the same node
1996       if (op2_node->in(op2_mop_idx) == _mop_node) {
1997         // Now check the constant
1998         const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1999         if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2000           return true;
2001         }
2002       }
2003     }
2004     return false;
2005   }
2006 };
2007 
2008 
2009 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2010   if (n != NULL && m != NULL) {
2011     if (m->Opcode() == Op_LoadI) {
2012       FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2013       return bmii.match(Op_AndI, -1, Op_SubI,  1,  0)  ||
2014              bmii.match(Op_AndI, -1, Op_AddI, -1, -1)  ||
2015              bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2016     } else if (m->Opcode() == Op_LoadL) {
2017       FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2018       return bmil.match(Op_AndL, -1, Op_SubL,  1,  0) ||
2019              bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2020              bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2021     }
2022   }
2023   return false;
2024 }
2025 #endif // X86
2026 
2027 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2028   Node *off = m->in(AddPNode::Offset);
2029   if (off->is_Con()) {
2030     address_visited.test_set(m->_idx); // Flag as address_visited
2031     mstack.push(m->in(AddPNode::Address), Pre_Visit);
2032     // Clone X+offset as it also folds into most addressing expressions
2033     mstack.push(off, Visit);
2034     mstack.push(m->in(AddPNode::Base), Pre_Visit);
2035     return true;
2036   }
2037   return false;
2038 }
2039 
2040 // A method-klass-holder may be passed in the inline_cache_reg
2041 // and then expanded into the inline_cache_reg and a method_oop register
2042 //   defined in ad_<arch>.cpp
2043 
2044 //------------------------------find_shared------------------------------------
2045 // Set bits if Node is shared or otherwise a root
2046 void Matcher::find_shared( Node *n ) {
2047   // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2048   MStack mstack(C->live_nodes() * 2);
2049   // Mark nodes as address_visited if they are inputs to an address expression
2050   VectorSet address_visited(Thread::current()->resource_area());
2051   mstack.push(n, Visit);     // Don't need to pre-visit root node
2052   while (mstack.is_nonempty()) {
2053     n = mstack.node();       // Leave node on stack
2054     Node_State nstate = mstack.state();
2055     uint nop = n->Opcode();
2056     if (nstate == Pre_Visit) {
2057       if (address_visited.test(n->_idx)) { // Visited in address already?
2058         // Flag as visited and shared now.
2059         set_visited(n);
2060       }
2061       if (is_visited(n)) {   // Visited already?
2062         // Node is shared and has no reason to clone.  Flag it as shared.
2063         // This causes it to match into a register for the sharing.
2064         set_shared(n);       // Flag as shared and
2065         mstack.pop();        // remove node from stack
2066         continue;
2067       }
2068       nstate = Visit; // Not already visited; so visit now
2069     }
2070     if (nstate == Visit) {
2071       mstack.set_state(Post_Visit);
2072       set_visited(n);   // Flag as visited now
2073       bool mem_op = false;
2074       int mem_addr_idx = MemNode::Address;
2075 
2076       switch( nop ) {  // Handle some opcodes special
2077       case Op_Phi:             // Treat Phis as shared roots
2078       case Op_Parm:
2079       case Op_Proj:            // All handled specially during matching
2080       case Op_SafePointScalarObject:
2081         set_shared(n);
2082         set_dontcare(n);
2083         break;
2084       case Op_If:
2085       case Op_CountedLoopEnd:
2086         mstack.set_state(Alt_Post_Visit); // Alternative way
2087         // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
2088         // with matching cmp/branch in 1 instruction.  The Matcher needs the
2089         // Bool and CmpX side-by-side, because it can only get at constants
2090         // that are at the leaves of Match trees, and the Bool's condition acts
2091         // as a constant here.
2092         mstack.push(n->in(1), Visit);         // Clone the Bool
2093         mstack.push(n->in(0), Pre_Visit);     // Visit control input
2094         continue; // while (mstack.is_nonempty())
2095       case Op_ConvI2D:         // These forms efficiently match with a prior
2096       case Op_ConvI2F:         //   Load but not a following Store
2097         if( n->in(1)->is_Load() &&        // Prior load
2098             n->outcnt() == 1 &&           // Not already shared
2099             n->unique_out()->is_Store() ) // Following store
2100           set_shared(n);       // Force it to be a root
2101         break;
2102       case Op_ReverseBytesI:
2103       case Op_ReverseBytesL:
2104         if( n->in(1)->is_Load() &&        // Prior load
2105             n->outcnt() == 1 )            // Not already shared
2106           set_shared(n);                  // Force it to be a root
2107         break;
2108       case Op_BoxLock:         // Cant match until we get stack-regs in ADLC
2109       case Op_IfFalse:
2110       case Op_IfTrue:
2111       case Op_MachProj:
2112       case Op_MergeMem:
2113       case Op_Catch:
2114       case Op_CatchProj:
2115       case Op_CProj:
2116       case Op_JumpProj:
2117       case Op_JProj:
2118       case Op_NeverBranch:
2119         set_dontcare(n);
2120         break;
2121       case Op_Jump:
2122         mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
2123         mstack.push(n->in(0), Pre_Visit);     // Visit Control input
2124         continue;                             // while (mstack.is_nonempty())
2125       case Op_StrComp:
2126       case Op_StrEquals:
2127       case Op_StrIndexOf:
2128       case Op_StrIndexOfChar:
2129       case Op_AryEq:
2130       case Op_HasNegatives:
2131       case Op_StrInflatedCopy:
2132       case Op_StrCompressedCopy:
2133       case Op_EncodeISOArray:
2134       case Op_FmaD:
2135       case Op_FmaF:
2136       case Op_FmaVD:
2137       case Op_FmaVF:
2138         set_shared(n); // Force result into register (it will be anyways)
2139         break;
2140       case Op_ConP: {  // Convert pointers above the centerline to NUL
2141         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2142         const TypePtr* tp = tn->type()->is_ptr();
2143         if (tp->_ptr == TypePtr::AnyNull) {
2144           tn->set_type(TypePtr::NULL_PTR);
2145         }
2146         break;
2147       }
2148       case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
2149         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2150         const TypePtr* tp = tn->type()->make_ptr();
2151         if (tp && tp->_ptr == TypePtr::AnyNull) {
2152           tn->set_type(TypeNarrowOop::NULL_PTR);
2153         }
2154         break;
2155       }
2156       case Op_Binary:         // These are introduced in the Post_Visit state.
2157         ShouldNotReachHere();
2158         break;
2159       case Op_ClearArray:
2160       case Op_SafePoint:
2161         mem_op = true;
2162         break;
2163 #if INCLUDE_SHENANDOAHGC
2164       case Op_ShenandoahReadBarrier:
2165         if (n->in(ShenandoahBarrierNode::ValueIn)->is_DecodeNarrowPtr()) {
2166           set_shared(n->in(ShenandoahBarrierNode::ValueIn)->in(1));
2167         }
2168         mem_op = true;
2169         set_shared(n);
2170         break;
2171 #endif
2172 #if INCLUDE_ZGC
2173       case Op_CallLeaf:
2174         if (UseZGC) {
2175           if (n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr() ||
2176               n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_weak_oop_field_preloaded_addr()) {
2177             mem_op = true;
2178             mem_addr_idx = TypeFunc::Parms+1;
2179           }
2180           break;
2181         }
2182 #endif
2183       default:
2184         if( n->is_Store() ) {
2185           // Do match stores, despite no ideal reg
2186           mem_op = true;
2187           break;
2188         }
2189         if( n->is_Mem() ) { // Loads and LoadStores
2190           mem_op = true;
2191           // Loads must be root of match tree due to prior load conflict
2192           if( C->subsume_loads() == false )
2193             set_shared(n);
2194         }
2195         // Fall into default case
2196         if( !n->ideal_reg() )
2197           set_dontcare(n);  // Unmatchable Nodes
2198       } // end_switch
2199 
2200       for(int i = n->req() - 1; i >= 0; --i) { // For my children
2201         Node *m = n->in(i); // Get ith input
2202         if (m == NULL) continue;  // Ignore NULLs
2203         uint mop = m->Opcode();
2204 
2205         // Must clone all producers of flags, or we will not match correctly.
2206         // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2207         // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
2208         // are also there, so we may match a float-branch to int-flags and
2209         // expect the allocator to haul the flags from the int-side to the
2210         // fp-side.  No can do.
2211         if( _must_clone[mop] ) {
2212           mstack.push(m, Visit);
2213           continue; // for(int i = ...)
2214         }
2215 
2216         if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2217           // Bases used in addresses must be shared but since
2218           // they are shared through a DecodeN they may appear
2219           // to have a single use so force sharing here.
2220           set_shared(m->in(AddPNode::Base)->in(1));
2221         }
2222 
2223         // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2224 #ifdef X86
2225         if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2226           mstack.push(m, Visit);
2227           continue;
2228         }
2229 #endif
2230 
2231         // Clone addressing expressions as they are "free" in memory access instructions
2232         if (mem_op && i == mem_addr_idx && mop == Op_AddP &&
2233             // When there are other uses besides address expressions
2234             // put it on stack and mark as shared.
2235             !is_visited(m)) {
2236           // Some inputs for address expression are not put on stack
2237           // to avoid marking them as shared and forcing them into register
2238           // if they are used only in address expressions.
2239           // But they should be marked as shared if there are other uses
2240           // besides address expressions.
2241 
2242           if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2243             continue;
2244           }
2245         }   // if( mem_op &&
2246         mstack.push(m, Pre_Visit);
2247       }     // for(int i = ...)
2248     }
2249     else if (nstate == Alt_Post_Visit) {
2250       mstack.pop(); // Remove node from stack
2251       // We cannot remove the Cmp input from the Bool here, as the Bool may be
2252       // shared and all users of the Bool need to move the Cmp in parallel.
2253       // This leaves both the Bool and the If pointing at the Cmp.  To
2254       // prevent the Matcher from trying to Match the Cmp along both paths
2255       // BoolNode::match_edge always returns a zero.
2256 
2257       // We reorder the Op_If in a pre-order manner, so we can visit without
2258       // accidentally sharing the Cmp (the Bool and the If make 2 users).
2259       n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2260     }
2261     else if (nstate == Post_Visit) {
2262       mstack.pop(); // Remove node from stack
2263 
2264       // Now hack a few special opcodes
2265       switch( n->Opcode() ) {       // Handle some opcodes special
2266       case Op_StorePConditional:
2267       case Op_StoreIConditional:
2268       case Op_StoreLConditional:
2269       case Op_CompareAndExchangeB:
2270       case Op_CompareAndExchangeS:
2271       case Op_CompareAndExchangeI:
2272       case Op_CompareAndExchangeL:
2273       case Op_CompareAndExchangeP:
2274       case Op_CompareAndExchangeN:
2275       case Op_WeakCompareAndSwapB:
2276       case Op_WeakCompareAndSwapS:
2277       case Op_WeakCompareAndSwapI:
2278       case Op_WeakCompareAndSwapL:
2279       case Op_WeakCompareAndSwapP:
2280       case Op_WeakCompareAndSwapN:
2281       case Op_CompareAndSwapB:
2282       case Op_CompareAndSwapS:
2283       case Op_CompareAndSwapI:
2284       case Op_CompareAndSwapL:
2285       case Op_CompareAndSwapP:
2286       case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
2287         Node *newval = n->in(MemNode::ValueIn );
2288         Node *oldval  = n->in(LoadStoreConditionalNode::ExpectedIn);
2289         Node *pair = new BinaryNode( oldval, newval );
2290         n->set_req(MemNode::ValueIn,pair);
2291         n->del_req(LoadStoreConditionalNode::ExpectedIn);
2292         break;
2293       }
2294       case Op_CMoveD:              // Convert trinary to binary-tree
2295       case Op_CMoveF:
2296       case Op_CMoveI:
2297       case Op_CMoveL:
2298       case Op_CMoveN:
2299       case Op_CMoveP:
2300       case Op_CMoveVF:
2301       case Op_CMoveVD:  {
2302         // Restructure into a binary tree for Matching.  It's possible that
2303         // we could move this code up next to the graph reshaping for IfNodes
2304         // or vice-versa, but I do not want to debug this for Ladybird.
2305         // 10/2/2000 CNC.
2306         Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2307         n->set_req(1,pair1);
2308         Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2309         n->set_req(2,pair2);
2310         n->del_req(3);
2311         break;
2312       }
2313       case Op_LoopLimit: {
2314         Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2315         n->set_req(1,pair1);
2316         n->set_req(2,n->in(3));
2317         n->del_req(3);
2318         break;
2319       }
2320       case Op_StrEquals:
2321       case Op_StrIndexOfChar: {
2322         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2323         n->set_req(2,pair1);
2324         n->set_req(3,n->in(4));
2325         n->del_req(4);
2326         break;
2327       }
2328       case Op_StrComp:
2329       case Op_StrIndexOf: {
2330         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2331         n->set_req(2,pair1);
2332         Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2333         n->set_req(3,pair2);
2334         n->del_req(5);
2335         n->del_req(4);
2336         break;
2337       }
2338       case Op_StrCompressedCopy:
2339       case Op_StrInflatedCopy:
2340       case Op_EncodeISOArray: {
2341         // Restructure into a binary tree for Matching.
2342         Node* pair = new BinaryNode(n->in(3), n->in(4));
2343         n->set_req(3, pair);
2344         n->del_req(4);
2345         break;
2346       }
2347       case Op_FmaD:
2348       case Op_FmaF:
2349       case Op_FmaVD:
2350       case Op_FmaVF: {
2351         // Restructure into a binary tree for Matching.
2352         Node* pair = new BinaryNode(n->in(1), n->in(2));
2353         n->set_req(2, pair);
2354         n->set_req(1, n->in(3));
2355         n->del_req(3);
2356         break;
2357       }
2358       default:
2359         break;
2360       }
2361     }
2362     else {
2363       ShouldNotReachHere();
2364     }
2365   } // end of while (mstack.is_nonempty())
2366 }
2367 
2368 #ifdef ASSERT
2369 // machine-independent root to machine-dependent root
2370 void Matcher::dump_old2new_map() {
2371   _old2new_map.dump();
2372 }
2373 #endif
2374 
2375 //---------------------------collect_null_checks-------------------------------
2376 // Find null checks in the ideal graph; write a machine-specific node for
2377 // it.  Used by later implicit-null-check handling.  Actually collects
2378 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2379 // value being tested.
2380 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2381   Node *iff = proj->in(0);
2382   if( iff->Opcode() == Op_If ) {
2383     // During matching If's have Bool & Cmp side-by-side
2384     BoolNode *b = iff->in(1)->as_Bool();
2385     Node *cmp = iff->in(2);
2386     int opc = cmp->Opcode();
2387     if (opc != Op_CmpP && opc != Op_CmpN) return;
2388 
2389     const Type* ct = cmp->in(2)->bottom_type();
2390     if (ct == TypePtr::NULL_PTR ||
2391         (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2392 
2393       bool push_it = false;
2394       if( proj->Opcode() == Op_IfTrue ) {
2395 #ifndef PRODUCT
2396         extern int all_null_checks_found;
2397         all_null_checks_found++;
2398 #endif
2399         if( b->_test._test == BoolTest::ne ) {
2400           push_it = true;
2401         }
2402       } else {
2403         assert( proj->Opcode() == Op_IfFalse, "" );
2404         if( b->_test._test == BoolTest::eq ) {
2405           push_it = true;
2406         }
2407       }
2408       if( push_it ) {
2409         _null_check_tests.push(proj);
2410         Node* val = cmp->in(1);
2411 #ifdef _LP64
2412         if (val->bottom_type()->isa_narrowoop() &&
2413             !Matcher::narrow_oop_use_complex_address()) {
2414           //
2415           // Look for DecodeN node which should be pinned to orig_proj.
2416           // On platforms (Sparc) which can not handle 2 adds
2417           // in addressing mode we have to keep a DecodeN node and
2418           // use it to do implicit NULL check in address.
2419           //
2420           // DecodeN node was pinned to non-null path (orig_proj) during
2421           // CastPP transformation in final_graph_reshaping_impl().
2422           //
2423           uint cnt = orig_proj->outcnt();
2424           for (uint i = 0; i < orig_proj->outcnt(); i++) {
2425             Node* d = orig_proj->raw_out(i);
2426             if (d->is_DecodeN() && d->in(1) == val) {
2427               val = d;
2428               val->set_req(0, NULL); // Unpin now.
2429               // Mark this as special case to distinguish from
2430               // a regular case: CmpP(DecodeN, NULL).
2431               val = (Node*)(((intptr_t)val) | 1);
2432               break;
2433             }
2434           }
2435         }
2436 #endif
2437         _null_check_tests.push(val);
2438       }
2439     }
2440   }
2441 }
2442 
2443 //---------------------------validate_null_checks------------------------------
2444 // Its possible that the value being NULL checked is not the root of a match
2445 // tree.  If so, I cannot use the value in an implicit null check.
2446 void Matcher::validate_null_checks( ) {
2447   uint cnt = _null_check_tests.size();
2448   for( uint i=0; i < cnt; i+=2 ) {
2449     Node *test = _null_check_tests[i];
2450     Node *val = _null_check_tests[i+1];
2451     bool is_decoden = ((intptr_t)val) & 1;
2452     val = (Node*)(((intptr_t)val) & ~1);
2453     if (has_new_node(val)) {
2454       Node* new_val = new_node(val);
2455       if (is_decoden) {
2456         assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2457         // Note: new_val may have a control edge if
2458         // the original ideal node DecodeN was matched before
2459         // it was unpinned in Matcher::collect_null_checks().
2460         // Unpin the mach node and mark it.
2461         new_val->set_req(0, NULL);
2462         new_val = (Node*)(((intptr_t)new_val) | 1);
2463       }
2464       // Is a match-tree root, so replace with the matched value
2465       _null_check_tests.map(i+1, new_val);
2466     } else {
2467       // Yank from candidate list
2468       _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2469       _null_check_tests.map(i,_null_check_tests[--cnt]);
2470       _null_check_tests.pop();
2471       _null_check_tests.pop();
2472       i-=2;
2473     }
2474   }
2475 }
2476 
2477 // Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
2478 // atomic instruction acting as a store_load barrier without any
2479 // intervening volatile load, and thus we don't need a barrier here.
2480 // We retain the Node to act as a compiler ordering barrier.
2481 bool Matcher::post_store_load_barrier(const Node* vmb) {
2482   Compile* C = Compile::current();
2483   assert(vmb->is_MemBar(), "");
2484   assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2485   const MemBarNode* membar = vmb->as_MemBar();
2486 
2487   // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2488   Node* ctrl = NULL;
2489   for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2490     Node* p = membar->fast_out(i);
2491     assert(p->is_Proj(), "only projections here");
2492     if ((p->as_Proj()->_con == TypeFunc::Control) &&
2493         !C->node_arena()->contains(p)) { // Unmatched old-space only
2494       ctrl = p;
2495       break;
2496     }
2497   }
2498   assert((ctrl != NULL), "missing control projection");
2499 
2500   for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2501     Node *x = ctrl->fast_out(j);
2502     int xop = x->Opcode();
2503 
2504     // We don't need current barrier if we see another or a lock
2505     // before seeing volatile load.
2506     //
2507     // Op_Fastunlock previously appeared in the Op_* list below.
2508     // With the advent of 1-0 lock operations we're no longer guaranteed
2509     // that a monitor exit operation contains a serializing instruction.
2510 
2511     if (xop == Op_MemBarVolatile ||
2512         xop == Op_CompareAndExchangeB ||
2513         xop == Op_CompareAndExchangeS ||
2514         xop == Op_CompareAndExchangeI ||
2515         xop == Op_CompareAndExchangeL ||
2516         xop == Op_CompareAndExchangeP ||
2517         xop == Op_CompareAndExchangeN ||
2518         xop == Op_WeakCompareAndSwapB ||
2519         xop == Op_WeakCompareAndSwapS ||
2520         xop == Op_WeakCompareAndSwapL ||
2521         xop == Op_WeakCompareAndSwapP ||
2522         xop == Op_WeakCompareAndSwapN ||
2523         xop == Op_WeakCompareAndSwapI ||
2524         xop == Op_CompareAndSwapB ||
2525         xop == Op_CompareAndSwapS ||
2526         xop == Op_CompareAndSwapL ||
2527         xop == Op_CompareAndSwapP ||
2528         xop == Op_CompareAndSwapN ||
2529         xop == Op_CompareAndSwapI) {
2530       return true;
2531     }
2532 
2533     // Op_FastLock previously appeared in the Op_* list above.
2534     // With biased locking we're no longer guaranteed that a monitor
2535     // enter operation contains a serializing instruction.
2536     if ((xop == Op_FastLock) && !UseBiasedLocking) {
2537       return true;
2538     }
2539 
2540     if (x->is_MemBar()) {
2541       // We must retain this membar if there is an upcoming volatile
2542       // load, which will be followed by acquire membar.
2543       if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2544         return false;
2545       } else {
2546         // For other kinds of barriers, check by pretending we
2547         // are them, and seeing if we can be removed.
2548         return post_store_load_barrier(x->as_MemBar());
2549       }
2550     }
2551 
2552     // probably not necessary to check for these
2553     if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2554       return false;
2555     }
2556   }
2557   return false;
2558 }
2559 
2560 // Check whether node n is a branch to an uncommon trap that we could
2561 // optimize as test with very high branch costs in case of going to
2562 // the uncommon trap. The code must be able to be recompiled to use
2563 // a cheaper test.
2564 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2565   // Don't do it for natives, adapters, or runtime stubs
2566   Compile *C = Compile::current();
2567   if (!C->is_method_compilation()) return false;
2568 
2569   assert(n->is_If(), "You should only call this on if nodes.");
2570   IfNode *ifn = n->as_If();
2571 
2572   Node *ifFalse = NULL;
2573   for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2574     if (ifn->fast_out(i)->is_IfFalse()) {
2575       ifFalse = ifn->fast_out(i);
2576       break;
2577     }
2578   }
2579   assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2580 
2581   Node *reg = ifFalse;
2582   int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
2583                // Alternatively use visited set?  Seems too expensive.
2584   while (reg != NULL && cnt > 0) {
2585     CallNode *call = NULL;
2586     RegionNode *nxt_reg = NULL;
2587     for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2588       Node *o = reg->fast_out(i);
2589       if (o->is_Call()) {
2590         call = o->as_Call();
2591       }
2592       if (o->is_Region()) {
2593         nxt_reg = o->as_Region();
2594       }
2595     }
2596 
2597     if (call &&
2598         call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2599       const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2600       if (trtype->isa_int() && trtype->is_int()->is_con()) {
2601         jint tr_con = trtype->is_int()->get_con();
2602         Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2603         Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2604         assert((int)reason < (int)BitsPerInt, "recode bit map");
2605 
2606         if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2607             && action != Deoptimization::Action_none) {
2608           // This uncommon trap is sure to recompile, eventually.
2609           // When that happens, C->too_many_traps will prevent
2610           // this transformation from happening again.
2611           return true;
2612         }
2613       }
2614     }
2615 
2616     reg = nxt_reg;
2617     cnt--;
2618   }
2619 
2620   return false;
2621 }
2622 
2623 //=============================================================================
2624 //---------------------------State---------------------------------------------
2625 State::State(void) {
2626 #ifdef ASSERT
2627   _id = 0;
2628   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2629   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2630   //memset(_cost, -1, sizeof(_cost));
2631   //memset(_rule, -1, sizeof(_rule));
2632 #endif
2633   memset(_valid, 0, sizeof(_valid));
2634 }
2635 
2636 #ifdef ASSERT
2637 State::~State() {
2638   _id = 99;
2639   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2640   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2641   memset(_cost, -3, sizeof(_cost));
2642   memset(_rule, -3, sizeof(_rule));
2643 }
2644 #endif
2645 
2646 #ifndef PRODUCT
2647 //---------------------------dump----------------------------------------------
2648 void State::dump() {
2649   tty->print("\n");
2650   dump(0);
2651 }
2652 
2653 void State::dump(int depth) {
2654   for( int j = 0; j < depth; j++ )
2655     tty->print("   ");
2656   tty->print("--N: ");
2657   _leaf->dump();
2658   uint i;
2659   for( i = 0; i < _LAST_MACH_OPER; i++ )
2660     // Check for valid entry
2661     if( valid(i) ) {
2662       for( int j = 0; j < depth; j++ )
2663         tty->print("   ");
2664         assert(_cost[i] != max_juint, "cost must be a valid value");
2665         assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2666         tty->print_cr("%s  %d  %s",
2667                       ruleName[i], _cost[i], ruleName[_rule[i]] );
2668       }
2669   tty->cr();
2670 
2671   for( i=0; i<2; i++ )
2672     if( _kids[i] )
2673       _kids[i]->dump(depth+1);
2674 }
2675 #endif