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src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

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2801   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2802 
2803   if (left->is_single_cpu()) {
2804     assert(dest->is_single_cpu(), "expect single result reg");
2805     __ negw(dest->as_register(), left->as_register());
2806   } else if (left->is_double_cpu()) {
2807     assert(dest->is_double_cpu(), "expect double result reg");
2808     __ neg(dest->as_register_lo(), left->as_register_lo());
2809   } else if (left->is_single_fpu()) {
2810     assert(dest->is_single_fpu(), "expect single float result reg");
2811     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2812   } else {
2813     assert(left->is_double_fpu(), "expect double float operand reg");
2814     assert(dest->is_double_fpu(), "expect double float result reg");
2815     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2816   }
2817 }
2818 
2819 
2820 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2821   assert(patch_code == lir_patch_none, "Patch code not supported");




2822   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2823 }
2824 
2825 
2826 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2827   assert(!tmp->is_valid(), "don't need temporary");
2828 
2829   CodeBlob *cb = CodeCache::find_blob(dest);
2830   if (cb) {
2831     __ far_call(RuntimeAddress(dest));
2832   } else {
2833     __ mov(rscratch1, RuntimeAddress(dest));
2834     __ blr(rscratch1);
2835   }
2836 
2837   if (info != NULL) {
2838     add_call_info_here(info);
2839   }
2840   __ maybe_isb();
2841 }




2801   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2802 
2803   if (left->is_single_cpu()) {
2804     assert(dest->is_single_cpu(), "expect single result reg");
2805     __ negw(dest->as_register(), left->as_register());
2806   } else if (left->is_double_cpu()) {
2807     assert(dest->is_double_cpu(), "expect double result reg");
2808     __ neg(dest->as_register_lo(), left->as_register_lo());
2809   } else if (left->is_single_fpu()) {
2810     assert(dest->is_single_fpu(), "expect single float result reg");
2811     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2812   } else {
2813     assert(left->is_double_fpu(), "expect double float operand reg");
2814     assert(dest->is_double_fpu(), "expect double float result reg");
2815     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2816   }
2817 }
2818 
2819 
2820 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2821   if (patch_code != lir_patch_none) {
2822     deoptimize_trap(info);
2823     return;
2824   }
2825 
2826   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2827 }
2828 
2829 
2830 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2831   assert(!tmp->is_valid(), "don't need temporary");
2832 
2833   CodeBlob *cb = CodeCache::find_blob(dest);
2834   if (cb) {
2835     __ far_call(RuntimeAddress(dest));
2836   } else {
2837     __ mov(rscratch1, RuntimeAddress(dest));
2838     __ blr(rscratch1);
2839   }
2840 
2841   if (info != NULL) {
2842     add_call_info_here(info);
2843   }
2844   __ maybe_isb();
2845 }


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