1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "memory/allocation.inline.hpp"
  27 #include "memory/resourceArea.hpp"
  28 #include "opto/ad.hpp"
  29 #include "opto/addnode.hpp"
  30 #include "opto/callnode.hpp"
  31 #include "opto/idealGraphPrinter.hpp"
  32 #include "opto/matcher.hpp"
  33 #include "opto/memnode.hpp"
  34 #include "opto/movenode.hpp"
  35 #include "opto/opcodes.hpp"
  36 #include "opto/regmask.hpp"
  37 #include "opto/rootnode.hpp"
  38 #include "opto/runtime.hpp"
  39 #include "opto/type.hpp"
  40 #include "opto/vectornode.hpp"
  41 #include "runtime/os.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "utilities/align.hpp"
  44 #if INCLUDE_ZGC
  45 #include "gc/z/zBarrierSetRuntime.hpp"
  46 #endif // INCLUDE_ZGC
  47 
  48 OptoReg::Name OptoReg::c_frame_pointer;
  49 
  50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
  51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
  52 RegMask Matcher::STACK_ONLY_mask;
  53 RegMask Matcher::c_frame_ptr_mask;
  54 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
  55 const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
  56 
  57 //---------------------------Matcher-------------------------------------------
  58 Matcher::Matcher()
  59 : PhaseTransform( Phase::Ins_Select ),
  60 #ifdef ASSERT
  61   _old2new_map(C->comp_arena()),
  62   _new2old_map(C->comp_arena()),
  63 #endif
  64   _shared_nodes(C->comp_arena()),
  65   _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
  66   _swallowed(swallowed),
  67   _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
  68   _end_inst_chain_rule(_END_INST_CHAIN_RULE),
  69   _must_clone(must_clone),
  70   _register_save_policy(register_save_policy),
  71   _c_reg_save_policy(c_reg_save_policy),
  72   _register_save_type(register_save_type),
  73   _ruleName(ruleName),
  74   _allocation_started(false),
  75   _states_arena(Chunk::medium_size, mtCompiler),
  76   _visited(&_states_arena),
  77   _shared(&_states_arena),
  78   _dontcare(&_states_arena) {
  79   C->set_matcher(this);
  80 
  81   idealreg2spillmask  [Op_RegI] = NULL;
  82   idealreg2spillmask  [Op_RegN] = NULL;
  83   idealreg2spillmask  [Op_RegL] = NULL;
  84   idealreg2spillmask  [Op_RegF] = NULL;
  85   idealreg2spillmask  [Op_RegD] = NULL;
  86   idealreg2spillmask  [Op_RegP] = NULL;
  87   idealreg2spillmask  [Op_VecS] = NULL;
  88   idealreg2spillmask  [Op_VecD] = NULL;
  89   idealreg2spillmask  [Op_VecX] = NULL;
  90   idealreg2spillmask  [Op_VecY] = NULL;
  91   idealreg2spillmask  [Op_VecZ] = NULL;
  92   idealreg2spillmask  [Op_RegFlags] = NULL;
  93 
  94   idealreg2debugmask  [Op_RegI] = NULL;
  95   idealreg2debugmask  [Op_RegN] = NULL;
  96   idealreg2debugmask  [Op_RegL] = NULL;
  97   idealreg2debugmask  [Op_RegF] = NULL;
  98   idealreg2debugmask  [Op_RegD] = NULL;
  99   idealreg2debugmask  [Op_RegP] = NULL;
 100   idealreg2debugmask  [Op_VecS] = NULL;
 101   idealreg2debugmask  [Op_VecD] = NULL;
 102   idealreg2debugmask  [Op_VecX] = NULL;
 103   idealreg2debugmask  [Op_VecY] = NULL;
 104   idealreg2debugmask  [Op_VecZ] = NULL;
 105   idealreg2debugmask  [Op_RegFlags] = NULL;
 106 
 107   idealreg2mhdebugmask[Op_RegI] = NULL;
 108   idealreg2mhdebugmask[Op_RegN] = NULL;
 109   idealreg2mhdebugmask[Op_RegL] = NULL;
 110   idealreg2mhdebugmask[Op_RegF] = NULL;
 111   idealreg2mhdebugmask[Op_RegD] = NULL;
 112   idealreg2mhdebugmask[Op_RegP] = NULL;
 113   idealreg2mhdebugmask[Op_VecS] = NULL;
 114   idealreg2mhdebugmask[Op_VecD] = NULL;
 115   idealreg2mhdebugmask[Op_VecX] = NULL;
 116   idealreg2mhdebugmask[Op_VecY] = NULL;
 117   idealreg2mhdebugmask[Op_VecZ] = NULL;
 118   idealreg2mhdebugmask[Op_RegFlags] = NULL;
 119 
 120   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
 121 }
 122 
 123 //------------------------------warp_incoming_stk_arg------------------------
 124 // This warps a VMReg into an OptoReg::Name
 125 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
 126   OptoReg::Name warped;
 127   if( reg->is_stack() ) {  // Stack slot argument?
 128     warped = OptoReg::add(_old_SP, reg->reg2stack() );
 129     warped = OptoReg::add(warped, C->out_preserve_stack_slots());
 130     if( warped >= _in_arg_limit )
 131       _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
 132     if (!RegMask::can_represent_arg(warped)) {
 133       // the compiler cannot represent this method's calling sequence
 134       C->record_method_not_compilable("unsupported incoming calling sequence");
 135       return OptoReg::Bad;
 136     }
 137     return warped;
 138   }
 139   return OptoReg::as_OptoReg(reg);
 140 }
 141 
 142 //---------------------------compute_old_SP------------------------------------
 143 OptoReg::Name Compile::compute_old_SP() {
 144   int fixed    = fixed_slots();
 145   int preserve = in_preserve_stack_slots();
 146   return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
 147 }
 148 
 149 
 150 
 151 #ifdef ASSERT
 152 void Matcher::verify_new_nodes_only(Node* xroot) {
 153   // Make sure that the new graph only references new nodes
 154   ResourceMark rm;
 155   Unique_Node_List worklist;
 156   VectorSet visited(Thread::current()->resource_area());
 157   worklist.push(xroot);
 158   while (worklist.size() > 0) {
 159     Node* n = worklist.pop();
 160     visited <<= n->_idx;
 161     assert(C->node_arena()->contains(n), "dead node");
 162     for (uint j = 0; j < n->req(); j++) {
 163       Node* in = n->in(j);
 164       if (in != NULL) {
 165         assert(C->node_arena()->contains(in), "dead node");
 166         if (!visited.test(in->_idx)) {
 167           worklist.push(in);
 168         }
 169       }
 170     }
 171   }
 172 }
 173 #endif
 174 
 175 
 176 //---------------------------match---------------------------------------------
 177 void Matcher::match( ) {
 178   if( MaxLabelRootDepth < 100 ) { // Too small?
 179     assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
 180     MaxLabelRootDepth = 100;
 181   }
 182   // One-time initialization of some register masks.
 183   init_spill_mask( C->root()->in(1) );
 184   _return_addr_mask = return_addr();
 185 #ifdef _LP64
 186   // Pointers take 2 slots in 64-bit land
 187   _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
 188 #endif
 189 
 190   // Map a Java-signature return type into return register-value
 191   // machine registers for 0, 1 and 2 returned values.
 192   const TypeTuple *range = C->tf()->range();
 193   if( range->cnt() > TypeFunc::Parms ) { // If not a void function
 194     // Get ideal-register return type
 195     uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
 196     // Get machine return register
 197     uint sop = C->start()->Opcode();
 198     OptoRegPair regs = return_value(ireg, false);
 199 
 200     // And mask for same
 201     _return_value_mask = RegMask(regs.first());
 202     if( OptoReg::is_valid(regs.second()) )
 203       _return_value_mask.Insert(regs.second());
 204   }
 205 
 206   // ---------------
 207   // Frame Layout
 208 
 209   // Need the method signature to determine the incoming argument types,
 210   // because the types determine which registers the incoming arguments are
 211   // in, and this affects the matched code.
 212   const TypeTuple *domain = C->tf()->domain();
 213   uint             argcnt = domain->cnt() - TypeFunc::Parms;
 214   BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
 215   VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
 216   _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
 217   _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
 218   uint i;
 219   for( i = 0; i<argcnt; i++ ) {
 220     sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
 221   }
 222 
 223   // Pass array of ideal registers and length to USER code (from the AD file)
 224   // that will convert this to an array of register numbers.
 225   const StartNode *start = C->start();
 226   start->calling_convention( sig_bt, vm_parm_regs, argcnt );
 227 #ifdef ASSERT
 228   // Sanity check users' calling convention.  Real handy while trying to
 229   // get the initial port correct.
 230   { for (uint i = 0; i<argcnt; i++) {
 231       if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 232         assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
 233         _parm_regs[i].set_bad();
 234         continue;
 235       }
 236       VMReg parm_reg = vm_parm_regs[i].first();
 237       assert(parm_reg->is_valid(), "invalid arg?");
 238       if (parm_reg->is_reg()) {
 239         OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
 240         assert(can_be_java_arg(opto_parm_reg) ||
 241                C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
 242                opto_parm_reg == inline_cache_reg(),
 243                "parameters in register must be preserved by runtime stubs");
 244       }
 245       for (uint j = 0; j < i; j++) {
 246         assert(parm_reg != vm_parm_regs[j].first(),
 247                "calling conv. must produce distinct regs");
 248       }
 249     }
 250   }
 251 #endif
 252 
 253   // Do some initial frame layout.
 254 
 255   // Compute the old incoming SP (may be called FP) as
 256   //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
 257   _old_SP = C->compute_old_SP();
 258   assert( is_even(_old_SP), "must be even" );
 259 
 260   // Compute highest incoming stack argument as
 261   //   _old_SP + out_preserve_stack_slots + incoming argument size.
 262   _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 263   assert( is_even(_in_arg_limit), "out_preserve must be even" );
 264   for( i = 0; i < argcnt; i++ ) {
 265     // Permit args to have no register
 266     _calling_convention_mask[i].Clear();
 267     if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 268       continue;
 269     }
 270     // calling_convention returns stack arguments as a count of
 271     // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
 272     // the allocators point of view, taking into account all the
 273     // preserve area, locks & pad2.
 274 
 275     OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
 276     if( OptoReg::is_valid(reg1))
 277       _calling_convention_mask[i].Insert(reg1);
 278 
 279     OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
 280     if( OptoReg::is_valid(reg2))
 281       _calling_convention_mask[i].Insert(reg2);
 282 
 283     // Saved biased stack-slot register number
 284     _parm_regs[i].set_pair(reg2, reg1);
 285   }
 286 
 287   // Finally, make sure the incoming arguments take up an even number of
 288   // words, in case the arguments or locals need to contain doubleword stack
 289   // slots.  The rest of the system assumes that stack slot pairs (in
 290   // particular, in the spill area) which look aligned will in fact be
 291   // aligned relative to the stack pointer in the target machine.  Double
 292   // stack slots will always be allocated aligned.
 293   _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
 294 
 295   // Compute highest outgoing stack argument as
 296   //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
 297   _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
 298   assert( is_even(_out_arg_limit), "out_preserve must be even" );
 299 
 300   if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
 301     // the compiler cannot represent this method's calling sequence
 302     C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
 303   }
 304 
 305   if (C->failing())  return;  // bailed out on incoming arg failure
 306 
 307   // ---------------
 308   // Collect roots of matcher trees.  Every node for which
 309   // _shared[_idx] is cleared is guaranteed to not be shared, and thus
 310   // can be a valid interior of some tree.
 311   find_shared( C->root() );
 312   find_shared( C->top() );
 313 
 314   C->print_method(PHASE_BEFORE_MATCHING);
 315 
 316   // Create new ideal node ConP #NULL even if it does exist in old space
 317   // to avoid false sharing if the corresponding mach node is not used.
 318   // The corresponding mach node is only used in rare cases for derived
 319   // pointers.
 320   Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
 321 
 322   // Swap out to old-space; emptying new-space
 323   Arena *old = C->node_arena()->move_contents(C->old_arena());
 324 
 325   // Save debug and profile information for nodes in old space:
 326   _old_node_note_array = C->node_note_array();
 327   if (_old_node_note_array != NULL) {
 328     C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
 329                            (C->comp_arena(), _old_node_note_array->length(),
 330                             0, NULL));
 331   }
 332 
 333   // Pre-size the new_node table to avoid the need for range checks.
 334   grow_new_node_array(C->unique());
 335 
 336   // Reset node counter so MachNodes start with _idx at 0
 337   int live_nodes = C->live_nodes();
 338   C->set_unique(0);
 339   C->reset_dead_node_list();
 340 
 341   // Recursively match trees from old space into new space.
 342   // Correct leaves of new-space Nodes; they point to old-space.
 343   _visited.Clear();             // Clear visit bits for xform call
 344   C->set_cached_top_node(xform( C->top(), live_nodes ));
 345   if (!C->failing()) {
 346     Node* xroot =        xform( C->root(), 1 );
 347     if (xroot == NULL) {
 348       Matcher::soft_match_failure();  // recursive matching process failed
 349       C->record_method_not_compilable("instruction match failed");
 350     } else {
 351       // During matching shared constants were attached to C->root()
 352       // because xroot wasn't available yet, so transfer the uses to
 353       // the xroot.
 354       for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
 355         Node* n = C->root()->fast_out(j);
 356         if (C->node_arena()->contains(n)) {
 357           assert(n->in(0) == C->root(), "should be control user");
 358           n->set_req(0, xroot);
 359           --j;
 360           --jmax;
 361         }
 362       }
 363 
 364       // Generate new mach node for ConP #NULL
 365       assert(new_ideal_null != NULL, "sanity");
 366       _mach_null = match_tree(new_ideal_null);
 367       // Don't set control, it will confuse GCM since there are no uses.
 368       // The control will be set when this node is used first time
 369       // in find_base_for_derived().
 370       assert(_mach_null != NULL, "");
 371 
 372       C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
 373 
 374 #ifdef ASSERT
 375       verify_new_nodes_only(xroot);
 376 #endif
 377     }
 378   }
 379   if (C->top() == NULL || C->root() == NULL) {
 380     C->record_method_not_compilable("graph lost"); // %%% cannot happen?
 381   }
 382   if (C->failing()) {
 383     // delete old;
 384     old->destruct_contents();
 385     return;
 386   }
 387   assert( C->top(), "" );
 388   assert( C->root(), "" );
 389   validate_null_checks();
 390 
 391   // Now smoke old-space
 392   NOT_DEBUG( old->destruct_contents() );
 393 
 394   // ------------------------
 395   // Set up save-on-entry registers
 396   Fixup_Save_On_Entry( );
 397 }
 398 
 399 
 400 //------------------------------Fixup_Save_On_Entry----------------------------
 401 // The stated purpose of this routine is to take care of save-on-entry
 402 // registers.  However, the overall goal of the Match phase is to convert into
 403 // machine-specific instructions which have RegMasks to guide allocation.
 404 // So what this procedure really does is put a valid RegMask on each input
 405 // to the machine-specific variations of all Return, TailCall and Halt
 406 // instructions.  It also adds edgs to define the save-on-entry values (and of
 407 // course gives them a mask).
 408 
 409 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
 410   RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
 411   // Do all the pre-defined register masks
 412   rms[TypeFunc::Control  ] = RegMask::Empty;
 413   rms[TypeFunc::I_O      ] = RegMask::Empty;
 414   rms[TypeFunc::Memory   ] = RegMask::Empty;
 415   rms[TypeFunc::ReturnAdr] = ret_adr;
 416   rms[TypeFunc::FramePtr ] = fp;
 417   return rms;
 418 }
 419 
 420 //---------------------------init_first_stack_mask-----------------------------
 421 // Create the initial stack mask used by values spilling to the stack.
 422 // Disallow any debug info in outgoing argument areas by setting the
 423 // initial mask accordingly.
 424 void Matcher::init_first_stack_mask() {
 425 
 426   // Allocate storage for spill masks as masks for the appropriate load type.
 427   RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
 428 
 429   idealreg2spillmask  [Op_RegN] = &rms[0];
 430   idealreg2spillmask  [Op_RegI] = &rms[1];
 431   idealreg2spillmask  [Op_RegL] = &rms[2];
 432   idealreg2spillmask  [Op_RegF] = &rms[3];
 433   idealreg2spillmask  [Op_RegD] = &rms[4];
 434   idealreg2spillmask  [Op_RegP] = &rms[5];
 435 
 436   idealreg2debugmask  [Op_RegN] = &rms[6];
 437   idealreg2debugmask  [Op_RegI] = &rms[7];
 438   idealreg2debugmask  [Op_RegL] = &rms[8];
 439   idealreg2debugmask  [Op_RegF] = &rms[9];
 440   idealreg2debugmask  [Op_RegD] = &rms[10];
 441   idealreg2debugmask  [Op_RegP] = &rms[11];
 442 
 443   idealreg2mhdebugmask[Op_RegN] = &rms[12];
 444   idealreg2mhdebugmask[Op_RegI] = &rms[13];
 445   idealreg2mhdebugmask[Op_RegL] = &rms[14];
 446   idealreg2mhdebugmask[Op_RegF] = &rms[15];
 447   idealreg2mhdebugmask[Op_RegD] = &rms[16];
 448   idealreg2mhdebugmask[Op_RegP] = &rms[17];
 449 
 450   idealreg2spillmask  [Op_VecS] = &rms[18];
 451   idealreg2spillmask  [Op_VecD] = &rms[19];
 452   idealreg2spillmask  [Op_VecX] = &rms[20];
 453   idealreg2spillmask  [Op_VecY] = &rms[21];
 454   idealreg2spillmask  [Op_VecZ] = &rms[22];
 455 
 456   OptoReg::Name i;
 457 
 458   // At first, start with the empty mask
 459   C->FIRST_STACK_mask().Clear();
 460 
 461   // Add in the incoming argument area
 462   OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 463   for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
 464     C->FIRST_STACK_mask().Insert(i);
 465   }
 466   // Add in all bits past the outgoing argument area
 467   guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
 468             "must be able to represent all call arguments in reg mask");
 469   OptoReg::Name init = _out_arg_limit;
 470   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
 471     C->FIRST_STACK_mask().Insert(i);
 472   }
 473   // Finally, set the "infinite stack" bit.
 474   C->FIRST_STACK_mask().set_AllStack();
 475 
 476   // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
 477   RegMask aligned_stack_mask = C->FIRST_STACK_mask();
 478   // Keep spill masks aligned.
 479   aligned_stack_mask.clear_to_pairs();
 480   assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 481 
 482   *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
 483 #ifdef _LP64
 484   *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
 485    idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
 486    idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
 487 #else
 488    idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
 489 #endif
 490   *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
 491    idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
 492   *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
 493    idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
 494   *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
 495    idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
 496   *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
 497    idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
 498 
 499   if (Matcher::vector_size_supported(T_BYTE,4)) {
 500     *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
 501      idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
 502   }
 503   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 504     // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
 505     // RA guarantees such alignment since it is needed for Double and Long values.
 506     *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
 507      idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
 508   }
 509   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 510     // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
 511     //
 512     // RA can use input arguments stack slots for spills but until RA
 513     // we don't know frame size and offset of input arg stack slots.
 514     //
 515     // Exclude last input arg stack slots to avoid spilling vectors there
 516     // otherwise vector spills could stomp over stack slots in caller frame.
 517     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 518     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
 519       aligned_stack_mask.Remove(in);
 520       in = OptoReg::add(in, -1);
 521     }
 522      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
 523      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 524     *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
 525      idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
 526   }
 527   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 528     // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
 529     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 530     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
 531       aligned_stack_mask.Remove(in);
 532       in = OptoReg::add(in, -1);
 533     }
 534      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
 535      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 536     *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
 537      idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
 538   }
 539   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 540     // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
 541     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 542     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
 543       aligned_stack_mask.Remove(in);
 544       in = OptoReg::add(in, -1);
 545     }
 546      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
 547      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 548     *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
 549      idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
 550   }
 551    if (UseFPUForSpilling) {
 552      // This mask logic assumes that the spill operations are
 553      // symmetric and that the registers involved are the same size.
 554      // On sparc for instance we may have to use 64 bit moves will
 555      // kill 2 registers when used with F0-F31.
 556      idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
 557      idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
 558 #ifdef _LP64
 559      idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
 560      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 561      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 562      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
 563 #else
 564      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
 565 #ifdef ARM
 566      // ARM has support for moving 64bit values between a pair of
 567      // integer registers and a double register
 568      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 569      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 570 #endif
 571 #endif
 572    }
 573 
 574   // Make up debug masks.  Any spill slot plus callee-save registers.
 575   // Caller-save registers are assumed to be trashable by the various
 576   // inline-cache fixup routines.
 577   *idealreg2debugmask  [Op_RegN]= *idealreg2spillmask[Op_RegN];
 578   *idealreg2debugmask  [Op_RegI]= *idealreg2spillmask[Op_RegI];
 579   *idealreg2debugmask  [Op_RegL]= *idealreg2spillmask[Op_RegL];
 580   *idealreg2debugmask  [Op_RegF]= *idealreg2spillmask[Op_RegF];
 581   *idealreg2debugmask  [Op_RegD]= *idealreg2spillmask[Op_RegD];
 582   *idealreg2debugmask  [Op_RegP]= *idealreg2spillmask[Op_RegP];
 583 
 584   *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
 585   *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
 586   *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
 587   *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
 588   *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
 589   *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
 590 
 591   // Prevent stub compilations from attempting to reference
 592   // callee-saved registers from debug info
 593   bool exclude_soe = !Compile::current()->is_method_compilation();
 594 
 595   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 596     // registers the caller has to save do not work
 597     if( _register_save_policy[i] == 'C' ||
 598         _register_save_policy[i] == 'A' ||
 599         (_register_save_policy[i] == 'E' && exclude_soe) ) {
 600       idealreg2debugmask  [Op_RegN]->Remove(i);
 601       idealreg2debugmask  [Op_RegI]->Remove(i); // Exclude save-on-call
 602       idealreg2debugmask  [Op_RegL]->Remove(i); // registers from debug
 603       idealreg2debugmask  [Op_RegF]->Remove(i); // masks
 604       idealreg2debugmask  [Op_RegD]->Remove(i);
 605       idealreg2debugmask  [Op_RegP]->Remove(i);
 606 
 607       idealreg2mhdebugmask[Op_RegN]->Remove(i);
 608       idealreg2mhdebugmask[Op_RegI]->Remove(i);
 609       idealreg2mhdebugmask[Op_RegL]->Remove(i);
 610       idealreg2mhdebugmask[Op_RegF]->Remove(i);
 611       idealreg2mhdebugmask[Op_RegD]->Remove(i);
 612       idealreg2mhdebugmask[Op_RegP]->Remove(i);
 613     }
 614   }
 615 
 616   // Subtract the register we use to save the SP for MethodHandle
 617   // invokes to from the debug mask.
 618   const RegMask save_mask = method_handle_invoke_SP_save_mask();
 619   idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
 620   idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
 621   idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
 622   idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
 623   idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
 624   idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
 625 }
 626 
 627 //---------------------------is_save_on_entry----------------------------------
 628 bool Matcher::is_save_on_entry( int reg ) {
 629   return
 630     _register_save_policy[reg] == 'E' ||
 631     _register_save_policy[reg] == 'A' || // Save-on-entry register?
 632     // Also save argument registers in the trampolining stubs
 633     (C->save_argument_registers() && is_spillable_arg(reg));
 634 }
 635 
 636 //---------------------------Fixup_Save_On_Entry-------------------------------
 637 void Matcher::Fixup_Save_On_Entry( ) {
 638   init_first_stack_mask();
 639 
 640   Node *root = C->root();       // Short name for root
 641   // Count number of save-on-entry registers.
 642   uint soe_cnt = number_of_saved_registers();
 643   uint i;
 644 
 645   // Find the procedure Start Node
 646   StartNode *start = C->start();
 647   assert( start, "Expect a start node" );
 648 
 649   // Save argument registers in the trampolining stubs
 650   if( C->save_argument_registers() )
 651     for( i = 0; i < _last_Mach_Reg; i++ )
 652       if( is_spillable_arg(i) )
 653         soe_cnt++;
 654 
 655   // Input RegMask array shared by all Returns.
 656   // The type for doubles and longs has a count of 2, but
 657   // there is only 1 returned value
 658   uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
 659   RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 660   // Returns have 0 or 1 returned values depending on call signature.
 661   // Return register is specified by return_value in the AD file.
 662   if (ret_edge_cnt > TypeFunc::Parms)
 663     ret_rms[TypeFunc::Parms+0] = _return_value_mask;
 664 
 665   // Input RegMask array shared by all Rethrows.
 666   uint reth_edge_cnt = TypeFunc::Parms+1;
 667   RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 668   // Rethrow takes exception oop only, but in the argument 0 slot.
 669   OptoReg::Name reg = find_receiver(false);
 670   if (reg >= 0) {
 671     reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
 672 #ifdef _LP64
 673     // Need two slots for ptrs in 64-bit land
 674     reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
 675 #endif
 676   }
 677 
 678   // Input RegMask array shared by all TailCalls
 679   uint tail_call_edge_cnt = TypeFunc::Parms+2;
 680   RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 681 
 682   // Input RegMask array shared by all TailJumps
 683   uint tail_jump_edge_cnt = TypeFunc::Parms+2;
 684   RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 685 
 686   // TailCalls have 2 returned values (target & moop), whose masks come
 687   // from the usual MachNode/MachOper mechanism.  Find a sample
 688   // TailCall to extract these masks and put the correct masks into
 689   // the tail_call_rms array.
 690   for( i=1; i < root->req(); i++ ) {
 691     MachReturnNode *m = root->in(i)->as_MachReturn();
 692     if( m->ideal_Opcode() == Op_TailCall ) {
 693       tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 694       tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 695       break;
 696     }
 697   }
 698 
 699   // TailJumps have 2 returned values (target & ex_oop), whose masks come
 700   // from the usual MachNode/MachOper mechanism.  Find a sample
 701   // TailJump to extract these masks and put the correct masks into
 702   // the tail_jump_rms array.
 703   for( i=1; i < root->req(); i++ ) {
 704     MachReturnNode *m = root->in(i)->as_MachReturn();
 705     if( m->ideal_Opcode() == Op_TailJump ) {
 706       tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 707       tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 708       break;
 709     }
 710   }
 711 
 712   // Input RegMask array shared by all Halts
 713   uint halt_edge_cnt = TypeFunc::Parms;
 714   RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 715 
 716   // Capture the return input masks into each exit flavor
 717   for( i=1; i < root->req(); i++ ) {
 718     MachReturnNode *exit = root->in(i)->as_MachReturn();
 719     switch( exit->ideal_Opcode() ) {
 720       case Op_Return   : exit->_in_rms = ret_rms;  break;
 721       case Op_Rethrow  : exit->_in_rms = reth_rms; break;
 722       case Op_TailCall : exit->_in_rms = tail_call_rms; break;
 723       case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
 724       case Op_Halt     : exit->_in_rms = halt_rms; break;
 725       default          : ShouldNotReachHere();
 726     }
 727   }
 728 
 729   // Next unused projection number from Start.
 730   int proj_cnt = C->tf()->domain()->cnt();
 731 
 732   // Do all the save-on-entry registers.  Make projections from Start for
 733   // them, and give them a use at the exit points.  To the allocator, they
 734   // look like incoming register arguments.
 735   for( i = 0; i < _last_Mach_Reg; i++ ) {
 736     if( is_save_on_entry(i) ) {
 737 
 738       // Add the save-on-entry to the mask array
 739       ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
 740       reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
 741       tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
 742       tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
 743       // Halts need the SOE registers, but only in the stack as debug info.
 744       // A just-prior uncommon-trap or deoptimization will use the SOE regs.
 745       halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
 746 
 747       Node *mproj;
 748 
 749       // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
 750       // into a single RegD.
 751       if( (i&1) == 0 &&
 752           _register_save_type[i  ] == Op_RegF &&
 753           _register_save_type[i+1] == Op_RegF &&
 754           is_save_on_entry(i+1) ) {
 755         // Add other bit for double
 756         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 757         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 758         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 759         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 760         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 761         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
 762         proj_cnt += 2;          // Skip 2 for doubles
 763       }
 764       else if( (i&1) == 1 &&    // Else check for high half of double
 765                _register_save_type[i-1] == Op_RegF &&
 766                _register_save_type[i  ] == Op_RegF &&
 767                is_save_on_entry(i-1) ) {
 768         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 769         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 770         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 771         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 772         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 773         mproj = C->top();
 774       }
 775       // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
 776       // into a single RegL.
 777       else if( (i&1) == 0 &&
 778           _register_save_type[i  ] == Op_RegI &&
 779           _register_save_type[i+1] == Op_RegI &&
 780         is_save_on_entry(i+1) ) {
 781         // Add other bit for long
 782         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 783         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 784         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 785         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 786         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 787         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
 788         proj_cnt += 2;          // Skip 2 for longs
 789       }
 790       else if( (i&1) == 1 &&    // Else check for high half of long
 791                _register_save_type[i-1] == Op_RegI &&
 792                _register_save_type[i  ] == Op_RegI &&
 793                is_save_on_entry(i-1) ) {
 794         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 795         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 796         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 797         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 798         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 799         mproj = C->top();
 800       } else {
 801         // Make a projection for it off the Start
 802         mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
 803       }
 804 
 805       ret_edge_cnt ++;
 806       reth_edge_cnt ++;
 807       tail_call_edge_cnt ++;
 808       tail_jump_edge_cnt ++;
 809       halt_edge_cnt ++;
 810 
 811       // Add a use of the SOE register to all exit paths
 812       for( uint j=1; j < root->req(); j++ )
 813         root->in(j)->add_req(mproj);
 814     } // End of if a save-on-entry register
 815   } // End of for all machine registers
 816 }
 817 
 818 //------------------------------init_spill_mask--------------------------------
 819 void Matcher::init_spill_mask( Node *ret ) {
 820   if( idealreg2regmask[Op_RegI] ) return; // One time only init
 821 
 822   OptoReg::c_frame_pointer = c_frame_pointer();
 823   c_frame_ptr_mask = c_frame_pointer();
 824 #ifdef _LP64
 825   // pointers are twice as big
 826   c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
 827 #endif
 828 
 829   // Start at OptoReg::stack0()
 830   STACK_ONLY_mask.Clear();
 831   OptoReg::Name init = OptoReg::stack2reg(0);
 832   // STACK_ONLY_mask is all stack bits
 833   OptoReg::Name i;
 834   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
 835     STACK_ONLY_mask.Insert(i);
 836   // Also set the "infinite stack" bit.
 837   STACK_ONLY_mask.set_AllStack();
 838 
 839   // Copy the register names over into the shared world
 840   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 841     // SharedInfo::regName[i] = regName[i];
 842     // Handy RegMasks per machine register
 843     mreg2regmask[i].Insert(i);
 844   }
 845 
 846   // Grab the Frame Pointer
 847   Node *fp  = ret->in(TypeFunc::FramePtr);
 848   Node *mem = ret->in(TypeFunc::Memory);
 849   const TypePtr* atp = TypePtr::BOTTOM;
 850   // Share frame pointer while making spill ops
 851   set_shared(fp);
 852 
 853   // Compute generic short-offset Loads
 854 #ifdef _LP64
 855   MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 856 #endif
 857   MachNode *spillI  = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
 858   MachNode *spillL  = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
 859   MachNode *spillF  = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
 860   MachNode *spillD  = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
 861   MachNode *spillP  = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 862   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 863          spillD != NULL && spillP != NULL, "");
 864   // Get the ADLC notion of the right regmask, for each basic type.
 865 #ifdef _LP64
 866   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 867 #endif
 868   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 869   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 870   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 871   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 872   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 873 
 874   // Vector regmasks.
 875   if (Matcher::vector_size_supported(T_BYTE,4)) {
 876     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 877     MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 878     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 879   }
 880   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 881     MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 882     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 883   }
 884   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 885     MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
 886     idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
 887   }
 888   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 889     MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
 890     idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
 891   }
 892   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 893     MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
 894     idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
 895   }
 896 }
 897 
 898 #ifdef ASSERT
 899 static void match_alias_type(Compile* C, Node* n, Node* m) {
 900   if (!VerifyAliases)  return;  // do not go looking for trouble by default
 901   const TypePtr* nat = n->adr_type();
 902   const TypePtr* mat = m->adr_type();
 903   int nidx = C->get_alias_index(nat);
 904   int midx = C->get_alias_index(mat);
 905   // Detune the assert for cases like (AndI 0xFF (LoadB p)).
 906   if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
 907     for (uint i = 1; i < n->req(); i++) {
 908       Node* n1 = n->in(i);
 909       const TypePtr* n1at = n1->adr_type();
 910       if (n1at != NULL) {
 911         nat = n1at;
 912         nidx = C->get_alias_index(n1at);
 913       }
 914     }
 915   }
 916   // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
 917   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
 918     switch (n->Opcode()) {
 919     case Op_PrefetchAllocation:
 920       nidx = Compile::AliasIdxRaw;
 921       nat = TypeRawPtr::BOTTOM;
 922       break;
 923     }
 924   }
 925   if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
 926     switch (n->Opcode()) {
 927     case Op_ClearArray:
 928       midx = Compile::AliasIdxRaw;
 929       mat = TypeRawPtr::BOTTOM;
 930       break;
 931     }
 932   }
 933   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
 934     switch (n->Opcode()) {
 935     case Op_Return:
 936     case Op_Rethrow:
 937     case Op_Halt:
 938     case Op_TailCall:
 939     case Op_TailJump:
 940       nidx = Compile::AliasIdxBot;
 941       nat = TypePtr::BOTTOM;
 942       break;
 943     }
 944   }
 945   if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
 946     switch (n->Opcode()) {
 947     case Op_StrComp:
 948     case Op_StrEquals:
 949     case Op_StrIndexOf:
 950     case Op_StrIndexOfChar:
 951     case Op_AryEq:
 952     case Op_HasNegatives:
 953     case Op_MemBarVolatile:
 954     case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
 955     case Op_StrInflatedCopy:
 956     case Op_StrCompressedCopy:
 957     case Op_OnSpinWait:
 958     case Op_EncodeISOArray:
 959       nidx = Compile::AliasIdxTop;
 960       nat = NULL;
 961       break;
 962     }
 963   }
 964   if (nidx != midx) {
 965     if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
 966       tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
 967       n->dump();
 968       m->dump();
 969     }
 970     assert(C->subsume_loads() && C->must_alias(nat, midx),
 971            "must not lose alias info when matching");
 972   }
 973 }
 974 #endif
 975 
 976 //------------------------------xform------------------------------------------
 977 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
 978 // Node in new-space.  Given a new-space Node, recursively walk his children.
 979 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
 980 Node *Matcher::xform( Node *n, int max_stack ) {
 981   // Use one stack to keep both: child's node/state and parent's node/index
 982   MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
 983   mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
 984   while (mstack.is_nonempty()) {
 985     C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
 986     if (C->failing()) return NULL;
 987     n = mstack.node();          // Leave node on stack
 988     Node_State nstate = mstack.state();
 989     if (nstate == Visit) {
 990       mstack.set_state(Post_Visit);
 991       Node *oldn = n;
 992       // Old-space or new-space check
 993       if (!C->node_arena()->contains(n)) {
 994         // Old space!
 995         Node* m;
 996         if (has_new_node(n)) {  // Not yet Label/Reduced
 997           m = new_node(n);
 998         } else {
 999           if (!is_dontcare(n)) { // Matcher can match this guy
1000             // Calls match special.  They match alone with no children.
1001             // Their children, the incoming arguments, match normally.
1002             m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1003             if (C->failing())  return NULL;
1004             if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1005           } else {                  // Nothing the matcher cares about
1006             if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) {       // Projections?
1007               // Convert to machine-dependent projection
1008               m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1009 #ifdef ASSERT
1010               _new2old_map.map(m->_idx, n);
1011 #endif
1012               if (m->in(0) != NULL) // m might be top
1013                 collect_null_checks(m, n);
1014             } else {                // Else just a regular 'ol guy
1015               m = n->clone();       // So just clone into new-space
1016 #ifdef ASSERT
1017               _new2old_map.map(m->_idx, n);
1018 #endif
1019               // Def-Use edges will be added incrementally as Uses
1020               // of this node are matched.
1021               assert(m->outcnt() == 0, "no Uses of this clone yet");
1022             }
1023           }
1024 
1025           set_new_node(n, m);       // Map old to new
1026           if (_old_node_note_array != NULL) {
1027             Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1028                                                   n->_idx);
1029             C->set_node_notes_at(m->_idx, nn);
1030           }
1031           debug_only(match_alias_type(C, n, m));
1032         }
1033         n = m;    // n is now a new-space node
1034         mstack.set_node(n);
1035       }
1036 
1037       // New space!
1038       if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1039 
1040       int i;
1041       // Put precedence edges on stack first (match them last).
1042       for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1043         Node *m = oldn->in(i);
1044         if (m == NULL) break;
1045         // set -1 to call add_prec() instead of set_req() during Step1
1046         mstack.push(m, Visit, n, -1);
1047       }
1048 
1049       // Handle precedence edges for interior nodes
1050       for (i = n->len()-1; (uint)i >= n->req(); i--) {
1051         Node *m = n->in(i);
1052         if (m == NULL || C->node_arena()->contains(m)) continue;
1053         n->rm_prec(i);
1054         // set -1 to call add_prec() instead of set_req() during Step1
1055         mstack.push(m, Visit, n, -1);
1056       }
1057 
1058       // For constant debug info, I'd rather have unmatched constants.
1059       int cnt = n->req();
1060       JVMState* jvms = n->jvms();
1061       int debug_cnt = jvms ? jvms->debug_start() : cnt;
1062 
1063       // Now do only debug info.  Clone constants rather than matching.
1064       // Constants are represented directly in the debug info without
1065       // the need for executable machine instructions.
1066       // Monitor boxes are also represented directly.
1067       for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1068         Node *m = n->in(i);          // Get input
1069         int op = m->Opcode();
1070         assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1071         if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1072             op == Op_ConF || op == Op_ConD || op == Op_ConL
1073             // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
1074             ) {
1075           m = m->clone();
1076 #ifdef ASSERT
1077           _new2old_map.map(m->_idx, n);
1078 #endif
1079           mstack.push(m, Post_Visit, n, i); // Don't need to visit
1080           mstack.push(m->in(0), Visit, m, 0);
1081         } else {
1082           mstack.push(m, Visit, n, i);
1083         }
1084       }
1085 
1086       // And now walk his children, and convert his inputs to new-space.
1087       for( ; i >= 0; --i ) { // For all normal inputs do
1088         Node *m = n->in(i);  // Get input
1089         if(m != NULL)
1090           mstack.push(m, Visit, n, i);
1091       }
1092 
1093     }
1094     else if (nstate == Post_Visit) {
1095       // Set xformed input
1096       Node *p = mstack.parent();
1097       if (p != NULL) { // root doesn't have parent
1098         int i = (int)mstack.index();
1099         if (i >= 0)
1100           p->set_req(i, n); // required input
1101         else if (i == -1)
1102           p->add_prec(n);   // precedence input
1103         else
1104           ShouldNotReachHere();
1105       }
1106       mstack.pop(); // remove processed node from stack
1107     }
1108     else {
1109       ShouldNotReachHere();
1110     }
1111   } // while (mstack.is_nonempty())
1112   return n; // Return new-space Node
1113 }
1114 
1115 //------------------------------warp_outgoing_stk_arg------------------------
1116 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1117   // Convert outgoing argument location to a pre-biased stack offset
1118   if (reg->is_stack()) {
1119     OptoReg::Name warped = reg->reg2stack();
1120     // Adjust the stack slot offset to be the register number used
1121     // by the allocator.
1122     warped = OptoReg::add(begin_out_arg_area, warped);
1123     // Keep track of the largest numbered stack slot used for an arg.
1124     // Largest used slot per call-site indicates the amount of stack
1125     // that is killed by the call.
1126     if( warped >= out_arg_limit_per_call )
1127       out_arg_limit_per_call = OptoReg::add(warped,1);
1128     if (!RegMask::can_represent_arg(warped)) {
1129       C->record_method_not_compilable("unsupported calling sequence");
1130       return OptoReg::Bad;
1131     }
1132     return warped;
1133   }
1134   return OptoReg::as_OptoReg(reg);
1135 }
1136 
1137 
1138 //------------------------------match_sfpt-------------------------------------
1139 // Helper function to match call instructions.  Calls match special.
1140 // They match alone with no children.  Their children, the incoming
1141 // arguments, match normally.
1142 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1143   MachSafePointNode *msfpt = NULL;
1144   MachCallNode      *mcall = NULL;
1145   uint               cnt;
1146   // Split out case for SafePoint vs Call
1147   CallNode *call;
1148   const TypeTuple *domain;
1149   ciMethod*        method = NULL;
1150   bool             is_method_handle_invoke = false;  // for special kill effects
1151   if( sfpt->is_Call() ) {
1152     call = sfpt->as_Call();
1153     domain = call->tf()->domain();
1154     cnt = domain->cnt();
1155 
1156     // Match just the call, nothing else
1157     MachNode *m = match_tree(call);
1158     if (C->failing())  return NULL;
1159     if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1160 
1161     // Copy data from the Ideal SafePoint to the machine version
1162     mcall = m->as_MachCall();
1163 
1164     mcall->set_tf(         call->tf());
1165     mcall->set_entry_point(call->entry_point());
1166     mcall->set_cnt(        call->cnt());
1167 
1168     if( mcall->is_MachCallJava() ) {
1169       MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
1170       const CallJavaNode *call_java =  call->as_CallJava();
1171       assert(call_java->validate_symbolic_info(), "inconsistent info");
1172       method = call_java->method();
1173       mcall_java->_method = method;
1174       mcall_java->_bci = call_java->_bci;
1175       mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1176       is_method_handle_invoke = call_java->is_method_handle_invoke();
1177       mcall_java->_method_handle_invoke = is_method_handle_invoke;
1178       mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1179       if (is_method_handle_invoke) {
1180         C->set_has_method_handle_invokes(true);
1181       }
1182       if( mcall_java->is_MachCallStaticJava() )
1183         mcall_java->as_MachCallStaticJava()->_name =
1184          call_java->as_CallStaticJava()->_name;
1185       if( mcall_java->is_MachCallDynamicJava() )
1186         mcall_java->as_MachCallDynamicJava()->_vtable_index =
1187          call_java->as_CallDynamicJava()->_vtable_index;
1188     }
1189     else if( mcall->is_MachCallRuntime() ) {
1190       mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1191     }
1192     msfpt = mcall;
1193   }
1194   // This is a non-call safepoint
1195   else {
1196     call = NULL;
1197     domain = NULL;
1198     MachNode *mn = match_tree(sfpt);
1199     if (C->failing())  return NULL;
1200     msfpt = mn->as_MachSafePoint();
1201     cnt = TypeFunc::Parms;
1202   }
1203 
1204   // Advertise the correct memory effects (for anti-dependence computation).
1205   msfpt->set_adr_type(sfpt->adr_type());
1206 
1207   // Allocate a private array of RegMasks.  These RegMasks are not shared.
1208   msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1209   // Empty them all.
1210   memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1211 
1212   // Do all the pre-defined non-Empty register masks
1213   msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1214   msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1215 
1216   // Place first outgoing argument can possibly be put.
1217   OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1218   assert( is_even(begin_out_arg_area), "" );
1219   // Compute max outgoing register number per call site.
1220   OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1221   // Calls to C may hammer extra stack slots above and beyond any arguments.
1222   // These are usually backing store for register arguments for varargs.
1223   if( call != NULL && call->is_CallRuntime() )
1224     out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1225 
1226 
1227   // Do the normal argument list (parameters) register masks
1228   int argcnt = cnt - TypeFunc::Parms;
1229   if( argcnt > 0 ) {          // Skip it all if we have no args
1230     BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1231     VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1232     int i;
1233     for( i = 0; i < argcnt; i++ ) {
1234       sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1235     }
1236     // V-call to pick proper calling convention
1237     call->calling_convention( sig_bt, parm_regs, argcnt );
1238 
1239 #ifdef ASSERT
1240     // Sanity check users' calling convention.  Really handy during
1241     // the initial porting effort.  Fairly expensive otherwise.
1242     { for (int i = 0; i<argcnt; i++) {
1243       if( !parm_regs[i].first()->is_valid() &&
1244           !parm_regs[i].second()->is_valid() ) continue;
1245       VMReg reg1 = parm_regs[i].first();
1246       VMReg reg2 = parm_regs[i].second();
1247       for (int j = 0; j < i; j++) {
1248         if( !parm_regs[j].first()->is_valid() &&
1249             !parm_regs[j].second()->is_valid() ) continue;
1250         VMReg reg3 = parm_regs[j].first();
1251         VMReg reg4 = parm_regs[j].second();
1252         if( !reg1->is_valid() ) {
1253           assert( !reg2->is_valid(), "valid halvsies" );
1254         } else if( !reg3->is_valid() ) {
1255           assert( !reg4->is_valid(), "valid halvsies" );
1256         } else {
1257           assert( reg1 != reg2, "calling conv. must produce distinct regs");
1258           assert( reg1 != reg3, "calling conv. must produce distinct regs");
1259           assert( reg1 != reg4, "calling conv. must produce distinct regs");
1260           assert( reg2 != reg3, "calling conv. must produce distinct regs");
1261           assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1262           assert( reg3 != reg4, "calling conv. must produce distinct regs");
1263         }
1264       }
1265     }
1266     }
1267 #endif
1268 
1269     // Visit each argument.  Compute its outgoing register mask.
1270     // Return results now can have 2 bits returned.
1271     // Compute max over all outgoing arguments both per call-site
1272     // and over the entire method.
1273     for( i = 0; i < argcnt; i++ ) {
1274       // Address of incoming argument mask to fill in
1275       RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1276       if( !parm_regs[i].first()->is_valid() &&
1277           !parm_regs[i].second()->is_valid() ) {
1278         continue;               // Avoid Halves
1279       }
1280       // Grab first register, adjust stack slots and insert in mask.
1281       OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1282       if (OptoReg::is_valid(reg1))
1283         rm->Insert( reg1 );
1284       // Grab second register (if any), adjust stack slots and insert in mask.
1285       OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1286       if (OptoReg::is_valid(reg2))
1287         rm->Insert( reg2 );
1288     } // End of for all arguments
1289 
1290     // Compute number of stack slots needed to restore stack in case of
1291     // Pascal-style argument popping.
1292     mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1293   }
1294 
1295   // Compute the max stack slot killed by any call.  These will not be
1296   // available for debug info, and will be used to adjust FIRST_STACK_mask
1297   // after all call sites have been visited.
1298   if( _out_arg_limit < out_arg_limit_per_call)
1299     _out_arg_limit = out_arg_limit_per_call;
1300 
1301   if (mcall) {
1302     // Kill the outgoing argument area, including any non-argument holes and
1303     // any legacy C-killed slots.  Use Fat-Projections to do the killing.
1304     // Since the max-per-method covers the max-per-call-site and debug info
1305     // is excluded on the max-per-method basis, debug info cannot land in
1306     // this killed area.
1307     uint r_cnt = mcall->tf()->range()->cnt();
1308     MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1309     if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1310       C->record_method_not_compilable("unsupported outgoing calling sequence");
1311     } else {
1312       for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1313         proj->_rout.Insert(OptoReg::Name(i));
1314     }
1315     if (proj->_rout.is_NotEmpty()) {
1316       push_projection(proj);
1317     }
1318   }
1319   // Transfer the safepoint information from the call to the mcall
1320   // Move the JVMState list
1321   msfpt->set_jvms(sfpt->jvms());
1322   for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1323     jvms->set_map(sfpt);
1324   }
1325 
1326   // Debug inputs begin just after the last incoming parameter
1327   assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1328          (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1329 
1330   // Move the OopMap
1331   msfpt->_oop_map = sfpt->_oop_map;
1332 
1333   // Add additional edges.
1334   if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1335     // For these calls we can not add MachConstantBase in expand(), as the
1336     // ins are not complete then.
1337     msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1338     if (msfpt->jvms() &&
1339         msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1340       // We added an edge before jvms, so we must adapt the position of the ins.
1341       msfpt->jvms()->adapt_position(+1);
1342     }
1343   }
1344 
1345   // Registers killed by the call are set in the local scheduling pass
1346   // of Global Code Motion.
1347   return msfpt;
1348 }
1349 
1350 //---------------------------match_tree----------------------------------------
1351 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
1352 // of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
1353 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1354 // a Load's result RegMask for memoization in idealreg2regmask[]
1355 MachNode *Matcher::match_tree( const Node *n ) {
1356   assert( n->Opcode() != Op_Phi, "cannot match" );
1357   assert( !n->is_block_start(), "cannot match" );
1358   // Set the mark for all locally allocated State objects.
1359   // When this call returns, the _states_arena arena will be reset
1360   // freeing all State objects.
1361   ResourceMark rm( &_states_arena );
1362 
1363   LabelRootDepth = 0;
1364 
1365   // StoreNodes require their Memory input to match any LoadNodes
1366   Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1367 #ifdef ASSERT
1368   Node* save_mem_node = _mem_node;
1369   _mem_node = n->is_Store() ? (Node*)n : NULL;
1370 #endif
1371   // State object for root node of match tree
1372   // Allocate it on _states_arena - stack allocation can cause stack overflow.
1373   State *s = new (&_states_arena) State;
1374   s->_kids[0] = NULL;
1375   s->_kids[1] = NULL;
1376   s->_leaf = (Node*)n;
1377   // Label the input tree, allocating labels from top-level arena
1378   Label_Root( n, s, n->in(0), mem );
1379   if (C->failing())  return NULL;
1380 
1381   // The minimum cost match for the whole tree is found at the root State
1382   uint mincost = max_juint;
1383   uint cost = max_juint;
1384   uint i;
1385   for( i = 0; i < NUM_OPERANDS; i++ ) {
1386     if( s->valid(i) &&                // valid entry and
1387         s->_cost[i] < cost &&         // low cost and
1388         s->_rule[i] >= NUM_OPERANDS ) // not an operand
1389       cost = s->_cost[mincost=i];
1390   }
1391   if (mincost == max_juint) {
1392 #ifndef PRODUCT
1393     tty->print("No matching rule for:");
1394     s->dump();
1395 #endif
1396     Matcher::soft_match_failure();
1397     return NULL;
1398   }
1399   // Reduce input tree based upon the state labels to machine Nodes
1400   MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1401 #ifdef ASSERT
1402   _old2new_map.map(n->_idx, m);
1403   _new2old_map.map(m->_idx, (Node*)n);
1404 #endif
1405 
1406   // Add any Matcher-ignored edges
1407   uint cnt = n->req();
1408   uint start = 1;
1409   if( mem != (Node*)1 ) start = MemNode::Memory+1;
1410   if( n->is_AddP() ) {
1411     assert( mem == (Node*)1, "" );
1412     start = AddPNode::Base+1;
1413   }
1414   for( i = start; i < cnt; i++ ) {
1415     if( !n->match_edge(i) ) {
1416       if( i < m->req() )
1417         m->ins_req( i, n->in(i) );
1418       else
1419         m->add_req( n->in(i) );
1420     }
1421   }
1422 
1423   debug_only( _mem_node = save_mem_node; )
1424   return m;
1425 }
1426 
1427 
1428 //------------------------------match_into_reg---------------------------------
1429 // Choose to either match this Node in a register or part of the current
1430 // match tree.  Return true for requiring a register and false for matching
1431 // as part of the current match tree.
1432 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1433 
1434   const Type *t = m->bottom_type();
1435 
1436   if (t->singleton()) {
1437     // Never force constants into registers.  Allow them to match as
1438     // constants or registers.  Copies of the same value will share
1439     // the same register.  See find_shared_node.
1440     return false;
1441   } else {                      // Not a constant
1442     // Stop recursion if they have different Controls.
1443     Node* m_control = m->in(0);
1444     // Control of load's memory can post-dominates load's control.
1445     // So use it since load can't float above its memory.
1446     Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1447     if (control && m_control && control != m_control && control != mem_control) {
1448 
1449       // Actually, we can live with the most conservative control we
1450       // find, if it post-dominates the others.  This allows us to
1451       // pick up load/op/store trees where the load can float a little
1452       // above the store.
1453       Node *x = control;
1454       const uint max_scan = 6;  // Arbitrary scan cutoff
1455       uint j;
1456       for (j=0; j<max_scan; j++) {
1457         if (x->is_Region())     // Bail out at merge points
1458           return true;
1459         x = x->in(0);
1460         if (x == m_control)     // Does 'control' post-dominate
1461           break;                // m->in(0)?  If so, we can use it
1462         if (x == mem_control)   // Does 'control' post-dominate
1463           break;                // mem_control?  If so, we can use it
1464       }
1465       if (j == max_scan)        // No post-domination before scan end?
1466         return true;            // Then break the match tree up
1467     }
1468     if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1469         (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1470       // These are commonly used in address expressions and can
1471       // efficiently fold into them on X64 in some cases.
1472       return false;
1473     }
1474   }
1475 
1476   // Not forceable cloning.  If shared, put it into a register.
1477   return shared;
1478 }
1479 
1480 
1481 //------------------------------Instruction Selection--------------------------
1482 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1483 // ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
1484 // things the Matcher does not match (e.g., Memory), and things with different
1485 // Controls (hence forced into different blocks).  We pass in the Control
1486 // selected for this entire State tree.
1487 
1488 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1489 // Store and the Load must have identical Memories (as well as identical
1490 // pointers).  Since the Matcher does not have anything for Memory (and
1491 // does not handle DAGs), I have to match the Memory input myself.  If the
1492 // Tree root is a Store, I require all Loads to have the identical memory.
1493 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1494   // Since Label_Root is a recursive function, its possible that we might run
1495   // out of stack space.  See bugs 6272980 & 6227033 for more info.
1496   LabelRootDepth++;
1497   if (LabelRootDepth > MaxLabelRootDepth) {
1498     C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1499     return NULL;
1500   }
1501   uint care = 0;                // Edges matcher cares about
1502   uint cnt = n->req();
1503   uint i = 0;
1504 
1505   // Examine children for memory state
1506   // Can only subsume a child into your match-tree if that child's memory state
1507   // is not modified along the path to another input.
1508   // It is unsafe even if the other inputs are separate roots.
1509   Node *input_mem = NULL;
1510   for( i = 1; i < cnt; i++ ) {
1511     if( !n->match_edge(i) ) continue;
1512     Node *m = n->in(i);         // Get ith input
1513     assert( m, "expect non-null children" );
1514     if( m->is_Load() ) {
1515       if( input_mem == NULL ) {
1516         input_mem = m->in(MemNode::Memory);
1517       } else if( input_mem != m->in(MemNode::Memory) ) {
1518         input_mem = NodeSentinel;
1519       }
1520     }
1521   }
1522 
1523   for( i = 1; i < cnt; i++ ){// For my children
1524     if( !n->match_edge(i) ) continue;
1525     Node *m = n->in(i);         // Get ith input
1526     // Allocate states out of a private arena
1527     State *s = new (&_states_arena) State;
1528     svec->_kids[care++] = s;
1529     assert( care <= 2, "binary only for now" );
1530 
1531     // Recursively label the State tree.
1532     s->_kids[0] = NULL;
1533     s->_kids[1] = NULL;
1534     s->_leaf = m;
1535 
1536     // Check for leaves of the State Tree; things that cannot be a part of
1537     // the current tree.  If it finds any, that value is matched as a
1538     // register operand.  If not, then the normal matching is used.
1539     if( match_into_reg(n, m, control, i, is_shared(m)) ||
1540         //
1541         // Stop recursion if this is LoadNode and the root of this tree is a
1542         // StoreNode and the load & store have different memories.
1543         ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1544         // Can NOT include the match of a subtree when its memory state
1545         // is used by any of the other subtrees
1546         (input_mem == NodeSentinel) ) {
1547       // Print when we exclude matching due to different memory states at input-loads
1548       if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1549         && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1550         tty->print_cr("invalid input_mem");
1551       }
1552       // Switch to a register-only opcode; this value must be in a register
1553       // and cannot be subsumed as part of a larger instruction.
1554       s->DFA( m->ideal_reg(), m );
1555 
1556     } else {
1557       // If match tree has no control and we do, adopt it for entire tree
1558       if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1559         control = m->in(0);         // Pick up control
1560       // Else match as a normal part of the match tree.
1561       control = Label_Root(m,s,control,mem);
1562       if (C->failing()) return NULL;
1563     }
1564   }
1565 
1566 
1567   // Call DFA to match this node, and return
1568   svec->DFA( n->Opcode(), n );
1569 
1570 #ifdef ASSERT
1571   uint x;
1572   for( x = 0; x < _LAST_MACH_OPER; x++ )
1573     if( svec->valid(x) )
1574       break;
1575 
1576   if (x >= _LAST_MACH_OPER) {
1577     n->dump();
1578     svec->dump();
1579     assert( false, "bad AD file" );
1580   }
1581 #endif
1582   return control;
1583 }
1584 
1585 
1586 // Con nodes reduced using the same rule can share their MachNode
1587 // which reduces the number of copies of a constant in the final
1588 // program.  The register allocator is free to split uses later to
1589 // split live ranges.
1590 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1591   if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1592 
1593   // See if this Con has already been reduced using this rule.
1594   if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1595   MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1596   if (last != NULL && rule == last->rule()) {
1597     // Don't expect control change for DecodeN
1598     if (leaf->is_DecodeNarrowPtr())
1599       return last;
1600     // Get the new space root.
1601     Node* xroot = new_node(C->root());
1602     if (xroot == NULL) {
1603       // This shouldn't happen give the order of matching.
1604       return NULL;
1605     }
1606 
1607     // Shared constants need to have their control be root so they
1608     // can be scheduled properly.
1609     Node* control = last->in(0);
1610     if (control != xroot) {
1611       if (control == NULL || control == C->root()) {
1612         last->set_req(0, xroot);
1613       } else {
1614         assert(false, "unexpected control");
1615         return NULL;
1616       }
1617     }
1618     return last;
1619   }
1620   return NULL;
1621 }
1622 
1623 
1624 //------------------------------ReduceInst-------------------------------------
1625 // Reduce a State tree (with given Control) into a tree of MachNodes.
1626 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1627 // complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
1628 // Each MachNode has a number of complicated MachOper operands; each
1629 // MachOper also covers a further tree of Ideal Nodes.
1630 
1631 // The root of the Ideal match tree is always an instruction, so we enter
1632 // the recursion here.  After building the MachNode, we need to recurse
1633 // the tree checking for these cases:
1634 // (1) Child is an instruction -
1635 //     Build the instruction (recursively), add it as an edge.
1636 //     Build a simple operand (register) to hold the result of the instruction.
1637 // (2) Child is an interior part of an instruction -
1638 //     Skip over it (do nothing)
1639 // (3) Child is the start of a operand -
1640 //     Build the operand, place it inside the instruction
1641 //     Call ReduceOper.
1642 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1643   assert( rule >= NUM_OPERANDS, "called with operand rule" );
1644 
1645   MachNode* shared_node = find_shared_node(s->_leaf, rule);
1646   if (shared_node != NULL) {
1647     return shared_node;
1648   }
1649 
1650   // Build the object to represent this state & prepare for recursive calls
1651   MachNode *mach = s->MachNodeGenerator(rule);
1652   guarantee(mach != NULL, "Missing MachNode");
1653   mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1654   assert( mach->_opnds[0] != NULL, "Missing result operand" );
1655   Node *leaf = s->_leaf;
1656   // Check for instruction or instruction chain rule
1657   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1658     assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1659            "duplicating node that's already been matched");
1660     // Instruction
1661     mach->add_req( leaf->in(0) ); // Set initial control
1662     // Reduce interior of complex instruction
1663     ReduceInst_Interior( s, rule, mem, mach, 1 );
1664   } else {
1665     // Instruction chain rules are data-dependent on their inputs
1666     mach->add_req(0);             // Set initial control to none
1667     ReduceInst_Chain_Rule( s, rule, mem, mach );
1668   }
1669 
1670   // If a Memory was used, insert a Memory edge
1671   if( mem != (Node*)1 ) {
1672     mach->ins_req(MemNode::Memory,mem);
1673 #ifdef ASSERT
1674     // Verify adr type after matching memory operation
1675     const MachOper* oper = mach->memory_operand();
1676     if (oper != NULL && oper != (MachOper*)-1) {
1677       // It has a unique memory operand.  Find corresponding ideal mem node.
1678       Node* m = NULL;
1679       if (leaf->is_Mem()) {
1680         m = leaf;
1681       } else {
1682         m = _mem_node;
1683         assert(m != NULL && m->is_Mem(), "expecting memory node");
1684       }
1685       const Type* mach_at = mach->adr_type();
1686       // DecodeN node consumed by an address may have different type
1687       // than its input. Don't compare types for such case.
1688       if (m->adr_type() != mach_at &&
1689           (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1690            (m->in(MemNode::Address)->is_AddP() &&
1691             m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1692            (m->in(MemNode::Address)->is_AddP() &&
1693             m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1694             m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1695         mach_at = m->adr_type();
1696       }
1697       if (m->adr_type() != mach_at) {
1698         m->dump();
1699         tty->print_cr("mach:");
1700         mach->dump(1);
1701       }
1702       assert(m->adr_type() == mach_at, "matcher should not change adr type");
1703     }
1704 #endif
1705   }
1706 
1707   // If the _leaf is an AddP, insert the base edge
1708   if (leaf->is_AddP()) {
1709     mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1710   }
1711 
1712   uint number_of_projections_prior = number_of_projections();
1713 
1714   // Perform any 1-to-many expansions required
1715   MachNode *ex = mach->Expand(s, _projection_list, mem);
1716   if (ex != mach) {
1717     assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1718     if( ex->in(1)->is_Con() )
1719       ex->in(1)->set_req(0, C->root());
1720     // Remove old node from the graph
1721     for( uint i=0; i<mach->req(); i++ ) {
1722       mach->set_req(i,NULL);
1723     }
1724 #ifdef ASSERT
1725     _new2old_map.map(ex->_idx, s->_leaf);
1726 #endif
1727   }
1728 
1729   // PhaseChaitin::fixup_spills will sometimes generate spill code
1730   // via the matcher.  By the time, nodes have been wired into the CFG,
1731   // and any further nodes generated by expand rules will be left hanging
1732   // in space, and will not get emitted as output code.  Catch this.
1733   // Also, catch any new register allocation constraints ("projections")
1734   // generated belatedly during spill code generation.
1735   if (_allocation_started) {
1736     guarantee(ex == mach, "no expand rules during spill generation");
1737     guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1738   }
1739 
1740   if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1741     // Record the con for sharing
1742     _shared_nodes.map(leaf->_idx, ex);
1743   }
1744 
1745   return ex;
1746 }
1747 
1748 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1749   for (uint i = n->req(); i < n->len(); i++) {
1750     if (n->in(i) != NULL) {
1751       mach->add_prec(n->in(i));
1752     }
1753   }
1754 }
1755 
1756 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1757   // 'op' is what I am expecting to receive
1758   int op = _leftOp[rule];
1759   // Operand type to catch childs result
1760   // This is what my child will give me.
1761   int opnd_class_instance = s->_rule[op];
1762   // Choose between operand class or not.
1763   // This is what I will receive.
1764   int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1765   // New rule for child.  Chase operand classes to get the actual rule.
1766   int newrule = s->_rule[catch_op];
1767 
1768   if( newrule < NUM_OPERANDS ) {
1769     // Chain from operand or operand class, may be output of shared node
1770     assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1771             "Bad AD file: Instruction chain rule must chain from operand");
1772     // Insert operand into array of operands for this instruction
1773     mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1774 
1775     ReduceOper( s, newrule, mem, mach );
1776   } else {
1777     // Chain from the result of an instruction
1778     assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1779     mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1780     Node *mem1 = (Node*)1;
1781     debug_only(Node *save_mem_node = _mem_node;)
1782     mach->add_req( ReduceInst(s, newrule, mem1) );
1783     debug_only(_mem_node = save_mem_node;)
1784   }
1785   return;
1786 }
1787 
1788 
1789 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1790   handle_precedence_edges(s->_leaf, mach);
1791 
1792   if( s->_leaf->is_Load() ) {
1793     Node *mem2 = s->_leaf->in(MemNode::Memory);
1794     assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1795     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1796     mem = mem2;
1797   }
1798   if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1799     if( mach->in(0) == NULL )
1800       mach->set_req(0, s->_leaf->in(0));
1801   }
1802 
1803   // Now recursively walk the state tree & add operand list.
1804   for( uint i=0; i<2; i++ ) {   // binary tree
1805     State *newstate = s->_kids[i];
1806     if( newstate == NULL ) break;      // Might only have 1 child
1807     // 'op' is what I am expecting to receive
1808     int op;
1809     if( i == 0 ) {
1810       op = _leftOp[rule];
1811     } else {
1812       op = _rightOp[rule];
1813     }
1814     // Operand type to catch childs result
1815     // This is what my child will give me.
1816     int opnd_class_instance = newstate->_rule[op];
1817     // Choose between operand class or not.
1818     // This is what I will receive.
1819     int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1820     // New rule for child.  Chase operand classes to get the actual rule.
1821     int newrule = newstate->_rule[catch_op];
1822 
1823     if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1824       // Operand/operandClass
1825       // Insert operand into array of operands for this instruction
1826       mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1827       ReduceOper( newstate, newrule, mem, mach );
1828 
1829     } else {                    // Child is internal operand or new instruction
1830       if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1831         // internal operand --> call ReduceInst_Interior
1832         // Interior of complex instruction.  Do nothing but recurse.
1833         num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1834       } else {
1835         // instruction --> call build operand(  ) to catch result
1836         //             --> ReduceInst( newrule )
1837         mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1838         Node *mem1 = (Node*)1;
1839         debug_only(Node *save_mem_node = _mem_node;)
1840         mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1841         debug_only(_mem_node = save_mem_node;)
1842       }
1843     }
1844     assert( mach->_opnds[num_opnds-1], "" );
1845   }
1846   return num_opnds;
1847 }
1848 
1849 // This routine walks the interior of possible complex operands.
1850 // At each point we check our children in the match tree:
1851 // (1) No children -
1852 //     We are a leaf; add _leaf field as an input to the MachNode
1853 // (2) Child is an internal operand -
1854 //     Skip over it ( do nothing )
1855 // (3) Child is an instruction -
1856 //     Call ReduceInst recursively and
1857 //     and instruction as an input to the MachNode
1858 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1859   assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1860   State *kid = s->_kids[0];
1861   assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1862 
1863   // Leaf?  And not subsumed?
1864   if( kid == NULL && !_swallowed[rule] ) {
1865     mach->add_req( s->_leaf );  // Add leaf pointer
1866     return;                     // Bail out
1867   }
1868 
1869   if( s->_leaf->is_Load() ) {
1870     assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1871     mem = s->_leaf->in(MemNode::Memory);
1872     debug_only(_mem_node = s->_leaf;)
1873   }
1874 
1875   handle_precedence_edges(s->_leaf, mach);
1876 
1877   if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1878     if( !mach->in(0) )
1879       mach->set_req(0,s->_leaf->in(0));
1880     else {
1881       assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1882     }
1883   }
1884 
1885   for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) {   // binary tree
1886     int newrule;
1887     if( i == 0)
1888       newrule = kid->_rule[_leftOp[rule]];
1889     else
1890       newrule = kid->_rule[_rightOp[rule]];
1891 
1892     if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1893       // Internal operand; recurse but do nothing else
1894       ReduceOper( kid, newrule, mem, mach );
1895 
1896     } else {                    // Child is a new instruction
1897       // Reduce the instruction, and add a direct pointer from this
1898       // machine instruction to the newly reduced one.
1899       Node *mem1 = (Node*)1;
1900       debug_only(Node *save_mem_node = _mem_node;)
1901       mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1902       debug_only(_mem_node = save_mem_node;)
1903     }
1904   }
1905 }
1906 
1907 
1908 // -------------------------------------------------------------------------
1909 // Java-Java calling convention
1910 // (what you use when Java calls Java)
1911 
1912 //------------------------------find_receiver----------------------------------
1913 // For a given signature, return the OptoReg for parameter 0.
1914 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1915   VMRegPair regs;
1916   BasicType sig_bt = T_OBJECT;
1917   calling_convention(&sig_bt, &regs, 1, is_outgoing);
1918   // Return argument 0 register.  In the LP64 build pointers
1919   // take 2 registers, but the VM wants only the 'main' name.
1920   return OptoReg::as_OptoReg(regs.first());
1921 }
1922 
1923 // This function identifies sub-graphs in which a 'load' node is
1924 // input to two different nodes, and such that it can be matched
1925 // with BMI instructions like blsi, blsr, etc.
1926 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1927 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1928 // refers to the same node.
1929 #ifdef X86
1930 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1931 // This is a temporary solution until we make DAGs expressible in ADL.
1932 template<typename ConType>
1933 class FusedPatternMatcher {
1934   Node* _op1_node;
1935   Node* _mop_node;
1936   int _con_op;
1937 
1938   static int match_next(Node* n, int next_op, int next_op_idx) {
1939     if (n->in(1) == NULL || n->in(2) == NULL) {
1940       return -1;
1941     }
1942 
1943     if (next_op_idx == -1) { // n is commutative, try rotations
1944       if (n->in(1)->Opcode() == next_op) {
1945         return 1;
1946       } else if (n->in(2)->Opcode() == next_op) {
1947         return 2;
1948       }
1949     } else {
1950       assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1951       if (n->in(next_op_idx)->Opcode() == next_op) {
1952         return next_op_idx;
1953       }
1954     }
1955     return -1;
1956   }
1957 public:
1958   FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1959     _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1960 
1961   bool match(int op1, int op1_op2_idx,  // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1962              int op2, int op2_con_idx,  // op2 and the index of the op2->con edge, -1 if op2 is commutative
1963              typename ConType::NativeType con_value) {
1964     if (_op1_node->Opcode() != op1) {
1965       return false;
1966     }
1967     if (_mop_node->outcnt() > 2) {
1968       return false;
1969     }
1970     op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1971     if (op1_op2_idx == -1) {
1972       return false;
1973     }
1974     // Memory operation must be the other edge
1975     int op1_mop_idx = (op1_op2_idx & 1) + 1;
1976 
1977     // Check that the mop node is really what we want
1978     if (_op1_node->in(op1_mop_idx) == _mop_node) {
1979       Node *op2_node = _op1_node->in(op1_op2_idx);
1980       if (op2_node->outcnt() > 1) {
1981         return false;
1982       }
1983       assert(op2_node->Opcode() == op2, "Should be");
1984       op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1985       if (op2_con_idx == -1) {
1986         return false;
1987       }
1988       // Memory operation must be the other edge
1989       int op2_mop_idx = (op2_con_idx & 1) + 1;
1990       // Check that the memory operation is the same node
1991       if (op2_node->in(op2_mop_idx) == _mop_node) {
1992         // Now check the constant
1993         const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1994         if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1995           return true;
1996         }
1997       }
1998     }
1999     return false;
2000   }
2001 };
2002 
2003 
2004 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2005   if (n != NULL && m != NULL) {
2006     if (m->Opcode() == Op_LoadI) {
2007       FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2008       return bmii.match(Op_AndI, -1, Op_SubI,  1,  0)  ||
2009              bmii.match(Op_AndI, -1, Op_AddI, -1, -1)  ||
2010              bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2011     } else if (m->Opcode() == Op_LoadL) {
2012       FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2013       return bmil.match(Op_AndL, -1, Op_SubL,  1,  0) ||
2014              bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2015              bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2016     }
2017   }
2018   return false;
2019 }
2020 #endif // X86
2021 
2022 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2023   Node *off = m->in(AddPNode::Offset);
2024   if (off->is_Con()) {
2025     address_visited.test_set(m->_idx); // Flag as address_visited
2026     mstack.push(m->in(AddPNode::Address), Pre_Visit);
2027     // Clone X+offset as it also folds into most addressing expressions
2028     mstack.push(off, Visit);
2029     mstack.push(m->in(AddPNode::Base), Pre_Visit);
2030     return true;
2031   }
2032   return false;
2033 }
2034 
2035 // A method-klass-holder may be passed in the inline_cache_reg
2036 // and then expanded into the inline_cache_reg and a method_oop register
2037 //   defined in ad_<arch>.cpp
2038 
2039 //------------------------------find_shared------------------------------------
2040 // Set bits if Node is shared or otherwise a root
2041 void Matcher::find_shared( Node *n ) {
2042   // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2043   MStack mstack(C->live_nodes() * 2);
2044   // Mark nodes as address_visited if they are inputs to an address expression
2045   VectorSet address_visited(Thread::current()->resource_area());
2046   mstack.push(n, Visit);     // Don't need to pre-visit root node
2047   while (mstack.is_nonempty()) {
2048     n = mstack.node();       // Leave node on stack
2049     Node_State nstate = mstack.state();
2050     uint nop = n->Opcode();
2051     if (nstate == Pre_Visit) {
2052       if (address_visited.test(n->_idx)) { // Visited in address already?
2053         // Flag as visited and shared now.
2054         set_visited(n);
2055       }
2056       if (is_visited(n)) {   // Visited already?
2057         // Node is shared and has no reason to clone.  Flag it as shared.
2058         // This causes it to match into a register for the sharing.
2059         set_shared(n);       // Flag as shared and
2060         if (n->is_DecodeNarrowPtr()) {
2061           // Oop field/array element loads must be shared but since
2062           // they are shared through a DecodeN they may appear to have
2063           // a single use so force sharing here.
2064           set_shared(n->in(1));
2065         }
2066         mstack.pop();        // remove node from stack
2067         continue;
2068       }
2069       nstate = Visit; // Not already visited; so visit now
2070     }
2071     if (nstate == Visit) {
2072       mstack.set_state(Post_Visit);
2073       set_visited(n);   // Flag as visited now
2074       bool mem_op = false;
2075       int mem_addr_idx = MemNode::Address;
2076 
2077       switch( nop ) {  // Handle some opcodes special
2078       case Op_Phi:             // Treat Phis as shared roots
2079       case Op_Parm:
2080       case Op_Proj:            // All handled specially during matching
2081       case Op_SafePointScalarObject:
2082         set_shared(n);
2083         set_dontcare(n);
2084         break;
2085       case Op_If:
2086       case Op_CountedLoopEnd:
2087         mstack.set_state(Alt_Post_Visit); // Alternative way
2088         // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
2089         // with matching cmp/branch in 1 instruction.  The Matcher needs the
2090         // Bool and CmpX side-by-side, because it can only get at constants
2091         // that are at the leaves of Match trees, and the Bool's condition acts
2092         // as a constant here.
2093         mstack.push(n->in(1), Visit);         // Clone the Bool
2094         mstack.push(n->in(0), Pre_Visit);     // Visit control input
2095         continue; // while (mstack.is_nonempty())
2096       case Op_ConvI2D:         // These forms efficiently match with a prior
2097       case Op_ConvI2F:         //   Load but not a following Store
2098         if( n->in(1)->is_Load() &&        // Prior load
2099             n->outcnt() == 1 &&           // Not already shared
2100             n->unique_out()->is_Store() ) // Following store
2101           set_shared(n);       // Force it to be a root
2102         break;
2103       case Op_ReverseBytesI:
2104       case Op_ReverseBytesL:
2105         if( n->in(1)->is_Load() &&        // Prior load
2106             n->outcnt() == 1 )            // Not already shared
2107           set_shared(n);                  // Force it to be a root
2108         break;
2109       case Op_BoxLock:         // Cant match until we get stack-regs in ADLC
2110       case Op_IfFalse:
2111       case Op_IfTrue:
2112       case Op_MachProj:
2113       case Op_MergeMem:
2114       case Op_Catch:
2115       case Op_CatchProj:
2116       case Op_CProj:
2117       case Op_JumpProj:
2118       case Op_JProj:
2119       case Op_NeverBranch:
2120         set_dontcare(n);
2121         break;
2122       case Op_Jump:
2123         mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
2124         mstack.push(n->in(0), Pre_Visit);     // Visit Control input
2125         continue;                             // while (mstack.is_nonempty())
2126       case Op_StrComp:
2127       case Op_StrEquals:
2128       case Op_StrIndexOf:
2129       case Op_StrIndexOfChar:
2130       case Op_AryEq:
2131       case Op_HasNegatives:
2132       case Op_StrInflatedCopy:
2133       case Op_StrCompressedCopy:
2134       case Op_EncodeISOArray:
2135       case Op_FmaD:
2136       case Op_FmaF:
2137       case Op_FmaVD:
2138       case Op_FmaVF:
2139         set_shared(n); // Force result into register (it will be anyways)
2140         break;
2141       case Op_ConP: {  // Convert pointers above the centerline to NUL
2142         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2143         const TypePtr* tp = tn->type()->is_ptr();
2144         if (tp->_ptr == TypePtr::AnyNull) {
2145           tn->set_type(TypePtr::NULL_PTR);
2146         }
2147         break;
2148       }
2149       case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
2150         TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2151         const TypePtr* tp = tn->type()->make_ptr();
2152         if (tp && tp->_ptr == TypePtr::AnyNull) {
2153           tn->set_type(TypeNarrowOop::NULL_PTR);
2154         }
2155         break;
2156       }
2157       case Op_Binary:         // These are introduced in the Post_Visit state.
2158         ShouldNotReachHere();
2159         break;
2160       case Op_ClearArray:
2161       case Op_SafePoint:
2162         mem_op = true;
2163         break;
2164 #if INCLUDE_ZGC
2165       case Op_CallLeaf:
2166         if (UseZGC) {
2167           if (n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr() ||
2168               n->as_Call()->entry_point() == ZBarrierSetRuntime::load_barrier_on_weak_oop_field_preloaded_addr()) {
2169             mem_op = true;
2170             mem_addr_idx = TypeFunc::Parms+1;
2171           }
2172           break;
2173         }
2174 #endif
2175       default:
2176         if( n->is_Store() ) {
2177           // Do match stores, despite no ideal reg
2178           mem_op = true;
2179           break;
2180         }
2181         if( n->is_Mem() ) { // Loads and LoadStores
2182           mem_op = true;
2183           // Loads must be root of match tree due to prior load conflict
2184           if( C->subsume_loads() == false )
2185             set_shared(n);
2186         }
2187         // Fall into default case
2188         if( !n->ideal_reg() )
2189           set_dontcare(n);  // Unmatchable Nodes
2190       } // end_switch
2191 
2192       for(int i = n->req() - 1; i >= 0; --i) { // For my children
2193         Node *m = n->in(i); // Get ith input
2194         if (m == NULL) continue;  // Ignore NULLs
2195         uint mop = m->Opcode();
2196 
2197         // Must clone all producers of flags, or we will not match correctly.
2198         // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2199         // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
2200         // are also there, so we may match a float-branch to int-flags and
2201         // expect the allocator to haul the flags from the int-side to the
2202         // fp-side.  No can do.
2203         if( _must_clone[mop] ) {
2204           mstack.push(m, Visit);
2205           continue; // for(int i = ...)
2206         }
2207 
2208         // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2209 #ifdef X86
2210         if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2211           mstack.push(m, Visit);
2212           continue;
2213         }
2214 #endif
2215 
2216         // Clone addressing expressions as they are "free" in memory access instructions
2217         if (mem_op && i == mem_addr_idx && mop == Op_AddP &&
2218             // When there are other uses besides address expressions
2219             // put it on stack and mark as shared.
2220             !is_visited(m)) {
2221           // Some inputs for address expression are not put on stack
2222           // to avoid marking them as shared and forcing them into register
2223           // if they are used only in address expressions.
2224           // But they should be marked as shared if there are other uses
2225           // besides address expressions.
2226 
2227           if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2228             continue;
2229           }
2230         }   // if( mem_op &&
2231         mstack.push(m, Pre_Visit);
2232       }     // for(int i = ...)
2233     }
2234     else if (nstate == Alt_Post_Visit) {
2235       mstack.pop(); // Remove node from stack
2236       // We cannot remove the Cmp input from the Bool here, as the Bool may be
2237       // shared and all users of the Bool need to move the Cmp in parallel.
2238       // This leaves both the Bool and the If pointing at the Cmp.  To
2239       // prevent the Matcher from trying to Match the Cmp along both paths
2240       // BoolNode::match_edge always returns a zero.
2241 
2242       // We reorder the Op_If in a pre-order manner, so we can visit without
2243       // accidentally sharing the Cmp (the Bool and the If make 2 users).
2244       n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2245     }
2246     else if (nstate == Post_Visit) {
2247       mstack.pop(); // Remove node from stack
2248 
2249       // Now hack a few special opcodes
2250       switch( n->Opcode() ) {       // Handle some opcodes special
2251       case Op_StorePConditional:
2252       case Op_StoreIConditional:
2253       case Op_StoreLConditional:
2254 #if INCLUDE_SHENANDOAHGC
2255       case Op_ShenandoahCompareAndExchangeP:
2256       case Op_ShenandoahCompareAndExchangeN:
2257       case Op_ShenandoahWeakCompareAndSwapP:
2258       case Op_ShenandoahWeakCompareAndSwapN:
2259       case Op_ShenandoahCompareAndSwapP:
2260       case Op_ShenandoahCompareAndSwapN:
2261 #endif
2262       case Op_CompareAndExchangeB:
2263       case Op_CompareAndExchangeS:
2264       case Op_CompareAndExchangeI:
2265       case Op_CompareAndExchangeL:
2266       case Op_CompareAndExchangeP:
2267       case Op_CompareAndExchangeN:
2268       case Op_WeakCompareAndSwapB:
2269       case Op_WeakCompareAndSwapS:
2270       case Op_WeakCompareAndSwapI:
2271       case Op_WeakCompareAndSwapL:
2272       case Op_WeakCompareAndSwapP:
2273       case Op_WeakCompareAndSwapN:
2274       case Op_CompareAndSwapB:
2275       case Op_CompareAndSwapS:
2276       case Op_CompareAndSwapI:
2277       case Op_CompareAndSwapL:
2278       case Op_CompareAndSwapP:
2279       case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
2280         Node *newval = n->in(MemNode::ValueIn );
2281         Node *oldval  = n->in(LoadStoreConditionalNode::ExpectedIn);
2282         Node *pair = new BinaryNode( oldval, newval );
2283         n->set_req(MemNode::ValueIn,pair);
2284         n->del_req(LoadStoreConditionalNode::ExpectedIn);
2285         break;
2286       }
2287       case Op_CMoveD:              // Convert trinary to binary-tree
2288       case Op_CMoveF:
2289       case Op_CMoveI:
2290       case Op_CMoveL:
2291       case Op_CMoveN:
2292       case Op_CMoveP:
2293       case Op_CMoveVF:
2294       case Op_CMoveVD:  {
2295         // Restructure into a binary tree for Matching.  It's possible that
2296         // we could move this code up next to the graph reshaping for IfNodes
2297         // or vice-versa, but I do not want to debug this for Ladybird.
2298         // 10/2/2000 CNC.
2299         Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2300         n->set_req(1,pair1);
2301         Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2302         n->set_req(2,pair2);
2303         n->del_req(3);
2304         break;
2305       }
2306       case Op_LoopLimit: {
2307         Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2308         n->set_req(1,pair1);
2309         n->set_req(2,n->in(3));
2310         n->del_req(3);
2311         break;
2312       }
2313       case Op_StrEquals:
2314       case Op_StrIndexOfChar: {
2315         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2316         n->set_req(2,pair1);
2317         n->set_req(3,n->in(4));
2318         n->del_req(4);
2319         break;
2320       }
2321       case Op_StrComp:
2322       case Op_StrIndexOf: {
2323         Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2324         n->set_req(2,pair1);
2325         Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2326         n->set_req(3,pair2);
2327         n->del_req(5);
2328         n->del_req(4);
2329         break;
2330       }
2331       case Op_StrCompressedCopy:
2332       case Op_StrInflatedCopy:
2333       case Op_EncodeISOArray: {
2334         // Restructure into a binary tree for Matching.
2335         Node* pair = new BinaryNode(n->in(3), n->in(4));
2336         n->set_req(3, pair);
2337         n->del_req(4);
2338         break;
2339       }
2340       case Op_FmaD:
2341       case Op_FmaF:
2342       case Op_FmaVD:
2343       case Op_FmaVF: {
2344         // Restructure into a binary tree for Matching.
2345         Node* pair = new BinaryNode(n->in(1), n->in(2));
2346         n->set_req(2, pair);
2347         n->set_req(1, n->in(3));
2348         n->del_req(3);
2349         break;
2350       }
2351       default:
2352         break;
2353       }
2354     }
2355     else {
2356       ShouldNotReachHere();
2357     }
2358   } // end of while (mstack.is_nonempty())
2359 }
2360 
2361 #ifdef ASSERT
2362 // machine-independent root to machine-dependent root
2363 void Matcher::dump_old2new_map() {
2364   _old2new_map.dump();
2365 }
2366 #endif
2367 
2368 //---------------------------collect_null_checks-------------------------------
2369 // Find null checks in the ideal graph; write a machine-specific node for
2370 // it.  Used by later implicit-null-check handling.  Actually collects
2371 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2372 // value being tested.
2373 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2374   Node *iff = proj->in(0);
2375   if( iff->Opcode() == Op_If ) {
2376     // During matching If's have Bool & Cmp side-by-side
2377     BoolNode *b = iff->in(1)->as_Bool();
2378     Node *cmp = iff->in(2);
2379     int opc = cmp->Opcode();
2380     if (opc != Op_CmpP && opc != Op_CmpN) return;
2381 
2382     const Type* ct = cmp->in(2)->bottom_type();
2383     if (ct == TypePtr::NULL_PTR ||
2384         (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2385 
2386       bool push_it = false;
2387       if( proj->Opcode() == Op_IfTrue ) {
2388 #ifndef PRODUCT
2389         extern int all_null_checks_found;
2390         all_null_checks_found++;
2391 #endif
2392         if( b->_test._test == BoolTest::ne ) {
2393           push_it = true;
2394         }
2395       } else {
2396         assert( proj->Opcode() == Op_IfFalse, "" );
2397         if( b->_test._test == BoolTest::eq ) {
2398           push_it = true;
2399         }
2400       }
2401       if( push_it ) {
2402         _null_check_tests.push(proj);
2403         Node* val = cmp->in(1);
2404 #ifdef _LP64
2405         if (val->bottom_type()->isa_narrowoop() &&
2406             !Matcher::narrow_oop_use_complex_address()) {
2407           //
2408           // Look for DecodeN node which should be pinned to orig_proj.
2409           // On platforms (Sparc) which can not handle 2 adds
2410           // in addressing mode we have to keep a DecodeN node and
2411           // use it to do implicit NULL check in address.
2412           //
2413           // DecodeN node was pinned to non-null path (orig_proj) during
2414           // CastPP transformation in final_graph_reshaping_impl().
2415           //
2416           uint cnt = orig_proj->outcnt();
2417           for (uint i = 0; i < orig_proj->outcnt(); i++) {
2418             Node* d = orig_proj->raw_out(i);
2419             if (d->is_DecodeN() && d->in(1) == val) {
2420               val = d;
2421               val->set_req(0, NULL); // Unpin now.
2422               // Mark this as special case to distinguish from
2423               // a regular case: CmpP(DecodeN, NULL).
2424               val = (Node*)(((intptr_t)val) | 1);
2425               break;
2426             }
2427           }
2428         }
2429 #endif
2430         _null_check_tests.push(val);
2431       }
2432     }
2433   }
2434 }
2435 
2436 //---------------------------validate_null_checks------------------------------
2437 // Its possible that the value being NULL checked is not the root of a match
2438 // tree.  If so, I cannot use the value in an implicit null check.
2439 void Matcher::validate_null_checks( ) {
2440   uint cnt = _null_check_tests.size();
2441   for( uint i=0; i < cnt; i+=2 ) {
2442     Node *test = _null_check_tests[i];
2443     Node *val = _null_check_tests[i+1];
2444     bool is_decoden = ((intptr_t)val) & 1;
2445     val = (Node*)(((intptr_t)val) & ~1);
2446     if (has_new_node(val)) {
2447       Node* new_val = new_node(val);
2448       if (is_decoden) {
2449         assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2450         // Note: new_val may have a control edge if
2451         // the original ideal node DecodeN was matched before
2452         // it was unpinned in Matcher::collect_null_checks().
2453         // Unpin the mach node and mark it.
2454         new_val->set_req(0, NULL);
2455         new_val = (Node*)(((intptr_t)new_val) | 1);
2456       }
2457       // Is a match-tree root, so replace with the matched value
2458       _null_check_tests.map(i+1, new_val);
2459     } else {
2460       // Yank from candidate list
2461       _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2462       _null_check_tests.map(i,_null_check_tests[--cnt]);
2463       _null_check_tests.pop();
2464       _null_check_tests.pop();
2465       i-=2;
2466     }
2467   }
2468 }
2469 
2470 // Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
2471 // atomic instruction acting as a store_load barrier without any
2472 // intervening volatile load, and thus we don't need a barrier here.
2473 // We retain the Node to act as a compiler ordering barrier.
2474 bool Matcher::post_store_load_barrier(const Node* vmb) {
2475   Compile* C = Compile::current();
2476   assert(vmb->is_MemBar(), "");
2477   assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2478   const MemBarNode* membar = vmb->as_MemBar();
2479 
2480   // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2481   Node* ctrl = NULL;
2482   for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2483     Node* p = membar->fast_out(i);
2484     assert(p->is_Proj(), "only projections here");
2485     if ((p->as_Proj()->_con == TypeFunc::Control) &&
2486         !C->node_arena()->contains(p)) { // Unmatched old-space only
2487       ctrl = p;
2488       break;
2489     }
2490   }
2491   assert((ctrl != NULL), "missing control projection");
2492 
2493   for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2494     Node *x = ctrl->fast_out(j);
2495     int xop = x->Opcode();
2496 
2497     // We don't need current barrier if we see another or a lock
2498     // before seeing volatile load.
2499     //
2500     // Op_Fastunlock previously appeared in the Op_* list below.
2501     // With the advent of 1-0 lock operations we're no longer guaranteed
2502     // that a monitor exit operation contains a serializing instruction.
2503 
2504     if (xop == Op_MemBarVolatile ||
2505 #if INCLUDE_SHENANDOAHGC
2506         xop == Op_ShenandoahCompareAndExchangeP ||
2507         xop == Op_ShenandoahCompareAndExchangeN ||
2508         xop == Op_ShenandoahWeakCompareAndSwapP ||
2509         xop == Op_ShenandoahWeakCompareAndSwapN ||
2510         xop == Op_ShenandoahCompareAndSwapN ||
2511         xop == Op_ShenandoahCompareAndSwapP ||
2512 #endif
2513         xop == Op_CompareAndExchangeB ||
2514         xop == Op_CompareAndExchangeS ||
2515         xop == Op_CompareAndExchangeI ||
2516         xop == Op_CompareAndExchangeL ||
2517         xop == Op_CompareAndExchangeP ||
2518         xop == Op_CompareAndExchangeN ||
2519         xop == Op_WeakCompareAndSwapB ||
2520         xop == Op_WeakCompareAndSwapS ||
2521         xop == Op_WeakCompareAndSwapL ||
2522         xop == Op_WeakCompareAndSwapP ||
2523         xop == Op_WeakCompareAndSwapN ||
2524         xop == Op_WeakCompareAndSwapI ||
2525         xop == Op_CompareAndSwapB ||
2526         xop == Op_CompareAndSwapS ||
2527         xop == Op_CompareAndSwapL ||
2528         xop == Op_CompareAndSwapP ||
2529         xop == Op_CompareAndSwapN ||
2530         xop == Op_CompareAndSwapI) {
2531       return true;
2532     }
2533 
2534     // Op_FastLock previously appeared in the Op_* list above.
2535     // With biased locking we're no longer guaranteed that a monitor
2536     // enter operation contains a serializing instruction.
2537     if ((xop == Op_FastLock) && !UseBiasedLocking) {
2538       return true;
2539     }
2540 
2541     if (x->is_MemBar()) {
2542       // We must retain this membar if there is an upcoming volatile
2543       // load, which will be followed by acquire membar.
2544       if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2545         return false;
2546       } else {
2547         // For other kinds of barriers, check by pretending we
2548         // are them, and seeing if we can be removed.
2549         return post_store_load_barrier(x->as_MemBar());
2550       }
2551     }
2552 
2553     // probably not necessary to check for these
2554     if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2555       return false;
2556     }
2557   }
2558   return false;
2559 }
2560 
2561 // Check whether node n is a branch to an uncommon trap that we could
2562 // optimize as test with very high branch costs in case of going to
2563 // the uncommon trap. The code must be able to be recompiled to use
2564 // a cheaper test.
2565 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2566   // Don't do it for natives, adapters, or runtime stubs
2567   Compile *C = Compile::current();
2568   if (!C->is_method_compilation()) return false;
2569 
2570   assert(n->is_If(), "You should only call this on if nodes.");
2571   IfNode *ifn = n->as_If();
2572 
2573   Node *ifFalse = NULL;
2574   for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2575     if (ifn->fast_out(i)->is_IfFalse()) {
2576       ifFalse = ifn->fast_out(i);
2577       break;
2578     }
2579   }
2580   assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2581 
2582   Node *reg = ifFalse;
2583   int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
2584                // Alternatively use visited set?  Seems too expensive.
2585   while (reg != NULL && cnt > 0) {
2586     CallNode *call = NULL;
2587     RegionNode *nxt_reg = NULL;
2588     for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2589       Node *o = reg->fast_out(i);
2590       if (o->is_Call()) {
2591         call = o->as_Call();
2592       }
2593       if (o->is_Region()) {
2594         nxt_reg = o->as_Region();
2595       }
2596     }
2597 
2598     if (call &&
2599         call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2600       const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2601       if (trtype->isa_int() && trtype->is_int()->is_con()) {
2602         jint tr_con = trtype->is_int()->get_con();
2603         Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2604         Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2605         assert((int)reason < (int)BitsPerInt, "recode bit map");
2606 
2607         if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2608             && action != Deoptimization::Action_none) {
2609           // This uncommon trap is sure to recompile, eventually.
2610           // When that happens, C->too_many_traps will prevent
2611           // this transformation from happening again.
2612           return true;
2613         }
2614       }
2615     }
2616 
2617     reg = nxt_reg;
2618     cnt--;
2619   }
2620 
2621   return false;
2622 }
2623 
2624 //=============================================================================
2625 //---------------------------State---------------------------------------------
2626 State::State(void) {
2627 #ifdef ASSERT
2628   _id = 0;
2629   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2630   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2631   //memset(_cost, -1, sizeof(_cost));
2632   //memset(_rule, -1, sizeof(_rule));
2633 #endif
2634   memset(_valid, 0, sizeof(_valid));
2635 }
2636 
2637 #ifdef ASSERT
2638 State::~State() {
2639   _id = 99;
2640   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2641   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2642   memset(_cost, -3, sizeof(_cost));
2643   memset(_rule, -3, sizeof(_rule));
2644 }
2645 #endif
2646 
2647 #ifndef PRODUCT
2648 //---------------------------dump----------------------------------------------
2649 void State::dump() {
2650   tty->print("\n");
2651   dump(0);
2652 }
2653 
2654 void State::dump(int depth) {
2655   for( int j = 0; j < depth; j++ )
2656     tty->print("   ");
2657   tty->print("--N: ");
2658   _leaf->dump();
2659   uint i;
2660   for( i = 0; i < _LAST_MACH_OPER; i++ )
2661     // Check for valid entry
2662     if( valid(i) ) {
2663       for( int j = 0; j < depth; j++ )
2664         tty->print("   ");
2665         assert(_cost[i] != max_juint, "cost must be a valid value");
2666         assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2667         tty->print_cr("%s  %d  %s",
2668                       ruleName[i], _cost[i], ruleName[_rule[i]] );
2669       }
2670   tty->cr();
2671 
2672   for( i=0; i<2; i++ )
2673     if( _kids[i] )
2674       _kids[i]->dump(depth+1);
2675 }
2676 #endif