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src/hotspot/cpu/aarch64/assembler_aarch64.cpp

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170   void Assembler::adr(Register Rd, address adr) {
171     intptr_t offset = adr - pc();
172     int offset_lo = offset & 3;
173     offset >>= 2;
174     starti;
175     f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
176     rf(Rd, 0);
177   }
178 
179   void Assembler::_adrp(Register Rd, address adr) {
180     uint64_t pc_page = (uint64_t)pc() >> 12;
181     uint64_t adr_page = (uint64_t)adr >> 12;
182     intptr_t offset = adr_page - pc_page;
183     int offset_lo = offset & 3;
184     offset >>= 2;
185     starti;
186     f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
187     zrf(Rd, 0);
188   }
189 




















190 // An "all-purpose" add/subtract immediate, per ARM documentation:
191 // A "programmer-friendly" assembler may accept a negative immediate
192 // between -(2^24 -1) and -1 inclusive, causing it to convert a
193 // requested ADD operation to a SUB, or vice versa, and then encode
194 // the absolute value of the immediate as for uimm24.
195 void Assembler::add_sub_immediate(Instruction_aarch64 &current_insn,
196                                   Register Rd, Register Rn, unsigned uimm, int op,
197                                   int negated_op) {
198   bool sets_flags = op & 1;   // this op sets flags
199   union {
200     unsigned u;
201     int imm;
202   };
203   u = uimm;
204   bool shift = false;
205   bool neg = imm < 0;
206   if (neg) {
207     imm = -imm;
208     op = negated_op;
209   }

170   void Assembler::adr(Register Rd, address adr) {
171     intptr_t offset = adr - pc();
172     int offset_lo = offset & 3;
173     offset >>= 2;
174     starti;
175     f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
176     rf(Rd, 0);
177   }
178 
179   void Assembler::_adrp(Register Rd, address adr) {
180     uint64_t pc_page = (uint64_t)pc() >> 12;
181     uint64_t adr_page = (uint64_t)adr >> 12;
182     intptr_t offset = adr_page - pc_page;
183     int offset_lo = offset & 3;
184     offset >>= 2;
185     starti;
186     f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
187     zrf(Rd, 0);
188   }
189 
190 // This encoding is similar (but not quite identical) to the encoding used
191 // by literal ld/st. see JDK-8324123.
192 // PRFM does not support writeback or pre/post index.
193 void Assembler::prfm(const Address &adr, prfop pfop) {
194   Address::mode mode = adr.getMode();
195   // PRFM does not support pre/post index
196   guarantee((mode != Address::pre) && (mode != Address::post), "prfm does not support pre/post indexing");
197   if (mode == Address::literal) {
198     starti;
199     f(0b11, 31, 30), f(0b011, 29, 27), f(0b000, 26, 24);
200     f(pfop, 4, 0);
201     int64_t offset = (adr.target() - pc()) >> 2;
202     sf(offset, 23, 5);
203   } else {
204     assert((mode == Address::base_plus_offset)
205             || (mode == Address::base_plus_offset_reg), "must be base_plus_offset/base_plus_offset_reg");
206     ld_st2(as_Register(pfop), adr, 0b11, 0b10);
207   }
208 }
209 
210 // An "all-purpose" add/subtract immediate, per ARM documentation:
211 // A "programmer-friendly" assembler may accept a negative immediate
212 // between -(2^24 -1) and -1 inclusive, causing it to convert a
213 // requested ADD operation to a SUB, or vice versa, and then encode
214 // the absolute value of the immediate as for uimm24.
215 void Assembler::add_sub_immediate(Instruction_aarch64 &current_insn,
216                                   Register Rd, Register Rn, unsigned uimm, int op,
217                                   int negated_op) {
218   bool sets_flags = op & 1;   // this op sets flags
219   union {
220     unsigned u;
221     int imm;
222   };
223   u = uimm;
224   bool shift = false;
225   bool neg = imm < 0;
226   if (neg) {
227     imm = -imm;
228     op = negated_op;
229   }
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