1 /*
   2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
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  24  */
  25 
  26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/register.hpp"
  30 #include "metaprogramming/enableIf.hpp"
  31 #include "utilities/debug.hpp"
  32 #include "utilities/globalDefinitions.hpp"
  33 #include "utilities/macros.hpp"
  34 #include <type_traits>
  35 
  36 #ifdef __GNUC__
  37 
  38 // __nop needs volatile so that compiler doesn't optimize it away
  39 #define NOP() asm volatile ("nop");
  40 
  41 #elif defined(_MSC_VER)
  42 
  43 // Use MSVC intrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I
  44 #define NOP() __nop();
  45 
  46 #endif
  47 
  48 
  49 // definitions of various symbolic names for machine registers
  50 
  51 // First intercalls between C and Java which use 8 general registers
  52 // and 8 floating registers
  53 
  54 // we also have to copy between x86 and ARM registers but that's a
  55 // secondary complication -- not all code employing C call convention
  56 // executes as x86 code though -- we generate some of it
  57 
  58 class Argument {
  59  public:
  60   enum {
  61     n_int_register_parameters_c   = 8,  // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
  62     n_float_register_parameters_c = 8,  // v0, v1, ... v7 (c_farg0, c_farg1, ... )
  63 
  64     n_int_register_parameters_j   = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
  65     n_float_register_parameters_j = 8  // v0, v1, ... v7 (j_farg0, j_farg1, ...
  66   };
  67 };
  68 
  69 constexpr Register c_rarg0 = r0;
  70 constexpr Register c_rarg1 = r1;
  71 constexpr Register c_rarg2 = r2;
  72 constexpr Register c_rarg3 = r3;
  73 constexpr Register c_rarg4 = r4;
  74 constexpr Register c_rarg5 = r5;
  75 constexpr Register c_rarg6 = r6;
  76 constexpr Register c_rarg7 = r7;
  77 
  78 constexpr FloatRegister c_farg0 = v0;
  79 constexpr FloatRegister c_farg1 = v1;
  80 constexpr FloatRegister c_farg2 = v2;
  81 constexpr FloatRegister c_farg3 = v3;
  82 constexpr FloatRegister c_farg4 = v4;
  83 constexpr FloatRegister c_farg5 = v5;
  84 constexpr FloatRegister c_farg6 = v6;
  85 constexpr FloatRegister c_farg7 = v7;
  86 
  87 // Symbolically name the register arguments used by the Java calling convention.
  88 // We have control over the convention for java so we can do what we please.
  89 // What pleases us is to offset the java calling convention so that when
  90 // we call a suitable jni method the arguments are lined up and we don't
  91 // have to do much shuffling. A suitable jni method is non-static and a
  92 // small number of arguments
  93 //
  94 //  |--------------------------------------------------------------------|
  95 //  | c_rarg0  c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7  |
  96 //  |--------------------------------------------------------------------|
  97 //  | r0       r1       r2      r3      r4      r5      r6      r7       |
  98 //  |--------------------------------------------------------------------|
  99 //  | j_rarg7  j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6  |
 100 //  |--------------------------------------------------------------------|
 101 
 102 
 103 constexpr Register j_rarg0 = c_rarg1;
 104 constexpr Register j_rarg1 = c_rarg2;
 105 constexpr Register j_rarg2 = c_rarg3;
 106 constexpr Register j_rarg3 = c_rarg4;
 107 constexpr Register j_rarg4 = c_rarg5;
 108 constexpr Register j_rarg5 = c_rarg6;
 109 constexpr Register j_rarg6 = c_rarg7;
 110 constexpr Register j_rarg7 = c_rarg0;
 111 
 112 // Java floating args are passed as per C
 113 
 114 constexpr FloatRegister j_farg0 = v0;
 115 constexpr FloatRegister j_farg1 = v1;
 116 constexpr FloatRegister j_farg2 = v2;
 117 constexpr FloatRegister j_farg3 = v3;
 118 constexpr FloatRegister j_farg4 = v4;
 119 constexpr FloatRegister j_farg5 = v5;
 120 constexpr FloatRegister j_farg6 = v6;
 121 constexpr FloatRegister j_farg7 = v7;
 122 
 123 // registers used to hold VM data either temporarily within a method
 124 // or across method calls
 125 
 126 // volatile (caller-save) registers
 127 
 128 // r8 is used for indirect result location return
 129 // we use it and r9 as scratch registers
 130 constexpr Register rscratch1 = r8;
 131 constexpr Register rscratch2 = r9;
 132 
 133 // current method -- must be in a call-clobbered register
 134 constexpr Register rmethod = r12;
 135 
 136 // non-volatile (callee-save) registers are r16-29
 137 // of which the following are dedicated global state
 138 
 139 constexpr Register lr            = r30; // link register
 140 constexpr Register rfp           = r29; // frame pointer
 141 constexpr Register rthread       = r28; // current thread
 142 constexpr Register rheapbase     = r27; // base of heap
 143 constexpr Register rcpool        = r26; // constant pool cache
 144 constexpr Register rlocals       = r24; // locals on stack
 145 constexpr Register rbcp          = r22; // bytecode pointer
 146 constexpr Register rdispatch     = r21; // dispatch table base
 147 constexpr Register esp           = r20; // Java expression stack pointer
 148 constexpr Register r19_sender_sp = r19; // sender's SP while in interpreter
 149 
 150 // Preserved predicate register with all elements set TRUE.
 151 constexpr PRegister ptrue = p7;
 152 
 153 #define assert_cond(ARG1) assert(ARG1, #ARG1)
 154 
 155 namespace asm_util {
 156   uint32_t encode_logical_immediate(bool is32, uint64_t imm);
 157   uint32_t encode_sve_logical_immediate(unsigned elembits, uint64_t imm);
 158   bool operand_valid_for_immediate_bits(int64_t imm, unsigned nbits);
 159 };
 160 
 161 using namespace asm_util;
 162 
 163 
 164 class Assembler;
 165 
 166 class Instruction_aarch64 {
 167   unsigned insn;
 168 #ifdef ASSERT
 169   unsigned bits;
 170 #endif
 171   Assembler *assem;
 172 
 173 public:
 174 
 175   Instruction_aarch64(class Assembler *as) {
 176 #ifdef ASSERT
 177     bits = 0;
 178 #endif
 179     insn = 0;
 180     assem = as;
 181   }
 182 
 183   inline ~Instruction_aarch64();
 184 
 185   unsigned &get_insn() { return insn; }
 186 #ifdef ASSERT
 187   unsigned &get_bits() { return bits; }
 188 #endif
 189 
 190   static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
 191     union {
 192       unsigned u;
 193       int n;
 194     };
 195 
 196     u = val << (31 - hi);
 197     n = n >> (31 - hi + lo);
 198     return n;
 199   }
 200 
 201   static inline uint32_t extract(uint32_t val, int msb, int lsb) {
 202     int nbits = msb - lsb + 1;
 203     assert_cond(msb >= lsb);
 204     uint32_t mask = checked_cast<uint32_t>(right_n_bits(nbits));
 205     uint32_t result = val >> lsb;
 206     result &= mask;
 207     return result;
 208   }
 209 
 210   static inline int32_t sextract(uint32_t val, int msb, int lsb) {
 211     uint32_t uval = extract(val, msb, lsb);
 212     return extend(uval, msb - lsb);
 213   }
 214 
 215   static ALWAYSINLINE void patch(address a, int msb, int lsb, uint64_t val) {
 216     int nbits = msb - lsb + 1;
 217     guarantee(val < (1ULL << nbits), "Field too big for insn");
 218     assert_cond(msb >= lsb);
 219     unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
 220     val <<= lsb;
 221     mask <<= lsb;
 222     unsigned target = *(unsigned *)a;
 223     target &= ~mask;
 224     target |= val;
 225     *(unsigned *)a = target;
 226   }
 227 
 228   static void spatch(address a, int msb, int lsb, int64_t val) {
 229     int nbits = msb - lsb + 1;
 230     int64_t chk = val >> (nbits - 1);
 231     guarantee (chk == -1 || chk == 0, "Field too big for insn at " INTPTR_FORMAT, p2i(a));
 232     unsigned uval = val;
 233     unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
 234     uval &= mask;
 235     uval <<= lsb;
 236     mask <<= lsb;
 237     unsigned target = *(unsigned *)a;
 238     target &= ~mask;
 239     target |= uval;
 240     *(unsigned *)a = target;
 241   }
 242 
 243   void f(unsigned val, int msb, int lsb) {
 244     int nbits = msb - lsb + 1;
 245     guarantee(val < (1ULL << nbits), "Field too big for insn");
 246     assert_cond(msb >= lsb);
 247     val <<= lsb;
 248     insn |= val;
 249 #ifdef ASSERT
 250     unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
 251     mask <<= lsb;
 252     assert_cond((bits & mask) == 0);
 253     bits |= mask;
 254 #endif
 255   }
 256 
 257   void f(unsigned val, int bit) {
 258     f(val, bit, bit);
 259   }
 260 
 261   void sf(int64_t val, int msb, int lsb) {
 262     int nbits = msb - lsb + 1;
 263     int64_t chk = val >> (nbits - 1);
 264     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 265     unsigned uval = val;
 266     unsigned mask = checked_cast<unsigned>(right_n_bits(nbits));
 267     uval &= mask;
 268     f(uval, lsb + nbits - 1, lsb);
 269   }
 270 
 271   void rf(Register r, int lsb) {
 272     f(r->raw_encoding(), lsb + 4, lsb);
 273   }
 274 
 275   // reg|ZR
 276   void zrf(Register r, int lsb) {
 277     f(r->raw_encoding() - (r == zr), lsb + 4, lsb);
 278   }
 279 
 280   // reg|SP
 281   void srf(Register r, int lsb) {
 282     f(r == sp ? 31 : r->raw_encoding(), lsb + 4, lsb);
 283   }
 284 
 285   void rf(FloatRegister r, int lsb) {
 286     f(r->raw_encoding(), lsb + 4, lsb);
 287   }
 288 
 289   void prf(PRegister r, int lsb) {
 290     f(r->raw_encoding(), lsb + 3, lsb);
 291   }
 292 
 293   void pgrf(PRegister r, int lsb) {
 294     f(r->raw_encoding(), lsb + 2, lsb);
 295   }
 296 
 297   unsigned get(int msb = 31, int lsb = 0) {
 298     int nbits = msb - lsb + 1;
 299     unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)) << lsb;
 300     assert_cond((bits & mask) == mask);
 301     return (insn & mask) >> lsb;
 302   }
 303 };
 304 
 305 #define starti Instruction_aarch64 current_insn(this);
 306 
 307 class PrePost {
 308   int _offset;
 309   Register _r;
 310 protected:
 311   PrePost(Register reg, int o) : _offset(o), _r(reg) { }
 312   ~PrePost() = default;
 313   PrePost(const PrePost&) = default;
 314   PrePost& operator=(const PrePost&) = default;
 315 public:
 316   int offset() const { return _offset; }
 317   Register reg() const { return _r; }
 318 };
 319 
 320 class Pre : public PrePost {
 321 public:
 322   Pre(Register reg, int o) : PrePost(reg, o) { }
 323 };
 324 
 325 class Post : public PrePost {
 326   Register _idx;
 327   bool _is_postreg;
 328 public:
 329   Post(Register reg, int o) : PrePost(reg, o), _idx(noreg), _is_postreg(false) {}
 330   Post(Register reg, Register idx) : PrePost(reg, 0), _idx(idx), _is_postreg(true) {}
 331   Register idx_reg() const { return _idx; }
 332   bool is_postreg() const { return _is_postreg; }
 333 };
 334 
 335 namespace ext
 336 {
 337   enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
 338 };
 339 
 340 // Addressing modes
 341 class Address {
 342  public:
 343 
 344   enum mode { no_mode, base_plus_offset, pre, post, post_reg,
 345               base_plus_offset_reg, literal };
 346 
 347   // Shift and extend for base reg + reg offset addressing
 348   class extend {
 349     int _option, _shift;
 350     ext::operation _op;
 351   public:
 352     extend() { }
 353     extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
 354     int option() const{ return _option; }
 355     int shift() const { return _shift; }
 356     ext::operation op() const { return _op; }
 357   };
 358 
 359   static extend uxtw(int shift = -1) { return extend(shift, 0b010, ext::uxtw); }
 360   static extend lsl(int shift = -1)  { return extend(shift, 0b011, ext::uxtx); }
 361   static extend sxtw(int shift = -1) { return extend(shift, 0b110, ext::sxtw); }
 362   static extend sxtx(int shift = -1) { return extend(shift, 0b111, ext::sxtx); }
 363 
 364  private:
 365   struct Nonliteral {
 366     Nonliteral(Register base, Register index, int64_t offset, extend ext = extend())
 367       : _base(base), _index(index), _offset(offset), _ext(ext) {}
 368     Register _base;
 369     Register _index;
 370     int64_t _offset;
 371     extend _ext;
 372   };
 373 
 374   struct Literal {
 375     Literal(address target, const RelocationHolder& rspec)
 376       : _target(target), _rspec(rspec) {}
 377 
 378     // If the target is far we'll need to load the ea of this to a
 379     // register to reach it. Otherwise if near we can do PC-relative
 380     // addressing.
 381     address _target;
 382 
 383     RelocationHolder _rspec;
 384   };
 385 
 386   void assert_is_nonliteral() const NOT_DEBUG_RETURN;
 387   void assert_is_literal() const NOT_DEBUG_RETURN;
 388 
 389   // Discriminated union, based on _mode.
 390   // - no_mode: uses dummy _nonliteral, for ease of copying.
 391   // - literal: only _literal is used.
 392   // - others: only _nonliteral is used.
 393   enum mode _mode;
 394   union {
 395     Nonliteral _nonliteral;
 396     Literal _literal;
 397   };
 398 
 399   // Helper for copy constructor and assignment operator.
 400   // Copy mode-relevant part of a into this.
 401   void copy_data(const Address& a) {
 402     assert(_mode == a._mode, "precondition");
 403     if (_mode == literal) {
 404       new (&_literal) Literal(a._literal);
 405     } else {
 406       // non-literal mode or no_mode.
 407       new (&_nonliteral) Nonliteral(a._nonliteral);
 408     }
 409   }
 410 
 411  public:
 412   // no_mode initializes _nonliteral for ease of copying.
 413   Address() :
 414     _mode(no_mode),
 415     _nonliteral(noreg, noreg, 0)
 416   {}
 417 
 418   Address(Register r) :
 419     _mode(base_plus_offset),
 420     _nonliteral(r, noreg, 0)
 421   {}
 422 
 423   template<typename T, ENABLE_IF(std::is_integral<T>::value)>
 424   Address(Register r, T o) :
 425     _mode(base_plus_offset),
 426     _nonliteral(r, noreg, o)
 427   {}
 428 
 429   Address(Register r, ByteSize disp) : Address(r, in_bytes(disp)) {}
 430 
 431   Address(Register r, Register r1, extend ext = lsl()) :
 432     _mode(base_plus_offset_reg),
 433     _nonliteral(r, r1, 0, ext)
 434   {}
 435 
 436   Address(Pre p) :
 437     _mode(pre),
 438     _nonliteral(p.reg(), noreg, p.offset())
 439   {}
 440 
 441   Address(Post p) :
 442     _mode(p.is_postreg() ? post_reg : post),
 443     _nonliteral(p.reg(), p.idx_reg(), p.offset())
 444   {}
 445 
 446   Address(address target, const RelocationHolder& rspec) :
 447     _mode(literal),
 448     _literal(target, rspec)
 449   {}
 450 
 451   Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
 452 
 453   Address(Register base, RegisterOrConstant index, extend ext = lsl()) {
 454     if (index.is_register()) {
 455       _mode = base_plus_offset_reg;
 456       new (&_nonliteral) Nonliteral(base, index.as_register(), 0, ext);
 457     } else {
 458       guarantee(ext.option() == ext::uxtx, "should be");
 459       assert(index.is_constant(), "should be");
 460       _mode = base_plus_offset;
 461       new (&_nonliteral) Nonliteral(base,
 462                                     noreg,
 463                                     index.as_constant() << ext.shift());
 464     }
 465   }
 466 
 467   Address(const Address& a) : _mode(a._mode) { copy_data(a); }
 468 
 469   // Verify the value is trivially destructible regardless of mode, so our
 470   // destructor can also be trivial, and so our assignment operator doesn't
 471   // need to destruct the old value before copying over it.
 472   static_assert(std::is_trivially_destructible<Literal>::value, "must be");
 473   static_assert(std::is_trivially_destructible<Nonliteral>::value, "must be");
 474 
 475   Address& operator=(const Address& a) {
 476     _mode = a._mode;
 477     copy_data(a);
 478     return *this;
 479   }
 480 
 481   ~Address() = default;
 482 
 483   Register base() const {
 484     assert_is_nonliteral();
 485     return _nonliteral._base;
 486   }
 487 
 488   int64_t offset() const {
 489     assert_is_nonliteral();
 490     return _nonliteral._offset;
 491   }
 492 
 493   Register index() const {
 494     assert_is_nonliteral();
 495     return _nonliteral._index;
 496   }
 497 
 498   extend ext() const {
 499     assert_is_nonliteral();
 500     return _nonliteral._ext;
 501   }
 502 
 503   mode getMode() const {
 504     return _mode;
 505   }
 506 
 507   bool uses(Register reg) const {
 508     switch (_mode) {
 509     case literal:
 510     case no_mode:
 511       return false;
 512     case base_plus_offset:
 513     case base_plus_offset_reg:
 514     case pre:
 515     case post:
 516     case post_reg:
 517       return base() == reg || index() == reg;
 518     default:
 519       ShouldNotReachHere();
 520       return false;
 521     }
 522   }
 523 
 524   address target() const {
 525     assert_is_literal();
 526     return _literal._target;
 527   }
 528 
 529   const RelocationHolder& rspec() const {
 530     assert_is_literal();
 531     return _literal._rspec;
 532   }
 533 
 534   void encode(Instruction_aarch64 *i) const {
 535     i->f(0b111, 29, 27);
 536     i->srf(base(), 5);
 537 
 538     switch(_mode) {
 539     case base_plus_offset:
 540       {
 541         unsigned size = i->get(31, 30);
 542         if (i->get(26, 26) && i->get(23, 23)) {
 543           // SIMD Q Type - Size = 128 bits
 544           assert(size == 0, "bad size");
 545           size = 0b100;
 546         }
 547         assert(offset_ok_for_immed(offset(), size),
 548                "must be, was: " INT64_FORMAT ", %d", offset(), size);
 549         unsigned mask = (1 << size) - 1;
 550         if (offset() < 0 || offset() & mask) {
 551           i->f(0b00, 25, 24);
 552           i->f(0, 21), i->f(0b00, 11, 10);
 553           i->sf(offset(), 20, 12);
 554         } else {
 555           i->f(0b01, 25, 24);
 556           i->f(offset() >> size, 21, 10);
 557         }
 558       }
 559       break;
 560 
 561     case base_plus_offset_reg:
 562       {
 563         i->f(0b00, 25, 24);
 564         i->f(1, 21);
 565         i->rf(index(), 16);
 566         i->f(ext().option(), 15, 13);
 567         unsigned size = i->get(31, 30);
 568         if (i->get(26, 26) && i->get(23, 23)) {
 569           // SIMD Q Type - Size = 128 bits
 570           assert(size == 0, "bad size");
 571           size = 0b100;
 572         }
 573         if (size == 0) // It's a byte
 574           i->f(ext().shift() >= 0, 12);
 575         else {
 576           assert(ext().shift() <= 0 || ext().shift() == (int)size, "bad shift");
 577           i->f(ext().shift() > 0, 12);
 578         }
 579         i->f(0b10, 11, 10);
 580       }
 581       break;
 582 
 583     case pre:
 584       i->f(0b00, 25, 24);
 585       i->f(0, 21), i->f(0b11, 11, 10);
 586       i->sf(offset(), 20, 12);
 587       break;
 588 
 589     case post:
 590       i->f(0b00, 25, 24);
 591       i->f(0, 21), i->f(0b01, 11, 10);
 592       i->sf(offset(), 20, 12);
 593       break;
 594 
 595     default:
 596       ShouldNotReachHere();
 597     }
 598   }
 599 
 600   void encode_pair(Instruction_aarch64 *i) const {
 601     switch(_mode) {
 602     case base_plus_offset:
 603       i->f(0b010, 25, 23);
 604       break;
 605     case pre:
 606       i->f(0b011, 25, 23);
 607       break;
 608     case post:
 609       i->f(0b001, 25, 23);
 610       break;
 611     default:
 612       ShouldNotReachHere();
 613     }
 614 
 615     unsigned size; // Operand shift in 32-bit words
 616 
 617     if (i->get(26, 26)) { // float
 618       switch(i->get(31, 30)) {
 619       case 0b10:
 620         size = 2; break;
 621       case 0b01:
 622         size = 1; break;
 623       case 0b00:
 624         size = 0; break;
 625       default:
 626         ShouldNotReachHere();
 627         size = 0;  // unreachable
 628       }
 629     } else {
 630       size = i->get(31, 31);
 631     }
 632 
 633     size = 4 << size;
 634     guarantee(offset() % size == 0, "bad offset");
 635     i->sf(offset() / size, 21, 15);
 636     i->srf(base(), 5);
 637   }
 638 
 639   void encode_nontemporal_pair(Instruction_aarch64 *i) const {
 640     guarantee(_mode == base_plus_offset, "Bad addressing mode for nontemporal op");
 641     i->f(0b000, 25, 23);
 642     unsigned size = i->get(31, 31);
 643     size = 4 << size;
 644     guarantee(offset() % size == 0, "bad offset");
 645     i->sf(offset() / size, 21, 15);
 646     i->srf(base(), 5);
 647   }
 648 
 649   void lea(MacroAssembler *, Register) const;
 650 
 651   static bool offset_ok_for_immed(int64_t offset, uint shift);
 652 
 653   static bool offset_ok_for_sve_immed(int64_t offset, int shift, int vl /* sve vector length */) {
 654     if (offset % vl == 0) {
 655       // Convert address offset into sve imm offset (MUL VL).
 656       int sve_offset = offset / vl;
 657       if (((-(1 << (shift - 1))) <= sve_offset) && (sve_offset < (1 << (shift - 1)))) {
 658         // sve_offset can be encoded
 659         return true;
 660       }
 661     }
 662     return false;
 663   }
 664 };
 665 
 666 // Convenience classes
 667 class RuntimeAddress: public Address {
 668 
 669   public:
 670 
 671   RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
 672 
 673 };
 674 
 675 class OopAddress: public Address {
 676 
 677   public:
 678 
 679   OopAddress(address target) : Address(target, relocInfo::oop_type){}
 680 
 681 };
 682 
 683 class ExternalAddress: public Address {
 684  private:
 685   static relocInfo::relocType reloc_for_target(address target) {
 686     // Sometimes ExternalAddress is used for values which aren't
 687     // exactly addresses, like the card table base.
 688     // external_word_type can't be used for values in the first page
 689     // so just skip the reloc in that case.
 690     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 691   }
 692 
 693  public:
 694 
 695   ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
 696 
 697 };
 698 
 699 class InternalAddress: public Address {
 700 
 701   public:
 702 
 703   InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
 704 };
 705 
 706 const int FPUStateSizeInWords = FloatRegister::number_of_registers * FloatRegister::save_slots_per_register;
 707 
 708 typedef enum {
 709   PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
 710   PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
 711   PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
 712 } prfop;
 713 
 714 class Assembler : public AbstractAssembler {
 715 
 716 public:
 717 
 718 #ifndef PRODUCT
 719   static const uintptr_t asm_bp;
 720 
 721   void emit_int32(jint x) {
 722     if ((uintptr_t)pc() == asm_bp)
 723       NOP();
 724     AbstractAssembler::emit_int32(x);
 725   }
 726 #else
 727   void emit_int32(jint x) {
 728     AbstractAssembler::emit_int32(x);
 729   }
 730 #endif
 731 
 732   enum { instruction_size = 4 };
 733 
 734   //---<  calculate length of instruction  >---
 735   // We just use the values set above.
 736   // instruction must start at passed address
 737   static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
 738 
 739   //---<  longest instructions  >---
 740   static unsigned int instr_maxlen() { return instruction_size; }
 741 
 742   Address adjust(Register base, int offset, bool preIncrement) {
 743     if (preIncrement)
 744       return Address(Pre(base, offset));
 745     else
 746       return Address(Post(base, offset));
 747   }
 748 
 749   Address pre(Register base, int offset) {
 750     return adjust(base, offset, true);
 751   }
 752 
 753   Address post(Register base, int offset) {
 754     return adjust(base, offset, false);
 755   }
 756 
 757   Address post(Register base, Register idx) {
 758     return Address(Post(base, idx));
 759   }
 760 
 761   static address locate_next_instruction(address inst);
 762 
 763 #define f current_insn.f
 764 #define sf current_insn.sf
 765 #define rf current_insn.rf
 766 #define srf current_insn.srf
 767 #define zrf current_insn.zrf
 768 #define prf current_insn.prf
 769 #define pgrf current_insn.pgrf
 770 
 771   typedef void (Assembler::* uncond_branch_insn)(address dest);
 772   typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
 773   typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
 774   typedef void (Assembler::* prefetch_insn)(address target, prfop);
 775 
 776   void wrap_label(Label &L, uncond_branch_insn insn);
 777   void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
 778   void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
 779   void wrap_label(Label &L, prfop, prefetch_insn insn);
 780 
 781   // PC-rel. addressing
 782 
 783   void adr(Register Rd, address dest);
 784   void _adrp(Register Rd, address dest);
 785 
 786   void adr(Register Rd, const Address &dest);
 787   void _adrp(Register Rd, const Address &dest);
 788 
 789   void adr(Register Rd, Label &L) {
 790     wrap_label(Rd, L, &Assembler::Assembler::adr);
 791   }
 792   void _adrp(Register Rd, Label &L) {
 793     wrap_label(Rd, L, &Assembler::_adrp);
 794   }
 795 
 796   void adrp(Register Rd, const Address &dest, uint64_t &offset) = delete;
 797 
 798   void prfm(const Address &adr, prfop pfop = PLDL1KEEP);
 799 
 800 #undef INSN
 801 
 802   void add_sub_immediate(Instruction_aarch64 &current_insn, Register Rd, Register Rn,
 803                          unsigned uimm, int op, int negated_op);
 804 
 805   // Add/subtract (immediate)
 806 #define INSN(NAME, decode, negated)                                     \
 807   void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
 808     starti;                                                             \
 809     f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
 810     zrf(Rd, 0), srf(Rn, 5);                                             \
 811   }                                                                     \
 812                                                                         \
 813   void NAME(Register Rd, Register Rn, unsigned imm) {                   \
 814     starti;                                                             \
 815     add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated);      \
 816   }
 817 
 818   INSN(addsw, 0b001, 0b011);
 819   INSN(subsw, 0b011, 0b001);
 820   INSN(adds,  0b101, 0b111);
 821   INSN(subs,  0b111, 0b101);
 822 
 823 #undef INSN
 824 
 825 #define INSN(NAME, decode, negated)                     \
 826   void NAME(Register Rd, Register Rn, unsigned imm) {   \
 827     starti;                                             \
 828     add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated);     \
 829   }
 830 
 831   INSN(addw, 0b000, 0b010);
 832   INSN(subw, 0b010, 0b000);
 833   INSN(add,  0b100, 0b110);
 834   INSN(sub,  0b110, 0b100);
 835 
 836 #undef INSN
 837 
 838  // Logical (immediate)
 839 #define INSN(NAME, decode, is32)                                \
 840   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 841     starti;                                                     \
 842     uint32_t val = encode_logical_immediate(is32, imm);         \
 843     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 844     srf(Rd, 0), zrf(Rn, 5);                                     \
 845   }
 846 
 847   INSN(andw, 0b000, true);
 848   INSN(orrw, 0b001, true);
 849   INSN(eorw, 0b010, true);
 850   INSN(andr, 0b100, false);
 851   INSN(orr,  0b101, false);
 852   INSN(eor,  0b110, false);
 853 
 854 #undef INSN
 855 
 856 #define INSN(NAME, decode, is32)                                \
 857   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 858     starti;                                                     \
 859     uint32_t val = encode_logical_immediate(is32, imm);         \
 860     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 861     zrf(Rd, 0), zrf(Rn, 5);                                     \
 862   }
 863 
 864   INSN(ands, 0b111, false);
 865   INSN(andsw, 0b011, true);
 866 
 867 #undef INSN
 868 
 869   // Move wide (immediate)
 870 #define INSN(NAME, opcode)                                              \
 871   void NAME(Register Rd, unsigned imm, unsigned shift = 0) {            \
 872     assert_cond((shift/16)*16 == shift);                                \
 873     starti;                                                             \
 874     f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21),        \
 875       f(imm, 20, 5);                                                    \
 876     zrf(Rd, 0);                                                         \
 877   }
 878 
 879   INSN(movnw, 0b000);
 880   INSN(movzw, 0b010);
 881   INSN(movkw, 0b011);
 882   INSN(movn,  0b100);
 883   INSN(movz,  0b110);
 884   INSN(movk,  0b111);
 885 
 886 #undef INSN
 887 
 888   // Bitfield
 889 #define INSN(NAME, opcode, size)                                        \
 890   void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) {   \
 891     starti;                                                             \
 892     guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
 893     f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10);                \
 894     zrf(Rn, 5), rf(Rd, 0);                                              \
 895   }
 896 
 897   INSN(sbfmw, 0b0001001100, 0);
 898   INSN(bfmw,  0b0011001100, 0);
 899   INSN(ubfmw, 0b0101001100, 0);
 900   INSN(sbfm,  0b1001001101, 1);
 901   INSN(bfm,   0b1011001101, 1);
 902   INSN(ubfm,  0b1101001101, 1);
 903 
 904 #undef INSN
 905 
 906   // Extract
 907 #define INSN(NAME, opcode, size)                                        \
 908   void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) {     \
 909     starti;                                                             \
 910     guarantee(size == 1 || imms < 32, "incorrect imms");                \
 911     f(opcode, 31, 21), f(imms, 15, 10);                                 \
 912     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
 913   }
 914 
 915   INSN(extrw, 0b00010011100, 0);
 916   INSN(extr,  0b10010011110, 1);
 917 
 918 #undef INSN
 919 
 920   // The maximum range of a branch is fixed for the AArch64
 921   // architecture.  In debug mode we shrink it in order to test
 922   // trampolines, but not so small that branches in the interpreter
 923   // are out of range.
 924   static const uint64_t branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
 925 
 926   static bool reachable_from_branch_at(address branch, address target) {
 927     return uabs(target - branch) < branch_range;
 928   }
 929 
 930   // Unconditional branch (immediate)
 931 #define INSN(NAME, opcode)                                              \
 932   void NAME(address dest) {                                             \
 933     starti;                                                             \
 934     int64_t offset = (dest - pc()) >> 2;                                \
 935     DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
 936     f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0);               \
 937   }                                                                     \
 938   void NAME(Label &L) {                                                 \
 939     wrap_label(L, &Assembler::NAME);                                    \
 940   }                                                                     \
 941   void NAME(const Address &dest);
 942 
 943   INSN(b, 0);
 944   INSN(bl, 1);
 945 
 946 #undef INSN
 947 
 948   // Compare & branch (immediate)
 949 #define INSN(NAME, opcode)                              \
 950   void NAME(Register Rt, address dest) {                \
 951     int64_t offset = (dest - pc()) >> 2;                \
 952     starti;                                             \
 953     f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0);    \
 954   }                                                     \
 955   void NAME(Register Rt, Label &L) {                    \
 956     wrap_label(Rt, L, &Assembler::NAME);                \
 957   }
 958 
 959   INSN(cbzw,  0b00110100);
 960   INSN(cbnzw, 0b00110101);
 961   INSN(cbz,   0b10110100);
 962   INSN(cbnz,  0b10110101);
 963 
 964 #undef INSN
 965 
 966   // Test & branch (immediate)
 967 #define INSN(NAME, opcode)                                              \
 968   void NAME(Register Rt, int bitpos, address dest) {                    \
 969     int64_t offset = (dest - pc()) >> 2;                                \
 970     int b5 = bitpos >> 5;                                               \
 971     bitpos &= 0x1f;                                                     \
 972     starti;                                                             \
 973     f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
 974     rf(Rt, 0);                                                          \
 975   }                                                                     \
 976   void NAME(Register Rt, int bitpos, Label &L) {                        \
 977     wrap_label(Rt, bitpos, L, &Assembler::NAME);                        \
 978   }
 979 
 980   INSN(tbz,  0b0110110);
 981   INSN(tbnz, 0b0110111);
 982 
 983 #undef INSN
 984 
 985   // Conditional branch (immediate)
 986   enum Condition
 987     {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
 988 
 989   void br(Condition  cond, address dest) {
 990     int64_t offset = (dest - pc()) >> 2;
 991     starti;
 992     f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
 993   }
 994 
 995 #define INSN(NAME, cond)                        \
 996   void NAME(address dest) {                     \
 997     br(cond, dest);                             \
 998   }
 999 
1000   INSN(beq, EQ);
1001   INSN(bne, NE);
1002   INSN(bhs, HS);
1003   INSN(bcs, CS);
1004   INSN(blo, LO);
1005   INSN(bcc, CC);
1006   INSN(bmi, MI);
1007   INSN(bpl, PL);
1008   INSN(bvs, VS);
1009   INSN(bvc, VC);
1010   INSN(bhi, HI);
1011   INSN(bls, LS);
1012   INSN(bge, GE);
1013   INSN(blt, LT);
1014   INSN(bgt, GT);
1015   INSN(ble, LE);
1016   INSN(bal, AL);
1017   INSN(bnv, NV);
1018 
1019   void br(Condition cc, Label &L);
1020 
1021 #undef INSN
1022 
1023   // Exception generation
1024   void generate_exception(int opc, int op2, int LL, unsigned imm) {
1025     starti;
1026     f(0b11010100, 31, 24);
1027     f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
1028   }
1029 
1030 #define INSN(NAME, opc, op2, LL)                \
1031   void NAME(unsigned imm) {                     \
1032     generate_exception(opc, op2, LL, imm);      \
1033   }
1034 
1035   INSN(svc, 0b000, 0, 0b01);
1036   INSN(hvc, 0b000, 0, 0b10);
1037   INSN(smc, 0b000, 0, 0b11);
1038   INSN(brk, 0b001, 0, 0b00);
1039   INSN(hlt, 0b010, 0, 0b00);
1040   INSN(dcps1, 0b101, 0, 0b01);
1041   INSN(dcps2, 0b101, 0, 0b10);
1042   INSN(dcps3, 0b101, 0, 0b11);
1043 
1044 #undef INSN
1045 
1046   // System
1047   void system(int op0, int op1, int CRn, int CRm, int op2,
1048               Register rt = dummy_reg)
1049   {
1050     starti;
1051     f(0b11010101000, 31, 21);
1052     f(op0, 20, 19);
1053     f(op1, 18, 16);
1054     f(CRn, 15, 12);
1055     f(CRm, 11, 8);
1056     f(op2, 7, 5);
1057     rf(rt, 0);
1058   }
1059 
1060   // Hint instructions
1061 
1062 #define INSN(NAME, crm, op2)               \
1063   void NAME() {                            \
1064     system(0b00, 0b011, 0b0010, crm, op2); \
1065   }
1066 
1067   INSN(nop,   0b000, 0b0000);
1068   INSN(yield, 0b000, 0b0001);
1069   INSN(wfe,   0b000, 0b0010);
1070   INSN(wfi,   0b000, 0b0011);
1071   INSN(sev,   0b000, 0b0100);
1072   INSN(sevl,  0b000, 0b0101);
1073 
1074   INSN(autia1716, 0b0001, 0b100);
1075   INSN(autiasp,   0b0011, 0b101);
1076   INSN(autiaz,    0b0011, 0b100);
1077   INSN(autib1716, 0b0001, 0b110);
1078   INSN(autibsp,   0b0011, 0b111);
1079   INSN(autibz,    0b0011, 0b110);
1080   INSN(pacia1716, 0b0001, 0b000);
1081   INSN(paciasp,   0b0011, 0b001);
1082   INSN(paciaz,    0b0011, 0b000);
1083   INSN(pacib1716, 0b0001, 0b010);
1084   INSN(pacibsp,   0b0011, 0b011);
1085   INSN(pacibz,    0b0011, 0b010);
1086   INSN(xpaclri,   0b0000, 0b111);
1087 
1088 #undef INSN
1089 
1090   // we only provide mrs and msr for the special purpose system
1091   // registers where op1 (instr[20:19]) == 11 and, (currently) only
1092   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1093 
1094   void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1095     starti;
1096     f(0b1101010100011, 31, 19);
1097     f(op1, 18, 16);
1098     f(CRn, 15, 12);
1099     f(CRm, 11, 8);
1100     f(op2, 7, 5);
1101     // writing zr is ok
1102     zrf(rt, 0);
1103   }
1104 
1105   void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1106     starti;
1107     f(0b1101010100111, 31, 19);
1108     f(op1, 18, 16);
1109     f(CRn, 15, 12);
1110     f(CRm, 11, 8);
1111     f(op2, 7, 5);
1112     // reading to zr is a mistake
1113     rf(rt, 0);
1114   }
1115 
1116   enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1117                 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1118 
1119   void dsb(barrier imm) {
1120     system(0b00, 0b011, 0b00011, imm, 0b100);
1121   }
1122 
1123   void dmb(barrier imm) {
1124     system(0b00, 0b011, 0b00011, imm, 0b101);
1125   }
1126 
1127   void isb() {
1128     system(0b00, 0b011, 0b00011, SY, 0b110);
1129   }
1130 
1131   void sys(int op1, int CRn, int CRm, int op2,
1132            Register rt = as_Register(0b11111)) {
1133     system(0b01, op1, CRn, CRm, op2, rt);
1134   }
1135 
1136   // Only implement operations accessible from EL0 or higher, i.e.,
1137   //            op1    CRn    CRm    op2
1138   // IC IVAU     3      7      5      1
1139   // DC CVAC     3      7      10     1
1140   // DC CVAP     3      7      12     1
1141   // DC CVAU     3      7      11     1
1142   // DC CIVAC    3      7      14     1
1143   // DC ZVA      3      7      4      1
1144   // So only deal with the CRm field.
1145   enum icache_maintenance {IVAU = 0b0101};
1146   enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1147 
1148   void dc(dcache_maintenance cm, Register Rt) {
1149     sys(0b011, 0b0111, cm, 0b001, Rt);
1150   }
1151 
1152   void ic(icache_maintenance cm, Register Rt) {
1153     sys(0b011, 0b0111, cm, 0b001, Rt);
1154   }
1155 
1156   // A more convenient access to dmb for our purposes
1157   enum Membar_mask_bits {
1158     // We can use ISH for a barrier because the Arm ARM says "This
1159     // architecture assumes that all Processing Elements that use the
1160     // same operating system or hypervisor are in the same Inner
1161     // Shareable shareability domain."
1162     StoreStore = ISHST,
1163     LoadStore  = ISHLD,
1164     LoadLoad   = ISHLD,
1165     StoreLoad  = ISH,
1166     AnyAny     = ISH
1167   };
1168 
1169   void membar(Membar_mask_bits order_constraint) {
1170     dmb(Assembler::barrier(order_constraint));
1171   }
1172 
1173   // Unconditional branch (register)
1174 
1175   void branch_reg(int OP, int A, int M, Register RN, Register RM) {
1176     starti;
1177     f(0b1101011, 31, 25);
1178     f(OP, 24, 21);
1179     f(0b111110000, 20, 12);
1180     f(A, 11, 11);
1181     f(M, 10, 10);
1182     rf(RN, 5);
1183     rf(RM, 0);
1184   }
1185 
1186 #define INSN(NAME, opc)                         \
1187   void NAME(Register RN) {                      \
1188     branch_reg(opc, 0, 0, RN, r0);              \
1189   }
1190 
1191   INSN(br,  0b0000);
1192   INSN(blr, 0b0001);
1193   INSN(ret, 0b0010);
1194 
1195   void ret(void *p); // This forces a compile-time error for ret(0)
1196 
1197 #undef INSN
1198 
1199 #define INSN(NAME, opc)                         \
1200   void NAME() {                                 \
1201     branch_reg(opc, 0, 0, dummy_reg, r0);       \
1202   }
1203 
1204   INSN(eret, 0b0100);
1205   INSN(drps, 0b0101);
1206 
1207 #undef INSN
1208 
1209 #define INSN(NAME, M)                                  \
1210   void NAME() {                                        \
1211     branch_reg(0b0010, 1, M, dummy_reg, dummy_reg);    \
1212   }
1213 
1214   INSN(retaa, 0);
1215   INSN(retab, 1);
1216 
1217 #undef INSN
1218 
1219 #define INSN(NAME, OP, M)                   \
1220   void NAME(Register rn) {                  \
1221     branch_reg(OP, 1, M, rn, dummy_reg);    \
1222   }
1223 
1224   INSN(braaz,  0b0000, 0);
1225   INSN(brabz,  0b0000, 1);
1226   INSN(blraaz, 0b0001, 0);
1227   INSN(blrabz, 0b0001, 1);
1228 
1229 #undef INSN
1230 
1231 #define INSN(NAME, OP, M)                  \
1232   void NAME(Register rn, Register rm) {    \
1233     branch_reg(OP, 1, M, rn, rm);          \
1234   }
1235 
1236   INSN(braa,  0b1000, 0);
1237   INSN(brab,  0b1000, 1);
1238   INSN(blraa, 0b1001, 0);
1239   INSN(blrab, 0b1001, 1);
1240 
1241 #undef INSN
1242 
1243   // Load/store exclusive
1244   enum operand_size { byte, halfword, word, xword };
1245 
1246   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1247     Register Rn, enum operand_size sz, int op, bool ordered) {
1248     starti;
1249     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1250     rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1251   }
1252 
1253   void load_exclusive(Register dst, Register addr,
1254                       enum operand_size sz, bool ordered) {
1255     load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1256                          sz, 0b010, ordered);
1257   }
1258 
1259   void store_exclusive(Register status, Register new_val, Register addr,
1260                        enum operand_size sz, bool ordered) {
1261     load_store_exclusive(status, new_val, dummy_reg, addr,
1262                          sz, 0b000, ordered);
1263   }
1264 
1265 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
1266   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
1267     guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1268     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
1269   }
1270 
1271 #define INSN3(NAME, sz, op, o0) /* Three registers */                   \
1272   void NAME(Register Rs, Register Rt, Register Rn) {                    \
1273     guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction");       \
1274     load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1275   }
1276 
1277 #define INSN2(NAME, sz, op, o0) /* Two registers */                     \
1278   void NAME(Register Rt, Register Rn) {                                 \
1279     load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1280                          Rn, sz, op, o0);                               \
1281   }
1282 
1283 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1284   void NAME(Register Rt1, Register Rt2, Register Rn) {                  \
1285     guarantee(Rt1 != Rt2, "unpredictable instruction");                 \
1286     load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0);          \
1287   }
1288 
1289   // bytes
1290   INSN3(stxrb,  byte, 0b000, 0);
1291   INSN3(stlxrb, byte, 0b000, 1);
1292   INSN2(ldxrb,  byte, 0b010, 0);
1293   INSN2(ldaxrb, byte, 0b010, 1);
1294   INSN2(stlrb,  byte, 0b100, 1);
1295   INSN2(ldarb,  byte, 0b110, 1);
1296 
1297   // halfwords
1298   INSN3(stxrh,  halfword, 0b000, 0);
1299   INSN3(stlxrh, halfword, 0b000, 1);
1300   INSN2(ldxrh,  halfword, 0b010, 0);
1301   INSN2(ldaxrh, halfword, 0b010, 1);
1302   INSN2(stlrh,  halfword, 0b100, 1);
1303   INSN2(ldarh,  halfword, 0b110, 1);
1304 
1305   // words
1306   INSN3(stxrw,  word, 0b000, 0);
1307   INSN3(stlxrw, word, 0b000, 1);
1308   INSN4(stxpw,  word, 0b001, 0);
1309   INSN4(stlxpw, word, 0b001, 1);
1310   INSN2(ldxrw,  word, 0b010, 0);
1311   INSN2(ldaxrw, word, 0b010, 1);
1312   INSN2(stlrw,  word, 0b100, 1);
1313   INSN2(ldarw,  word, 0b110, 1);
1314   // pairs of words
1315   INSN_FOO(ldxpw,  word, 0b011, 0);
1316   INSN_FOO(ldaxpw, word, 0b011, 1);
1317 
1318   // xwords
1319   INSN3(stxr,  xword, 0b000, 0);
1320   INSN3(stlxr, xword, 0b000, 1);
1321   INSN4(stxp,  xword, 0b001, 0);
1322   INSN4(stlxp, xword, 0b001, 1);
1323   INSN2(ldxr,  xword, 0b010, 0);
1324   INSN2(ldaxr, xword, 0b010, 1);
1325   INSN2(stlr,  xword, 0b100, 1);
1326   INSN2(ldar,  xword, 0b110, 1);
1327   // pairs of xwords
1328   INSN_FOO(ldxp,  xword, 0b011, 0);
1329   INSN_FOO(ldaxp, xword, 0b011, 1);
1330 
1331 #undef INSN2
1332 #undef INSN3
1333 #undef INSN4
1334 #undef INSN_FOO
1335 
1336   // 8.1 Compare and swap extensions
1337   void lse_cas(Register Rs, Register Rt, Register Rn,
1338                         enum operand_size sz, bool a, bool r, bool not_pair) {
1339     starti;
1340     if (! not_pair) { // Pair
1341       assert(sz == word || sz == xword, "invalid size");
1342       /* The size bit is in bit 30, not 31 */
1343       sz = (operand_size)(sz == word ? 0b00:0b01);
1344     }
1345     f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1346     zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1347   }
1348 
1349   // CAS
1350 #define INSN(NAME, a, r)                                                \
1351   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1352     assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
1353     lse_cas(Rs, Rt, Rn, sz, a, r, true);                                \
1354   }
1355   INSN(cas,   false, false)
1356   INSN(casa,  true,  false)
1357   INSN(casl,  false, true)
1358   INSN(casal, true,  true)
1359 #undef INSN
1360 
1361   // CASP
1362 #define INSN(NAME, a, r)                                                \
1363   void NAME(operand_size sz, Register Rs, Register Rs1,                 \
1364             Register Rt, Register Rt1, Register Rn) {                   \
1365     assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 &&    \
1366            Rs->successor() == Rs1 && Rt->successor() == Rt1 &&          \
1367            Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers");     \
1368     lse_cas(Rs, Rt, Rn, sz, a, r, false);                               \
1369   }
1370   INSN(casp,   false, false)
1371   INSN(caspa,  true,  false)
1372   INSN(caspl,  false, true)
1373   INSN(caspal, true,  true)
1374 #undef INSN
1375 
1376   // 8.1 Atomic operations
1377   void lse_atomic(Register Rs, Register Rt, Register Rn,
1378                   enum operand_size sz, int op1, int op2, bool a, bool r) {
1379     starti;
1380     f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1381     zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1382   }
1383 
1384 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2)                   \
1385   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1386     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false);                 \
1387   }                                                                     \
1388   void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1389     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false);                  \
1390   }                                                                     \
1391   void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1392     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true);                  \
1393   }                                                                     \
1394   void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1395     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true);                   \
1396   }
1397   INSN(ldadd,  ldadda,  ldaddl,  ldaddal,  0, 0b000);
1398   INSN(ldbic,  ldbica,  ldbicl,  ldbical,  0, 0b001);
1399   INSN(ldeor,  ldeora,  ldeorl,  ldeoral,  0, 0b010);
1400   INSN(ldorr,  ldorra,  ldorrl,  ldorral,  0, 0b011);
1401   INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1402   INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1403   INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1404   INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1405   INSN(swp,    swpa,    swpl,    swpal,    1, 0b000);
1406 #undef INSN
1407 
1408   // Load register (literal)
1409 #define INSN(NAME, opc, V)                                              \
1410   void NAME(Register Rt, address dest) {                                \
1411     int64_t offset = (dest - pc()) >> 2;                                \
1412     starti;                                                             \
1413     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1414       sf(offset, 23, 5);                                                \
1415     rf(Rt, 0);                                                          \
1416   }                                                                     \
1417   void NAME(Register Rt, address dest, relocInfo::relocType rtype) {    \
1418     InstructionMark im(this);                                           \
1419     guarantee(rtype == relocInfo::internal_word_type,                   \
1420               "only internal_word_type relocs make sense here");        \
1421     code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1422     NAME(Rt, dest);                                                     \
1423   }                                                                     \
1424   void NAME(Register Rt, Label &L) {                                    \
1425     wrap_label(Rt, L, &Assembler::NAME);                                \
1426   }
1427 
1428   INSN(ldrw, 0b00, 0);
1429   INSN(ldr, 0b01, 0);
1430   INSN(ldrsw, 0b10, 0);
1431 
1432 #undef INSN
1433 
1434 #define INSN(NAME, opc, V)                                              \
1435   void NAME(FloatRegister Rt, address dest) {                           \
1436     int64_t offset = (dest - pc()) >> 2;                                \
1437     starti;                                                             \
1438     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1439       sf(offset, 23, 5);                                                \
1440     rf(as_Register(Rt), 0);                                             \
1441   }
1442 
1443   INSN(ldrs, 0b00, 1);
1444   INSN(ldrd, 0b01, 1);
1445   INSN(ldrq, 0b10, 1);
1446 
1447 #undef INSN
1448 
1449 #define INSN(NAME, size, opc)                                           \
1450   void NAME(FloatRegister Rt, Register Rn) {                            \
1451     starti;                                                             \
1452     f(size, 31, 30), f(0b111100, 29, 24), f(opc, 23, 22), f(0, 21);     \
1453     f(0, 20, 12), f(0b01, 11, 10);                                      \
1454     rf(Rn, 5), rf(as_Register(Rt), 0);                                  \
1455   }
1456 
1457   INSN(ldrs, 0b10, 0b01);
1458   INSN(ldrd, 0b11, 0b01);
1459   INSN(ldrq, 0b00, 0b11);
1460 
1461 #undef INSN
1462 
1463 
1464 #define INSN(NAME, opc, V)                                              \
1465   void NAME(address dest, prfop op = PLDL1KEEP) {                       \
1466     int64_t offset = (dest - pc()) >> 2;                                \
1467     starti;                                                             \
1468     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1469       sf(offset, 23, 5);                                                \
1470     f(op, 4, 0);                                                        \
1471   }                                                                     \
1472   void NAME(Label &L, prfop op = PLDL1KEEP) {                           \
1473     wrap_label(L, op, &Assembler::NAME);                                \
1474   }
1475 
1476   INSN(prfm, 0b11, 0);
1477 
1478 #undef INSN
1479 
1480   // Load/store
1481   void ld_st1(int opc, int p1, int V, int L,
1482               Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1483     starti;
1484     f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1485     zrf(Rt2, 10), zrf(Rt1, 0);
1486     if (no_allocate) {
1487       adr.encode_nontemporal_pair(&current_insn);
1488     } else {
1489       adr.encode_pair(&current_insn);
1490     }
1491   }
1492 
1493   // Load/store register pair (offset)
1494 #define INSN(NAME, size, p1, V, L, no_allocate)         \
1495   void NAME(Register Rt1, Register Rt2, Address adr) {  \
1496     ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1497    }
1498 
1499   INSN(stpw,  0b00, 0b101, 0, 0, false);
1500   INSN(ldpw,  0b00, 0b101, 0, 1, false);
1501   INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1502   INSN(stp,   0b10, 0b101, 0, 0, false);
1503   INSN(ldp,   0b10, 0b101, 0, 1, false);
1504 
1505   // Load/store no-allocate pair (offset)
1506   INSN(stnpw, 0b00, 0b101, 0, 0, true);
1507   INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1508   INSN(stnp,  0b10, 0b101, 0, 0, true);
1509   INSN(ldnp,  0b10, 0b101, 0, 1, true);
1510 
1511 #undef INSN
1512 
1513 #define INSN(NAME, size, p1, V, L, no_allocate)                         \
1514   void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) {        \
1515     ld_st1(size, p1, V, L,                                              \
1516            as_Register(Rt1), as_Register(Rt2), adr, no_allocate);       \
1517    }
1518 
1519   INSN(stps, 0b00, 0b101, 1, 0, false);
1520   INSN(ldps, 0b00, 0b101, 1, 1, false);
1521   INSN(stpd, 0b01, 0b101, 1, 0, false);
1522   INSN(ldpd, 0b01, 0b101, 1, 1, false);
1523   INSN(stpq, 0b10, 0b101, 1, 0, false);
1524   INSN(ldpq, 0b10, 0b101, 1, 1, false);
1525 
1526 #undef INSN
1527 
1528   // Load/store register (all modes)
1529   void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1530     starti;
1531 
1532     f(V, 26); // general reg?
1533     zrf(Rt, 0);
1534 
1535     // Encoding for literal loads is done here (rather than pushed
1536     // down into Address::encode) because the encoding of this
1537     // instruction is too different from all of the other forms to
1538     // make it worth sharing.
1539     if (adr.getMode() == Address::literal) {
1540       assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1541       assert(op == 0b01, "literal form can only be used with loads");
1542       f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1543       int64_t offset = (adr.target() - pc()) >> 2;
1544       sf(offset, 23, 5);
1545       code_section()->relocate(pc(), adr.rspec());
1546       return;
1547     }
1548 
1549     f(size, 31, 30);
1550     f(op, 23, 22); // str
1551     adr.encode(&current_insn);
1552   }
1553 
1554 #define INSN(NAME, size, op)                            \
1555   void NAME(Register Rt, const Address &adr) {          \
1556     ld_st2(Rt, adr, size, op);                          \
1557   }                                                     \
1558 
1559   INSN(str,  0b11, 0b00);
1560   INSN(strw, 0b10, 0b00);
1561   INSN(strb, 0b00, 0b00);
1562   INSN(strh, 0b01, 0b00);
1563 
1564   INSN(ldr,  0b11, 0b01);
1565   INSN(ldrw, 0b10, 0b01);
1566   INSN(ldrb, 0b00, 0b01);
1567   INSN(ldrh, 0b01, 0b01);
1568 
1569   INSN(ldrsb,  0b00, 0b10);
1570   INSN(ldrsbw, 0b00, 0b11);
1571   INSN(ldrsh,  0b01, 0b10);
1572   INSN(ldrshw, 0b01, 0b11);
1573   INSN(ldrsw,  0b10, 0b10);
1574 
1575 #undef INSN
1576 
1577 #define INSN(NAME, size, op)                            \
1578   void NAME(FloatRegister Rt, const Address &adr) {     \
1579     ld_st2(as_Register(Rt), adr, size, op, 1);          \
1580   }
1581 
1582   INSN(strd, 0b11, 0b00);
1583   INSN(strs, 0b10, 0b00);
1584   INSN(ldrd, 0b11, 0b01);
1585   INSN(ldrs, 0b10, 0b01);
1586   INSN(strq, 0b00, 0b10);
1587   INSN(ldrq, 0x00, 0b11);
1588 
1589 #undef INSN
1590 
1591 /* SIMD extensions
1592  *
1593  * We just use FloatRegister in the following. They are exactly the same
1594  * as SIMD registers.
1595  */
1596 public:
1597 
1598   enum SIMD_Arrangement {
1599     T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q, INVALID_ARRANGEMENT
1600   };
1601 
1602   enum SIMD_RegVariant {
1603       B, H, S, D, Q, INVALID
1604   };
1605 
1606 private:
1607 
1608   static SIMD_Arrangement _esize2arrangement_table[9][2];
1609   static SIMD_RegVariant _esize2regvariant[9];
1610 
1611 public:
1612 
1613   static SIMD_Arrangement esize2arrangement(unsigned esize, bool isQ);
1614   static SIMD_RegVariant elemType_to_regVariant(BasicType bt);
1615   static SIMD_RegVariant elemBytes_to_regVariant(unsigned esize);
1616   // Return the corresponding bits for different SIMD_RegVariant value.
1617   static unsigned regVariant_to_elemBits(SIMD_RegVariant T);
1618 
1619   enum shift_kind { LSL, LSR, ASR, ROR };
1620 
1621   void op_shifted_reg(Instruction_aarch64 &current_insn, unsigned decode,
1622                       enum shift_kind kind, unsigned shift,
1623                       unsigned size, unsigned op) {
1624     f(size, 31);
1625     f(op, 30, 29);
1626     f(decode, 28, 24);
1627     f(shift, 15, 10);
1628     f(kind, 23, 22);
1629   }
1630 
1631   // Logical (shifted register)
1632 #define INSN(NAME, size, op, N)                                         \
1633   void NAME(Register Rd, Register Rn, Register Rm,                      \
1634             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1635     starti;                                                             \
1636     guarantee(size == 1 || shift < 32, "incorrect shift");              \
1637     f(N, 21);                                                           \
1638     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
1639     op_shifted_reg(current_insn, 0b01010, kind, shift, size, op);       \
1640   }
1641 
1642   INSN(andr,  1, 0b00, 0);
1643   INSN(orr,   1, 0b01, 0);
1644   INSN(eor,   1, 0b10, 0);
1645   INSN(ands,  1, 0b11, 0);
1646   INSN(andw,  0, 0b00, 0);
1647   INSN(orrw,  0, 0b01, 0);
1648   INSN(eorw,  0, 0b10, 0);
1649   INSN(andsw, 0, 0b11, 0);
1650 
1651 #undef INSN
1652 
1653 #define INSN(NAME, size, op, N)                                         \
1654   void NAME(Register Rd, Register Rn, Register Rm,                      \
1655             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1656     starti;                                                             \
1657     f(N, 21);                                                           \
1658     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
1659     op_shifted_reg(current_insn, 0b01010, kind, shift, size, op);       \
1660   }                                                                     \
1661                                                                         \
1662   /* These instructions have no immediate form. Provide an overload so  \
1663      that if anyone does try to use an immediate operand -- this has    \
1664      happened! -- we'll get a compile-time error. */                    \
1665   void NAME(Register Rd, Register Rn, unsigned imm,                     \
1666             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1667     assert(false, " can't be used with immediate operand");             \
1668   }
1669 
1670   INSN(bic,   1, 0b00, 1);
1671   INSN(orn,   1, 0b01, 1);
1672   INSN(eon,   1, 0b10, 1);
1673   INSN(bics,  1, 0b11, 1);
1674   INSN(bicw,  0, 0b00, 1);
1675   INSN(ornw,  0, 0b01, 1);
1676   INSN(eonw,  0, 0b10, 1);
1677   INSN(bicsw, 0, 0b11, 1);
1678 
1679 #undef INSN
1680 
1681 #ifdef _WIN64
1682 // In MSVC, `mvn` is defined as a macro and it affects compilation
1683 #undef mvn
1684 #endif
1685 
1686   // Aliases for short forms of orn
1687 void mvn(Register Rd, Register Rm,
1688             enum shift_kind kind = LSL, unsigned shift = 0) {
1689   orn(Rd, zr, Rm, kind, shift);
1690 }
1691 
1692 void mvnw(Register Rd, Register Rm,
1693             enum shift_kind kind = LSL, unsigned shift = 0) {
1694   ornw(Rd, zr, Rm, kind, shift);
1695 }
1696 
1697   // Add/subtract (shifted register)
1698 #define INSN(NAME, size, op)                            \
1699   void NAME(Register Rd, Register Rn, Register Rm,      \
1700             enum shift_kind kind, unsigned shift = 0) { \
1701     starti;                                             \
1702     f(0, 21);                                           \
1703     assert_cond(kind != ROR);                           \
1704     guarantee(size == 1 || shift < 32, "incorrect shift");\
1705     zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16);                \
1706     op_shifted_reg(current_insn, 0b01011, kind, shift, size, op);      \
1707   }
1708 
1709   INSN(add,  1, 0b000);
1710   INSN(sub,  1, 0b10);
1711   INSN(addw, 0, 0b000);
1712   INSN(subw, 0, 0b10);
1713 
1714   INSN(adds,  1, 0b001);
1715   INSN(subs,  1, 0b11);
1716   INSN(addsw, 0, 0b001);
1717   INSN(subsw, 0, 0b11);
1718 
1719 #undef INSN
1720 
1721   // Add/subtract (extended register)
1722 #define INSN(NAME, op)                                                  \
1723   void NAME(Register Rd, Register Rn, Register Rm,                      \
1724            ext::operation option, int amount = 0) {                     \
1725     starti;                                                             \
1726     zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0);                                \
1727     add_sub_extended_reg(current_insn, op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1728   }
1729 
1730   void add_sub_extended_reg(Instruction_aarch64 &current_insn, unsigned op, unsigned decode,
1731     Register Rd, Register Rn, Register Rm,
1732     unsigned opt, ext::operation option, unsigned imm) {
1733     guarantee(imm <= 4, "shift amount must be <= 4");
1734     f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1735     f(option, 15, 13), f(imm, 12, 10);
1736   }
1737 
1738   INSN(addw, 0b000);
1739   INSN(subw, 0b010);
1740   INSN(add,  0b100);
1741   INSN(sub,  0b110);
1742 
1743 #undef INSN
1744 
1745 #define INSN(NAME, op)                                                  \
1746   void NAME(Register Rd, Register Rn, Register Rm,                      \
1747            ext::operation option, int amount = 0) {                     \
1748     starti;                                                             \
1749     zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0);                                \
1750     add_sub_extended_reg(current_insn, op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1751   }
1752 
1753   INSN(addsw, 0b001);
1754   INSN(subsw, 0b011);
1755   INSN(adds,  0b101);
1756   INSN(subs,  0b111);
1757 
1758 #undef INSN
1759 
1760   // Aliases for short forms of add and sub
1761 #define INSN(NAME)                                      \
1762   void NAME(Register Rd, Register Rn, Register Rm) {    \
1763     if (Rd == sp || Rn == sp)                           \
1764       NAME(Rd, Rn, Rm, ext::uxtx);                      \
1765     else                                                \
1766       NAME(Rd, Rn, Rm, LSL);                            \
1767   }
1768 
1769   INSN(addw);
1770   INSN(subw);
1771   INSN(add);
1772   INSN(sub);
1773 
1774   INSN(addsw);
1775   INSN(subsw);
1776   INSN(adds);
1777   INSN(subs);
1778 
1779 #undef INSN
1780 
1781   // Add/subtract (with carry)
1782   void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1783     starti;
1784     f(op, 31, 29);
1785     f(0b11010000, 28, 21);
1786     f(0b000000, 15, 10);
1787     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1788   }
1789 
1790   #define INSN(NAME, op)                                \
1791     void NAME(Register Rd, Register Rn, Register Rm) {  \
1792       add_sub_carry(op, Rd, Rn, Rm);                    \
1793     }
1794 
1795   INSN(adcw,  0b000);
1796   INSN(adcsw, 0b001);
1797   INSN(sbcw,  0b010);
1798   INSN(sbcsw, 0b011);
1799   INSN(adc,   0b100);
1800   INSN(adcs,  0b101);
1801   INSN(sbc,   0b110);
1802   INSN(sbcs,  0b111);
1803 
1804 #undef INSN
1805 
1806   // Conditional compare (both kinds)
1807   void conditional_compare(unsigned op, int o1, int o2, int o3,
1808                            Register Rn, unsigned imm5, unsigned nzcv,
1809                            unsigned cond) {
1810     starti;
1811     f(op, 31, 29);
1812     f(0b11010010, 28, 21);
1813     f(cond, 15, 12);
1814     f(o1, 11);
1815     f(o2, 10);
1816     f(o3, 4);
1817     f(nzcv, 3, 0);
1818     f(imm5, 20, 16), zrf(Rn, 5);
1819   }
1820 
1821 #define INSN(NAME, op)                                                  \
1822   void NAME(Register Rn, Register Rm, int imm, Condition cond) {        \
1823     int regNumber = (Rm == zr ? 31 : Rm->encoding());                   \
1824     conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond);         \
1825   }                                                                     \
1826                                                                         \
1827   void NAME(Register Rn, int imm5, int imm, Condition cond) {           \
1828     conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond);              \
1829   }
1830 
1831   INSN(ccmnw, 0b001);
1832   INSN(ccmpw, 0b011);
1833   INSN(ccmn, 0b101);
1834   INSN(ccmp, 0b111);
1835 
1836 #undef INSN
1837 
1838   // Conditional select
1839   void conditional_select(unsigned op, unsigned op2,
1840                           Register Rd, Register Rn, Register Rm,
1841                           unsigned cond) {
1842     starti;
1843     f(op, 31, 29);
1844     f(0b11010100, 28, 21);
1845     f(cond, 15, 12);
1846     f(op2, 11, 10);
1847     zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1848   }
1849 
1850 #define INSN(NAME, op, op2)                                             \
1851   void NAME(Register Rd, Register Rn, Register Rm, Condition cond) {    \
1852     conditional_select(op, op2, Rd, Rn, Rm, cond);                      \
1853   }
1854 
1855   INSN(cselw,  0b000, 0b00);
1856   INSN(csincw, 0b000, 0b01);
1857   INSN(csinvw, 0b010, 0b00);
1858   INSN(csnegw, 0b010, 0b01);
1859   INSN(csel,   0b100, 0b00);
1860   INSN(csinc,  0b100, 0b01);
1861   INSN(csinv,  0b110, 0b00);
1862   INSN(csneg,  0b110, 0b01);
1863 
1864 #undef INSN
1865 
1866   // Data processing
1867   void data_processing(Instruction_aarch64 &current_insn, unsigned op29, unsigned opcode,
1868                        Register Rd, Register Rn) {
1869     f(op29, 31, 29), f(0b11010110, 28, 21);
1870     f(opcode, 15, 10);
1871     rf(Rn, 5), rf(Rd, 0);
1872   }
1873 
1874   // (1 source)
1875 #define INSN(NAME, op29, opcode2, opcode)                       \
1876   void NAME(Register Rd, Register Rn) {                         \
1877     starti;                                                     \
1878     f(opcode2, 20, 16);                                         \
1879     data_processing(current_insn, op29, opcode, Rd, Rn);        \
1880   }
1881 
1882   INSN(rbitw,  0b010, 0b00000, 0b00000);
1883   INSN(rev16w, 0b010, 0b00000, 0b00001);
1884   INSN(revw,   0b010, 0b00000, 0b00010);
1885   INSN(clzw,   0b010, 0b00000, 0b00100);
1886   INSN(clsw,   0b010, 0b00000, 0b00101);
1887 
1888   INSN(rbit,   0b110, 0b00000, 0b00000);
1889   INSN(rev16,  0b110, 0b00000, 0b00001);
1890   INSN(rev32,  0b110, 0b00000, 0b00010);
1891   INSN(rev,    0b110, 0b00000, 0b00011);
1892   INSN(clz,    0b110, 0b00000, 0b00100);
1893   INSN(cls,    0b110, 0b00000, 0b00101);
1894 
1895   // PAC instructions
1896   INSN(pacia,  0b110, 0b00001, 0b00000);
1897   INSN(pacib,  0b110, 0b00001, 0b00001);
1898   INSN(pacda,  0b110, 0b00001, 0b00010);
1899   INSN(pacdb,  0b110, 0b00001, 0b00011);
1900   INSN(autia,  0b110, 0b00001, 0b00100);
1901   INSN(autib,  0b110, 0b00001, 0b00101);
1902   INSN(autda,  0b110, 0b00001, 0b00110);
1903   INSN(autdb,  0b110, 0b00001, 0b00111);
1904 
1905 #undef INSN
1906 
1907 #define INSN(NAME, op29, opcode2, opcode)                       \
1908   void NAME(Register Rd) {                                      \
1909     starti;                                                     \
1910     f(opcode2, 20, 16);                                         \
1911     data_processing(current_insn, op29, opcode, Rd, dummy_reg); \
1912   }
1913 
1914   // PAC instructions (with zero modifier)
1915   INSN(paciza,  0b110, 0b00001, 0b01000);
1916   INSN(pacizb,  0b110, 0b00001, 0b01001);
1917   INSN(pacdza,  0b110, 0b00001, 0b01010);
1918   INSN(pacdzb,  0b110, 0b00001, 0b01011);
1919   INSN(autiza,  0b110, 0b00001, 0b01100);
1920   INSN(autizb,  0b110, 0b00001, 0b01101);
1921   INSN(autdza,  0b110, 0b00001, 0b01110);
1922   INSN(autdzb,  0b110, 0b00001, 0b01111);
1923   INSN(xpaci,   0b110, 0b00001, 0b10000);
1924   INSN(xpacd,   0b110, 0b00001, 0b10001);
1925 
1926 #undef INSN
1927 
1928   // Data-processing (2 source)
1929 #define INSN(NAME, op29, opcode)                                \
1930   void NAME(Register Rd, Register Rn, Register Rm) {            \
1931     starti;                                                     \
1932     rf(Rm, 16);                                                 \
1933     data_processing(current_insn, op29, opcode, Rd, Rn);        \
1934   }
1935 
1936   INSN(udivw, 0b000, 0b000010);
1937   INSN(sdivw, 0b000, 0b000011);
1938   INSN(lslvw, 0b000, 0b001000);
1939   INSN(lsrvw, 0b000, 0b001001);
1940   INSN(asrvw, 0b000, 0b001010);
1941   INSN(rorvw, 0b000, 0b001011);
1942 
1943   INSN(udiv, 0b100, 0b000010);
1944   INSN(sdiv, 0b100, 0b000011);
1945   INSN(lslv, 0b100, 0b001000);
1946   INSN(lsrv, 0b100, 0b001001);
1947   INSN(asrv, 0b100, 0b001010);
1948   INSN(rorv, 0b100, 0b001011);
1949 
1950 #undef INSN
1951 
1952   // Data-processing (3 source)
1953   void data_processing(unsigned op54, unsigned op31, unsigned o0,
1954                        Register Rd, Register Rn, Register Rm,
1955                        Register Ra) {
1956     starti;
1957     f(op54, 31, 29), f(0b11011, 28, 24);
1958     f(op31, 23, 21), f(o0, 15);
1959     zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1960   }
1961 
1962 #define INSN(NAME, op54, op31, o0)                                      \
1963   void NAME(Register Rd, Register Rn, Register Rm, Register Ra) {       \
1964     data_processing(op54, op31, o0, Rd, Rn, Rm, Ra);                    \
1965   }
1966 
1967   INSN(maddw,  0b000, 0b000, 0);
1968   INSN(msubw,  0b000, 0b000, 1);
1969   INSN(madd,   0b100, 0b000, 0);
1970   INSN(msub,   0b100, 0b000, 1);
1971   INSN(smaddl, 0b100, 0b001, 0);
1972   INSN(smsubl, 0b100, 0b001, 1);
1973   INSN(umaddl, 0b100, 0b101, 0);
1974   INSN(umsubl, 0b100, 0b101, 1);
1975 
1976 #undef INSN
1977 
1978 #define INSN(NAME, op54, op31, o0)                                      \
1979   void NAME(Register Rd, Register Rn, Register Rm) {                    \
1980     data_processing(op54, op31, o0, Rd, Rn, Rm, as_Register(31));       \
1981   }
1982 
1983   INSN(smulh, 0b100, 0b010, 0);
1984   INSN(umulh, 0b100, 0b110, 0);
1985 
1986 #undef INSN
1987 
1988   // Floating-point data-processing (1 source)
1989   void data_processing(unsigned type, unsigned opcode,
1990                        FloatRegister Vd, FloatRegister Vn) {
1991     starti;
1992     f(0b000, 31, 29);
1993     f(0b11110, 28, 24);
1994     f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1995     rf(Vn, 5), rf(Vd, 0);
1996   }
1997 
1998 #define INSN(NAME, type, opcode)                        \
1999   void NAME(FloatRegister Vd, FloatRegister Vn) {       \
2000     data_processing(type, opcode, Vd, Vn);              \
2001   }
2002 
2003   INSN(fmovs,  0b00, 0b000000);
2004   INSN(fabss,  0b00, 0b000001);
2005   INSN(fnegs,  0b00, 0b000010);
2006   INSN(fsqrts, 0b00, 0b000011);
2007   INSN(fcvts,  0b00, 0b000101);   // Single-precision to double-precision
2008   INSN(fcvths, 0b11, 0b000100);   // Half-precision to single-precision
2009   INSN(fcvtsh, 0b00, 0b000111);   // Single-precision to half-precision
2010 
2011   INSN(fmovd,  0b01, 0b000000);
2012   INSN(fabsd,  0b01, 0b000001);
2013   INSN(fnegd,  0b01, 0b000010);
2014   INSN(fsqrtd, 0b01, 0b000011);
2015   INSN(fcvtd,  0b01, 0b000100);   // Double-precision to single-precision
2016 
2017 private:
2018   void _fcvt_narrow_extend(FloatRegister Vd, SIMD_Arrangement Ta,
2019                            FloatRegister Vn, SIMD_Arrangement Tb, bool do_extend) {
2020     assert((do_extend && (Tb >> 1) + 1 == (Ta >> 1))
2021            || (!do_extend && (Ta >> 1) + 1 == (Tb >> 1)), "Incompatible arrangement");
2022     starti;
2023     int op30 = (do_extend ? Tb : Ta) & 1;
2024     int op22 = ((do_extend ? Ta : Tb) >> 1) & 1;
2025     f(0, 31), f(op30, 30), f(0b0011100, 29, 23), f(op22, 22);
2026     f(0b100001011, 21, 13), f(do_extend ? 1 : 0, 12), f(0b10, 11, 10);
2027     rf(Vn, 5), rf(Vd, 0);
2028   }
2029 
2030 public:
2031   void fcvtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb) {
2032     assert(Tb == T4H || Tb == T8H|| Tb == T2S || Tb == T4S, "invalid arrangement");
2033     _fcvt_narrow_extend(Vd, Ta, Vn, Tb, true);
2034   }
2035 
2036   void fcvtn(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb) {
2037     assert(Ta == T4H || Ta == T8H|| Ta == T2S || Ta == T4S, "invalid arrangement");
2038     _fcvt_narrow_extend(Vd, Ta, Vn, Tb, false);
2039   }
2040 
2041 #undef INSN
2042 
2043   // Floating-point data-processing (2 source)
2044   void data_processing(unsigned op31, unsigned type, unsigned opcode,
2045                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
2046     starti;
2047     f(op31, 31, 29);
2048     f(0b11110, 28, 24);
2049     f(type, 23, 22), f(1, 21), f(opcode, 15, 10);
2050     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
2051   }
2052 
2053 #define INSN(NAME, op31, type, opcode)                  \
2054   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
2055     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
2056   }
2057 
2058   INSN(fabds,  0b011, 0b10, 0b110101);
2059   INSN(fmuls,  0b000, 0b00, 0b000010);
2060   INSN(fdivs,  0b000, 0b00, 0b000110);
2061   INSN(fadds,  0b000, 0b00, 0b001010);
2062   INSN(fsubs,  0b000, 0b00, 0b001110);
2063   INSN(fmaxs,  0b000, 0b00, 0b010010);
2064   INSN(fmins,  0b000, 0b00, 0b010110);
2065   INSN(fnmuls, 0b000, 0b00, 0b100010);
2066 
2067   INSN(fabdd,  0b011, 0b11, 0b110101);
2068   INSN(fmuld,  0b000, 0b01, 0b000010);
2069   INSN(fdivd,  0b000, 0b01, 0b000110);
2070   INSN(faddd,  0b000, 0b01, 0b001010);
2071   INSN(fsubd,  0b000, 0b01, 0b001110);
2072   INSN(fmaxd,  0b000, 0b01, 0b010010);
2073   INSN(fmind,  0b000, 0b01, 0b010110);
2074   INSN(fnmuld, 0b000, 0b01, 0b100010);
2075 
2076 #undef INSN
2077 
2078    // Floating-point data-processing (3 source)
2079   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
2080                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
2081                        FloatRegister Va) {
2082     starti;
2083     f(op31, 31, 29);
2084     f(0b11111, 28, 24);
2085     f(type, 23, 22), f(o1, 21), f(o0, 15);
2086     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
2087   }
2088 
2089 #define INSN(NAME, op31, type, o1, o0)                                  \
2090   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
2091             FloatRegister Va) {                                         \
2092     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
2093   }
2094 
2095   INSN(fmadds,  0b000, 0b00, 0, 0);
2096   INSN(fmsubs,  0b000, 0b00, 0, 1);
2097   INSN(fnmadds, 0b000, 0b00, 1, 0);
2098   INSN(fnmsubs, 0b000, 0b00, 1, 1);
2099 
2100   INSN(fmaddd,  0b000, 0b01, 0, 0);
2101   INSN(fmsubd,  0b000, 0b01, 0, 1);
2102   INSN(fnmaddd, 0b000, 0b01, 1, 0);
2103   INSN(fnmsub,  0b000, 0b01, 1, 1);
2104 
2105 #undef INSN
2106 
2107    // Floating-point conditional select
2108   void fp_conditional_select(unsigned op31, unsigned type,
2109                              unsigned op1, unsigned op2,
2110                              Condition cond, FloatRegister Vd,
2111                              FloatRegister Vn, FloatRegister Vm) {
2112     starti;
2113     f(op31, 31, 29);
2114     f(0b11110, 28, 24);
2115     f(type, 23, 22);
2116     f(op1, 21, 21);
2117     f(op2, 11, 10);
2118     f(cond, 15, 12);
2119     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
2120   }
2121 
2122 #define INSN(NAME, op31, type, op1, op2)                                \
2123   void NAME(FloatRegister Vd, FloatRegister Vn,                         \
2124             FloatRegister Vm, Condition cond) {                         \
2125     fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm);      \
2126   }
2127 
2128   INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
2129   INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
2130 
2131 #undef INSN
2132 
2133   // Conversion between floating-point and integer
2134   void float_int_convert(unsigned sflag, unsigned ftype,
2135                          unsigned rmode, unsigned opcode,
2136                          Register Rd, Register Rn) {
2137     starti;
2138     f(sflag, 31);
2139     f(0b00, 30, 29);
2140     f(0b11110, 28, 24);
2141     f(ftype, 23, 22), f(1, 21), f(rmode, 20, 19);
2142     f(opcode, 18, 16), f(0b000000, 15, 10);
2143     zrf(Rn, 5), zrf(Rd, 0);
2144   }
2145 
2146 #define INSN(NAME, sflag, ftype, rmode, opcode)                          \
2147   void NAME(Register Rd, FloatRegister Vn) {                             \
2148     float_int_convert(sflag, ftype, rmode, opcode, Rd, as_Register(Vn)); \
2149   }
2150 
2151   INSN(fcvtzsw, 0b0, 0b00, 0b11, 0b000);
2152   INSN(fcvtzs,  0b1, 0b00, 0b11, 0b000);
2153   INSN(fcvtzdw, 0b0, 0b01, 0b11, 0b000);
2154   INSN(fcvtzd,  0b1, 0b01, 0b11, 0b000);
2155 
2156   // RoundToNearestTiesAway
2157   INSN(fcvtassw, 0b0, 0b00, 0b00, 0b100);  // float -> signed word
2158   INSN(fcvtasd,  0b1, 0b01, 0b00, 0b100);  // double -> signed xword
2159 
2160   // RoundTowardsNegative
2161   INSN(fcvtmssw, 0b0, 0b00, 0b10, 0b000);  // float -> signed word
2162   INSN(fcvtmsd,  0b1, 0b01, 0b10, 0b000);  // double -> signed xword
2163 
2164   INSN(fmovs, 0b0, 0b00, 0b00, 0b110);
2165   INSN(fmovd, 0b1, 0b01, 0b00, 0b110);
2166 
2167   INSN(fmovhid, 0b1, 0b10, 0b01, 0b110);
2168 
2169 #undef INSN
2170 
2171 #define INSN(NAME, sflag, type, rmode, opcode)                          \
2172   void NAME(FloatRegister Vd, Register Rn) {                            \
2173     float_int_convert(sflag, type, rmode, opcode, as_Register(Vd), Rn); \
2174   }
2175 
2176   INSN(fmovs, 0b0, 0b00, 0b00, 0b111);
2177   INSN(fmovd, 0b1, 0b01, 0b00, 0b111);
2178 
2179   INSN(scvtfws, 0b0, 0b00, 0b00, 0b010);
2180   INSN(scvtfs,  0b1, 0b00, 0b00, 0b010);
2181   INSN(scvtfwd, 0b0, 0b01, 0b00, 0b010);
2182   INSN(scvtfd,  0b1, 0b01, 0b00, 0b010);
2183 
2184   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
2185 
2186 #undef INSN
2187 
2188   enum sign_kind { SIGNED, UNSIGNED };
2189 
2190 private:
2191   void _xcvtf_scalar_integer(sign_kind sign, unsigned sz,
2192                              FloatRegister Rd, FloatRegister Rn) {
2193     starti;
2194     f(0b01, 31, 30), f(sign == SIGNED ? 0 : 1, 29);
2195     f(0b111100, 27, 23), f((sz >> 1) & 1, 22), f(0b100001110110, 21, 10);
2196     rf(Rn, 5), rf(Rd, 0);
2197   }
2198 
2199 public:
2200 #define INSN(NAME, sign, sz)                        \
2201   void NAME(FloatRegister Rd, FloatRegister Rn) {   \
2202     _xcvtf_scalar_integer(sign, sz, Rd, Rn);        \
2203   }
2204 
2205   INSN(scvtfs, SIGNED, 0);
2206   INSN(scvtfd, SIGNED, 1);
2207 
2208 #undef INSN
2209 
2210 private:
2211   void _xcvtf_vector_integer(sign_kind sign, SIMD_Arrangement T,
2212                              FloatRegister Rd, FloatRegister Rn) {
2213     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
2214     starti;
2215     f(0, 31), f(T & 1, 30), f(sign == SIGNED ? 0 : 1, 29);
2216     f(0b011100, 28, 23), f((T >> 1) & 1, 22), f(0b100001110110, 21, 10);
2217     rf(Rn, 5), rf(Rd, 0);
2218   }
2219 
2220 public:
2221   void scvtfv(SIMD_Arrangement T, FloatRegister Rd, FloatRegister Rn) {
2222     _xcvtf_vector_integer(SIGNED, T, Rd, Rn);
2223   }
2224 
2225   // Floating-point compare
2226   void float_compare(unsigned op31, unsigned type,
2227                      unsigned op, unsigned op2,
2228                      FloatRegister Vn, FloatRegister Vm = as_FloatRegister(0)) {
2229     starti;
2230     f(op31, 31, 29);
2231     f(0b11110, 28, 24);
2232     f(type, 23, 22), f(1, 21);
2233     f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
2234     rf(Vn, 5), rf(Vm, 16);
2235   }
2236 
2237 
2238 #define INSN(NAME, op31, type, op, op2)                 \
2239   void NAME(FloatRegister Vn, FloatRegister Vm) {       \
2240     float_compare(op31, type, op, op2, Vn, Vm);         \
2241   }
2242 
2243 #define INSN1(NAME, op31, type, op, op2)        \
2244   void NAME(FloatRegister Vn, double d) {       \
2245     assert_cond(d == 0.0);                      \
2246     float_compare(op31, type, op, op2, Vn);     \
2247   }
2248 
2249   INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2250   INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2251   // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2252   // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2253 
2254   INSN(fcmpd, 0b000,   0b01, 0b00, 0b00000);
2255   INSN1(fcmpd, 0b000,  0b01, 0b00, 0b01000);
2256   // INSN(fcmped, 0b000,  0b01, 0b00, 0b10000);
2257   // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2258 
2259 #undef INSN
2260 #undef INSN1
2261 
2262 // Floating-point compare. 3-registers versions (scalar).
2263 #define INSN(NAME, sz, e)                                             \
2264   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {   \
2265     starti;                                                           \
2266     f(0b01111110, 31, 24), f(e, 23), f(sz, 22), f(1, 21), rf(Vm, 16); \
2267     f(0b111011, 15, 10), rf(Vn, 5), rf(Vd, 0);                        \
2268   }                                                                   \
2269 
2270   INSN(facged, 1, 0); // facge-double
2271   INSN(facges, 0, 0); // facge-single
2272   INSN(facgtd, 1, 1); // facgt-double
2273   INSN(facgts, 0, 1); // facgt-single
2274 
2275 #undef INSN
2276 
2277   // Floating-point Move (immediate)
2278 private:
2279   unsigned pack(double value);
2280 
2281   void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2282     starti;
2283     f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2284     f(pack(value), 20, 13), f(0b10000000, 12, 5);
2285     rf(Vn, 0);
2286   }
2287 
2288 public:
2289 
2290   void fmovs(FloatRegister Vn, double value) {
2291     if (value)
2292       fmov_imm(Vn, value, 0b00);
2293     else
2294       movi(Vn, T2S, 0);
2295   }
2296   void fmovd(FloatRegister Vn, double value) {
2297     if (value)
2298       fmov_imm(Vn, value, 0b01);
2299     else
2300       movi(Vn, T1D, 0);
2301   }
2302 
2303   // Floating-point data-processing (1 source)
2304 
2305    // Floating-point rounding
2306    // type: half-precision = 11
2307    //       single         = 00
2308    //       double         = 01
2309    // rmode: A = Away     = 100
2310    //        I = current  = 111
2311    //        M = MinusInf = 010
2312    //        N = eveN     = 000
2313    //        P = PlusInf  = 001
2314    //        X = eXact    = 110
2315    //        Z = Zero     = 011
2316   void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2317     starti;
2318     f(0b00011110, 31, 24);
2319     f(type, 23, 22);
2320     f(0b1001, 21, 18);
2321     f(rmode, 17, 15);
2322     f(0b10000, 14, 10);
2323     rf(Rn, 5), rf(Rd, 0);
2324   }
2325 #define INSN(NAME, type, rmode)                   \
2326   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2327     float_round(type, rmode, Vd, Vn);             \
2328   }
2329 
2330 public:
2331   INSN(frintah, 0b11, 0b100);
2332   INSN(frintih, 0b11, 0b111);
2333   INSN(frintmh, 0b11, 0b010);
2334   INSN(frintnh, 0b11, 0b000);
2335   INSN(frintph, 0b11, 0b001);
2336   INSN(frintxh, 0b11, 0b110);
2337   INSN(frintzh, 0b11, 0b011);
2338 
2339   INSN(frintas, 0b00, 0b100);
2340   INSN(frintis, 0b00, 0b111);
2341   INSN(frintms, 0b00, 0b010);
2342   INSN(frintns, 0b00, 0b000);
2343   INSN(frintps, 0b00, 0b001);
2344   INSN(frintxs, 0b00, 0b110);
2345   INSN(frintzs, 0b00, 0b011);
2346 
2347   INSN(frintad, 0b01, 0b100);
2348   INSN(frintid, 0b01, 0b111);
2349   INSN(frintmd, 0b01, 0b010);
2350   INSN(frintnd, 0b01, 0b000);
2351   INSN(frintpd, 0b01, 0b001);
2352   INSN(frintxd, 0b01, 0b110);
2353   INSN(frintzd, 0b01, 0b011);
2354 #undef INSN
2355 
2356 private:
2357   static short SIMD_Size_in_bytes[];
2358 
2359 public:
2360 #define INSN(NAME, op)                                                  \
2361   void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) {  \
2362     ld_st2(as_Register(Rt), adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2363   }
2364 
2365   INSN(ldr, 1);
2366   INSN(str, 0);
2367 
2368 #undef INSN
2369 
2370  private:
2371 
2372   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2373     starti;
2374     f(0,31), f((int)T & 1, 30);
2375     f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2376     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2377   }
2378   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2379              int imm, int op1, int op2, int regs) {
2380 
2381     bool replicate = op2 >> 2 == 3;
2382     // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2383     int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2384     guarantee(T < T1Q , "incorrect arrangement");
2385     guarantee(imm == expectedImmediate, "bad offset");
2386     starti;
2387     f(0,31), f((int)T & 1, 30);
2388     f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2389     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2390   }
2391   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2392              Register Xm, int op1, int op2) {
2393     starti;
2394     f(0,31), f((int)T & 1, 30);
2395     f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2396     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2397   }
2398 
2399   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2400     switch (a.getMode()) {
2401     case Address::base_plus_offset:
2402       guarantee(a.offset() == 0, "no offset allowed here");
2403       ld_st(Vt, T, a.base(), op1, op2);
2404       break;
2405     case Address::post:
2406       ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2407       break;
2408     case Address::post_reg:
2409       ld_st(Vt, T, a.base(), a.index(), op1, op2);
2410       break;
2411     default:
2412       ShouldNotReachHere();
2413     }
2414   }
2415 
2416   // Single-structure load/store method (all addressing variants)
2417   void ld_st(FloatRegister Vt, SIMD_RegVariant T, int index, Address a,
2418              int op1, int op2, int regs) {
2419     int expectedImmediate = (regVariant_to_elemBits(T) >> 3) * regs;
2420     int sVal = (T < D) ? (index >> (2 - T)) & 0x01 : 0;
2421     int opcode = (T < D) ? (T << 2) : ((T & 0x02) << 2);
2422     int size = (T < D) ? (index & (0x3 << T)) : 1;  // only care about low 2b
2423     Register Xn = a.base();
2424     int Rm;
2425 
2426     switch (a.getMode()) {
2427     case Address::base_plus_offset:
2428       guarantee(a.offset() == 0, "no offset allowed here");
2429       Rm = 0;
2430       break;
2431     case Address::post:
2432       guarantee(a.offset() == expectedImmediate, "bad offset");
2433       op1 |= 0b100;
2434       Rm = 0b11111;
2435       break;
2436     case Address::post_reg:
2437       op1 |= 0b100;
2438       Rm = a.index()->encoding();
2439       break;
2440     default:
2441       ShouldNotReachHere();
2442       Rm = 0;  // unreachable
2443     }
2444 
2445     starti;
2446     f(0,31), f((index >> (3 - T)), 30);
2447     f(op1, 29, 21), f(Rm, 20, 16), f(op2 | opcode | sVal, 15, 12);
2448     f(size, 11, 10), srf(Xn, 5), rf(Vt, 0);
2449   }
2450 
2451  public:
2452 
2453 #define INSN1(NAME, op1, op2)                                           \
2454   void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) {   \
2455     ld_st(Vt, T, a, op1, op2, 1);                                       \
2456  }
2457 
2458 #define INSN2(NAME, op1, op2)                                           \
2459   void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2460     assert(Vt->successor() == Vt2, "Registers must be ordered");        \
2461     ld_st(Vt, T, a, op1, op2, 2);                                       \
2462   }
2463 
2464 #define INSN3(NAME, op1, op2)                                           \
2465   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2466             SIMD_Arrangement T, const Address &a) {                     \
2467     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3,           \
2468            "Registers must be ordered");                                \
2469     ld_st(Vt, T, a, op1, op2, 3);                                       \
2470   }
2471 
2472 #define INSN4(NAME, op1, op2)                                           \
2473   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2474             FloatRegister Vt4, SIMD_Arrangement T, const Address &a) {  \
2475     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&         \
2476            Vt3->successor() == Vt4, "Registers must be ordered");       \
2477     ld_st(Vt, T, a, op1, op2, 4);                                       \
2478   }
2479 
2480   INSN1(ld1,  0b001100010, 0b0111);
2481   INSN2(ld1,  0b001100010, 0b1010);
2482   INSN3(ld1,  0b001100010, 0b0110);
2483   INSN4(ld1,  0b001100010, 0b0010);
2484 
2485   INSN2(ld2,  0b001100010, 0b1000);
2486   INSN3(ld3,  0b001100010, 0b0100);
2487   INSN4(ld4,  0b001100010, 0b0000);
2488 
2489   INSN1(st1,  0b001100000, 0b0111);
2490   INSN2(st1,  0b001100000, 0b1010);
2491   INSN3(st1,  0b001100000, 0b0110);
2492   INSN4(st1,  0b001100000, 0b0010);
2493 
2494   INSN2(st2,  0b001100000, 0b1000);
2495   INSN3(st3,  0b001100000, 0b0100);
2496   INSN4(st4,  0b001100000, 0b0000);
2497 
2498   INSN1(ld1r, 0b001101010, 0b1100);
2499   INSN2(ld2r, 0b001101011, 0b1100);
2500   INSN3(ld3r, 0b001101010, 0b1110);
2501   INSN4(ld4r, 0b001101011, 0b1110);
2502 
2503 #undef INSN1
2504 #undef INSN2
2505 #undef INSN3
2506 #undef INSN4
2507 
2508 // Handle common single-structure ld/st parameter sanity checks
2509 // for all variations (1 to 4) of SIMD reigster inputs.  This
2510 // method will call the routine that generates the opcode.
2511 template<typename R, typename... Rx>
2512   void ldst_sstr(SIMD_RegVariant T, int index, const Address &a,
2513             int op1, int op2, R firstReg, Rx... otherRegs) {
2514     const FloatRegister vtSet[] = { firstReg, otherRegs... };
2515     const int regCount = sizeof...(otherRegs) + 1;
2516     assert(index >= 0 && (T <= D) && ((T == B && index <= 15) ||
2517               (T == H && index <= 7) || (T == S && index <= 3) ||
2518               (T == D && index <= 1)), "invalid index");
2519     assert(regCount >= 1 && regCount <= 4, "illegal register count");
2520 
2521     // Check to make sure when multiple SIMD registers are used
2522     // that they are in successive order.
2523     for (int i = 0; i < regCount - 1; i++) {
2524       assert(vtSet[i]->successor() == vtSet[i + 1],
2525              "Registers must be ordered");
2526     }
2527 
2528     ld_st(firstReg, T, index, a, op1, op2, regCount);
2529   }
2530 
2531 // Define a set of INSN1/2/3/4 macros to handle single-structure
2532 // load/store instructions.
2533 #define INSN1(NAME, op1, op2)                                           \
2534   void NAME(FloatRegister Vt, SIMD_RegVariant T, int index,             \
2535             const Address &a) {                                         \
2536     ldst_sstr(T, index, a, op1, op2, Vt);                               \
2537  }
2538 
2539 #define INSN2(NAME, op1, op2)                                           \
2540   void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_RegVariant T,     \
2541             int index, const Address &a) {                              \
2542     ldst_sstr(T, index, a, op1, op2, Vt, Vt2);                          \
2543   }
2544 
2545 #define INSN3(NAME, op1, op2)                                           \
2546   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2547             SIMD_RegVariant T, int index, const Address &a) {           \
2548     ldst_sstr(T, index, a, op1, op2, Vt, Vt2, Vt3);                     \
2549   }
2550 
2551 #define INSN4(NAME, op1, op2)                                           \
2552   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2553             FloatRegister Vt4, SIMD_RegVariant T, int index,            \
2554             const Address &a) {                                         \
2555     ldst_sstr(T, index, a, op1, op2, Vt, Vt2, Vt3, Vt4);                \
2556   }
2557 
2558   INSN1(st1, 0b001101000, 0b0000);
2559   INSN2(st2, 0b001101001, 0b0000);
2560   INSN3(st3, 0b001101000, 0b0010);
2561   INSN4(st4, 0b001101001, 0b0010);
2562 
2563 #undef INSN1
2564 #undef INSN2
2565 #undef INSN3
2566 #undef INSN4
2567 
2568 #define INSN(NAME, opc)                                                                 \
2569   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2570     starti;                                                                             \
2571     assert(T == T8B || T == T16B, "must be T8B or T16B");                               \
2572     f(0, 31), f((int)T & 1, 30), f(opc, 29, 21);                                        \
2573     rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);                              \
2574   }
2575 
2576   INSN(eor,  0b101110001);
2577   INSN(orr,  0b001110101);
2578   INSN(andr, 0b001110001);
2579   INSN(bic,  0b001110011);
2580   INSN(bif,  0b101110111);
2581   INSN(bit,  0b101110101);
2582   INSN(bsl,  0b101110011);
2583   INSN(orn,  0b001110111);
2584 
2585 #undef INSN
2586 
2587   // Advanced SIMD three different
2588 #define INSN(NAME, opc, opc2, acceptT2D)                                                \
2589   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2590     guarantee(T != T1Q && T != T1D, "incorrect arrangement");                           \
2591     if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement");                       \
2592     starti;                                                                             \
2593     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2594     f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10);                      \
2595     rf(Vn, 5), rf(Vd, 0);                                                               \
2596   }
2597 
2598   INSN(addv,   0, 0b100001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2599   INSN(subv,   1, 0b100001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2600   INSN(uqsubv, 1, 0b001011, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2601   INSN(mulv,   0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2602   INSN(mlav,   0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2603   INSN(mlsv,   1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2604   INSN(sshl,   0, 0b010001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2605   INSN(ushl,   1, 0b010001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2606   INSN(addpv,  0, 0b101111, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2607   INSN(smullv, 0, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2608   INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2609   INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2610   INSN(maxv,   0, 0b011001, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2611   INSN(minv,   0, 0b011011, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2612   INSN(smaxp,  0, 0b101001, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2613   INSN(sminp,  0, 0b101011, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2614 
2615 #undef INSN
2616 
2617 #define INSN(NAME, opc, opc2, accepted) \
2618   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2619     guarantee(T != T1Q && T != T1D, "incorrect arrangement");                           \
2620     if (accepted < 3) guarantee(T != T2D, "incorrect arrangement");                     \
2621     if (accepted < 2) guarantee(T != T2S, "incorrect arrangement");                     \
2622     if (accepted < 1) guarantee(T == T8B || T == T16B, "incorrect arrangement");        \
2623     starti;                                                                             \
2624     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2625     f((int)T >> 1, 23, 22), f(opc2, 21, 10);                                            \
2626     rf(Vn, 5), rf(Vd, 0);                                                               \
2627   }
2628 
2629   INSN(absr,   0, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2630   INSN(negr,   1, 0b100000101110, 3); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2631   INSN(notr,   1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2632   INSN(addv,   0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2633   INSN(smaxv,  0, 0b110000101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2634   INSN(umaxv,  1, 0b110000101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2635   INSN(sminv,  0, 0b110001101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2636   INSN(uminv,  1, 0b110001101010, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2637   INSN(cls,    0, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2638   INSN(clz,    1, 0b100000010010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2639   INSN(cnt,    0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2640   INSN(uaddlp, 1, 0b100000001010, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2641   INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2642 
2643 #undef INSN
2644 
2645 #define INSN(NAME, opc) \
2646   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                  \
2647     starti;                                                                            \
2648     assert(T == T4S, "arrangement must be T4S");                                       \
2649     f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23),                      \
2650     f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0);          \
2651   }
2652 
2653   INSN(fmaxv, 0);
2654   INSN(fminv, 1);
2655 
2656 #undef INSN
2657 
2658 // Advanced SIMD modified immediate
2659 #define INSN(NAME, op0, cmode0) \
2660   void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) {   \
2661     unsigned cmode = cmode0;                                                           \
2662     unsigned op = op0;                                                                 \
2663     starti;                                                                            \
2664     assert(lsl == 0 ||                                                                 \
2665            ((T == T4H || T == T8H) && lsl == 8) ||                                     \
2666            ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2667     cmode |= lsl >> 2;                                                                 \
2668     if (T == T4H || T == T8H) cmode |= 0b1000;                                         \
2669     if (!(T == T4H || T == T8H || T == T2S || T == T4S)) {                             \
2670       assert(op == 0 && cmode0 == 0, "must be MOVI");                                  \
2671       cmode = 0b1110;                                                                  \
2672       if (T == T1D || T == T2D) op = 1;                                                \
2673     }                                                                                  \
2674     f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19);                   \
2675     f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5);  \
2676     rf(Vd, 0);                                                                         \
2677   }
2678 
2679   INSN(movi, 0, 0);
2680   INSN(orri, 0, 1);
2681   INSN(mvni, 1, 0);
2682   INSN(bici, 1, 1);
2683 
2684 #undef INSN
2685 
2686 #define INSN(NAME, op, cmode)                                           \
2687   void NAME(FloatRegister Vd, SIMD_Arrangement T, double imm) {         \
2688     unsigned imm8 = pack(imm);                                          \
2689     starti;                                                             \
2690     f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19);    \
2691     f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2692     rf(Vd, 0);                                                          \
2693   }
2694 
2695   INSN(fmovs, 0, 0b1111);
2696   INSN(fmovd, 1, 0b1111);
2697 
2698 #undef INSN
2699 
2700 // Advanced SIMD three same
2701 #define INSN(NAME, op1, op2, op3)                                                       \
2702   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2703     starti;                                                                             \
2704     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                    \
2705     f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23);            \
2706     f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0);    \
2707   }
2708 
2709   INSN(fabd, 1, 1, 0b110101);
2710   INSN(fadd, 0, 0, 0b110101);
2711   INSN(fdiv, 1, 0, 0b111111);
2712   INSN(faddp, 1, 0, 0b110101);
2713   INSN(fmul, 1, 0, 0b110111);
2714   INSN(fsub, 0, 1, 0b110101);
2715   INSN(fmla, 0, 0, 0b110011);
2716   INSN(fmls, 0, 1, 0b110011);
2717   INSN(fmax, 0, 0, 0b111101);
2718   INSN(fmin, 0, 1, 0b111101);
2719   INSN(facgt, 1, 1, 0b111011);
2720 
2721 #undef INSN
2722 
2723   // AdvSIMD vector compare
2724   void cm(Condition cond, FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) {
2725     starti;
2726     assert(T != T1Q && T != T1D, "incorrect arrangement");
2727     int cond_op;
2728     switch (cond) {
2729       case EQ: cond_op = 0b110001; break;
2730       case GT: cond_op = 0b000110; break;
2731       case GE: cond_op = 0b000111; break;
2732       case HI: cond_op = 0b100110; break;
2733       case HS: cond_op = 0b100111; break;
2734       default:
2735         ShouldNotReachHere();
2736         break;
2737     }
2738 
2739     f(0, 31), f((int)T & 1, 30), f((cond_op >> 5) & 1, 29);
2740     f(0b01110, 28, 24), f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16);
2741     f(cond_op & 0b11111, 15, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2742   }
2743 
2744   // AdvSIMD Floating-point vector compare
2745   void fcm(Condition cond, FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) {
2746     starti;
2747     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
2748     int cond_op;
2749     switch (cond) {
2750       case EQ: cond_op = 0b00; break;
2751       case GT: cond_op = 0b11; break;
2752       case GE: cond_op = 0b10; break;
2753       default:
2754         ShouldNotReachHere();
2755         break;
2756     }
2757 
2758     f(0, 31), f((int)T & 1, 30), f((cond_op >> 1) & 1, 29);
2759     f(0b01110, 28, 24), f(cond_op & 1, 23), f(T == T2D ? 1 : 0, 22);
2760     f(1, 21), rf(Vm, 16), f(0b111001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2761   }
2762 
2763 #define INSN(NAME, opc)                                                                 \
2764   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2765     starti;                                                                             \
2766     assert(T == T4S, "arrangement must be T4S");                                        \
2767     f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);         \
2768   }
2769 
2770   INSN(sha1c,     0b000000);
2771   INSN(sha1m,     0b001000);
2772   INSN(sha1p,     0b000100);
2773   INSN(sha1su0,   0b001100);
2774   INSN(sha256h2,  0b010100);
2775   INSN(sha256h,   0b010000);
2776   INSN(sha256su1, 0b011000);
2777 
2778 #undef INSN
2779 
2780 #define INSN(NAME, opc)                                                                 \
2781   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2782     starti;                                                                             \
2783     assert(T == T4S, "arrangement must be T4S");                                        \
2784     f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);                \
2785   }
2786 
2787   INSN(sha1h,     0b000010);
2788   INSN(sha1su1,   0b000110);
2789   INSN(sha256su0, 0b001010);
2790 
2791 #undef INSN
2792 
2793 #define INSN(NAME, opc)                                                                 \
2794   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2795     starti;                                                                             \
2796     assert(T == T2D, "arrangement must be T2D");                                        \
2797     f(0b11001110011, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);         \
2798   }
2799 
2800   INSN(sha512h,   0b100000);
2801   INSN(sha512h2,  0b100001);
2802   INSN(sha512su1, 0b100010);
2803 
2804 #undef INSN
2805 
2806 #define INSN(NAME, opc)                                                                 \
2807   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2808     starti;                                                                             \
2809     assert(T == T2D, "arrangement must be T2D");                                        \
2810     f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);                                               \
2811   }
2812 
2813   INSN(sha512su0, 0b1100111011000000100000);
2814 
2815 #undef INSN
2816 
2817 #define INSN(NAME, opc)                                                                                   \
2818   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, FloatRegister Va) { \
2819     starti;                                                                                               \
2820     assert(T == T16B, "arrangement must be T16B");                                                        \
2821     f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(0b0, 15, 15), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);  \
2822   }
2823 
2824   INSN(eor3, 0b000);
2825   INSN(bcax, 0b001);
2826 
2827 #undef INSN
2828 
2829 #define INSN(NAME, opc)                                                                               \
2830   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, unsigned imm) { \
2831     starti;                                                                                           \
2832     assert(T == T2D, "arrangement must be T2D");                                                      \
2833     f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(imm, 15, 10), rf(Vn, 5), rf(Vd, 0);          \
2834   }
2835 
2836   INSN(xar, 0b100);
2837 
2838 #undef INSN
2839 
2840 #define INSN(NAME, opc)                                                                           \
2841   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) {           \
2842     starti;                                                                                       \
2843     assert(T == T2D, "arrangement must be T2D");                                                  \
2844     f(0b11001110, 31, 24), f(opc, 23, 21), rf(Vm, 16), f(0b100011, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2845   }
2846 
2847   INSN(rax1, 0b011);
2848 
2849 #undef INSN
2850 
2851 #define INSN(NAME, opc)                           \
2852   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2853     starti;                                       \
2854     f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);         \
2855   }
2856 
2857   INSN(aese,   0b0100111000101000010010);
2858   INSN(aesd,   0b0100111000101000010110);
2859   INSN(aesmc,  0b0100111000101000011010);
2860   INSN(aesimc, 0b0100111000101000011110);
2861 
2862 #undef INSN
2863 
2864 #define INSN(NAME, op1, op2) \
2865   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2866     starti;                                                                                            \
2867     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                                   \
2868     assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index");     \
2869     f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23);                                      \
2870     f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16);                              \
2871     f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10);                                  \
2872     rf(Vn, 5), rf(Vd, 0);                                                                              \
2873   }
2874 
2875   // FMLA/FMLS - Vector - Scalar
2876   INSN(fmlavs, 0, 0b0001);
2877   INSN(fmlsvs, 0, 0b0101);
2878   // FMULX - Vector - Scalar
2879   INSN(fmulxvs, 1, 0b1001);
2880 
2881 #undef INSN
2882 
2883   // Floating-point Reciprocal Estimate
2884   void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2885     assert(type == D || type == S, "Wrong type for frecpe");
2886     starti;
2887     f(0b010111101, 31, 23);
2888     f(type == D ? 1 : 0, 22);
2889     f(0b100001110110, 21, 10);
2890     rf(Vn, 5), rf(Vd, 0);
2891   }
2892 
2893   // (long) {a, b} -> (a + b)
2894   void addpd(FloatRegister Vd, FloatRegister Vn) {
2895     starti;
2896     f(0b0101111011110001101110, 31, 10);
2897     rf(Vn, 5), rf(Vd, 0);
2898   }
2899 
2900   // Floating-point AdvSIMD scalar pairwise
2901 #define INSN(NAME, op1, op2) \
2902   void NAME(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {                 \
2903     starti;                                                                             \
2904     assert(type == D || type == S, "Wrong type for faddp/fmaxp/fminp");                 \
2905     f(0b0111111, 31, 25), f(op1, 24, 23),                                               \
2906     f(type == S ? 0 : 1, 22), f(0b11000, 21, 17), f(op2, 16, 10), rf(Vn, 5), rf(Vd, 0); \
2907   }
2908 
2909   INSN(faddp, 0b00, 0b0110110);
2910   INSN(fmaxp, 0b00, 0b0111110);
2911   INSN(fminp, 0b01, 0b0111110);
2912 
2913 #undef INSN
2914 
2915   void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2916     starti;
2917     assert(T != Q, "invalid register variant");
2918     f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2919     f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2920   }
2921 
2922 #define INSN(NAME, cond, op1, op2)                                                      \
2923   void NAME(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {                \
2924     starti;                                                                             \
2925     assert(cond, "invalid register variant");                                           \
2926     f(0, 31), f(op1, 30), f(0b001110000, 29, 21);                                       \
2927     f(((idx << 1) | 1) << (int)T, 20, 16), f(op2, 15, 10);                              \
2928     rf(Vn, 5), rf(Rd, 0);                                                               \
2929   }
2930 
2931   INSN(umov, (T != Q), (T == D ? 1 : 0), 0b001111);
2932   INSN(smov, (T < D),  1,                0b001011);
2933 
2934 #undef INSN
2935 
2936 #define INSN(NAME, opc, opc2, isSHR)                                    \
2937   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2938     starti;                                                             \
2939     /* The encodings for the immh:immb fields (bits 22:16) in *SHR are  \
2940      *   0001 xxx       8B/16B, shift = 16  - UInt(immh:immb)           \
2941      *   001x xxx       4H/8H,  shift = 32  - UInt(immh:immb)           \
2942      *   01xx xxx       2S/4S,  shift = 64  - UInt(immh:immb)           \
2943      *   1xxx xxx       1D/2D,  shift = 128 - UInt(immh:immb)           \
2944      *   (1D is RESERVED)                                               \
2945      * for SHL shift is calculated as:                                  \
2946      *   0001 xxx       8B/16B, shift = UInt(immh:immb) - 8             \
2947      *   001x xxx       4H/8H,  shift = UInt(immh:immb) - 16            \
2948      *   01xx xxx       2S/4S,  shift = UInt(immh:immb) - 32            \
2949      *   1xxx xxx       1D/2D,  shift = UInt(immh:immb) - 64            \
2950      *   (1D is RESERVED)                                               \
2951      */                                                                 \
2952     guarantee(!isSHR || (isSHR && (shift != 0)), "impossible encoding");\
2953     assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value");           \
2954     int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0)));               \
2955     int encodedShift = isSHR ? cVal - shift : cVal + shift;             \
2956     f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23),            \
2957     f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0);     \
2958   }
2959 
2960   INSN(shl,  0, 0b010101, /* isSHR = */ false);
2961   INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2962   INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2963   INSN(usra, 1, 0b000101, /* isSHR = */ true);
2964   INSN(ssra, 0, 0b000101, /* isSHR = */ true);
2965   INSN(sli,  1, 0b010101, /* isSHR = */ false);
2966 
2967 #undef INSN
2968 
2969 #define INSN(NAME, opc, opc2, isSHR)                                    \
2970   void NAME(FloatRegister Vd, FloatRegister Vn, int shift){             \
2971     starti;                                                             \
2972     int encodedShift = isSHR ? 128 - shift : 64 + shift;                \
2973     f(0b01, 31, 30), f(opc, 29), f(0b111110, 28, 23),                   \
2974     f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0);     \
2975   }
2976 
2977   INSN(shld,  0, 0b010101, /* isSHR = */ false);
2978   INSN(sshrd, 0, 0b000001, /* isSHR = */ true);
2979   INSN(ushrd, 1, 0b000001, /* isSHR = */ true);
2980 
2981 #undef INSN
2982 
2983 private:
2984   void _xshll(sign_kind sign, FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2985     starti;
2986     /* The encodings for the immh:immb fields (bits 22:16) are
2987      *   0001 xxx       8H, 8B/16B shift = xxx
2988      *   001x xxx       4S, 4H/8H  shift = xxxx
2989      *   01xx xxx       2D, 2S/4S  shift = xxxxx
2990      *   1xxx xxx       RESERVED
2991      */
2992     assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2993     assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2994     f(0, 31), f(Tb & 1, 30), f(sign == SIGNED ? 0 : 1, 29), f(0b011110, 28, 23);
2995     f((1 << ((Tb>>1)+3))|shift, 22, 16);
2996     f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2997   }
2998 
2999 public:
3000   void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
3001     assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
3002     _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
3003   }
3004 
3005   void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
3006     assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
3007     _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
3008   }
3009 
3010   void uxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb) {
3011     ushll(Vd, Ta, Vn, Tb, 0);
3012   }
3013 
3014   void sshll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
3015     assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
3016     _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
3017   }
3018 
3019   void sshll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
3020     assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
3021     _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
3022   }
3023 
3024   void sxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb) {
3025     sshll(Vd, Ta, Vn, Tb, 0);
3026   }
3027 
3028   // Move from general purpose register
3029   //   mov  Vd.T[index], Rn
3030   void mov(FloatRegister Vd, SIMD_RegVariant T, int index, Register Xn) {
3031     guarantee(T != Q, "invalid register variant");
3032     starti;
3033     f(0b01001110000, 31, 21), f(((1 << T) | (index << (T + 1))), 20, 16);
3034     f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
3035   }
3036 
3037   // Move to general purpose register
3038   //   mov  Rd, Vn.T[index]
3039   void mov(Register Xd, FloatRegister Vn, SIMD_RegVariant T, int index) {
3040     guarantee(T == S || T == D, "invalid register variant");
3041     umov(Xd, Vn, T, index);
3042   }
3043 
3044 private:
3045   void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
3046     starti;
3047     assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
3048            (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
3049     int size = (Ta == T1Q) ? 0b11 : 0b00;
3050     f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
3051     f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
3052   }
3053 
3054 public:
3055   void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
3056     assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
3057     _pmull(Vd, Ta, Vn, Vm, Tb);
3058   }
3059 
3060   void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
3061     assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
3062     _pmull(Vd, Ta, Vn, Vm, Tb);
3063   }
3064 
3065   void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
3066     starti;
3067     int size_b = (int)Tb >> 1;
3068     int size_a = (int)Ta >> 1;
3069     assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
3070     f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
3071     f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
3072   }
3073 
3074   void xtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
3075     starti;
3076     int size_b = (int)Tb >> 1;
3077     int size_a = (int)Ta >> 1;
3078     assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
3079     f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size_b, 23, 22);
3080     f(0b100001001010, 21, 10), rf(Vn, 5), rf(Vd, 0);
3081   }
3082 
3083   void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
3084   {
3085     starti;
3086     assert(T != T1D, "reserved encoding");
3087     f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
3088     f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
3089   }
3090 
3091   void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
3092   {
3093     starti;
3094     assert(T != T1D, "reserved encoding");
3095     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
3096     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
3097     f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
3098   }
3099 
3100   // Advanced SIMD scalar copy
3101   void dup(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int index = 0)
3102   {
3103     starti;
3104     assert(T != Q, "invalid size");
3105     f(0b01011110000, 31, 21);
3106     f((1 << T) | (index << (T + 1)), 20, 16);
3107     f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
3108   }
3109 
3110   // AdvSIMD ZIP/UZP/TRN
3111 #define INSN(NAME, opcode)                                              \
3112   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
3113     guarantee(T != T1D && T != T1Q, "invalid arrangement");             \
3114     starti;                                                             \
3115     f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15);                  \
3116     f(opcode, 14, 12), f(0b10, 11, 10);                                 \
3117     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);                                   \
3118     f(T & 1, 30), f(T >> 1, 23, 22);                                    \
3119   }
3120 
3121   INSN(uzp1, 0b001);
3122   INSN(trn1, 0b010);
3123   INSN(zip1, 0b011);
3124   INSN(uzp2, 0b101);
3125   INSN(trn2, 0b110);
3126   INSN(zip2, 0b111);
3127 
3128 #undef INSN
3129 
3130   // CRC32 instructions
3131 #define INSN(NAME, c, sf, sz)                                             \
3132   void NAME(Register Rd, Register Rn, Register Rm) {                      \
3133     starti;                                                               \
3134     f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12);       \
3135     f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                      \
3136   }
3137 
3138   INSN(crc32b,  0, 0, 0b00);
3139   INSN(crc32h,  0, 0, 0b01);
3140   INSN(crc32w,  0, 0, 0b10);
3141   INSN(crc32x,  0, 1, 0b11);
3142   INSN(crc32cb, 1, 0, 0b00);
3143   INSN(crc32ch, 1, 0, 0b01);
3144   INSN(crc32cw, 1, 0, 0b10);
3145   INSN(crc32cx, 1, 1, 0b11);
3146 
3147 #undef INSN
3148 
3149   // Table vector lookup
3150 #define INSN(NAME, op)                                                  \
3151   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
3152     starti;                                                             \
3153     assert(T == T8B || T == T16B, "invalid arrangement");               \
3154     assert(0 < registers && registers <= 4, "invalid number of registers"); \
3155     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
3156     f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
3157   }
3158 
3159   INSN(tbl, 0);
3160   INSN(tbx, 1);
3161 
3162 #undef INSN
3163 
3164   // AdvSIMD two-reg misc
3165   // In this instruction group, the 2 bits in the size field ([23:22]) may be
3166   // fixed or determined by the "SIMD_Arrangement T", or both. The additional
3167   // parameter "tmask" is a 2-bit mask used to indicate which bits in the size
3168   // field are determined by the SIMD_Arrangement. The bit of "tmask" should be
3169   // set to 1 if corresponding bit marked as "x" in the ArmARM.
3170 #define INSN(NAME, U, size, tmask, opcode)                                          \
3171   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
3172        starti;                                                                      \
3173        assert((ASSERTION), MSG);                                                    \
3174        f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
3175        f(size | ((int)(T >> 1) & tmask), 23, 22), f(0b10000, 21, 17);               \
3176        f(opcode, 16, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                    \
3177  }
3178 
3179 #define MSG "invalid arrangement"
3180 
3181 #define ASSERTION (T == T2S || T == T4S || T == T2D)
3182   INSN(fsqrt,  1, 0b10, 0b01, 0b11111);
3183   INSN(fabs,   0, 0b10, 0b01, 0b01111);
3184   INSN(fneg,   1, 0b10, 0b01, 0b01111);
3185   INSN(frintn, 0, 0b00, 0b01, 0b11000);
3186   INSN(frintm, 0, 0b00, 0b01, 0b11001);
3187   INSN(frintp, 0, 0b10, 0b01, 0b11000);
3188   INSN(fcvtas, 0, 0b00, 0b01, 0b11100);
3189   INSN(fcvtzs, 0, 0b10, 0b01, 0b11011);
3190   INSN(fcvtms, 0, 0b00, 0b01, 0b11011);
3191 #undef ASSERTION
3192 
3193 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
3194   INSN(rev64, 0, 0b00, 0b11, 0b00000);
3195 #undef ASSERTION
3196 
3197 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
3198   INSN(rev32, 1, 0b00, 0b11, 0b00000);
3199 #undef ASSERTION
3200 
3201 #define ASSERTION (T == T8B || T == T16B)
3202   INSN(rev16, 0, 0b00, 0b11, 0b00001);
3203   INSN(rbit,  1, 0b01, 0b00, 0b00101);
3204 #undef ASSERTION
3205 
3206 #undef MSG
3207 
3208 #undef INSN
3209 
3210   // AdvSIMD compare with zero (vector)
3211   void cm(Condition cond, FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
3212     starti;
3213     assert(T != T1Q && T != T1D, "invalid arrangement");
3214     int cond_op;
3215     switch (cond) {
3216       case EQ: cond_op = 0b001; break;
3217       case GE: cond_op = 0b100; break;
3218       case GT: cond_op = 0b000; break;
3219       case LE: cond_op = 0b101; break;
3220       case LT: cond_op = 0b010; break;
3221       default:
3222         ShouldNotReachHere();
3223         break;
3224     }
3225 
3226     f(0, 31), f((int)T & 1, 30), f((cond_op >> 2) & 1, 29);
3227     f(0b01110, 28, 24), f((int)T >> 1, 23, 22), f(0b10000010, 21, 14);
3228     f(cond_op & 0b11, 13, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);
3229   }
3230 
3231   // AdvSIMD Floating-point compare with zero (vector)
3232   void fcm(Condition cond, FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
3233     starti;
3234     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
3235     int cond_op;
3236     switch (cond) {
3237       case EQ: cond_op = 0b010; break;
3238       case GT: cond_op = 0b000; break;
3239       case GE: cond_op = 0b001; break;
3240       case LE: cond_op = 0b011; break;
3241       case LT: cond_op = 0b100; break;
3242       default:
3243         ShouldNotReachHere();
3244         break;
3245     }
3246 
3247     f(0, 31), f((int)T & 1, 30), f(cond_op & 1, 29), f(0b011101, 28, 23);
3248     f(((int)(T >> 1) & 1), 22), f(0b10000011, 21, 14);
3249     f((cond_op >> 1) & 0b11, 13, 12), f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);
3250   }
3251 
3252   void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
3253   {
3254     starti;
3255     assert(T == T8B || T == T16B, "invalid arrangement");
3256     assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
3257     f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
3258     rf(Vm, 16), f(0, 15), f(index, 14, 11);
3259     f(0, 10), rf(Vn, 5), rf(Vd, 0);
3260   }
3261 
3262 // SVE arithmetic - unpredicated
3263 #define INSN(NAME, opcode)                                                             \
3264   void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) { \
3265     starti;                                                                            \
3266     assert(T != Q, "invalid register variant");                                        \
3267     f(0b00000100, 31, 24), f(T, 23, 22), f(1, 21),                                     \
3268     rf(Zm, 16), f(0, 15, 13), f(opcode, 12, 10), rf(Zn, 5), rf(Zd, 0);                 \
3269   }
3270   INSN(sve_add, 0b000);
3271   INSN(sve_sub, 0b001);
3272 #undef INSN
3273 
3274 // SVE integer add/subtract immediate (unpredicated)
3275 #define INSN(NAME, op)                                                  \
3276   void NAME(FloatRegister Zd, SIMD_RegVariant T, unsigned imm8) {       \
3277     starti;                                                             \
3278     /* The immediate is an unsigned value in the range 0 to 255, and    \
3279      * for element width of 16 bits or higher it may also be a          \
3280      * positive multiple of 256 in the range 256 to 65280.              \
3281      */                                                                 \
3282     assert(T != Q, "invalid size");                                     \
3283     int sh = 0;                                                         \
3284     if (imm8 <= 0xff) {                                                 \
3285       sh = 0;                                                           \
3286     } else if (T != B && imm8 <= 0xff00 && (imm8 & 0xff) == 0) {        \
3287       sh = 1;                                                           \
3288       imm8 = (imm8 >> 8);                                               \
3289     } else {                                                            \
3290       guarantee(false, "invalid immediate");                            \
3291     }                                                                   \
3292     f(0b00100101, 31, 24), f(T, 23, 22), f(0b10000, 21, 17);            \
3293     f(op, 16, 14), f(sh, 13), f(imm8, 12, 5), rf(Zd, 0);                \
3294   }
3295 
3296   INSN(sve_add, 0b011);
3297   INSN(sve_sub, 0b111);
3298 #undef INSN
3299 
3300 // SVE floating-point arithmetic - unpredicated
3301 #define INSN(NAME, opcode)                                                             \
3302   void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) { \
3303     starti;                                                                            \
3304     assert(T == S || T == D, "invalid register variant");                              \
3305     f(0b01100101, 31, 24), f(T, 23, 22), f(0, 21),                                     \
3306     rf(Zm, 16), f(0, 15, 13), f(opcode, 12, 10), rf(Zn, 5), rf(Zd, 0);                 \
3307   }
3308 
3309   INSN(sve_fadd, 0b000);
3310   INSN(sve_fmul, 0b010);
3311   INSN(sve_fsub, 0b001);
3312 #undef INSN
3313 
3314 private:
3315   void sve_predicate_reg_insn(unsigned op24, unsigned op13,
3316                               FloatRegister Zd_or_Vd, SIMD_RegVariant T,
3317                               PRegister Pg, FloatRegister Zn_or_Vn) {
3318     starti;
3319     f(op24, 31, 24), f(T, 23, 22), f(op13, 21, 13);
3320     pgrf(Pg, 10), rf(Zn_or_Vn, 5), rf(Zd_or_Vd, 0);
3321   }
3322 
3323   void sve_shift_imm_encoding(SIMD_RegVariant T, int shift, bool isSHR,
3324                               int& tszh, int& tszl_imm) {
3325     /* The encodings for the tszh:tszl:imm3 fields
3326      * for shift right is calculated as:
3327      *   0001 xxx       B, shift = 16  - UInt(tszh:tszl:imm3)
3328      *   001x xxx       H, shift = 32  - UInt(tszh:tszl:imm3)
3329      *   01xx xxx       S, shift = 64  - UInt(tszh:tszl:imm3)
3330      *   1xxx xxx       D, shift = 128 - UInt(tszh:tszl:imm3)
3331      * for shift left is calculated as:
3332      *   0001 xxx       B, shift = UInt(tszh:tszl:imm3) - 8
3333      *   001x xxx       H, shift = UInt(tszh:tszl:imm3) - 16
3334      *   01xx xxx       S, shift = UInt(tszh:tszl:imm3) - 32
3335      *   1xxx xxx       D, shift = UInt(tszh:tszl:imm3) - 64
3336      */
3337     assert(T != Q, "Invalid register variant");
3338     if (isSHR) {
3339       assert(((1 << (T + 3)) >= shift) && (shift > 0) , "Invalid shift value");
3340     } else {
3341       assert(((1 << (T + 3)) > shift) && (shift >= 0) , "Invalid shift value");
3342     }
3343     int cVal = (1 << ((T + 3) + (isSHR ? 1 : 0)));
3344     int encodedShift = isSHR ? cVal - shift : cVal + shift;
3345     tszh = encodedShift >> 5;
3346     tszl_imm = encodedShift & 0x1f;
3347   }
3348 
3349 public:
3350 
3351 // SVE integer arithmetic - predicate
3352 #define INSN(NAME, op1, op2)                                                                            \
3353   void NAME(FloatRegister Zdn_or_Zd_or_Vd, SIMD_RegVariant T, PRegister Pg, FloatRegister Znm_or_Vn) {  \
3354     assert(T != Q, "invalid register variant");                                                         \
3355     sve_predicate_reg_insn(op1, op2, Zdn_or_Zd_or_Vd, T, Pg, Znm_or_Vn);                                \
3356   }
3357 
3358   INSN(sve_abs,   0b00000100, 0b010110101); // vector abs, unary
3359   INSN(sve_add,   0b00000100, 0b000000000); // vector add
3360   INSN(sve_and,   0b00000100, 0b011010000); // vector and
3361   INSN(sve_andv,  0b00000100, 0b011010001); // bitwise and reduction to scalar
3362   INSN(sve_asr,   0b00000100, 0b010000100); // vector arithmetic shift right
3363   INSN(sve_bic,   0b00000100, 0b011011000); // vector bitwise clear
3364   INSN(sve_clz,   0b00000100, 0b011001101); // vector count leading zero bits
3365   INSN(sve_cnt,   0b00000100, 0b011010101); // count non-zero bits
3366   INSN(sve_cpy,   0b00000101, 0b100000100); // copy scalar to each active vector element
3367   INSN(sve_eor,   0b00000100, 0b011001000); // vector eor
3368   INSN(sve_eorv,  0b00000100, 0b011001001); // bitwise xor reduction to scalar
3369   INSN(sve_lsl,   0b00000100, 0b010011100); // vector logical shift left
3370   INSN(sve_lsr,   0b00000100, 0b010001100); // vector logical shift right
3371   INSN(sve_mul,   0b00000100, 0b010000000); // vector mul
3372   INSN(sve_neg,   0b00000100, 0b010111101); // vector neg, unary
3373   INSN(sve_not,   0b00000100, 0b011110101); // bitwise invert vector, unary
3374   INSN(sve_orr,   0b00000100, 0b011000000); // vector or
3375   INSN(sve_orv,   0b00000100, 0b011000001); // bitwise or reduction to scalar
3376   INSN(sve_smax,  0b00000100, 0b001000000); // signed maximum vectors
3377   INSN(sve_smaxv, 0b00000100, 0b001000001); // signed maximum reduction to scalar
3378   INSN(sve_smin,  0b00000100, 0b001010000); // signed minimum vectors
3379   INSN(sve_sminv, 0b00000100, 0b001010001); // signed minimum reduction to scalar
3380   INSN(sve_sub,   0b00000100, 0b000001000); // vector sub
3381   INSN(sve_uaddv, 0b00000100, 0b000001001); // unsigned add reduction to scalar
3382 #undef INSN
3383 
3384 // SVE floating-point arithmetic - predicate
3385 #define INSN(NAME, op1, op2)                                                                          \
3386   void NAME(FloatRegister Zd_or_Zdn_or_Vd, SIMD_RegVariant T, PRegister Pg, FloatRegister Zn_or_Zm) { \
3387     assert(T == S || T == D, "invalid register variant");                                             \
3388     sve_predicate_reg_insn(op1, op2, Zd_or_Zdn_or_Vd, T, Pg, Zn_or_Zm);                               \
3389   }
3390 
3391   INSN(sve_fabd,   0b01100101, 0b001000100); // floating-point absolute difference
3392   INSN(sve_fabs,   0b00000100, 0b011100101);
3393   INSN(sve_fadd,   0b01100101, 0b000000100);
3394   INSN(sve_fadda,  0b01100101, 0b011000001); // add strictly-ordered reduction to scalar Vd
3395   INSN(sve_fdiv,   0b01100101, 0b001101100);
3396   INSN(sve_fmax,   0b01100101, 0b000110100); // floating-point maximum
3397   INSN(sve_fmaxv,  0b01100101, 0b000110001); // floating-point maximum recursive reduction to scalar
3398   INSN(sve_fmin,   0b01100101, 0b000111100); // floating-point minimum
3399   INSN(sve_fminv,  0b01100101, 0b000111001); // floating-point minimum recursive reduction to scalar
3400   INSN(sve_fmul,   0b01100101, 0b000010100);
3401   INSN(sve_fneg,   0b00000100, 0b011101101);
3402   INSN(sve_frintm, 0b01100101, 0b000010101); // floating-point round to integral value, toward minus infinity
3403   INSN(sve_frintn, 0b01100101, 0b000000101); // floating-point round to integral value, nearest with ties to even
3404   INSN(sve_frinta, 0b01100101, 0b000100101); // floating-point round to integral value, nearest with ties to away
3405   INSN(sve_frintp, 0b01100101, 0b000001101); // floating-point round to integral value, toward plus infinity
3406   INSN(sve_fsqrt,  0b01100101, 0b001101101);
3407   INSN(sve_fsub,   0b01100101, 0b000001100);
3408 #undef INSN
3409 
3410   // SVE multiple-add/sub - predicated
3411 #define INSN(NAME, op0, op1, op2)                                                                     \
3412   void NAME(FloatRegister Zda, SIMD_RegVariant T, PRegister Pg, FloatRegister Zn, FloatRegister Zm) { \
3413     starti;                                                                                           \
3414     assert(T != Q, "invalid size");                                                                   \
3415     f(op0, 31, 24), f(T, 23, 22), f(op1, 21), rf(Zm, 16);                                             \
3416     f(op2, 15, 13), pgrf(Pg, 10), rf(Zn, 5), rf(Zda, 0);                                              \
3417   }
3418 
3419   INSN(sve_fmla,  0b01100101, 1, 0b000); // floating-point fused multiply-add, writing addend: Zda = Zda + Zn * Zm
3420   INSN(sve_fmls,  0b01100101, 1, 0b001); // floating-point fused multiply-subtract: Zda = Zda + -Zn * Zm
3421   INSN(sve_fnmla, 0b01100101, 1, 0b010); // floating-point negated fused multiply-add: Zda = -Zda + -Zn * Zm
3422   INSN(sve_fnmls, 0b01100101, 1, 0b011); // floating-point negated fused multiply-subtract: Zda = -Zda + Zn * Zm
3423   INSN(sve_fmad,  0b01100101, 1, 0b100); // floating-point fused multiply-add, writing multiplicand: Zda = Zm + Zda * Zn
3424   INSN(sve_fmsb,  0b01100101, 1, 0b101); // floating-point fused multiply-subtract, writing multiplicand: Zda = Zm + -Zda * Zn
3425   INSN(sve_fnmad, 0b01100101, 1, 0b110); // floating-point negated fused multiply-add, writing multiplicand: Zda = -Zm + -Zda * Zn
3426   INSN(sve_fnmsb, 0b01100101, 1, 0b111); // floating-point negated fused multiply-subtract, writing multiplicand: Zda = -Zm + Zda * Zn
3427   INSN(sve_mla,   0b00000100, 0, 0b010); // multiply-add, writing addend: Zda = Zda + Zn*Zm
3428   INSN(sve_mls,   0b00000100, 0, 0b011); // multiply-subtract, writing addend: Zda = Zda + -Zn*Zm
3429 #undef INSN
3430 
3431 // SVE bitwise logical - unpredicated
3432 #define INSN(NAME, opc)                                              \
3433   void NAME(FloatRegister Zd, FloatRegister Zn, FloatRegister Zm) {  \
3434     starti;                                                          \
3435     f(0b00000100, 31, 24), f(opc, 23, 22), f(1, 21),                 \
3436     rf(Zm, 16), f(0b001100, 15, 10), rf(Zn, 5), rf(Zd, 0);           \
3437   }
3438   INSN(sve_and, 0b00);
3439   INSN(sve_eor, 0b10);
3440   INSN(sve_orr, 0b01);
3441   INSN(sve_bic, 0b11);
3442 #undef INSN
3443 
3444 // SVE bitwise logical with immediate (unpredicated)
3445 #define INSN(NAME, opc)                                                      \
3446   void NAME(FloatRegister Zd, SIMD_RegVariant T, uint64_t imm) {             \
3447     starti;                                                                  \
3448     unsigned elembits = regVariant_to_elemBits(T);                           \
3449     uint32_t val = encode_sve_logical_immediate(elembits, imm);              \
3450     f(0b00000101, 31, 24), f(opc, 23, 22), f(0b0000, 21, 18);                \
3451     f(val, 17, 5), rf(Zd, 0);                                                \
3452   }
3453   INSN(sve_and, 0b10);
3454   INSN(sve_eor, 0b01);
3455   INSN(sve_orr, 0b00);
3456 #undef INSN
3457 
3458 // SVE shift immediate - unpredicated
3459 #define INSN(NAME, opc, isSHR)                                                  \
3460   void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, int shift) { \
3461     starti;                                                                     \
3462     int tszh, tszl_imm;                                                         \
3463     sve_shift_imm_encoding(T, shift, isSHR, tszh, tszl_imm);                    \
3464     f(0b00000100, 31, 24);                                                      \
3465     f(tszh, 23, 22), f(1,21), f(tszl_imm, 20, 16);                              \
3466     f(0b100, 15, 13), f(opc, 12, 10), rf(Zn, 5), rf(Zd, 0);                     \
3467   }
3468 
3469   INSN(sve_asr, 0b100, /* isSHR = */ true);
3470   INSN(sve_lsl, 0b111, /* isSHR = */ false);
3471   INSN(sve_lsr, 0b101, /* isSHR = */ true);
3472 #undef INSN
3473 
3474 // SVE bitwise shift by immediate (predicated)
3475 #define INSN(NAME, opc, isSHR)                                                  \
3476   void NAME(FloatRegister Zdn, SIMD_RegVariant T, PRegister Pg, int shift) {    \
3477     starti;                                                                     \
3478     int tszh, tszl_imm;                                                         \
3479     sve_shift_imm_encoding(T, shift, isSHR, tszh, tszl_imm);                    \
3480     f(0b00000100, 31, 24), f(tszh, 23, 22), f(0b00, 21, 20), f(opc, 19, 16);    \
3481     f(0b100, 15, 13), pgrf(Pg, 10), f(tszl_imm, 9, 5), rf(Zdn, 0);              \
3482   }
3483 
3484   INSN(sve_asr, 0b0000, /* isSHR = */ true);
3485   INSN(sve_lsl, 0b0011, /* isSHR = */ false);
3486   INSN(sve_lsr, 0b0001, /* isSHR = */ true);
3487 #undef INSN
3488 
3489 private:
3490 
3491   // Scalar base + immediate index
3492   void sve_ld_st1(FloatRegister Zt, Register Xn, int imm, PRegister Pg,
3493               SIMD_RegVariant T, int op1, int type, int op2) {
3494     starti;
3495     assert_cond(T >= type);
3496     f(op1, 31, 25), f(type, 24, 23), f(T, 22, 21);
3497     f(0, 20), sf(imm, 19, 16), f(op2, 15, 13);
3498     pgrf(Pg, 10), srf(Xn, 5), rf(Zt, 0);
3499   }
3500 
3501   // Scalar base + scalar index
3502   void sve_ld_st1(FloatRegister Zt, Register Xn, Register Xm, PRegister Pg,
3503               SIMD_RegVariant T, int op1, int type, int op2) {
3504     starti;
3505     assert_cond(T >= type);
3506     f(op1, 31, 25), f(type, 24, 23), f(T, 22, 21);
3507     rf(Xm, 16), f(op2, 15, 13);
3508     pgrf(Pg, 10), srf(Xn, 5), rf(Zt, 0);
3509   }
3510 
3511   void sve_ld_st1(FloatRegister Zt, PRegister Pg,
3512               SIMD_RegVariant T, const Address &a,
3513               int op1, int type, int imm_op2, int scalar_op2) {
3514     switch (a.getMode()) {
3515     case Address::base_plus_offset:
3516       sve_ld_st1(Zt, a.base(), a.offset(), Pg, T, op1, type, imm_op2);
3517       break;
3518     case Address::base_plus_offset_reg:
3519       sve_ld_st1(Zt, a.base(), a.index(), Pg, T, op1, type, scalar_op2);
3520       break;
3521     default:
3522       ShouldNotReachHere();
3523     }
3524   }
3525 
3526 public:
3527 
3528 // SVE contiguous load/store
3529 #define INSN(NAME, op1, type, imm_op2, scalar_op2)                                   \
3530   void NAME(FloatRegister Zt, SIMD_RegVariant T, PRegister Pg, const Address &a) {   \
3531     assert(T != Q, "invalid register variant");                                      \
3532     sve_ld_st1(Zt, Pg, T, a, op1, type, imm_op2, scalar_op2);                        \
3533   }
3534 
3535   INSN(sve_ld1b, 0b1010010, 0b00, 0b101, 0b010);
3536   INSN(sve_st1b, 0b1110010, 0b00, 0b111, 0b010);
3537   INSN(sve_ld1h, 0b1010010, 0b01, 0b101, 0b010);
3538   INSN(sve_st1h, 0b1110010, 0b01, 0b111, 0b010);
3539   INSN(sve_ld1w, 0b1010010, 0b10, 0b101, 0b010);
3540   INSN(sve_st1w, 0b1110010, 0b10, 0b111, 0b010);
3541   INSN(sve_ld1d, 0b1010010, 0b11, 0b101, 0b010);
3542   INSN(sve_st1d, 0b1110010, 0b11, 0b111, 0b010);
3543 #undef INSN
3544 
3545 // Gather/scatter load/store (SVE) - scalar plus vector
3546 #define INSN(NAME, op1, type, op2, op3)                                         \
3547   void NAME(FloatRegister Zt, PRegister Pg, Register Xn, FloatRegister Zm) {    \
3548     starti;                                                                     \
3549     f(op1, 31, 25), f(type, 24, 23), f(op2, 22, 21), rf(Zm, 16);                \
3550     f(op3, 15, 13), pgrf(Pg, 10), srf(Xn, 5), rf(Zt, 0);                        \
3551   }
3552   // SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)
3553   INSN(sve_ld1w_gather,  0b1000010, 0b10, 0b01, 0b010);
3554   // SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
3555   INSN(sve_ld1d_gather,  0b1100010, 0b11, 0b01, 0b010);
3556   // SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
3557   INSN(sve_st1w_scatter, 0b1110010, 0b10, 0b11, 0b100);
3558   // SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)
3559   INSN(sve_st1d_scatter, 0b1110010, 0b11, 0b01, 0b100);
3560 #undef INSN
3561 
3562 // SVE load/store - unpredicated
3563 #define INSN(NAME, op1)                                                         \
3564   void NAME(FloatRegister Zt, const Address &a)  {                              \
3565     starti;                                                                     \
3566     assert(a.index() == noreg, "invalid address variant");                      \
3567     f(op1, 31, 29), f(0b0010110, 28, 22), sf(a.offset() >> 3, 21, 16),          \
3568     f(0b010, 15, 13), f(a.offset() & 0x7, 12, 10), srf(a.base(), 5), rf(Zt, 0); \
3569   }
3570 
3571   INSN(sve_ldr, 0b100); // LDR (vector)
3572   INSN(sve_str, 0b111); // STR (vector)
3573 #undef INSN
3574 
3575 // SVE stack frame adjustment
3576 #define INSN(NAME, op) \
3577   void NAME(Register Xd, Register Xn, int imm6) {                 \
3578     starti;                                                       \
3579     f(0b000001000, 31, 23), f(op, 22, 21);                        \
3580     srf(Xn, 16), f(0b01010, 15, 11), sf(imm6, 10, 5), srf(Xd, 0); \
3581   }
3582 
3583   INSN(sve_addvl, 0b01); // Add multiple of vector register size to scalar register
3584   INSN(sve_addpl, 0b11); // Add multiple of predicate register size to scalar register
3585 #undef INSN
3586 
3587 // SVE inc/dec register by element count
3588 #define INSN(NAME, op) \
3589   void NAME(Register Xdn, SIMD_RegVariant T, unsigned imm4 = 1, int pattern = 0b11111) { \
3590     starti;                                                                              \
3591     assert(T != Q, "invalid size");                                                      \
3592     f(0b00000100,31, 24), f(T, 23, 22), f(0b11, 21, 20);                                 \
3593     f(imm4 - 1, 19, 16), f(0b11100, 15, 11), f(op, 10), f(pattern, 9, 5), rf(Xdn, 0);    \
3594   }
3595 
3596   INSN(sve_inc, 0);
3597   INSN(sve_dec, 1);
3598 #undef INSN
3599 
3600 // SVE predicate logical operations
3601 #define INSN(NAME, op1, op2, op3) \
3602   void NAME(PRegister Pd, PRegister Pg, PRegister Pn, PRegister Pm) { \
3603     starti;                                                           \
3604     f(0b00100101, 31, 24), f(op1, 23, 22), f(0b00, 21, 20);           \
3605     prf(Pm, 16), f(0b01, 15, 14), prf(Pg, 10), f(op2, 9);             \
3606     prf(Pn, 5), f(op3, 4), prf(Pd, 0);                                \
3607   }
3608 
3609   INSN(sve_and,  0b00, 0b0, 0b0);
3610   INSN(sve_ands, 0b01, 0b0, 0b0);
3611   INSN(sve_eor,  0b00, 0b1, 0b0);
3612   INSN(sve_eors, 0b01, 0b1, 0b0);
3613   INSN(sve_orr,  0b10, 0b0, 0b0);
3614   INSN(sve_orrs, 0b11, 0b0, 0b0);
3615   INSN(sve_bic,  0b00, 0b0, 0b1);
3616 #undef INSN
3617 
3618   // SVE increment register by predicate count
3619   void sve_incp(const Register rd, SIMD_RegVariant T, PRegister pg) {
3620     starti;
3621     assert(T != Q, "invalid size");
3622     f(0b00100101, 31, 24), f(T, 23, 22), f(0b1011001000100, 21, 9),
3623     prf(pg, 5), rf(rd, 0);
3624   }
3625 
3626   // SVE broadcast general-purpose register to vector elements (unpredicated)
3627   void sve_dup(FloatRegister Zd, SIMD_RegVariant T, Register Rn) {
3628     starti;
3629     assert(T != Q, "invalid size");
3630     f(0b00000101, 31, 24), f(T, 23, 22), f(0b100000001110, 21, 10);
3631     srf(Rn, 5), rf(Zd, 0);
3632   }
3633 
3634   // SVE broadcast signed immediate to vector elements (unpredicated)
3635   void sve_dup(FloatRegister Zd, SIMD_RegVariant T, int imm8) {
3636     starti;
3637     assert(T != Q, "invalid size");
3638     int sh = 0;
3639     if (imm8 <= 127 && imm8 >= -128) {
3640       sh = 0;
3641     } else if (T != B && imm8 <= 32512 && imm8 >= -32768 && (imm8 & 0xff) == 0) {
3642       sh = 1;
3643       imm8 = (imm8 >> 8);
3644     } else {
3645       guarantee(false, "invalid immediate");
3646     }
3647     f(0b00100101, 31, 24), f(T, 23, 22), f(0b11100011, 21, 14);
3648     f(sh, 13), sf(imm8, 12, 5), rf(Zd, 0);
3649   }
3650 
3651   // SVE predicate test
3652   void sve_ptest(PRegister Pg, PRegister Pn) {
3653     starti;
3654     f(0b001001010101000011, 31, 14), prf(Pg, 10), f(0, 9), prf(Pn, 5), f(0, 4, 0);
3655   }
3656 
3657   // SVE predicate initialize
3658   void sve_ptrue(PRegister pd, SIMD_RegVariant esize, int pattern = 0b11111) {
3659     starti;
3660     f(0b00100101, 31, 24), f(esize, 23, 22), f(0b011000111000, 21, 10);
3661     f(pattern, 9, 5), f(0b0, 4), prf(pd, 0);
3662   }
3663 
3664   // SVE predicate zero
3665   void sve_pfalse(PRegister pd) {
3666     starti;
3667     f(0b00100101, 31, 24), f(0b00, 23, 22), f(0b011000111001, 21, 10);
3668     f(0b000000, 9, 4), prf(pd, 0);
3669   }
3670 
3671 // SVE load/store predicate register
3672 #define INSN(NAME, op1)                                                  \
3673   void NAME(PRegister Pt, const Address &a)  {                           \
3674     starti;                                                              \
3675     assert(a.index() == noreg, "invalid address variant");               \
3676     f(op1, 31, 29), f(0b0010110, 28, 22), sf(a.offset() >> 3, 21, 16),   \
3677     f(0b000, 15, 13), f(a.offset() & 0x7, 12, 10), srf(a.base(), 5),     \
3678     f(0, 4), prf(Pt, 0);                                                 \
3679   }
3680 
3681   INSN(sve_ldr, 0b100); // LDR (predicate)
3682   INSN(sve_str, 0b111); // STR (predicate)
3683 #undef INSN
3684 
3685   // SVE move predicate register
3686   void sve_mov(PRegister Pd, PRegister Pn) {
3687     starti;
3688     f(0b001001011000, 31, 20), prf(Pn, 16), f(0b01, 15, 14), prf(Pn, 10);
3689     f(0, 9), prf(Pn, 5), f(0, 4), prf(Pd, 0);
3690   }
3691 
3692   // SVE copy general-purpose register to vector elements (predicated)
3693   void sve_cpy(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, Register Rn) {
3694     starti;
3695     assert(T != Q, "invalid size");
3696     f(0b00000101, 31, 24), f(T, 23, 22), f(0b101000101, 21, 13);
3697     pgrf(Pg, 10), srf(Rn, 5), rf(Zd, 0);
3698   }
3699 
3700 private:
3701   void sve_cpy(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int imm8,
3702                bool isMerge, bool isFloat) {
3703     starti;
3704     assert(T != Q, "invalid size");
3705     int sh = 0;
3706     if (imm8 <= 127 && imm8 >= -128) {
3707       sh = 0;
3708     } else if (T != B && imm8 <= 32512 && imm8 >= -32768 && (imm8 & 0xff) == 0) {
3709       sh = 1;
3710       imm8 = (imm8 >> 8);
3711     } else {
3712       guarantee(false, "invalid immediate");
3713     }
3714     int m = isMerge ? 1 : 0;
3715     f(0b00000101, 31, 24), f(T, 23, 22), f(0b01, 21, 20);
3716     prf(Pg, 16), f(isFloat ? 1 : 0, 15), f(m, 14), f(sh, 13), sf(imm8, 12, 5), rf(Zd, 0);
3717   }
3718 
3719 public:
3720   // SVE copy signed integer immediate to vector elements (predicated)
3721   void sve_cpy(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, int imm8, bool isMerge) {
3722     sve_cpy(Zd, T, Pg, imm8, isMerge, /*isFloat*/false);
3723   }
3724   // SVE copy floating-point immediate to vector elements (predicated)
3725   void sve_cpy(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg, double d) {
3726     sve_cpy(Zd, T, Pg, checked_cast<int8_t>(pack(d)), /*isMerge*/true, /*isFloat*/true);
3727   }
3728 
3729   // SVE conditionally select elements from two vectors
3730   void sve_sel(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg,
3731                FloatRegister Zn, FloatRegister Zm) {
3732     starti;
3733     assert(T != Q, "invalid size");
3734     f(0b00000101, 31, 24), f(T, 23, 22), f(0b1, 21), rf(Zm, 16);
3735     f(0b11, 15, 14), prf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
3736   }
3737 
3738   // SVE Permute Vector - Extract
3739   void sve_ext(FloatRegister Zdn, FloatRegister Zm, int imm8) {
3740     starti;
3741     f(0b00000101001, 31, 21), f(imm8 >> 3, 20, 16), f(0b000, 15, 13);
3742     f(imm8 & 0b111, 12, 10), rf(Zm, 5), rf(Zdn, 0);
3743   }
3744 
3745 // SVE Integer/Floating-Point Compare - Vectors
3746 #define INSN(NAME, op1, op2, fp)  \
3747   void NAME(Condition cond, PRegister Pd, SIMD_RegVariant T, PRegister Pg,             \
3748             FloatRegister Zn, FloatRegister Zm) {                                      \
3749     starti;                                                                            \
3750     assert(T != Q, "invalid size");                                                    \
3751     bool is_absolute = op2 == 0b11;                                                    \
3752     if (fp == 1) {                                                                     \
3753       assert(T != B, "invalid size");                                                  \
3754       if (is_absolute) {                                                               \
3755         assert(cond == GT || cond == GE, "invalid condition for fac");                 \
3756       } else {                                                                         \
3757         assert(cond != HI && cond != HS, "invalid condition for fcm");                 \
3758       }                                                                                \
3759     }                                                                                  \
3760     int cond_op;                                                                       \
3761     switch(cond) {                                                                     \
3762       case EQ: cond_op = (op2 << 2) | 0b10; break;                                     \
3763       case NE: cond_op = (op2 << 2) | 0b11; break;                                     \
3764       case GE: cond_op = (op2 << 2) | (is_absolute ? 0b01 : 0b00); break;              \
3765       case GT: cond_op = (op2 << 2) | (is_absolute ? 0b11 : 0b01); break;              \
3766       case HI: cond_op = 0b0001; break;                                                \
3767       case HS: cond_op = 0b0000; break;                                                \
3768       default:                                                                         \
3769         ShouldNotReachHere();                                                          \
3770     }                                                                                  \
3771     f(op1, 31, 24), f(T, 23, 22), f(0, 21), rf(Zm, 16), f((cond_op >> 1) & 7, 15, 13); \
3772     pgrf(Pg, 10), rf(Zn, 5), f(cond_op & 1, 4), prf(Pd, 0);                            \
3773   }
3774 
3775   INSN(sve_cmp, 0b00100100, 0b10, 0); // Integer compare vectors
3776   INSN(sve_fcm, 0b01100101, 0b01, 1); // Floating-point compare vectors
3777   INSN(sve_fac, 0b01100101, 0b11, 1); // Floating-point absolute compare vectors
3778 #undef INSN
3779 
3780 private:
3781   // Convert Assembler::Condition to op encoding - used by sve integer compare encoding
3782   static int assembler_cond_to_sve_op(Condition cond, bool &is_unsigned) {
3783     if (cond == HI || cond == HS || cond == LO || cond == LS) {
3784       is_unsigned = true;
3785     } else {
3786       is_unsigned = false;
3787     }
3788 
3789     switch (cond) {
3790       case HI:
3791       case GT:
3792         return 0b0001;
3793       case HS:
3794       case GE:
3795         return 0b0000;
3796       case LO:
3797       case LT:
3798         return 0b0010;
3799       case LS:
3800       case LE:
3801         return 0b0011;
3802       case EQ:
3803         return 0b1000;
3804       case NE:
3805         return 0b1001;
3806       default:
3807         ShouldNotReachHere();
3808         return -1;
3809     }
3810   }
3811 
3812 public:
3813   // SVE Integer Compare - 5 bits signed imm and 7 bits unsigned imm
3814   void sve_cmp(Condition cond, PRegister Pd, SIMD_RegVariant T,
3815                PRegister Pg, FloatRegister Zn, int imm) {
3816     starti;
3817     assert(T != Q, "invalid size");
3818     bool is_unsigned = false;
3819     int cond_op = assembler_cond_to_sve_op(cond, is_unsigned);
3820     f(is_unsigned ? 0b00100100 : 0b00100101, 31, 24), f(T, 23, 22);
3821     f(is_unsigned ? 0b1 : 0b0, 21);
3822     if (is_unsigned) {
3823       f(imm, 20, 14), f((cond_op >> 1) & 0x1, 13);
3824     } else {
3825       sf(imm, 20, 16), f((cond_op >> 1) & 0x7, 15, 13);
3826     }
3827     pgrf(Pg, 10), rf(Zn, 5), f(cond_op & 0x1, 4), prf(Pd, 0);
3828   }
3829 
3830   // SVE Floating-point compare vector with zero
3831   void sve_fcm(Condition cond, PRegister Pd, SIMD_RegVariant T,
3832                PRegister Pg, FloatRegister Zn, double d) {
3833     starti;
3834     assert(T != Q, "invalid size");
3835     guarantee(d == 0.0, "invalid immediate");
3836     int cond_op;
3837     switch(cond) {
3838       case EQ: cond_op = 0b100; break;
3839       case GT: cond_op = 0b001; break;
3840       case GE: cond_op = 0b000; break;
3841       case LT: cond_op = 0b010; break;
3842       case LE: cond_op = 0b011; break;
3843       case NE: cond_op = 0b110; break;
3844       default:
3845         ShouldNotReachHere();
3846     }
3847     f(0b01100101, 31, 24), f(T, 23, 22), f(0b0100, 21, 18),
3848     f((cond_op >> 1) & 0x3, 17, 16), f(0b001, 15, 13),
3849     pgrf(Pg, 10), rf(Zn, 5);
3850     f(cond_op & 0x1, 4), prf(Pd, 0);
3851   }
3852 
3853 // SVE unpack vector elements
3854 #define INSN(NAME, op) \
3855   void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) { \
3856     starti;                                                          \
3857     assert(T != B && T != Q, "invalid size");                        \
3858     f(0b00000101, 31, 24), f(T, 23, 22), f(0b1100, 21, 18);          \
3859     f(op, 17, 16), f(0b001110, 15, 10), rf(Zn, 5), rf(Zd, 0);        \
3860   }
3861 
3862   INSN(sve_uunpkhi, 0b11); // Signed unpack and extend half of vector - high half
3863   INSN(sve_uunpklo, 0b10); // Signed unpack and extend half of vector - low half
3864   INSN(sve_sunpkhi, 0b01); // Unsigned unpack and extend half of vector - high half
3865   INSN(sve_sunpklo, 0b00); // Unsigned unpack and extend half of vector - low half
3866 #undef INSN
3867 
3868 // SVE unpack predicate elements
3869 #define INSN(NAME, op) \
3870   void NAME(PRegister Pd, PRegister Pn) { \
3871     starti;                                                          \
3872     f(0b000001010011000, 31, 17), f(op, 16), f(0b0100000, 15, 9);    \
3873     prf(Pn, 5), f(0b0, 4), prf(Pd, 0);                               \
3874   }
3875 
3876   INSN(sve_punpkhi, 0b1); // Unpack and widen high half of predicate
3877   INSN(sve_punpklo, 0b0); // Unpack and widen low half of predicate
3878 #undef INSN
3879 
3880 // SVE permute vector elements
3881 #define INSN(NAME, op) \
3882   void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) { \
3883     starti;                                                                            \
3884     assert(T != Q, "invalid size");                                                    \
3885     f(0b00000101, 31, 24), f(T, 23, 22), f(0b1, 21), rf(Zm, 16);                       \
3886     f(0b01101, 15, 11), f(op, 10), rf(Zn, 5), rf(Zd, 0);                               \
3887   }
3888 
3889   INSN(sve_uzp1, 0b0); // Concatenate even elements from two vectors
3890   INSN(sve_uzp2, 0b1); // Concatenate odd elements from two vectors
3891 #undef INSN
3892 
3893 // SVE permute predicate elements
3894 #define INSN(NAME, op) \
3895   void NAME(PRegister Pd, SIMD_RegVariant T, PRegister Pn, PRegister Pm) {             \
3896     starti;                                                                            \
3897     assert(T != Q, "invalid size");                                                    \
3898     f(0b00000101, 31, 24), f(T, 23, 22), f(0b10, 21, 20), prf(Pm, 16);                 \
3899     f(0b01001, 15, 11), f(op, 10), f(0b0, 9), prf(Pn, 5), f(0b0, 4), prf(Pd, 0);       \
3900   }
3901 
3902   INSN(sve_uzp1, 0b0); // Concatenate even elements from two predicates
3903   INSN(sve_uzp2, 0b1); // Concatenate odd elements from two predicates
3904 #undef INSN
3905 
3906 // SVE integer compare scalar count and limit
3907 #define INSN(NAME, sf, op)                                                \
3908   void NAME(PRegister Pd, SIMD_RegVariant T, Register Rn, Register Rm) {  \
3909     starti;                                                               \
3910     assert(T != Q, "invalid register variant");                           \
3911     f(0b00100101, 31, 24), f(T, 23, 22), f(1, 21),                        \
3912     zrf(Rm, 16), f(0, 15, 13), f(sf, 12), f(op >> 1, 11, 10),             \
3913     zrf(Rn, 5), f(op & 1, 4), prf(Pd, 0);                                 \
3914   }
3915   // While incrementing signed scalar less than scalar
3916   INSN(sve_whileltw, 0b0, 0b010);
3917   INSN(sve_whilelt,  0b1, 0b010);
3918   // While incrementing signed scalar less than or equal to scalar
3919   INSN(sve_whilelew, 0b0, 0b011);
3920   INSN(sve_whilele,  0b1, 0b011);
3921   // While incrementing unsigned scalar lower than scalar
3922   INSN(sve_whilelow, 0b0, 0b110);
3923   INSN(sve_whilelo,  0b1, 0b110);
3924   // While incrementing unsigned scalar lower than or the same as scalar
3925   INSN(sve_whilelsw, 0b0, 0b111);
3926   INSN(sve_whilels,  0b1, 0b111);
3927 #undef INSN
3928 
3929   // SVE predicate reverse
3930   void sve_rev(PRegister Pd, SIMD_RegVariant T, PRegister Pn) {
3931     starti;
3932     assert(T != Q, "invalid size");
3933     f(0b00000101, 31, 24), f(T, 23, 22), f(0b1101000100000, 21, 9);
3934     prf(Pn, 5), f(0, 4), prf(Pd, 0);
3935   }
3936 
3937 // SVE partition break condition
3938 #define INSN(NAME, op) \
3939   void NAME(PRegister Pd, PRegister Pg, PRegister Pn, bool isMerge) {      \
3940     starti;                                                                \
3941     f(0b00100101, 31, 24), f(op, 23, 22), f(0b01000001, 21, 14);           \
3942     prf(Pg, 10), f(0b0, 9), prf(Pn, 5), f(isMerge ? 1 : 0, 4), prf(Pd, 0); \
3943   }
3944 
3945   INSN(sve_brka, 0b00); // Break after first true condition
3946   INSN(sve_brkb, 0b10); // Break before first true condition
3947 #undef INSN
3948 
3949 // Element count and increment scalar (SVE)
3950 #define INSN(NAME, TYPE)                                                             \
3951   void NAME(Register Xdn, unsigned imm4 = 1, int pattern = 0b11111) {                \
3952     starti;                                                                          \
3953     f(0b00000100, 31, 24), f(TYPE, 23, 22), f(0b10, 21, 20);                         \
3954     f(imm4 - 1, 19, 16), f(0b11100, 15, 11), f(0, 10), f(pattern, 9, 5), rf(Xdn, 0); \
3955   }
3956 
3957   INSN(sve_cntb, B);  // Set scalar to multiple of 8-bit predicate constraint element count
3958   INSN(sve_cnth, H);  // Set scalar to multiple of 16-bit predicate constraint element count
3959   INSN(sve_cntw, S);  // Set scalar to multiple of 32-bit predicate constraint element count
3960   INSN(sve_cntd, D);  // Set scalar to multiple of 64-bit predicate constraint element count
3961 #undef INSN
3962 
3963   // Set scalar to active predicate element count
3964   void sve_cntp(Register Xd, SIMD_RegVariant T, PRegister Pg, PRegister Pn) {
3965     starti;
3966     assert(T != Q, "invalid size");
3967     f(0b00100101, 31, 24), f(T, 23, 22), f(0b10000010, 21, 14);
3968     prf(Pg, 10), f(0, 9), prf(Pn, 5), rf(Xd, 0);
3969   }
3970 
3971   // SVE convert signed integer to floating-point (predicated)
3972   void sve_scvtf(FloatRegister Zd, SIMD_RegVariant T_dst, PRegister Pg,
3973                  FloatRegister Zn, SIMD_RegVariant T_src) {
3974     starti;
3975     assert(T_src != B && T_dst != B && T_src != Q && T_dst != Q &&
3976            (T_src != H || T_dst == T_src), "invalid register variant");
3977     int opc = T_dst;
3978     int opc2 = T_src;
3979     // In most cases we can treat T_dst, T_src as opc, opc2,
3980     // except for the following two combinations.
3981     // +-----+------+---+------------------------------------+
3982     // | opc | opc2 | U |        Instruction Details         |
3983     // +-----+------+---+------------------------------------+
3984     // |  11 |   00 | 0 | SCVTF - 32-bit to double-precision |
3985     // |  11 |   10 | 0 | SCVTF - 64-bit to single-precision |
3986     // +-----+------+---+------------------------------------+
3987     if (T_src == S && T_dst == D) {
3988       opc = 0b11;
3989       opc2 = 0b00;
3990     } else if (T_src == D && T_dst == S) {
3991       opc = 0b11;
3992       opc2 = 0b10;
3993     }
3994     f(0b01100101, 31, 24), f(opc, 23, 22), f(0b010, 21, 19);
3995     f(opc2, 18, 17), f(0b0101, 16, 13);
3996     pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
3997   }
3998 
3999   // SVE floating-point convert to signed integer, rounding toward zero (predicated)
4000   void sve_fcvtzs(FloatRegister Zd, SIMD_RegVariant T_dst, PRegister Pg,
4001                   FloatRegister Zn, SIMD_RegVariant T_src) {
4002     starti;
4003     assert(T_src != B && T_dst != B && T_src != Q && T_dst != Q &&
4004            (T_dst != H || T_src == H), "invalid register variant");
4005     int opc = T_src;
4006     int opc2 = T_dst;
4007     // In most cases we can treat T_src, T_dst as opc, opc2,
4008     // except for the following two combinations.
4009     // +-----+------+---+-------------------------------------+
4010     // | opc | opc2 | U |         Instruction Details         |
4011     // +-----+------+---+-------------------------------------+
4012     // |  11 |  10  | 0 | FCVTZS - single-precision to 64-bit |
4013     // |  11 |  00  | 0 | FCVTZS - double-precision to 32-bit |
4014     // +-----+------+---+-------------------------------------+
4015     if (T_src == S && T_dst == D) {
4016       opc = 0b11;
4017       opc2 = 0b10;
4018     } else if (T_src == D && T_dst == S) {
4019       opc = 0b11;
4020       opc2 = 0b00;
4021     }
4022     f(0b01100101, 31, 24), f(opc, 23, 22), f(0b011, 21, 19);
4023     f(opc2, 18, 17), f(0b0101, 16, 13);
4024     pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
4025   }
4026 
4027   // SVE floating-point convert precision (predicated)
4028   void sve_fcvt(FloatRegister Zd, SIMD_RegVariant T_dst, PRegister Pg,
4029                 FloatRegister Zn, SIMD_RegVariant T_src) {
4030     starti;
4031     assert(T_src != B && T_dst != B && T_src != Q && T_dst != Q &&
4032            T_src != T_dst, "invalid register variant");
4033     // The encodings of fields op1 (bits 17-16) and op2 (bits 23-22)
4034     // depend on T_src and T_dst as given below -
4035     // +-----+------+---------------------------------------------+
4036     // | op2 | op1  |             Instruction Details             |
4037     // +-----+------+---------------------------------------------+
4038     // |  10 |  01  | FCVT - half-precision to single-precision   |
4039     // |  11 |  01  | FCVT - half-precision to double-precision   |
4040     // |  10 |  00  | FCVT - single-precision to half-precision   |
4041     // |  11 |  11  | FCVT - single-precision to double-precision |
4042     // |  11 |  00  | FCVT - double-preciison to half-precision   |
4043     // |  11 |  10  | FCVT - double-precision to single-precision |
4044     // +-----+------+---+-----------------------------------------+
4045     int op1 = 0b00;
4046     int op2 = (T_src == D || T_dst == D) ? 0b11 : 0b10;
4047     if (T_src == H) {
4048       op1 = 0b01;
4049     } else if (T_dst == S) {
4050       op1 = 0b10;
4051     } else if (T_dst == D) {
4052       op1 = 0b11;
4053     }
4054     f(0b01100101, 31, 24), f(op2, 23, 22), f(0b0010, 21, 18);
4055     f(op1, 17, 16), f(0b101, 15, 13);
4056     pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
4057   }
4058 
4059 // SVE extract element to general-purpose register
4060 #define INSN(NAME, before)                                                      \
4061   void NAME(Register Rd, SIMD_RegVariant T, PRegister Pg,  FloatRegister Zn) {  \
4062     starti;                                                                     \
4063     f(0b00000101, 31, 24), f(T, 23, 22), f(0b10000, 21, 17);                    \
4064     f(before, 16), f(0b101, 15, 13);                                            \
4065     pgrf(Pg, 10), rf(Zn, 5), rf(Rd, 0);                                         \
4066   }
4067 
4068   INSN(sve_lasta, 0b0);
4069   INSN(sve_lastb, 0b1);
4070 #undef INSN
4071 
4072 // SVE extract element to SIMD&FP scalar register
4073 #define INSN(NAME, before)                                                           \
4074   void NAME(FloatRegister Vd, SIMD_RegVariant T, PRegister Pg,  FloatRegister Zn) {  \
4075     starti;                                                                          \
4076     f(0b00000101, 31, 24), f(T, 23, 22), f(0b10001, 21, 17);                         \
4077     f(before, 16), f(0b100, 15, 13);                                                 \
4078     pgrf(Pg, 10), rf(Zn, 5), rf(Vd, 0);                                              \
4079   }
4080 
4081   INSN(sve_lasta, 0b0);
4082   INSN(sve_lastb, 0b1);
4083 #undef INSN
4084 
4085 // SVE reverse within elements
4086 #define INSN(NAME, opc, cond)                                                        \
4087   void NAME(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg,  FloatRegister Zn) {  \
4088     starti;                                                                          \
4089     assert(cond, "invalid size");                                                    \
4090     f(0b00000101, 31, 24), f(T, 23, 22), f(0b1001, 21, 18), f(opc, 17, 16);          \
4091     f(0b100, 15, 13), pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);                            \
4092   }
4093 
4094   INSN(sve_revb, 0b00, T == H || T == S || T == D);
4095   INSN(sve_rbit, 0b11, T != Q);
4096 #undef INSN
4097 
4098   // SVE Create index starting from general-purpose register and incremented by immediate
4099   void sve_index(FloatRegister Zd, SIMD_RegVariant T, Register Rn, int imm) {
4100     starti;
4101     assert(T != Q, "invalid size");
4102     f(0b00000100, 31, 24), f(T, 23, 22), f(0b1, 21);
4103     sf(imm, 20, 16), f(0b010001, 15, 10);
4104     rf(Rn, 5), rf(Zd, 0);
4105   }
4106 
4107   // SVE create index starting from and incremented by immediate
4108   void sve_index(FloatRegister Zd, SIMD_RegVariant T, int imm1, int imm2) {
4109     starti;
4110     assert(T != Q, "invalid size");
4111     f(0b00000100, 31, 24), f(T, 23, 22), f(0b1, 21);
4112     sf(imm2, 20, 16), f(0b010000, 15, 10);
4113     sf(imm1, 9, 5), rf(Zd, 0);
4114   }
4115 
4116   // SVE programmable table lookup/permute using vector of element indices
4117   void sve_tbl(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, FloatRegister Zm) {
4118     starti;
4119     assert(T != Q, "invalid size");
4120     f(0b00000101, 31, 24), f(T, 23, 22), f(0b1, 21), rf(Zm, 16);
4121     f(0b001100, 15, 10), rf(Zn, 5), rf(Zd, 0);
4122   }
4123 
4124   // Shuffle active elements of vector to the right and fill with zero
4125   void sve_compact(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn, PRegister Pg) {
4126     starti;
4127     assert(T == S || T == D, "invalid size");
4128     f(0b00000101, 31, 24), f(T, 23, 22), f(0b100001100, 21, 13);
4129     pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
4130   }
4131 
4132   // SVE2 Count matching elements in vector
4133   void sve_histcnt(FloatRegister Zd, SIMD_RegVariant T, PRegister Pg,
4134                    FloatRegister Zn, FloatRegister Zm) {
4135     starti;
4136     assert(T == S || T == D, "invalid size");
4137     f(0b01000101, 31, 24), f(T, 23, 22), f(0b1, 21), rf(Zm, 16);
4138     f(0b110, 15, 13), pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);
4139   }
4140 
4141 // SVE2 bitwise permute
4142 #define INSN(NAME, opc)                                                                  \
4143   void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn,  FloatRegister Zm) {  \
4144     starti;                                                                              \
4145     assert(T != Q, "invalid size");                                                      \
4146     f(0b01000101, 31, 24), f(T, 23, 22), f(0b0, 21);                                     \
4147     rf(Zm, 16), f(0b1011, 15, 12), f(opc, 11, 10);                                       \
4148     rf(Zn, 5), rf(Zd, 0);                                                                \
4149   }
4150 
4151   INSN(sve_bext, 0b00);
4152   INSN(sve_bdep, 0b01);
4153 #undef INSN
4154 
4155 // SVE2 bitwise ternary operations
4156 #define INSN(NAME, opc)                                               \
4157   void NAME(FloatRegister Zdn, FloatRegister Zm, FloatRegister Zk) {  \
4158     starti;                                                           \
4159     f(0b00000100, 31, 24), f(opc, 23, 21), rf(Zm, 16);                \
4160     f(0b001110, 15, 10), rf(Zk, 5), rf(Zdn, 0);                       \
4161   }
4162 
4163   INSN(sve_eor3, 0b001); // Bitwise exclusive OR of three vectors
4164 #undef INSN
4165 
4166   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
4167   }
4168 
4169   // Stack overflow checking
4170   virtual void bang_stack_with_offset(int offset);
4171 
4172   static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
4173   static bool operand_valid_for_sve_logical_immediate(unsigned elembits, uint64_t imm);
4174   static bool operand_valid_for_add_sub_immediate(int64_t imm);
4175   static bool operand_valid_for_sve_add_sub_immediate(int64_t imm);
4176   static bool operand_valid_for_float_immediate(double imm);
4177   static int  operand_valid_for_movi_immediate(uint64_t imm64, SIMD_Arrangement T);
4178 
4179   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
4180   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
4181 };
4182 
4183 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
4184                                              Assembler::Membar_mask_bits b) {
4185   return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
4186 }
4187 
4188 Instruction_aarch64::~Instruction_aarch64() {
4189   assem->emit_int32(insn);
4190   assert_cond(get_bits() == 0xffffffff);
4191 }
4192 
4193 #undef f
4194 #undef sf
4195 #undef rf
4196 #undef srf
4197 #undef zrf
4198 #undef prf
4199 #undef pgrf
4200 #undef fixed
4201 
4202 #undef starti
4203 
4204 // Invert a condition
4205 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
4206   return Assembler::Condition(int(cond) ^ 1);
4207 }
4208 
4209 extern "C" void das(uint64_t start, int len);
4210 
4211 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP