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src/hotspot/cpu/aarch64/assembler_aarch64.hpp

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 778   void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
 779   void wrap_label(Label &L, prfop, prefetch_insn insn);
 780 
 781   // PC-rel. addressing
 782 
 783   void adr(Register Rd, address dest);
 784   void _adrp(Register Rd, address dest);
 785 
 786   void adr(Register Rd, const Address &dest);
 787   void _adrp(Register Rd, const Address &dest);
 788 
 789   void adr(Register Rd, Label &L) {
 790     wrap_label(Rd, L, &Assembler::Assembler::adr);
 791   }
 792   void _adrp(Register Rd, Label &L) {
 793     wrap_label(Rd, L, &Assembler::_adrp);
 794   }
 795 
 796   void adrp(Register Rd, const Address &dest, uint64_t &offset) = delete;
 797 


 798 #undef INSN
 799 
 800   void add_sub_immediate(Instruction_aarch64 &current_insn, Register Rd, Register Rn,
 801                          unsigned uimm, int op, int negated_op);
 802 
 803   // Add/subtract (immediate)
 804 #define INSN(NAME, decode, negated)                                     \
 805   void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
 806     starti;                                                             \
 807     f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
 808     zrf(Rd, 0), srf(Rn, 5);                                             \
 809   }                                                                     \
 810                                                                         \
 811   void NAME(Register Rd, Register Rn, unsigned imm) {                   \
 812     starti;                                                             \
 813     add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated);      \
 814   }
 815 
 816   INSN(addsw, 0b001, 0b011);
 817   INSN(subsw, 0b011, 0b001);

1555   }                                                     \
1556 
1557   INSN(str,  0b11, 0b00);
1558   INSN(strw, 0b10, 0b00);
1559   INSN(strb, 0b00, 0b00);
1560   INSN(strh, 0b01, 0b00);
1561 
1562   INSN(ldr,  0b11, 0b01);
1563   INSN(ldrw, 0b10, 0b01);
1564   INSN(ldrb, 0b00, 0b01);
1565   INSN(ldrh, 0b01, 0b01);
1566 
1567   INSN(ldrsb,  0b00, 0b10);
1568   INSN(ldrsbw, 0b00, 0b11);
1569   INSN(ldrsh,  0b01, 0b10);
1570   INSN(ldrshw, 0b01, 0b11);
1571   INSN(ldrsw,  0b10, 0b10);
1572 
1573 #undef INSN
1574 
1575 #define INSN(NAME, size, op)                                    \
1576   void NAME(const Address &adr, prfop pfop = PLDL1KEEP) {       \
1577     ld_st2(as_Register(pfop), adr, size, op);                   \
1578   }
1579 
1580   INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1581                           // writeback modes, but the assembler
1582                           // doesn't enfore that.
1583 
1584 #undef INSN
1585 
1586 #define INSN(NAME, size, op)                            \
1587   void NAME(FloatRegister Rt, const Address &adr) {     \
1588     ld_st2(as_Register(Rt), adr, size, op, 1);          \
1589   }
1590 
1591   INSN(strd, 0b11, 0b00);
1592   INSN(strs, 0b10, 0b00);
1593   INSN(ldrd, 0b11, 0b01);
1594   INSN(ldrs, 0b10, 0b01);
1595   INSN(strq, 0b00, 0b10);
1596   INSN(ldrq, 0x00, 0b11);
1597 
1598 #undef INSN
1599 
1600 /* SIMD extensions
1601  *
1602  * We just use FloatRegister in the following. They are exactly the same
1603  * as SIMD registers.
1604  */
1605 public:

 778   void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
 779   void wrap_label(Label &L, prfop, prefetch_insn insn);
 780 
 781   // PC-rel. addressing
 782 
 783   void adr(Register Rd, address dest);
 784   void _adrp(Register Rd, address dest);
 785 
 786   void adr(Register Rd, const Address &dest);
 787   void _adrp(Register Rd, const Address &dest);
 788 
 789   void adr(Register Rd, Label &L) {
 790     wrap_label(Rd, L, &Assembler::Assembler::adr);
 791   }
 792   void _adrp(Register Rd, Label &L) {
 793     wrap_label(Rd, L, &Assembler::_adrp);
 794   }
 795 
 796   void adrp(Register Rd, const Address &dest, uint64_t &offset) = delete;
 797 
 798   void prfm(const Address &adr, prfop pfop = PLDL1KEEP);
 799 
 800 #undef INSN
 801 
 802   void add_sub_immediate(Instruction_aarch64 &current_insn, Register Rd, Register Rn,
 803                          unsigned uimm, int op, int negated_op);
 804 
 805   // Add/subtract (immediate)
 806 #define INSN(NAME, decode, negated)                                     \
 807   void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
 808     starti;                                                             \
 809     f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
 810     zrf(Rd, 0), srf(Rn, 5);                                             \
 811   }                                                                     \
 812                                                                         \
 813   void NAME(Register Rd, Register Rn, unsigned imm) {                   \
 814     starti;                                                             \
 815     add_sub_immediate(current_insn, Rd, Rn, imm, decode, negated);      \
 816   }
 817 
 818   INSN(addsw, 0b001, 0b011);
 819   INSN(subsw, 0b011, 0b001);

1557   }                                                     \
1558 
1559   INSN(str,  0b11, 0b00);
1560   INSN(strw, 0b10, 0b00);
1561   INSN(strb, 0b00, 0b00);
1562   INSN(strh, 0b01, 0b00);
1563 
1564   INSN(ldr,  0b11, 0b01);
1565   INSN(ldrw, 0b10, 0b01);
1566   INSN(ldrb, 0b00, 0b01);
1567   INSN(ldrh, 0b01, 0b01);
1568 
1569   INSN(ldrsb,  0b00, 0b10);
1570   INSN(ldrsbw, 0b00, 0b11);
1571   INSN(ldrsh,  0b01, 0b10);
1572   INSN(ldrshw, 0b01, 0b11);
1573   INSN(ldrsw,  0b10, 0b10);
1574 
1575 #undef INSN
1576 











1577 #define INSN(NAME, size, op)                            \
1578   void NAME(FloatRegister Rt, const Address &adr) {     \
1579     ld_st2(as_Register(Rt), adr, size, op, 1);          \
1580   }
1581 
1582   INSN(strd, 0b11, 0b00);
1583   INSN(strs, 0b10, 0b00);
1584   INSN(ldrd, 0b11, 0b01);
1585   INSN(ldrs, 0b10, 0b01);
1586   INSN(strq, 0b00, 0b10);
1587   INSN(ldrq, 0x00, 0b11);
1588 
1589 #undef INSN
1590 
1591 /* SIMD extensions
1592  *
1593  * We just use FloatRegister in the following. They are exactly the same
1594  * as SIMD registers.
1595  */
1596 public:
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